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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/cmsis/TARGET_CORTEX_A/core_ca.h@3:f3764f852aa8, 2018-10-11 (annotated)
- Committer:
- kadonotakashi
- Date:
- Thu Oct 11 02:27:46 2018 +0000
- Revision:
- 3:f3764f852aa8
- Parent:
- 0:8fdf9a60065b
Nucreo 446 + SSD1331 test version;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
kadonotakashi | 0:8fdf9a60065b | 2 | * @file core_ca.h |
kadonotakashi | 0:8fdf9a60065b | 3 | * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File |
kadonotakashi | 0:8fdf9a60065b | 4 | * @version V1.0.1 |
kadonotakashi | 0:8fdf9a60065b | 5 | * @date 07. May 2018 |
kadonotakashi | 0:8fdf9a60065b | 6 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 7 | /* |
kadonotakashi | 0:8fdf9a60065b | 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 9 | * |
kadonotakashi | 0:8fdf9a60065b | 10 | * SPDX-License-Identifier: Apache-2.0 |
kadonotakashi | 0:8fdf9a60065b | 11 | * |
kadonotakashi | 0:8fdf9a60065b | 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
kadonotakashi | 0:8fdf9a60065b | 13 | * not use this file except in compliance with the License. |
kadonotakashi | 0:8fdf9a60065b | 14 | * You may obtain a copy of the License at |
kadonotakashi | 0:8fdf9a60065b | 15 | * |
kadonotakashi | 0:8fdf9a60065b | 16 | * www.apache.org/licenses/LICENSE-2.0 |
kadonotakashi | 0:8fdf9a60065b | 17 | * |
kadonotakashi | 0:8fdf9a60065b | 18 | * Unless required by applicable law or agreed to in writing, software |
kadonotakashi | 0:8fdf9a60065b | 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
kadonotakashi | 0:8fdf9a60065b | 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
kadonotakashi | 0:8fdf9a60065b | 21 | * See the License for the specific language governing permissions and |
kadonotakashi | 0:8fdf9a60065b | 22 | * limitations under the License. |
kadonotakashi | 0:8fdf9a60065b | 23 | */ |
kadonotakashi | 0:8fdf9a60065b | 24 | |
kadonotakashi | 0:8fdf9a60065b | 25 | #if defined ( __ICCARM__ ) |
kadonotakashi | 0:8fdf9a60065b | 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
kadonotakashi | 0:8fdf9a60065b | 27 | #elif defined (__clang__) |
kadonotakashi | 0:8fdf9a60065b | 28 | #pragma clang system_header /* treat file as system include file */ |
kadonotakashi | 0:8fdf9a60065b | 29 | #endif |
kadonotakashi | 0:8fdf9a60065b | 30 | |
kadonotakashi | 0:8fdf9a60065b | 31 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 32 | extern "C" { |
kadonotakashi | 0:8fdf9a60065b | 33 | #endif |
kadonotakashi | 0:8fdf9a60065b | 34 | |
kadonotakashi | 0:8fdf9a60065b | 35 | #ifndef __CORE_CA_H_GENERIC |
kadonotakashi | 0:8fdf9a60065b | 36 | #define __CORE_CA_H_GENERIC |
kadonotakashi | 0:8fdf9a60065b | 37 | |
kadonotakashi | 0:8fdf9a60065b | 38 | |
kadonotakashi | 0:8fdf9a60065b | 39 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 40 | * CMSIS definitions |
kadonotakashi | 0:8fdf9a60065b | 41 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 42 | |
kadonotakashi | 0:8fdf9a60065b | 43 | /* CMSIS CA definitions */ |
kadonotakashi | 0:8fdf9a60065b | 44 | #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ |
kadonotakashi | 0:8fdf9a60065b | 45 | #define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ |
kadonotakashi | 0:8fdf9a60065b | 46 | #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ |
kadonotakashi | 0:8fdf9a60065b | 47 | __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ |
kadonotakashi | 0:8fdf9a60065b | 48 | |
kadonotakashi | 0:8fdf9a60065b | 49 | #if defined ( __CC_ARM ) |
kadonotakashi | 0:8fdf9a60065b | 50 | #if defined __TARGET_FPU_VFP |
kadonotakashi | 0:8fdf9a60065b | 51 | #if (__FPU_PRESENT == 1) |
kadonotakashi | 0:8fdf9a60065b | 52 | #define __FPU_USED 1U |
kadonotakashi | 0:8fdf9a60065b | 53 | #else |
kadonotakashi | 0:8fdf9a60065b | 54 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 55 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 56 | #endif |
kadonotakashi | 0:8fdf9a60065b | 57 | #else |
kadonotakashi | 0:8fdf9a60065b | 58 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 59 | #endif |
kadonotakashi | 0:8fdf9a60065b | 60 | |
kadonotakashi | 0:8fdf9a60065b | 61 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
kadonotakashi | 0:8fdf9a60065b | 62 | #if defined __ARM_PCS_VFP |
kadonotakashi | 0:8fdf9a60065b | 63 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
kadonotakashi | 0:8fdf9a60065b | 64 | #define __FPU_USED 1U |
kadonotakashi | 0:8fdf9a60065b | 65 | #else |
kadonotakashi | 0:8fdf9a60065b | 66 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 67 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 68 | #endif |
kadonotakashi | 0:8fdf9a60065b | 69 | #else |
kadonotakashi | 0:8fdf9a60065b | 70 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 71 | #endif |
kadonotakashi | 0:8fdf9a60065b | 72 | |
kadonotakashi | 0:8fdf9a60065b | 73 | #elif defined ( __ICCARM__ ) |
kadonotakashi | 0:8fdf9a60065b | 74 | #if defined __ARMVFP__ |
kadonotakashi | 0:8fdf9a60065b | 75 | #if (__FPU_PRESENT == 1) |
kadonotakashi | 0:8fdf9a60065b | 76 | #define __FPU_USED 1U |
kadonotakashi | 0:8fdf9a60065b | 77 | #else |
kadonotakashi | 0:8fdf9a60065b | 78 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 79 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 80 | #endif |
kadonotakashi | 0:8fdf9a60065b | 81 | #else |
kadonotakashi | 0:8fdf9a60065b | 82 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 83 | #endif |
kadonotakashi | 0:8fdf9a60065b | 84 | |
kadonotakashi | 0:8fdf9a60065b | 85 | #elif defined ( __TMS470__ ) |
kadonotakashi | 0:8fdf9a60065b | 86 | #if defined __TI_VFP_SUPPORT__ |
kadonotakashi | 0:8fdf9a60065b | 87 | #if (__FPU_PRESENT == 1) |
kadonotakashi | 0:8fdf9a60065b | 88 | #define __FPU_USED 1U |
kadonotakashi | 0:8fdf9a60065b | 89 | #else |
kadonotakashi | 0:8fdf9a60065b | 90 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 91 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 92 | #endif |
kadonotakashi | 0:8fdf9a60065b | 93 | #else |
kadonotakashi | 0:8fdf9a60065b | 94 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 95 | #endif |
kadonotakashi | 0:8fdf9a60065b | 96 | |
kadonotakashi | 0:8fdf9a60065b | 97 | #elif defined ( __GNUC__ ) |
kadonotakashi | 0:8fdf9a60065b | 98 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
kadonotakashi | 0:8fdf9a60065b | 99 | #if (__FPU_PRESENT == 1) |
kadonotakashi | 0:8fdf9a60065b | 100 | #define __FPU_USED 1U |
kadonotakashi | 0:8fdf9a60065b | 101 | #else |
kadonotakashi | 0:8fdf9a60065b | 102 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 103 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 104 | #endif |
kadonotakashi | 0:8fdf9a60065b | 105 | #else |
kadonotakashi | 0:8fdf9a60065b | 106 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 107 | #endif |
kadonotakashi | 0:8fdf9a60065b | 108 | |
kadonotakashi | 0:8fdf9a60065b | 109 | #elif defined ( __TASKING__ ) |
kadonotakashi | 0:8fdf9a60065b | 110 | #if defined __FPU_VFP__ |
kadonotakashi | 0:8fdf9a60065b | 111 | #if (__FPU_PRESENT == 1) |
kadonotakashi | 0:8fdf9a60065b | 112 | #define __FPU_USED 1U |
kadonotakashi | 0:8fdf9a60065b | 113 | #else |
kadonotakashi | 0:8fdf9a60065b | 114 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 115 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 116 | #endif |
kadonotakashi | 0:8fdf9a60065b | 117 | #else |
kadonotakashi | 0:8fdf9a60065b | 118 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 119 | #endif |
kadonotakashi | 0:8fdf9a60065b | 120 | #endif |
kadonotakashi | 0:8fdf9a60065b | 121 | |
kadonotakashi | 0:8fdf9a60065b | 122 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
kadonotakashi | 0:8fdf9a60065b | 123 | |
kadonotakashi | 0:8fdf9a60065b | 124 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 125 | } |
kadonotakashi | 0:8fdf9a60065b | 126 | #endif |
kadonotakashi | 0:8fdf9a60065b | 127 | |
kadonotakashi | 0:8fdf9a60065b | 128 | #endif /* __CORE_CA_H_GENERIC */ |
kadonotakashi | 0:8fdf9a60065b | 129 | |
kadonotakashi | 0:8fdf9a60065b | 130 | #ifndef __CMSIS_GENERIC |
kadonotakashi | 0:8fdf9a60065b | 131 | |
kadonotakashi | 0:8fdf9a60065b | 132 | #ifndef __CORE_CA_H_DEPENDANT |
kadonotakashi | 0:8fdf9a60065b | 133 | #define __CORE_CA_H_DEPENDANT |
kadonotakashi | 0:8fdf9a60065b | 134 | |
kadonotakashi | 0:8fdf9a60065b | 135 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 136 | extern "C" { |
kadonotakashi | 0:8fdf9a60065b | 137 | #endif |
kadonotakashi | 0:8fdf9a60065b | 138 | |
kadonotakashi | 0:8fdf9a60065b | 139 | /* check device defines and use defaults */ |
kadonotakashi | 0:8fdf9a60065b | 140 | #if defined __CHECK_DEVICE_DEFINES |
kadonotakashi | 0:8fdf9a60065b | 141 | #ifndef __CA_REV |
kadonotakashi | 0:8fdf9a60065b | 142 | #define __CA_REV 0x0000U |
kadonotakashi | 0:8fdf9a60065b | 143 | #warning "__CA_REV not defined in device header file; using default!" |
kadonotakashi | 0:8fdf9a60065b | 144 | #endif |
kadonotakashi | 0:8fdf9a60065b | 145 | |
kadonotakashi | 0:8fdf9a60065b | 146 | #ifndef __FPU_PRESENT |
kadonotakashi | 0:8fdf9a60065b | 147 | #define __FPU_PRESENT 0U |
kadonotakashi | 0:8fdf9a60065b | 148 | #warning "__FPU_PRESENT not defined in device header file; using default!" |
kadonotakashi | 0:8fdf9a60065b | 149 | #endif |
kadonotakashi | 0:8fdf9a60065b | 150 | |
kadonotakashi | 0:8fdf9a60065b | 151 | #ifndef __GIC_PRESENT |
kadonotakashi | 0:8fdf9a60065b | 152 | #define __GIC_PRESENT 1U |
kadonotakashi | 0:8fdf9a60065b | 153 | #warning "__GIC_PRESENT not defined in device header file; using default!" |
kadonotakashi | 0:8fdf9a60065b | 154 | #endif |
kadonotakashi | 0:8fdf9a60065b | 155 | |
kadonotakashi | 0:8fdf9a60065b | 156 | #ifndef __TIM_PRESENT |
kadonotakashi | 0:8fdf9a60065b | 157 | #define __TIM_PRESENT 1U |
kadonotakashi | 0:8fdf9a60065b | 158 | #warning "__TIM_PRESENT not defined in device header file; using default!" |
kadonotakashi | 0:8fdf9a60065b | 159 | #endif |
kadonotakashi | 0:8fdf9a60065b | 160 | |
kadonotakashi | 0:8fdf9a60065b | 161 | #ifndef __L2C_PRESENT |
kadonotakashi | 0:8fdf9a60065b | 162 | #define __L2C_PRESENT 0U |
kadonotakashi | 0:8fdf9a60065b | 163 | #warning "__L2C_PRESENT not defined in device header file; using default!" |
kadonotakashi | 0:8fdf9a60065b | 164 | #endif |
kadonotakashi | 0:8fdf9a60065b | 165 | #endif |
kadonotakashi | 0:8fdf9a60065b | 166 | |
kadonotakashi | 0:8fdf9a60065b | 167 | /* IO definitions (access restrictions to peripheral registers) */ |
kadonotakashi | 0:8fdf9a60065b | 168 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 169 | #define __I volatile /*!< \brief Defines 'read only' permissions */ |
kadonotakashi | 0:8fdf9a60065b | 170 | #else |
kadonotakashi | 0:8fdf9a60065b | 171 | #define __I volatile const /*!< \brief Defines 'read only' permissions */ |
kadonotakashi | 0:8fdf9a60065b | 172 | #endif |
kadonotakashi | 0:8fdf9a60065b | 173 | #define __O volatile /*!< \brief Defines 'write only' permissions */ |
kadonotakashi | 0:8fdf9a60065b | 174 | #define __IO volatile /*!< \brief Defines 'read / write' permissions */ |
kadonotakashi | 0:8fdf9a60065b | 175 | |
kadonotakashi | 0:8fdf9a60065b | 176 | /* following defines should be used for structure members */ |
kadonotakashi | 0:8fdf9a60065b | 177 | #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ |
kadonotakashi | 0:8fdf9a60065b | 178 | #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ |
kadonotakashi | 0:8fdf9a60065b | 179 | #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ |
kadonotakashi | 0:8fdf9a60065b | 180 | #define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas |
kadonotakashi | 0:8fdf9a60065b | 181 | |
kadonotakashi | 0:8fdf9a60065b | 182 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 183 | * Register Abstraction |
kadonotakashi | 0:8fdf9a60065b | 184 | Core Register contain: |
kadonotakashi | 0:8fdf9a60065b | 185 | - CPSR |
kadonotakashi | 0:8fdf9a60065b | 186 | - CP15 Registers |
kadonotakashi | 0:8fdf9a60065b | 187 | - L2C-310 Cache Controller |
kadonotakashi | 0:8fdf9a60065b | 188 | - Generic Interrupt Controller Distributor |
kadonotakashi | 0:8fdf9a60065b | 189 | - Generic Interrupt Controller Interface |
kadonotakashi | 0:8fdf9a60065b | 190 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 191 | |
kadonotakashi | 0:8fdf9a60065b | 192 | /* Core Register CPSR */ |
kadonotakashi | 0:8fdf9a60065b | 193 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 194 | { |
kadonotakashi | 0:8fdf9a60065b | 195 | struct |
kadonotakashi | 0:8fdf9a60065b | 196 | { |
kadonotakashi | 0:8fdf9a60065b | 197 | uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ |
kadonotakashi | 0:8fdf9a60065b | 198 | uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ |
kadonotakashi | 0:8fdf9a60065b | 199 | uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ |
kadonotakashi | 0:8fdf9a60065b | 200 | uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ |
kadonotakashi | 0:8fdf9a60065b | 201 | uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ |
kadonotakashi | 0:8fdf9a60065b | 202 | uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ |
kadonotakashi | 0:8fdf9a60065b | 203 | uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ |
kadonotakashi | 0:8fdf9a60065b | 204 | uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ |
kadonotakashi | 0:8fdf9a60065b | 205 | RESERVED(0:4, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 206 | uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ |
kadonotakashi | 0:8fdf9a60065b | 207 | uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ |
kadonotakashi | 0:8fdf9a60065b | 208 | uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ |
kadonotakashi | 0:8fdf9a60065b | 209 | uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 210 | uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 211 | uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 212 | uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 213 | } b; /*!< \brief Structure used for bit access */ |
kadonotakashi | 0:8fdf9a60065b | 214 | uint32_t w; /*!< \brief Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 215 | } CPSR_Type; |
kadonotakashi | 0:8fdf9a60065b | 216 | |
kadonotakashi | 0:8fdf9a60065b | 217 | |
kadonotakashi | 0:8fdf9a60065b | 218 | |
kadonotakashi | 0:8fdf9a60065b | 219 | /* CPSR Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 220 | #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ |
kadonotakashi | 0:8fdf9a60065b | 221 | #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ |
kadonotakashi | 0:8fdf9a60065b | 222 | |
kadonotakashi | 0:8fdf9a60065b | 223 | #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ |
kadonotakashi | 0:8fdf9a60065b | 224 | #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ |
kadonotakashi | 0:8fdf9a60065b | 225 | |
kadonotakashi | 0:8fdf9a60065b | 226 | #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ |
kadonotakashi | 0:8fdf9a60065b | 227 | #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ |
kadonotakashi | 0:8fdf9a60065b | 228 | |
kadonotakashi | 0:8fdf9a60065b | 229 | #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ |
kadonotakashi | 0:8fdf9a60065b | 230 | #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ |
kadonotakashi | 0:8fdf9a60065b | 231 | |
kadonotakashi | 0:8fdf9a60065b | 232 | #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ |
kadonotakashi | 0:8fdf9a60065b | 233 | #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ |
kadonotakashi | 0:8fdf9a60065b | 234 | |
kadonotakashi | 0:8fdf9a60065b | 235 | #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 236 | #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 237 | |
kadonotakashi | 0:8fdf9a60065b | 238 | #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ |
kadonotakashi | 0:8fdf9a60065b | 239 | #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ |
kadonotakashi | 0:8fdf9a60065b | 240 | |
kadonotakashi | 0:8fdf9a60065b | 241 | #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ |
kadonotakashi | 0:8fdf9a60065b | 242 | #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 243 | |
kadonotakashi | 0:8fdf9a60065b | 244 | #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 245 | #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 246 | |
kadonotakashi | 0:8fdf9a60065b | 247 | #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ |
kadonotakashi | 0:8fdf9a60065b | 248 | #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ |
kadonotakashi | 0:8fdf9a60065b | 249 | |
kadonotakashi | 0:8fdf9a60065b | 250 | #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ |
kadonotakashi | 0:8fdf9a60065b | 251 | #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ |
kadonotakashi | 0:8fdf9a60065b | 252 | |
kadonotakashi | 0:8fdf9a60065b | 253 | #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ |
kadonotakashi | 0:8fdf9a60065b | 254 | #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ |
kadonotakashi | 0:8fdf9a60065b | 255 | |
kadonotakashi | 0:8fdf9a60065b | 256 | #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ |
kadonotakashi | 0:8fdf9a60065b | 257 | #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ |
kadonotakashi | 0:8fdf9a60065b | 258 | |
kadonotakashi | 0:8fdf9a60065b | 259 | #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ |
kadonotakashi | 0:8fdf9a60065b | 260 | #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ |
kadonotakashi | 0:8fdf9a60065b | 261 | |
kadonotakashi | 0:8fdf9a60065b | 262 | #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ |
kadonotakashi | 0:8fdf9a60065b | 263 | #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ |
kadonotakashi | 0:8fdf9a60065b | 264 | |
kadonotakashi | 0:8fdf9a60065b | 265 | #define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ |
kadonotakashi | 0:8fdf9a60065b | 266 | #define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ |
kadonotakashi | 0:8fdf9a60065b | 267 | #define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ |
kadonotakashi | 0:8fdf9a60065b | 268 | #define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ |
kadonotakashi | 0:8fdf9a60065b | 269 | #define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ |
kadonotakashi | 0:8fdf9a60065b | 270 | #define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ |
kadonotakashi | 0:8fdf9a60065b | 271 | #define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ |
kadonotakashi | 0:8fdf9a60065b | 272 | #define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ |
kadonotakashi | 0:8fdf9a60065b | 273 | #define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ |
kadonotakashi | 0:8fdf9a60065b | 274 | |
kadonotakashi | 0:8fdf9a60065b | 275 | /* CP15 Register SCTLR */ |
kadonotakashi | 0:8fdf9a60065b | 276 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 277 | { |
kadonotakashi | 0:8fdf9a60065b | 278 | struct |
kadonotakashi | 0:8fdf9a60065b | 279 | { |
kadonotakashi | 0:8fdf9a60065b | 280 | uint32_t M:1; /*!< \brief bit: 0 MMU enable */ |
kadonotakashi | 0:8fdf9a60065b | 281 | uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ |
kadonotakashi | 0:8fdf9a60065b | 282 | uint32_t C:1; /*!< \brief bit: 2 Cache enable */ |
kadonotakashi | 0:8fdf9a60065b | 283 | RESERVED(0:2, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 284 | uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ |
kadonotakashi | 0:8fdf9a60065b | 285 | RESERVED(1:1, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 286 | uint32_t B:1; /*!< \brief bit: 7 Endianness model */ |
kadonotakashi | 0:8fdf9a60065b | 287 | RESERVED(2:2, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 288 | uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ |
kadonotakashi | 0:8fdf9a60065b | 289 | uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ |
kadonotakashi | 0:8fdf9a60065b | 290 | uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ |
kadonotakashi | 0:8fdf9a60065b | 291 | uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ |
kadonotakashi | 0:8fdf9a60065b | 292 | uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ |
kadonotakashi | 0:8fdf9a60065b | 293 | RESERVED(3:2, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 294 | uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ |
kadonotakashi | 0:8fdf9a60065b | 295 | RESERVED(4:1, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 296 | uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ |
kadonotakashi | 0:8fdf9a60065b | 297 | uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ |
kadonotakashi | 0:8fdf9a60065b | 298 | uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ |
kadonotakashi | 0:8fdf9a60065b | 299 | uint32_t U:1; /*!< \brief bit: 22 Alignment model */ |
kadonotakashi | 0:8fdf9a60065b | 300 | RESERVED(5:1, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 301 | uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ |
kadonotakashi | 0:8fdf9a60065b | 302 | uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ |
kadonotakashi | 0:8fdf9a60065b | 303 | RESERVED(6:1, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 304 | uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ |
kadonotakashi | 0:8fdf9a60065b | 305 | uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ |
kadonotakashi | 0:8fdf9a60065b | 306 | uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ |
kadonotakashi | 0:8fdf9a60065b | 307 | uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ |
kadonotakashi | 0:8fdf9a60065b | 308 | RESERVED(7:1, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 309 | } b; /*!< \brief Structure used for bit access */ |
kadonotakashi | 0:8fdf9a60065b | 310 | uint32_t w; /*!< \brief Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 311 | } SCTLR_Type; |
kadonotakashi | 0:8fdf9a60065b | 312 | |
kadonotakashi | 0:8fdf9a60065b | 313 | #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ |
kadonotakashi | 0:8fdf9a60065b | 314 | #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 315 | |
kadonotakashi | 0:8fdf9a60065b | 316 | #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ |
kadonotakashi | 0:8fdf9a60065b | 317 | #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 318 | |
kadonotakashi | 0:8fdf9a60065b | 319 | #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ |
kadonotakashi | 0:8fdf9a60065b | 320 | #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 321 | |
kadonotakashi | 0:8fdf9a60065b | 322 | #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ |
kadonotakashi | 0:8fdf9a60065b | 323 | #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ |
kadonotakashi | 0:8fdf9a60065b | 324 | |
kadonotakashi | 0:8fdf9a60065b | 325 | #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ |
kadonotakashi | 0:8fdf9a60065b | 326 | #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 327 | |
kadonotakashi | 0:8fdf9a60065b | 328 | #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ |
kadonotakashi | 0:8fdf9a60065b | 329 | #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 330 | |
kadonotakashi | 0:8fdf9a60065b | 331 | #define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ |
kadonotakashi | 0:8fdf9a60065b | 332 | #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ |
kadonotakashi | 0:8fdf9a60065b | 333 | |
kadonotakashi | 0:8fdf9a60065b | 334 | #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ |
kadonotakashi | 0:8fdf9a60065b | 335 | #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ |
kadonotakashi | 0:8fdf9a60065b | 336 | |
kadonotakashi | 0:8fdf9a60065b | 337 | #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ |
kadonotakashi | 0:8fdf9a60065b | 338 | #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 339 | |
kadonotakashi | 0:8fdf9a60065b | 340 | #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ |
kadonotakashi | 0:8fdf9a60065b | 341 | #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 342 | |
kadonotakashi | 0:8fdf9a60065b | 343 | #define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ |
kadonotakashi | 0:8fdf9a60065b | 344 | #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ |
kadonotakashi | 0:8fdf9a60065b | 345 | |
kadonotakashi | 0:8fdf9a60065b | 346 | #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ |
kadonotakashi | 0:8fdf9a60065b | 347 | #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 348 | |
kadonotakashi | 0:8fdf9a60065b | 349 | #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ |
kadonotakashi | 0:8fdf9a60065b | 350 | #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ |
kadonotakashi | 0:8fdf9a60065b | 351 | |
kadonotakashi | 0:8fdf9a60065b | 352 | #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ |
kadonotakashi | 0:8fdf9a60065b | 353 | #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ |
kadonotakashi | 0:8fdf9a60065b | 354 | |
kadonotakashi | 0:8fdf9a60065b | 355 | #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ |
kadonotakashi | 0:8fdf9a60065b | 356 | #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ |
kadonotakashi | 0:8fdf9a60065b | 357 | |
kadonotakashi | 0:8fdf9a60065b | 358 | #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ |
kadonotakashi | 0:8fdf9a60065b | 359 | #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ |
kadonotakashi | 0:8fdf9a60065b | 360 | |
kadonotakashi | 0:8fdf9a60065b | 361 | #define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ |
kadonotakashi | 0:8fdf9a60065b | 362 | #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ |
kadonotakashi | 0:8fdf9a60065b | 363 | |
kadonotakashi | 0:8fdf9a60065b | 364 | #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 365 | #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 366 | |
kadonotakashi | 0:8fdf9a60065b | 367 | #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ |
kadonotakashi | 0:8fdf9a60065b | 368 | #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ |
kadonotakashi | 0:8fdf9a60065b | 369 | |
kadonotakashi | 0:8fdf9a60065b | 370 | #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ |
kadonotakashi | 0:8fdf9a60065b | 371 | #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ |
kadonotakashi | 0:8fdf9a60065b | 372 | |
kadonotakashi | 0:8fdf9a60065b | 373 | #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ |
kadonotakashi | 0:8fdf9a60065b | 374 | #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ |
kadonotakashi | 0:8fdf9a60065b | 375 | |
kadonotakashi | 0:8fdf9a60065b | 376 | /* CP15 Register ACTLR */ |
kadonotakashi | 0:8fdf9a60065b | 377 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 378 | { |
kadonotakashi | 0:8fdf9a60065b | 379 | #if __CORTEX_A == 5 || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 380 | /** \brief Structure used for bit access on Cortex-A5 */ |
kadonotakashi | 0:8fdf9a60065b | 381 | struct |
kadonotakashi | 0:8fdf9a60065b | 382 | { |
kadonotakashi | 0:8fdf9a60065b | 383 | uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ |
kadonotakashi | 0:8fdf9a60065b | 384 | RESERVED(0:5, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 385 | uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ |
kadonotakashi | 0:8fdf9a60065b | 386 | uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ |
kadonotakashi | 0:8fdf9a60065b | 387 | RESERVED(1:2, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 388 | uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ |
kadonotakashi | 0:8fdf9a60065b | 389 | uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ |
kadonotakashi | 0:8fdf9a60065b | 390 | uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ |
kadonotakashi | 0:8fdf9a60065b | 391 | uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ |
kadonotakashi | 0:8fdf9a60065b | 392 | uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ |
kadonotakashi | 0:8fdf9a60065b | 393 | uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ |
kadonotakashi | 0:8fdf9a60065b | 394 | uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ |
kadonotakashi | 0:8fdf9a60065b | 395 | RESERVED(3:9, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 396 | uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ |
kadonotakashi | 0:8fdf9a60065b | 397 | RESERVED(7:3, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 398 | } b; |
kadonotakashi | 0:8fdf9a60065b | 399 | #endif |
kadonotakashi | 0:8fdf9a60065b | 400 | #if __CORTEX_A == 7 || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 401 | /** \brief Structure used for bit access on Cortex-A7 */ |
kadonotakashi | 0:8fdf9a60065b | 402 | struct |
kadonotakashi | 0:8fdf9a60065b | 403 | { |
kadonotakashi | 0:8fdf9a60065b | 404 | RESERVED(0:6, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 405 | uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ |
kadonotakashi | 0:8fdf9a60065b | 406 | RESERVED(1:3, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 407 | uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ |
kadonotakashi | 0:8fdf9a60065b | 408 | uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ |
kadonotakashi | 0:8fdf9a60065b | 409 | uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ |
kadonotakashi | 0:8fdf9a60065b | 410 | uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ |
kadonotakashi | 0:8fdf9a60065b | 411 | uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ |
kadonotakashi | 0:8fdf9a60065b | 412 | RESERVED(3:12, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 413 | uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ |
kadonotakashi | 0:8fdf9a60065b | 414 | RESERVED(7:3, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 415 | } b; |
kadonotakashi | 0:8fdf9a60065b | 416 | #endif |
kadonotakashi | 0:8fdf9a60065b | 417 | #if __CORTEX_A == 9 || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 418 | /** \brief Structure used for bit access on Cortex-A9 */ |
kadonotakashi | 0:8fdf9a60065b | 419 | struct |
kadonotakashi | 0:8fdf9a60065b | 420 | { |
kadonotakashi | 0:8fdf9a60065b | 421 | uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ |
kadonotakashi | 0:8fdf9a60065b | 422 | RESERVED(0:1, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 423 | uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ |
kadonotakashi | 0:8fdf9a60065b | 424 | uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ |
kadonotakashi | 0:8fdf9a60065b | 425 | RESERVED(1:2, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 426 | uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ |
kadonotakashi | 0:8fdf9a60065b | 427 | uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ |
kadonotakashi | 0:8fdf9a60065b | 428 | uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ |
kadonotakashi | 0:8fdf9a60065b | 429 | uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ |
kadonotakashi | 0:8fdf9a60065b | 430 | RESERVED(7:22, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 431 | } b; |
kadonotakashi | 0:8fdf9a60065b | 432 | #endif |
kadonotakashi | 0:8fdf9a60065b | 433 | uint32_t w; /*!< \brief Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 434 | } ACTLR_Type; |
kadonotakashi | 0:8fdf9a60065b | 435 | |
kadonotakashi | 0:8fdf9a60065b | 436 | #define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ |
kadonotakashi | 0:8fdf9a60065b | 437 | #define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ |
kadonotakashi | 0:8fdf9a60065b | 438 | |
kadonotakashi | 0:8fdf9a60065b | 439 | #define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ |
kadonotakashi | 0:8fdf9a60065b | 440 | #define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ |
kadonotakashi | 0:8fdf9a60065b | 441 | |
kadonotakashi | 0:8fdf9a60065b | 442 | #define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ |
kadonotakashi | 0:8fdf9a60065b | 443 | #define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 444 | |
kadonotakashi | 0:8fdf9a60065b | 445 | #define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ |
kadonotakashi | 0:8fdf9a60065b | 446 | #define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 447 | |
kadonotakashi | 0:8fdf9a60065b | 448 | #define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ |
kadonotakashi | 0:8fdf9a60065b | 449 | #define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 450 | |
kadonotakashi | 0:8fdf9a60065b | 451 | #define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ |
kadonotakashi | 0:8fdf9a60065b | 452 | #define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ |
kadonotakashi | 0:8fdf9a60065b | 453 | |
kadonotakashi | 0:8fdf9a60065b | 454 | #define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ |
kadonotakashi | 0:8fdf9a60065b | 455 | #define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 456 | |
kadonotakashi | 0:8fdf9a60065b | 457 | #define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ |
kadonotakashi | 0:8fdf9a60065b | 458 | #define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 459 | |
kadonotakashi | 0:8fdf9a60065b | 460 | #define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ |
kadonotakashi | 0:8fdf9a60065b | 461 | #define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 462 | |
kadonotakashi | 0:8fdf9a60065b | 463 | #define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ |
kadonotakashi | 0:8fdf9a60065b | 464 | #define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ |
kadonotakashi | 0:8fdf9a60065b | 465 | |
kadonotakashi | 0:8fdf9a60065b | 466 | #define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ |
kadonotakashi | 0:8fdf9a60065b | 467 | #define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 468 | |
kadonotakashi | 0:8fdf9a60065b | 469 | #define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ |
kadonotakashi | 0:8fdf9a60065b | 470 | #define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 471 | |
kadonotakashi | 0:8fdf9a60065b | 472 | #define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ |
kadonotakashi | 0:8fdf9a60065b | 473 | #define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 474 | |
kadonotakashi | 0:8fdf9a60065b | 475 | #define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ |
kadonotakashi | 0:8fdf9a60065b | 476 | #define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ |
kadonotakashi | 0:8fdf9a60065b | 477 | |
kadonotakashi | 0:8fdf9a60065b | 478 | #define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ |
kadonotakashi | 0:8fdf9a60065b | 479 | #define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 480 | |
kadonotakashi | 0:8fdf9a60065b | 481 | #define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ |
kadonotakashi | 0:8fdf9a60065b | 482 | #define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 483 | |
kadonotakashi | 0:8fdf9a60065b | 484 | #define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ |
kadonotakashi | 0:8fdf9a60065b | 485 | #define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ |
kadonotakashi | 0:8fdf9a60065b | 486 | |
kadonotakashi | 0:8fdf9a60065b | 487 | #define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ |
kadonotakashi | 0:8fdf9a60065b | 488 | #define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 489 | |
kadonotakashi | 0:8fdf9a60065b | 490 | #define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ |
kadonotakashi | 0:8fdf9a60065b | 491 | #define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ |
kadonotakashi | 0:8fdf9a60065b | 492 | |
kadonotakashi | 0:8fdf9a60065b | 493 | /* CP15 Register CPACR */ |
kadonotakashi | 0:8fdf9a60065b | 494 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 495 | { |
kadonotakashi | 0:8fdf9a60065b | 496 | struct |
kadonotakashi | 0:8fdf9a60065b | 497 | { |
kadonotakashi | 0:8fdf9a60065b | 498 | uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ |
kadonotakashi | 0:8fdf9a60065b | 499 | uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ |
kadonotakashi | 0:8fdf9a60065b | 500 | uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ |
kadonotakashi | 0:8fdf9a60065b | 501 | uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ |
kadonotakashi | 0:8fdf9a60065b | 502 | uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ |
kadonotakashi | 0:8fdf9a60065b | 503 | uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ |
kadonotakashi | 0:8fdf9a60065b | 504 | uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ |
kadonotakashi | 0:8fdf9a60065b | 505 | uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ |
kadonotakashi | 0:8fdf9a60065b | 506 | uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ |
kadonotakashi | 0:8fdf9a60065b | 507 | uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ |
kadonotakashi | 0:8fdf9a60065b | 508 | uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ |
kadonotakashi | 0:8fdf9a60065b | 509 | uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ |
kadonotakashi | 0:8fdf9a60065b | 510 | uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ |
kadonotakashi | 0:8fdf9a60065b | 511 | uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ |
kadonotakashi | 0:8fdf9a60065b | 512 | uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ |
kadonotakashi | 0:8fdf9a60065b | 513 | RESERVED(0:1, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 514 | uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ |
kadonotakashi | 0:8fdf9a60065b | 515 | uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ |
kadonotakashi | 0:8fdf9a60065b | 516 | } b; /*!< \brief Structure used for bit access */ |
kadonotakashi | 0:8fdf9a60065b | 517 | uint32_t w; /*!< \brief Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 518 | } CPACR_Type; |
kadonotakashi | 0:8fdf9a60065b | 519 | |
kadonotakashi | 0:8fdf9a60065b | 520 | #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ |
kadonotakashi | 0:8fdf9a60065b | 521 | #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 522 | |
kadonotakashi | 0:8fdf9a60065b | 523 | #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ |
kadonotakashi | 0:8fdf9a60065b | 524 | #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 525 | |
kadonotakashi | 0:8fdf9a60065b | 526 | #define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ |
kadonotakashi | 0:8fdf9a60065b | 527 | #define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 528 | |
kadonotakashi | 0:8fdf9a60065b | 529 | #define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ |
kadonotakashi | 0:8fdf9a60065b | 530 | #define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ |
kadonotakashi | 0:8fdf9a60065b | 531 | |
kadonotakashi | 0:8fdf9a60065b | 532 | #define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ |
kadonotakashi | 0:8fdf9a60065b | 533 | #define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ |
kadonotakashi | 0:8fdf9a60065b | 534 | #define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ |
kadonotakashi | 0:8fdf9a60065b | 535 | |
kadonotakashi | 0:8fdf9a60065b | 536 | /* CP15 Register DFSR */ |
kadonotakashi | 0:8fdf9a60065b | 537 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 538 | { |
kadonotakashi | 0:8fdf9a60065b | 539 | struct |
kadonotakashi | 0:8fdf9a60065b | 540 | { |
kadonotakashi | 0:8fdf9a60065b | 541 | uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ |
kadonotakashi | 0:8fdf9a60065b | 542 | uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ |
kadonotakashi | 0:8fdf9a60065b | 543 | RESERVED(0:1, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 544 | uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ |
kadonotakashi | 0:8fdf9a60065b | 545 | uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ |
kadonotakashi | 0:8fdf9a60065b | 546 | uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ |
kadonotakashi | 0:8fdf9a60065b | 547 | uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ |
kadonotakashi | 0:8fdf9a60065b | 548 | uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ |
kadonotakashi | 0:8fdf9a60065b | 549 | RESERVED(1:18, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 550 | } s; /*!< \brief Structure used for bit access in short format */ |
kadonotakashi | 0:8fdf9a60065b | 551 | struct |
kadonotakashi | 0:8fdf9a60065b | 552 | { |
kadonotakashi | 0:8fdf9a60065b | 553 | uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ |
kadonotakashi | 0:8fdf9a60065b | 554 | RESERVED(0:3, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 555 | uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ |
kadonotakashi | 0:8fdf9a60065b | 556 | RESERVED(1:1, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 557 | uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ |
kadonotakashi | 0:8fdf9a60065b | 558 | uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ |
kadonotakashi | 0:8fdf9a60065b | 559 | uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ |
kadonotakashi | 0:8fdf9a60065b | 560 | RESERVED(2:18, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 561 | } l; /*!< \brief Structure used for bit access in long format */ |
kadonotakashi | 0:8fdf9a60065b | 562 | uint32_t w; /*!< \brief Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 563 | } DFSR_Type; |
kadonotakashi | 0:8fdf9a60065b | 564 | |
kadonotakashi | 0:8fdf9a60065b | 565 | #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ |
kadonotakashi | 0:8fdf9a60065b | 566 | #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ |
kadonotakashi | 0:8fdf9a60065b | 567 | |
kadonotakashi | 0:8fdf9a60065b | 568 | #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ |
kadonotakashi | 0:8fdf9a60065b | 569 | #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ |
kadonotakashi | 0:8fdf9a60065b | 570 | |
kadonotakashi | 0:8fdf9a60065b | 571 | #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ |
kadonotakashi | 0:8fdf9a60065b | 572 | #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 573 | |
kadonotakashi | 0:8fdf9a60065b | 574 | #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 575 | #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 576 | |
kadonotakashi | 0:8fdf9a60065b | 577 | #define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ |
kadonotakashi | 0:8fdf9a60065b | 578 | #define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 579 | |
kadonotakashi | 0:8fdf9a60065b | 580 | #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ |
kadonotakashi | 0:8fdf9a60065b | 581 | #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ |
kadonotakashi | 0:8fdf9a60065b | 582 | |
kadonotakashi | 0:8fdf9a60065b | 583 | #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 584 | #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 585 | |
kadonotakashi | 0:8fdf9a60065b | 586 | #define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ |
kadonotakashi | 0:8fdf9a60065b | 587 | #define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 588 | |
kadonotakashi | 0:8fdf9a60065b | 589 | /* CP15 Register IFSR */ |
kadonotakashi | 0:8fdf9a60065b | 590 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 591 | { |
kadonotakashi | 0:8fdf9a60065b | 592 | struct |
kadonotakashi | 0:8fdf9a60065b | 593 | { |
kadonotakashi | 0:8fdf9a60065b | 594 | uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ |
kadonotakashi | 0:8fdf9a60065b | 595 | RESERVED(0:5, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 596 | uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ |
kadonotakashi | 0:8fdf9a60065b | 597 | uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ |
kadonotakashi | 0:8fdf9a60065b | 598 | RESERVED(1:1, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 599 | uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ |
kadonotakashi | 0:8fdf9a60065b | 600 | RESERVED(2:19, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 601 | } s; /*!< \brief Structure used for bit access in short format */ |
kadonotakashi | 0:8fdf9a60065b | 602 | struct |
kadonotakashi | 0:8fdf9a60065b | 603 | { |
kadonotakashi | 0:8fdf9a60065b | 604 | uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ |
kadonotakashi | 0:8fdf9a60065b | 605 | RESERVED(0:3, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 606 | uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ |
kadonotakashi | 0:8fdf9a60065b | 607 | RESERVED(1:2, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 608 | uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ |
kadonotakashi | 0:8fdf9a60065b | 609 | RESERVED(2:19, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 610 | } l; /*!< \brief Structure used for bit access in long format */ |
kadonotakashi | 0:8fdf9a60065b | 611 | uint32_t w; /*!< \brief Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 612 | } IFSR_Type; |
kadonotakashi | 0:8fdf9a60065b | 613 | |
kadonotakashi | 0:8fdf9a60065b | 614 | #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ |
kadonotakashi | 0:8fdf9a60065b | 615 | #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 616 | |
kadonotakashi | 0:8fdf9a60065b | 617 | #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 618 | #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 619 | |
kadonotakashi | 0:8fdf9a60065b | 620 | #define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ |
kadonotakashi | 0:8fdf9a60065b | 621 | #define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 622 | |
kadonotakashi | 0:8fdf9a60065b | 623 | #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 624 | #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 625 | |
kadonotakashi | 0:8fdf9a60065b | 626 | #define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ |
kadonotakashi | 0:8fdf9a60065b | 627 | #define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 628 | |
kadonotakashi | 0:8fdf9a60065b | 629 | /* CP15 Register ISR */ |
kadonotakashi | 0:8fdf9a60065b | 630 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 631 | { |
kadonotakashi | 0:8fdf9a60065b | 632 | struct |
kadonotakashi | 0:8fdf9a60065b | 633 | { |
kadonotakashi | 0:8fdf9a60065b | 634 | RESERVED(0:6, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 635 | uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ |
kadonotakashi | 0:8fdf9a60065b | 636 | uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ |
kadonotakashi | 0:8fdf9a60065b | 637 | uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ |
kadonotakashi | 0:8fdf9a60065b | 638 | RESERVED(1:23, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 639 | } b; /*!< \brief Structure used for bit access */ |
kadonotakashi | 0:8fdf9a60065b | 640 | uint32_t w; /*!< \brief Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 641 | } ISR_Type; |
kadonotakashi | 0:8fdf9a60065b | 642 | |
kadonotakashi | 0:8fdf9a60065b | 643 | #define ISR_A_Pos 13U /*!< \brief ISR: A Position */ |
kadonotakashi | 0:8fdf9a60065b | 644 | #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ |
kadonotakashi | 0:8fdf9a60065b | 645 | |
kadonotakashi | 0:8fdf9a60065b | 646 | #define ISR_I_Pos 12U /*!< \brief ISR: I Position */ |
kadonotakashi | 0:8fdf9a60065b | 647 | #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ |
kadonotakashi | 0:8fdf9a60065b | 648 | |
kadonotakashi | 0:8fdf9a60065b | 649 | #define ISR_F_Pos 11U /*!< \brief ISR: F Position */ |
kadonotakashi | 0:8fdf9a60065b | 650 | #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ |
kadonotakashi | 0:8fdf9a60065b | 651 | |
kadonotakashi | 0:8fdf9a60065b | 652 | /* DACR Register */ |
kadonotakashi | 0:8fdf9a60065b | 653 | #define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ |
kadonotakashi | 0:8fdf9a60065b | 654 | #define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ |
kadonotakashi | 0:8fdf9a60065b | 655 | #define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ |
kadonotakashi | 0:8fdf9a60065b | 656 | #define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ |
kadonotakashi | 0:8fdf9a60065b | 657 | #define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ |
kadonotakashi | 0:8fdf9a60065b | 658 | |
kadonotakashi | 0:8fdf9a60065b | 659 | /** |
kadonotakashi | 0:8fdf9a60065b | 660 | \brief Mask and shift a bit field value for use in a register bit range. |
kadonotakashi | 0:8fdf9a60065b | 661 | \param [in] field Name of the register bit field. |
kadonotakashi | 0:8fdf9a60065b | 662 | \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
kadonotakashi | 0:8fdf9a60065b | 663 | \return Masked and shifted value. |
kadonotakashi | 0:8fdf9a60065b | 664 | */ |
kadonotakashi | 0:8fdf9a60065b | 665 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
kadonotakashi | 0:8fdf9a60065b | 666 | |
kadonotakashi | 0:8fdf9a60065b | 667 | /** |
kadonotakashi | 0:8fdf9a60065b | 668 | \brief Mask and shift a register value to extract a bit filed value. |
kadonotakashi | 0:8fdf9a60065b | 669 | \param [in] field Name of the register bit field. |
kadonotakashi | 0:8fdf9a60065b | 670 | \param [in] value Value of register. This parameter is interpreted as an uint32_t type. |
kadonotakashi | 0:8fdf9a60065b | 671 | \return Masked and shifted bit field value. |
kadonotakashi | 0:8fdf9a60065b | 672 | */ |
kadonotakashi | 0:8fdf9a60065b | 673 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
kadonotakashi | 0:8fdf9a60065b | 674 | |
kadonotakashi | 0:8fdf9a60065b | 675 | |
kadonotakashi | 0:8fdf9a60065b | 676 | /** |
kadonotakashi | 0:8fdf9a60065b | 677 | \brief Union type to access the L2C_310 Cache Controller. |
kadonotakashi | 0:8fdf9a60065b | 678 | */ |
kadonotakashi | 0:8fdf9a60065b | 679 | #if (__L2C_PRESENT == 1U) || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 680 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 681 | { |
kadonotakashi | 0:8fdf9a60065b | 682 | __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ |
kadonotakashi | 0:8fdf9a60065b | 683 | __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ |
kadonotakashi | 0:8fdf9a60065b | 684 | RESERVED(0[0x3e], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 685 | __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 686 | __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ |
kadonotakashi | 0:8fdf9a60065b | 687 | RESERVED(1[0x3e], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 688 | __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ |
kadonotakashi | 0:8fdf9a60065b | 689 | __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ |
kadonotakashi | 0:8fdf9a60065b | 690 | __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ |
kadonotakashi | 0:8fdf9a60065b | 691 | RESERVED(2[0x2], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 692 | __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ |
kadonotakashi | 0:8fdf9a60065b | 693 | __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ |
kadonotakashi | 0:8fdf9a60065b | 694 | __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ |
kadonotakashi | 0:8fdf9a60065b | 695 | __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ |
kadonotakashi | 0:8fdf9a60065b | 696 | RESERVED(3[0x143], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 697 | __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ |
kadonotakashi | 0:8fdf9a60065b | 698 | RESERVED(4[0xf], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 699 | __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ |
kadonotakashi | 0:8fdf9a60065b | 700 | RESERVED(6[2], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 701 | __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ |
kadonotakashi | 0:8fdf9a60065b | 702 | RESERVED(5[0xc], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 703 | __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ |
kadonotakashi | 0:8fdf9a60065b | 704 | RESERVED(7[1], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 705 | __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ |
kadonotakashi | 0:8fdf9a60065b | 706 | __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ |
kadonotakashi | 0:8fdf9a60065b | 707 | RESERVED(8[0xc], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 708 | __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ |
kadonotakashi | 0:8fdf9a60065b | 709 | RESERVED(9[1], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 710 | __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ |
kadonotakashi | 0:8fdf9a60065b | 711 | __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ |
kadonotakashi | 0:8fdf9a60065b | 712 | RESERVED(10[0x40], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 713 | __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 714 | __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 715 | __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 716 | __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 717 | __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 718 | __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 719 | __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 720 | __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 721 | __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 722 | __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 723 | __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 724 | __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 725 | __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 726 | __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 727 | __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 728 | __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ |
kadonotakashi | 0:8fdf9a60065b | 729 | RESERVED(11[0x4], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 730 | __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ |
kadonotakashi | 0:8fdf9a60065b | 731 | __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ |
kadonotakashi | 0:8fdf9a60065b | 732 | RESERVED(12[0xaa], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 733 | __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ |
kadonotakashi | 0:8fdf9a60065b | 734 | __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ |
kadonotakashi | 0:8fdf9a60065b | 735 | RESERVED(13[0xce], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 736 | __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 737 | } L2C_310_TypeDef; |
kadonotakashi | 0:8fdf9a60065b | 738 | |
kadonotakashi | 0:8fdf9a60065b | 739 | #define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ |
kadonotakashi | 0:8fdf9a60065b | 740 | #endif |
kadonotakashi | 0:8fdf9a60065b | 741 | |
kadonotakashi | 0:8fdf9a60065b | 742 | #if (__GIC_PRESENT == 1U) || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 743 | |
kadonotakashi | 0:8fdf9a60065b | 744 | /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) |
kadonotakashi | 0:8fdf9a60065b | 745 | */ |
kadonotakashi | 0:8fdf9a60065b | 746 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 747 | { |
kadonotakashi | 0:8fdf9a60065b | 748 | __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 749 | __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ |
kadonotakashi | 0:8fdf9a60065b | 750 | __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ |
kadonotakashi | 0:8fdf9a60065b | 751 | RESERVED(0, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 752 | __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ |
kadonotakashi | 0:8fdf9a60065b | 753 | RESERVED(1[11], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 754 | __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ |
kadonotakashi | 0:8fdf9a60065b | 755 | RESERVED(2, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 756 | __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ |
kadonotakashi | 0:8fdf9a60065b | 757 | RESERVED(3, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 758 | __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ |
kadonotakashi | 0:8fdf9a60065b | 759 | RESERVED(4, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 760 | __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ |
kadonotakashi | 0:8fdf9a60065b | 761 | RESERVED(5[9], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 762 | __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ |
kadonotakashi | 0:8fdf9a60065b | 763 | __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ |
kadonotakashi | 0:8fdf9a60065b | 764 | __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ |
kadonotakashi | 0:8fdf9a60065b | 765 | __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ |
kadonotakashi | 0:8fdf9a60065b | 766 | __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ |
kadonotakashi | 0:8fdf9a60065b | 767 | __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ |
kadonotakashi | 0:8fdf9a60065b | 768 | __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ |
kadonotakashi | 0:8fdf9a60065b | 769 | __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ |
kadonotakashi | 0:8fdf9a60065b | 770 | RESERVED(6, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 771 | __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ |
kadonotakashi | 0:8fdf9a60065b | 772 | RESERVED(7, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 773 | __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ |
kadonotakashi | 0:8fdf9a60065b | 774 | __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ |
kadonotakashi | 0:8fdf9a60065b | 775 | RESERVED(8[32], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 776 | __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ |
kadonotakashi | 0:8fdf9a60065b | 777 | __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ |
kadonotakashi | 0:8fdf9a60065b | 778 | RESERVED(9[3], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 779 | __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ |
kadonotakashi | 0:8fdf9a60065b | 780 | __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ |
kadonotakashi | 0:8fdf9a60065b | 781 | RESERVED(10[5236], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 782 | __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ |
kadonotakashi | 0:8fdf9a60065b | 783 | } GICDistributor_Type; |
kadonotakashi | 0:8fdf9a60065b | 784 | |
kadonotakashi | 0:8fdf9a60065b | 785 | #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ |
kadonotakashi | 0:8fdf9a60065b | 786 | |
kadonotakashi | 0:8fdf9a60065b | 787 | /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) |
kadonotakashi | 0:8fdf9a60065b | 788 | */ |
kadonotakashi | 0:8fdf9a60065b | 789 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 790 | { |
kadonotakashi | 0:8fdf9a60065b | 791 | __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 792 | __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ |
kadonotakashi | 0:8fdf9a60065b | 793 | __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ |
kadonotakashi | 0:8fdf9a60065b | 794 | __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ |
kadonotakashi | 0:8fdf9a60065b | 795 | __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ |
kadonotakashi | 0:8fdf9a60065b | 796 | __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ |
kadonotakashi | 0:8fdf9a60065b | 797 | __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ |
kadonotakashi | 0:8fdf9a60065b | 798 | __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ |
kadonotakashi | 0:8fdf9a60065b | 799 | __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ |
kadonotakashi | 0:8fdf9a60065b | 800 | __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ |
kadonotakashi | 0:8fdf9a60065b | 801 | __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ |
kadonotakashi | 0:8fdf9a60065b | 802 | __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ |
kadonotakashi | 0:8fdf9a60065b | 803 | RESERVED(1[40], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 804 | __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ |
kadonotakashi | 0:8fdf9a60065b | 805 | __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ |
kadonotakashi | 0:8fdf9a60065b | 806 | RESERVED(2[3], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 807 | __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ |
kadonotakashi | 0:8fdf9a60065b | 808 | RESERVED(3[960], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 809 | __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ |
kadonotakashi | 0:8fdf9a60065b | 810 | } GICInterface_Type; |
kadonotakashi | 0:8fdf9a60065b | 811 | |
kadonotakashi | 0:8fdf9a60065b | 812 | #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ |
kadonotakashi | 0:8fdf9a60065b | 813 | #endif |
kadonotakashi | 0:8fdf9a60065b | 814 | |
kadonotakashi | 0:8fdf9a60065b | 815 | #if (__TIM_PRESENT == 1U) || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 816 | #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 817 | /** \brief Structure type to access the Private Timer |
kadonotakashi | 0:8fdf9a60065b | 818 | */ |
kadonotakashi | 0:8fdf9a60065b | 819 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 820 | { |
kadonotakashi | 0:8fdf9a60065b | 821 | __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register |
kadonotakashi | 0:8fdf9a60065b | 822 | __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register |
kadonotakashi | 0:8fdf9a60065b | 823 | __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register |
kadonotakashi | 0:8fdf9a60065b | 824 | __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register |
kadonotakashi | 0:8fdf9a60065b | 825 | RESERVED(0[4], uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 826 | __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register |
kadonotakashi | 0:8fdf9a60065b | 827 | __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register |
kadonotakashi | 0:8fdf9a60065b | 828 | __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register |
kadonotakashi | 0:8fdf9a60065b | 829 | __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register |
kadonotakashi | 0:8fdf9a60065b | 830 | __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register |
kadonotakashi | 0:8fdf9a60065b | 831 | __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register |
kadonotakashi | 0:8fdf9a60065b | 832 | } Timer_Type; |
kadonotakashi | 0:8fdf9a60065b | 833 | #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ |
kadonotakashi | 0:8fdf9a60065b | 834 | #endif |
kadonotakashi | 0:8fdf9a60065b | 835 | #endif |
kadonotakashi | 0:8fdf9a60065b | 836 | |
kadonotakashi | 0:8fdf9a60065b | 837 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 838 | * Hardware Abstraction Layer |
kadonotakashi | 0:8fdf9a60065b | 839 | Core Function Interface contains: |
kadonotakashi | 0:8fdf9a60065b | 840 | - L1 Cache Functions |
kadonotakashi | 0:8fdf9a60065b | 841 | - L2C-310 Cache Controller Functions |
kadonotakashi | 0:8fdf9a60065b | 842 | - PL1 Timer Functions |
kadonotakashi | 0:8fdf9a60065b | 843 | - GIC Functions |
kadonotakashi | 0:8fdf9a60065b | 844 | - MMU Functions |
kadonotakashi | 0:8fdf9a60065b | 845 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 846 | |
kadonotakashi | 0:8fdf9a60065b | 847 | /* ########################## L1 Cache functions ################################# */ |
kadonotakashi | 0:8fdf9a60065b | 848 | |
kadonotakashi | 0:8fdf9a60065b | 849 | /** \brief Enable Caches by setting I and C bits in SCTLR register. |
kadonotakashi | 0:8fdf9a60065b | 850 | */ |
kadonotakashi | 0:8fdf9a60065b | 851 | __STATIC_FORCEINLINE void L1C_EnableCaches(void) { |
kadonotakashi | 0:8fdf9a60065b | 852 | __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); |
kadonotakashi | 0:8fdf9a60065b | 853 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 854 | } |
kadonotakashi | 0:8fdf9a60065b | 855 | |
kadonotakashi | 0:8fdf9a60065b | 856 | /** \brief Disable Caches by clearing I and C bits in SCTLR register. |
kadonotakashi | 0:8fdf9a60065b | 857 | */ |
kadonotakashi | 0:8fdf9a60065b | 858 | __STATIC_FORCEINLINE void L1C_DisableCaches(void) { |
kadonotakashi | 0:8fdf9a60065b | 859 | __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); |
kadonotakashi | 0:8fdf9a60065b | 860 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 861 | } |
kadonotakashi | 0:8fdf9a60065b | 862 | |
kadonotakashi | 0:8fdf9a60065b | 863 | /** \brief Enable Branch Prediction by setting Z bit in SCTLR register. |
kadonotakashi | 0:8fdf9a60065b | 864 | */ |
kadonotakashi | 0:8fdf9a60065b | 865 | __STATIC_FORCEINLINE void L1C_EnableBTAC(void) { |
kadonotakashi | 0:8fdf9a60065b | 866 | __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); |
kadonotakashi | 0:8fdf9a60065b | 867 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 868 | } |
kadonotakashi | 0:8fdf9a60065b | 869 | |
kadonotakashi | 0:8fdf9a60065b | 870 | /** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. |
kadonotakashi | 0:8fdf9a60065b | 871 | */ |
kadonotakashi | 0:8fdf9a60065b | 872 | __STATIC_FORCEINLINE void L1C_DisableBTAC(void) { |
kadonotakashi | 0:8fdf9a60065b | 873 | __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); |
kadonotakashi | 0:8fdf9a60065b | 874 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 875 | } |
kadonotakashi | 0:8fdf9a60065b | 876 | |
kadonotakashi | 0:8fdf9a60065b | 877 | /** \brief Invalidate entire branch predictor array |
kadonotakashi | 0:8fdf9a60065b | 878 | */ |
kadonotakashi | 0:8fdf9a60065b | 879 | __STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { |
kadonotakashi | 0:8fdf9a60065b | 880 | __set_BPIALL(0); |
kadonotakashi | 0:8fdf9a60065b | 881 | __DSB(); //ensure completion of the invalidation |
kadonotakashi | 0:8fdf9a60065b | 882 | __ISB(); //ensure instruction fetch path sees new state |
kadonotakashi | 0:8fdf9a60065b | 883 | } |
kadonotakashi | 0:8fdf9a60065b | 884 | |
kadonotakashi | 0:8fdf9a60065b | 885 | /** \brief Invalidate the whole instruction cache |
kadonotakashi | 0:8fdf9a60065b | 886 | */ |
kadonotakashi | 0:8fdf9a60065b | 887 | __STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { |
kadonotakashi | 0:8fdf9a60065b | 888 | __set_ICIALLU(0); |
kadonotakashi | 0:8fdf9a60065b | 889 | __DSB(); //ensure completion of the invalidation |
kadonotakashi | 0:8fdf9a60065b | 890 | __ISB(); //ensure instruction fetch path sees new I cache state |
kadonotakashi | 0:8fdf9a60065b | 891 | } |
kadonotakashi | 0:8fdf9a60065b | 892 | |
kadonotakashi | 0:8fdf9a60065b | 893 | /** \brief Clean data cache line by address. |
kadonotakashi | 0:8fdf9a60065b | 894 | * \param [in] va Pointer to data to clear the cache for. |
kadonotakashi | 0:8fdf9a60065b | 895 | */ |
kadonotakashi | 0:8fdf9a60065b | 896 | __STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { |
kadonotakashi | 0:8fdf9a60065b | 897 | __set_DCCMVAC((uint32_t)va); |
kadonotakashi | 0:8fdf9a60065b | 898 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
kadonotakashi | 0:8fdf9a60065b | 899 | } |
kadonotakashi | 0:8fdf9a60065b | 900 | |
kadonotakashi | 0:8fdf9a60065b | 901 | /** \brief Invalidate data cache line by address. |
kadonotakashi | 0:8fdf9a60065b | 902 | * \param [in] va Pointer to data to invalidate the cache for. |
kadonotakashi | 0:8fdf9a60065b | 903 | */ |
kadonotakashi | 0:8fdf9a60065b | 904 | __STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { |
kadonotakashi | 0:8fdf9a60065b | 905 | __set_DCIMVAC((uint32_t)va); |
kadonotakashi | 0:8fdf9a60065b | 906 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
kadonotakashi | 0:8fdf9a60065b | 907 | } |
kadonotakashi | 0:8fdf9a60065b | 908 | |
kadonotakashi | 0:8fdf9a60065b | 909 | /** \brief Clean and Invalidate data cache by address. |
kadonotakashi | 0:8fdf9a60065b | 910 | * \param [in] va Pointer to data to invalidate the cache for. |
kadonotakashi | 0:8fdf9a60065b | 911 | */ |
kadonotakashi | 0:8fdf9a60065b | 912 | __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { |
kadonotakashi | 0:8fdf9a60065b | 913 | __set_DCCIMVAC((uint32_t)va); |
kadonotakashi | 0:8fdf9a60065b | 914 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
kadonotakashi | 0:8fdf9a60065b | 915 | } |
kadonotakashi | 0:8fdf9a60065b | 916 | |
kadonotakashi | 0:8fdf9a60065b | 917 | /** \brief Calculate log2 rounded up |
kadonotakashi | 0:8fdf9a60065b | 918 | * - log(0) => 0 |
kadonotakashi | 0:8fdf9a60065b | 919 | * - log(1) => 0 |
kadonotakashi | 0:8fdf9a60065b | 920 | * - log(2) => 1 |
kadonotakashi | 0:8fdf9a60065b | 921 | * - log(3) => 2 |
kadonotakashi | 0:8fdf9a60065b | 922 | * - log(4) => 2 |
kadonotakashi | 0:8fdf9a60065b | 923 | * - log(5) => 3 |
kadonotakashi | 0:8fdf9a60065b | 924 | * : : |
kadonotakashi | 0:8fdf9a60065b | 925 | * - log(16) => 4 |
kadonotakashi | 0:8fdf9a60065b | 926 | * - log(32) => 5 |
kadonotakashi | 0:8fdf9a60065b | 927 | * : : |
kadonotakashi | 0:8fdf9a60065b | 928 | * \param [in] n input value parameter |
kadonotakashi | 0:8fdf9a60065b | 929 | * \return log2(n) |
kadonotakashi | 0:8fdf9a60065b | 930 | */ |
kadonotakashi | 0:8fdf9a60065b | 931 | __STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) |
kadonotakashi | 0:8fdf9a60065b | 932 | { |
kadonotakashi | 0:8fdf9a60065b | 933 | if (n < 2U) { |
kadonotakashi | 0:8fdf9a60065b | 934 | return 0U; |
kadonotakashi | 0:8fdf9a60065b | 935 | } |
kadonotakashi | 0:8fdf9a60065b | 936 | uint8_t log = 0U; |
kadonotakashi | 0:8fdf9a60065b | 937 | uint32_t t = n; |
kadonotakashi | 0:8fdf9a60065b | 938 | while(t > 1U) |
kadonotakashi | 0:8fdf9a60065b | 939 | { |
kadonotakashi | 0:8fdf9a60065b | 940 | log++; |
kadonotakashi | 0:8fdf9a60065b | 941 | t >>= 1U; |
kadonotakashi | 0:8fdf9a60065b | 942 | } |
kadonotakashi | 0:8fdf9a60065b | 943 | if (n & 1U) { log++; } |
kadonotakashi | 0:8fdf9a60065b | 944 | return log; |
kadonotakashi | 0:8fdf9a60065b | 945 | } |
kadonotakashi | 0:8fdf9a60065b | 946 | |
kadonotakashi | 0:8fdf9a60065b | 947 | /** \brief Apply cache maintenance to given cache level. |
kadonotakashi | 0:8fdf9a60065b | 948 | * \param [in] level cache level to be maintained |
kadonotakashi | 0:8fdf9a60065b | 949 | * \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean |
kadonotakashi | 0:8fdf9a60065b | 950 | */ |
kadonotakashi | 0:8fdf9a60065b | 951 | __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) |
kadonotakashi | 0:8fdf9a60065b | 952 | { |
kadonotakashi | 0:8fdf9a60065b | 953 | uint32_t Dummy; |
kadonotakashi | 0:8fdf9a60065b | 954 | uint32_t ccsidr; |
kadonotakashi | 0:8fdf9a60065b | 955 | uint32_t num_sets; |
kadonotakashi | 0:8fdf9a60065b | 956 | uint32_t num_ways; |
kadonotakashi | 0:8fdf9a60065b | 957 | uint32_t shift_way; |
kadonotakashi | 0:8fdf9a60065b | 958 | uint32_t log2_linesize; |
kadonotakashi | 0:8fdf9a60065b | 959 | int32_t log2_num_ways; |
kadonotakashi | 0:8fdf9a60065b | 960 | |
kadonotakashi | 0:8fdf9a60065b | 961 | Dummy = level << 1U; |
kadonotakashi | 0:8fdf9a60065b | 962 | /* set csselr, select ccsidr register */ |
kadonotakashi | 0:8fdf9a60065b | 963 | __set_CSSELR(Dummy); |
kadonotakashi | 0:8fdf9a60065b | 964 | /* get current ccsidr register */ |
kadonotakashi | 0:8fdf9a60065b | 965 | ccsidr = __get_CCSIDR(); |
kadonotakashi | 0:8fdf9a60065b | 966 | num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; |
kadonotakashi | 0:8fdf9a60065b | 967 | num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; |
kadonotakashi | 0:8fdf9a60065b | 968 | log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; |
kadonotakashi | 0:8fdf9a60065b | 969 | log2_num_ways = __log2_up(num_ways); |
kadonotakashi | 0:8fdf9a60065b | 970 | if ((log2_num_ways < 0) || (log2_num_ways > 32)) { |
kadonotakashi | 0:8fdf9a60065b | 971 | return; // FATAL ERROR |
kadonotakashi | 0:8fdf9a60065b | 972 | } |
kadonotakashi | 0:8fdf9a60065b | 973 | shift_way = 32U - (uint32_t)log2_num_ways; |
kadonotakashi | 0:8fdf9a60065b | 974 | for(int32_t way = num_ways-1; way >= 0; way--) |
kadonotakashi | 0:8fdf9a60065b | 975 | { |
kadonotakashi | 0:8fdf9a60065b | 976 | for(int32_t set = num_sets-1; set >= 0; set--) |
kadonotakashi | 0:8fdf9a60065b | 977 | { |
kadonotakashi | 0:8fdf9a60065b | 978 | Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); |
kadonotakashi | 0:8fdf9a60065b | 979 | switch (maint) |
kadonotakashi | 0:8fdf9a60065b | 980 | { |
kadonotakashi | 0:8fdf9a60065b | 981 | case 0U: __set_DCISW(Dummy); break; |
kadonotakashi | 0:8fdf9a60065b | 982 | case 1U: __set_DCCSW(Dummy); break; |
kadonotakashi | 0:8fdf9a60065b | 983 | default: __set_DCCISW(Dummy); break; |
kadonotakashi | 0:8fdf9a60065b | 984 | } |
kadonotakashi | 0:8fdf9a60065b | 985 | } |
kadonotakashi | 0:8fdf9a60065b | 986 | } |
kadonotakashi | 0:8fdf9a60065b | 987 | __DMB(); |
kadonotakashi | 0:8fdf9a60065b | 988 | } |
kadonotakashi | 0:8fdf9a60065b | 989 | |
kadonotakashi | 0:8fdf9a60065b | 990 | /** \brief Clean and Invalidate the entire data or unified cache |
kadonotakashi | 0:8fdf9a60065b | 991 | * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency |
kadonotakashi | 0:8fdf9a60065b | 992 | * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean |
kadonotakashi | 0:8fdf9a60065b | 993 | */ |
kadonotakashi | 0:8fdf9a60065b | 994 | __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { |
kadonotakashi | 0:8fdf9a60065b | 995 | uint32_t clidr; |
kadonotakashi | 0:8fdf9a60065b | 996 | uint32_t cache_type; |
kadonotakashi | 0:8fdf9a60065b | 997 | clidr = __get_CLIDR(); |
kadonotakashi | 0:8fdf9a60065b | 998 | for(uint32_t i = 0U; i<7U; i++) |
kadonotakashi | 0:8fdf9a60065b | 999 | { |
kadonotakashi | 0:8fdf9a60065b | 1000 | cache_type = (clidr >> i*3U) & 0x7UL; |
kadonotakashi | 0:8fdf9a60065b | 1001 | if ((cache_type >= 2U) && (cache_type <= 4U)) |
kadonotakashi | 0:8fdf9a60065b | 1002 | { |
kadonotakashi | 0:8fdf9a60065b | 1003 | __L1C_MaintainDCacheSetWay(i, op); |
kadonotakashi | 0:8fdf9a60065b | 1004 | } |
kadonotakashi | 0:8fdf9a60065b | 1005 | } |
kadonotakashi | 0:8fdf9a60065b | 1006 | } |
kadonotakashi | 0:8fdf9a60065b | 1007 | |
kadonotakashi | 0:8fdf9a60065b | 1008 | /** \brief Clean and Invalidate the entire data or unified cache |
kadonotakashi | 0:8fdf9a60065b | 1009 | * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency |
kadonotakashi | 0:8fdf9a60065b | 1010 | * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean |
kadonotakashi | 0:8fdf9a60065b | 1011 | * \deprecated Use generic L1C_CleanInvalidateCache instead. |
kadonotakashi | 0:8fdf9a60065b | 1012 | */ |
kadonotakashi | 0:8fdf9a60065b | 1013 | CMSIS_DEPRECATED |
kadonotakashi | 0:8fdf9a60065b | 1014 | __STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { |
kadonotakashi | 0:8fdf9a60065b | 1015 | L1C_CleanInvalidateCache(op); |
kadonotakashi | 0:8fdf9a60065b | 1016 | } |
kadonotakashi | 0:8fdf9a60065b | 1017 | |
kadonotakashi | 0:8fdf9a60065b | 1018 | /** \brief Invalidate the whole data cache. |
kadonotakashi | 0:8fdf9a60065b | 1019 | */ |
kadonotakashi | 0:8fdf9a60065b | 1020 | __STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { |
kadonotakashi | 0:8fdf9a60065b | 1021 | L1C_CleanInvalidateCache(0); |
kadonotakashi | 0:8fdf9a60065b | 1022 | } |
kadonotakashi | 0:8fdf9a60065b | 1023 | |
kadonotakashi | 0:8fdf9a60065b | 1024 | /** \brief Clean the whole data cache. |
kadonotakashi | 0:8fdf9a60065b | 1025 | */ |
kadonotakashi | 0:8fdf9a60065b | 1026 | __STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { |
kadonotakashi | 0:8fdf9a60065b | 1027 | L1C_CleanInvalidateCache(1); |
kadonotakashi | 0:8fdf9a60065b | 1028 | } |
kadonotakashi | 0:8fdf9a60065b | 1029 | |
kadonotakashi | 0:8fdf9a60065b | 1030 | /** \brief Clean and invalidate the whole data cache. |
kadonotakashi | 0:8fdf9a60065b | 1031 | */ |
kadonotakashi | 0:8fdf9a60065b | 1032 | __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { |
kadonotakashi | 0:8fdf9a60065b | 1033 | L1C_CleanInvalidateCache(2); |
kadonotakashi | 0:8fdf9a60065b | 1034 | } |
kadonotakashi | 0:8fdf9a60065b | 1035 | |
kadonotakashi | 0:8fdf9a60065b | 1036 | /* ########################## L2 Cache functions ################################# */ |
kadonotakashi | 0:8fdf9a60065b | 1037 | #if (__L2C_PRESENT == 1U) || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 1038 | /** \brief Cache Sync operation by writing CACHE_SYNC register. |
kadonotakashi | 0:8fdf9a60065b | 1039 | */ |
kadonotakashi | 0:8fdf9a60065b | 1040 | __STATIC_INLINE void L2C_Sync(void) |
kadonotakashi | 0:8fdf9a60065b | 1041 | { |
kadonotakashi | 0:8fdf9a60065b | 1042 | L2C_310->CACHE_SYNC = 0x0; |
kadonotakashi | 0:8fdf9a60065b | 1043 | } |
kadonotakashi | 0:8fdf9a60065b | 1044 | |
kadonotakashi | 0:8fdf9a60065b | 1045 | /** \brief Read cache controller cache ID from CACHE_ID register. |
kadonotakashi | 0:8fdf9a60065b | 1046 | * \return L2C_310_TypeDef::CACHE_ID |
kadonotakashi | 0:8fdf9a60065b | 1047 | */ |
kadonotakashi | 0:8fdf9a60065b | 1048 | __STATIC_INLINE int L2C_GetID (void) |
kadonotakashi | 0:8fdf9a60065b | 1049 | { |
kadonotakashi | 0:8fdf9a60065b | 1050 | return L2C_310->CACHE_ID; |
kadonotakashi | 0:8fdf9a60065b | 1051 | } |
kadonotakashi | 0:8fdf9a60065b | 1052 | |
kadonotakashi | 0:8fdf9a60065b | 1053 | /** \brief Read cache controller cache type from CACHE_TYPE register. |
kadonotakashi | 0:8fdf9a60065b | 1054 | * \return L2C_310_TypeDef::CACHE_TYPE |
kadonotakashi | 0:8fdf9a60065b | 1055 | */ |
kadonotakashi | 0:8fdf9a60065b | 1056 | __STATIC_INLINE int L2C_GetType (void) |
kadonotakashi | 0:8fdf9a60065b | 1057 | { |
kadonotakashi | 0:8fdf9a60065b | 1058 | return L2C_310->CACHE_TYPE; |
kadonotakashi | 0:8fdf9a60065b | 1059 | } |
kadonotakashi | 0:8fdf9a60065b | 1060 | |
kadonotakashi | 0:8fdf9a60065b | 1061 | /** \brief Invalidate all cache by way |
kadonotakashi | 0:8fdf9a60065b | 1062 | */ |
kadonotakashi | 0:8fdf9a60065b | 1063 | __STATIC_INLINE void L2C_InvAllByWay (void) |
kadonotakashi | 0:8fdf9a60065b | 1064 | { |
kadonotakashi | 0:8fdf9a60065b | 1065 | unsigned int assoc; |
kadonotakashi | 0:8fdf9a60065b | 1066 | |
kadonotakashi | 0:8fdf9a60065b | 1067 | if (L2C_310->AUX_CNT & (1U << 16U)) { |
kadonotakashi | 0:8fdf9a60065b | 1068 | assoc = 16U; |
kadonotakashi | 0:8fdf9a60065b | 1069 | } else { |
kadonotakashi | 0:8fdf9a60065b | 1070 | assoc = 8U; |
kadonotakashi | 0:8fdf9a60065b | 1071 | } |
kadonotakashi | 0:8fdf9a60065b | 1072 | |
kadonotakashi | 0:8fdf9a60065b | 1073 | L2C_310->INV_WAY = (1U << assoc) - 1U; |
kadonotakashi | 0:8fdf9a60065b | 1074 | while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate |
kadonotakashi | 0:8fdf9a60065b | 1075 | |
kadonotakashi | 0:8fdf9a60065b | 1076 | L2C_Sync(); |
kadonotakashi | 0:8fdf9a60065b | 1077 | } |
kadonotakashi | 0:8fdf9a60065b | 1078 | |
kadonotakashi | 0:8fdf9a60065b | 1079 | /** \brief Clean and Invalidate all cache by way |
kadonotakashi | 0:8fdf9a60065b | 1080 | */ |
kadonotakashi | 0:8fdf9a60065b | 1081 | __STATIC_INLINE void L2C_CleanInvAllByWay (void) |
kadonotakashi | 0:8fdf9a60065b | 1082 | { |
kadonotakashi | 0:8fdf9a60065b | 1083 | unsigned int assoc; |
kadonotakashi | 0:8fdf9a60065b | 1084 | |
kadonotakashi | 0:8fdf9a60065b | 1085 | if (L2C_310->AUX_CNT & (1U << 16U)) { |
kadonotakashi | 0:8fdf9a60065b | 1086 | assoc = 16U; |
kadonotakashi | 0:8fdf9a60065b | 1087 | } else { |
kadonotakashi | 0:8fdf9a60065b | 1088 | assoc = 8U; |
kadonotakashi | 0:8fdf9a60065b | 1089 | } |
kadonotakashi | 0:8fdf9a60065b | 1090 | |
kadonotakashi | 0:8fdf9a60065b | 1091 | L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; |
kadonotakashi | 0:8fdf9a60065b | 1092 | while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate |
kadonotakashi | 0:8fdf9a60065b | 1093 | |
kadonotakashi | 0:8fdf9a60065b | 1094 | L2C_Sync(); |
kadonotakashi | 0:8fdf9a60065b | 1095 | } |
kadonotakashi | 0:8fdf9a60065b | 1096 | |
kadonotakashi | 0:8fdf9a60065b | 1097 | /** \brief Enable Level 2 Cache |
kadonotakashi | 0:8fdf9a60065b | 1098 | */ |
kadonotakashi | 0:8fdf9a60065b | 1099 | __STATIC_INLINE void L2C_Enable(void) |
kadonotakashi | 0:8fdf9a60065b | 1100 | { |
kadonotakashi | 0:8fdf9a60065b | 1101 | L2C_310->CONTROL = 0; |
kadonotakashi | 0:8fdf9a60065b | 1102 | L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; |
kadonotakashi | 0:8fdf9a60065b | 1103 | L2C_310->DEBUG_CONTROL = 0; |
kadonotakashi | 0:8fdf9a60065b | 1104 | L2C_310->DATA_LOCK_0_WAY = 0; |
kadonotakashi | 0:8fdf9a60065b | 1105 | L2C_310->CACHE_SYNC = 0; |
kadonotakashi | 0:8fdf9a60065b | 1106 | L2C_310->CONTROL = 0x01; |
kadonotakashi | 0:8fdf9a60065b | 1107 | L2C_Sync(); |
kadonotakashi | 0:8fdf9a60065b | 1108 | } |
kadonotakashi | 0:8fdf9a60065b | 1109 | |
kadonotakashi | 0:8fdf9a60065b | 1110 | /** \brief Disable Level 2 Cache |
kadonotakashi | 0:8fdf9a60065b | 1111 | */ |
kadonotakashi | 0:8fdf9a60065b | 1112 | __STATIC_INLINE void L2C_Disable(void) |
kadonotakashi | 0:8fdf9a60065b | 1113 | { |
kadonotakashi | 0:8fdf9a60065b | 1114 | L2C_310->CONTROL = 0x00; |
kadonotakashi | 0:8fdf9a60065b | 1115 | L2C_Sync(); |
kadonotakashi | 0:8fdf9a60065b | 1116 | } |
kadonotakashi | 0:8fdf9a60065b | 1117 | |
kadonotakashi | 0:8fdf9a60065b | 1118 | /** \brief Invalidate cache by physical address |
kadonotakashi | 0:8fdf9a60065b | 1119 | * \param [in] pa Pointer to data to invalidate cache for. |
kadonotakashi | 0:8fdf9a60065b | 1120 | */ |
kadonotakashi | 0:8fdf9a60065b | 1121 | __STATIC_INLINE void L2C_InvPa (void *pa) |
kadonotakashi | 0:8fdf9a60065b | 1122 | { |
kadonotakashi | 0:8fdf9a60065b | 1123 | L2C_310->INV_LINE_PA = (unsigned int)pa; |
kadonotakashi | 0:8fdf9a60065b | 1124 | L2C_Sync(); |
kadonotakashi | 0:8fdf9a60065b | 1125 | } |
kadonotakashi | 0:8fdf9a60065b | 1126 | |
kadonotakashi | 0:8fdf9a60065b | 1127 | /** \brief Clean cache by physical address |
kadonotakashi | 0:8fdf9a60065b | 1128 | * \param [in] pa Pointer to data to invalidate cache for. |
kadonotakashi | 0:8fdf9a60065b | 1129 | */ |
kadonotakashi | 0:8fdf9a60065b | 1130 | __STATIC_INLINE void L2C_CleanPa (void *pa) |
kadonotakashi | 0:8fdf9a60065b | 1131 | { |
kadonotakashi | 0:8fdf9a60065b | 1132 | L2C_310->CLEAN_LINE_PA = (unsigned int)pa; |
kadonotakashi | 0:8fdf9a60065b | 1133 | L2C_Sync(); |
kadonotakashi | 0:8fdf9a60065b | 1134 | } |
kadonotakashi | 0:8fdf9a60065b | 1135 | |
kadonotakashi | 0:8fdf9a60065b | 1136 | /** \brief Clean and invalidate cache by physical address |
kadonotakashi | 0:8fdf9a60065b | 1137 | * \param [in] pa Pointer to data to invalidate cache for. |
kadonotakashi | 0:8fdf9a60065b | 1138 | */ |
kadonotakashi | 0:8fdf9a60065b | 1139 | __STATIC_INLINE void L2C_CleanInvPa (void *pa) |
kadonotakashi | 0:8fdf9a60065b | 1140 | { |
kadonotakashi | 0:8fdf9a60065b | 1141 | L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; |
kadonotakashi | 0:8fdf9a60065b | 1142 | L2C_Sync(); |
kadonotakashi | 0:8fdf9a60065b | 1143 | } |
kadonotakashi | 0:8fdf9a60065b | 1144 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1145 | |
kadonotakashi | 0:8fdf9a60065b | 1146 | /* ########################## GIC functions ###################################### */ |
kadonotakashi | 0:8fdf9a60065b | 1147 | #if (__GIC_PRESENT == 1U) || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 1148 | |
kadonotakashi | 0:8fdf9a60065b | 1149 | /** \brief Enable the interrupt distributor using the GIC's CTLR register. |
kadonotakashi | 0:8fdf9a60065b | 1150 | */ |
kadonotakashi | 0:8fdf9a60065b | 1151 | __STATIC_INLINE void GIC_EnableDistributor(void) |
kadonotakashi | 0:8fdf9a60065b | 1152 | { |
kadonotakashi | 0:8fdf9a60065b | 1153 | GICDistributor->CTLR |= 1U; |
kadonotakashi | 0:8fdf9a60065b | 1154 | } |
kadonotakashi | 0:8fdf9a60065b | 1155 | |
kadonotakashi | 0:8fdf9a60065b | 1156 | /** \brief Disable the interrupt distributor using the GIC's CTLR register. |
kadonotakashi | 0:8fdf9a60065b | 1157 | */ |
kadonotakashi | 0:8fdf9a60065b | 1158 | __STATIC_INLINE void GIC_DisableDistributor(void) |
kadonotakashi | 0:8fdf9a60065b | 1159 | { |
kadonotakashi | 0:8fdf9a60065b | 1160 | GICDistributor->CTLR &=~1U; |
kadonotakashi | 0:8fdf9a60065b | 1161 | } |
kadonotakashi | 0:8fdf9a60065b | 1162 | |
kadonotakashi | 0:8fdf9a60065b | 1163 | /** \brief Read the GIC's TYPER register. |
kadonotakashi | 0:8fdf9a60065b | 1164 | * \return GICDistributor_Type::TYPER |
kadonotakashi | 0:8fdf9a60065b | 1165 | */ |
kadonotakashi | 0:8fdf9a60065b | 1166 | __STATIC_INLINE uint32_t GIC_DistributorInfo(void) |
kadonotakashi | 0:8fdf9a60065b | 1167 | { |
kadonotakashi | 0:8fdf9a60065b | 1168 | return (GICDistributor->TYPER); |
kadonotakashi | 0:8fdf9a60065b | 1169 | } |
kadonotakashi | 0:8fdf9a60065b | 1170 | |
kadonotakashi | 0:8fdf9a60065b | 1171 | /** \brief Reads the GIC's IIDR register. |
kadonotakashi | 0:8fdf9a60065b | 1172 | * \return GICDistributor_Type::IIDR |
kadonotakashi | 0:8fdf9a60065b | 1173 | */ |
kadonotakashi | 0:8fdf9a60065b | 1174 | __STATIC_INLINE uint32_t GIC_DistributorImplementer(void) |
kadonotakashi | 0:8fdf9a60065b | 1175 | { |
kadonotakashi | 0:8fdf9a60065b | 1176 | return (GICDistributor->IIDR); |
kadonotakashi | 0:8fdf9a60065b | 1177 | } |
kadonotakashi | 0:8fdf9a60065b | 1178 | |
kadonotakashi | 0:8fdf9a60065b | 1179 | /** \brief Sets the GIC's ITARGETSR register for the given interrupt. |
kadonotakashi | 0:8fdf9a60065b | 1180 | * \param [in] IRQn Interrupt to be configured. |
kadonotakashi | 0:8fdf9a60065b | 1181 | * \param [in] cpu_target CPU interfaces to assign this interrupt to. |
kadonotakashi | 0:8fdf9a60065b | 1182 | */ |
kadonotakashi | 0:8fdf9a60065b | 1183 | __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) |
kadonotakashi | 0:8fdf9a60065b | 1184 | { |
kadonotakashi | 0:8fdf9a60065b | 1185 | uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); |
kadonotakashi | 0:8fdf9a60065b | 1186 | GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); |
kadonotakashi | 0:8fdf9a60065b | 1187 | } |
kadonotakashi | 0:8fdf9a60065b | 1188 | |
kadonotakashi | 0:8fdf9a60065b | 1189 | /** \brief Read the GIC's ITARGETSR register. |
kadonotakashi | 0:8fdf9a60065b | 1190 | * \param [in] IRQn Interrupt to acquire the configuration for. |
kadonotakashi | 0:8fdf9a60065b | 1191 | * \return GICDistributor_Type::ITARGETSR |
kadonotakashi | 0:8fdf9a60065b | 1192 | */ |
kadonotakashi | 0:8fdf9a60065b | 1193 | __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1194 | { |
kadonotakashi | 0:8fdf9a60065b | 1195 | return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; |
kadonotakashi | 0:8fdf9a60065b | 1196 | } |
kadonotakashi | 0:8fdf9a60065b | 1197 | |
kadonotakashi | 0:8fdf9a60065b | 1198 | /** \brief Enable the CPU's interrupt interface. |
kadonotakashi | 0:8fdf9a60065b | 1199 | */ |
kadonotakashi | 0:8fdf9a60065b | 1200 | __STATIC_INLINE void GIC_EnableInterface(void) |
kadonotakashi | 0:8fdf9a60065b | 1201 | { |
kadonotakashi | 0:8fdf9a60065b | 1202 | GICInterface->CTLR |= 1U; //enable interface |
kadonotakashi | 0:8fdf9a60065b | 1203 | } |
kadonotakashi | 0:8fdf9a60065b | 1204 | |
kadonotakashi | 0:8fdf9a60065b | 1205 | /** \brief Disable the CPU's interrupt interface. |
kadonotakashi | 0:8fdf9a60065b | 1206 | */ |
kadonotakashi | 0:8fdf9a60065b | 1207 | __STATIC_INLINE void GIC_DisableInterface(void) |
kadonotakashi | 0:8fdf9a60065b | 1208 | { |
kadonotakashi | 0:8fdf9a60065b | 1209 | GICInterface->CTLR &=~1U; //disable distributor |
kadonotakashi | 0:8fdf9a60065b | 1210 | } |
kadonotakashi | 0:8fdf9a60065b | 1211 | |
kadonotakashi | 0:8fdf9a60065b | 1212 | /** \brief Read the CPU's IAR register. |
kadonotakashi | 0:8fdf9a60065b | 1213 | * \return GICInterface_Type::IAR |
kadonotakashi | 0:8fdf9a60065b | 1214 | */ |
kadonotakashi | 0:8fdf9a60065b | 1215 | __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) |
kadonotakashi | 0:8fdf9a60065b | 1216 | { |
kadonotakashi | 0:8fdf9a60065b | 1217 | return (IRQn_Type)(GICInterface->IAR); |
kadonotakashi | 0:8fdf9a60065b | 1218 | } |
kadonotakashi | 0:8fdf9a60065b | 1219 | |
kadonotakashi | 0:8fdf9a60065b | 1220 | /** \brief Writes the given interrupt number to the CPU's EOIR register. |
kadonotakashi | 0:8fdf9a60065b | 1221 | * \param [in] IRQn The interrupt to be signaled as finished. |
kadonotakashi | 0:8fdf9a60065b | 1222 | */ |
kadonotakashi | 0:8fdf9a60065b | 1223 | __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1224 | { |
kadonotakashi | 0:8fdf9a60065b | 1225 | GICInterface->EOIR = IRQn; |
kadonotakashi | 0:8fdf9a60065b | 1226 | } |
kadonotakashi | 0:8fdf9a60065b | 1227 | |
kadonotakashi | 0:8fdf9a60065b | 1228 | /** \brief Enables the given interrupt using GIC's ISENABLER register. |
kadonotakashi | 0:8fdf9a60065b | 1229 | * \param [in] IRQn The interrupt to be enabled. |
kadonotakashi | 0:8fdf9a60065b | 1230 | */ |
kadonotakashi | 0:8fdf9a60065b | 1231 | __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1232 | { |
kadonotakashi | 0:8fdf9a60065b | 1233 | GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); |
kadonotakashi | 0:8fdf9a60065b | 1234 | } |
kadonotakashi | 0:8fdf9a60065b | 1235 | |
kadonotakashi | 0:8fdf9a60065b | 1236 | /** \brief Get interrupt enable status using GIC's ISENABLER register. |
kadonotakashi | 0:8fdf9a60065b | 1237 | * \param [in] IRQn The interrupt to be queried. |
kadonotakashi | 0:8fdf9a60065b | 1238 | * \return 0 - interrupt is not enabled, 1 - interrupt is enabled. |
kadonotakashi | 0:8fdf9a60065b | 1239 | */ |
kadonotakashi | 0:8fdf9a60065b | 1240 | __STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1241 | { |
kadonotakashi | 0:8fdf9a60065b | 1242 | return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; |
kadonotakashi | 0:8fdf9a60065b | 1243 | } |
kadonotakashi | 0:8fdf9a60065b | 1244 | |
kadonotakashi | 0:8fdf9a60065b | 1245 | /** \brief Disables the given interrupt using GIC's ICENABLER register. |
kadonotakashi | 0:8fdf9a60065b | 1246 | * \param [in] IRQn The interrupt to be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1247 | */ |
kadonotakashi | 0:8fdf9a60065b | 1248 | __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1249 | { |
kadonotakashi | 0:8fdf9a60065b | 1250 | GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); |
kadonotakashi | 0:8fdf9a60065b | 1251 | } |
kadonotakashi | 0:8fdf9a60065b | 1252 | |
kadonotakashi | 0:8fdf9a60065b | 1253 | /** \brief Get interrupt pending status from GIC's ISPENDR register. |
kadonotakashi | 0:8fdf9a60065b | 1254 | * \param [in] IRQn The interrupt to be queried. |
kadonotakashi | 0:8fdf9a60065b | 1255 | * \return 0 - interrupt is not pending, 1 - interrupt is pendig. |
kadonotakashi | 0:8fdf9a60065b | 1256 | */ |
kadonotakashi | 0:8fdf9a60065b | 1257 | __STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1258 | { |
kadonotakashi | 0:8fdf9a60065b | 1259 | uint32_t pend; |
kadonotakashi | 0:8fdf9a60065b | 1260 | |
kadonotakashi | 0:8fdf9a60065b | 1261 | if (IRQn >= 16U) { |
kadonotakashi | 0:8fdf9a60065b | 1262 | pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; |
kadonotakashi | 0:8fdf9a60065b | 1263 | } else { |
kadonotakashi | 0:8fdf9a60065b | 1264 | // INTID 0-15 Software Generated Interrupt |
kadonotakashi | 0:8fdf9a60065b | 1265 | pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; |
kadonotakashi | 0:8fdf9a60065b | 1266 | // No CPU identification offered |
kadonotakashi | 0:8fdf9a60065b | 1267 | if (pend != 0U) { |
kadonotakashi | 0:8fdf9a60065b | 1268 | pend = 1U; |
kadonotakashi | 0:8fdf9a60065b | 1269 | } else { |
kadonotakashi | 0:8fdf9a60065b | 1270 | pend = 0U; |
kadonotakashi | 0:8fdf9a60065b | 1271 | } |
kadonotakashi | 0:8fdf9a60065b | 1272 | } |
kadonotakashi | 0:8fdf9a60065b | 1273 | |
kadonotakashi | 0:8fdf9a60065b | 1274 | return (pend); |
kadonotakashi | 0:8fdf9a60065b | 1275 | } |
kadonotakashi | 0:8fdf9a60065b | 1276 | |
kadonotakashi | 0:8fdf9a60065b | 1277 | /** \brief Sets the given interrupt as pending using GIC's ISPENDR register. |
kadonotakashi | 0:8fdf9a60065b | 1278 | * \param [in] IRQn The interrupt to be enabled. |
kadonotakashi | 0:8fdf9a60065b | 1279 | */ |
kadonotakashi | 0:8fdf9a60065b | 1280 | __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1281 | { |
kadonotakashi | 0:8fdf9a60065b | 1282 | if (IRQn >= 16U) { |
kadonotakashi | 0:8fdf9a60065b | 1283 | GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); |
kadonotakashi | 0:8fdf9a60065b | 1284 | } else { |
kadonotakashi | 0:8fdf9a60065b | 1285 | // INTID 0-15 Software Generated Interrupt |
kadonotakashi | 0:8fdf9a60065b | 1286 | GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); |
kadonotakashi | 0:8fdf9a60065b | 1287 | } |
kadonotakashi | 0:8fdf9a60065b | 1288 | } |
kadonotakashi | 0:8fdf9a60065b | 1289 | |
kadonotakashi | 0:8fdf9a60065b | 1290 | /** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. |
kadonotakashi | 0:8fdf9a60065b | 1291 | * \param [in] IRQn The interrupt to be enabled. |
kadonotakashi | 0:8fdf9a60065b | 1292 | */ |
kadonotakashi | 0:8fdf9a60065b | 1293 | __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1294 | { |
kadonotakashi | 0:8fdf9a60065b | 1295 | if (IRQn >= 16U) { |
kadonotakashi | 0:8fdf9a60065b | 1296 | GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); |
kadonotakashi | 0:8fdf9a60065b | 1297 | } else { |
kadonotakashi | 0:8fdf9a60065b | 1298 | // INTID 0-15 Software Generated Interrupt |
kadonotakashi | 0:8fdf9a60065b | 1299 | GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); |
kadonotakashi | 0:8fdf9a60065b | 1300 | } |
kadonotakashi | 0:8fdf9a60065b | 1301 | } |
kadonotakashi | 0:8fdf9a60065b | 1302 | |
kadonotakashi | 0:8fdf9a60065b | 1303 | /** \brief Sets the interrupt configuration using GIC's ICFGR register. |
kadonotakashi | 0:8fdf9a60065b | 1304 | * \param [in] IRQn The interrupt to be configured. |
kadonotakashi | 0:8fdf9a60065b | 1305 | * \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) |
kadonotakashi | 0:8fdf9a60065b | 1306 | * Bit 1: 0 - level sensitive, 1 - edge triggered |
kadonotakashi | 0:8fdf9a60065b | 1307 | */ |
kadonotakashi | 0:8fdf9a60065b | 1308 | __STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) |
kadonotakashi | 0:8fdf9a60065b | 1309 | { |
kadonotakashi | 0:8fdf9a60065b | 1310 | uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; |
kadonotakashi | 0:8fdf9a60065b | 1311 | uint32_t shift = (IRQn % 16U) << 1U; |
kadonotakashi | 0:8fdf9a60065b | 1312 | |
kadonotakashi | 0:8fdf9a60065b | 1313 | icfgr &= (~(3U << shift)); |
kadonotakashi | 0:8fdf9a60065b | 1314 | icfgr |= ( int_config << shift); |
kadonotakashi | 0:8fdf9a60065b | 1315 | |
kadonotakashi | 0:8fdf9a60065b | 1316 | GICDistributor->ICFGR[IRQn / 16U] = icfgr; |
kadonotakashi | 0:8fdf9a60065b | 1317 | } |
kadonotakashi | 0:8fdf9a60065b | 1318 | |
kadonotakashi | 0:8fdf9a60065b | 1319 | /** \brief Get the interrupt configuration from the GIC's ICFGR register. |
kadonotakashi | 0:8fdf9a60065b | 1320 | * \param [in] IRQn Interrupt to acquire the configuration for. |
kadonotakashi | 0:8fdf9a60065b | 1321 | * \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) |
kadonotakashi | 0:8fdf9a60065b | 1322 | * Bit 1: 0 - level sensitive, 1 - edge triggered |
kadonotakashi | 0:8fdf9a60065b | 1323 | */ |
kadonotakashi | 0:8fdf9a60065b | 1324 | __STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1325 | { |
kadonotakashi | 0:8fdf9a60065b | 1326 | return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); |
kadonotakashi | 0:8fdf9a60065b | 1327 | } |
kadonotakashi | 0:8fdf9a60065b | 1328 | |
kadonotakashi | 0:8fdf9a60065b | 1329 | /** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. |
kadonotakashi | 0:8fdf9a60065b | 1330 | * \param [in] IRQn The interrupt to be configured. |
kadonotakashi | 0:8fdf9a60065b | 1331 | * \param [in] priority The priority for the interrupt, lower values denote higher priorities. |
kadonotakashi | 0:8fdf9a60065b | 1332 | */ |
kadonotakashi | 0:8fdf9a60065b | 1333 | __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
kadonotakashi | 0:8fdf9a60065b | 1334 | { |
kadonotakashi | 0:8fdf9a60065b | 1335 | uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); |
kadonotakashi | 0:8fdf9a60065b | 1336 | GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); |
kadonotakashi | 0:8fdf9a60065b | 1337 | } |
kadonotakashi | 0:8fdf9a60065b | 1338 | |
kadonotakashi | 0:8fdf9a60065b | 1339 | /** \brief Read the current interrupt priority from GIC's IPRIORITYR register. |
kadonotakashi | 0:8fdf9a60065b | 1340 | * \param [in] IRQn The interrupt to be queried. |
kadonotakashi | 0:8fdf9a60065b | 1341 | */ |
kadonotakashi | 0:8fdf9a60065b | 1342 | __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1343 | { |
kadonotakashi | 0:8fdf9a60065b | 1344 | return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; |
kadonotakashi | 0:8fdf9a60065b | 1345 | } |
kadonotakashi | 0:8fdf9a60065b | 1346 | |
kadonotakashi | 0:8fdf9a60065b | 1347 | /** \brief Set the interrupt priority mask using CPU's PMR register. |
kadonotakashi | 0:8fdf9a60065b | 1348 | * \param [in] priority Priority mask to be set. |
kadonotakashi | 0:8fdf9a60065b | 1349 | */ |
kadonotakashi | 0:8fdf9a60065b | 1350 | __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) |
kadonotakashi | 0:8fdf9a60065b | 1351 | { |
kadonotakashi | 0:8fdf9a60065b | 1352 | GICInterface->PMR = priority & 0xFFUL; //set priority mask |
kadonotakashi | 0:8fdf9a60065b | 1353 | } |
kadonotakashi | 0:8fdf9a60065b | 1354 | |
kadonotakashi | 0:8fdf9a60065b | 1355 | /** \brief Read the current interrupt priority mask from CPU's PMR register. |
kadonotakashi | 0:8fdf9a60065b | 1356 | * \result GICInterface_Type::PMR |
kadonotakashi | 0:8fdf9a60065b | 1357 | */ |
kadonotakashi | 0:8fdf9a60065b | 1358 | __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) |
kadonotakashi | 0:8fdf9a60065b | 1359 | { |
kadonotakashi | 0:8fdf9a60065b | 1360 | return GICInterface->PMR; |
kadonotakashi | 0:8fdf9a60065b | 1361 | } |
kadonotakashi | 0:8fdf9a60065b | 1362 | |
kadonotakashi | 0:8fdf9a60065b | 1363 | /** \brief Configures the group priority and subpriority split point using CPU's BPR register. |
kadonotakashi | 0:8fdf9a60065b | 1364 | * \param [in] binary_point Amount of bits used as subpriority. |
kadonotakashi | 0:8fdf9a60065b | 1365 | */ |
kadonotakashi | 0:8fdf9a60065b | 1366 | __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) |
kadonotakashi | 0:8fdf9a60065b | 1367 | { |
kadonotakashi | 0:8fdf9a60065b | 1368 | GICInterface->BPR = binary_point & 7U; //set binary point |
kadonotakashi | 0:8fdf9a60065b | 1369 | } |
kadonotakashi | 0:8fdf9a60065b | 1370 | |
kadonotakashi | 0:8fdf9a60065b | 1371 | /** \brief Read the current group priority and subpriority split point from CPU's BPR register. |
kadonotakashi | 0:8fdf9a60065b | 1372 | * \return GICInterface_Type::BPR |
kadonotakashi | 0:8fdf9a60065b | 1373 | */ |
kadonotakashi | 0:8fdf9a60065b | 1374 | __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) |
kadonotakashi | 0:8fdf9a60065b | 1375 | { |
kadonotakashi | 0:8fdf9a60065b | 1376 | return GICInterface->BPR; |
kadonotakashi | 0:8fdf9a60065b | 1377 | } |
kadonotakashi | 0:8fdf9a60065b | 1378 | |
kadonotakashi | 0:8fdf9a60065b | 1379 | /** \brief Get the status for a given interrupt. |
kadonotakashi | 0:8fdf9a60065b | 1380 | * \param [in] IRQn The interrupt to get status for. |
kadonotakashi | 0:8fdf9a60065b | 1381 | * \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active |
kadonotakashi | 0:8fdf9a60065b | 1382 | */ |
kadonotakashi | 0:8fdf9a60065b | 1383 | __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1384 | { |
kadonotakashi | 0:8fdf9a60065b | 1385 | uint32_t pending, active; |
kadonotakashi | 0:8fdf9a60065b | 1386 | |
kadonotakashi | 0:8fdf9a60065b | 1387 | active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; |
kadonotakashi | 0:8fdf9a60065b | 1388 | pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; |
kadonotakashi | 0:8fdf9a60065b | 1389 | |
kadonotakashi | 0:8fdf9a60065b | 1390 | return ((active<<1U) | pending); |
kadonotakashi | 0:8fdf9a60065b | 1391 | } |
kadonotakashi | 0:8fdf9a60065b | 1392 | |
kadonotakashi | 0:8fdf9a60065b | 1393 | /** \brief Generate a software interrupt using GIC's SGIR register. |
kadonotakashi | 0:8fdf9a60065b | 1394 | * \param [in] IRQn Software interrupt to be generated. |
kadonotakashi | 0:8fdf9a60065b | 1395 | * \param [in] target_list List of CPUs the software interrupt should be forwarded to. |
kadonotakashi | 0:8fdf9a60065b | 1396 | * \param [in] filter_list Filter to be applied to determine interrupt receivers. |
kadonotakashi | 0:8fdf9a60065b | 1397 | */ |
kadonotakashi | 0:8fdf9a60065b | 1398 | __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) |
kadonotakashi | 0:8fdf9a60065b | 1399 | { |
kadonotakashi | 0:8fdf9a60065b | 1400 | GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); |
kadonotakashi | 0:8fdf9a60065b | 1401 | } |
kadonotakashi | 0:8fdf9a60065b | 1402 | |
kadonotakashi | 0:8fdf9a60065b | 1403 | /** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. |
kadonotakashi | 0:8fdf9a60065b | 1404 | * \return GICInterface_Type::HPPIR |
kadonotakashi | 0:8fdf9a60065b | 1405 | */ |
kadonotakashi | 0:8fdf9a60065b | 1406 | __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) |
kadonotakashi | 0:8fdf9a60065b | 1407 | { |
kadonotakashi | 0:8fdf9a60065b | 1408 | return GICInterface->HPPIR; |
kadonotakashi | 0:8fdf9a60065b | 1409 | } |
kadonotakashi | 0:8fdf9a60065b | 1410 | |
kadonotakashi | 0:8fdf9a60065b | 1411 | /** \brief Provides information about the implementer and revision of the CPU interface. |
kadonotakashi | 0:8fdf9a60065b | 1412 | * \return GICInterface_Type::IIDR |
kadonotakashi | 0:8fdf9a60065b | 1413 | */ |
kadonotakashi | 0:8fdf9a60065b | 1414 | __STATIC_INLINE uint32_t GIC_GetInterfaceId(void) |
kadonotakashi | 0:8fdf9a60065b | 1415 | { |
kadonotakashi | 0:8fdf9a60065b | 1416 | return GICInterface->IIDR; |
kadonotakashi | 0:8fdf9a60065b | 1417 | } |
kadonotakashi | 0:8fdf9a60065b | 1418 | |
kadonotakashi | 0:8fdf9a60065b | 1419 | /** \brief Set the interrupt group from the GIC's IGROUPR register. |
kadonotakashi | 0:8fdf9a60065b | 1420 | * \param [in] IRQn The interrupt to be queried. |
kadonotakashi | 0:8fdf9a60065b | 1421 | * \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 |
kadonotakashi | 0:8fdf9a60065b | 1422 | */ |
kadonotakashi | 0:8fdf9a60065b | 1423 | __STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) |
kadonotakashi | 0:8fdf9a60065b | 1424 | { |
kadonotakashi | 0:8fdf9a60065b | 1425 | uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; |
kadonotakashi | 0:8fdf9a60065b | 1426 | uint32_t shift = (IRQn % 32U); |
kadonotakashi | 0:8fdf9a60065b | 1427 | |
kadonotakashi | 0:8fdf9a60065b | 1428 | igroupr &= (~(1U << shift)); |
kadonotakashi | 0:8fdf9a60065b | 1429 | igroupr |= ( (group & 1U) << shift); |
kadonotakashi | 0:8fdf9a60065b | 1430 | |
kadonotakashi | 0:8fdf9a60065b | 1431 | GICDistributor->IGROUPR[IRQn / 32U] = igroupr; |
kadonotakashi | 0:8fdf9a60065b | 1432 | } |
kadonotakashi | 0:8fdf9a60065b | 1433 | #define GIC_SetSecurity GIC_SetGroup |
kadonotakashi | 0:8fdf9a60065b | 1434 | |
kadonotakashi | 0:8fdf9a60065b | 1435 | /** \brief Get the interrupt group from the GIC's IGROUPR register. |
kadonotakashi | 0:8fdf9a60065b | 1436 | * \param [in] IRQn The interrupt to be queried. |
kadonotakashi | 0:8fdf9a60065b | 1437 | * \return 0 - Group 0, 1 - Group 1 |
kadonotakashi | 0:8fdf9a60065b | 1438 | */ |
kadonotakashi | 0:8fdf9a60065b | 1439 | __STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 1440 | { |
kadonotakashi | 0:8fdf9a60065b | 1441 | return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; |
kadonotakashi | 0:8fdf9a60065b | 1442 | } |
kadonotakashi | 0:8fdf9a60065b | 1443 | #define GIC_GetSecurity GIC_GetGroup |
kadonotakashi | 0:8fdf9a60065b | 1444 | |
kadonotakashi | 0:8fdf9a60065b | 1445 | /** \brief Initialize the interrupt distributor. |
kadonotakashi | 0:8fdf9a60065b | 1446 | */ |
kadonotakashi | 0:8fdf9a60065b | 1447 | __STATIC_INLINE void GIC_DistInit(void) |
kadonotakashi | 0:8fdf9a60065b | 1448 | { |
kadonotakashi | 0:8fdf9a60065b | 1449 | uint32_t i; |
kadonotakashi | 0:8fdf9a60065b | 1450 | uint32_t num_irq = 0U; |
kadonotakashi | 0:8fdf9a60065b | 1451 | uint32_t priority_field; |
kadonotakashi | 0:8fdf9a60065b | 1452 | |
kadonotakashi | 0:8fdf9a60065b | 1453 | //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, |
kadonotakashi | 0:8fdf9a60065b | 1454 | //configuring all of the interrupts as Secure. |
kadonotakashi | 0:8fdf9a60065b | 1455 | |
kadonotakashi | 0:8fdf9a60065b | 1456 | //Disable interrupt forwarding |
kadonotakashi | 0:8fdf9a60065b | 1457 | GIC_DisableDistributor(); |
kadonotakashi | 0:8fdf9a60065b | 1458 | //Get the maximum number of interrupts that the GIC supports |
kadonotakashi | 0:8fdf9a60065b | 1459 | num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); |
kadonotakashi | 0:8fdf9a60065b | 1460 | |
kadonotakashi | 0:8fdf9a60065b | 1461 | /* Priority level is implementation defined. |
kadonotakashi | 0:8fdf9a60065b | 1462 | To determine the number of priority bits implemented write 0xFF to an IPRIORITYR |
kadonotakashi | 0:8fdf9a60065b | 1463 | priority field and read back the value stored.*/ |
kadonotakashi | 0:8fdf9a60065b | 1464 | GIC_SetPriority((IRQn_Type)0U, 0xFFU); |
kadonotakashi | 0:8fdf9a60065b | 1465 | priority_field = GIC_GetPriority((IRQn_Type)0U); |
kadonotakashi | 0:8fdf9a60065b | 1466 | |
kadonotakashi | 0:8fdf9a60065b | 1467 | for (i = 32U; i < num_irq; i++) |
kadonotakashi | 0:8fdf9a60065b | 1468 | { |
kadonotakashi | 0:8fdf9a60065b | 1469 | //Disable the SPI interrupt |
kadonotakashi | 0:8fdf9a60065b | 1470 | GIC_DisableIRQ((IRQn_Type)i); |
kadonotakashi | 0:8fdf9a60065b | 1471 | //Set level-sensitive (and N-N model) |
kadonotakashi | 0:8fdf9a60065b | 1472 | GIC_SetConfiguration((IRQn_Type)i, 0U); |
kadonotakashi | 0:8fdf9a60065b | 1473 | //Set priority |
kadonotakashi | 0:8fdf9a60065b | 1474 | GIC_SetPriority((IRQn_Type)i, priority_field/2U); |
kadonotakashi | 0:8fdf9a60065b | 1475 | //Set target list to CPU0 |
kadonotakashi | 0:8fdf9a60065b | 1476 | GIC_SetTarget((IRQn_Type)i, 1U); |
kadonotakashi | 0:8fdf9a60065b | 1477 | } |
kadonotakashi | 0:8fdf9a60065b | 1478 | //Enable distributor |
kadonotakashi | 0:8fdf9a60065b | 1479 | GIC_EnableDistributor(); |
kadonotakashi | 0:8fdf9a60065b | 1480 | } |
kadonotakashi | 0:8fdf9a60065b | 1481 | |
kadonotakashi | 0:8fdf9a60065b | 1482 | /** \brief Initialize the CPU's interrupt interface |
kadonotakashi | 0:8fdf9a60065b | 1483 | */ |
kadonotakashi | 0:8fdf9a60065b | 1484 | __STATIC_INLINE void GIC_CPUInterfaceInit(void) |
kadonotakashi | 0:8fdf9a60065b | 1485 | { |
kadonotakashi | 0:8fdf9a60065b | 1486 | uint32_t i; |
kadonotakashi | 0:8fdf9a60065b | 1487 | uint32_t priority_field; |
kadonotakashi | 0:8fdf9a60065b | 1488 | |
kadonotakashi | 0:8fdf9a60065b | 1489 | //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, |
kadonotakashi | 0:8fdf9a60065b | 1490 | //configuring all of the interrupts as Secure. |
kadonotakashi | 0:8fdf9a60065b | 1491 | |
kadonotakashi | 0:8fdf9a60065b | 1492 | //Disable interrupt forwarding |
kadonotakashi | 0:8fdf9a60065b | 1493 | GIC_DisableInterface(); |
kadonotakashi | 0:8fdf9a60065b | 1494 | |
kadonotakashi | 0:8fdf9a60065b | 1495 | /* Priority level is implementation defined. |
kadonotakashi | 0:8fdf9a60065b | 1496 | To determine the number of priority bits implemented write 0xFF to an IPRIORITYR |
kadonotakashi | 0:8fdf9a60065b | 1497 | priority field and read back the value stored.*/ |
kadonotakashi | 0:8fdf9a60065b | 1498 | GIC_SetPriority((IRQn_Type)0U, 0xFFU); |
kadonotakashi | 0:8fdf9a60065b | 1499 | priority_field = GIC_GetPriority((IRQn_Type)0U); |
kadonotakashi | 0:8fdf9a60065b | 1500 | |
kadonotakashi | 0:8fdf9a60065b | 1501 | //SGI and PPI |
kadonotakashi | 0:8fdf9a60065b | 1502 | for (i = 0U; i < 32U; i++) |
kadonotakashi | 0:8fdf9a60065b | 1503 | { |
kadonotakashi | 0:8fdf9a60065b | 1504 | if(i > 15U) { |
kadonotakashi | 0:8fdf9a60065b | 1505 | //Set level-sensitive (and N-N model) for PPI |
kadonotakashi | 0:8fdf9a60065b | 1506 | GIC_SetConfiguration((IRQn_Type)i, 0U); |
kadonotakashi | 0:8fdf9a60065b | 1507 | } |
kadonotakashi | 0:8fdf9a60065b | 1508 | //Disable SGI and PPI interrupts |
kadonotakashi | 0:8fdf9a60065b | 1509 | GIC_DisableIRQ((IRQn_Type)i); |
kadonotakashi | 0:8fdf9a60065b | 1510 | //Set priority |
kadonotakashi | 0:8fdf9a60065b | 1511 | GIC_SetPriority((IRQn_Type)i, priority_field/2U); |
kadonotakashi | 0:8fdf9a60065b | 1512 | } |
kadonotakashi | 0:8fdf9a60065b | 1513 | //Enable interface |
kadonotakashi | 0:8fdf9a60065b | 1514 | GIC_EnableInterface(); |
kadonotakashi | 0:8fdf9a60065b | 1515 | //Set binary point to 0 |
kadonotakashi | 0:8fdf9a60065b | 1516 | GIC_SetBinaryPoint(0U); |
kadonotakashi | 0:8fdf9a60065b | 1517 | //Set priority mask |
kadonotakashi | 0:8fdf9a60065b | 1518 | GIC_SetInterfacePriorityMask(0xFFU); |
kadonotakashi | 0:8fdf9a60065b | 1519 | } |
kadonotakashi | 0:8fdf9a60065b | 1520 | |
kadonotakashi | 0:8fdf9a60065b | 1521 | /** \brief Initialize and enable the GIC |
kadonotakashi | 0:8fdf9a60065b | 1522 | */ |
kadonotakashi | 0:8fdf9a60065b | 1523 | __STATIC_INLINE void GIC_Enable(void) |
kadonotakashi | 0:8fdf9a60065b | 1524 | { |
kadonotakashi | 0:8fdf9a60065b | 1525 | GIC_DistInit(); |
kadonotakashi | 0:8fdf9a60065b | 1526 | GIC_CPUInterfaceInit(); //per CPU |
kadonotakashi | 0:8fdf9a60065b | 1527 | } |
kadonotakashi | 0:8fdf9a60065b | 1528 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1529 | |
kadonotakashi | 0:8fdf9a60065b | 1530 | /* ########################## Generic Timer functions ############################ */ |
kadonotakashi | 0:8fdf9a60065b | 1531 | #if (__TIM_PRESENT == 1U) || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 1532 | |
kadonotakashi | 0:8fdf9a60065b | 1533 | /* PL1 Physical Timer */ |
kadonotakashi | 0:8fdf9a60065b | 1534 | #if (__CORTEX_A == 7U) || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 1535 | |
kadonotakashi | 0:8fdf9a60065b | 1536 | /** \brief Physical Timer Control register */ |
kadonotakashi | 0:8fdf9a60065b | 1537 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 1538 | { |
kadonotakashi | 0:8fdf9a60065b | 1539 | struct |
kadonotakashi | 0:8fdf9a60065b | 1540 | { |
kadonotakashi | 0:8fdf9a60065b | 1541 | uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ |
kadonotakashi | 0:8fdf9a60065b | 1542 | uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ |
kadonotakashi | 0:8fdf9a60065b | 1543 | uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ |
kadonotakashi | 0:8fdf9a60065b | 1544 | RESERVED(0:29, uint32_t) |
kadonotakashi | 0:8fdf9a60065b | 1545 | } b; /*!< \brief Structure used for bit access */ |
kadonotakashi | 0:8fdf9a60065b | 1546 | uint32_t w; /*!< \brief Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 1547 | } CNTP_CTL_Type; |
kadonotakashi | 0:8fdf9a60065b | 1548 | |
kadonotakashi | 0:8fdf9a60065b | 1549 | /** \brief Configures the frequency the timer shall run at. |
kadonotakashi | 0:8fdf9a60065b | 1550 | * \param [in] value The timer frequency in Hz. |
kadonotakashi | 0:8fdf9a60065b | 1551 | */ |
kadonotakashi | 0:8fdf9a60065b | 1552 | __STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) |
kadonotakashi | 0:8fdf9a60065b | 1553 | { |
kadonotakashi | 0:8fdf9a60065b | 1554 | __set_CNTFRQ(value); |
kadonotakashi | 0:8fdf9a60065b | 1555 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 1556 | } |
kadonotakashi | 0:8fdf9a60065b | 1557 | |
kadonotakashi | 0:8fdf9a60065b | 1558 | /** \brief Sets the reset value of the timer. |
kadonotakashi | 0:8fdf9a60065b | 1559 | * \param [in] value The value the timer is loaded with. |
kadonotakashi | 0:8fdf9a60065b | 1560 | */ |
kadonotakashi | 0:8fdf9a60065b | 1561 | __STATIC_INLINE void PL1_SetLoadValue(uint32_t value) |
kadonotakashi | 0:8fdf9a60065b | 1562 | { |
kadonotakashi | 0:8fdf9a60065b | 1563 | __set_CNTP_TVAL(value); |
kadonotakashi | 0:8fdf9a60065b | 1564 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 1565 | } |
kadonotakashi | 0:8fdf9a60065b | 1566 | |
kadonotakashi | 0:8fdf9a60065b | 1567 | /** \brief Get the current counter value. |
kadonotakashi | 0:8fdf9a60065b | 1568 | * \return Current counter value. |
kadonotakashi | 0:8fdf9a60065b | 1569 | */ |
kadonotakashi | 0:8fdf9a60065b | 1570 | __STATIC_INLINE uint32_t PL1_GetCurrentValue(void) |
kadonotakashi | 0:8fdf9a60065b | 1571 | { |
kadonotakashi | 0:8fdf9a60065b | 1572 | return(__get_CNTP_TVAL()); |
kadonotakashi | 0:8fdf9a60065b | 1573 | } |
kadonotakashi | 0:8fdf9a60065b | 1574 | |
kadonotakashi | 0:8fdf9a60065b | 1575 | /** \brief Get the current physical counter value. |
kadonotakashi | 0:8fdf9a60065b | 1576 | * \return Current physical counter value. |
kadonotakashi | 0:8fdf9a60065b | 1577 | */ |
kadonotakashi | 0:8fdf9a60065b | 1578 | __STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) |
kadonotakashi | 0:8fdf9a60065b | 1579 | { |
kadonotakashi | 0:8fdf9a60065b | 1580 | return(__get_CNTPCT()); |
kadonotakashi | 0:8fdf9a60065b | 1581 | } |
kadonotakashi | 0:8fdf9a60065b | 1582 | |
kadonotakashi | 0:8fdf9a60065b | 1583 | /** \brief Set the physical compare value. |
kadonotakashi | 0:8fdf9a60065b | 1584 | * \param [in] value New physical timer compare value. |
kadonotakashi | 0:8fdf9a60065b | 1585 | */ |
kadonotakashi | 0:8fdf9a60065b | 1586 | __STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) |
kadonotakashi | 0:8fdf9a60065b | 1587 | { |
kadonotakashi | 0:8fdf9a60065b | 1588 | __set_CNTP_CVAL(value); |
kadonotakashi | 0:8fdf9a60065b | 1589 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 1590 | } |
kadonotakashi | 0:8fdf9a60065b | 1591 | |
kadonotakashi | 0:8fdf9a60065b | 1592 | /** \brief Get the physical compare value. |
kadonotakashi | 0:8fdf9a60065b | 1593 | * \return Physical compare value. |
kadonotakashi | 0:8fdf9a60065b | 1594 | */ |
kadonotakashi | 0:8fdf9a60065b | 1595 | __STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) |
kadonotakashi | 0:8fdf9a60065b | 1596 | { |
kadonotakashi | 0:8fdf9a60065b | 1597 | return(__get_CNTP_CVAL()); |
kadonotakashi | 0:8fdf9a60065b | 1598 | } |
kadonotakashi | 0:8fdf9a60065b | 1599 | |
kadonotakashi | 0:8fdf9a60065b | 1600 | /** \brief Configure the timer by setting the control value. |
kadonotakashi | 0:8fdf9a60065b | 1601 | * \param [in] value New timer control value. |
kadonotakashi | 0:8fdf9a60065b | 1602 | */ |
kadonotakashi | 0:8fdf9a60065b | 1603 | __STATIC_INLINE void PL1_SetControl(uint32_t value) |
kadonotakashi | 0:8fdf9a60065b | 1604 | { |
kadonotakashi | 0:8fdf9a60065b | 1605 | __set_CNTP_CTL(value); |
kadonotakashi | 0:8fdf9a60065b | 1606 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 1607 | } |
kadonotakashi | 0:8fdf9a60065b | 1608 | |
kadonotakashi | 0:8fdf9a60065b | 1609 | /** \brief Get the control value. |
kadonotakashi | 0:8fdf9a60065b | 1610 | * \return Control value. |
kadonotakashi | 0:8fdf9a60065b | 1611 | */ |
kadonotakashi | 0:8fdf9a60065b | 1612 | __STATIC_INLINE uint32_t PL1_GetControl(void) |
kadonotakashi | 0:8fdf9a60065b | 1613 | { |
kadonotakashi | 0:8fdf9a60065b | 1614 | return(__get_CNTP_CTL()); |
kadonotakashi | 0:8fdf9a60065b | 1615 | } |
kadonotakashi | 0:8fdf9a60065b | 1616 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1617 | |
kadonotakashi | 0:8fdf9a60065b | 1618 | /* Private Timer */ |
kadonotakashi | 0:8fdf9a60065b | 1619 | #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) |
kadonotakashi | 0:8fdf9a60065b | 1620 | /** \brief Set the load value to timers LOAD register. |
kadonotakashi | 0:8fdf9a60065b | 1621 | * \param [in] value The load value to be set. |
kadonotakashi | 0:8fdf9a60065b | 1622 | */ |
kadonotakashi | 0:8fdf9a60065b | 1623 | __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) |
kadonotakashi | 0:8fdf9a60065b | 1624 | { |
kadonotakashi | 0:8fdf9a60065b | 1625 | PTIM->LOAD = value; |
kadonotakashi | 0:8fdf9a60065b | 1626 | } |
kadonotakashi | 0:8fdf9a60065b | 1627 | |
kadonotakashi | 0:8fdf9a60065b | 1628 | /** \brief Get the load value from timers LOAD register. |
kadonotakashi | 0:8fdf9a60065b | 1629 | * \return Timer_Type::LOAD |
kadonotakashi | 0:8fdf9a60065b | 1630 | */ |
kadonotakashi | 0:8fdf9a60065b | 1631 | __STATIC_INLINE uint32_t PTIM_GetLoadValue(void) |
kadonotakashi | 0:8fdf9a60065b | 1632 | { |
kadonotakashi | 0:8fdf9a60065b | 1633 | return(PTIM->LOAD); |
kadonotakashi | 0:8fdf9a60065b | 1634 | } |
kadonotakashi | 0:8fdf9a60065b | 1635 | |
kadonotakashi | 0:8fdf9a60065b | 1636 | /** \brief Set current counter value from its COUNTER register. |
kadonotakashi | 0:8fdf9a60065b | 1637 | */ |
kadonotakashi | 0:8fdf9a60065b | 1638 | __STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) |
kadonotakashi | 0:8fdf9a60065b | 1639 | { |
kadonotakashi | 0:8fdf9a60065b | 1640 | PTIM->COUNTER = value; |
kadonotakashi | 0:8fdf9a60065b | 1641 | } |
kadonotakashi | 0:8fdf9a60065b | 1642 | |
kadonotakashi | 0:8fdf9a60065b | 1643 | /** \brief Get current counter value from timers COUNTER register. |
kadonotakashi | 0:8fdf9a60065b | 1644 | * \result Timer_Type::COUNTER |
kadonotakashi | 0:8fdf9a60065b | 1645 | */ |
kadonotakashi | 0:8fdf9a60065b | 1646 | __STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) |
kadonotakashi | 0:8fdf9a60065b | 1647 | { |
kadonotakashi | 0:8fdf9a60065b | 1648 | return(PTIM->COUNTER); |
kadonotakashi | 0:8fdf9a60065b | 1649 | } |
kadonotakashi | 0:8fdf9a60065b | 1650 | |
kadonotakashi | 0:8fdf9a60065b | 1651 | /** \brief Configure the timer using its CONTROL register. |
kadonotakashi | 0:8fdf9a60065b | 1652 | * \param [in] value The new configuration value to be set. |
kadonotakashi | 0:8fdf9a60065b | 1653 | */ |
kadonotakashi | 0:8fdf9a60065b | 1654 | __STATIC_INLINE void PTIM_SetControl(uint32_t value) |
kadonotakashi | 0:8fdf9a60065b | 1655 | { |
kadonotakashi | 0:8fdf9a60065b | 1656 | PTIM->CONTROL = value; |
kadonotakashi | 0:8fdf9a60065b | 1657 | } |
kadonotakashi | 0:8fdf9a60065b | 1658 | |
kadonotakashi | 0:8fdf9a60065b | 1659 | /** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. |
kadonotakashi | 0:8fdf9a60065b | 1660 | * \return Timer_Type::CONTROL |
kadonotakashi | 0:8fdf9a60065b | 1661 | */ |
kadonotakashi | 0:8fdf9a60065b | 1662 | __STATIC_INLINE uint32_t PTIM_GetControl(void) |
kadonotakashi | 0:8fdf9a60065b | 1663 | { |
kadonotakashi | 0:8fdf9a60065b | 1664 | return(PTIM->CONTROL); |
kadonotakashi | 0:8fdf9a60065b | 1665 | } |
kadonotakashi | 0:8fdf9a60065b | 1666 | |
kadonotakashi | 0:8fdf9a60065b | 1667 | /** ref Timer_Type::CONTROL Get the event flag in timers ISR register. |
kadonotakashi | 0:8fdf9a60065b | 1668 | * \return 0 - flag is not set, 1- flag is set |
kadonotakashi | 0:8fdf9a60065b | 1669 | */ |
kadonotakashi | 0:8fdf9a60065b | 1670 | __STATIC_INLINE uint32_t PTIM_GetEventFlag(void) |
kadonotakashi | 0:8fdf9a60065b | 1671 | { |
kadonotakashi | 0:8fdf9a60065b | 1672 | return (PTIM->ISR & 1UL); |
kadonotakashi | 0:8fdf9a60065b | 1673 | } |
kadonotakashi | 0:8fdf9a60065b | 1674 | |
kadonotakashi | 0:8fdf9a60065b | 1675 | /** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. |
kadonotakashi | 0:8fdf9a60065b | 1676 | */ |
kadonotakashi | 0:8fdf9a60065b | 1677 | __STATIC_INLINE void PTIM_ClearEventFlag(void) |
kadonotakashi | 0:8fdf9a60065b | 1678 | { |
kadonotakashi | 0:8fdf9a60065b | 1679 | PTIM->ISR = 1; |
kadonotakashi | 0:8fdf9a60065b | 1680 | } |
kadonotakashi | 0:8fdf9a60065b | 1681 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1682 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1683 | |
kadonotakashi | 0:8fdf9a60065b | 1684 | /* ########################## MMU functions ###################################### */ |
kadonotakashi | 0:8fdf9a60065b | 1685 | |
kadonotakashi | 0:8fdf9a60065b | 1686 | #define SECTION_DESCRIPTOR (0x2) |
kadonotakashi | 0:8fdf9a60065b | 1687 | #define SECTION_MASK (0xFFFFFFFC) |
kadonotakashi | 0:8fdf9a60065b | 1688 | |
kadonotakashi | 0:8fdf9a60065b | 1689 | #define SECTION_TEXCB_MASK (0xFFFF8FF3) |
kadonotakashi | 0:8fdf9a60065b | 1690 | #define SECTION_B_SHIFT (2) |
kadonotakashi | 0:8fdf9a60065b | 1691 | #define SECTION_C_SHIFT (3) |
kadonotakashi | 0:8fdf9a60065b | 1692 | #define SECTION_TEX0_SHIFT (12) |
kadonotakashi | 0:8fdf9a60065b | 1693 | #define SECTION_TEX1_SHIFT (13) |
kadonotakashi | 0:8fdf9a60065b | 1694 | #define SECTION_TEX2_SHIFT (14) |
kadonotakashi | 0:8fdf9a60065b | 1695 | |
kadonotakashi | 0:8fdf9a60065b | 1696 | #define SECTION_XN_MASK (0xFFFFFFEF) |
kadonotakashi | 0:8fdf9a60065b | 1697 | #define SECTION_XN_SHIFT (4) |
kadonotakashi | 0:8fdf9a60065b | 1698 | |
kadonotakashi | 0:8fdf9a60065b | 1699 | #define SECTION_DOMAIN_MASK (0xFFFFFE1F) |
kadonotakashi | 0:8fdf9a60065b | 1700 | #define SECTION_DOMAIN_SHIFT (5) |
kadonotakashi | 0:8fdf9a60065b | 1701 | |
kadonotakashi | 0:8fdf9a60065b | 1702 | #define SECTION_P_MASK (0xFFFFFDFF) |
kadonotakashi | 0:8fdf9a60065b | 1703 | #define SECTION_P_SHIFT (9) |
kadonotakashi | 0:8fdf9a60065b | 1704 | |
kadonotakashi | 0:8fdf9a60065b | 1705 | #define SECTION_AP_MASK (0xFFFF73FF) |
kadonotakashi | 0:8fdf9a60065b | 1706 | #define SECTION_AP_SHIFT (10) |
kadonotakashi | 0:8fdf9a60065b | 1707 | #define SECTION_AP2_SHIFT (15) |
kadonotakashi | 0:8fdf9a60065b | 1708 | |
kadonotakashi | 0:8fdf9a60065b | 1709 | #define SECTION_S_MASK (0xFFFEFFFF) |
kadonotakashi | 0:8fdf9a60065b | 1710 | #define SECTION_S_SHIFT (16) |
kadonotakashi | 0:8fdf9a60065b | 1711 | |
kadonotakashi | 0:8fdf9a60065b | 1712 | #define SECTION_NG_MASK (0xFFFDFFFF) |
kadonotakashi | 0:8fdf9a60065b | 1713 | #define SECTION_NG_SHIFT (17) |
kadonotakashi | 0:8fdf9a60065b | 1714 | |
kadonotakashi | 0:8fdf9a60065b | 1715 | #define SECTION_NS_MASK (0xFFF7FFFF) |
kadonotakashi | 0:8fdf9a60065b | 1716 | #define SECTION_NS_SHIFT (19) |
kadonotakashi | 0:8fdf9a60065b | 1717 | |
kadonotakashi | 0:8fdf9a60065b | 1718 | #define PAGE_L1_DESCRIPTOR (0x1) |
kadonotakashi | 0:8fdf9a60065b | 1719 | #define PAGE_L1_MASK (0xFFFFFFFC) |
kadonotakashi | 0:8fdf9a60065b | 1720 | |
kadonotakashi | 0:8fdf9a60065b | 1721 | #define PAGE_L2_4K_DESC (0x2) |
kadonotakashi | 0:8fdf9a60065b | 1722 | #define PAGE_L2_4K_MASK (0xFFFFFFFD) |
kadonotakashi | 0:8fdf9a60065b | 1723 | |
kadonotakashi | 0:8fdf9a60065b | 1724 | #define PAGE_L2_64K_DESC (0x1) |
kadonotakashi | 0:8fdf9a60065b | 1725 | #define PAGE_L2_64K_MASK (0xFFFFFFFC) |
kadonotakashi | 0:8fdf9a60065b | 1726 | |
kadonotakashi | 0:8fdf9a60065b | 1727 | #define PAGE_4K_TEXCB_MASK (0xFFFFFE33) |
kadonotakashi | 0:8fdf9a60065b | 1728 | #define PAGE_4K_B_SHIFT (2) |
kadonotakashi | 0:8fdf9a60065b | 1729 | #define PAGE_4K_C_SHIFT (3) |
kadonotakashi | 0:8fdf9a60065b | 1730 | #define PAGE_4K_TEX0_SHIFT (6) |
kadonotakashi | 0:8fdf9a60065b | 1731 | #define PAGE_4K_TEX1_SHIFT (7) |
kadonotakashi | 0:8fdf9a60065b | 1732 | #define PAGE_4K_TEX2_SHIFT (8) |
kadonotakashi | 0:8fdf9a60065b | 1733 | |
kadonotakashi | 0:8fdf9a60065b | 1734 | #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) |
kadonotakashi | 0:8fdf9a60065b | 1735 | #define PAGE_64K_B_SHIFT (2) |
kadonotakashi | 0:8fdf9a60065b | 1736 | #define PAGE_64K_C_SHIFT (3) |
kadonotakashi | 0:8fdf9a60065b | 1737 | #define PAGE_64K_TEX0_SHIFT (12) |
kadonotakashi | 0:8fdf9a60065b | 1738 | #define PAGE_64K_TEX1_SHIFT (13) |
kadonotakashi | 0:8fdf9a60065b | 1739 | #define PAGE_64K_TEX2_SHIFT (14) |
kadonotakashi | 0:8fdf9a60065b | 1740 | |
kadonotakashi | 0:8fdf9a60065b | 1741 | #define PAGE_TEXCB_MASK (0xFFFF8FF3) |
kadonotakashi | 0:8fdf9a60065b | 1742 | #define PAGE_B_SHIFT (2) |
kadonotakashi | 0:8fdf9a60065b | 1743 | #define PAGE_C_SHIFT (3) |
kadonotakashi | 0:8fdf9a60065b | 1744 | #define PAGE_TEX_SHIFT (12) |
kadonotakashi | 0:8fdf9a60065b | 1745 | |
kadonotakashi | 0:8fdf9a60065b | 1746 | #define PAGE_XN_4K_MASK (0xFFFFFFFE) |
kadonotakashi | 0:8fdf9a60065b | 1747 | #define PAGE_XN_4K_SHIFT (0) |
kadonotakashi | 0:8fdf9a60065b | 1748 | #define PAGE_XN_64K_MASK (0xFFFF7FFF) |
kadonotakashi | 0:8fdf9a60065b | 1749 | #define PAGE_XN_64K_SHIFT (15) |
kadonotakashi | 0:8fdf9a60065b | 1750 | |
kadonotakashi | 0:8fdf9a60065b | 1751 | #define PAGE_DOMAIN_MASK (0xFFFFFE1F) |
kadonotakashi | 0:8fdf9a60065b | 1752 | #define PAGE_DOMAIN_SHIFT (5) |
kadonotakashi | 0:8fdf9a60065b | 1753 | |
kadonotakashi | 0:8fdf9a60065b | 1754 | #define PAGE_P_MASK (0xFFFFFDFF) |
kadonotakashi | 0:8fdf9a60065b | 1755 | #define PAGE_P_SHIFT (9) |
kadonotakashi | 0:8fdf9a60065b | 1756 | |
kadonotakashi | 0:8fdf9a60065b | 1757 | #define PAGE_AP_MASK (0xFFFFFDCF) |
kadonotakashi | 0:8fdf9a60065b | 1758 | #define PAGE_AP_SHIFT (4) |
kadonotakashi | 0:8fdf9a60065b | 1759 | #define PAGE_AP2_SHIFT (9) |
kadonotakashi | 0:8fdf9a60065b | 1760 | |
kadonotakashi | 0:8fdf9a60065b | 1761 | #define PAGE_S_MASK (0xFFFFFBFF) |
kadonotakashi | 0:8fdf9a60065b | 1762 | #define PAGE_S_SHIFT (10) |
kadonotakashi | 0:8fdf9a60065b | 1763 | |
kadonotakashi | 0:8fdf9a60065b | 1764 | #define PAGE_NG_MASK (0xFFFFF7FF) |
kadonotakashi | 0:8fdf9a60065b | 1765 | #define PAGE_NG_SHIFT (11) |
kadonotakashi | 0:8fdf9a60065b | 1766 | |
kadonotakashi | 0:8fdf9a60065b | 1767 | #define PAGE_NS_MASK (0xFFFFFFF7) |
kadonotakashi | 0:8fdf9a60065b | 1768 | #define PAGE_NS_SHIFT (3) |
kadonotakashi | 0:8fdf9a60065b | 1769 | |
kadonotakashi | 0:8fdf9a60065b | 1770 | #define OFFSET_1M (0x00100000) |
kadonotakashi | 0:8fdf9a60065b | 1771 | #define OFFSET_64K (0x00010000) |
kadonotakashi | 0:8fdf9a60065b | 1772 | #define OFFSET_4K (0x00001000) |
kadonotakashi | 0:8fdf9a60065b | 1773 | |
kadonotakashi | 0:8fdf9a60065b | 1774 | #define DESCRIPTOR_FAULT (0x00000000) |
kadonotakashi | 0:8fdf9a60065b | 1775 | |
kadonotakashi | 0:8fdf9a60065b | 1776 | /* Attributes enumerations */ |
kadonotakashi | 0:8fdf9a60065b | 1777 | |
kadonotakashi | 0:8fdf9a60065b | 1778 | /* Region size attributes */ |
kadonotakashi | 0:8fdf9a60065b | 1779 | typedef enum |
kadonotakashi | 0:8fdf9a60065b | 1780 | { |
kadonotakashi | 0:8fdf9a60065b | 1781 | SECTION, |
kadonotakashi | 0:8fdf9a60065b | 1782 | PAGE_4k, |
kadonotakashi | 0:8fdf9a60065b | 1783 | PAGE_64k, |
kadonotakashi | 0:8fdf9a60065b | 1784 | } mmu_region_size_Type; |
kadonotakashi | 0:8fdf9a60065b | 1785 | |
kadonotakashi | 0:8fdf9a60065b | 1786 | /* Region type attributes */ |
kadonotakashi | 0:8fdf9a60065b | 1787 | typedef enum |
kadonotakashi | 0:8fdf9a60065b | 1788 | { |
kadonotakashi | 0:8fdf9a60065b | 1789 | NORMAL, |
kadonotakashi | 0:8fdf9a60065b | 1790 | DEVICE, |
kadonotakashi | 0:8fdf9a60065b | 1791 | SHARED_DEVICE, |
kadonotakashi | 0:8fdf9a60065b | 1792 | NON_SHARED_DEVICE, |
kadonotakashi | 0:8fdf9a60065b | 1793 | STRONGLY_ORDERED |
kadonotakashi | 0:8fdf9a60065b | 1794 | } mmu_memory_Type; |
kadonotakashi | 0:8fdf9a60065b | 1795 | |
kadonotakashi | 0:8fdf9a60065b | 1796 | /* Region cacheability attributes */ |
kadonotakashi | 0:8fdf9a60065b | 1797 | typedef enum |
kadonotakashi | 0:8fdf9a60065b | 1798 | { |
kadonotakashi | 0:8fdf9a60065b | 1799 | NON_CACHEABLE, |
kadonotakashi | 0:8fdf9a60065b | 1800 | WB_WA, |
kadonotakashi | 0:8fdf9a60065b | 1801 | WT, |
kadonotakashi | 0:8fdf9a60065b | 1802 | WB_NO_WA, |
kadonotakashi | 0:8fdf9a60065b | 1803 | } mmu_cacheability_Type; |
kadonotakashi | 0:8fdf9a60065b | 1804 | |
kadonotakashi | 0:8fdf9a60065b | 1805 | /* Region parity check attributes */ |
kadonotakashi | 0:8fdf9a60065b | 1806 | typedef enum |
kadonotakashi | 0:8fdf9a60065b | 1807 | { |
kadonotakashi | 0:8fdf9a60065b | 1808 | ECC_DISABLED, |
kadonotakashi | 0:8fdf9a60065b | 1809 | ECC_ENABLED, |
kadonotakashi | 0:8fdf9a60065b | 1810 | } mmu_ecc_check_Type; |
kadonotakashi | 0:8fdf9a60065b | 1811 | |
kadonotakashi | 0:8fdf9a60065b | 1812 | /* Region execution attributes */ |
kadonotakashi | 0:8fdf9a60065b | 1813 | typedef enum |
kadonotakashi | 0:8fdf9a60065b | 1814 | { |
kadonotakashi | 0:8fdf9a60065b | 1815 | EXECUTE, |
kadonotakashi | 0:8fdf9a60065b | 1816 | NON_EXECUTE, |
kadonotakashi | 0:8fdf9a60065b | 1817 | } mmu_execute_Type; |
kadonotakashi | 0:8fdf9a60065b | 1818 | |
kadonotakashi | 0:8fdf9a60065b | 1819 | /* Region global attributes */ |
kadonotakashi | 0:8fdf9a60065b | 1820 | typedef enum |
kadonotakashi | 0:8fdf9a60065b | 1821 | { |
kadonotakashi | 0:8fdf9a60065b | 1822 | GLOBAL, |
kadonotakashi | 0:8fdf9a60065b | 1823 | NON_GLOBAL, |
kadonotakashi | 0:8fdf9a60065b | 1824 | } mmu_global_Type; |
kadonotakashi | 0:8fdf9a60065b | 1825 | |
kadonotakashi | 0:8fdf9a60065b | 1826 | /* Region shareability attributes */ |
kadonotakashi | 0:8fdf9a60065b | 1827 | typedef enum |
kadonotakashi | 0:8fdf9a60065b | 1828 | { |
kadonotakashi | 0:8fdf9a60065b | 1829 | NON_SHARED, |
kadonotakashi | 0:8fdf9a60065b | 1830 | SHARED, |
kadonotakashi | 0:8fdf9a60065b | 1831 | } mmu_shared_Type; |
kadonotakashi | 0:8fdf9a60065b | 1832 | |
kadonotakashi | 0:8fdf9a60065b | 1833 | /* Region security attributes */ |
kadonotakashi | 0:8fdf9a60065b | 1834 | typedef enum |
kadonotakashi | 0:8fdf9a60065b | 1835 | { |
kadonotakashi | 0:8fdf9a60065b | 1836 | SECURE, |
kadonotakashi | 0:8fdf9a60065b | 1837 | NON_SECURE, |
kadonotakashi | 0:8fdf9a60065b | 1838 | } mmu_secure_Type; |
kadonotakashi | 0:8fdf9a60065b | 1839 | |
kadonotakashi | 0:8fdf9a60065b | 1840 | /* Region access attributes */ |
kadonotakashi | 0:8fdf9a60065b | 1841 | typedef enum |
kadonotakashi | 0:8fdf9a60065b | 1842 | { |
kadonotakashi | 0:8fdf9a60065b | 1843 | NO_ACCESS, |
kadonotakashi | 0:8fdf9a60065b | 1844 | RW, |
kadonotakashi | 0:8fdf9a60065b | 1845 | READ, |
kadonotakashi | 0:8fdf9a60065b | 1846 | } mmu_access_Type; |
kadonotakashi | 0:8fdf9a60065b | 1847 | |
kadonotakashi | 0:8fdf9a60065b | 1848 | /* Memory Region definition */ |
kadonotakashi | 0:8fdf9a60065b | 1849 | typedef struct RegionStruct { |
kadonotakashi | 0:8fdf9a60065b | 1850 | mmu_region_size_Type rg_t; |
kadonotakashi | 0:8fdf9a60065b | 1851 | mmu_memory_Type mem_t; |
kadonotakashi | 0:8fdf9a60065b | 1852 | uint8_t domain; |
kadonotakashi | 0:8fdf9a60065b | 1853 | mmu_cacheability_Type inner_norm_t; |
kadonotakashi | 0:8fdf9a60065b | 1854 | mmu_cacheability_Type outer_norm_t; |
kadonotakashi | 0:8fdf9a60065b | 1855 | mmu_ecc_check_Type e_t; |
kadonotakashi | 0:8fdf9a60065b | 1856 | mmu_execute_Type xn_t; |
kadonotakashi | 0:8fdf9a60065b | 1857 | mmu_global_Type g_t; |
kadonotakashi | 0:8fdf9a60065b | 1858 | mmu_secure_Type sec_t; |
kadonotakashi | 0:8fdf9a60065b | 1859 | mmu_access_Type priv_t; |
kadonotakashi | 0:8fdf9a60065b | 1860 | mmu_access_Type user_t; |
kadonotakashi | 0:8fdf9a60065b | 1861 | mmu_shared_Type sh_t; |
kadonotakashi | 0:8fdf9a60065b | 1862 | |
kadonotakashi | 0:8fdf9a60065b | 1863 | } mmu_region_attributes_Type; |
kadonotakashi | 0:8fdf9a60065b | 1864 | |
kadonotakashi | 0:8fdf9a60065b | 1865 | //Following macros define the descriptors and attributes |
kadonotakashi | 0:8fdf9a60065b | 1866 | //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 |
kadonotakashi | 0:8fdf9a60065b | 1867 | #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ |
kadonotakashi | 0:8fdf9a60065b | 1868 | region.domain = 0x0; \ |
kadonotakashi | 0:8fdf9a60065b | 1869 | region.e_t = ECC_DISABLED; \ |
kadonotakashi | 0:8fdf9a60065b | 1870 | region.g_t = GLOBAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1871 | region.inner_norm_t = WB_WA; \ |
kadonotakashi | 0:8fdf9a60065b | 1872 | region.outer_norm_t = WB_WA; \ |
kadonotakashi | 0:8fdf9a60065b | 1873 | region.mem_t = NORMAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1874 | region.sec_t = SECURE; \ |
kadonotakashi | 0:8fdf9a60065b | 1875 | region.xn_t = EXECUTE; \ |
kadonotakashi | 0:8fdf9a60065b | 1876 | region.priv_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1877 | region.user_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1878 | region.sh_t = NON_SHARED; \ |
kadonotakashi | 0:8fdf9a60065b | 1879 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
kadonotakashi | 0:8fdf9a60065b | 1880 | |
kadonotakashi | 0:8fdf9a60065b | 1881 | //Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 |
kadonotakashi | 0:8fdf9a60065b | 1882 | #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ |
kadonotakashi | 0:8fdf9a60065b | 1883 | region.domain = 0x0; \ |
kadonotakashi | 0:8fdf9a60065b | 1884 | region.e_t = ECC_DISABLED; \ |
kadonotakashi | 0:8fdf9a60065b | 1885 | region.g_t = GLOBAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1886 | region.inner_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 1887 | region.outer_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 1888 | region.mem_t = NORMAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1889 | region.sec_t = SECURE; \ |
kadonotakashi | 0:8fdf9a60065b | 1890 | region.xn_t = EXECUTE; \ |
kadonotakashi | 0:8fdf9a60065b | 1891 | region.priv_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1892 | region.user_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1893 | region.sh_t = NON_SHARED; \ |
kadonotakashi | 0:8fdf9a60065b | 1894 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
kadonotakashi | 0:8fdf9a60065b | 1895 | |
kadonotakashi | 0:8fdf9a60065b | 1896 | //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 |
kadonotakashi | 0:8fdf9a60065b | 1897 | #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ |
kadonotakashi | 0:8fdf9a60065b | 1898 | region.domain = 0x0; \ |
kadonotakashi | 0:8fdf9a60065b | 1899 | region.e_t = ECC_DISABLED; \ |
kadonotakashi | 0:8fdf9a60065b | 1900 | region.g_t = GLOBAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1901 | region.inner_norm_t = WB_WA; \ |
kadonotakashi | 0:8fdf9a60065b | 1902 | region.outer_norm_t = WB_WA; \ |
kadonotakashi | 0:8fdf9a60065b | 1903 | region.mem_t = NORMAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1904 | region.sec_t = SECURE; \ |
kadonotakashi | 0:8fdf9a60065b | 1905 | region.xn_t = EXECUTE; \ |
kadonotakashi | 0:8fdf9a60065b | 1906 | region.priv_t = READ; \ |
kadonotakashi | 0:8fdf9a60065b | 1907 | region.user_t = READ; \ |
kadonotakashi | 0:8fdf9a60065b | 1908 | region.sh_t = NON_SHARED; \ |
kadonotakashi | 0:8fdf9a60065b | 1909 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
kadonotakashi | 0:8fdf9a60065b | 1910 | |
kadonotakashi | 0:8fdf9a60065b | 1911 | //Sect_Normal_RO. Sect_Normal_Cod, but not executable |
kadonotakashi | 0:8fdf9a60065b | 1912 | #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ |
kadonotakashi | 0:8fdf9a60065b | 1913 | region.domain = 0x0; \ |
kadonotakashi | 0:8fdf9a60065b | 1914 | region.e_t = ECC_DISABLED; \ |
kadonotakashi | 0:8fdf9a60065b | 1915 | region.g_t = GLOBAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1916 | region.inner_norm_t = WB_WA; \ |
kadonotakashi | 0:8fdf9a60065b | 1917 | region.outer_norm_t = WB_WA; \ |
kadonotakashi | 0:8fdf9a60065b | 1918 | region.mem_t = NORMAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1919 | region.sec_t = SECURE; \ |
kadonotakashi | 0:8fdf9a60065b | 1920 | region.xn_t = NON_EXECUTE; \ |
kadonotakashi | 0:8fdf9a60065b | 1921 | region.priv_t = READ; \ |
kadonotakashi | 0:8fdf9a60065b | 1922 | region.user_t = READ; \ |
kadonotakashi | 0:8fdf9a60065b | 1923 | region.sh_t = NON_SHARED; \ |
kadonotakashi | 0:8fdf9a60065b | 1924 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
kadonotakashi | 0:8fdf9a60065b | 1925 | |
kadonotakashi | 0:8fdf9a60065b | 1926 | //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable |
kadonotakashi | 0:8fdf9a60065b | 1927 | #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ |
kadonotakashi | 0:8fdf9a60065b | 1928 | region.domain = 0x0; \ |
kadonotakashi | 0:8fdf9a60065b | 1929 | region.e_t = ECC_DISABLED; \ |
kadonotakashi | 0:8fdf9a60065b | 1930 | region.g_t = GLOBAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1931 | region.inner_norm_t = WB_WA; \ |
kadonotakashi | 0:8fdf9a60065b | 1932 | region.outer_norm_t = WB_WA; \ |
kadonotakashi | 0:8fdf9a60065b | 1933 | region.mem_t = NORMAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1934 | region.sec_t = SECURE; \ |
kadonotakashi | 0:8fdf9a60065b | 1935 | region.xn_t = NON_EXECUTE; \ |
kadonotakashi | 0:8fdf9a60065b | 1936 | region.priv_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1937 | region.user_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1938 | region.sh_t = NON_SHARED; \ |
kadonotakashi | 0:8fdf9a60065b | 1939 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
kadonotakashi | 0:8fdf9a60065b | 1940 | //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 |
kadonotakashi | 0:8fdf9a60065b | 1941 | #define section_so(descriptor_l1, region) region.rg_t = SECTION; \ |
kadonotakashi | 0:8fdf9a60065b | 1942 | region.domain = 0x0; \ |
kadonotakashi | 0:8fdf9a60065b | 1943 | region.e_t = ECC_DISABLED; \ |
kadonotakashi | 0:8fdf9a60065b | 1944 | region.g_t = GLOBAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1945 | region.inner_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 1946 | region.outer_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 1947 | region.mem_t = STRONGLY_ORDERED; \ |
kadonotakashi | 0:8fdf9a60065b | 1948 | region.sec_t = SECURE; \ |
kadonotakashi | 0:8fdf9a60065b | 1949 | region.xn_t = NON_EXECUTE; \ |
kadonotakashi | 0:8fdf9a60065b | 1950 | region.priv_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1951 | region.user_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1952 | region.sh_t = NON_SHARED; \ |
kadonotakashi | 0:8fdf9a60065b | 1953 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
kadonotakashi | 0:8fdf9a60065b | 1954 | |
kadonotakashi | 0:8fdf9a60065b | 1955 | //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 |
kadonotakashi | 0:8fdf9a60065b | 1956 | #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ |
kadonotakashi | 0:8fdf9a60065b | 1957 | region.domain = 0x0; \ |
kadonotakashi | 0:8fdf9a60065b | 1958 | region.e_t = ECC_DISABLED; \ |
kadonotakashi | 0:8fdf9a60065b | 1959 | region.g_t = GLOBAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1960 | region.inner_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 1961 | region.outer_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 1962 | region.mem_t = STRONGLY_ORDERED; \ |
kadonotakashi | 0:8fdf9a60065b | 1963 | region.sec_t = SECURE; \ |
kadonotakashi | 0:8fdf9a60065b | 1964 | region.xn_t = NON_EXECUTE; \ |
kadonotakashi | 0:8fdf9a60065b | 1965 | region.priv_t = READ; \ |
kadonotakashi | 0:8fdf9a60065b | 1966 | region.user_t = READ; \ |
kadonotakashi | 0:8fdf9a60065b | 1967 | region.sh_t = NON_SHARED; \ |
kadonotakashi | 0:8fdf9a60065b | 1968 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
kadonotakashi | 0:8fdf9a60065b | 1969 | |
kadonotakashi | 0:8fdf9a60065b | 1970 | //Sect_Device_RW. Sect_Device_RO, but writeable |
kadonotakashi | 0:8fdf9a60065b | 1971 | #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ |
kadonotakashi | 0:8fdf9a60065b | 1972 | region.domain = 0x0; \ |
kadonotakashi | 0:8fdf9a60065b | 1973 | region.e_t = ECC_DISABLED; \ |
kadonotakashi | 0:8fdf9a60065b | 1974 | region.g_t = GLOBAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1975 | region.inner_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 1976 | region.outer_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 1977 | region.mem_t = STRONGLY_ORDERED; \ |
kadonotakashi | 0:8fdf9a60065b | 1978 | region.sec_t = SECURE; \ |
kadonotakashi | 0:8fdf9a60065b | 1979 | region.xn_t = NON_EXECUTE; \ |
kadonotakashi | 0:8fdf9a60065b | 1980 | region.priv_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1981 | region.user_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1982 | region.sh_t = NON_SHARED; \ |
kadonotakashi | 0:8fdf9a60065b | 1983 | MMU_GetSectionDescriptor(&descriptor_l1, region); |
kadonotakashi | 0:8fdf9a60065b | 1984 | //Page_4k_Device_RW. Shared device, not executable, rw, domain 0 |
kadonotakashi | 0:8fdf9a60065b | 1985 | #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ |
kadonotakashi | 0:8fdf9a60065b | 1986 | region.domain = 0x0; \ |
kadonotakashi | 0:8fdf9a60065b | 1987 | region.e_t = ECC_DISABLED; \ |
kadonotakashi | 0:8fdf9a60065b | 1988 | region.g_t = GLOBAL; \ |
kadonotakashi | 0:8fdf9a60065b | 1989 | region.inner_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 1990 | region.outer_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 1991 | region.mem_t = SHARED_DEVICE; \ |
kadonotakashi | 0:8fdf9a60065b | 1992 | region.sec_t = SECURE; \ |
kadonotakashi | 0:8fdf9a60065b | 1993 | region.xn_t = NON_EXECUTE; \ |
kadonotakashi | 0:8fdf9a60065b | 1994 | region.priv_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1995 | region.user_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 1996 | region.sh_t = NON_SHARED; \ |
kadonotakashi | 0:8fdf9a60065b | 1997 | MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); |
kadonotakashi | 0:8fdf9a60065b | 1998 | |
kadonotakashi | 0:8fdf9a60065b | 1999 | //Page_64k_Device_RW. Shared device, not executable, rw, domain 0 |
kadonotakashi | 0:8fdf9a60065b | 2000 | #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ |
kadonotakashi | 0:8fdf9a60065b | 2001 | region.domain = 0x0; \ |
kadonotakashi | 0:8fdf9a60065b | 2002 | region.e_t = ECC_DISABLED; \ |
kadonotakashi | 0:8fdf9a60065b | 2003 | region.g_t = GLOBAL; \ |
kadonotakashi | 0:8fdf9a60065b | 2004 | region.inner_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 2005 | region.outer_norm_t = NON_CACHEABLE; \ |
kadonotakashi | 0:8fdf9a60065b | 2006 | region.mem_t = SHARED_DEVICE; \ |
kadonotakashi | 0:8fdf9a60065b | 2007 | region.sec_t = SECURE; \ |
kadonotakashi | 0:8fdf9a60065b | 2008 | region.xn_t = NON_EXECUTE; \ |
kadonotakashi | 0:8fdf9a60065b | 2009 | region.priv_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 2010 | region.user_t = RW; \ |
kadonotakashi | 0:8fdf9a60065b | 2011 | region.sh_t = NON_SHARED; \ |
kadonotakashi | 0:8fdf9a60065b | 2012 | MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); |
kadonotakashi | 0:8fdf9a60065b | 2013 | |
kadonotakashi | 0:8fdf9a60065b | 2014 | /** \brief Set section execution-never attribute |
kadonotakashi | 0:8fdf9a60065b | 2015 | |
kadonotakashi | 0:8fdf9a60065b | 2016 | \param [out] descriptor_l1 L1 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2017 | \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. |
kadonotakashi | 0:8fdf9a60065b | 2018 | |
kadonotakashi | 0:8fdf9a60065b | 2019 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2020 | */ |
kadonotakashi | 0:8fdf9a60065b | 2021 | __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) |
kadonotakashi | 0:8fdf9a60065b | 2022 | { |
kadonotakashi | 0:8fdf9a60065b | 2023 | *descriptor_l1 &= SECTION_XN_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2024 | *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2025 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2026 | } |
kadonotakashi | 0:8fdf9a60065b | 2027 | |
kadonotakashi | 0:8fdf9a60065b | 2028 | /** \brief Set section domain |
kadonotakashi | 0:8fdf9a60065b | 2029 | |
kadonotakashi | 0:8fdf9a60065b | 2030 | \param [out] descriptor_l1 L1 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2031 | \param [in] domain Section domain |
kadonotakashi | 0:8fdf9a60065b | 2032 | |
kadonotakashi | 0:8fdf9a60065b | 2033 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2034 | */ |
kadonotakashi | 0:8fdf9a60065b | 2035 | __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) |
kadonotakashi | 0:8fdf9a60065b | 2036 | { |
kadonotakashi | 0:8fdf9a60065b | 2037 | *descriptor_l1 &= SECTION_DOMAIN_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2038 | *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2039 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2040 | } |
kadonotakashi | 0:8fdf9a60065b | 2041 | |
kadonotakashi | 0:8fdf9a60065b | 2042 | /** \brief Set section parity check |
kadonotakashi | 0:8fdf9a60065b | 2043 | |
kadonotakashi | 0:8fdf9a60065b | 2044 | \param [out] descriptor_l1 L1 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2045 | \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED |
kadonotakashi | 0:8fdf9a60065b | 2046 | |
kadonotakashi | 0:8fdf9a60065b | 2047 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2048 | */ |
kadonotakashi | 0:8fdf9a60065b | 2049 | __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) |
kadonotakashi | 0:8fdf9a60065b | 2050 | { |
kadonotakashi | 0:8fdf9a60065b | 2051 | *descriptor_l1 &= SECTION_P_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2052 | *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2053 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2054 | } |
kadonotakashi | 0:8fdf9a60065b | 2055 | |
kadonotakashi | 0:8fdf9a60065b | 2056 | /** \brief Set section access privileges |
kadonotakashi | 0:8fdf9a60065b | 2057 | |
kadonotakashi | 0:8fdf9a60065b | 2058 | \param [out] descriptor_l1 L1 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2059 | \param [in] user User Level Access: NO_ACCESS, RW, READ |
kadonotakashi | 0:8fdf9a60065b | 2060 | \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ |
kadonotakashi | 0:8fdf9a60065b | 2061 | \param [in] afe Access flag enable |
kadonotakashi | 0:8fdf9a60065b | 2062 | |
kadonotakashi | 0:8fdf9a60065b | 2063 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2064 | */ |
kadonotakashi | 0:8fdf9a60065b | 2065 | __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) |
kadonotakashi | 0:8fdf9a60065b | 2066 | { |
kadonotakashi | 0:8fdf9a60065b | 2067 | uint32_t ap = 0; |
kadonotakashi | 0:8fdf9a60065b | 2068 | |
kadonotakashi | 0:8fdf9a60065b | 2069 | if (afe == 0) { //full access |
kadonotakashi | 0:8fdf9a60065b | 2070 | if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } |
kadonotakashi | 0:8fdf9a60065b | 2071 | else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } |
kadonotakashi | 0:8fdf9a60065b | 2072 | else if ((priv == RW) && (user == READ)) { ap = 0x2; } |
kadonotakashi | 0:8fdf9a60065b | 2073 | else if ((priv == RW) && (user == RW)) { ap = 0x3; } |
kadonotakashi | 0:8fdf9a60065b | 2074 | else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } |
kadonotakashi | 0:8fdf9a60065b | 2075 | else if ((priv == READ) && (user == READ)) { ap = 0x7; } |
kadonotakashi | 0:8fdf9a60065b | 2076 | } |
kadonotakashi | 0:8fdf9a60065b | 2077 | |
kadonotakashi | 0:8fdf9a60065b | 2078 | else { //Simplified access |
kadonotakashi | 0:8fdf9a60065b | 2079 | if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } |
kadonotakashi | 0:8fdf9a60065b | 2080 | else if ((priv == RW) && (user == RW)) { ap = 0x3; } |
kadonotakashi | 0:8fdf9a60065b | 2081 | else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } |
kadonotakashi | 0:8fdf9a60065b | 2082 | else if ((priv == READ) && (user == READ)) { ap = 0x7; } |
kadonotakashi | 0:8fdf9a60065b | 2083 | } |
kadonotakashi | 0:8fdf9a60065b | 2084 | |
kadonotakashi | 0:8fdf9a60065b | 2085 | *descriptor_l1 &= SECTION_AP_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2086 | *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; |
kadonotakashi | 0:8fdf9a60065b | 2087 | *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; |
kadonotakashi | 0:8fdf9a60065b | 2088 | |
kadonotakashi | 0:8fdf9a60065b | 2089 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2090 | } |
kadonotakashi | 0:8fdf9a60065b | 2091 | |
kadonotakashi | 0:8fdf9a60065b | 2092 | /** \brief Set section shareability |
kadonotakashi | 0:8fdf9a60065b | 2093 | |
kadonotakashi | 0:8fdf9a60065b | 2094 | \param [out] descriptor_l1 L1 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2095 | \param [in] s_bit Section shareability: NON_SHARED, SHARED |
kadonotakashi | 0:8fdf9a60065b | 2096 | |
kadonotakashi | 0:8fdf9a60065b | 2097 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2098 | */ |
kadonotakashi | 0:8fdf9a60065b | 2099 | __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) |
kadonotakashi | 0:8fdf9a60065b | 2100 | { |
kadonotakashi | 0:8fdf9a60065b | 2101 | *descriptor_l1 &= SECTION_S_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2102 | *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2103 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2104 | } |
kadonotakashi | 0:8fdf9a60065b | 2105 | |
kadonotakashi | 0:8fdf9a60065b | 2106 | /** \brief Set section Global attribute |
kadonotakashi | 0:8fdf9a60065b | 2107 | |
kadonotakashi | 0:8fdf9a60065b | 2108 | \param [out] descriptor_l1 L1 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2109 | \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL |
kadonotakashi | 0:8fdf9a60065b | 2110 | |
kadonotakashi | 0:8fdf9a60065b | 2111 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2112 | */ |
kadonotakashi | 0:8fdf9a60065b | 2113 | __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) |
kadonotakashi | 0:8fdf9a60065b | 2114 | { |
kadonotakashi | 0:8fdf9a60065b | 2115 | *descriptor_l1 &= SECTION_NG_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2116 | *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2117 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2118 | } |
kadonotakashi | 0:8fdf9a60065b | 2119 | |
kadonotakashi | 0:8fdf9a60065b | 2120 | /** \brief Set section Security attribute |
kadonotakashi | 0:8fdf9a60065b | 2121 | |
kadonotakashi | 0:8fdf9a60065b | 2122 | \param [out] descriptor_l1 L1 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2123 | \param [in] s_bit Section Security attribute: SECURE, NON_SECURE |
kadonotakashi | 0:8fdf9a60065b | 2124 | |
kadonotakashi | 0:8fdf9a60065b | 2125 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2126 | */ |
kadonotakashi | 0:8fdf9a60065b | 2127 | __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) |
kadonotakashi | 0:8fdf9a60065b | 2128 | { |
kadonotakashi | 0:8fdf9a60065b | 2129 | *descriptor_l1 &= SECTION_NS_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2130 | *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2131 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2132 | } |
kadonotakashi | 0:8fdf9a60065b | 2133 | |
kadonotakashi | 0:8fdf9a60065b | 2134 | /* Page 4k or 64k */ |
kadonotakashi | 0:8fdf9a60065b | 2135 | /** \brief Set 4k/64k page execution-never attribute |
kadonotakashi | 0:8fdf9a60065b | 2136 | |
kadonotakashi | 0:8fdf9a60065b | 2137 | \param [out] descriptor_l2 L2 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2138 | \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. |
kadonotakashi | 0:8fdf9a60065b | 2139 | \param [in] page Page size: PAGE_4k, PAGE_64k, |
kadonotakashi | 0:8fdf9a60065b | 2140 | |
kadonotakashi | 0:8fdf9a60065b | 2141 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2142 | */ |
kadonotakashi | 0:8fdf9a60065b | 2143 | __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) |
kadonotakashi | 0:8fdf9a60065b | 2144 | { |
kadonotakashi | 0:8fdf9a60065b | 2145 | if (page == PAGE_4k) |
kadonotakashi | 0:8fdf9a60065b | 2146 | { |
kadonotakashi | 0:8fdf9a60065b | 2147 | *descriptor_l2 &= PAGE_XN_4K_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2148 | *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2149 | } |
kadonotakashi | 0:8fdf9a60065b | 2150 | else |
kadonotakashi | 0:8fdf9a60065b | 2151 | { |
kadonotakashi | 0:8fdf9a60065b | 2152 | *descriptor_l2 &= PAGE_XN_64K_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2153 | *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2154 | } |
kadonotakashi | 0:8fdf9a60065b | 2155 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2156 | } |
kadonotakashi | 0:8fdf9a60065b | 2157 | |
kadonotakashi | 0:8fdf9a60065b | 2158 | /** \brief Set 4k/64k page domain |
kadonotakashi | 0:8fdf9a60065b | 2159 | |
kadonotakashi | 0:8fdf9a60065b | 2160 | \param [out] descriptor_l1 L1 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2161 | \param [in] domain Page domain |
kadonotakashi | 0:8fdf9a60065b | 2162 | |
kadonotakashi | 0:8fdf9a60065b | 2163 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2164 | */ |
kadonotakashi | 0:8fdf9a60065b | 2165 | __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) |
kadonotakashi | 0:8fdf9a60065b | 2166 | { |
kadonotakashi | 0:8fdf9a60065b | 2167 | *descriptor_l1 &= PAGE_DOMAIN_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2168 | *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2169 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2170 | } |
kadonotakashi | 0:8fdf9a60065b | 2171 | |
kadonotakashi | 0:8fdf9a60065b | 2172 | /** \brief Set 4k/64k page parity check |
kadonotakashi | 0:8fdf9a60065b | 2173 | |
kadonotakashi | 0:8fdf9a60065b | 2174 | \param [out] descriptor_l1 L1 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2175 | \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED |
kadonotakashi | 0:8fdf9a60065b | 2176 | |
kadonotakashi | 0:8fdf9a60065b | 2177 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2178 | */ |
kadonotakashi | 0:8fdf9a60065b | 2179 | __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) |
kadonotakashi | 0:8fdf9a60065b | 2180 | { |
kadonotakashi | 0:8fdf9a60065b | 2181 | *descriptor_l1 &= SECTION_P_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2182 | *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2183 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2184 | } |
kadonotakashi | 0:8fdf9a60065b | 2185 | |
kadonotakashi | 0:8fdf9a60065b | 2186 | /** \brief Set 4k/64k page access privileges |
kadonotakashi | 0:8fdf9a60065b | 2187 | |
kadonotakashi | 0:8fdf9a60065b | 2188 | \param [out] descriptor_l2 L2 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2189 | \param [in] user User Level Access: NO_ACCESS, RW, READ |
kadonotakashi | 0:8fdf9a60065b | 2190 | \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ |
kadonotakashi | 0:8fdf9a60065b | 2191 | \param [in] afe Access flag enable |
kadonotakashi | 0:8fdf9a60065b | 2192 | |
kadonotakashi | 0:8fdf9a60065b | 2193 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2194 | */ |
kadonotakashi | 0:8fdf9a60065b | 2195 | __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) |
kadonotakashi | 0:8fdf9a60065b | 2196 | { |
kadonotakashi | 0:8fdf9a60065b | 2197 | uint32_t ap = 0; |
kadonotakashi | 0:8fdf9a60065b | 2198 | |
kadonotakashi | 0:8fdf9a60065b | 2199 | if (afe == 0) { //full access |
kadonotakashi | 0:8fdf9a60065b | 2200 | if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } |
kadonotakashi | 0:8fdf9a60065b | 2201 | else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } |
kadonotakashi | 0:8fdf9a60065b | 2202 | else if ((priv == RW) && (user == READ)) { ap = 0x2; } |
kadonotakashi | 0:8fdf9a60065b | 2203 | else if ((priv == RW) && (user == RW)) { ap = 0x3; } |
kadonotakashi | 0:8fdf9a60065b | 2204 | else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } |
kadonotakashi | 0:8fdf9a60065b | 2205 | else if ((priv == READ) && (user == READ)) { ap = 0x6; } |
kadonotakashi | 0:8fdf9a60065b | 2206 | } |
kadonotakashi | 0:8fdf9a60065b | 2207 | |
kadonotakashi | 0:8fdf9a60065b | 2208 | else { //Simplified access |
kadonotakashi | 0:8fdf9a60065b | 2209 | if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } |
kadonotakashi | 0:8fdf9a60065b | 2210 | else if ((priv == RW) && (user == RW)) { ap = 0x3; } |
kadonotakashi | 0:8fdf9a60065b | 2211 | else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } |
kadonotakashi | 0:8fdf9a60065b | 2212 | else if ((priv == READ) && (user == READ)) { ap = 0x7; } |
kadonotakashi | 0:8fdf9a60065b | 2213 | } |
kadonotakashi | 0:8fdf9a60065b | 2214 | |
kadonotakashi | 0:8fdf9a60065b | 2215 | *descriptor_l2 &= PAGE_AP_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2216 | *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; |
kadonotakashi | 0:8fdf9a60065b | 2217 | *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; |
kadonotakashi | 0:8fdf9a60065b | 2218 | |
kadonotakashi | 0:8fdf9a60065b | 2219 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2220 | } |
kadonotakashi | 0:8fdf9a60065b | 2221 | |
kadonotakashi | 0:8fdf9a60065b | 2222 | /** \brief Set 4k/64k page shareability |
kadonotakashi | 0:8fdf9a60065b | 2223 | |
kadonotakashi | 0:8fdf9a60065b | 2224 | \param [out] descriptor_l2 L2 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2225 | \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED |
kadonotakashi | 0:8fdf9a60065b | 2226 | |
kadonotakashi | 0:8fdf9a60065b | 2227 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2228 | */ |
kadonotakashi | 0:8fdf9a60065b | 2229 | __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) |
kadonotakashi | 0:8fdf9a60065b | 2230 | { |
kadonotakashi | 0:8fdf9a60065b | 2231 | *descriptor_l2 &= PAGE_S_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2232 | *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2233 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2234 | } |
kadonotakashi | 0:8fdf9a60065b | 2235 | |
kadonotakashi | 0:8fdf9a60065b | 2236 | /** \brief Set 4k/64k page Global attribute |
kadonotakashi | 0:8fdf9a60065b | 2237 | |
kadonotakashi | 0:8fdf9a60065b | 2238 | \param [out] descriptor_l2 L2 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2239 | \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL |
kadonotakashi | 0:8fdf9a60065b | 2240 | |
kadonotakashi | 0:8fdf9a60065b | 2241 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2242 | */ |
kadonotakashi | 0:8fdf9a60065b | 2243 | __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) |
kadonotakashi | 0:8fdf9a60065b | 2244 | { |
kadonotakashi | 0:8fdf9a60065b | 2245 | *descriptor_l2 &= PAGE_NG_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2246 | *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2247 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2248 | } |
kadonotakashi | 0:8fdf9a60065b | 2249 | |
kadonotakashi | 0:8fdf9a60065b | 2250 | /** \brief Set 4k/64k page Security attribute |
kadonotakashi | 0:8fdf9a60065b | 2251 | |
kadonotakashi | 0:8fdf9a60065b | 2252 | \param [out] descriptor_l1 L1 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2253 | \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE |
kadonotakashi | 0:8fdf9a60065b | 2254 | |
kadonotakashi | 0:8fdf9a60065b | 2255 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2256 | */ |
kadonotakashi | 0:8fdf9a60065b | 2257 | __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) |
kadonotakashi | 0:8fdf9a60065b | 2258 | { |
kadonotakashi | 0:8fdf9a60065b | 2259 | *descriptor_l1 &= PAGE_NS_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2260 | *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2261 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2262 | } |
kadonotakashi | 0:8fdf9a60065b | 2263 | |
kadonotakashi | 0:8fdf9a60065b | 2264 | /** \brief Set Section memory attributes |
kadonotakashi | 0:8fdf9a60065b | 2265 | |
kadonotakashi | 0:8fdf9a60065b | 2266 | \param [out] descriptor_l1 L1 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2267 | \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED |
kadonotakashi | 0:8fdf9a60065b | 2268 | \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, |
kadonotakashi | 0:8fdf9a60065b | 2269 | \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, |
kadonotakashi | 0:8fdf9a60065b | 2270 | |
kadonotakashi | 0:8fdf9a60065b | 2271 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2272 | */ |
kadonotakashi | 0:8fdf9a60065b | 2273 | __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) |
kadonotakashi | 0:8fdf9a60065b | 2274 | { |
kadonotakashi | 0:8fdf9a60065b | 2275 | *descriptor_l1 &= SECTION_TEXCB_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2276 | |
kadonotakashi | 0:8fdf9a60065b | 2277 | if (STRONGLY_ORDERED == mem) |
kadonotakashi | 0:8fdf9a60065b | 2278 | { |
kadonotakashi | 0:8fdf9a60065b | 2279 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2280 | } |
kadonotakashi | 0:8fdf9a60065b | 2281 | else if (SHARED_DEVICE == mem) |
kadonotakashi | 0:8fdf9a60065b | 2282 | { |
kadonotakashi | 0:8fdf9a60065b | 2283 | *descriptor_l1 |= (1 << SECTION_B_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2284 | } |
kadonotakashi | 0:8fdf9a60065b | 2285 | else if (NON_SHARED_DEVICE == mem) |
kadonotakashi | 0:8fdf9a60065b | 2286 | { |
kadonotakashi | 0:8fdf9a60065b | 2287 | *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2288 | } |
kadonotakashi | 0:8fdf9a60065b | 2289 | else if (NORMAL == mem) |
kadonotakashi | 0:8fdf9a60065b | 2290 | { |
kadonotakashi | 0:8fdf9a60065b | 2291 | *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; |
kadonotakashi | 0:8fdf9a60065b | 2292 | switch(inner) |
kadonotakashi | 0:8fdf9a60065b | 2293 | { |
kadonotakashi | 0:8fdf9a60065b | 2294 | case NON_CACHEABLE: |
kadonotakashi | 0:8fdf9a60065b | 2295 | break; |
kadonotakashi | 0:8fdf9a60065b | 2296 | case WB_WA: |
kadonotakashi | 0:8fdf9a60065b | 2297 | *descriptor_l1 |= (1 << SECTION_B_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2298 | break; |
kadonotakashi | 0:8fdf9a60065b | 2299 | case WT: |
kadonotakashi | 0:8fdf9a60065b | 2300 | *descriptor_l1 |= 1 << SECTION_C_SHIFT; |
kadonotakashi | 0:8fdf9a60065b | 2301 | break; |
kadonotakashi | 0:8fdf9a60065b | 2302 | case WB_NO_WA: |
kadonotakashi | 0:8fdf9a60065b | 2303 | *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2304 | break; |
kadonotakashi | 0:8fdf9a60065b | 2305 | } |
kadonotakashi | 0:8fdf9a60065b | 2306 | switch(outer) |
kadonotakashi | 0:8fdf9a60065b | 2307 | { |
kadonotakashi | 0:8fdf9a60065b | 2308 | case NON_CACHEABLE: |
kadonotakashi | 0:8fdf9a60065b | 2309 | break; |
kadonotakashi | 0:8fdf9a60065b | 2310 | case WB_WA: |
kadonotakashi | 0:8fdf9a60065b | 2311 | *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2312 | break; |
kadonotakashi | 0:8fdf9a60065b | 2313 | case WT: |
kadonotakashi | 0:8fdf9a60065b | 2314 | *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; |
kadonotakashi | 0:8fdf9a60065b | 2315 | break; |
kadonotakashi | 0:8fdf9a60065b | 2316 | case WB_NO_WA: |
kadonotakashi | 0:8fdf9a60065b | 2317 | *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2318 | break; |
kadonotakashi | 0:8fdf9a60065b | 2319 | } |
kadonotakashi | 0:8fdf9a60065b | 2320 | } |
kadonotakashi | 0:8fdf9a60065b | 2321 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2322 | } |
kadonotakashi | 0:8fdf9a60065b | 2323 | |
kadonotakashi | 0:8fdf9a60065b | 2324 | /** \brief Set 4k/64k page memory attributes |
kadonotakashi | 0:8fdf9a60065b | 2325 | |
kadonotakashi | 0:8fdf9a60065b | 2326 | \param [out] descriptor_l2 L2 descriptor. |
kadonotakashi | 0:8fdf9a60065b | 2327 | \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED |
kadonotakashi | 0:8fdf9a60065b | 2328 | \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, |
kadonotakashi | 0:8fdf9a60065b | 2329 | \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, |
kadonotakashi | 0:8fdf9a60065b | 2330 | \param [in] page Page size |
kadonotakashi | 0:8fdf9a60065b | 2331 | |
kadonotakashi | 0:8fdf9a60065b | 2332 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2333 | */ |
kadonotakashi | 0:8fdf9a60065b | 2334 | __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) |
kadonotakashi | 0:8fdf9a60065b | 2335 | { |
kadonotakashi | 0:8fdf9a60065b | 2336 | *descriptor_l2 &= PAGE_4K_TEXCB_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2337 | |
kadonotakashi | 0:8fdf9a60065b | 2338 | if (page == PAGE_64k) |
kadonotakashi | 0:8fdf9a60065b | 2339 | { |
kadonotakashi | 0:8fdf9a60065b | 2340 | //same as section |
kadonotakashi | 0:8fdf9a60065b | 2341 | MMU_MemorySection(descriptor_l2, mem, outer, inner); |
kadonotakashi | 0:8fdf9a60065b | 2342 | } |
kadonotakashi | 0:8fdf9a60065b | 2343 | else |
kadonotakashi | 0:8fdf9a60065b | 2344 | { |
kadonotakashi | 0:8fdf9a60065b | 2345 | if (STRONGLY_ORDERED == mem) |
kadonotakashi | 0:8fdf9a60065b | 2346 | { |
kadonotakashi | 0:8fdf9a60065b | 2347 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2348 | } |
kadonotakashi | 0:8fdf9a60065b | 2349 | else if (SHARED_DEVICE == mem) |
kadonotakashi | 0:8fdf9a60065b | 2350 | { |
kadonotakashi | 0:8fdf9a60065b | 2351 | *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2352 | } |
kadonotakashi | 0:8fdf9a60065b | 2353 | else if (NON_SHARED_DEVICE == mem) |
kadonotakashi | 0:8fdf9a60065b | 2354 | { |
kadonotakashi | 0:8fdf9a60065b | 2355 | *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2356 | } |
kadonotakashi | 0:8fdf9a60065b | 2357 | else if (NORMAL == mem) |
kadonotakashi | 0:8fdf9a60065b | 2358 | { |
kadonotakashi | 0:8fdf9a60065b | 2359 | *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; |
kadonotakashi | 0:8fdf9a60065b | 2360 | switch(inner) |
kadonotakashi | 0:8fdf9a60065b | 2361 | { |
kadonotakashi | 0:8fdf9a60065b | 2362 | case NON_CACHEABLE: |
kadonotakashi | 0:8fdf9a60065b | 2363 | break; |
kadonotakashi | 0:8fdf9a60065b | 2364 | case WB_WA: |
kadonotakashi | 0:8fdf9a60065b | 2365 | *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2366 | break; |
kadonotakashi | 0:8fdf9a60065b | 2367 | case WT: |
kadonotakashi | 0:8fdf9a60065b | 2368 | *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; |
kadonotakashi | 0:8fdf9a60065b | 2369 | break; |
kadonotakashi | 0:8fdf9a60065b | 2370 | case WB_NO_WA: |
kadonotakashi | 0:8fdf9a60065b | 2371 | *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2372 | break; |
kadonotakashi | 0:8fdf9a60065b | 2373 | } |
kadonotakashi | 0:8fdf9a60065b | 2374 | switch(outer) |
kadonotakashi | 0:8fdf9a60065b | 2375 | { |
kadonotakashi | 0:8fdf9a60065b | 2376 | case NON_CACHEABLE: |
kadonotakashi | 0:8fdf9a60065b | 2377 | break; |
kadonotakashi | 0:8fdf9a60065b | 2378 | case WB_WA: |
kadonotakashi | 0:8fdf9a60065b | 2379 | *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2380 | break; |
kadonotakashi | 0:8fdf9a60065b | 2381 | case WT: |
kadonotakashi | 0:8fdf9a60065b | 2382 | *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; |
kadonotakashi | 0:8fdf9a60065b | 2383 | break; |
kadonotakashi | 0:8fdf9a60065b | 2384 | case WB_NO_WA: |
kadonotakashi | 0:8fdf9a60065b | 2385 | *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 2386 | break; |
kadonotakashi | 0:8fdf9a60065b | 2387 | } |
kadonotakashi | 0:8fdf9a60065b | 2388 | } |
kadonotakashi | 0:8fdf9a60065b | 2389 | } |
kadonotakashi | 0:8fdf9a60065b | 2390 | |
kadonotakashi | 0:8fdf9a60065b | 2391 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2392 | } |
kadonotakashi | 0:8fdf9a60065b | 2393 | |
kadonotakashi | 0:8fdf9a60065b | 2394 | /** \brief Create a L1 section descriptor |
kadonotakashi | 0:8fdf9a60065b | 2395 | |
kadonotakashi | 0:8fdf9a60065b | 2396 | \param [out] descriptor L1 descriptor |
kadonotakashi | 0:8fdf9a60065b | 2397 | \param [in] reg Section attributes |
kadonotakashi | 0:8fdf9a60065b | 2398 | |
kadonotakashi | 0:8fdf9a60065b | 2399 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2400 | */ |
kadonotakashi | 0:8fdf9a60065b | 2401 | __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) |
kadonotakashi | 0:8fdf9a60065b | 2402 | { |
kadonotakashi | 0:8fdf9a60065b | 2403 | *descriptor = 0; |
kadonotakashi | 0:8fdf9a60065b | 2404 | |
kadonotakashi | 0:8fdf9a60065b | 2405 | MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); |
kadonotakashi | 0:8fdf9a60065b | 2406 | MMU_XNSection(descriptor,reg.xn_t); |
kadonotakashi | 0:8fdf9a60065b | 2407 | MMU_DomainSection(descriptor, reg.domain); |
kadonotakashi | 0:8fdf9a60065b | 2408 | MMU_PSection(descriptor, reg.e_t); |
kadonotakashi | 0:8fdf9a60065b | 2409 | MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1); |
kadonotakashi | 0:8fdf9a60065b | 2410 | MMU_SharedSection(descriptor,reg.sh_t); |
kadonotakashi | 0:8fdf9a60065b | 2411 | MMU_GlobalSection(descriptor,reg.g_t); |
kadonotakashi | 0:8fdf9a60065b | 2412 | MMU_SecureSection(descriptor,reg.sec_t); |
kadonotakashi | 0:8fdf9a60065b | 2413 | *descriptor &= SECTION_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2414 | *descriptor |= SECTION_DESCRIPTOR; |
kadonotakashi | 0:8fdf9a60065b | 2415 | |
kadonotakashi | 0:8fdf9a60065b | 2416 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2417 | } |
kadonotakashi | 0:8fdf9a60065b | 2418 | |
kadonotakashi | 0:8fdf9a60065b | 2419 | |
kadonotakashi | 0:8fdf9a60065b | 2420 | /** \brief Create a L1 and L2 4k/64k page descriptor |
kadonotakashi | 0:8fdf9a60065b | 2421 | |
kadonotakashi | 0:8fdf9a60065b | 2422 | \param [out] descriptor L1 descriptor |
kadonotakashi | 0:8fdf9a60065b | 2423 | \param [out] descriptor2 L2 descriptor |
kadonotakashi | 0:8fdf9a60065b | 2424 | \param [in] reg 4k/64k page attributes |
kadonotakashi | 0:8fdf9a60065b | 2425 | |
kadonotakashi | 0:8fdf9a60065b | 2426 | \return 0 |
kadonotakashi | 0:8fdf9a60065b | 2427 | */ |
kadonotakashi | 0:8fdf9a60065b | 2428 | __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) |
kadonotakashi | 0:8fdf9a60065b | 2429 | { |
kadonotakashi | 0:8fdf9a60065b | 2430 | *descriptor = 0; |
kadonotakashi | 0:8fdf9a60065b | 2431 | *descriptor2 = 0; |
kadonotakashi | 0:8fdf9a60065b | 2432 | |
kadonotakashi | 0:8fdf9a60065b | 2433 | switch (reg.rg_t) |
kadonotakashi | 0:8fdf9a60065b | 2434 | { |
kadonotakashi | 0:8fdf9a60065b | 2435 | case PAGE_4k: |
kadonotakashi | 0:8fdf9a60065b | 2436 | MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); |
kadonotakashi | 0:8fdf9a60065b | 2437 | MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); |
kadonotakashi | 0:8fdf9a60065b | 2438 | MMU_DomainPage(descriptor, reg.domain); |
kadonotakashi | 0:8fdf9a60065b | 2439 | MMU_PPage(descriptor, reg.e_t); |
kadonotakashi | 0:8fdf9a60065b | 2440 | MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); |
kadonotakashi | 0:8fdf9a60065b | 2441 | MMU_SharedPage(descriptor2,reg.sh_t); |
kadonotakashi | 0:8fdf9a60065b | 2442 | MMU_GlobalPage(descriptor2,reg.g_t); |
kadonotakashi | 0:8fdf9a60065b | 2443 | MMU_SecurePage(descriptor,reg.sec_t); |
kadonotakashi | 0:8fdf9a60065b | 2444 | *descriptor &= PAGE_L1_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2445 | *descriptor |= PAGE_L1_DESCRIPTOR; |
kadonotakashi | 0:8fdf9a60065b | 2446 | *descriptor2 &= PAGE_L2_4K_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2447 | *descriptor2 |= PAGE_L2_4K_DESC; |
kadonotakashi | 0:8fdf9a60065b | 2448 | break; |
kadonotakashi | 0:8fdf9a60065b | 2449 | |
kadonotakashi | 0:8fdf9a60065b | 2450 | case PAGE_64k: |
kadonotakashi | 0:8fdf9a60065b | 2451 | MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); |
kadonotakashi | 0:8fdf9a60065b | 2452 | MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); |
kadonotakashi | 0:8fdf9a60065b | 2453 | MMU_DomainPage(descriptor, reg.domain); |
kadonotakashi | 0:8fdf9a60065b | 2454 | MMU_PPage(descriptor, reg.e_t); |
kadonotakashi | 0:8fdf9a60065b | 2455 | MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); |
kadonotakashi | 0:8fdf9a60065b | 2456 | MMU_SharedPage(descriptor2,reg.sh_t); |
kadonotakashi | 0:8fdf9a60065b | 2457 | MMU_GlobalPage(descriptor2,reg.g_t); |
kadonotakashi | 0:8fdf9a60065b | 2458 | MMU_SecurePage(descriptor,reg.sec_t); |
kadonotakashi | 0:8fdf9a60065b | 2459 | *descriptor &= PAGE_L1_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2460 | *descriptor |= PAGE_L1_DESCRIPTOR; |
kadonotakashi | 0:8fdf9a60065b | 2461 | *descriptor2 &= PAGE_L2_64K_MASK; |
kadonotakashi | 0:8fdf9a60065b | 2462 | *descriptor2 |= PAGE_L2_64K_DESC; |
kadonotakashi | 0:8fdf9a60065b | 2463 | break; |
kadonotakashi | 0:8fdf9a60065b | 2464 | |
kadonotakashi | 0:8fdf9a60065b | 2465 | case SECTION: |
kadonotakashi | 0:8fdf9a60065b | 2466 | //error |
kadonotakashi | 0:8fdf9a60065b | 2467 | break; |
kadonotakashi | 0:8fdf9a60065b | 2468 | } |
kadonotakashi | 0:8fdf9a60065b | 2469 | |
kadonotakashi | 0:8fdf9a60065b | 2470 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 2471 | } |
kadonotakashi | 0:8fdf9a60065b | 2472 | |
kadonotakashi | 0:8fdf9a60065b | 2473 | /** \brief Create a 1MB Section |
kadonotakashi | 0:8fdf9a60065b | 2474 | |
kadonotakashi | 0:8fdf9a60065b | 2475 | \param [in] ttb Translation table base address |
kadonotakashi | 0:8fdf9a60065b | 2476 | \param [in] base_address Section base address |
kadonotakashi | 0:8fdf9a60065b | 2477 | \param [in] count Number of sections to create |
kadonotakashi | 0:8fdf9a60065b | 2478 | \param [in] descriptor_l1 L1 descriptor (region attributes) |
kadonotakashi | 0:8fdf9a60065b | 2479 | |
kadonotakashi | 0:8fdf9a60065b | 2480 | */ |
kadonotakashi | 0:8fdf9a60065b | 2481 | __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) |
kadonotakashi | 0:8fdf9a60065b | 2482 | { |
kadonotakashi | 0:8fdf9a60065b | 2483 | uint32_t offset; |
kadonotakashi | 0:8fdf9a60065b | 2484 | uint32_t entry; |
kadonotakashi | 0:8fdf9a60065b | 2485 | uint32_t i; |
kadonotakashi | 0:8fdf9a60065b | 2486 | |
kadonotakashi | 0:8fdf9a60065b | 2487 | offset = base_address >> 20; |
kadonotakashi | 0:8fdf9a60065b | 2488 | entry = (base_address & 0xFFF00000) | descriptor_l1; |
kadonotakashi | 0:8fdf9a60065b | 2489 | |
kadonotakashi | 0:8fdf9a60065b | 2490 | //4 bytes aligned |
kadonotakashi | 0:8fdf9a60065b | 2491 | ttb = ttb + offset; |
kadonotakashi | 0:8fdf9a60065b | 2492 | |
kadonotakashi | 0:8fdf9a60065b | 2493 | for (i = 0; i < count; i++ ) |
kadonotakashi | 0:8fdf9a60065b | 2494 | { |
kadonotakashi | 0:8fdf9a60065b | 2495 | //4 bytes aligned |
kadonotakashi | 0:8fdf9a60065b | 2496 | *ttb++ = entry; |
kadonotakashi | 0:8fdf9a60065b | 2497 | entry += OFFSET_1M; |
kadonotakashi | 0:8fdf9a60065b | 2498 | } |
kadonotakashi | 0:8fdf9a60065b | 2499 | } |
kadonotakashi | 0:8fdf9a60065b | 2500 | |
kadonotakashi | 0:8fdf9a60065b | 2501 | /** \brief Create a 4k page entry |
kadonotakashi | 0:8fdf9a60065b | 2502 | |
kadonotakashi | 0:8fdf9a60065b | 2503 | \param [in] ttb L1 table base address |
kadonotakashi | 0:8fdf9a60065b | 2504 | \param [in] base_address 4k base address |
kadonotakashi | 0:8fdf9a60065b | 2505 | \param [in] count Number of 4k pages to create |
kadonotakashi | 0:8fdf9a60065b | 2506 | \param [in] descriptor_l1 L1 descriptor (region attributes) |
kadonotakashi | 0:8fdf9a60065b | 2507 | \param [in] ttb_l2 L2 table base address |
kadonotakashi | 0:8fdf9a60065b | 2508 | \param [in] descriptor_l2 L2 descriptor (region attributes) |
kadonotakashi | 0:8fdf9a60065b | 2509 | |
kadonotakashi | 0:8fdf9a60065b | 2510 | */ |
kadonotakashi | 0:8fdf9a60065b | 2511 | __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) |
kadonotakashi | 0:8fdf9a60065b | 2512 | { |
kadonotakashi | 0:8fdf9a60065b | 2513 | |
kadonotakashi | 0:8fdf9a60065b | 2514 | uint32_t offset, offset2; |
kadonotakashi | 0:8fdf9a60065b | 2515 | uint32_t entry, entry2; |
kadonotakashi | 0:8fdf9a60065b | 2516 | uint32_t i; |
kadonotakashi | 0:8fdf9a60065b | 2517 | |
kadonotakashi | 0:8fdf9a60065b | 2518 | offset = base_address >> 20; |
kadonotakashi | 0:8fdf9a60065b | 2519 | entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; |
kadonotakashi | 0:8fdf9a60065b | 2520 | |
kadonotakashi | 0:8fdf9a60065b | 2521 | //4 bytes aligned |
kadonotakashi | 0:8fdf9a60065b | 2522 | ttb += offset; |
kadonotakashi | 0:8fdf9a60065b | 2523 | //create l1_entry |
kadonotakashi | 0:8fdf9a60065b | 2524 | *ttb = entry; |
kadonotakashi | 0:8fdf9a60065b | 2525 | |
kadonotakashi | 0:8fdf9a60065b | 2526 | offset2 = (base_address & 0xff000) >> 12; |
kadonotakashi | 0:8fdf9a60065b | 2527 | ttb_l2 += offset2; |
kadonotakashi | 0:8fdf9a60065b | 2528 | entry2 = (base_address & 0xFFFFF000) | descriptor_l2; |
kadonotakashi | 0:8fdf9a60065b | 2529 | for (i = 0; i < count; i++ ) |
kadonotakashi | 0:8fdf9a60065b | 2530 | { |
kadonotakashi | 0:8fdf9a60065b | 2531 | //4 bytes aligned |
kadonotakashi | 0:8fdf9a60065b | 2532 | *ttb_l2++ = entry2; |
kadonotakashi | 0:8fdf9a60065b | 2533 | entry2 += OFFSET_4K; |
kadonotakashi | 0:8fdf9a60065b | 2534 | } |
kadonotakashi | 0:8fdf9a60065b | 2535 | } |
kadonotakashi | 0:8fdf9a60065b | 2536 | |
kadonotakashi | 0:8fdf9a60065b | 2537 | /** \brief Create a 64k page entry |
kadonotakashi | 0:8fdf9a60065b | 2538 | |
kadonotakashi | 0:8fdf9a60065b | 2539 | \param [in] ttb L1 table base address |
kadonotakashi | 0:8fdf9a60065b | 2540 | \param [in] base_address 64k base address |
kadonotakashi | 0:8fdf9a60065b | 2541 | \param [in] count Number of 64k pages to create |
kadonotakashi | 0:8fdf9a60065b | 2542 | \param [in] descriptor_l1 L1 descriptor (region attributes) |
kadonotakashi | 0:8fdf9a60065b | 2543 | \param [in] ttb_l2 L2 table base address |
kadonotakashi | 0:8fdf9a60065b | 2544 | \param [in] descriptor_l2 L2 descriptor (region attributes) |
kadonotakashi | 0:8fdf9a60065b | 2545 | |
kadonotakashi | 0:8fdf9a60065b | 2546 | */ |
kadonotakashi | 0:8fdf9a60065b | 2547 | __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) |
kadonotakashi | 0:8fdf9a60065b | 2548 | { |
kadonotakashi | 0:8fdf9a60065b | 2549 | uint32_t offset, offset2; |
kadonotakashi | 0:8fdf9a60065b | 2550 | uint32_t entry, entry2; |
kadonotakashi | 0:8fdf9a60065b | 2551 | uint32_t i,j; |
kadonotakashi | 0:8fdf9a60065b | 2552 | |
kadonotakashi | 0:8fdf9a60065b | 2553 | |
kadonotakashi | 0:8fdf9a60065b | 2554 | offset = base_address >> 20; |
kadonotakashi | 0:8fdf9a60065b | 2555 | entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; |
kadonotakashi | 0:8fdf9a60065b | 2556 | |
kadonotakashi | 0:8fdf9a60065b | 2557 | //4 bytes aligned |
kadonotakashi | 0:8fdf9a60065b | 2558 | ttb += offset; |
kadonotakashi | 0:8fdf9a60065b | 2559 | //create l1_entry |
kadonotakashi | 0:8fdf9a60065b | 2560 | *ttb = entry; |
kadonotakashi | 0:8fdf9a60065b | 2561 | |
kadonotakashi | 0:8fdf9a60065b | 2562 | offset2 = (base_address & 0xff000) >> 12; |
kadonotakashi | 0:8fdf9a60065b | 2563 | ttb_l2 += offset2; |
kadonotakashi | 0:8fdf9a60065b | 2564 | entry2 = (base_address & 0xFFFF0000) | descriptor_l2; |
kadonotakashi | 0:8fdf9a60065b | 2565 | for (i = 0; i < count; i++ ) |
kadonotakashi | 0:8fdf9a60065b | 2566 | { |
kadonotakashi | 0:8fdf9a60065b | 2567 | //create 16 entries |
kadonotakashi | 0:8fdf9a60065b | 2568 | for (j = 0; j < 16; j++) |
kadonotakashi | 0:8fdf9a60065b | 2569 | { |
kadonotakashi | 0:8fdf9a60065b | 2570 | //4 bytes aligned |
kadonotakashi | 0:8fdf9a60065b | 2571 | *ttb_l2++ = entry2; |
kadonotakashi | 0:8fdf9a60065b | 2572 | } |
kadonotakashi | 0:8fdf9a60065b | 2573 | entry2 += OFFSET_64K; |
kadonotakashi | 0:8fdf9a60065b | 2574 | } |
kadonotakashi | 0:8fdf9a60065b | 2575 | } |
kadonotakashi | 0:8fdf9a60065b | 2576 | |
kadonotakashi | 0:8fdf9a60065b | 2577 | /** \brief Enable MMU |
kadonotakashi | 0:8fdf9a60065b | 2578 | */ |
kadonotakashi | 0:8fdf9a60065b | 2579 | __STATIC_INLINE void MMU_Enable(void) |
kadonotakashi | 0:8fdf9a60065b | 2580 | { |
kadonotakashi | 0:8fdf9a60065b | 2581 | // Set M bit 0 to enable the MMU |
kadonotakashi | 0:8fdf9a60065b | 2582 | // Set AFE bit to enable simplified access permissions model |
kadonotakashi | 0:8fdf9a60065b | 2583 | // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking |
kadonotakashi | 0:8fdf9a60065b | 2584 | __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); |
kadonotakashi | 0:8fdf9a60065b | 2585 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 2586 | } |
kadonotakashi | 0:8fdf9a60065b | 2587 | |
kadonotakashi | 0:8fdf9a60065b | 2588 | /** \brief Disable MMU |
kadonotakashi | 0:8fdf9a60065b | 2589 | */ |
kadonotakashi | 0:8fdf9a60065b | 2590 | __STATIC_INLINE void MMU_Disable(void) |
kadonotakashi | 0:8fdf9a60065b | 2591 | { |
kadonotakashi | 0:8fdf9a60065b | 2592 | // Clear M bit 0 to disable the MMU |
kadonotakashi | 0:8fdf9a60065b | 2593 | __set_SCTLR( __get_SCTLR() & ~1); |
kadonotakashi | 0:8fdf9a60065b | 2594 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 2595 | } |
kadonotakashi | 0:8fdf9a60065b | 2596 | |
kadonotakashi | 0:8fdf9a60065b | 2597 | /** \brief Invalidate entire unified TLB |
kadonotakashi | 0:8fdf9a60065b | 2598 | */ |
kadonotakashi | 0:8fdf9a60065b | 2599 | |
kadonotakashi | 0:8fdf9a60065b | 2600 | __STATIC_INLINE void MMU_InvalidateTLB(void) |
kadonotakashi | 0:8fdf9a60065b | 2601 | { |
kadonotakashi | 0:8fdf9a60065b | 2602 | __set_TLBIALL(0); |
kadonotakashi | 0:8fdf9a60065b | 2603 | __DSB(); //ensure completion of the invalidation |
kadonotakashi | 0:8fdf9a60065b | 2604 | __ISB(); //ensure instruction fetch path sees new state |
kadonotakashi | 0:8fdf9a60065b | 2605 | } |
kadonotakashi | 0:8fdf9a60065b | 2606 | |
kadonotakashi | 0:8fdf9a60065b | 2607 | |
kadonotakashi | 0:8fdf9a60065b | 2608 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 2609 | } |
kadonotakashi | 0:8fdf9a60065b | 2610 | #endif |
kadonotakashi | 0:8fdf9a60065b | 2611 | |
kadonotakashi | 0:8fdf9a60065b | 2612 | #endif /* __CORE_CA_H_DEPENDANT */ |
kadonotakashi | 0:8fdf9a60065b | 2613 | |
kadonotakashi | 0:8fdf9a60065b | 2614 | #endif /* __CMSIS_GENERIC */ |