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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/cmsis/TARGET_CORTEX_A/cmsis_armcc.h@3:f3764f852aa8, 2018-10-11 (annotated)
- Committer:
- kadonotakashi
- Date:
- Thu Oct 11 02:27:46 2018 +0000
- Revision:
- 3:f3764f852aa8
- Parent:
- 0:8fdf9a60065b
Nucreo 446 + SSD1331 test version;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
kadonotakashi | 0:8fdf9a60065b | 2 | * @file cmsis_armcc.h |
kadonotakashi | 0:8fdf9a60065b | 3 | * @brief CMSIS compiler specific macros, functions, instructions |
kadonotakashi | 0:8fdf9a60065b | 4 | * @version V1.0.2 |
kadonotakashi | 0:8fdf9a60065b | 5 | * @date 10. January 2018 |
kadonotakashi | 0:8fdf9a60065b | 6 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 7 | /* |
kadonotakashi | 0:8fdf9a60065b | 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 9 | * |
kadonotakashi | 0:8fdf9a60065b | 10 | * SPDX-License-Identifier: Apache-2.0 |
kadonotakashi | 0:8fdf9a60065b | 11 | * |
kadonotakashi | 0:8fdf9a60065b | 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
kadonotakashi | 0:8fdf9a60065b | 13 | * not use this file except in compliance with the License. |
kadonotakashi | 0:8fdf9a60065b | 14 | * You may obtain a copy of the License at |
kadonotakashi | 0:8fdf9a60065b | 15 | * |
kadonotakashi | 0:8fdf9a60065b | 16 | * www.apache.org/licenses/LICENSE-2.0 |
kadonotakashi | 0:8fdf9a60065b | 17 | * |
kadonotakashi | 0:8fdf9a60065b | 18 | * Unless required by applicable law or agreed to in writing, software |
kadonotakashi | 0:8fdf9a60065b | 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
kadonotakashi | 0:8fdf9a60065b | 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
kadonotakashi | 0:8fdf9a60065b | 21 | * See the License for the specific language governing permissions and |
kadonotakashi | 0:8fdf9a60065b | 22 | * limitations under the License. |
kadonotakashi | 0:8fdf9a60065b | 23 | */ |
kadonotakashi | 0:8fdf9a60065b | 24 | |
kadonotakashi | 0:8fdf9a60065b | 25 | #ifndef __CMSIS_ARMCC_H |
kadonotakashi | 0:8fdf9a60065b | 26 | #define __CMSIS_ARMCC_H |
kadonotakashi | 0:8fdf9a60065b | 27 | |
kadonotakashi | 0:8fdf9a60065b | 28 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) |
kadonotakashi | 0:8fdf9a60065b | 29 | #error "Please use Arm Compiler Toolchain V4.0.677 or later!" |
kadonotakashi | 0:8fdf9a60065b | 30 | #endif |
kadonotakashi | 0:8fdf9a60065b | 31 | |
kadonotakashi | 0:8fdf9a60065b | 32 | /* CMSIS compiler control architecture macros */ |
kadonotakashi | 0:8fdf9a60065b | 33 | #if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1)) |
kadonotakashi | 0:8fdf9a60065b | 34 | #define __ARM_ARCH_7A__ 1 |
kadonotakashi | 0:8fdf9a60065b | 35 | #endif |
kadonotakashi | 0:8fdf9a60065b | 36 | |
kadonotakashi | 0:8fdf9a60065b | 37 | /* CMSIS compiler specific defines */ |
kadonotakashi | 0:8fdf9a60065b | 38 | #ifndef __ASM |
kadonotakashi | 0:8fdf9a60065b | 39 | #define __ASM __asm |
kadonotakashi | 0:8fdf9a60065b | 40 | #endif |
kadonotakashi | 0:8fdf9a60065b | 41 | #ifndef __INLINE |
kadonotakashi | 0:8fdf9a60065b | 42 | #define __INLINE __inline |
kadonotakashi | 0:8fdf9a60065b | 43 | #endif |
kadonotakashi | 0:8fdf9a60065b | 44 | #ifndef __FORCEINLINE |
kadonotakashi | 0:8fdf9a60065b | 45 | #define __FORCEINLINE __forceinline |
kadonotakashi | 0:8fdf9a60065b | 46 | #endif |
kadonotakashi | 0:8fdf9a60065b | 47 | #ifndef __STATIC_INLINE |
kadonotakashi | 0:8fdf9a60065b | 48 | #define __STATIC_INLINE static __inline |
kadonotakashi | 0:8fdf9a60065b | 49 | #endif |
kadonotakashi | 0:8fdf9a60065b | 50 | #ifndef __STATIC_FORCEINLINE |
kadonotakashi | 0:8fdf9a60065b | 51 | #define __STATIC_FORCEINLINE static __forceinline |
kadonotakashi | 0:8fdf9a60065b | 52 | #endif |
kadonotakashi | 0:8fdf9a60065b | 53 | #ifndef __NO_RETURN |
kadonotakashi | 0:8fdf9a60065b | 54 | #define __NO_RETURN __declspec(noreturn) |
kadonotakashi | 0:8fdf9a60065b | 55 | #endif |
kadonotakashi | 0:8fdf9a60065b | 56 | #ifndef CMSIS_DEPRECATED |
kadonotakashi | 0:8fdf9a60065b | 57 | #define CMSIS_DEPRECATED __attribute__((deprecated)) |
kadonotakashi | 0:8fdf9a60065b | 58 | #endif |
kadonotakashi | 0:8fdf9a60065b | 59 | #ifndef __USED |
kadonotakashi | 0:8fdf9a60065b | 60 | #define __USED __attribute__((used)) |
kadonotakashi | 0:8fdf9a60065b | 61 | #endif |
kadonotakashi | 0:8fdf9a60065b | 62 | #ifndef __WEAK |
kadonotakashi | 0:8fdf9a60065b | 63 | #define __WEAK __attribute__((weak)) |
kadonotakashi | 0:8fdf9a60065b | 64 | #endif |
kadonotakashi | 0:8fdf9a60065b | 65 | #ifndef __PACKED |
kadonotakashi | 0:8fdf9a60065b | 66 | #define __PACKED __attribute__((packed)) |
kadonotakashi | 0:8fdf9a60065b | 67 | #endif |
kadonotakashi | 0:8fdf9a60065b | 68 | #ifndef __PACKED_STRUCT |
kadonotakashi | 0:8fdf9a60065b | 69 | #define __PACKED_STRUCT __packed struct |
kadonotakashi | 0:8fdf9a60065b | 70 | #endif |
kadonotakashi | 0:8fdf9a60065b | 71 | #ifndef __UNALIGNED_UINT16_WRITE |
kadonotakashi | 0:8fdf9a60065b | 72 | #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) |
kadonotakashi | 0:8fdf9a60065b | 73 | #endif |
kadonotakashi | 0:8fdf9a60065b | 74 | #ifndef __UNALIGNED_UINT16_READ |
kadonotakashi | 0:8fdf9a60065b | 75 | #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) |
kadonotakashi | 0:8fdf9a60065b | 76 | #endif |
kadonotakashi | 0:8fdf9a60065b | 77 | #ifndef __UNALIGNED_UINT32_WRITE |
kadonotakashi | 0:8fdf9a60065b | 78 | #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) |
kadonotakashi | 0:8fdf9a60065b | 79 | #endif |
kadonotakashi | 0:8fdf9a60065b | 80 | #ifndef __UNALIGNED_UINT32_READ |
kadonotakashi | 0:8fdf9a60065b | 81 | #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) |
kadonotakashi | 0:8fdf9a60065b | 82 | #endif |
kadonotakashi | 0:8fdf9a60065b | 83 | #ifndef __ALIGNED |
kadonotakashi | 0:8fdf9a60065b | 84 | #define __ALIGNED(x) __attribute__((aligned(x))) |
kadonotakashi | 0:8fdf9a60065b | 85 | #endif |
kadonotakashi | 0:8fdf9a60065b | 86 | #ifndef __PACKED |
kadonotakashi | 0:8fdf9a60065b | 87 | #define __PACKED __attribute__((packed)) |
kadonotakashi | 0:8fdf9a60065b | 88 | #endif |
kadonotakashi | 0:8fdf9a60065b | 89 | |
kadonotakashi | 0:8fdf9a60065b | 90 | /* ########################## Core Instruction Access ######################### */ |
kadonotakashi | 0:8fdf9a60065b | 91 | /** |
kadonotakashi | 0:8fdf9a60065b | 92 | \brief No Operation |
kadonotakashi | 0:8fdf9a60065b | 93 | */ |
kadonotakashi | 0:8fdf9a60065b | 94 | #define __NOP __nop |
kadonotakashi | 0:8fdf9a60065b | 95 | |
kadonotakashi | 0:8fdf9a60065b | 96 | /** |
kadonotakashi | 0:8fdf9a60065b | 97 | \brief Wait For Interrupt |
kadonotakashi | 0:8fdf9a60065b | 98 | */ |
kadonotakashi | 0:8fdf9a60065b | 99 | #define __WFI __wfi |
kadonotakashi | 0:8fdf9a60065b | 100 | |
kadonotakashi | 0:8fdf9a60065b | 101 | /** |
kadonotakashi | 0:8fdf9a60065b | 102 | \brief Wait For Event |
kadonotakashi | 0:8fdf9a60065b | 103 | */ |
kadonotakashi | 0:8fdf9a60065b | 104 | #define __WFE __wfe |
kadonotakashi | 0:8fdf9a60065b | 105 | |
kadonotakashi | 0:8fdf9a60065b | 106 | /** |
kadonotakashi | 0:8fdf9a60065b | 107 | \brief Send Event |
kadonotakashi | 0:8fdf9a60065b | 108 | */ |
kadonotakashi | 0:8fdf9a60065b | 109 | #define __SEV __sev |
kadonotakashi | 0:8fdf9a60065b | 110 | |
kadonotakashi | 0:8fdf9a60065b | 111 | /** |
kadonotakashi | 0:8fdf9a60065b | 112 | \brief Instruction Synchronization Barrier |
kadonotakashi | 0:8fdf9a60065b | 113 | */ |
kadonotakashi | 0:8fdf9a60065b | 114 | #define __ISB() do {\ |
kadonotakashi | 0:8fdf9a60065b | 115 | __schedule_barrier();\ |
kadonotakashi | 0:8fdf9a60065b | 116 | __isb(0xF);\ |
kadonotakashi | 0:8fdf9a60065b | 117 | __schedule_barrier();\ |
kadonotakashi | 0:8fdf9a60065b | 118 | } while (0U) |
kadonotakashi | 0:8fdf9a60065b | 119 | |
kadonotakashi | 0:8fdf9a60065b | 120 | /** |
kadonotakashi | 0:8fdf9a60065b | 121 | \brief Data Synchronization Barrier |
kadonotakashi | 0:8fdf9a60065b | 122 | */ |
kadonotakashi | 0:8fdf9a60065b | 123 | #define __DSB() do {\ |
kadonotakashi | 0:8fdf9a60065b | 124 | __schedule_barrier();\ |
kadonotakashi | 0:8fdf9a60065b | 125 | __dsb(0xF);\ |
kadonotakashi | 0:8fdf9a60065b | 126 | __schedule_barrier();\ |
kadonotakashi | 0:8fdf9a60065b | 127 | } while (0U) |
kadonotakashi | 0:8fdf9a60065b | 128 | |
kadonotakashi | 0:8fdf9a60065b | 129 | /** |
kadonotakashi | 0:8fdf9a60065b | 130 | \brief Data Memory Barrier |
kadonotakashi | 0:8fdf9a60065b | 131 | */ |
kadonotakashi | 0:8fdf9a60065b | 132 | #define __DMB() do {\ |
kadonotakashi | 0:8fdf9a60065b | 133 | __schedule_barrier();\ |
kadonotakashi | 0:8fdf9a60065b | 134 | __dmb(0xF);\ |
kadonotakashi | 0:8fdf9a60065b | 135 | __schedule_barrier();\ |
kadonotakashi | 0:8fdf9a60065b | 136 | } while (0U) |
kadonotakashi | 0:8fdf9a60065b | 137 | |
kadonotakashi | 0:8fdf9a60065b | 138 | /** |
kadonotakashi | 0:8fdf9a60065b | 139 | \brief Reverse byte order (32 bit) |
kadonotakashi | 0:8fdf9a60065b | 140 | \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. |
kadonotakashi | 0:8fdf9a60065b | 141 | \param [in] value Value to reverse |
kadonotakashi | 0:8fdf9a60065b | 142 | \return Reversed value |
kadonotakashi | 0:8fdf9a60065b | 143 | */ |
kadonotakashi | 0:8fdf9a60065b | 144 | #define __REV __rev |
kadonotakashi | 0:8fdf9a60065b | 145 | |
kadonotakashi | 0:8fdf9a60065b | 146 | /** |
kadonotakashi | 0:8fdf9a60065b | 147 | \brief Reverse byte order (16 bit) |
kadonotakashi | 0:8fdf9a60065b | 148 | \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. |
kadonotakashi | 0:8fdf9a60065b | 149 | \param [in] value Value to reverse |
kadonotakashi | 0:8fdf9a60065b | 150 | \return Reversed value |
kadonotakashi | 0:8fdf9a60065b | 151 | */ |
kadonotakashi | 0:8fdf9a60065b | 152 | #ifndef __NO_EMBEDDED_ASM |
kadonotakashi | 0:8fdf9a60065b | 153 | __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) |
kadonotakashi | 0:8fdf9a60065b | 154 | { |
kadonotakashi | 0:8fdf9a60065b | 155 | rev16 r0, r0 |
kadonotakashi | 0:8fdf9a60065b | 156 | bx lr |
kadonotakashi | 0:8fdf9a60065b | 157 | } |
kadonotakashi | 0:8fdf9a60065b | 158 | #endif |
kadonotakashi | 0:8fdf9a60065b | 159 | |
kadonotakashi | 0:8fdf9a60065b | 160 | /** |
kadonotakashi | 0:8fdf9a60065b | 161 | \brief Reverse byte order (16 bit) |
kadonotakashi | 0:8fdf9a60065b | 162 | \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. |
kadonotakashi | 0:8fdf9a60065b | 163 | \param [in] value Value to reverse |
kadonotakashi | 0:8fdf9a60065b | 164 | \return Reversed value |
kadonotakashi | 0:8fdf9a60065b | 165 | */ |
kadonotakashi | 0:8fdf9a60065b | 166 | #ifndef __NO_EMBEDDED_ASM |
kadonotakashi | 0:8fdf9a60065b | 167 | __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) |
kadonotakashi | 0:8fdf9a60065b | 168 | { |
kadonotakashi | 0:8fdf9a60065b | 169 | revsh r0, r0 |
kadonotakashi | 0:8fdf9a60065b | 170 | bx lr |
kadonotakashi | 0:8fdf9a60065b | 171 | } |
kadonotakashi | 0:8fdf9a60065b | 172 | #endif |
kadonotakashi | 0:8fdf9a60065b | 173 | |
kadonotakashi | 0:8fdf9a60065b | 174 | /** |
kadonotakashi | 0:8fdf9a60065b | 175 | \brief Rotate Right in unsigned value (32 bit) |
kadonotakashi | 0:8fdf9a60065b | 176 | \param [in] op1 Value to rotate |
kadonotakashi | 0:8fdf9a60065b | 177 | \param [in] op2 Number of Bits to rotate |
kadonotakashi | 0:8fdf9a60065b | 178 | \return Rotated value |
kadonotakashi | 0:8fdf9a60065b | 179 | */ |
kadonotakashi | 0:8fdf9a60065b | 180 | #define __ROR __ror |
kadonotakashi | 0:8fdf9a60065b | 181 | |
kadonotakashi | 0:8fdf9a60065b | 182 | /** |
kadonotakashi | 0:8fdf9a60065b | 183 | \brief Breakpoint |
kadonotakashi | 0:8fdf9a60065b | 184 | \param [in] value is ignored by the processor. |
kadonotakashi | 0:8fdf9a60065b | 185 | If required, a debugger can use it to store additional information about the breakpoint. |
kadonotakashi | 0:8fdf9a60065b | 186 | */ |
kadonotakashi | 0:8fdf9a60065b | 187 | #define __BKPT(value) __breakpoint(value) |
kadonotakashi | 0:8fdf9a60065b | 188 | |
kadonotakashi | 0:8fdf9a60065b | 189 | /** |
kadonotakashi | 0:8fdf9a60065b | 190 | \brief Reverse bit order of value |
kadonotakashi | 0:8fdf9a60065b | 191 | \param [in] value Value to reverse |
kadonotakashi | 0:8fdf9a60065b | 192 | \return Reversed value |
kadonotakashi | 0:8fdf9a60065b | 193 | */ |
kadonotakashi | 0:8fdf9a60065b | 194 | #define __RBIT __rbit |
kadonotakashi | 0:8fdf9a60065b | 195 | |
kadonotakashi | 0:8fdf9a60065b | 196 | /** |
kadonotakashi | 0:8fdf9a60065b | 197 | \brief Count leading zeros |
kadonotakashi | 0:8fdf9a60065b | 198 | \param [in] value Value to count the leading zeros |
kadonotakashi | 0:8fdf9a60065b | 199 | \return number of leading zeros in value |
kadonotakashi | 0:8fdf9a60065b | 200 | */ |
kadonotakashi | 0:8fdf9a60065b | 201 | #define __CLZ __clz |
kadonotakashi | 0:8fdf9a60065b | 202 | |
kadonotakashi | 0:8fdf9a60065b | 203 | /** |
kadonotakashi | 0:8fdf9a60065b | 204 | \brief LDR Exclusive (8 bit) |
kadonotakashi | 0:8fdf9a60065b | 205 | \details Executes a exclusive LDR instruction for 8 bit value. |
kadonotakashi | 0:8fdf9a60065b | 206 | \param [in] ptr Pointer to data |
kadonotakashi | 0:8fdf9a60065b | 207 | \return value of type uint8_t at (*ptr) |
kadonotakashi | 0:8fdf9a60065b | 208 | */ |
kadonotakashi | 0:8fdf9a60065b | 209 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
kadonotakashi | 0:8fdf9a60065b | 210 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) |
kadonotakashi | 0:8fdf9a60065b | 211 | #else |
kadonotakashi | 0:8fdf9a60065b | 212 | #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") |
kadonotakashi | 0:8fdf9a60065b | 213 | #endif |
kadonotakashi | 0:8fdf9a60065b | 214 | |
kadonotakashi | 0:8fdf9a60065b | 215 | /** |
kadonotakashi | 0:8fdf9a60065b | 216 | \brief LDR Exclusive (16 bit) |
kadonotakashi | 0:8fdf9a60065b | 217 | \details Executes a exclusive LDR instruction for 16 bit values. |
kadonotakashi | 0:8fdf9a60065b | 218 | \param [in] ptr Pointer to data |
kadonotakashi | 0:8fdf9a60065b | 219 | \return value of type uint16_t at (*ptr) |
kadonotakashi | 0:8fdf9a60065b | 220 | */ |
kadonotakashi | 0:8fdf9a60065b | 221 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
kadonotakashi | 0:8fdf9a60065b | 222 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) |
kadonotakashi | 0:8fdf9a60065b | 223 | #else |
kadonotakashi | 0:8fdf9a60065b | 224 | #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") |
kadonotakashi | 0:8fdf9a60065b | 225 | #endif |
kadonotakashi | 0:8fdf9a60065b | 226 | |
kadonotakashi | 0:8fdf9a60065b | 227 | /** |
kadonotakashi | 0:8fdf9a60065b | 228 | \brief LDR Exclusive (32 bit) |
kadonotakashi | 0:8fdf9a60065b | 229 | \details Executes a exclusive LDR instruction for 32 bit values. |
kadonotakashi | 0:8fdf9a60065b | 230 | \param [in] ptr Pointer to data |
kadonotakashi | 0:8fdf9a60065b | 231 | \return value of type uint32_t at (*ptr) |
kadonotakashi | 0:8fdf9a60065b | 232 | */ |
kadonotakashi | 0:8fdf9a60065b | 233 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
kadonotakashi | 0:8fdf9a60065b | 234 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) |
kadonotakashi | 0:8fdf9a60065b | 235 | #else |
kadonotakashi | 0:8fdf9a60065b | 236 | #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") |
kadonotakashi | 0:8fdf9a60065b | 237 | #endif |
kadonotakashi | 0:8fdf9a60065b | 238 | |
kadonotakashi | 0:8fdf9a60065b | 239 | /** |
kadonotakashi | 0:8fdf9a60065b | 240 | \brief STR Exclusive (8 bit) |
kadonotakashi | 0:8fdf9a60065b | 241 | \details Executes a exclusive STR instruction for 8 bit values. |
kadonotakashi | 0:8fdf9a60065b | 242 | \param [in] value Value to store |
kadonotakashi | 0:8fdf9a60065b | 243 | \param [in] ptr Pointer to location |
kadonotakashi | 0:8fdf9a60065b | 244 | \return 0 Function succeeded |
kadonotakashi | 0:8fdf9a60065b | 245 | \return 1 Function failed |
kadonotakashi | 0:8fdf9a60065b | 246 | */ |
kadonotakashi | 0:8fdf9a60065b | 247 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
kadonotakashi | 0:8fdf9a60065b | 248 | #define __STREXB(value, ptr) __strex(value, ptr) |
kadonotakashi | 0:8fdf9a60065b | 249 | #else |
kadonotakashi | 0:8fdf9a60065b | 250 | #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
kadonotakashi | 0:8fdf9a60065b | 251 | #endif |
kadonotakashi | 0:8fdf9a60065b | 252 | |
kadonotakashi | 0:8fdf9a60065b | 253 | /** |
kadonotakashi | 0:8fdf9a60065b | 254 | \brief STR Exclusive (16 bit) |
kadonotakashi | 0:8fdf9a60065b | 255 | \details Executes a exclusive STR instruction for 16 bit values. |
kadonotakashi | 0:8fdf9a60065b | 256 | \param [in] value Value to store |
kadonotakashi | 0:8fdf9a60065b | 257 | \param [in] ptr Pointer to location |
kadonotakashi | 0:8fdf9a60065b | 258 | \return 0 Function succeeded |
kadonotakashi | 0:8fdf9a60065b | 259 | \return 1 Function failed |
kadonotakashi | 0:8fdf9a60065b | 260 | */ |
kadonotakashi | 0:8fdf9a60065b | 261 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
kadonotakashi | 0:8fdf9a60065b | 262 | #define __STREXH(value, ptr) __strex(value, ptr) |
kadonotakashi | 0:8fdf9a60065b | 263 | #else |
kadonotakashi | 0:8fdf9a60065b | 264 | #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
kadonotakashi | 0:8fdf9a60065b | 265 | #endif |
kadonotakashi | 0:8fdf9a60065b | 266 | |
kadonotakashi | 0:8fdf9a60065b | 267 | /** |
kadonotakashi | 0:8fdf9a60065b | 268 | \brief STR Exclusive (32 bit) |
kadonotakashi | 0:8fdf9a60065b | 269 | \details Executes a exclusive STR instruction for 32 bit values. |
kadonotakashi | 0:8fdf9a60065b | 270 | \param [in] value Value to store |
kadonotakashi | 0:8fdf9a60065b | 271 | \param [in] ptr Pointer to location |
kadonotakashi | 0:8fdf9a60065b | 272 | \return 0 Function succeeded |
kadonotakashi | 0:8fdf9a60065b | 273 | \return 1 Function failed |
kadonotakashi | 0:8fdf9a60065b | 274 | */ |
kadonotakashi | 0:8fdf9a60065b | 275 | #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
kadonotakashi | 0:8fdf9a60065b | 276 | #define __STREXW(value, ptr) __strex(value, ptr) |
kadonotakashi | 0:8fdf9a60065b | 277 | #else |
kadonotakashi | 0:8fdf9a60065b | 278 | #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
kadonotakashi | 0:8fdf9a60065b | 279 | #endif |
kadonotakashi | 0:8fdf9a60065b | 280 | |
kadonotakashi | 0:8fdf9a60065b | 281 | /** |
kadonotakashi | 0:8fdf9a60065b | 282 | \brief Remove the exclusive lock |
kadonotakashi | 0:8fdf9a60065b | 283 | \details Removes the exclusive lock which is created by LDREX. |
kadonotakashi | 0:8fdf9a60065b | 284 | */ |
kadonotakashi | 0:8fdf9a60065b | 285 | #define __CLREX __clrex |
kadonotakashi | 0:8fdf9a60065b | 286 | |
kadonotakashi | 0:8fdf9a60065b | 287 | |
kadonotakashi | 0:8fdf9a60065b | 288 | /** |
kadonotakashi | 0:8fdf9a60065b | 289 | \brief Signed Saturate |
kadonotakashi | 0:8fdf9a60065b | 290 | \details Saturates a signed value. |
kadonotakashi | 0:8fdf9a60065b | 291 | \param [in] value Value to be saturated |
kadonotakashi | 0:8fdf9a60065b | 292 | \param [in] sat Bit position to saturate to (1..32) |
kadonotakashi | 0:8fdf9a60065b | 293 | \return Saturated value |
kadonotakashi | 0:8fdf9a60065b | 294 | */ |
kadonotakashi | 0:8fdf9a60065b | 295 | #define __SSAT __ssat |
kadonotakashi | 0:8fdf9a60065b | 296 | |
kadonotakashi | 0:8fdf9a60065b | 297 | /** |
kadonotakashi | 0:8fdf9a60065b | 298 | \brief Unsigned Saturate |
kadonotakashi | 0:8fdf9a60065b | 299 | \details Saturates an unsigned value. |
kadonotakashi | 0:8fdf9a60065b | 300 | \param [in] value Value to be saturated |
kadonotakashi | 0:8fdf9a60065b | 301 | \param [in] sat Bit position to saturate to (0..31) |
kadonotakashi | 0:8fdf9a60065b | 302 | \return Saturated value |
kadonotakashi | 0:8fdf9a60065b | 303 | */ |
kadonotakashi | 0:8fdf9a60065b | 304 | #define __USAT __usat |
kadonotakashi | 0:8fdf9a60065b | 305 | |
kadonotakashi | 0:8fdf9a60065b | 306 | /* ########################### Core Function Access ########################### */ |
kadonotakashi | 0:8fdf9a60065b | 307 | |
kadonotakashi | 0:8fdf9a60065b | 308 | /** |
kadonotakashi | 0:8fdf9a60065b | 309 | \brief Get FPSCR (Floating Point Status/Control) |
kadonotakashi | 0:8fdf9a60065b | 310 | \return Floating Point Status/Control register value |
kadonotakashi | 0:8fdf9a60065b | 311 | */ |
kadonotakashi | 0:8fdf9a60065b | 312 | __STATIC_INLINE uint32_t __get_FPSCR(void) |
kadonotakashi | 0:8fdf9a60065b | 313 | { |
kadonotakashi | 0:8fdf9a60065b | 314 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
kadonotakashi | 0:8fdf9a60065b | 315 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
kadonotakashi | 0:8fdf9a60065b | 316 | register uint32_t __regfpscr __ASM("fpscr"); |
kadonotakashi | 0:8fdf9a60065b | 317 | return(__regfpscr); |
kadonotakashi | 0:8fdf9a60065b | 318 | #else |
kadonotakashi | 0:8fdf9a60065b | 319 | return(0U); |
kadonotakashi | 0:8fdf9a60065b | 320 | #endif |
kadonotakashi | 0:8fdf9a60065b | 321 | } |
kadonotakashi | 0:8fdf9a60065b | 322 | |
kadonotakashi | 0:8fdf9a60065b | 323 | /** |
kadonotakashi | 0:8fdf9a60065b | 324 | \brief Set FPSCR (Floating Point Status/Control) |
kadonotakashi | 0:8fdf9a60065b | 325 | \param [in] fpscr Floating Point Status/Control value to set |
kadonotakashi | 0:8fdf9a60065b | 326 | */ |
kadonotakashi | 0:8fdf9a60065b | 327 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
kadonotakashi | 0:8fdf9a60065b | 328 | { |
kadonotakashi | 0:8fdf9a60065b | 329 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
kadonotakashi | 0:8fdf9a60065b | 330 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
kadonotakashi | 0:8fdf9a60065b | 331 | register uint32_t __regfpscr __ASM("fpscr"); |
kadonotakashi | 0:8fdf9a60065b | 332 | __regfpscr = (fpscr); |
kadonotakashi | 0:8fdf9a60065b | 333 | #else |
kadonotakashi | 0:8fdf9a60065b | 334 | (void)fpscr; |
kadonotakashi | 0:8fdf9a60065b | 335 | #endif |
kadonotakashi | 0:8fdf9a60065b | 336 | } |
kadonotakashi | 0:8fdf9a60065b | 337 | |
kadonotakashi | 0:8fdf9a60065b | 338 | /** \brief Get CPSR (Current Program Status Register) |
kadonotakashi | 0:8fdf9a60065b | 339 | \return CPSR Register value |
kadonotakashi | 0:8fdf9a60065b | 340 | */ |
kadonotakashi | 0:8fdf9a60065b | 341 | __STATIC_INLINE uint32_t __get_CPSR(void) |
kadonotakashi | 0:8fdf9a60065b | 342 | { |
kadonotakashi | 0:8fdf9a60065b | 343 | register uint32_t __regCPSR __ASM("cpsr"); |
kadonotakashi | 0:8fdf9a60065b | 344 | return(__regCPSR); |
kadonotakashi | 0:8fdf9a60065b | 345 | } |
kadonotakashi | 0:8fdf9a60065b | 346 | |
kadonotakashi | 0:8fdf9a60065b | 347 | |
kadonotakashi | 0:8fdf9a60065b | 348 | /** \brief Set CPSR (Current Program Status Register) |
kadonotakashi | 0:8fdf9a60065b | 349 | \param [in] cpsr CPSR value to set |
kadonotakashi | 0:8fdf9a60065b | 350 | */ |
kadonotakashi | 0:8fdf9a60065b | 351 | __STATIC_INLINE void __set_CPSR(uint32_t cpsr) |
kadonotakashi | 0:8fdf9a60065b | 352 | { |
kadonotakashi | 0:8fdf9a60065b | 353 | register uint32_t __regCPSR __ASM("cpsr"); |
kadonotakashi | 0:8fdf9a60065b | 354 | __regCPSR = cpsr; |
kadonotakashi | 0:8fdf9a60065b | 355 | } |
kadonotakashi | 0:8fdf9a60065b | 356 | |
kadonotakashi | 0:8fdf9a60065b | 357 | /** \brief Get Mode |
kadonotakashi | 0:8fdf9a60065b | 358 | \return Processor Mode |
kadonotakashi | 0:8fdf9a60065b | 359 | */ |
kadonotakashi | 0:8fdf9a60065b | 360 | __STATIC_INLINE uint32_t __get_mode(void) |
kadonotakashi | 0:8fdf9a60065b | 361 | { |
kadonotakashi | 0:8fdf9a60065b | 362 | return (__get_CPSR() & 0x1FU); |
kadonotakashi | 0:8fdf9a60065b | 363 | } |
kadonotakashi | 0:8fdf9a60065b | 364 | |
kadonotakashi | 0:8fdf9a60065b | 365 | /** \brief Set Mode |
kadonotakashi | 0:8fdf9a60065b | 366 | \param [in] mode Mode value to set |
kadonotakashi | 0:8fdf9a60065b | 367 | */ |
kadonotakashi | 0:8fdf9a60065b | 368 | __STATIC_INLINE __ASM void __set_mode(uint32_t mode) |
kadonotakashi | 0:8fdf9a60065b | 369 | { |
kadonotakashi | 0:8fdf9a60065b | 370 | MOV r1, lr |
kadonotakashi | 0:8fdf9a60065b | 371 | MSR CPSR_C, r0 |
kadonotakashi | 0:8fdf9a60065b | 372 | BX r1 |
kadonotakashi | 0:8fdf9a60065b | 373 | } |
kadonotakashi | 0:8fdf9a60065b | 374 | |
kadonotakashi | 0:8fdf9a60065b | 375 | /** \brief Get Stack Pointer |
kadonotakashi | 0:8fdf9a60065b | 376 | \return Stack Pointer |
kadonotakashi | 0:8fdf9a60065b | 377 | */ |
kadonotakashi | 0:8fdf9a60065b | 378 | __STATIC_INLINE __ASM uint32_t __get_SP(void) |
kadonotakashi | 0:8fdf9a60065b | 379 | { |
kadonotakashi | 0:8fdf9a60065b | 380 | MOV r0, sp |
kadonotakashi | 0:8fdf9a60065b | 381 | BX lr |
kadonotakashi | 0:8fdf9a60065b | 382 | } |
kadonotakashi | 0:8fdf9a60065b | 383 | |
kadonotakashi | 0:8fdf9a60065b | 384 | /** \brief Set Stack Pointer |
kadonotakashi | 0:8fdf9a60065b | 385 | \param [in] stack Stack Pointer value to set |
kadonotakashi | 0:8fdf9a60065b | 386 | */ |
kadonotakashi | 0:8fdf9a60065b | 387 | __STATIC_INLINE __ASM void __set_SP(uint32_t stack) |
kadonotakashi | 0:8fdf9a60065b | 388 | { |
kadonotakashi | 0:8fdf9a60065b | 389 | MOV sp, r0 |
kadonotakashi | 0:8fdf9a60065b | 390 | BX lr |
kadonotakashi | 0:8fdf9a60065b | 391 | } |
kadonotakashi | 0:8fdf9a60065b | 392 | |
kadonotakashi | 0:8fdf9a60065b | 393 | |
kadonotakashi | 0:8fdf9a60065b | 394 | /** \brief Get USR/SYS Stack Pointer |
kadonotakashi | 0:8fdf9a60065b | 395 | \return USR/SYSStack Pointer |
kadonotakashi | 0:8fdf9a60065b | 396 | */ |
kadonotakashi | 0:8fdf9a60065b | 397 | __STATIC_INLINE __ASM uint32_t __get_SP_usr(void) |
kadonotakashi | 0:8fdf9a60065b | 398 | { |
kadonotakashi | 0:8fdf9a60065b | 399 | ARM |
kadonotakashi | 0:8fdf9a60065b | 400 | PRESERVE8 |
kadonotakashi | 0:8fdf9a60065b | 401 | |
kadonotakashi | 0:8fdf9a60065b | 402 | MRS R1, CPSR |
kadonotakashi | 0:8fdf9a60065b | 403 | CPS #0x1F ;no effect in USR mode |
kadonotakashi | 0:8fdf9a60065b | 404 | MOV R0, SP |
kadonotakashi | 0:8fdf9a60065b | 405 | MSR CPSR_c, R1 ;no effect in USR mode |
kadonotakashi | 0:8fdf9a60065b | 406 | ISB |
kadonotakashi | 0:8fdf9a60065b | 407 | BX LR |
kadonotakashi | 0:8fdf9a60065b | 408 | } |
kadonotakashi | 0:8fdf9a60065b | 409 | |
kadonotakashi | 0:8fdf9a60065b | 410 | /** \brief Set USR/SYS Stack Pointer |
kadonotakashi | 0:8fdf9a60065b | 411 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set |
kadonotakashi | 0:8fdf9a60065b | 412 | */ |
kadonotakashi | 0:8fdf9a60065b | 413 | __STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack) |
kadonotakashi | 0:8fdf9a60065b | 414 | { |
kadonotakashi | 0:8fdf9a60065b | 415 | ARM |
kadonotakashi | 0:8fdf9a60065b | 416 | PRESERVE8 |
kadonotakashi | 0:8fdf9a60065b | 417 | |
kadonotakashi | 0:8fdf9a60065b | 418 | MRS R1, CPSR |
kadonotakashi | 0:8fdf9a60065b | 419 | CPS #0x1F ;no effect in USR mode |
kadonotakashi | 0:8fdf9a60065b | 420 | MOV SP, R0 |
kadonotakashi | 0:8fdf9a60065b | 421 | MSR CPSR_c, R1 ;no effect in USR mode |
kadonotakashi | 0:8fdf9a60065b | 422 | ISB |
kadonotakashi | 0:8fdf9a60065b | 423 | BX LR |
kadonotakashi | 0:8fdf9a60065b | 424 | } |
kadonotakashi | 0:8fdf9a60065b | 425 | |
kadonotakashi | 0:8fdf9a60065b | 426 | /** \brief Get FPEXC (Floating Point Exception Control Register) |
kadonotakashi | 0:8fdf9a60065b | 427 | \return Floating Point Exception Control Register value |
kadonotakashi | 0:8fdf9a60065b | 428 | */ |
kadonotakashi | 0:8fdf9a60065b | 429 | __STATIC_INLINE uint32_t __get_FPEXC(void) |
kadonotakashi | 0:8fdf9a60065b | 430 | { |
kadonotakashi | 0:8fdf9a60065b | 431 | #if (__FPU_PRESENT == 1) |
kadonotakashi | 0:8fdf9a60065b | 432 | register uint32_t __regfpexc __ASM("fpexc"); |
kadonotakashi | 0:8fdf9a60065b | 433 | return(__regfpexc); |
kadonotakashi | 0:8fdf9a60065b | 434 | #else |
kadonotakashi | 0:8fdf9a60065b | 435 | return(0); |
kadonotakashi | 0:8fdf9a60065b | 436 | #endif |
kadonotakashi | 0:8fdf9a60065b | 437 | } |
kadonotakashi | 0:8fdf9a60065b | 438 | |
kadonotakashi | 0:8fdf9a60065b | 439 | /** \brief Set FPEXC (Floating Point Exception Control Register) |
kadonotakashi | 0:8fdf9a60065b | 440 | \param [in] fpexc Floating Point Exception Control value to set |
kadonotakashi | 0:8fdf9a60065b | 441 | */ |
kadonotakashi | 0:8fdf9a60065b | 442 | __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) |
kadonotakashi | 0:8fdf9a60065b | 443 | { |
kadonotakashi | 0:8fdf9a60065b | 444 | #if (__FPU_PRESENT == 1) |
kadonotakashi | 0:8fdf9a60065b | 445 | register uint32_t __regfpexc __ASM("fpexc"); |
kadonotakashi | 0:8fdf9a60065b | 446 | __regfpexc = (fpexc); |
kadonotakashi | 0:8fdf9a60065b | 447 | #endif |
kadonotakashi | 0:8fdf9a60065b | 448 | } |
kadonotakashi | 0:8fdf9a60065b | 449 | |
kadonotakashi | 0:8fdf9a60065b | 450 | /* |
kadonotakashi | 0:8fdf9a60065b | 451 | * Include common core functions to access Coprocessor 15 registers |
kadonotakashi | 0:8fdf9a60065b | 452 | */ |
kadonotakashi | 0:8fdf9a60065b | 453 | |
kadonotakashi | 0:8fdf9a60065b | 454 | #define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) |
kadonotakashi | 0:8fdf9a60065b | 455 | #define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) |
kadonotakashi | 0:8fdf9a60065b | 456 | #define __get_CP64(cp, op1, Rt, CRm) \ |
kadonotakashi | 0:8fdf9a60065b | 457 | do { \ |
kadonotakashi | 0:8fdf9a60065b | 458 | uint32_t ltmp, htmp; \ |
kadonotakashi | 0:8fdf9a60065b | 459 | __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ |
kadonotakashi | 0:8fdf9a60065b | 460 | (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \ |
kadonotakashi | 0:8fdf9a60065b | 461 | } while(0) |
kadonotakashi | 0:8fdf9a60065b | 462 | |
kadonotakashi | 0:8fdf9a60065b | 463 | #define __set_CP64(cp, op1, Rt, CRm) \ |
kadonotakashi | 0:8fdf9a60065b | 464 | do { \ |
kadonotakashi | 0:8fdf9a60065b | 465 | const uint64_t tmp = (Rt); \ |
kadonotakashi | 0:8fdf9a60065b | 466 | const uint32_t ltmp = (uint32_t)(tmp); \ |
kadonotakashi | 0:8fdf9a60065b | 467 | const uint32_t htmp = (uint32_t)(tmp >> 32U); \ |
kadonotakashi | 0:8fdf9a60065b | 468 | __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ |
kadonotakashi | 0:8fdf9a60065b | 469 | } while(0) |
kadonotakashi | 0:8fdf9a60065b | 470 | |
kadonotakashi | 0:8fdf9a60065b | 471 | #include "cmsis_cp15.h" |
kadonotakashi | 0:8fdf9a60065b | 472 | |
kadonotakashi | 0:8fdf9a60065b | 473 | /** \brief Enable Floating Point Unit |
kadonotakashi | 0:8fdf9a60065b | 474 | |
kadonotakashi | 0:8fdf9a60065b | 475 | Critical section, called from undef handler, so systick is disabled |
kadonotakashi | 0:8fdf9a60065b | 476 | */ |
kadonotakashi | 0:8fdf9a60065b | 477 | __STATIC_INLINE __ASM void __FPU_Enable(void) |
kadonotakashi | 0:8fdf9a60065b | 478 | { |
kadonotakashi | 0:8fdf9a60065b | 479 | ARM |
kadonotakashi | 0:8fdf9a60065b | 480 | |
kadonotakashi | 0:8fdf9a60065b | 481 | //Permit access to VFP/NEON, registers by modifying CPACR |
kadonotakashi | 0:8fdf9a60065b | 482 | MRC p15,0,R1,c1,c0,2 |
kadonotakashi | 0:8fdf9a60065b | 483 | ORR R1,R1,#0x00F00000 |
kadonotakashi | 0:8fdf9a60065b | 484 | MCR p15,0,R1,c1,c0,2 |
kadonotakashi | 0:8fdf9a60065b | 485 | |
kadonotakashi | 0:8fdf9a60065b | 486 | //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted |
kadonotakashi | 0:8fdf9a60065b | 487 | ISB |
kadonotakashi | 0:8fdf9a60065b | 488 | |
kadonotakashi | 0:8fdf9a60065b | 489 | //Enable VFP/NEON |
kadonotakashi | 0:8fdf9a60065b | 490 | VMRS R1,FPEXC |
kadonotakashi | 0:8fdf9a60065b | 491 | ORR R1,R1,#0x40000000 |
kadonotakashi | 0:8fdf9a60065b | 492 | VMSR FPEXC,R1 |
kadonotakashi | 0:8fdf9a60065b | 493 | |
kadonotakashi | 0:8fdf9a60065b | 494 | //Initialise VFP/NEON registers to 0 |
kadonotakashi | 0:8fdf9a60065b | 495 | MOV R2,#0 |
kadonotakashi | 0:8fdf9a60065b | 496 | |
kadonotakashi | 0:8fdf9a60065b | 497 | //Initialise D16 registers to 0 |
kadonotakashi | 0:8fdf9a60065b | 498 | VMOV D0, R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 499 | VMOV D1, R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 500 | VMOV D2, R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 501 | VMOV D3, R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 502 | VMOV D4, R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 503 | VMOV D5, R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 504 | VMOV D6, R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 505 | VMOV D7, R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 506 | VMOV D8, R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 507 | VMOV D9, R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 508 | VMOV D10,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 509 | VMOV D11,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 510 | VMOV D12,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 511 | VMOV D13,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 512 | VMOV D14,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 513 | VMOV D15,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 514 | |
kadonotakashi | 0:8fdf9a60065b | 515 | IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 |
kadonotakashi | 0:8fdf9a60065b | 516 | //Initialise D32 registers to 0 |
kadonotakashi | 0:8fdf9a60065b | 517 | VMOV D16,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 518 | VMOV D17,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 519 | VMOV D18,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 520 | VMOV D19,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 521 | VMOV D20,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 522 | VMOV D21,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 523 | VMOV D22,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 524 | VMOV D23,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 525 | VMOV D24,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 526 | VMOV D25,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 527 | VMOV D26,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 528 | VMOV D27,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 529 | VMOV D28,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 530 | VMOV D29,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 531 | VMOV D30,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 532 | VMOV D31,R2,R2 |
kadonotakashi | 0:8fdf9a60065b | 533 | ENDIF |
kadonotakashi | 0:8fdf9a60065b | 534 | |
kadonotakashi | 0:8fdf9a60065b | 535 | //Initialise FPSCR to a known state |
kadonotakashi | 0:8fdf9a60065b | 536 | VMRS R2,FPSCR |
kadonotakashi | 0:8fdf9a60065b | 537 | LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. |
kadonotakashi | 0:8fdf9a60065b | 538 | AND R2,R2,R3 |
kadonotakashi | 0:8fdf9a60065b | 539 | VMSR FPSCR,R2 |
kadonotakashi | 0:8fdf9a60065b | 540 | |
kadonotakashi | 0:8fdf9a60065b | 541 | BX LR |
kadonotakashi | 0:8fdf9a60065b | 542 | } |
kadonotakashi | 0:8fdf9a60065b | 543 | |
kadonotakashi | 0:8fdf9a60065b | 544 | #endif /* __CMSIS_ARMCC_H */ |