takashi kadono / Mbed OS Nucleo_446

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/drivers/QSPI.cpp@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:
kadonotakashi
Date:
Wed Oct 10 00:33:53 2018 +0000
Revision:
0:8fdf9a60065b
how to make mbed librry

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /* mbed Microcontroller Library
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2006-2018 ARM Limited
kadonotakashi 0:8fdf9a60065b 3 *
kadonotakashi 0:8fdf9a60065b 4 * Licensed under the Apache License, Version 2.0 (the "License");
kadonotakashi 0:8fdf9a60065b 5 * you may not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 6 * You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * http://www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 11 * distributed under the License is distributed on an "AS IS" BASIS,
kadonotakashi 0:8fdf9a60065b 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 13 * See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 14 * limitations under the License.
kadonotakashi 0:8fdf9a60065b 15 */
kadonotakashi 0:8fdf9a60065b 16
kadonotakashi 0:8fdf9a60065b 17 #include "drivers/QSPI.h"
kadonotakashi 0:8fdf9a60065b 18 #include "platform/mbed_critical.h"
kadonotakashi 0:8fdf9a60065b 19 #include <string.h>
kadonotakashi 0:8fdf9a60065b 20
kadonotakashi 0:8fdf9a60065b 21 #if DEVICE_QSPI
kadonotakashi 0:8fdf9a60065b 22
kadonotakashi 0:8fdf9a60065b 23 namespace mbed {
kadonotakashi 0:8fdf9a60065b 24
kadonotakashi 0:8fdf9a60065b 25 QSPI *QSPI::_owner = NULL;
kadonotakashi 0:8fdf9a60065b 26 SingletonPtr<PlatformMutex> QSPI::_mutex;
kadonotakashi 0:8fdf9a60065b 27
kadonotakashi 0:8fdf9a60065b 28 QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi()
kadonotakashi 0:8fdf9a60065b 29 {
kadonotakashi 0:8fdf9a60065b 30 _qspi_io0 = io0;
kadonotakashi 0:8fdf9a60065b 31 _qspi_io1 = io1;
kadonotakashi 0:8fdf9a60065b 32 _qspi_io2 = io2;
kadonotakashi 0:8fdf9a60065b 33 _qspi_io3 = io3;
kadonotakashi 0:8fdf9a60065b 34 _qspi_clk = sclk;
kadonotakashi 0:8fdf9a60065b 35 _qspi_cs = ssel;
kadonotakashi 0:8fdf9a60065b 36 _inst_width = QSPI_CFG_BUS_SINGLE;
kadonotakashi 0:8fdf9a60065b 37 _address_width = QSPI_CFG_BUS_SINGLE;
kadonotakashi 0:8fdf9a60065b 38 _address_size = QSPI_CFG_ADDR_SIZE_24;
kadonotakashi 0:8fdf9a60065b 39 _alt_width = QSPI_CFG_BUS_SINGLE;
kadonotakashi 0:8fdf9a60065b 40 _alt_size = QSPI_CFG_ALT_SIZE_8;
kadonotakashi 0:8fdf9a60065b 41 _data_width = QSPI_CFG_BUS_SINGLE;
kadonotakashi 0:8fdf9a60065b 42 _num_dummy_cycles = 0;
kadonotakashi 0:8fdf9a60065b 43 _mode = mode;
kadonotakashi 0:8fdf9a60065b 44 _hz = ONE_MHZ;
kadonotakashi 0:8fdf9a60065b 45 _initialized = false;
kadonotakashi 0:8fdf9a60065b 46
kadonotakashi 0:8fdf9a60065b 47 //Go ahead init the device here with the default config
kadonotakashi 0:8fdf9a60065b 48 bool success = _initialize();
kadonotakashi 0:8fdf9a60065b 49 MBED_ASSERT(success);
kadonotakashi 0:8fdf9a60065b 50 }
kadonotakashi 0:8fdf9a60065b 51
kadonotakashi 0:8fdf9a60065b 52 qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width_t address_width, qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width, int dummy_cycles)
kadonotakashi 0:8fdf9a60065b 53 {
kadonotakashi 0:8fdf9a60065b 54 qspi_status_t ret_status = QSPI_STATUS_OK;
kadonotakashi 0:8fdf9a60065b 55
kadonotakashi 0:8fdf9a60065b 56 lock();
kadonotakashi 0:8fdf9a60065b 57 _inst_width = inst_width;
kadonotakashi 0:8fdf9a60065b 58 _address_width = address_width;
kadonotakashi 0:8fdf9a60065b 59 _address_size = address_size;
kadonotakashi 0:8fdf9a60065b 60 _alt_width = alt_width;
kadonotakashi 0:8fdf9a60065b 61 _alt_size = alt_size;
kadonotakashi 0:8fdf9a60065b 62 _data_width = data_width;
kadonotakashi 0:8fdf9a60065b 63 _num_dummy_cycles = dummy_cycles;
kadonotakashi 0:8fdf9a60065b 64
kadonotakashi 0:8fdf9a60065b 65 unlock();
kadonotakashi 0:8fdf9a60065b 66
kadonotakashi 0:8fdf9a60065b 67 return ret_status;
kadonotakashi 0:8fdf9a60065b 68 }
kadonotakashi 0:8fdf9a60065b 69
kadonotakashi 0:8fdf9a60065b 70 qspi_status_t QSPI::set_frequency(int hz)
kadonotakashi 0:8fdf9a60065b 71 {
kadonotakashi 0:8fdf9a60065b 72 qspi_status_t ret_status = QSPI_STATUS_OK;
kadonotakashi 0:8fdf9a60065b 73
kadonotakashi 0:8fdf9a60065b 74 if (_initialized) {
kadonotakashi 0:8fdf9a60065b 75 lock();
kadonotakashi 0:8fdf9a60065b 76 _hz = hz;
kadonotakashi 0:8fdf9a60065b 77 //If the same owner, just change freq.
kadonotakashi 0:8fdf9a60065b 78 //Otherwise we may have to change mode as well, so call _acquire
kadonotakashi 0:8fdf9a60065b 79 if (_owner == this) {
kadonotakashi 0:8fdf9a60065b 80 if (QSPI_STATUS_OK != qspi_frequency(&_qspi, _hz)) {
kadonotakashi 0:8fdf9a60065b 81 ret_status = QSPI_STATUS_ERROR;
kadonotakashi 0:8fdf9a60065b 82 }
kadonotakashi 0:8fdf9a60065b 83 } else {
kadonotakashi 0:8fdf9a60065b 84 _acquire();
kadonotakashi 0:8fdf9a60065b 85 }
kadonotakashi 0:8fdf9a60065b 86 unlock();
kadonotakashi 0:8fdf9a60065b 87 } else {
kadonotakashi 0:8fdf9a60065b 88 ret_status = QSPI_STATUS_ERROR;
kadonotakashi 0:8fdf9a60065b 89 }
kadonotakashi 0:8fdf9a60065b 90
kadonotakashi 0:8fdf9a60065b 91 return ret_status;
kadonotakashi 0:8fdf9a60065b 92 }
kadonotakashi 0:8fdf9a60065b 93
kadonotakashi 0:8fdf9a60065b 94 qspi_status_t QSPI::read(int address, char *rx_buffer, size_t *rx_length)
kadonotakashi 0:8fdf9a60065b 95 {
kadonotakashi 0:8fdf9a60065b 96 qspi_status_t ret_status = QSPI_STATUS_ERROR;
kadonotakashi 0:8fdf9a60065b 97
kadonotakashi 0:8fdf9a60065b 98 if (_initialized) {
kadonotakashi 0:8fdf9a60065b 99 if ((rx_length != NULL) && (rx_buffer != NULL)) {
kadonotakashi 0:8fdf9a60065b 100 if (*rx_length != 0) {
kadonotakashi 0:8fdf9a60065b 101 lock();
kadonotakashi 0:8fdf9a60065b 102 if (true == _acquire()) {
kadonotakashi 0:8fdf9a60065b 103 _build_qspi_command(-1, address, -1);
kadonotakashi 0:8fdf9a60065b 104 if (QSPI_STATUS_OK == qspi_read(&_qspi, &_qspi_command, rx_buffer, rx_length)) {
kadonotakashi 0:8fdf9a60065b 105 ret_status = QSPI_STATUS_OK;
kadonotakashi 0:8fdf9a60065b 106 }
kadonotakashi 0:8fdf9a60065b 107 }
kadonotakashi 0:8fdf9a60065b 108 unlock();
kadonotakashi 0:8fdf9a60065b 109 }
kadonotakashi 0:8fdf9a60065b 110 } else {
kadonotakashi 0:8fdf9a60065b 111 ret_status = QSPI_STATUS_INVALID_PARAMETER;
kadonotakashi 0:8fdf9a60065b 112 }
kadonotakashi 0:8fdf9a60065b 113 }
kadonotakashi 0:8fdf9a60065b 114
kadonotakashi 0:8fdf9a60065b 115 return ret_status;
kadonotakashi 0:8fdf9a60065b 116 }
kadonotakashi 0:8fdf9a60065b 117
kadonotakashi 0:8fdf9a60065b 118 qspi_status_t QSPI::write(int address, const char *tx_buffer, size_t *tx_length)
kadonotakashi 0:8fdf9a60065b 119 {
kadonotakashi 0:8fdf9a60065b 120 qspi_status_t ret_status = QSPI_STATUS_ERROR;
kadonotakashi 0:8fdf9a60065b 121
kadonotakashi 0:8fdf9a60065b 122 if (_initialized) {
kadonotakashi 0:8fdf9a60065b 123 if ((tx_length != NULL) && (tx_buffer != NULL)) {
kadonotakashi 0:8fdf9a60065b 124 if (*tx_length != 0) {
kadonotakashi 0:8fdf9a60065b 125 lock();
kadonotakashi 0:8fdf9a60065b 126 if (true == _acquire()) {
kadonotakashi 0:8fdf9a60065b 127 _build_qspi_command(-1, address, -1);
kadonotakashi 0:8fdf9a60065b 128 if (QSPI_STATUS_OK == qspi_write(&_qspi, &_qspi_command, tx_buffer, tx_length)) {
kadonotakashi 0:8fdf9a60065b 129 ret_status = QSPI_STATUS_OK;
kadonotakashi 0:8fdf9a60065b 130 }
kadonotakashi 0:8fdf9a60065b 131 }
kadonotakashi 0:8fdf9a60065b 132 unlock();
kadonotakashi 0:8fdf9a60065b 133 }
kadonotakashi 0:8fdf9a60065b 134 } else {
kadonotakashi 0:8fdf9a60065b 135 ret_status = QSPI_STATUS_INVALID_PARAMETER;
kadonotakashi 0:8fdf9a60065b 136 }
kadonotakashi 0:8fdf9a60065b 137 }
kadonotakashi 0:8fdf9a60065b 138
kadonotakashi 0:8fdf9a60065b 139 return ret_status;
kadonotakashi 0:8fdf9a60065b 140 }
kadonotakashi 0:8fdf9a60065b 141
kadonotakashi 0:8fdf9a60065b 142 qspi_status_t QSPI::read(int instruction, int alt, int address, char *rx_buffer, size_t *rx_length)
kadonotakashi 0:8fdf9a60065b 143 {
kadonotakashi 0:8fdf9a60065b 144 qspi_status_t ret_status = QSPI_STATUS_ERROR;
kadonotakashi 0:8fdf9a60065b 145
kadonotakashi 0:8fdf9a60065b 146 if (_initialized) {
kadonotakashi 0:8fdf9a60065b 147 if ((rx_length != NULL) && (rx_buffer != NULL)) {
kadonotakashi 0:8fdf9a60065b 148 if (*rx_length != 0) {
kadonotakashi 0:8fdf9a60065b 149 lock();
kadonotakashi 0:8fdf9a60065b 150 if (true == _acquire()) {
kadonotakashi 0:8fdf9a60065b 151 _build_qspi_command(instruction, address, alt);
kadonotakashi 0:8fdf9a60065b 152 if (QSPI_STATUS_OK == qspi_read(&_qspi, &_qspi_command, rx_buffer, rx_length)) {
kadonotakashi 0:8fdf9a60065b 153 ret_status = QSPI_STATUS_OK;
kadonotakashi 0:8fdf9a60065b 154 }
kadonotakashi 0:8fdf9a60065b 155 }
kadonotakashi 0:8fdf9a60065b 156 unlock();
kadonotakashi 0:8fdf9a60065b 157 }
kadonotakashi 0:8fdf9a60065b 158 } else {
kadonotakashi 0:8fdf9a60065b 159 ret_status = QSPI_STATUS_INVALID_PARAMETER;
kadonotakashi 0:8fdf9a60065b 160 }
kadonotakashi 0:8fdf9a60065b 161 }
kadonotakashi 0:8fdf9a60065b 162
kadonotakashi 0:8fdf9a60065b 163 return ret_status;
kadonotakashi 0:8fdf9a60065b 164 }
kadonotakashi 0:8fdf9a60065b 165
kadonotakashi 0:8fdf9a60065b 166 qspi_status_t QSPI::write(int instruction, int alt, int address, const char *tx_buffer, size_t *tx_length)
kadonotakashi 0:8fdf9a60065b 167 {
kadonotakashi 0:8fdf9a60065b 168 qspi_status_t ret_status = QSPI_STATUS_ERROR;
kadonotakashi 0:8fdf9a60065b 169
kadonotakashi 0:8fdf9a60065b 170 if (_initialized) {
kadonotakashi 0:8fdf9a60065b 171 if ((tx_length != NULL) && (tx_buffer != NULL)) {
kadonotakashi 0:8fdf9a60065b 172 if (*tx_length != 0) {
kadonotakashi 0:8fdf9a60065b 173 lock();
kadonotakashi 0:8fdf9a60065b 174 if (true == _acquire()) {
kadonotakashi 0:8fdf9a60065b 175 _build_qspi_command(instruction, address, alt);
kadonotakashi 0:8fdf9a60065b 176 if (QSPI_STATUS_OK == qspi_write(&_qspi, &_qspi_command, tx_buffer, tx_length)) {
kadonotakashi 0:8fdf9a60065b 177 ret_status = QSPI_STATUS_OK;
kadonotakashi 0:8fdf9a60065b 178 }
kadonotakashi 0:8fdf9a60065b 179 }
kadonotakashi 0:8fdf9a60065b 180 unlock();
kadonotakashi 0:8fdf9a60065b 181 }
kadonotakashi 0:8fdf9a60065b 182 } else {
kadonotakashi 0:8fdf9a60065b 183 ret_status = QSPI_STATUS_INVALID_PARAMETER;
kadonotakashi 0:8fdf9a60065b 184 }
kadonotakashi 0:8fdf9a60065b 185 }
kadonotakashi 0:8fdf9a60065b 186
kadonotakashi 0:8fdf9a60065b 187 return ret_status;
kadonotakashi 0:8fdf9a60065b 188 }
kadonotakashi 0:8fdf9a60065b 189
kadonotakashi 0:8fdf9a60065b 190 qspi_status_t QSPI::command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length)
kadonotakashi 0:8fdf9a60065b 191 {
kadonotakashi 0:8fdf9a60065b 192 qspi_status_t ret_status = QSPI_STATUS_ERROR;
kadonotakashi 0:8fdf9a60065b 193
kadonotakashi 0:8fdf9a60065b 194 if (_initialized) {
kadonotakashi 0:8fdf9a60065b 195 lock();
kadonotakashi 0:8fdf9a60065b 196 if (true == _acquire()) {
kadonotakashi 0:8fdf9a60065b 197 _build_qspi_command(instruction, address, -1); //We just need the command
kadonotakashi 0:8fdf9a60065b 198 if (QSPI_STATUS_OK == qspi_command_transfer(&_qspi, &_qspi_command, (const void *)tx_buffer, tx_length, (void *)rx_buffer, rx_length)) {
kadonotakashi 0:8fdf9a60065b 199 ret_status = QSPI_STATUS_OK;
kadonotakashi 0:8fdf9a60065b 200 }
kadonotakashi 0:8fdf9a60065b 201 }
kadonotakashi 0:8fdf9a60065b 202 unlock();
kadonotakashi 0:8fdf9a60065b 203 }
kadonotakashi 0:8fdf9a60065b 204
kadonotakashi 0:8fdf9a60065b 205 return ret_status;
kadonotakashi 0:8fdf9a60065b 206 }
kadonotakashi 0:8fdf9a60065b 207
kadonotakashi 0:8fdf9a60065b 208 void QSPI::lock()
kadonotakashi 0:8fdf9a60065b 209 {
kadonotakashi 0:8fdf9a60065b 210 _mutex->lock();
kadonotakashi 0:8fdf9a60065b 211 }
kadonotakashi 0:8fdf9a60065b 212
kadonotakashi 0:8fdf9a60065b 213 void QSPI::unlock()
kadonotakashi 0:8fdf9a60065b 214 {
kadonotakashi 0:8fdf9a60065b 215 _mutex->unlock();
kadonotakashi 0:8fdf9a60065b 216 }
kadonotakashi 0:8fdf9a60065b 217
kadonotakashi 0:8fdf9a60065b 218 // Note: Private helper function to initialize qspi HAL
kadonotakashi 0:8fdf9a60065b 219 bool QSPI::_initialize()
kadonotakashi 0:8fdf9a60065b 220 {
kadonotakashi 0:8fdf9a60065b 221 if (_mode != 0 && _mode != 1) {
kadonotakashi 0:8fdf9a60065b 222 _initialized = false;
kadonotakashi 0:8fdf9a60065b 223 return _initialized;
kadonotakashi 0:8fdf9a60065b 224 }
kadonotakashi 0:8fdf9a60065b 225
kadonotakashi 0:8fdf9a60065b 226 qspi_status_t ret = qspi_init(&_qspi, _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs, _hz, _mode);
kadonotakashi 0:8fdf9a60065b 227 if (QSPI_STATUS_OK == ret) {
kadonotakashi 0:8fdf9a60065b 228 _initialized = true;
kadonotakashi 0:8fdf9a60065b 229 } else {
kadonotakashi 0:8fdf9a60065b 230 _initialized = false;
kadonotakashi 0:8fdf9a60065b 231 }
kadonotakashi 0:8fdf9a60065b 232
kadonotakashi 0:8fdf9a60065b 233 return _initialized;
kadonotakashi 0:8fdf9a60065b 234 }
kadonotakashi 0:8fdf9a60065b 235
kadonotakashi 0:8fdf9a60065b 236 // Note: Private function with no locking
kadonotakashi 0:8fdf9a60065b 237 bool QSPI::_acquire()
kadonotakashi 0:8fdf9a60065b 238 {
kadonotakashi 0:8fdf9a60065b 239 if (_owner != this) {
kadonotakashi 0:8fdf9a60065b 240 //This will set freq as well
kadonotakashi 0:8fdf9a60065b 241 _initialize();
kadonotakashi 0:8fdf9a60065b 242 _owner = this;
kadonotakashi 0:8fdf9a60065b 243 }
kadonotakashi 0:8fdf9a60065b 244
kadonotakashi 0:8fdf9a60065b 245 return _initialized;
kadonotakashi 0:8fdf9a60065b 246 }
kadonotakashi 0:8fdf9a60065b 247
kadonotakashi 0:8fdf9a60065b 248 void QSPI::_build_qspi_command(int instruction, int address, int alt)
kadonotakashi 0:8fdf9a60065b 249 {
kadonotakashi 0:8fdf9a60065b 250 memset(&_qspi_command, 0, sizeof(qspi_command_t));
kadonotakashi 0:8fdf9a60065b 251 //Set up instruction phase parameters
kadonotakashi 0:8fdf9a60065b 252 _qspi_command.instruction.bus_width = _inst_width;
kadonotakashi 0:8fdf9a60065b 253 if (instruction != -1) {
kadonotakashi 0:8fdf9a60065b 254 _qspi_command.instruction.value = instruction;
kadonotakashi 0:8fdf9a60065b 255 _qspi_command.instruction.disabled = false;
kadonotakashi 0:8fdf9a60065b 256 } else {
kadonotakashi 0:8fdf9a60065b 257 _qspi_command.instruction.disabled = true;
kadonotakashi 0:8fdf9a60065b 258 }
kadonotakashi 0:8fdf9a60065b 259
kadonotakashi 0:8fdf9a60065b 260 //Set up address phase parameters
kadonotakashi 0:8fdf9a60065b 261 _qspi_command.address.bus_width = _address_width;
kadonotakashi 0:8fdf9a60065b 262 _qspi_command.address.size = _address_size;
kadonotakashi 0:8fdf9a60065b 263 if (address != -1) {
kadonotakashi 0:8fdf9a60065b 264 _qspi_command.address.value = address;
kadonotakashi 0:8fdf9a60065b 265 _qspi_command.address.disabled = false;
kadonotakashi 0:8fdf9a60065b 266 } else {
kadonotakashi 0:8fdf9a60065b 267 _qspi_command.address.disabled = true;
kadonotakashi 0:8fdf9a60065b 268 }
kadonotakashi 0:8fdf9a60065b 269
kadonotakashi 0:8fdf9a60065b 270 //Set up alt phase parameters
kadonotakashi 0:8fdf9a60065b 271 _qspi_command.alt.bus_width = _alt_width;
kadonotakashi 0:8fdf9a60065b 272 _qspi_command.alt.size = _alt_size;
kadonotakashi 0:8fdf9a60065b 273 if (alt != -1) {
kadonotakashi 0:8fdf9a60065b 274 _qspi_command.alt.value = alt;
kadonotakashi 0:8fdf9a60065b 275 _qspi_command.alt.disabled = false;
kadonotakashi 0:8fdf9a60065b 276 } else {
kadonotakashi 0:8fdf9a60065b 277 _qspi_command.alt.disabled = true;
kadonotakashi 0:8fdf9a60065b 278 }
kadonotakashi 0:8fdf9a60065b 279
kadonotakashi 0:8fdf9a60065b 280 _qspi_command.dummy_count = _num_dummy_cycles;
kadonotakashi 0:8fdf9a60065b 281
kadonotakashi 0:8fdf9a60065b 282 //Set up bus width for data phase
kadonotakashi 0:8fdf9a60065b 283 _qspi_command.data.bus_width = _data_width;
kadonotakashi 0:8fdf9a60065b 284 }
kadonotakashi 0:8fdf9a60065b 285
kadonotakashi 0:8fdf9a60065b 286 } // namespace mbed
kadonotakashi 0:8fdf9a60065b 287
kadonotakashi 0:8fdf9a60065b 288 #endif