takashi kadono / Mbed OS Nucleo_446

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/cmsis/TARGET_CORTEX_M/mpu_armv8.h@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:
kadonotakashi
Date:
Wed Oct 10 00:33:53 2018 +0000
Revision:
0:8fdf9a60065b
how to make mbed librry

Who changed what in which revision?

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kadonotakashi 0:8fdf9a60065b 1 /******************************************************************************
kadonotakashi 0:8fdf9a60065b 2 * @file mpu_armv8.h
kadonotakashi 0:8fdf9a60065b 3 * @brief CMSIS MPU API for Armv8-M MPU
kadonotakashi 0:8fdf9a60065b 4 * @version V5.0.4
kadonotakashi 0:8fdf9a60065b 5 * @date 10. January 2018
kadonotakashi 0:8fdf9a60065b 6 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 7 /*
kadonotakashi 0:8fdf9a60065b 8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * SPDX-License-Identifier: Apache-2.0
kadonotakashi 0:8fdf9a60065b 11 *
kadonotakashi 0:8fdf9a60065b 12 * Licensed under the Apache License, Version 2.0 (the License); you may
kadonotakashi 0:8fdf9a60065b 13 * not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 14 * You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 15 *
kadonotakashi 0:8fdf9a60065b 16 * www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 17 *
kadonotakashi 0:8fdf9a60065b 18 * Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
kadonotakashi 0:8fdf9a60065b 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 21 * See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 22 * limitations under the License.
kadonotakashi 0:8fdf9a60065b 23 */
kadonotakashi 0:8fdf9a60065b 24
kadonotakashi 0:8fdf9a60065b 25 #if defined ( __ICCARM__ )
kadonotakashi 0:8fdf9a60065b 26 #pragma system_include /* treat file as system include file for MISRA check */
kadonotakashi 0:8fdf9a60065b 27 #elif defined (__clang__)
kadonotakashi 0:8fdf9a60065b 28 #pragma clang system_header /* treat file as system include file */
kadonotakashi 0:8fdf9a60065b 29 #endif
kadonotakashi 0:8fdf9a60065b 30
kadonotakashi 0:8fdf9a60065b 31 #ifndef ARM_MPU_ARMV8_H
kadonotakashi 0:8fdf9a60065b 32 #define ARM_MPU_ARMV8_H
kadonotakashi 0:8fdf9a60065b 33
kadonotakashi 0:8fdf9a60065b 34 /** \brief Attribute for device memory (outer only) */
kadonotakashi 0:8fdf9a60065b 35 #define ARM_MPU_ATTR_DEVICE ( 0U )
kadonotakashi 0:8fdf9a60065b 36
kadonotakashi 0:8fdf9a60065b 37 /** \brief Attribute for non-cacheable, normal memory */
kadonotakashi 0:8fdf9a60065b 38 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
kadonotakashi 0:8fdf9a60065b 39
kadonotakashi 0:8fdf9a60065b 40 /** \brief Attribute for normal memory (outer and inner)
kadonotakashi 0:8fdf9a60065b 41 * \param NT Non-Transient: Set to 1 for non-transient data.
kadonotakashi 0:8fdf9a60065b 42 * \param WB Write-Back: Set to 1 to use write-back update policy.
kadonotakashi 0:8fdf9a60065b 43 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
kadonotakashi 0:8fdf9a60065b 44 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
kadonotakashi 0:8fdf9a60065b 45 */
kadonotakashi 0:8fdf9a60065b 46 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
kadonotakashi 0:8fdf9a60065b 47 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
kadonotakashi 0:8fdf9a60065b 48
kadonotakashi 0:8fdf9a60065b 49 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
kadonotakashi 0:8fdf9a60065b 50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
kadonotakashi 0:8fdf9a60065b 51
kadonotakashi 0:8fdf9a60065b 52 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
kadonotakashi 0:8fdf9a60065b 53 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
kadonotakashi 0:8fdf9a60065b 54
kadonotakashi 0:8fdf9a60065b 55 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
kadonotakashi 0:8fdf9a60065b 56 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
kadonotakashi 0:8fdf9a60065b 57
kadonotakashi 0:8fdf9a60065b 58 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
kadonotakashi 0:8fdf9a60065b 59 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
kadonotakashi 0:8fdf9a60065b 60
kadonotakashi 0:8fdf9a60065b 61 /** \brief Memory Attribute
kadonotakashi 0:8fdf9a60065b 62 * \param O Outer memory attributes
kadonotakashi 0:8fdf9a60065b 63 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
kadonotakashi 0:8fdf9a60065b 64 */
kadonotakashi 0:8fdf9a60065b 65 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
kadonotakashi 0:8fdf9a60065b 66
kadonotakashi 0:8fdf9a60065b 67 /** \brief Normal memory non-shareable */
kadonotakashi 0:8fdf9a60065b 68 #define ARM_MPU_SH_NON (0U)
kadonotakashi 0:8fdf9a60065b 69
kadonotakashi 0:8fdf9a60065b 70 /** \brief Normal memory outer shareable */
kadonotakashi 0:8fdf9a60065b 71 #define ARM_MPU_SH_OUTER (2U)
kadonotakashi 0:8fdf9a60065b 72
kadonotakashi 0:8fdf9a60065b 73 /** \brief Normal memory inner shareable */
kadonotakashi 0:8fdf9a60065b 74 #define ARM_MPU_SH_INNER (3U)
kadonotakashi 0:8fdf9a60065b 75
kadonotakashi 0:8fdf9a60065b 76 /** \brief Memory access permissions
kadonotakashi 0:8fdf9a60065b 77 * \param RO Read-Only: Set to 1 for read-only memory.
kadonotakashi 0:8fdf9a60065b 78 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
kadonotakashi 0:8fdf9a60065b 79 */
kadonotakashi 0:8fdf9a60065b 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
kadonotakashi 0:8fdf9a60065b 81
kadonotakashi 0:8fdf9a60065b 82 /** \brief Region Base Address Register value
kadonotakashi 0:8fdf9a60065b 83 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
kadonotakashi 0:8fdf9a60065b 84 * \param SH Defines the Shareability domain for this memory region.
kadonotakashi 0:8fdf9a60065b 85 * \param RO Read-Only: Set to 1 for a read-only memory region.
kadonotakashi 0:8fdf9a60065b 86 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
kadonotakashi 0:8fdf9a60065b 87 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
kadonotakashi 0:8fdf9a60065b 88 */
kadonotakashi 0:8fdf9a60065b 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
kadonotakashi 0:8fdf9a60065b 90 ((BASE & MPU_RBAR_BASE_Msk) | \
kadonotakashi 0:8fdf9a60065b 91 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
kadonotakashi 0:8fdf9a60065b 92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
kadonotakashi 0:8fdf9a60065b 93 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
kadonotakashi 0:8fdf9a60065b 94
kadonotakashi 0:8fdf9a60065b 95 /** \brief Region Limit Address Register value
kadonotakashi 0:8fdf9a60065b 96 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
kadonotakashi 0:8fdf9a60065b 97 * \param IDX The attribute index to be associated with this memory region.
kadonotakashi 0:8fdf9a60065b 98 */
kadonotakashi 0:8fdf9a60065b 99 #define ARM_MPU_RLAR(LIMIT, IDX) \
kadonotakashi 0:8fdf9a60065b 100 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
kadonotakashi 0:8fdf9a60065b 101 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
kadonotakashi 0:8fdf9a60065b 102 (MPU_RLAR_EN_Msk))
kadonotakashi 0:8fdf9a60065b 103
kadonotakashi 0:8fdf9a60065b 104 /**
kadonotakashi 0:8fdf9a60065b 105 * Struct for a single MPU Region
kadonotakashi 0:8fdf9a60065b 106 */
kadonotakashi 0:8fdf9a60065b 107 typedef struct {
kadonotakashi 0:8fdf9a60065b 108 uint32_t RBAR; /*!< Region Base Address Register value */
kadonotakashi 0:8fdf9a60065b 109 uint32_t RLAR; /*!< Region Limit Address Register value */
kadonotakashi 0:8fdf9a60065b 110 } ARM_MPU_Region_t;
kadonotakashi 0:8fdf9a60065b 111
kadonotakashi 0:8fdf9a60065b 112 /** Enable the MPU.
kadonotakashi 0:8fdf9a60065b 113 * \param MPU_Control Default access permissions for unconfigured regions.
kadonotakashi 0:8fdf9a60065b 114 */
kadonotakashi 0:8fdf9a60065b 115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
kadonotakashi 0:8fdf9a60065b 116 {
kadonotakashi 0:8fdf9a60065b 117 __DSB();
kadonotakashi 0:8fdf9a60065b 118 __ISB();
kadonotakashi 0:8fdf9a60065b 119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
kadonotakashi 0:8fdf9a60065b 120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
kadonotakashi 0:8fdf9a60065b 121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
kadonotakashi 0:8fdf9a60065b 122 #endif
kadonotakashi 0:8fdf9a60065b 123 }
kadonotakashi 0:8fdf9a60065b 124
kadonotakashi 0:8fdf9a60065b 125 /** Disable the MPU.
kadonotakashi 0:8fdf9a60065b 126 */
kadonotakashi 0:8fdf9a60065b 127 __STATIC_INLINE void ARM_MPU_Disable(void)
kadonotakashi 0:8fdf9a60065b 128 {
kadonotakashi 0:8fdf9a60065b 129 __DSB();
kadonotakashi 0:8fdf9a60065b 130 __ISB();
kadonotakashi 0:8fdf9a60065b 131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
kadonotakashi 0:8fdf9a60065b 132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
kadonotakashi 0:8fdf9a60065b 133 #endif
kadonotakashi 0:8fdf9a60065b 134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
kadonotakashi 0:8fdf9a60065b 135 }
kadonotakashi 0:8fdf9a60065b 136
kadonotakashi 0:8fdf9a60065b 137 #ifdef MPU_NS
kadonotakashi 0:8fdf9a60065b 138 /** Enable the Non-secure MPU.
kadonotakashi 0:8fdf9a60065b 139 * \param MPU_Control Default access permissions for unconfigured regions.
kadonotakashi 0:8fdf9a60065b 140 */
kadonotakashi 0:8fdf9a60065b 141 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
kadonotakashi 0:8fdf9a60065b 142 {
kadonotakashi 0:8fdf9a60065b 143 __DSB();
kadonotakashi 0:8fdf9a60065b 144 __ISB();
kadonotakashi 0:8fdf9a60065b 145 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
kadonotakashi 0:8fdf9a60065b 146 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
kadonotakashi 0:8fdf9a60065b 147 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
kadonotakashi 0:8fdf9a60065b 148 #endif
kadonotakashi 0:8fdf9a60065b 149 }
kadonotakashi 0:8fdf9a60065b 150
kadonotakashi 0:8fdf9a60065b 151 /** Disable the Non-secure MPU.
kadonotakashi 0:8fdf9a60065b 152 */
kadonotakashi 0:8fdf9a60065b 153 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
kadonotakashi 0:8fdf9a60065b 154 {
kadonotakashi 0:8fdf9a60065b 155 __DSB();
kadonotakashi 0:8fdf9a60065b 156 __ISB();
kadonotakashi 0:8fdf9a60065b 157 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
kadonotakashi 0:8fdf9a60065b 158 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
kadonotakashi 0:8fdf9a60065b 159 #endif
kadonotakashi 0:8fdf9a60065b 160 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
kadonotakashi 0:8fdf9a60065b 161 }
kadonotakashi 0:8fdf9a60065b 162 #endif
kadonotakashi 0:8fdf9a60065b 163
kadonotakashi 0:8fdf9a60065b 164 /** Set the memory attribute encoding to the given MPU.
kadonotakashi 0:8fdf9a60065b 165 * \param mpu Pointer to the MPU to be configured.
kadonotakashi 0:8fdf9a60065b 166 * \param idx The attribute index to be set [0-7]
kadonotakashi 0:8fdf9a60065b 167 * \param attr The attribute value to be set.
kadonotakashi 0:8fdf9a60065b 168 */
kadonotakashi 0:8fdf9a60065b 169 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
kadonotakashi 0:8fdf9a60065b 170 {
kadonotakashi 0:8fdf9a60065b 171 const uint8_t reg = idx / 4U;
kadonotakashi 0:8fdf9a60065b 172 const uint32_t pos = ((idx % 4U) * 8U);
kadonotakashi 0:8fdf9a60065b 173 const uint32_t mask = 0xFFU << pos;
kadonotakashi 0:8fdf9a60065b 174
kadonotakashi 0:8fdf9a60065b 175 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
kadonotakashi 0:8fdf9a60065b 176 return; // invalid index
kadonotakashi 0:8fdf9a60065b 177 }
kadonotakashi 0:8fdf9a60065b 178
kadonotakashi 0:8fdf9a60065b 179 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
kadonotakashi 0:8fdf9a60065b 180 }
kadonotakashi 0:8fdf9a60065b 181
kadonotakashi 0:8fdf9a60065b 182 /** Set the memory attribute encoding.
kadonotakashi 0:8fdf9a60065b 183 * \param idx The attribute index to be set [0-7]
kadonotakashi 0:8fdf9a60065b 184 * \param attr The attribute value to be set.
kadonotakashi 0:8fdf9a60065b 185 */
kadonotakashi 0:8fdf9a60065b 186 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
kadonotakashi 0:8fdf9a60065b 187 {
kadonotakashi 0:8fdf9a60065b 188 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
kadonotakashi 0:8fdf9a60065b 189 }
kadonotakashi 0:8fdf9a60065b 190
kadonotakashi 0:8fdf9a60065b 191 #ifdef MPU_NS
kadonotakashi 0:8fdf9a60065b 192 /** Set the memory attribute encoding to the Non-secure MPU.
kadonotakashi 0:8fdf9a60065b 193 * \param idx The attribute index to be set [0-7]
kadonotakashi 0:8fdf9a60065b 194 * \param attr The attribute value to be set.
kadonotakashi 0:8fdf9a60065b 195 */
kadonotakashi 0:8fdf9a60065b 196 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
kadonotakashi 0:8fdf9a60065b 197 {
kadonotakashi 0:8fdf9a60065b 198 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
kadonotakashi 0:8fdf9a60065b 199 }
kadonotakashi 0:8fdf9a60065b 200 #endif
kadonotakashi 0:8fdf9a60065b 201
kadonotakashi 0:8fdf9a60065b 202 /** Clear and disable the given MPU region of the given MPU.
kadonotakashi 0:8fdf9a60065b 203 * \param mpu Pointer to MPU to be used.
kadonotakashi 0:8fdf9a60065b 204 * \param rnr Region number to be cleared.
kadonotakashi 0:8fdf9a60065b 205 */
kadonotakashi 0:8fdf9a60065b 206 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
kadonotakashi 0:8fdf9a60065b 207 {
kadonotakashi 0:8fdf9a60065b 208 mpu->RNR = rnr;
kadonotakashi 0:8fdf9a60065b 209 mpu->RLAR = 0U;
kadonotakashi 0:8fdf9a60065b 210 }
kadonotakashi 0:8fdf9a60065b 211
kadonotakashi 0:8fdf9a60065b 212 /** Clear and disable the given MPU region.
kadonotakashi 0:8fdf9a60065b 213 * \param rnr Region number to be cleared.
kadonotakashi 0:8fdf9a60065b 214 */
kadonotakashi 0:8fdf9a60065b 215 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
kadonotakashi 0:8fdf9a60065b 216 {
kadonotakashi 0:8fdf9a60065b 217 ARM_MPU_ClrRegionEx(MPU, rnr);
kadonotakashi 0:8fdf9a60065b 218 }
kadonotakashi 0:8fdf9a60065b 219
kadonotakashi 0:8fdf9a60065b 220 #ifdef MPU_NS
kadonotakashi 0:8fdf9a60065b 221 /** Clear and disable the given Non-secure MPU region.
kadonotakashi 0:8fdf9a60065b 222 * \param rnr Region number to be cleared.
kadonotakashi 0:8fdf9a60065b 223 */
kadonotakashi 0:8fdf9a60065b 224 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
kadonotakashi 0:8fdf9a60065b 225 {
kadonotakashi 0:8fdf9a60065b 226 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
kadonotakashi 0:8fdf9a60065b 227 }
kadonotakashi 0:8fdf9a60065b 228 #endif
kadonotakashi 0:8fdf9a60065b 229
kadonotakashi 0:8fdf9a60065b 230 /** Configure the given MPU region of the given MPU.
kadonotakashi 0:8fdf9a60065b 231 * \param mpu Pointer to MPU to be used.
kadonotakashi 0:8fdf9a60065b 232 * \param rnr Region number to be configured.
kadonotakashi 0:8fdf9a60065b 233 * \param rbar Value for RBAR register.
kadonotakashi 0:8fdf9a60065b 234 * \param rlar Value for RLAR register.
kadonotakashi 0:8fdf9a60065b 235 */
kadonotakashi 0:8fdf9a60065b 236 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
kadonotakashi 0:8fdf9a60065b 237 {
kadonotakashi 0:8fdf9a60065b 238 mpu->RNR = rnr;
kadonotakashi 0:8fdf9a60065b 239 mpu->RBAR = rbar;
kadonotakashi 0:8fdf9a60065b 240 mpu->RLAR = rlar;
kadonotakashi 0:8fdf9a60065b 241 }
kadonotakashi 0:8fdf9a60065b 242
kadonotakashi 0:8fdf9a60065b 243 /** Configure the given MPU region.
kadonotakashi 0:8fdf9a60065b 244 * \param rnr Region number to be configured.
kadonotakashi 0:8fdf9a60065b 245 * \param rbar Value for RBAR register.
kadonotakashi 0:8fdf9a60065b 246 * \param rlar Value for RLAR register.
kadonotakashi 0:8fdf9a60065b 247 */
kadonotakashi 0:8fdf9a60065b 248 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
kadonotakashi 0:8fdf9a60065b 249 {
kadonotakashi 0:8fdf9a60065b 250 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
kadonotakashi 0:8fdf9a60065b 251 }
kadonotakashi 0:8fdf9a60065b 252
kadonotakashi 0:8fdf9a60065b 253 #ifdef MPU_NS
kadonotakashi 0:8fdf9a60065b 254 /** Configure the given Non-secure MPU region.
kadonotakashi 0:8fdf9a60065b 255 * \param rnr Region number to be configured.
kadonotakashi 0:8fdf9a60065b 256 * \param rbar Value for RBAR register.
kadonotakashi 0:8fdf9a60065b 257 * \param rlar Value for RLAR register.
kadonotakashi 0:8fdf9a60065b 258 */
kadonotakashi 0:8fdf9a60065b 259 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
kadonotakashi 0:8fdf9a60065b 260 {
kadonotakashi 0:8fdf9a60065b 261 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
kadonotakashi 0:8fdf9a60065b 262 }
kadonotakashi 0:8fdf9a60065b 263 #endif
kadonotakashi 0:8fdf9a60065b 264
kadonotakashi 0:8fdf9a60065b 265 /** Memcopy with strictly ordered memory access, e.g. for register targets.
kadonotakashi 0:8fdf9a60065b 266 * \param dst Destination data is copied to.
kadonotakashi 0:8fdf9a60065b 267 * \param src Source data is copied from.
kadonotakashi 0:8fdf9a60065b 268 * \param len Amount of data words to be copied.
kadonotakashi 0:8fdf9a60065b 269 */
kadonotakashi 0:8fdf9a60065b 270 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
kadonotakashi 0:8fdf9a60065b 271 {
kadonotakashi 0:8fdf9a60065b 272 uint32_t i;
kadonotakashi 0:8fdf9a60065b 273 for (i = 0U; i < len; ++i)
kadonotakashi 0:8fdf9a60065b 274 {
kadonotakashi 0:8fdf9a60065b 275 dst[i] = src[i];
kadonotakashi 0:8fdf9a60065b 276 }
kadonotakashi 0:8fdf9a60065b 277 }
kadonotakashi 0:8fdf9a60065b 278
kadonotakashi 0:8fdf9a60065b 279 /** Load the given number of MPU regions from a table to the given MPU.
kadonotakashi 0:8fdf9a60065b 280 * \param mpu Pointer to the MPU registers to be used.
kadonotakashi 0:8fdf9a60065b 281 * \param rnr First region number to be configured.
kadonotakashi 0:8fdf9a60065b 282 * \param table Pointer to the MPU configuration table.
kadonotakashi 0:8fdf9a60065b 283 * \param cnt Amount of regions to be configured.
kadonotakashi 0:8fdf9a60065b 284 */
kadonotakashi 0:8fdf9a60065b 285 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
kadonotakashi 0:8fdf9a60065b 286 {
kadonotakashi 0:8fdf9a60065b 287 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
kadonotakashi 0:8fdf9a60065b 288 if (cnt == 1U) {
kadonotakashi 0:8fdf9a60065b 289 mpu->RNR = rnr;
kadonotakashi 0:8fdf9a60065b 290 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
kadonotakashi 0:8fdf9a60065b 291 } else {
kadonotakashi 0:8fdf9a60065b 292 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
kadonotakashi 0:8fdf9a60065b 293 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
kadonotakashi 0:8fdf9a60065b 294
kadonotakashi 0:8fdf9a60065b 295 mpu->RNR = rnrBase;
kadonotakashi 0:8fdf9a60065b 296 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
kadonotakashi 0:8fdf9a60065b 297 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
kadonotakashi 0:8fdf9a60065b 298 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
kadonotakashi 0:8fdf9a60065b 299 table += c;
kadonotakashi 0:8fdf9a60065b 300 cnt -= c;
kadonotakashi 0:8fdf9a60065b 301 rnrOffset = 0U;
kadonotakashi 0:8fdf9a60065b 302 rnrBase += MPU_TYPE_RALIASES;
kadonotakashi 0:8fdf9a60065b 303 mpu->RNR = rnrBase;
kadonotakashi 0:8fdf9a60065b 304 }
kadonotakashi 0:8fdf9a60065b 305
kadonotakashi 0:8fdf9a60065b 306 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
kadonotakashi 0:8fdf9a60065b 307 }
kadonotakashi 0:8fdf9a60065b 308 }
kadonotakashi 0:8fdf9a60065b 309
kadonotakashi 0:8fdf9a60065b 310 /** Load the given number of MPU regions from a table.
kadonotakashi 0:8fdf9a60065b 311 * \param rnr First region number to be configured.
kadonotakashi 0:8fdf9a60065b 312 * \param table Pointer to the MPU configuration table.
kadonotakashi 0:8fdf9a60065b 313 * \param cnt Amount of regions to be configured.
kadonotakashi 0:8fdf9a60065b 314 */
kadonotakashi 0:8fdf9a60065b 315 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
kadonotakashi 0:8fdf9a60065b 316 {
kadonotakashi 0:8fdf9a60065b 317 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
kadonotakashi 0:8fdf9a60065b 318 }
kadonotakashi 0:8fdf9a60065b 319
kadonotakashi 0:8fdf9a60065b 320 #ifdef MPU_NS
kadonotakashi 0:8fdf9a60065b 321 /** Load the given number of MPU regions from a table to the Non-secure MPU.
kadonotakashi 0:8fdf9a60065b 322 * \param rnr First region number to be configured.
kadonotakashi 0:8fdf9a60065b 323 * \param table Pointer to the MPU configuration table.
kadonotakashi 0:8fdf9a60065b 324 * \param cnt Amount of regions to be configured.
kadonotakashi 0:8fdf9a60065b 325 */
kadonotakashi 0:8fdf9a60065b 326 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
kadonotakashi 0:8fdf9a60065b 327 {
kadonotakashi 0:8fdf9a60065b 328 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
kadonotakashi 0:8fdf9a60065b 329 }
kadonotakashi 0:8fdf9a60065b 330 #endif
kadonotakashi 0:8fdf9a60065b 331
kadonotakashi 0:8fdf9a60065b 332 #endif
kadonotakashi 0:8fdf9a60065b 333