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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

mbed-os/cmsis/TARGET_CORTEX_M/core_cm7.h@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:: kadonotakashi
Date:: Wed Oct 10 00:33:53 2018 +0000
Revision:: 0:8fdf9a60065b

how to make mbed librry

Who changed what in which revision?

User	Revision	Line number	New contents of line
kadonotakashi	0:8fdf9a60065b	1	/************************************************************************//
kadonotakashi	0:8fdf9a60065b	2	* @file core_cm7.h
kadonotakashi	0:8fdf9a60065b	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
kadonotakashi	0:8fdf9a60065b	4	* @version V5.0.8
kadonotakashi	0:8fdf9a60065b	5	* @date 04. June 2018
kadonotakashi	0:8fdf9a60065b	6	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	7	/*
kadonotakashi	0:8fdf9a60065b	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
kadonotakashi	0:8fdf9a60065b	9	*
kadonotakashi	0:8fdf9a60065b	10	* SPDX-License-Identifier: Apache-2.0
kadonotakashi	0:8fdf9a60065b	11	*
kadonotakashi	0:8fdf9a60065b	12	* Licensed under the Apache License, Version 2.0 (the License); you may
kadonotakashi	0:8fdf9a60065b	13	* not use this file except in compliance with the License.
kadonotakashi	0:8fdf9a60065b	14	* You may obtain a copy of the License at
kadonotakashi	0:8fdf9a60065b	15	*
kadonotakashi	0:8fdf9a60065b	16	* www.apache.org/licenses/LICENSE-2.0
kadonotakashi	0:8fdf9a60065b	17	*
kadonotakashi	0:8fdf9a60065b	18	* Unless required by applicable law or agreed to in writing, software
kadonotakashi	0:8fdf9a60065b	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
kadonotakashi	0:8fdf9a60065b	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi	0:8fdf9a60065b	21	* See the License for the specific language governing permissions and
kadonotakashi	0:8fdf9a60065b	22	* limitations under the License.
kadonotakashi	0:8fdf9a60065b	23	*/
kadonotakashi	0:8fdf9a60065b	24
kadonotakashi	0:8fdf9a60065b	25	#if defined ( __ICCARM__ )
kadonotakashi	0:8fdf9a60065b	26	#pragma system_include /* treat file as system include file for MISRA check */
kadonotakashi	0:8fdf9a60065b	27	#elif defined (__clang__)
kadonotakashi	0:8fdf9a60065b	28	#pragma clang system_header /* treat file as system include file */
kadonotakashi	0:8fdf9a60065b	29	#endif
kadonotakashi	0:8fdf9a60065b	30
kadonotakashi	0:8fdf9a60065b	31	#ifndef __CORE_CM7_H_GENERIC
kadonotakashi	0:8fdf9a60065b	32	#define __CORE_CM7_H_GENERIC
kadonotakashi	0:8fdf9a60065b	33
kadonotakashi	0:8fdf9a60065b	34	#include <stdint.h>
kadonotakashi	0:8fdf9a60065b	35
kadonotakashi	0:8fdf9a60065b	36	#ifdef __cplusplus
kadonotakashi	0:8fdf9a60065b	37	extern "C" {
kadonotakashi	0:8fdf9a60065b	38	#endif
kadonotakashi	0:8fdf9a60065b	39
kadonotakashi	0:8fdf9a60065b	40	/**
kadonotakashi	0:8fdf9a60065b	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
kadonotakashi	0:8fdf9a60065b	42	CMSIS violates the following MISRA-C:2004 rules:
kadonotakashi	0:8fdf9a60065b	43
kadonotakashi	0:8fdf9a60065b	44	\li Required Rule 8.5, object/function definition in header file.<br>
kadonotakashi	0:8fdf9a60065b	45	Function definitions in header files are used to allow 'inlining'.
kadonotakashi	0:8fdf9a60065b	46
kadonotakashi	0:8fdf9a60065b	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
kadonotakashi	0:8fdf9a60065b	48	Unions are used for effective representation of core registers.
kadonotakashi	0:8fdf9a60065b	49
kadonotakashi	0:8fdf9a60065b	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
kadonotakashi	0:8fdf9a60065b	51	Function-like macros are used to allow more efficient code.
kadonotakashi	0:8fdf9a60065b	52	*/
kadonotakashi	0:8fdf9a60065b	53
kadonotakashi	0:8fdf9a60065b	54
kadonotakashi	0:8fdf9a60065b	55	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	56	* CMSIS definitions
kadonotakashi	0:8fdf9a60065b	57	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	58	/**
kadonotakashi	0:8fdf9a60065b	59	\ingroup Cortex_M7
kadonotakashi	0:8fdf9a60065b	60	@{
kadonotakashi	0:8fdf9a60065b	61	*/
kadonotakashi	0:8fdf9a60065b	62
kadonotakashi	0:8fdf9a60065b	63	#include "cmsis_version.h"
kadonotakashi	0:8fdf9a60065b	64
kadonotakashi	0:8fdf9a60065b	65	/* CMSIS CM7 definitions */
kadonotakashi	0:8fdf9a60065b	66	#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
kadonotakashi	0:8fdf9a60065b	67	#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
kadonotakashi	0:8fdf9a60065b	68	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) \| \
kadonotakashi	0:8fdf9a60065b	69	__CM7_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
kadonotakashi	0:8fdf9a60065b	70
kadonotakashi	0:8fdf9a60065b	71	#define __CORTEX_M (7U) /!< Cortex-M Core /
kadonotakashi	0:8fdf9a60065b	72
kadonotakashi	0:8fdf9a60065b	73	/** __FPU_USED indicates whether an FPU is used or not.
kadonotakashi	0:8fdf9a60065b	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
kadonotakashi	0:8fdf9a60065b	75	*/
kadonotakashi	0:8fdf9a60065b	76	#if defined ( __CC_ARM )
kadonotakashi	0:8fdf9a60065b	77	#if defined __TARGET_FPU_VFP
kadonotakashi	0:8fdf9a60065b	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	79	#define __FPU_USED 1U
kadonotakashi	0:8fdf9a60065b	80	#else
kadonotakashi	0:8fdf9a60065b	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	82	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	83	#endif
kadonotakashi	0:8fdf9a60065b	84	#else
kadonotakashi	0:8fdf9a60065b	85	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	86	#endif
kadonotakashi	0:8fdf9a60065b	87
kadonotakashi	0:8fdf9a60065b	88	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
kadonotakashi	0:8fdf9a60065b	89	#if defined __ARM_PCS_VFP
kadonotakashi	0:8fdf9a60065b	90	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	91	#define __FPU_USED 1U
kadonotakashi	0:8fdf9a60065b	92	#else
kadonotakashi	0:8fdf9a60065b	93	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	94	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	95	#endif
kadonotakashi	0:8fdf9a60065b	96	#else
kadonotakashi	0:8fdf9a60065b	97	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	98	#endif
kadonotakashi	0:8fdf9a60065b	99
kadonotakashi	0:8fdf9a60065b	100	#elif defined ( __GNUC__ )
kadonotakashi	0:8fdf9a60065b	101	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
kadonotakashi	0:8fdf9a60065b	102	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	103	#define __FPU_USED 1U
kadonotakashi	0:8fdf9a60065b	104	#else
kadonotakashi	0:8fdf9a60065b	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	106	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	107	#endif
kadonotakashi	0:8fdf9a60065b	108	#else
kadonotakashi	0:8fdf9a60065b	109	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	110	#endif
kadonotakashi	0:8fdf9a60065b	111
kadonotakashi	0:8fdf9a60065b	112	#elif defined ( __ICCARM__ )
kadonotakashi	0:8fdf9a60065b	113	#if defined __ARMVFP__
kadonotakashi	0:8fdf9a60065b	114	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	115	#define __FPU_USED 1U
kadonotakashi	0:8fdf9a60065b	116	#else
kadonotakashi	0:8fdf9a60065b	117	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	118	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	119	#endif
kadonotakashi	0:8fdf9a60065b	120	#else
kadonotakashi	0:8fdf9a60065b	121	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	122	#endif
kadonotakashi	0:8fdf9a60065b	123
kadonotakashi	0:8fdf9a60065b	124	#elif defined ( __TI_ARM__ )
kadonotakashi	0:8fdf9a60065b	125	#if defined __TI_VFP_SUPPORT__
kadonotakashi	0:8fdf9a60065b	126	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	127	#define __FPU_USED 1U
kadonotakashi	0:8fdf9a60065b	128	#else
kadonotakashi	0:8fdf9a60065b	129	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	130	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	131	#endif
kadonotakashi	0:8fdf9a60065b	132	#else
kadonotakashi	0:8fdf9a60065b	133	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	134	#endif
kadonotakashi	0:8fdf9a60065b	135
kadonotakashi	0:8fdf9a60065b	136	#elif defined ( __TASKING__ )
kadonotakashi	0:8fdf9a60065b	137	#if defined __FPU_VFP__
kadonotakashi	0:8fdf9a60065b	138	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	139	#define __FPU_USED 1U
kadonotakashi	0:8fdf9a60065b	140	#else
kadonotakashi	0:8fdf9a60065b	141	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	142	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	143	#endif
kadonotakashi	0:8fdf9a60065b	144	#else
kadonotakashi	0:8fdf9a60065b	145	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	146	#endif
kadonotakashi	0:8fdf9a60065b	147
kadonotakashi	0:8fdf9a60065b	148	#elif defined ( __CSMC__ )
kadonotakashi	0:8fdf9a60065b	149	#if ( __CSMC__ & 0x400U)
kadonotakashi	0:8fdf9a60065b	150	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	151	#define __FPU_USED 1U
kadonotakashi	0:8fdf9a60065b	152	#else
kadonotakashi	0:8fdf9a60065b	153	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	154	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	155	#endif
kadonotakashi	0:8fdf9a60065b	156	#else
kadonotakashi	0:8fdf9a60065b	157	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	158	#endif
kadonotakashi	0:8fdf9a60065b	159
kadonotakashi	0:8fdf9a60065b	160	#endif
kadonotakashi	0:8fdf9a60065b	161
kadonotakashi	0:8fdf9a60065b	162	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
kadonotakashi	0:8fdf9a60065b	163
kadonotakashi	0:8fdf9a60065b	164
kadonotakashi	0:8fdf9a60065b	165	#ifdef __cplusplus
kadonotakashi	0:8fdf9a60065b	166	}
kadonotakashi	0:8fdf9a60065b	167	#endif
kadonotakashi	0:8fdf9a60065b	168
kadonotakashi	0:8fdf9a60065b	169	#endif /* __CORE_CM7_H_GENERIC */
kadonotakashi	0:8fdf9a60065b	170
kadonotakashi	0:8fdf9a60065b	171	#ifndef __CMSIS_GENERIC
kadonotakashi	0:8fdf9a60065b	172
kadonotakashi	0:8fdf9a60065b	173	#ifndef __CORE_CM7_H_DEPENDANT
kadonotakashi	0:8fdf9a60065b	174	#define __CORE_CM7_H_DEPENDANT
kadonotakashi	0:8fdf9a60065b	175
kadonotakashi	0:8fdf9a60065b	176	#ifdef __cplusplus
kadonotakashi	0:8fdf9a60065b	177	extern "C" {
kadonotakashi	0:8fdf9a60065b	178	#endif
kadonotakashi	0:8fdf9a60065b	179
kadonotakashi	0:8fdf9a60065b	180	/* check device defines and use defaults */
kadonotakashi	0:8fdf9a60065b	181	#if defined __CHECK_DEVICE_DEFINES
kadonotakashi	0:8fdf9a60065b	182	#ifndef __CM7_REV
kadonotakashi	0:8fdf9a60065b	183	#define __CM7_REV 0x0000U
kadonotakashi	0:8fdf9a60065b	184	#warning "__CM7_REV not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	185	#endif
kadonotakashi	0:8fdf9a60065b	186
kadonotakashi	0:8fdf9a60065b	187	#ifndef __FPU_PRESENT
kadonotakashi	0:8fdf9a60065b	188	#define __FPU_PRESENT 0U
kadonotakashi	0:8fdf9a60065b	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	190	#endif
kadonotakashi	0:8fdf9a60065b	191
kadonotakashi	0:8fdf9a60065b	192	#ifndef __MPU_PRESENT
kadonotakashi	0:8fdf9a60065b	193	#define __MPU_PRESENT 0U
kadonotakashi	0:8fdf9a60065b	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	195	#endif
kadonotakashi	0:8fdf9a60065b	196
kadonotakashi	0:8fdf9a60065b	197	#ifndef __ICACHE_PRESENT
kadonotakashi	0:8fdf9a60065b	198	#define __ICACHE_PRESENT 0U
kadonotakashi	0:8fdf9a60065b	199	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	200	#endif
kadonotakashi	0:8fdf9a60065b	201
kadonotakashi	0:8fdf9a60065b	202	#ifndef __DCACHE_PRESENT
kadonotakashi	0:8fdf9a60065b	203	#define __DCACHE_PRESENT 0U
kadonotakashi	0:8fdf9a60065b	204	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	205	#endif
kadonotakashi	0:8fdf9a60065b	206
kadonotakashi	0:8fdf9a60065b	207	#ifndef __DTCM_PRESENT
kadonotakashi	0:8fdf9a60065b	208	#define __DTCM_PRESENT 0U
kadonotakashi	0:8fdf9a60065b	209	#warning "__DTCM_PRESENT not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	210	#endif
kadonotakashi	0:8fdf9a60065b	211
kadonotakashi	0:8fdf9a60065b	212	#ifndef __NVIC_PRIO_BITS
kadonotakashi	0:8fdf9a60065b	213	#define __NVIC_PRIO_BITS 3U
kadonotakashi	0:8fdf9a60065b	214	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	215	#endif
kadonotakashi	0:8fdf9a60065b	216
kadonotakashi	0:8fdf9a60065b	217	#ifndef __Vendor_SysTickConfig
kadonotakashi	0:8fdf9a60065b	218	#define __Vendor_SysTickConfig 0U
kadonotakashi	0:8fdf9a60065b	219	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	220	#endif
kadonotakashi	0:8fdf9a60065b	221	#endif
kadonotakashi	0:8fdf9a60065b	222
kadonotakashi	0:8fdf9a60065b	223	/* IO definitions (access restrictions to peripheral registers) */
kadonotakashi	0:8fdf9a60065b	224	/**
kadonotakashi	0:8fdf9a60065b	225	\defgroup CMSIS_glob_defs CMSIS Global Defines
kadonotakashi	0:8fdf9a60065b	226
kadonotakashi	0:8fdf9a60065b	227	<strong>IO Type Qualifiers</strong> are used
kadonotakashi	0:8fdf9a60065b	228	\li to specify the access to peripheral variables.
kadonotakashi	0:8fdf9a60065b	229	\li for automatic generation of peripheral register debug information.
kadonotakashi	0:8fdf9a60065b	230	*/
kadonotakashi	0:8fdf9a60065b	231	#ifdef __cplusplus
kadonotakashi	0:8fdf9a60065b	232	#define __I volatile /!< Defines 'read only' permissions /
kadonotakashi	0:8fdf9a60065b	233	#else
kadonotakashi	0:8fdf9a60065b	234	#define __I volatile const /!< Defines 'read only' permissions /
kadonotakashi	0:8fdf9a60065b	235	#endif
kadonotakashi	0:8fdf9a60065b	236	#define __O volatile /!< Defines 'write only' permissions /
kadonotakashi	0:8fdf9a60065b	237	#define __IO volatile /!< Defines 'read / write' permissions /
kadonotakashi	0:8fdf9a60065b	238
kadonotakashi	0:8fdf9a60065b	239	/* following defines should be used for structure members */
kadonotakashi	0:8fdf9a60065b	240	#define __IM volatile const /! Defines 'read only' structure member permissions /
kadonotakashi	0:8fdf9a60065b	241	#define __OM volatile /! Defines 'write only' structure member permissions /
kadonotakashi	0:8fdf9a60065b	242	#define __IOM volatile /! Defines 'read / write' structure member permissions /
kadonotakashi	0:8fdf9a60065b	243
kadonotakashi	0:8fdf9a60065b	244	/@} end of group Cortex_M7 /
kadonotakashi	0:8fdf9a60065b	245
kadonotakashi	0:8fdf9a60065b	246
kadonotakashi	0:8fdf9a60065b	247
kadonotakashi	0:8fdf9a60065b	248	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	249	* Register Abstraction
kadonotakashi	0:8fdf9a60065b	250	Core Register contain:
kadonotakashi	0:8fdf9a60065b	251	- Core Register
kadonotakashi	0:8fdf9a60065b	252	- Core NVIC Register
kadonotakashi	0:8fdf9a60065b	253	- Core SCB Register
kadonotakashi	0:8fdf9a60065b	254	- Core SysTick Register
kadonotakashi	0:8fdf9a60065b	255	- Core Debug Register
kadonotakashi	0:8fdf9a60065b	256	- Core MPU Register
kadonotakashi	0:8fdf9a60065b	257	- Core FPU Register
kadonotakashi	0:8fdf9a60065b	258	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	259	/**
kadonotakashi	0:8fdf9a60065b	260	\defgroup CMSIS_core_register Defines and Type Definitions
kadonotakashi	0:8fdf9a60065b	261	\brief Type definitions and defines for Cortex-M processor based devices.
kadonotakashi	0:8fdf9a60065b	262	*/
kadonotakashi	0:8fdf9a60065b	263
kadonotakashi	0:8fdf9a60065b	264	/**
kadonotakashi	0:8fdf9a60065b	265	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	266	\defgroup CMSIS_CORE Status and Control Registers
kadonotakashi	0:8fdf9a60065b	267	\brief Core Register type definitions.
kadonotakashi	0:8fdf9a60065b	268	@{
kadonotakashi	0:8fdf9a60065b	269	*/
kadonotakashi	0:8fdf9a60065b	270
kadonotakashi	0:8fdf9a60065b	271	/**
kadonotakashi	0:8fdf9a60065b	272	\brief Union type to access the Application Program Status Register (APSR).
kadonotakashi	0:8fdf9a60065b	273	*/
kadonotakashi	0:8fdf9a60065b	274	typedef union
kadonotakashi	0:8fdf9a60065b	275	{
kadonotakashi	0:8fdf9a60065b	276	struct
kadonotakashi	0:8fdf9a60065b	277	{
kadonotakashi	0:8fdf9a60065b	278	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
kadonotakashi	0:8fdf9a60065b	279	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
kadonotakashi	0:8fdf9a60065b	280	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
kadonotakashi	0:8fdf9a60065b	281	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
kadonotakashi	0:8fdf9a60065b	282	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
kadonotakashi	0:8fdf9a60065b	283	uint32_t C:1; /!< bit: 29 Carry condition code flag /
kadonotakashi	0:8fdf9a60065b	284	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
kadonotakashi	0:8fdf9a60065b	285	uint32_t N:1; /!< bit: 31 Negative condition code flag /
kadonotakashi	0:8fdf9a60065b	286	} b; /!< Structure used for bit access /
kadonotakashi	0:8fdf9a60065b	287	uint32_t w; /!< Type used for word access /
kadonotakashi	0:8fdf9a60065b	288	} APSR_Type;
kadonotakashi	0:8fdf9a60065b	289
kadonotakashi	0:8fdf9a60065b	290	/* APSR Register Definitions */
kadonotakashi	0:8fdf9a60065b	291	#define APSR_N_Pos 31U /!< APSR: N Position /
kadonotakashi	0:8fdf9a60065b	292	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
kadonotakashi	0:8fdf9a60065b	293
kadonotakashi	0:8fdf9a60065b	294	#define APSR_Z_Pos 30U /!< APSR: Z Position /
kadonotakashi	0:8fdf9a60065b	295	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
kadonotakashi	0:8fdf9a60065b	296
kadonotakashi	0:8fdf9a60065b	297	#define APSR_C_Pos 29U /!< APSR: C Position /
kadonotakashi	0:8fdf9a60065b	298	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
kadonotakashi	0:8fdf9a60065b	299
kadonotakashi	0:8fdf9a60065b	300	#define APSR_V_Pos 28U /!< APSR: V Position /
kadonotakashi	0:8fdf9a60065b	301	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
kadonotakashi	0:8fdf9a60065b	302
kadonotakashi	0:8fdf9a60065b	303	#define APSR_Q_Pos 27U /!< APSR: Q Position /
kadonotakashi	0:8fdf9a60065b	304	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
kadonotakashi	0:8fdf9a60065b	305
kadonotakashi	0:8fdf9a60065b	306	#define APSR_GE_Pos 16U /!< APSR: GE Position /
kadonotakashi	0:8fdf9a60065b	307	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
kadonotakashi	0:8fdf9a60065b	308
kadonotakashi	0:8fdf9a60065b	309
kadonotakashi	0:8fdf9a60065b	310	/**
kadonotakashi	0:8fdf9a60065b	311	\brief Union type to access the Interrupt Program Status Register (IPSR).
kadonotakashi	0:8fdf9a60065b	312	*/
kadonotakashi	0:8fdf9a60065b	313	typedef union
kadonotakashi	0:8fdf9a60065b	314	{
kadonotakashi	0:8fdf9a60065b	315	struct
kadonotakashi	0:8fdf9a60065b	316	{
kadonotakashi	0:8fdf9a60065b	317	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
kadonotakashi	0:8fdf9a60065b	318	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
kadonotakashi	0:8fdf9a60065b	319	} b; /!< Structure used for bit access /
kadonotakashi	0:8fdf9a60065b	320	uint32_t w; /!< Type used for word access /
kadonotakashi	0:8fdf9a60065b	321	} IPSR_Type;
kadonotakashi	0:8fdf9a60065b	322
kadonotakashi	0:8fdf9a60065b	323	/* IPSR Register Definitions */
kadonotakashi	0:8fdf9a60065b	324	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
kadonotakashi	0:8fdf9a60065b	325	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
kadonotakashi	0:8fdf9a60065b	326
kadonotakashi	0:8fdf9a60065b	327
kadonotakashi	0:8fdf9a60065b	328	/**
kadonotakashi	0:8fdf9a60065b	329	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
kadonotakashi	0:8fdf9a60065b	330	*/
kadonotakashi	0:8fdf9a60065b	331	typedef union
kadonotakashi	0:8fdf9a60065b	332	{
kadonotakashi	0:8fdf9a60065b	333	struct
kadonotakashi	0:8fdf9a60065b	334	{
kadonotakashi	0:8fdf9a60065b	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
kadonotakashi	0:8fdf9a60065b	336	uint32_t _reserved0:1; /!< bit: 9 Reserved /
kadonotakashi	0:8fdf9a60065b	337	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
kadonotakashi	0:8fdf9a60065b	338	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
kadonotakashi	0:8fdf9a60065b	339	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
kadonotakashi	0:8fdf9a60065b	340	uint32_t T:1; /!< bit: 24 Thumb bit /
kadonotakashi	0:8fdf9a60065b	341	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
kadonotakashi	0:8fdf9a60065b	342	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
kadonotakashi	0:8fdf9a60065b	343	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
kadonotakashi	0:8fdf9a60065b	344	uint32_t C:1; /!< bit: 29 Carry condition code flag /
kadonotakashi	0:8fdf9a60065b	345	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
kadonotakashi	0:8fdf9a60065b	346	uint32_t N:1; /!< bit: 31 Negative condition code flag /
kadonotakashi	0:8fdf9a60065b	347	} b; /!< Structure used for bit access /
kadonotakashi	0:8fdf9a60065b	348	uint32_t w; /!< Type used for word access /
kadonotakashi	0:8fdf9a60065b	349	} xPSR_Type;
kadonotakashi	0:8fdf9a60065b	350
kadonotakashi	0:8fdf9a60065b	351	/* xPSR Register Definitions */
kadonotakashi	0:8fdf9a60065b	352	#define xPSR_N_Pos 31U /!< xPSR: N Position /
kadonotakashi	0:8fdf9a60065b	353	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
kadonotakashi	0:8fdf9a60065b	354
kadonotakashi	0:8fdf9a60065b	355	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
kadonotakashi	0:8fdf9a60065b	356	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
kadonotakashi	0:8fdf9a60065b	357
kadonotakashi	0:8fdf9a60065b	358	#define xPSR_C_Pos 29U /!< xPSR: C Position /
kadonotakashi	0:8fdf9a60065b	359	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
kadonotakashi	0:8fdf9a60065b	360
kadonotakashi	0:8fdf9a60065b	361	#define xPSR_V_Pos 28U /!< xPSR: V Position /
kadonotakashi	0:8fdf9a60065b	362	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
kadonotakashi	0:8fdf9a60065b	363
kadonotakashi	0:8fdf9a60065b	364	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
kadonotakashi	0:8fdf9a60065b	365	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
kadonotakashi	0:8fdf9a60065b	366
kadonotakashi	0:8fdf9a60065b	367	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
kadonotakashi	0:8fdf9a60065b	368	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
kadonotakashi	0:8fdf9a60065b	369
kadonotakashi	0:8fdf9a60065b	370	#define xPSR_T_Pos 24U /!< xPSR: T Position /
kadonotakashi	0:8fdf9a60065b	371	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
kadonotakashi	0:8fdf9a60065b	372
kadonotakashi	0:8fdf9a60065b	373	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
kadonotakashi	0:8fdf9a60065b	374	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
kadonotakashi	0:8fdf9a60065b	375
kadonotakashi	0:8fdf9a60065b	376	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
kadonotakashi	0:8fdf9a60065b	377	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
kadonotakashi	0:8fdf9a60065b	378
kadonotakashi	0:8fdf9a60065b	379	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
kadonotakashi	0:8fdf9a60065b	380	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
kadonotakashi	0:8fdf9a60065b	381
kadonotakashi	0:8fdf9a60065b	382
kadonotakashi	0:8fdf9a60065b	383	/**
kadonotakashi	0:8fdf9a60065b	384	\brief Union type to access the Control Registers (CONTROL).
kadonotakashi	0:8fdf9a60065b	385	*/
kadonotakashi	0:8fdf9a60065b	386	typedef union
kadonotakashi	0:8fdf9a60065b	387	{
kadonotakashi	0:8fdf9a60065b	388	struct
kadonotakashi	0:8fdf9a60065b	389	{
kadonotakashi	0:8fdf9a60065b	390	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
kadonotakashi	0:8fdf9a60065b	391	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
kadonotakashi	0:8fdf9a60065b	392	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
kadonotakashi	0:8fdf9a60065b	393	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
kadonotakashi	0:8fdf9a60065b	394	} b; /!< Structure used for bit access /
kadonotakashi	0:8fdf9a60065b	395	uint32_t w; /!< Type used for word access /
kadonotakashi	0:8fdf9a60065b	396	} CONTROL_Type;
kadonotakashi	0:8fdf9a60065b	397
kadonotakashi	0:8fdf9a60065b	398	/* CONTROL Register Definitions */
kadonotakashi	0:8fdf9a60065b	399	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
kadonotakashi	0:8fdf9a60065b	400	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
kadonotakashi	0:8fdf9a60065b	401
kadonotakashi	0:8fdf9a60065b	402	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
kadonotakashi	0:8fdf9a60065b	403	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
kadonotakashi	0:8fdf9a60065b	404
kadonotakashi	0:8fdf9a60065b	405	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
kadonotakashi	0:8fdf9a60065b	406	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
kadonotakashi	0:8fdf9a60065b	407
kadonotakashi	0:8fdf9a60065b	408	/@} end of group CMSIS_CORE /
kadonotakashi	0:8fdf9a60065b	409
kadonotakashi	0:8fdf9a60065b	410
kadonotakashi	0:8fdf9a60065b	411	/**
kadonotakashi	0:8fdf9a60065b	412	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	413	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
kadonotakashi	0:8fdf9a60065b	414	\brief Type definitions for the NVIC Registers
kadonotakashi	0:8fdf9a60065b	415	@{
kadonotakashi	0:8fdf9a60065b	416	*/
kadonotakashi	0:8fdf9a60065b	417
kadonotakashi	0:8fdf9a60065b	418	/**
kadonotakashi	0:8fdf9a60065b	419	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
kadonotakashi	0:8fdf9a60065b	420	*/
kadonotakashi	0:8fdf9a60065b	421	typedef struct
kadonotakashi	0:8fdf9a60065b	422	{
kadonotakashi	0:8fdf9a60065b	423	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
kadonotakashi	0:8fdf9a60065b	424	uint32_t RESERVED0[24U];
kadonotakashi	0:8fdf9a60065b	425	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
kadonotakashi	0:8fdf9a60065b	426	uint32_t RSERVED1[24U];
kadonotakashi	0:8fdf9a60065b	427	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
kadonotakashi	0:8fdf9a60065b	428	uint32_t RESERVED2[24U];
kadonotakashi	0:8fdf9a60065b	429	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
kadonotakashi	0:8fdf9a60065b	430	uint32_t RESERVED3[24U];
kadonotakashi	0:8fdf9a60065b	431	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
kadonotakashi	0:8fdf9a60065b	432	uint32_t RESERVED4[56U];
kadonotakashi	0:8fdf9a60065b	433	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
kadonotakashi	0:8fdf9a60065b	434	uint32_t RESERVED5[644U];
kadonotakashi	0:8fdf9a60065b	435	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
kadonotakashi	0:8fdf9a60065b	436	} NVIC_Type;
kadonotakashi	0:8fdf9a60065b	437
kadonotakashi	0:8fdf9a60065b	438	/* Software Triggered Interrupt Register Definitions */
kadonotakashi	0:8fdf9a60065b	439	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
kadonotakashi	0:8fdf9a60065b	440	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
kadonotakashi	0:8fdf9a60065b	441
kadonotakashi	0:8fdf9a60065b	442	/@} end of group CMSIS_NVIC /
kadonotakashi	0:8fdf9a60065b	443
kadonotakashi	0:8fdf9a60065b	444
kadonotakashi	0:8fdf9a60065b	445	/**
kadonotakashi	0:8fdf9a60065b	446	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	447	\defgroup CMSIS_SCB System Control Block (SCB)
kadonotakashi	0:8fdf9a60065b	448	\brief Type definitions for the System Control Block Registers
kadonotakashi	0:8fdf9a60065b	449	@{
kadonotakashi	0:8fdf9a60065b	450	*/
kadonotakashi	0:8fdf9a60065b	451
kadonotakashi	0:8fdf9a60065b	452	/**
kadonotakashi	0:8fdf9a60065b	453	\brief Structure type to access the System Control Block (SCB).
kadonotakashi	0:8fdf9a60065b	454	*/
kadonotakashi	0:8fdf9a60065b	455	typedef struct
kadonotakashi	0:8fdf9a60065b	456	{
kadonotakashi	0:8fdf9a60065b	457	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
kadonotakashi	0:8fdf9a60065b	458	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
kadonotakashi	0:8fdf9a60065b	459	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
kadonotakashi	0:8fdf9a60065b	460	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
kadonotakashi	0:8fdf9a60065b	461	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
kadonotakashi	0:8fdf9a60065b	462	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
kadonotakashi	0:8fdf9a60065b	463	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
kadonotakashi	0:8fdf9a60065b	464	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
kadonotakashi	0:8fdf9a60065b	465	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
kadonotakashi	0:8fdf9a60065b	466	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
kadonotakashi	0:8fdf9a60065b	467	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
kadonotakashi	0:8fdf9a60065b	468	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
kadonotakashi	0:8fdf9a60065b	469	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
kadonotakashi	0:8fdf9a60065b	470	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
kadonotakashi	0:8fdf9a60065b	471	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
kadonotakashi	0:8fdf9a60065b	472	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
kadonotakashi	0:8fdf9a60065b	473	__IM uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
kadonotakashi	0:8fdf9a60065b	474	__IM uint32_t ID_MFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
kadonotakashi	0:8fdf9a60065b	475	__IM uint32_t ID_ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
kadonotakashi	0:8fdf9a60065b	476	uint32_t RESERVED0[1U];
kadonotakashi	0:8fdf9a60065b	477	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
kadonotakashi	0:8fdf9a60065b	478	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
kadonotakashi	0:8fdf9a60065b	479	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
kadonotakashi	0:8fdf9a60065b	480	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
kadonotakashi	0:8fdf9a60065b	481	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
kadonotakashi	0:8fdf9a60065b	482	uint32_t RESERVED3[93U];
kadonotakashi	0:8fdf9a60065b	483	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
kadonotakashi	0:8fdf9a60065b	484	uint32_t RESERVED4[15U];
kadonotakashi	0:8fdf9a60065b	485	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
kadonotakashi	0:8fdf9a60065b	486	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
kadonotakashi	0:8fdf9a60065b	487	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
kadonotakashi	0:8fdf9a60065b	488	uint32_t RESERVED5[1U];
kadonotakashi	0:8fdf9a60065b	489	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
kadonotakashi	0:8fdf9a60065b	490	uint32_t RESERVED6[1U];
kadonotakashi	0:8fdf9a60065b	491	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
kadonotakashi	0:8fdf9a60065b	492	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
kadonotakashi	0:8fdf9a60065b	493	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
kadonotakashi	0:8fdf9a60065b	494	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
kadonotakashi	0:8fdf9a60065b	495	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
kadonotakashi	0:8fdf9a60065b	496	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
kadonotakashi	0:8fdf9a60065b	497	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
kadonotakashi	0:8fdf9a60065b	498	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
kadonotakashi	0:8fdf9a60065b	499	uint32_t RESERVED7[6U];
kadonotakashi	0:8fdf9a60065b	500	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
kadonotakashi	0:8fdf9a60065b	501	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
kadonotakashi	0:8fdf9a60065b	502	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
kadonotakashi	0:8fdf9a60065b	503	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
kadonotakashi	0:8fdf9a60065b	504	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
kadonotakashi	0:8fdf9a60065b	505	uint32_t RESERVED8[1U];
kadonotakashi	0:8fdf9a60065b	506	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
kadonotakashi	0:8fdf9a60065b	507	} SCB_Type;
kadonotakashi	0:8fdf9a60065b	508
kadonotakashi	0:8fdf9a60065b	509	/* SCB CPUID Register Definitions */
kadonotakashi	0:8fdf9a60065b	510	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
kadonotakashi	0:8fdf9a60065b	511	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
kadonotakashi	0:8fdf9a60065b	512
kadonotakashi	0:8fdf9a60065b	513	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
kadonotakashi	0:8fdf9a60065b	514	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
kadonotakashi	0:8fdf9a60065b	515
kadonotakashi	0:8fdf9a60065b	516	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
kadonotakashi	0:8fdf9a60065b	517	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
kadonotakashi	0:8fdf9a60065b	518
kadonotakashi	0:8fdf9a60065b	519	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
kadonotakashi	0:8fdf9a60065b	520	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
kadonotakashi	0:8fdf9a60065b	521
kadonotakashi	0:8fdf9a60065b	522	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
kadonotakashi	0:8fdf9a60065b	523	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
kadonotakashi	0:8fdf9a60065b	524
kadonotakashi	0:8fdf9a60065b	525	/* SCB Interrupt Control State Register Definitions */
kadonotakashi	0:8fdf9a60065b	526	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
kadonotakashi	0:8fdf9a60065b	527	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
kadonotakashi	0:8fdf9a60065b	528
kadonotakashi	0:8fdf9a60065b	529	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
kadonotakashi	0:8fdf9a60065b	530	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
kadonotakashi	0:8fdf9a60065b	531
kadonotakashi	0:8fdf9a60065b	532	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
kadonotakashi	0:8fdf9a60065b	533	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
kadonotakashi	0:8fdf9a60065b	534
kadonotakashi	0:8fdf9a60065b	535	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
kadonotakashi	0:8fdf9a60065b	536	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
kadonotakashi	0:8fdf9a60065b	537
kadonotakashi	0:8fdf9a60065b	538	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
kadonotakashi	0:8fdf9a60065b	539	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
kadonotakashi	0:8fdf9a60065b	540
kadonotakashi	0:8fdf9a60065b	541	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
kadonotakashi	0:8fdf9a60065b	542	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
kadonotakashi	0:8fdf9a60065b	543
kadonotakashi	0:8fdf9a60065b	544	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
kadonotakashi	0:8fdf9a60065b	545	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
kadonotakashi	0:8fdf9a60065b	546
kadonotakashi	0:8fdf9a60065b	547	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
kadonotakashi	0:8fdf9a60065b	548	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
kadonotakashi	0:8fdf9a60065b	549
kadonotakashi	0:8fdf9a60065b	550	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
kadonotakashi	0:8fdf9a60065b	551	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
kadonotakashi	0:8fdf9a60065b	552
kadonotakashi	0:8fdf9a60065b	553	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
kadonotakashi	0:8fdf9a60065b	554	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
kadonotakashi	0:8fdf9a60065b	555
kadonotakashi	0:8fdf9a60065b	556	/* SCB Vector Table Offset Register Definitions */
kadonotakashi	0:8fdf9a60065b	557	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
kadonotakashi	0:8fdf9a60065b	558	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
kadonotakashi	0:8fdf9a60065b	559
kadonotakashi	0:8fdf9a60065b	560	/* SCB Application Interrupt and Reset Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	561	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
kadonotakashi	0:8fdf9a60065b	562	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
kadonotakashi	0:8fdf9a60065b	563
kadonotakashi	0:8fdf9a60065b	564	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
kadonotakashi	0:8fdf9a60065b	565	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
kadonotakashi	0:8fdf9a60065b	566
kadonotakashi	0:8fdf9a60065b	567	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
kadonotakashi	0:8fdf9a60065b	568	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
kadonotakashi	0:8fdf9a60065b	569
kadonotakashi	0:8fdf9a60065b	570	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
kadonotakashi	0:8fdf9a60065b	571	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
kadonotakashi	0:8fdf9a60065b	572
kadonotakashi	0:8fdf9a60065b	573	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
kadonotakashi	0:8fdf9a60065b	574	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
kadonotakashi	0:8fdf9a60065b	575
kadonotakashi	0:8fdf9a60065b	576	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
kadonotakashi	0:8fdf9a60065b	577	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
kadonotakashi	0:8fdf9a60065b	578
kadonotakashi	0:8fdf9a60065b	579	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
kadonotakashi	0:8fdf9a60065b	580	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
kadonotakashi	0:8fdf9a60065b	581
kadonotakashi	0:8fdf9a60065b	582	/* SCB System Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	583	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
kadonotakashi	0:8fdf9a60065b	584	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
kadonotakashi	0:8fdf9a60065b	585
kadonotakashi	0:8fdf9a60065b	586	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
kadonotakashi	0:8fdf9a60065b	587	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
kadonotakashi	0:8fdf9a60065b	588
kadonotakashi	0:8fdf9a60065b	589	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
kadonotakashi	0:8fdf9a60065b	590	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
kadonotakashi	0:8fdf9a60065b	591
kadonotakashi	0:8fdf9a60065b	592	/* SCB Configuration Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	593	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: Branch prediction enable bit Position /
kadonotakashi	0:8fdf9a60065b	594	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
kadonotakashi	0:8fdf9a60065b	595
kadonotakashi	0:8fdf9a60065b	596	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: Instruction cache enable bit Position /
kadonotakashi	0:8fdf9a60065b	597	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
kadonotakashi	0:8fdf9a60065b	598
kadonotakashi	0:8fdf9a60065b	599	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: Cache enable bit Position /
kadonotakashi	0:8fdf9a60065b	600	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
kadonotakashi	0:8fdf9a60065b	601
kadonotakashi	0:8fdf9a60065b	602	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
kadonotakashi	0:8fdf9a60065b	603	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
kadonotakashi	0:8fdf9a60065b	604
kadonotakashi	0:8fdf9a60065b	605	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
kadonotakashi	0:8fdf9a60065b	606	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
kadonotakashi	0:8fdf9a60065b	607
kadonotakashi	0:8fdf9a60065b	608	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
kadonotakashi	0:8fdf9a60065b	609	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
kadonotakashi	0:8fdf9a60065b	610
kadonotakashi	0:8fdf9a60065b	611	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
kadonotakashi	0:8fdf9a60065b	612	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
kadonotakashi	0:8fdf9a60065b	613
kadonotakashi	0:8fdf9a60065b	614	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
kadonotakashi	0:8fdf9a60065b	615	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
kadonotakashi	0:8fdf9a60065b	616
kadonotakashi	0:8fdf9a60065b	617	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
kadonotakashi	0:8fdf9a60065b	618	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
kadonotakashi	0:8fdf9a60065b	619
kadonotakashi	0:8fdf9a60065b	620	/* SCB System Handler Control and State Register Definitions */
kadonotakashi	0:8fdf9a60065b	621	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
kadonotakashi	0:8fdf9a60065b	622	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
kadonotakashi	0:8fdf9a60065b	623
kadonotakashi	0:8fdf9a60065b	624	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
kadonotakashi	0:8fdf9a60065b	625	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
kadonotakashi	0:8fdf9a60065b	626
kadonotakashi	0:8fdf9a60065b	627	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
kadonotakashi	0:8fdf9a60065b	628	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
kadonotakashi	0:8fdf9a60065b	629
kadonotakashi	0:8fdf9a60065b	630	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
kadonotakashi	0:8fdf9a60065b	631	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
kadonotakashi	0:8fdf9a60065b	632
kadonotakashi	0:8fdf9a60065b	633	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
kadonotakashi	0:8fdf9a60065b	634	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
kadonotakashi	0:8fdf9a60065b	635
kadonotakashi	0:8fdf9a60065b	636	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
kadonotakashi	0:8fdf9a60065b	637	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
kadonotakashi	0:8fdf9a60065b	638
kadonotakashi	0:8fdf9a60065b	639	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
kadonotakashi	0:8fdf9a60065b	640	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
kadonotakashi	0:8fdf9a60065b	641
kadonotakashi	0:8fdf9a60065b	642	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
kadonotakashi	0:8fdf9a60065b	643	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
kadonotakashi	0:8fdf9a60065b	644
kadonotakashi	0:8fdf9a60065b	645	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
kadonotakashi	0:8fdf9a60065b	646	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
kadonotakashi	0:8fdf9a60065b	647
kadonotakashi	0:8fdf9a60065b	648	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
kadonotakashi	0:8fdf9a60065b	649	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
kadonotakashi	0:8fdf9a60065b	650
kadonotakashi	0:8fdf9a60065b	651	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
kadonotakashi	0:8fdf9a60065b	652	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
kadonotakashi	0:8fdf9a60065b	653
kadonotakashi	0:8fdf9a60065b	654	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
kadonotakashi	0:8fdf9a60065b	655	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
kadonotakashi	0:8fdf9a60065b	656
kadonotakashi	0:8fdf9a60065b	657	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
kadonotakashi	0:8fdf9a60065b	658	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
kadonotakashi	0:8fdf9a60065b	659
kadonotakashi	0:8fdf9a60065b	660	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
kadonotakashi	0:8fdf9a60065b	661	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
kadonotakashi	0:8fdf9a60065b	662
kadonotakashi	0:8fdf9a60065b	663	/* SCB Configurable Fault Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	664	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
kadonotakashi	0:8fdf9a60065b	665	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
kadonotakashi	0:8fdf9a60065b	666
kadonotakashi	0:8fdf9a60065b	667	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
kadonotakashi	0:8fdf9a60065b	668	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
kadonotakashi	0:8fdf9a60065b	669
kadonotakashi	0:8fdf9a60065b	670	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
kadonotakashi	0:8fdf9a60065b	671	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
kadonotakashi	0:8fdf9a60065b	672
kadonotakashi	0:8fdf9a60065b	673	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
kadonotakashi	0:8fdf9a60065b	674	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
kadonotakashi	0:8fdf9a60065b	675	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
kadonotakashi	0:8fdf9a60065b	676
kadonotakashi	0:8fdf9a60065b	677	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
kadonotakashi	0:8fdf9a60065b	678	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
kadonotakashi	0:8fdf9a60065b	679
kadonotakashi	0:8fdf9a60065b	680	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
kadonotakashi	0:8fdf9a60065b	681	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
kadonotakashi	0:8fdf9a60065b	682
kadonotakashi	0:8fdf9a60065b	683	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
kadonotakashi	0:8fdf9a60065b	684	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
kadonotakashi	0:8fdf9a60065b	685
kadonotakashi	0:8fdf9a60065b	686	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
kadonotakashi	0:8fdf9a60065b	687	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
kadonotakashi	0:8fdf9a60065b	688
kadonotakashi	0:8fdf9a60065b	689	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
kadonotakashi	0:8fdf9a60065b	690	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
kadonotakashi	0:8fdf9a60065b	691
kadonotakashi	0:8fdf9a60065b	692	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
kadonotakashi	0:8fdf9a60065b	693	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
kadonotakashi	0:8fdf9a60065b	694	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
kadonotakashi	0:8fdf9a60065b	695
kadonotakashi	0:8fdf9a60065b	696	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
kadonotakashi	0:8fdf9a60065b	697	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
kadonotakashi	0:8fdf9a60065b	698
kadonotakashi	0:8fdf9a60065b	699	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
kadonotakashi	0:8fdf9a60065b	700	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
kadonotakashi	0:8fdf9a60065b	701
kadonotakashi	0:8fdf9a60065b	702	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
kadonotakashi	0:8fdf9a60065b	703	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
kadonotakashi	0:8fdf9a60065b	704
kadonotakashi	0:8fdf9a60065b	705	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
kadonotakashi	0:8fdf9a60065b	706	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
kadonotakashi	0:8fdf9a60065b	707
kadonotakashi	0:8fdf9a60065b	708	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
kadonotakashi	0:8fdf9a60065b	709	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
kadonotakashi	0:8fdf9a60065b	710
kadonotakashi	0:8fdf9a60065b	711	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
kadonotakashi	0:8fdf9a60065b	712	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
kadonotakashi	0:8fdf9a60065b	713
kadonotakashi	0:8fdf9a60065b	714	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
kadonotakashi	0:8fdf9a60065b	715	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
kadonotakashi	0:8fdf9a60065b	716	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
kadonotakashi	0:8fdf9a60065b	717
kadonotakashi	0:8fdf9a60065b	718	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
kadonotakashi	0:8fdf9a60065b	719	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
kadonotakashi	0:8fdf9a60065b	720
kadonotakashi	0:8fdf9a60065b	721	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
kadonotakashi	0:8fdf9a60065b	722	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
kadonotakashi	0:8fdf9a60065b	723
kadonotakashi	0:8fdf9a60065b	724	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
kadonotakashi	0:8fdf9a60065b	725	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
kadonotakashi	0:8fdf9a60065b	726
kadonotakashi	0:8fdf9a60065b	727	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
kadonotakashi	0:8fdf9a60065b	728	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
kadonotakashi	0:8fdf9a60065b	729
kadonotakashi	0:8fdf9a60065b	730	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
kadonotakashi	0:8fdf9a60065b	731	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
kadonotakashi	0:8fdf9a60065b	732
kadonotakashi	0:8fdf9a60065b	733	/* SCB Hard Fault Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	734	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
kadonotakashi	0:8fdf9a60065b	735	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
kadonotakashi	0:8fdf9a60065b	736
kadonotakashi	0:8fdf9a60065b	737	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
kadonotakashi	0:8fdf9a60065b	738	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
kadonotakashi	0:8fdf9a60065b	739
kadonotakashi	0:8fdf9a60065b	740	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
kadonotakashi	0:8fdf9a60065b	741	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
kadonotakashi	0:8fdf9a60065b	742
kadonotakashi	0:8fdf9a60065b	743	/* SCB Debug Fault Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	744	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
kadonotakashi	0:8fdf9a60065b	745	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
kadonotakashi	0:8fdf9a60065b	746
kadonotakashi	0:8fdf9a60065b	747	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
kadonotakashi	0:8fdf9a60065b	748	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
kadonotakashi	0:8fdf9a60065b	749
kadonotakashi	0:8fdf9a60065b	750	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
kadonotakashi	0:8fdf9a60065b	751	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
kadonotakashi	0:8fdf9a60065b	752
kadonotakashi	0:8fdf9a60065b	753	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
kadonotakashi	0:8fdf9a60065b	754	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
kadonotakashi	0:8fdf9a60065b	755
kadonotakashi	0:8fdf9a60065b	756	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
kadonotakashi	0:8fdf9a60065b	757	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
kadonotakashi	0:8fdf9a60065b	758
kadonotakashi	0:8fdf9a60065b	759	/* SCB Cache Level ID Register Definitions */
kadonotakashi	0:8fdf9a60065b	760	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
kadonotakashi	0:8fdf9a60065b	761	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
kadonotakashi	0:8fdf9a60065b	762
kadonotakashi	0:8fdf9a60065b	763	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
kadonotakashi	0:8fdf9a60065b	764	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
kadonotakashi	0:8fdf9a60065b	765
kadonotakashi	0:8fdf9a60065b	766	/* SCB Cache Type Register Definitions */
kadonotakashi	0:8fdf9a60065b	767	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
kadonotakashi	0:8fdf9a60065b	768	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
kadonotakashi	0:8fdf9a60065b	769
kadonotakashi	0:8fdf9a60065b	770	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
kadonotakashi	0:8fdf9a60065b	771	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
kadonotakashi	0:8fdf9a60065b	772
kadonotakashi	0:8fdf9a60065b	773	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
kadonotakashi	0:8fdf9a60065b	774	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
kadonotakashi	0:8fdf9a60065b	775
kadonotakashi	0:8fdf9a60065b	776	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
kadonotakashi	0:8fdf9a60065b	777	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
kadonotakashi	0:8fdf9a60065b	778
kadonotakashi	0:8fdf9a60065b	779	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
kadonotakashi	0:8fdf9a60065b	780	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
kadonotakashi	0:8fdf9a60065b	781
kadonotakashi	0:8fdf9a60065b	782	/* SCB Cache Size ID Register Definitions */
kadonotakashi	0:8fdf9a60065b	783	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
kadonotakashi	0:8fdf9a60065b	784	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
kadonotakashi	0:8fdf9a60065b	785
kadonotakashi	0:8fdf9a60065b	786	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
kadonotakashi	0:8fdf9a60065b	787	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
kadonotakashi	0:8fdf9a60065b	788
kadonotakashi	0:8fdf9a60065b	789	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
kadonotakashi	0:8fdf9a60065b	790	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
kadonotakashi	0:8fdf9a60065b	791
kadonotakashi	0:8fdf9a60065b	792	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
kadonotakashi	0:8fdf9a60065b	793	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
kadonotakashi	0:8fdf9a60065b	794
kadonotakashi	0:8fdf9a60065b	795	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
kadonotakashi	0:8fdf9a60065b	796	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
kadonotakashi	0:8fdf9a60065b	797
kadonotakashi	0:8fdf9a60065b	798	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
kadonotakashi	0:8fdf9a60065b	799	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
kadonotakashi	0:8fdf9a60065b	800
kadonotakashi	0:8fdf9a60065b	801	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
kadonotakashi	0:8fdf9a60065b	802	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
kadonotakashi	0:8fdf9a60065b	803
kadonotakashi	0:8fdf9a60065b	804	/* SCB Cache Size Selection Register Definitions */
kadonotakashi	0:8fdf9a60065b	805	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
kadonotakashi	0:8fdf9a60065b	806	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
kadonotakashi	0:8fdf9a60065b	807
kadonotakashi	0:8fdf9a60065b	808	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
kadonotakashi	0:8fdf9a60065b	809	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
kadonotakashi	0:8fdf9a60065b	810
kadonotakashi	0:8fdf9a60065b	811	/* SCB Software Triggered Interrupt Register Definitions */
kadonotakashi	0:8fdf9a60065b	812	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
kadonotakashi	0:8fdf9a60065b	813	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
kadonotakashi	0:8fdf9a60065b	814
kadonotakashi	0:8fdf9a60065b	815	/* SCB D-Cache Invalidate by Set-way Register Definitions */
kadonotakashi	0:8fdf9a60065b	816	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
kadonotakashi	0:8fdf9a60065b	817	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
kadonotakashi	0:8fdf9a60065b	818
kadonotakashi	0:8fdf9a60065b	819	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
kadonotakashi	0:8fdf9a60065b	820	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
kadonotakashi	0:8fdf9a60065b	821
kadonotakashi	0:8fdf9a60065b	822	/* SCB D-Cache Clean by Set-way Register Definitions */
kadonotakashi	0:8fdf9a60065b	823	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
kadonotakashi	0:8fdf9a60065b	824	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
kadonotakashi	0:8fdf9a60065b	825
kadonotakashi	0:8fdf9a60065b	826	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
kadonotakashi	0:8fdf9a60065b	827	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
kadonotakashi	0:8fdf9a60065b	828
kadonotakashi	0:8fdf9a60065b	829	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
kadonotakashi	0:8fdf9a60065b	830	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
kadonotakashi	0:8fdf9a60065b	831	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
kadonotakashi	0:8fdf9a60065b	832
kadonotakashi	0:8fdf9a60065b	833	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
kadonotakashi	0:8fdf9a60065b	834	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
kadonotakashi	0:8fdf9a60065b	835
kadonotakashi	0:8fdf9a60065b	836	/* Instruction Tightly-Coupled Memory Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	837	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
kadonotakashi	0:8fdf9a60065b	838	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
kadonotakashi	0:8fdf9a60065b	839
kadonotakashi	0:8fdf9a60065b	840	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
kadonotakashi	0:8fdf9a60065b	841	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
kadonotakashi	0:8fdf9a60065b	842
kadonotakashi	0:8fdf9a60065b	843	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
kadonotakashi	0:8fdf9a60065b	844	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
kadonotakashi	0:8fdf9a60065b	845
kadonotakashi	0:8fdf9a60065b	846	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
kadonotakashi	0:8fdf9a60065b	847	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
kadonotakashi	0:8fdf9a60065b	848
kadonotakashi	0:8fdf9a60065b	849	/* Data Tightly-Coupled Memory Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	850	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
kadonotakashi	0:8fdf9a60065b	851	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
kadonotakashi	0:8fdf9a60065b	852
kadonotakashi	0:8fdf9a60065b	853	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
kadonotakashi	0:8fdf9a60065b	854	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
kadonotakashi	0:8fdf9a60065b	855
kadonotakashi	0:8fdf9a60065b	856	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
kadonotakashi	0:8fdf9a60065b	857	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
kadonotakashi	0:8fdf9a60065b	858
kadonotakashi	0:8fdf9a60065b	859	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
kadonotakashi	0:8fdf9a60065b	860	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
kadonotakashi	0:8fdf9a60065b	861
kadonotakashi	0:8fdf9a60065b	862	/* AHBP Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	863	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
kadonotakashi	0:8fdf9a60065b	864	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
kadonotakashi	0:8fdf9a60065b	865
kadonotakashi	0:8fdf9a60065b	866	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
kadonotakashi	0:8fdf9a60065b	867	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
kadonotakashi	0:8fdf9a60065b	868
kadonotakashi	0:8fdf9a60065b	869	/* L1 Cache Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	870	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
kadonotakashi	0:8fdf9a60065b	871	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
kadonotakashi	0:8fdf9a60065b	872
kadonotakashi	0:8fdf9a60065b	873	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
kadonotakashi	0:8fdf9a60065b	874	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
kadonotakashi	0:8fdf9a60065b	875
kadonotakashi	0:8fdf9a60065b	876	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
kadonotakashi	0:8fdf9a60065b	877	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
kadonotakashi	0:8fdf9a60065b	878
kadonotakashi	0:8fdf9a60065b	879	/* AHBS Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	880	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
kadonotakashi	0:8fdf9a60065b	881	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
kadonotakashi	0:8fdf9a60065b	882
kadonotakashi	0:8fdf9a60065b	883	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
kadonotakashi	0:8fdf9a60065b	884	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
kadonotakashi	0:8fdf9a60065b	885
kadonotakashi	0:8fdf9a60065b	886	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
kadonotakashi	0:8fdf9a60065b	887	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
kadonotakashi	0:8fdf9a60065b	888
kadonotakashi	0:8fdf9a60065b	889	/* Auxiliary Bus Fault Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	890	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
kadonotakashi	0:8fdf9a60065b	891	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
kadonotakashi	0:8fdf9a60065b	892
kadonotakashi	0:8fdf9a60065b	893	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
kadonotakashi	0:8fdf9a60065b	894	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
kadonotakashi	0:8fdf9a60065b	895
kadonotakashi	0:8fdf9a60065b	896	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
kadonotakashi	0:8fdf9a60065b	897	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
kadonotakashi	0:8fdf9a60065b	898
kadonotakashi	0:8fdf9a60065b	899	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
kadonotakashi	0:8fdf9a60065b	900	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
kadonotakashi	0:8fdf9a60065b	901
kadonotakashi	0:8fdf9a60065b	902	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
kadonotakashi	0:8fdf9a60065b	903	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
kadonotakashi	0:8fdf9a60065b	904
kadonotakashi	0:8fdf9a60065b	905	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
kadonotakashi	0:8fdf9a60065b	906	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
kadonotakashi	0:8fdf9a60065b	907
kadonotakashi	0:8fdf9a60065b	908	/@} end of group CMSIS_SCB /
kadonotakashi	0:8fdf9a60065b	909
kadonotakashi	0:8fdf9a60065b	910
kadonotakashi	0:8fdf9a60065b	911	/**
kadonotakashi	0:8fdf9a60065b	912	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	913	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
kadonotakashi	0:8fdf9a60065b	914	\brief Type definitions for the System Control and ID Register not in the SCB
kadonotakashi	0:8fdf9a60065b	915	@{
kadonotakashi	0:8fdf9a60065b	916	*/
kadonotakashi	0:8fdf9a60065b	917
kadonotakashi	0:8fdf9a60065b	918	/**
kadonotakashi	0:8fdf9a60065b	919	\brief Structure type to access the System Control and ID Register not in the SCB.
kadonotakashi	0:8fdf9a60065b	920	*/
kadonotakashi	0:8fdf9a60065b	921	typedef struct
kadonotakashi	0:8fdf9a60065b	922	{
kadonotakashi	0:8fdf9a60065b	923	uint32_t RESERVED0[1U];
kadonotakashi	0:8fdf9a60065b	924	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
kadonotakashi	0:8fdf9a60065b	925	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
kadonotakashi	0:8fdf9a60065b	926	} SCnSCB_Type;
kadonotakashi	0:8fdf9a60065b	927
kadonotakashi	0:8fdf9a60065b	928	/* Interrupt Controller Type Register Definitions */
kadonotakashi	0:8fdf9a60065b	929	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
kadonotakashi	0:8fdf9a60065b	930	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
kadonotakashi	0:8fdf9a60065b	931
kadonotakashi	0:8fdf9a60065b	932	/* Auxiliary Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	933	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /!< ACTLR: DISITMATBFLUSH Position /
kadonotakashi	0:8fdf9a60065b	934	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
kadonotakashi	0:8fdf9a60065b	935
kadonotakashi	0:8fdf9a60065b	936	#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /!< ACTLR: DISRAMODE Position /
kadonotakashi	0:8fdf9a60065b	937	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
kadonotakashi	0:8fdf9a60065b	938
kadonotakashi	0:8fdf9a60065b	939	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /!< ACTLR: FPEXCODIS Position /
kadonotakashi	0:8fdf9a60065b	940	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
kadonotakashi	0:8fdf9a60065b	941
kadonotakashi	0:8fdf9a60065b	942	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
kadonotakashi	0:8fdf9a60065b	943	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
kadonotakashi	0:8fdf9a60065b	944
kadonotakashi	0:8fdf9a60065b	945	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
kadonotakashi	0:8fdf9a60065b	946	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
kadonotakashi	0:8fdf9a60065b	947
kadonotakashi	0:8fdf9a60065b	948	/@} end of group CMSIS_SCnotSCB /
kadonotakashi	0:8fdf9a60065b	949
kadonotakashi	0:8fdf9a60065b	950
kadonotakashi	0:8fdf9a60065b	951	/**
kadonotakashi	0:8fdf9a60065b	952	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	953	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
kadonotakashi	0:8fdf9a60065b	954	\brief Type definitions for the System Timer Registers.
kadonotakashi	0:8fdf9a60065b	955	@{
kadonotakashi	0:8fdf9a60065b	956	*/
kadonotakashi	0:8fdf9a60065b	957
kadonotakashi	0:8fdf9a60065b	958	/**
kadonotakashi	0:8fdf9a60065b	959	\brief Structure type to access the System Timer (SysTick).
kadonotakashi	0:8fdf9a60065b	960	*/
kadonotakashi	0:8fdf9a60065b	961	typedef struct
kadonotakashi	0:8fdf9a60065b	962	{
kadonotakashi	0:8fdf9a60065b	963	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
kadonotakashi	0:8fdf9a60065b	964	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
kadonotakashi	0:8fdf9a60065b	965	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
kadonotakashi	0:8fdf9a60065b	966	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
kadonotakashi	0:8fdf9a60065b	967	} SysTick_Type;
kadonotakashi	0:8fdf9a60065b	968
kadonotakashi	0:8fdf9a60065b	969	/* SysTick Control / Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	970	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
kadonotakashi	0:8fdf9a60065b	971	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
kadonotakashi	0:8fdf9a60065b	972
kadonotakashi	0:8fdf9a60065b	973	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
kadonotakashi	0:8fdf9a60065b	974	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
kadonotakashi	0:8fdf9a60065b	975
kadonotakashi	0:8fdf9a60065b	976	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
kadonotakashi	0:8fdf9a60065b	977	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
kadonotakashi	0:8fdf9a60065b	978
kadonotakashi	0:8fdf9a60065b	979	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
kadonotakashi	0:8fdf9a60065b	980	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
kadonotakashi	0:8fdf9a60065b	981
kadonotakashi	0:8fdf9a60065b	982	/* SysTick Reload Register Definitions */
kadonotakashi	0:8fdf9a60065b	983	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
kadonotakashi	0:8fdf9a60065b	984	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
kadonotakashi	0:8fdf9a60065b	985
kadonotakashi	0:8fdf9a60065b	986	/* SysTick Current Register Definitions */
kadonotakashi	0:8fdf9a60065b	987	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
kadonotakashi	0:8fdf9a60065b	988	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
kadonotakashi	0:8fdf9a60065b	989
kadonotakashi	0:8fdf9a60065b	990	/* SysTick Calibration Register Definitions */
kadonotakashi	0:8fdf9a60065b	991	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
kadonotakashi	0:8fdf9a60065b	992	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
kadonotakashi	0:8fdf9a60065b	993
kadonotakashi	0:8fdf9a60065b	994	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
kadonotakashi	0:8fdf9a60065b	995	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
kadonotakashi	0:8fdf9a60065b	996
kadonotakashi	0:8fdf9a60065b	997	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
kadonotakashi	0:8fdf9a60065b	998	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
kadonotakashi	0:8fdf9a60065b	999
kadonotakashi	0:8fdf9a60065b	1000	/@} end of group CMSIS_SysTick /
kadonotakashi	0:8fdf9a60065b	1001
kadonotakashi	0:8fdf9a60065b	1002
kadonotakashi	0:8fdf9a60065b	1003	/**
kadonotakashi	0:8fdf9a60065b	1004	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1005	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
kadonotakashi	0:8fdf9a60065b	1006	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
kadonotakashi	0:8fdf9a60065b	1007	@{
kadonotakashi	0:8fdf9a60065b	1008	*/
kadonotakashi	0:8fdf9a60065b	1009
kadonotakashi	0:8fdf9a60065b	1010	/**
kadonotakashi	0:8fdf9a60065b	1011	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
kadonotakashi	0:8fdf9a60065b	1012	*/
kadonotakashi	0:8fdf9a60065b	1013	typedef struct
kadonotakashi	0:8fdf9a60065b	1014	{
kadonotakashi	0:8fdf9a60065b	1015	__OM union
kadonotakashi	0:8fdf9a60065b	1016	{
kadonotakashi	0:8fdf9a60065b	1017	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
kadonotakashi	0:8fdf9a60065b	1018	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
kadonotakashi	0:8fdf9a60065b	1019	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
kadonotakashi	0:8fdf9a60065b	1020	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
kadonotakashi	0:8fdf9a60065b	1021	uint32_t RESERVED0[864U];
kadonotakashi	0:8fdf9a60065b	1022	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
kadonotakashi	0:8fdf9a60065b	1023	uint32_t RESERVED1[15U];
kadonotakashi	0:8fdf9a60065b	1024	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
kadonotakashi	0:8fdf9a60065b	1025	uint32_t RESERVED2[15U];
kadonotakashi	0:8fdf9a60065b	1026	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
kadonotakashi	0:8fdf9a60065b	1027	uint32_t RESERVED3[29U];
kadonotakashi	0:8fdf9a60065b	1028	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
kadonotakashi	0:8fdf9a60065b	1029	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
kadonotakashi	0:8fdf9a60065b	1030	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
kadonotakashi	0:8fdf9a60065b	1031	uint32_t RESERVED4[43U];
kadonotakashi	0:8fdf9a60065b	1032	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
kadonotakashi	0:8fdf9a60065b	1033	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
kadonotakashi	0:8fdf9a60065b	1034	uint32_t RESERVED5[6U];
kadonotakashi	0:8fdf9a60065b	1035	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
kadonotakashi	0:8fdf9a60065b	1036	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
kadonotakashi	0:8fdf9a60065b	1037	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
kadonotakashi	0:8fdf9a60065b	1038	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
kadonotakashi	0:8fdf9a60065b	1039	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
kadonotakashi	0:8fdf9a60065b	1040	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
kadonotakashi	0:8fdf9a60065b	1041	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
kadonotakashi	0:8fdf9a60065b	1042	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
kadonotakashi	0:8fdf9a60065b	1043	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
kadonotakashi	0:8fdf9a60065b	1044	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
kadonotakashi	0:8fdf9a60065b	1045	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
kadonotakashi	0:8fdf9a60065b	1046	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
kadonotakashi	0:8fdf9a60065b	1047	} ITM_Type;
kadonotakashi	0:8fdf9a60065b	1048
kadonotakashi	0:8fdf9a60065b	1049	/* ITM Trace Privilege Register Definitions */
kadonotakashi	0:8fdf9a60065b	1050	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
kadonotakashi	0:8fdf9a60065b	1051	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
kadonotakashi	0:8fdf9a60065b	1052
kadonotakashi	0:8fdf9a60065b	1053	/* ITM Trace Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1054	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
kadonotakashi	0:8fdf9a60065b	1055	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
kadonotakashi	0:8fdf9a60065b	1056
kadonotakashi	0:8fdf9a60065b	1057	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
kadonotakashi	0:8fdf9a60065b	1058	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
kadonotakashi	0:8fdf9a60065b	1059
kadonotakashi	0:8fdf9a60065b	1060	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
kadonotakashi	0:8fdf9a60065b	1061	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
kadonotakashi	0:8fdf9a60065b	1062
kadonotakashi	0:8fdf9a60065b	1063	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
kadonotakashi	0:8fdf9a60065b	1064	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
kadonotakashi	0:8fdf9a60065b	1065
kadonotakashi	0:8fdf9a60065b	1066	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
kadonotakashi	0:8fdf9a60065b	1067	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
kadonotakashi	0:8fdf9a60065b	1068
kadonotakashi	0:8fdf9a60065b	1069	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
kadonotakashi	0:8fdf9a60065b	1070	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
kadonotakashi	0:8fdf9a60065b	1071
kadonotakashi	0:8fdf9a60065b	1072	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
kadonotakashi	0:8fdf9a60065b	1073	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
kadonotakashi	0:8fdf9a60065b	1074
kadonotakashi	0:8fdf9a60065b	1075	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
kadonotakashi	0:8fdf9a60065b	1076	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
kadonotakashi	0:8fdf9a60065b	1077
kadonotakashi	0:8fdf9a60065b	1078	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
kadonotakashi	0:8fdf9a60065b	1079	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
kadonotakashi	0:8fdf9a60065b	1080
kadonotakashi	0:8fdf9a60065b	1081	/* ITM Integration Write Register Definitions */
kadonotakashi	0:8fdf9a60065b	1082	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
kadonotakashi	0:8fdf9a60065b	1083	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
kadonotakashi	0:8fdf9a60065b	1084
kadonotakashi	0:8fdf9a60065b	1085	/* ITM Integration Read Register Definitions */
kadonotakashi	0:8fdf9a60065b	1086	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
kadonotakashi	0:8fdf9a60065b	1087	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
kadonotakashi	0:8fdf9a60065b	1088
kadonotakashi	0:8fdf9a60065b	1089	/* ITM Integration Mode Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1090	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
kadonotakashi	0:8fdf9a60065b	1091	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
kadonotakashi	0:8fdf9a60065b	1092
kadonotakashi	0:8fdf9a60065b	1093	/* ITM Lock Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	1094	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
kadonotakashi	0:8fdf9a60065b	1095	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
kadonotakashi	0:8fdf9a60065b	1096
kadonotakashi	0:8fdf9a60065b	1097	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
kadonotakashi	0:8fdf9a60065b	1098	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
kadonotakashi	0:8fdf9a60065b	1099
kadonotakashi	0:8fdf9a60065b	1100	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
kadonotakashi	0:8fdf9a60065b	1101	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
kadonotakashi	0:8fdf9a60065b	1102
kadonotakashi	0:8fdf9a60065b	1103	/@}/ /* end of group CMSIS_ITM */
kadonotakashi	0:8fdf9a60065b	1104
kadonotakashi	0:8fdf9a60065b	1105
kadonotakashi	0:8fdf9a60065b	1106	/**
kadonotakashi	0:8fdf9a60065b	1107	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1108	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
kadonotakashi	0:8fdf9a60065b	1109	\brief Type definitions for the Data Watchpoint and Trace (DWT)
kadonotakashi	0:8fdf9a60065b	1110	@{
kadonotakashi	0:8fdf9a60065b	1111	*/
kadonotakashi	0:8fdf9a60065b	1112
kadonotakashi	0:8fdf9a60065b	1113	/**
kadonotakashi	0:8fdf9a60065b	1114	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
kadonotakashi	0:8fdf9a60065b	1115	*/
kadonotakashi	0:8fdf9a60065b	1116	typedef struct
kadonotakashi	0:8fdf9a60065b	1117	{
kadonotakashi	0:8fdf9a60065b	1118	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
kadonotakashi	0:8fdf9a60065b	1119	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
kadonotakashi	0:8fdf9a60065b	1120	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
kadonotakashi	0:8fdf9a60065b	1121	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
kadonotakashi	0:8fdf9a60065b	1122	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
kadonotakashi	0:8fdf9a60065b	1123	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
kadonotakashi	0:8fdf9a60065b	1124	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
kadonotakashi	0:8fdf9a60065b	1125	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
kadonotakashi	0:8fdf9a60065b	1126	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
kadonotakashi	0:8fdf9a60065b	1127	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
kadonotakashi	0:8fdf9a60065b	1128	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
kadonotakashi	0:8fdf9a60065b	1129	uint32_t RESERVED0[1U];
kadonotakashi	0:8fdf9a60065b	1130	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
kadonotakashi	0:8fdf9a60065b	1131	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
kadonotakashi	0:8fdf9a60065b	1132	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
kadonotakashi	0:8fdf9a60065b	1133	uint32_t RESERVED1[1U];
kadonotakashi	0:8fdf9a60065b	1134	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
kadonotakashi	0:8fdf9a60065b	1135	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
kadonotakashi	0:8fdf9a60065b	1136	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
kadonotakashi	0:8fdf9a60065b	1137	uint32_t RESERVED2[1U];
kadonotakashi	0:8fdf9a60065b	1138	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
kadonotakashi	0:8fdf9a60065b	1139	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
kadonotakashi	0:8fdf9a60065b	1140	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
kadonotakashi	0:8fdf9a60065b	1141	uint32_t RESERVED3[981U];
kadonotakashi	0:8fdf9a60065b	1142	__OM uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
kadonotakashi	0:8fdf9a60065b	1143	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
kadonotakashi	0:8fdf9a60065b	1144	} DWT_Type;
kadonotakashi	0:8fdf9a60065b	1145
kadonotakashi	0:8fdf9a60065b	1146	/* DWT Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1147	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
kadonotakashi	0:8fdf9a60065b	1148	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
kadonotakashi	0:8fdf9a60065b	1149
kadonotakashi	0:8fdf9a60065b	1150	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
kadonotakashi	0:8fdf9a60065b	1151	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
kadonotakashi	0:8fdf9a60065b	1152
kadonotakashi	0:8fdf9a60065b	1153	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
kadonotakashi	0:8fdf9a60065b	1154	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
kadonotakashi	0:8fdf9a60065b	1155
kadonotakashi	0:8fdf9a60065b	1156	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
kadonotakashi	0:8fdf9a60065b	1157	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
kadonotakashi	0:8fdf9a60065b	1158
kadonotakashi	0:8fdf9a60065b	1159	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
kadonotakashi	0:8fdf9a60065b	1160	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
kadonotakashi	0:8fdf9a60065b	1161
kadonotakashi	0:8fdf9a60065b	1162	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
kadonotakashi	0:8fdf9a60065b	1163	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	1164
kadonotakashi	0:8fdf9a60065b	1165	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
kadonotakashi	0:8fdf9a60065b	1166	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	1167
kadonotakashi	0:8fdf9a60065b	1168	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
kadonotakashi	0:8fdf9a60065b	1169	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	1170
kadonotakashi	0:8fdf9a60065b	1171	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
kadonotakashi	0:8fdf9a60065b	1172	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	1173
kadonotakashi	0:8fdf9a60065b	1174	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
kadonotakashi	0:8fdf9a60065b	1175	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	1176
kadonotakashi	0:8fdf9a60065b	1177	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
kadonotakashi	0:8fdf9a60065b	1178	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	1179
kadonotakashi	0:8fdf9a60065b	1180	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
kadonotakashi	0:8fdf9a60065b	1181	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
kadonotakashi	0:8fdf9a60065b	1182
kadonotakashi	0:8fdf9a60065b	1183	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
kadonotakashi	0:8fdf9a60065b	1184	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
kadonotakashi	0:8fdf9a60065b	1185
kadonotakashi	0:8fdf9a60065b	1186	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
kadonotakashi	0:8fdf9a60065b	1187	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
kadonotakashi	0:8fdf9a60065b	1188
kadonotakashi	0:8fdf9a60065b	1189	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
kadonotakashi	0:8fdf9a60065b	1190	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
kadonotakashi	0:8fdf9a60065b	1191
kadonotakashi	0:8fdf9a60065b	1192	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
kadonotakashi	0:8fdf9a60065b	1193	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
kadonotakashi	0:8fdf9a60065b	1194
kadonotakashi	0:8fdf9a60065b	1195	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
kadonotakashi	0:8fdf9a60065b	1196	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
kadonotakashi	0:8fdf9a60065b	1197
kadonotakashi	0:8fdf9a60065b	1198	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
kadonotakashi	0:8fdf9a60065b	1199	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
kadonotakashi	0:8fdf9a60065b	1200
kadonotakashi	0:8fdf9a60065b	1201	/* DWT CPI Count Register Definitions */
kadonotakashi	0:8fdf9a60065b	1202	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
kadonotakashi	0:8fdf9a60065b	1203	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
kadonotakashi	0:8fdf9a60065b	1204
kadonotakashi	0:8fdf9a60065b	1205	/* DWT Exception Overhead Count Register Definitions */
kadonotakashi	0:8fdf9a60065b	1206	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
kadonotakashi	0:8fdf9a60065b	1207	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
kadonotakashi	0:8fdf9a60065b	1208
kadonotakashi	0:8fdf9a60065b	1209	/* DWT Sleep Count Register Definitions */
kadonotakashi	0:8fdf9a60065b	1210	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
kadonotakashi	0:8fdf9a60065b	1211	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
kadonotakashi	0:8fdf9a60065b	1212
kadonotakashi	0:8fdf9a60065b	1213	/* DWT LSU Count Register Definitions */
kadonotakashi	0:8fdf9a60065b	1214	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
kadonotakashi	0:8fdf9a60065b	1215	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
kadonotakashi	0:8fdf9a60065b	1216
kadonotakashi	0:8fdf9a60065b	1217	/* DWT Folded-instruction Count Register Definitions */
kadonotakashi	0:8fdf9a60065b	1218	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
kadonotakashi	0:8fdf9a60065b	1219	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
kadonotakashi	0:8fdf9a60065b	1220
kadonotakashi	0:8fdf9a60065b	1221	/* DWT Comparator Mask Register Definitions */
kadonotakashi	0:8fdf9a60065b	1222	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
kadonotakashi	0:8fdf9a60065b	1223	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
kadonotakashi	0:8fdf9a60065b	1224
kadonotakashi	0:8fdf9a60065b	1225	/* DWT Comparator Function Register Definitions */
kadonotakashi	0:8fdf9a60065b	1226	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
kadonotakashi	0:8fdf9a60065b	1227	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
kadonotakashi	0:8fdf9a60065b	1228
kadonotakashi	0:8fdf9a60065b	1229	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
kadonotakashi	0:8fdf9a60065b	1230	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
kadonotakashi	0:8fdf9a60065b	1231
kadonotakashi	0:8fdf9a60065b	1232	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
kadonotakashi	0:8fdf9a60065b	1233	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
kadonotakashi	0:8fdf9a60065b	1234
kadonotakashi	0:8fdf9a60065b	1235	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
kadonotakashi	0:8fdf9a60065b	1236	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
kadonotakashi	0:8fdf9a60065b	1237
kadonotakashi	0:8fdf9a60065b	1238	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
kadonotakashi	0:8fdf9a60065b	1239	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
kadonotakashi	0:8fdf9a60065b	1240
kadonotakashi	0:8fdf9a60065b	1241	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
kadonotakashi	0:8fdf9a60065b	1242	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
kadonotakashi	0:8fdf9a60065b	1243
kadonotakashi	0:8fdf9a60065b	1244	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
kadonotakashi	0:8fdf9a60065b	1245	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
kadonotakashi	0:8fdf9a60065b	1246
kadonotakashi	0:8fdf9a60065b	1247	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
kadonotakashi	0:8fdf9a60065b	1248	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
kadonotakashi	0:8fdf9a60065b	1249
kadonotakashi	0:8fdf9a60065b	1250	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
kadonotakashi	0:8fdf9a60065b	1251	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
kadonotakashi	0:8fdf9a60065b	1252
kadonotakashi	0:8fdf9a60065b	1253	/@}/ /* end of group CMSIS_DWT */
kadonotakashi	0:8fdf9a60065b	1254
kadonotakashi	0:8fdf9a60065b	1255
kadonotakashi	0:8fdf9a60065b	1256	/**
kadonotakashi	0:8fdf9a60065b	1257	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1258	\defgroup CMSIS_TPI Trace Port Interface (TPI)
kadonotakashi	0:8fdf9a60065b	1259	\brief Type definitions for the Trace Port Interface (TPI)
kadonotakashi	0:8fdf9a60065b	1260	@{
kadonotakashi	0:8fdf9a60065b	1261	*/
kadonotakashi	0:8fdf9a60065b	1262
kadonotakashi	0:8fdf9a60065b	1263	/**
kadonotakashi	0:8fdf9a60065b	1264	\brief Structure type to access the Trace Port Interface Register (TPI).
kadonotakashi	0:8fdf9a60065b	1265	*/
kadonotakashi	0:8fdf9a60065b	1266	typedef struct
kadonotakashi	0:8fdf9a60065b	1267	{
kadonotakashi	0:8fdf9a60065b	1268	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
kadonotakashi	0:8fdf9a60065b	1269	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
kadonotakashi	0:8fdf9a60065b	1270	uint32_t RESERVED0[2U];
kadonotakashi	0:8fdf9a60065b	1271	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
kadonotakashi	0:8fdf9a60065b	1272	uint32_t RESERVED1[55U];
kadonotakashi	0:8fdf9a60065b	1273	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
kadonotakashi	0:8fdf9a60065b	1274	uint32_t RESERVED2[131U];
kadonotakashi	0:8fdf9a60065b	1275	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
kadonotakashi	0:8fdf9a60065b	1276	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
kadonotakashi	0:8fdf9a60065b	1277	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
kadonotakashi	0:8fdf9a60065b	1278	uint32_t RESERVED3[759U];
kadonotakashi	0:8fdf9a60065b	1279	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER Register /
kadonotakashi	0:8fdf9a60065b	1280	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
kadonotakashi	0:8fdf9a60065b	1281	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
kadonotakashi	0:8fdf9a60065b	1282	uint32_t RESERVED4[1U];
kadonotakashi	0:8fdf9a60065b	1283	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
kadonotakashi	0:8fdf9a60065b	1284	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
kadonotakashi	0:8fdf9a60065b	1285	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
kadonotakashi	0:8fdf9a60065b	1286	uint32_t RESERVED5[39U];
kadonotakashi	0:8fdf9a60065b	1287	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
kadonotakashi	0:8fdf9a60065b	1288	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
kadonotakashi	0:8fdf9a60065b	1289	uint32_t RESERVED7[8U];
kadonotakashi	0:8fdf9a60065b	1290	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
kadonotakashi	0:8fdf9a60065b	1291	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
kadonotakashi	0:8fdf9a60065b	1292	} TPI_Type;
kadonotakashi	0:8fdf9a60065b	1293
kadonotakashi	0:8fdf9a60065b	1294	/* TPI Asynchronous Clock Prescaler Register Definitions */
kadonotakashi	0:8fdf9a60065b	1295	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
kadonotakashi	0:8fdf9a60065b	1296	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
kadonotakashi	0:8fdf9a60065b	1297
kadonotakashi	0:8fdf9a60065b	1298	/* TPI Selected Pin Protocol Register Definitions */
kadonotakashi	0:8fdf9a60065b	1299	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
kadonotakashi	0:8fdf9a60065b	1300	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
kadonotakashi	0:8fdf9a60065b	1301
kadonotakashi	0:8fdf9a60065b	1302	/* TPI Formatter and Flush Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	1303	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
kadonotakashi	0:8fdf9a60065b	1304	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
kadonotakashi	0:8fdf9a60065b	1305
kadonotakashi	0:8fdf9a60065b	1306	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
kadonotakashi	0:8fdf9a60065b	1307	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
kadonotakashi	0:8fdf9a60065b	1308
kadonotakashi	0:8fdf9a60065b	1309	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
kadonotakashi	0:8fdf9a60065b	1310	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
kadonotakashi	0:8fdf9a60065b	1311
kadonotakashi	0:8fdf9a60065b	1312	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
kadonotakashi	0:8fdf9a60065b	1313	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
kadonotakashi	0:8fdf9a60065b	1314
kadonotakashi	0:8fdf9a60065b	1315	/* TPI Formatter and Flush Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1316	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
kadonotakashi	0:8fdf9a60065b	1317	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
kadonotakashi	0:8fdf9a60065b	1318
kadonotakashi	0:8fdf9a60065b	1319	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
kadonotakashi	0:8fdf9a60065b	1320	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
kadonotakashi	0:8fdf9a60065b	1321
kadonotakashi	0:8fdf9a60065b	1322	/* TPI TRIGGER Register Definitions */
kadonotakashi	0:8fdf9a60065b	1323	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
kadonotakashi	0:8fdf9a60065b	1324	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
kadonotakashi	0:8fdf9a60065b	1325
kadonotakashi	0:8fdf9a60065b	1326	/* TPI Integration ETM Data Register Definitions (FIFO0) */
kadonotakashi	0:8fdf9a60065b	1327	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
kadonotakashi	0:8fdf9a60065b	1328	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
kadonotakashi	0:8fdf9a60065b	1329
kadonotakashi	0:8fdf9a60065b	1330	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
kadonotakashi	0:8fdf9a60065b	1331	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
kadonotakashi	0:8fdf9a60065b	1332
kadonotakashi	0:8fdf9a60065b	1333	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
kadonotakashi	0:8fdf9a60065b	1334	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
kadonotakashi	0:8fdf9a60065b	1335
kadonotakashi	0:8fdf9a60065b	1336	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
kadonotakashi	0:8fdf9a60065b	1337	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
kadonotakashi	0:8fdf9a60065b	1338
kadonotakashi	0:8fdf9a60065b	1339	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
kadonotakashi	0:8fdf9a60065b	1340	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
kadonotakashi	0:8fdf9a60065b	1341
kadonotakashi	0:8fdf9a60065b	1342	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
kadonotakashi	0:8fdf9a60065b	1343	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
kadonotakashi	0:8fdf9a60065b	1344
kadonotakashi	0:8fdf9a60065b	1345	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
kadonotakashi	0:8fdf9a60065b	1346	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
kadonotakashi	0:8fdf9a60065b	1347
kadonotakashi	0:8fdf9a60065b	1348	/* TPI ITATBCTR2 Register Definitions */
kadonotakashi	0:8fdf9a60065b	1349	#define TPI_ITATBCTR2_ATREADY2_Pos 0U /!< TPI ITATBCTR2: ATREADY2 Position /
kadonotakashi	0:8fdf9a60065b	1350	#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/) /!< TPI ITATBCTR2: ATREADY2 Mask /
kadonotakashi	0:8fdf9a60065b	1351
kadonotakashi	0:8fdf9a60065b	1352	#define TPI_ITATBCTR2_ATREADY1_Pos 0U /!< TPI ITATBCTR2: ATREADY1 Position /
kadonotakashi	0:8fdf9a60065b	1353	#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/) /!< TPI ITATBCTR2: ATREADY1 Mask /
kadonotakashi	0:8fdf9a60065b	1354
kadonotakashi	0:8fdf9a60065b	1355	/* TPI Integration ITM Data Register Definitions (FIFO1) */
kadonotakashi	0:8fdf9a60065b	1356	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
kadonotakashi	0:8fdf9a60065b	1357	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
kadonotakashi	0:8fdf9a60065b	1358
kadonotakashi	0:8fdf9a60065b	1359	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
kadonotakashi	0:8fdf9a60065b	1360	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
kadonotakashi	0:8fdf9a60065b	1361
kadonotakashi	0:8fdf9a60065b	1362	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
kadonotakashi	0:8fdf9a60065b	1363	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
kadonotakashi	0:8fdf9a60065b	1364
kadonotakashi	0:8fdf9a60065b	1365	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
kadonotakashi	0:8fdf9a60065b	1366	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
kadonotakashi	0:8fdf9a60065b	1367
kadonotakashi	0:8fdf9a60065b	1368	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
kadonotakashi	0:8fdf9a60065b	1369	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
kadonotakashi	0:8fdf9a60065b	1370
kadonotakashi	0:8fdf9a60065b	1371	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
kadonotakashi	0:8fdf9a60065b	1372	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
kadonotakashi	0:8fdf9a60065b	1373
kadonotakashi	0:8fdf9a60065b	1374	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
kadonotakashi	0:8fdf9a60065b	1375	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
kadonotakashi	0:8fdf9a60065b	1376
kadonotakashi	0:8fdf9a60065b	1377	/* TPI ITATBCTR0 Register Definitions */
kadonotakashi	0:8fdf9a60065b	1378	#define TPI_ITATBCTR0_ATREADY2_Pos 0U /!< TPI ITATBCTR0: ATREADY2 Position /
kadonotakashi	0:8fdf9a60065b	1379	#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/) /!< TPI ITATBCTR0: ATREADY2 Mask /
kadonotakashi	0:8fdf9a60065b	1380
kadonotakashi	0:8fdf9a60065b	1381	#define TPI_ITATBCTR0_ATREADY1_Pos 0U /!< TPI ITATBCTR0: ATREADY1 Position /
kadonotakashi	0:8fdf9a60065b	1382	#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/) /!< TPI ITATBCTR0: ATREADY1 Mask /
kadonotakashi	0:8fdf9a60065b	1383
kadonotakashi	0:8fdf9a60065b	1384	/* TPI Integration Mode Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1385	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
kadonotakashi	0:8fdf9a60065b	1386	#define TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
kadonotakashi	0:8fdf9a60065b	1387
kadonotakashi	0:8fdf9a60065b	1388	/* TPI DEVID Register Definitions */
kadonotakashi	0:8fdf9a60065b	1389	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
kadonotakashi	0:8fdf9a60065b	1390	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
kadonotakashi	0:8fdf9a60065b	1391
kadonotakashi	0:8fdf9a60065b	1392	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
kadonotakashi	0:8fdf9a60065b	1393	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
kadonotakashi	0:8fdf9a60065b	1394
kadonotakashi	0:8fdf9a60065b	1395	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
kadonotakashi	0:8fdf9a60065b	1396	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
kadonotakashi	0:8fdf9a60065b	1397
kadonotakashi	0:8fdf9a60065b	1398	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
kadonotakashi	0:8fdf9a60065b	1399	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
kadonotakashi	0:8fdf9a60065b	1400
kadonotakashi	0:8fdf9a60065b	1401	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
kadonotakashi	0:8fdf9a60065b	1402	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
kadonotakashi	0:8fdf9a60065b	1403
kadonotakashi	0:8fdf9a60065b	1404	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
kadonotakashi	0:8fdf9a60065b	1405	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
kadonotakashi	0:8fdf9a60065b	1406
kadonotakashi	0:8fdf9a60065b	1407	/* TPI DEVTYPE Register Definitions */
kadonotakashi	0:8fdf9a60065b	1408	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
kadonotakashi	0:8fdf9a60065b	1409	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
kadonotakashi	0:8fdf9a60065b	1410
kadonotakashi	0:8fdf9a60065b	1411	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
kadonotakashi	0:8fdf9a60065b	1412	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
kadonotakashi	0:8fdf9a60065b	1413
kadonotakashi	0:8fdf9a60065b	1414	/@}/ /* end of group CMSIS_TPI */
kadonotakashi	0:8fdf9a60065b	1415
kadonotakashi	0:8fdf9a60065b	1416
kadonotakashi	0:8fdf9a60065b	1417	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	1418	/**
kadonotakashi	0:8fdf9a60065b	1419	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1420	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
kadonotakashi	0:8fdf9a60065b	1421	\brief Type definitions for the Memory Protection Unit (MPU)
kadonotakashi	0:8fdf9a60065b	1422	@{
kadonotakashi	0:8fdf9a60065b	1423	*/
kadonotakashi	0:8fdf9a60065b	1424
kadonotakashi	0:8fdf9a60065b	1425	/**
kadonotakashi	0:8fdf9a60065b	1426	\brief Structure type to access the Memory Protection Unit (MPU).
kadonotakashi	0:8fdf9a60065b	1427	*/
kadonotakashi	0:8fdf9a60065b	1428	typedef struct
kadonotakashi	0:8fdf9a60065b	1429	{
kadonotakashi	0:8fdf9a60065b	1430	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
kadonotakashi	0:8fdf9a60065b	1431	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
kadonotakashi	0:8fdf9a60065b	1432	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
kadonotakashi	0:8fdf9a60065b	1433	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
kadonotakashi	0:8fdf9a60065b	1434	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
kadonotakashi	0:8fdf9a60065b	1435	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
kadonotakashi	0:8fdf9a60065b	1436	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
kadonotakashi	0:8fdf9a60065b	1437	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
kadonotakashi	0:8fdf9a60065b	1438	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
kadonotakashi	0:8fdf9a60065b	1439	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
kadonotakashi	0:8fdf9a60065b	1440	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
kadonotakashi	0:8fdf9a60065b	1441	} MPU_Type;
kadonotakashi	0:8fdf9a60065b	1442
kadonotakashi	0:8fdf9a60065b	1443	#define MPU_TYPE_RALIASES 4U
kadonotakashi	0:8fdf9a60065b	1444
kadonotakashi	0:8fdf9a60065b	1445	/* MPU Type Register Definitions */
kadonotakashi	0:8fdf9a60065b	1446	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
kadonotakashi	0:8fdf9a60065b	1447	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
kadonotakashi	0:8fdf9a60065b	1448
kadonotakashi	0:8fdf9a60065b	1449	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
kadonotakashi	0:8fdf9a60065b	1450	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
kadonotakashi	0:8fdf9a60065b	1451
kadonotakashi	0:8fdf9a60065b	1452	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
kadonotakashi	0:8fdf9a60065b	1453	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
kadonotakashi	0:8fdf9a60065b	1454
kadonotakashi	0:8fdf9a60065b	1455	/* MPU Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1456	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
kadonotakashi	0:8fdf9a60065b	1457	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
kadonotakashi	0:8fdf9a60065b	1458
kadonotakashi	0:8fdf9a60065b	1459	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
kadonotakashi	0:8fdf9a60065b	1460	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
kadonotakashi	0:8fdf9a60065b	1461
kadonotakashi	0:8fdf9a60065b	1462	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
kadonotakashi	0:8fdf9a60065b	1463	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
kadonotakashi	0:8fdf9a60065b	1464
kadonotakashi	0:8fdf9a60065b	1465	/* MPU Region Number Register Definitions */
kadonotakashi	0:8fdf9a60065b	1466	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
kadonotakashi	0:8fdf9a60065b	1467	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
kadonotakashi	0:8fdf9a60065b	1468
kadonotakashi	0:8fdf9a60065b	1469	/* MPU Region Base Address Register Definitions */
kadonotakashi	0:8fdf9a60065b	1470	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
kadonotakashi	0:8fdf9a60065b	1471	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
kadonotakashi	0:8fdf9a60065b	1472
kadonotakashi	0:8fdf9a60065b	1473	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
kadonotakashi	0:8fdf9a60065b	1474	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
kadonotakashi	0:8fdf9a60065b	1475
kadonotakashi	0:8fdf9a60065b	1476	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
kadonotakashi	0:8fdf9a60065b	1477	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
kadonotakashi	0:8fdf9a60065b	1478
kadonotakashi	0:8fdf9a60065b	1479	/* MPU Region Attribute and Size Register Definitions */
kadonotakashi	0:8fdf9a60065b	1480	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
kadonotakashi	0:8fdf9a60065b	1481	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
kadonotakashi	0:8fdf9a60065b	1482
kadonotakashi	0:8fdf9a60065b	1483	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
kadonotakashi	0:8fdf9a60065b	1484	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
kadonotakashi	0:8fdf9a60065b	1485
kadonotakashi	0:8fdf9a60065b	1486	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
kadonotakashi	0:8fdf9a60065b	1487	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
kadonotakashi	0:8fdf9a60065b	1488
kadonotakashi	0:8fdf9a60065b	1489	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
kadonotakashi	0:8fdf9a60065b	1490	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
kadonotakashi	0:8fdf9a60065b	1491
kadonotakashi	0:8fdf9a60065b	1492	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
kadonotakashi	0:8fdf9a60065b	1493	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
kadonotakashi	0:8fdf9a60065b	1494
kadonotakashi	0:8fdf9a60065b	1495	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
kadonotakashi	0:8fdf9a60065b	1496	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
kadonotakashi	0:8fdf9a60065b	1497
kadonotakashi	0:8fdf9a60065b	1498	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
kadonotakashi	0:8fdf9a60065b	1499	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
kadonotakashi	0:8fdf9a60065b	1500
kadonotakashi	0:8fdf9a60065b	1501	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
kadonotakashi	0:8fdf9a60065b	1502	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
kadonotakashi	0:8fdf9a60065b	1503
kadonotakashi	0:8fdf9a60065b	1504	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
kadonotakashi	0:8fdf9a60065b	1505	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
kadonotakashi	0:8fdf9a60065b	1506
kadonotakashi	0:8fdf9a60065b	1507	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
kadonotakashi	0:8fdf9a60065b	1508	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
kadonotakashi	0:8fdf9a60065b	1509
kadonotakashi	0:8fdf9a60065b	1510	/@} end of group CMSIS_MPU /
kadonotakashi	0:8fdf9a60065b	1511	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
kadonotakashi	0:8fdf9a60065b	1512
kadonotakashi	0:8fdf9a60065b	1513
kadonotakashi	0:8fdf9a60065b	1514	/**
kadonotakashi	0:8fdf9a60065b	1515	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1516	\defgroup CMSIS_FPU Floating Point Unit (FPU)
kadonotakashi	0:8fdf9a60065b	1517	\brief Type definitions for the Floating Point Unit (FPU)
kadonotakashi	0:8fdf9a60065b	1518	@{
kadonotakashi	0:8fdf9a60065b	1519	*/
kadonotakashi	0:8fdf9a60065b	1520
kadonotakashi	0:8fdf9a60065b	1521	/**
kadonotakashi	0:8fdf9a60065b	1522	\brief Structure type to access the Floating Point Unit (FPU).
kadonotakashi	0:8fdf9a60065b	1523	*/
kadonotakashi	0:8fdf9a60065b	1524	typedef struct
kadonotakashi	0:8fdf9a60065b	1525	{
kadonotakashi	0:8fdf9a60065b	1526	uint32_t RESERVED0[1U];
kadonotakashi	0:8fdf9a60065b	1527	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
kadonotakashi	0:8fdf9a60065b	1528	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
kadonotakashi	0:8fdf9a60065b	1529	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
kadonotakashi	0:8fdf9a60065b	1530	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
kadonotakashi	0:8fdf9a60065b	1531	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
kadonotakashi	0:8fdf9a60065b	1532	__IM uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
kadonotakashi	0:8fdf9a60065b	1533	} FPU_Type;
kadonotakashi	0:8fdf9a60065b	1534
kadonotakashi	0:8fdf9a60065b	1535	/* Floating-Point Context Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1536	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
kadonotakashi	0:8fdf9a60065b	1537	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
kadonotakashi	0:8fdf9a60065b	1538
kadonotakashi	0:8fdf9a60065b	1539	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
kadonotakashi	0:8fdf9a60065b	1540	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
kadonotakashi	0:8fdf9a60065b	1541
kadonotakashi	0:8fdf9a60065b	1542	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
kadonotakashi	0:8fdf9a60065b	1543	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
kadonotakashi	0:8fdf9a60065b	1544
kadonotakashi	0:8fdf9a60065b	1545	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
kadonotakashi	0:8fdf9a60065b	1546	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
kadonotakashi	0:8fdf9a60065b	1547
kadonotakashi	0:8fdf9a60065b	1548	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
kadonotakashi	0:8fdf9a60065b	1549	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
kadonotakashi	0:8fdf9a60065b	1550
kadonotakashi	0:8fdf9a60065b	1551	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
kadonotakashi	0:8fdf9a60065b	1552	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
kadonotakashi	0:8fdf9a60065b	1553
kadonotakashi	0:8fdf9a60065b	1554	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
kadonotakashi	0:8fdf9a60065b	1555	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
kadonotakashi	0:8fdf9a60065b	1556
kadonotakashi	0:8fdf9a60065b	1557	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
kadonotakashi	0:8fdf9a60065b	1558	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
kadonotakashi	0:8fdf9a60065b	1559
kadonotakashi	0:8fdf9a60065b	1560	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
kadonotakashi	0:8fdf9a60065b	1561	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
kadonotakashi	0:8fdf9a60065b	1562
kadonotakashi	0:8fdf9a60065b	1563	/* Floating-Point Context Address Register Definitions */
kadonotakashi	0:8fdf9a60065b	1564	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
kadonotakashi	0:8fdf9a60065b	1565	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
kadonotakashi	0:8fdf9a60065b	1566
kadonotakashi	0:8fdf9a60065b	1567	/* Floating-Point Default Status Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1568	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
kadonotakashi	0:8fdf9a60065b	1569	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
kadonotakashi	0:8fdf9a60065b	1570
kadonotakashi	0:8fdf9a60065b	1571	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
kadonotakashi	0:8fdf9a60065b	1572	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
kadonotakashi	0:8fdf9a60065b	1573
kadonotakashi	0:8fdf9a60065b	1574	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
kadonotakashi	0:8fdf9a60065b	1575	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
kadonotakashi	0:8fdf9a60065b	1576
kadonotakashi	0:8fdf9a60065b	1577	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
kadonotakashi	0:8fdf9a60065b	1578	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
kadonotakashi	0:8fdf9a60065b	1579
kadonotakashi	0:8fdf9a60065b	1580	/* Media and FP Feature Register 0 Definitions */
kadonotakashi	0:8fdf9a60065b	1581	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
kadonotakashi	0:8fdf9a60065b	1582	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
kadonotakashi	0:8fdf9a60065b	1583
kadonotakashi	0:8fdf9a60065b	1584	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
kadonotakashi	0:8fdf9a60065b	1585	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
kadonotakashi	0:8fdf9a60065b	1586
kadonotakashi	0:8fdf9a60065b	1587	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
kadonotakashi	0:8fdf9a60065b	1588	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
kadonotakashi	0:8fdf9a60065b	1589
kadonotakashi	0:8fdf9a60065b	1590	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
kadonotakashi	0:8fdf9a60065b	1591	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
kadonotakashi	0:8fdf9a60065b	1592
kadonotakashi	0:8fdf9a60065b	1593	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
kadonotakashi	0:8fdf9a60065b	1594	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
kadonotakashi	0:8fdf9a60065b	1595
kadonotakashi	0:8fdf9a60065b	1596	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
kadonotakashi	0:8fdf9a60065b	1597	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
kadonotakashi	0:8fdf9a60065b	1598
kadonotakashi	0:8fdf9a60065b	1599	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
kadonotakashi	0:8fdf9a60065b	1600	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
kadonotakashi	0:8fdf9a60065b	1601
kadonotakashi	0:8fdf9a60065b	1602	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
kadonotakashi	0:8fdf9a60065b	1603	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
kadonotakashi	0:8fdf9a60065b	1604
kadonotakashi	0:8fdf9a60065b	1605	/* Media and FP Feature Register 1 Definitions */
kadonotakashi	0:8fdf9a60065b	1606	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
kadonotakashi	0:8fdf9a60065b	1607	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
kadonotakashi	0:8fdf9a60065b	1608
kadonotakashi	0:8fdf9a60065b	1609	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
kadonotakashi	0:8fdf9a60065b	1610	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
kadonotakashi	0:8fdf9a60065b	1611
kadonotakashi	0:8fdf9a60065b	1612	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
kadonotakashi	0:8fdf9a60065b	1613	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
kadonotakashi	0:8fdf9a60065b	1614
kadonotakashi	0:8fdf9a60065b	1615	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
kadonotakashi	0:8fdf9a60065b	1616	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
kadonotakashi	0:8fdf9a60065b	1617
kadonotakashi	0:8fdf9a60065b	1618	/* Media and FP Feature Register 2 Definitions */
kadonotakashi	0:8fdf9a60065b	1619
kadonotakashi	0:8fdf9a60065b	1620	/@} end of group CMSIS_FPU /
kadonotakashi	0:8fdf9a60065b	1621
kadonotakashi	0:8fdf9a60065b	1622
kadonotakashi	0:8fdf9a60065b	1623	/**
kadonotakashi	0:8fdf9a60065b	1624	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1625	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
kadonotakashi	0:8fdf9a60065b	1626	\brief Type definitions for the Core Debug Registers
kadonotakashi	0:8fdf9a60065b	1627	@{
kadonotakashi	0:8fdf9a60065b	1628	*/
kadonotakashi	0:8fdf9a60065b	1629
kadonotakashi	0:8fdf9a60065b	1630	/**
kadonotakashi	0:8fdf9a60065b	1631	\brief Structure type to access the Core Debug Register (CoreDebug).
kadonotakashi	0:8fdf9a60065b	1632	*/
kadonotakashi	0:8fdf9a60065b	1633	typedef struct
kadonotakashi	0:8fdf9a60065b	1634	{
kadonotakashi	0:8fdf9a60065b	1635	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
kadonotakashi	0:8fdf9a60065b	1636	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
kadonotakashi	0:8fdf9a60065b	1637	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
kadonotakashi	0:8fdf9a60065b	1638	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
kadonotakashi	0:8fdf9a60065b	1639	} CoreDebug_Type;
kadonotakashi	0:8fdf9a60065b	1640
kadonotakashi	0:8fdf9a60065b	1641	/* Debug Halting Control and Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	1642	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
kadonotakashi	0:8fdf9a60065b	1643	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
kadonotakashi	0:8fdf9a60065b	1644
kadonotakashi	0:8fdf9a60065b	1645	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
kadonotakashi	0:8fdf9a60065b	1646	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
kadonotakashi	0:8fdf9a60065b	1647
kadonotakashi	0:8fdf9a60065b	1648	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
kadonotakashi	0:8fdf9a60065b	1649	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
kadonotakashi	0:8fdf9a60065b	1650
kadonotakashi	0:8fdf9a60065b	1651	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
kadonotakashi	0:8fdf9a60065b	1652	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
kadonotakashi	0:8fdf9a60065b	1653
kadonotakashi	0:8fdf9a60065b	1654	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
kadonotakashi	0:8fdf9a60065b	1655	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
kadonotakashi	0:8fdf9a60065b	1656
kadonotakashi	0:8fdf9a60065b	1657	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
kadonotakashi	0:8fdf9a60065b	1658	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
kadonotakashi	0:8fdf9a60065b	1659
kadonotakashi	0:8fdf9a60065b	1660	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
kadonotakashi	0:8fdf9a60065b	1661	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
kadonotakashi	0:8fdf9a60065b	1662
kadonotakashi	0:8fdf9a60065b	1663	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
kadonotakashi	0:8fdf9a60065b	1664	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
kadonotakashi	0:8fdf9a60065b	1665
kadonotakashi	0:8fdf9a60065b	1666	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
kadonotakashi	0:8fdf9a60065b	1667	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
kadonotakashi	0:8fdf9a60065b	1668
kadonotakashi	0:8fdf9a60065b	1669	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
kadonotakashi	0:8fdf9a60065b	1670	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
kadonotakashi	0:8fdf9a60065b	1671
kadonotakashi	0:8fdf9a60065b	1672	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
kadonotakashi	0:8fdf9a60065b	1673	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
kadonotakashi	0:8fdf9a60065b	1674
kadonotakashi	0:8fdf9a60065b	1675	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
kadonotakashi	0:8fdf9a60065b	1676	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
kadonotakashi	0:8fdf9a60065b	1677
kadonotakashi	0:8fdf9a60065b	1678	/* Debug Core Register Selector Register Definitions */
kadonotakashi	0:8fdf9a60065b	1679	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
kadonotakashi	0:8fdf9a60065b	1680	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
kadonotakashi	0:8fdf9a60065b	1681
kadonotakashi	0:8fdf9a60065b	1682	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
kadonotakashi	0:8fdf9a60065b	1683	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1684
kadonotakashi	0:8fdf9a60065b	1685	/* Debug Exception and Monitor Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1686	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
kadonotakashi	0:8fdf9a60065b	1687	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
kadonotakashi	0:8fdf9a60065b	1688
kadonotakashi	0:8fdf9a60065b	1689	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
kadonotakashi	0:8fdf9a60065b	1690	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
kadonotakashi	0:8fdf9a60065b	1691
kadonotakashi	0:8fdf9a60065b	1692	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
kadonotakashi	0:8fdf9a60065b	1693	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
kadonotakashi	0:8fdf9a60065b	1694
kadonotakashi	0:8fdf9a60065b	1695	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
kadonotakashi	0:8fdf9a60065b	1696	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
kadonotakashi	0:8fdf9a60065b	1697
kadonotakashi	0:8fdf9a60065b	1698	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
kadonotakashi	0:8fdf9a60065b	1699	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
kadonotakashi	0:8fdf9a60065b	1700
kadonotakashi	0:8fdf9a60065b	1701	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
kadonotakashi	0:8fdf9a60065b	1702	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
kadonotakashi	0:8fdf9a60065b	1703
kadonotakashi	0:8fdf9a60065b	1704	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
kadonotakashi	0:8fdf9a60065b	1705	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
kadonotakashi	0:8fdf9a60065b	1706
kadonotakashi	0:8fdf9a60065b	1707	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
kadonotakashi	0:8fdf9a60065b	1708	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
kadonotakashi	0:8fdf9a60065b	1709
kadonotakashi	0:8fdf9a60065b	1710	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
kadonotakashi	0:8fdf9a60065b	1711	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
kadonotakashi	0:8fdf9a60065b	1712
kadonotakashi	0:8fdf9a60065b	1713	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
kadonotakashi	0:8fdf9a60065b	1714	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
kadonotakashi	0:8fdf9a60065b	1715
kadonotakashi	0:8fdf9a60065b	1716	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
kadonotakashi	0:8fdf9a60065b	1717	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
kadonotakashi	0:8fdf9a60065b	1718
kadonotakashi	0:8fdf9a60065b	1719	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
kadonotakashi	0:8fdf9a60065b	1720	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
kadonotakashi	0:8fdf9a60065b	1721
kadonotakashi	0:8fdf9a60065b	1722	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
kadonotakashi	0:8fdf9a60065b	1723	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
kadonotakashi	0:8fdf9a60065b	1724
kadonotakashi	0:8fdf9a60065b	1725	/@} end of group CMSIS_CoreDebug /
kadonotakashi	0:8fdf9a60065b	1726
kadonotakashi	0:8fdf9a60065b	1727
kadonotakashi	0:8fdf9a60065b	1728	/**
kadonotakashi	0:8fdf9a60065b	1729	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1730	\defgroup CMSIS_core_bitfield Core register bit field macros
kadonotakashi	0:8fdf9a60065b	1731	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
kadonotakashi	0:8fdf9a60065b	1732	@{
kadonotakashi	0:8fdf9a60065b	1733	*/
kadonotakashi	0:8fdf9a60065b	1734
kadonotakashi	0:8fdf9a60065b	1735	/**
kadonotakashi	0:8fdf9a60065b	1736	\brief Mask and shift a bit field value for use in a register bit range.
kadonotakashi	0:8fdf9a60065b	1737	\param[in] field Name of the register bit field.
kadonotakashi	0:8fdf9a60065b	1738	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
kadonotakashi	0:8fdf9a60065b	1739	\return Masked and shifted value.
kadonotakashi	0:8fdf9a60065b	1740	*/
kadonotakashi	0:8fdf9a60065b	1741	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
kadonotakashi	0:8fdf9a60065b	1742
kadonotakashi	0:8fdf9a60065b	1743	/**
kadonotakashi	0:8fdf9a60065b	1744	\brief Mask and shift a register value to extract a bit filed value.
kadonotakashi	0:8fdf9a60065b	1745	\param[in] field Name of the register bit field.
kadonotakashi	0:8fdf9a60065b	1746	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
kadonotakashi	0:8fdf9a60065b	1747	\return Masked and shifted bit field value.
kadonotakashi	0:8fdf9a60065b	1748	*/
kadonotakashi	0:8fdf9a60065b	1749	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
kadonotakashi	0:8fdf9a60065b	1750
kadonotakashi	0:8fdf9a60065b	1751	/@} end of group CMSIS_core_bitfield /
kadonotakashi	0:8fdf9a60065b	1752
kadonotakashi	0:8fdf9a60065b	1753
kadonotakashi	0:8fdf9a60065b	1754	/**
kadonotakashi	0:8fdf9a60065b	1755	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1756	\defgroup CMSIS_core_base Core Definitions
kadonotakashi	0:8fdf9a60065b	1757	\brief Definitions for base addresses, unions, and structures.
kadonotakashi	0:8fdf9a60065b	1758	@{
kadonotakashi	0:8fdf9a60065b	1759	*/
kadonotakashi	0:8fdf9a60065b	1760
kadonotakashi	0:8fdf9a60065b	1761	/* Memory mapping of Core Hardware */
kadonotakashi	0:8fdf9a60065b	1762	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
kadonotakashi	0:8fdf9a60065b	1763	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
kadonotakashi	0:8fdf9a60065b	1764	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
kadonotakashi	0:8fdf9a60065b	1765	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
kadonotakashi	0:8fdf9a60065b	1766	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
kadonotakashi	0:8fdf9a60065b	1767	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
kadonotakashi	0:8fdf9a60065b	1768	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
kadonotakashi	0:8fdf9a60065b	1769	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
kadonotakashi	0:8fdf9a60065b	1770
kadonotakashi	0:8fdf9a60065b	1771	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
kadonotakashi	0:8fdf9a60065b	1772	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
kadonotakashi	0:8fdf9a60065b	1773	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
kadonotakashi	0:8fdf9a60065b	1774	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
kadonotakashi	0:8fdf9a60065b	1775	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
kadonotakashi	0:8fdf9a60065b	1776	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
kadonotakashi	0:8fdf9a60065b	1777	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
kadonotakashi	0:8fdf9a60065b	1778	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
kadonotakashi	0:8fdf9a60065b	1779
kadonotakashi	0:8fdf9a60065b	1780	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	1781	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
kadonotakashi	0:8fdf9a60065b	1782	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
kadonotakashi	0:8fdf9a60065b	1783	#endif
kadonotakashi	0:8fdf9a60065b	1784
kadonotakashi	0:8fdf9a60065b	1785	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
kadonotakashi	0:8fdf9a60065b	1786	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
kadonotakashi	0:8fdf9a60065b	1787
kadonotakashi	0:8fdf9a60065b	1788	/@} /
kadonotakashi	0:8fdf9a60065b	1789
kadonotakashi	0:8fdf9a60065b	1790
kadonotakashi	0:8fdf9a60065b	1791
kadonotakashi	0:8fdf9a60065b	1792	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	1793	* Hardware Abstraction Layer
kadonotakashi	0:8fdf9a60065b	1794	Core Function Interface contains:
kadonotakashi	0:8fdf9a60065b	1795	- Core NVIC Functions
kadonotakashi	0:8fdf9a60065b	1796	- Core SysTick Functions
kadonotakashi	0:8fdf9a60065b	1797	- Core Debug Functions
kadonotakashi	0:8fdf9a60065b	1798	- Core Register Access Functions
kadonotakashi	0:8fdf9a60065b	1799	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	1800	/**
kadonotakashi	0:8fdf9a60065b	1801	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
kadonotakashi	0:8fdf9a60065b	1802	*/
kadonotakashi	0:8fdf9a60065b	1803
kadonotakashi	0:8fdf9a60065b	1804
kadonotakashi	0:8fdf9a60065b	1805
kadonotakashi	0:8fdf9a60065b	1806	/* ########################## NVIC functions #################################### */
kadonotakashi	0:8fdf9a60065b	1807	/**
kadonotakashi	0:8fdf9a60065b	1808	\ingroup CMSIS_Core_FunctionInterface
kadonotakashi	0:8fdf9a60065b	1809	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
kadonotakashi	0:8fdf9a60065b	1810	\brief Functions that manage interrupts and exceptions via the NVIC.
kadonotakashi	0:8fdf9a60065b	1811	@{
kadonotakashi	0:8fdf9a60065b	1812	*/
kadonotakashi	0:8fdf9a60065b	1813
kadonotakashi	0:8fdf9a60065b	1814	#ifdef CMSIS_NVIC_VIRTUAL
kadonotakashi	0:8fdf9a60065b	1815	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
kadonotakashi	0:8fdf9a60065b	1816	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
kadonotakashi	0:8fdf9a60065b	1817	#endif
kadonotakashi	0:8fdf9a60065b	1818	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
kadonotakashi	0:8fdf9a60065b	1819	#else
kadonotakashi	0:8fdf9a60065b	1820	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
kadonotakashi	0:8fdf9a60065b	1821	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
kadonotakashi	0:8fdf9a60065b	1822	#define NVIC_EnableIRQ __NVIC_EnableIRQ
kadonotakashi	0:8fdf9a60065b	1823	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
kadonotakashi	0:8fdf9a60065b	1824	#define NVIC_DisableIRQ __NVIC_DisableIRQ
kadonotakashi	0:8fdf9a60065b	1825	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
kadonotakashi	0:8fdf9a60065b	1826	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
kadonotakashi	0:8fdf9a60065b	1827	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
kadonotakashi	0:8fdf9a60065b	1828	#define NVIC_GetActive __NVIC_GetActive
kadonotakashi	0:8fdf9a60065b	1829	#define NVIC_SetPriority __NVIC_SetPriority
kadonotakashi	0:8fdf9a60065b	1830	#define NVIC_GetPriority __NVIC_GetPriority
kadonotakashi	0:8fdf9a60065b	1831	#define NVIC_SystemReset __NVIC_SystemReset
kadonotakashi	0:8fdf9a60065b	1832	#endif /* CMSIS_NVIC_VIRTUAL */
kadonotakashi	0:8fdf9a60065b	1833
kadonotakashi	0:8fdf9a60065b	1834	#ifdef CMSIS_VECTAB_VIRTUAL
kadonotakashi	0:8fdf9a60065b	1835	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kadonotakashi	0:8fdf9a60065b	1836	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
kadonotakashi	0:8fdf9a60065b	1837	#endif
kadonotakashi	0:8fdf9a60065b	1838	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kadonotakashi	0:8fdf9a60065b	1839	#else
kadonotakashi	0:8fdf9a60065b	1840	#define NVIC_SetVector __NVIC_SetVector
kadonotakashi	0:8fdf9a60065b	1841	#define NVIC_GetVector __NVIC_GetVector
kadonotakashi	0:8fdf9a60065b	1842	#endif /* (CMSIS_VECTAB_VIRTUAL) */
kadonotakashi	0:8fdf9a60065b	1843
kadonotakashi	0:8fdf9a60065b	1844	#define NVIC_USER_IRQ_OFFSET 16
kadonotakashi	0:8fdf9a60065b	1845
kadonotakashi	0:8fdf9a60065b	1846
kadonotakashi	0:8fdf9a60065b	1847	/* The following EXC_RETURN values are saved the LR on exception entry */
kadonotakashi	0:8fdf9a60065b	1848	#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
kadonotakashi	0:8fdf9a60065b	1849	#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
kadonotakashi	0:8fdf9a60065b	1850	#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
kadonotakashi	0:8fdf9a60065b	1851	#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
kadonotakashi	0:8fdf9a60065b	1852	#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
kadonotakashi	0:8fdf9a60065b	1853	#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
kadonotakashi	0:8fdf9a60065b	1854
kadonotakashi	0:8fdf9a60065b	1855
kadonotakashi	0:8fdf9a60065b	1856	/**
kadonotakashi	0:8fdf9a60065b	1857	\brief Set Priority Grouping
kadonotakashi	0:8fdf9a60065b	1858	\details Sets the priority grouping field using the required unlock sequence.
kadonotakashi	0:8fdf9a60065b	1859	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
kadonotakashi	0:8fdf9a60065b	1860	Only values from 0..7 are used.
kadonotakashi	0:8fdf9a60065b	1861	In case of a conflict between priority grouping and available
kadonotakashi	0:8fdf9a60065b	1862	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kadonotakashi	0:8fdf9a60065b	1863	\param [in] PriorityGroup Priority grouping field.
kadonotakashi	0:8fdf9a60065b	1864	*/
kadonotakashi	0:8fdf9a60065b	1865	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
kadonotakashi	0:8fdf9a60065b	1866	{
kadonotakashi	0:8fdf9a60065b	1867	uint32_t reg_value;
kadonotakashi	0:8fdf9a60065b	1868	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kadonotakashi	0:8fdf9a60065b	1869
kadonotakashi	0:8fdf9a60065b	1870	reg_value = SCB->AIRCR; /* read old register configuration */
kadonotakashi	0:8fdf9a60065b	1871	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
kadonotakashi	0:8fdf9a60065b	1872	reg_value = (reg_value \|
kadonotakashi	0:8fdf9a60065b	1873	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
kadonotakashi	0:8fdf9a60065b	1874	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
kadonotakashi	0:8fdf9a60065b	1875	SCB->AIRCR = reg_value;
kadonotakashi	0:8fdf9a60065b	1876	}
kadonotakashi	0:8fdf9a60065b	1877
kadonotakashi	0:8fdf9a60065b	1878
kadonotakashi	0:8fdf9a60065b	1879	/**
kadonotakashi	0:8fdf9a60065b	1880	\brief Get Priority Grouping
kadonotakashi	0:8fdf9a60065b	1881	\details Reads the priority grouping field from the NVIC Interrupt Controller.
kadonotakashi	0:8fdf9a60065b	1882	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
kadonotakashi	0:8fdf9a60065b	1883	*/
kadonotakashi	0:8fdf9a60065b	1884	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
kadonotakashi	0:8fdf9a60065b	1885	{
kadonotakashi	0:8fdf9a60065b	1886	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
kadonotakashi	0:8fdf9a60065b	1887	}
kadonotakashi	0:8fdf9a60065b	1888
kadonotakashi	0:8fdf9a60065b	1889
kadonotakashi	0:8fdf9a60065b	1890	/**
kadonotakashi	0:8fdf9a60065b	1891	\brief Enable Interrupt
kadonotakashi	0:8fdf9a60065b	1892	\details Enables a device specific interrupt in the NVIC interrupt controller.
kadonotakashi	0:8fdf9a60065b	1893	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1894	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1895	*/
kadonotakashi	0:8fdf9a60065b	1896	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1897	{
kadonotakashi	0:8fdf9a60065b	1898	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1899	{
kadonotakashi	0:8fdf9a60065b	1900	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kadonotakashi	0:8fdf9a60065b	1901	}
kadonotakashi	0:8fdf9a60065b	1902	}
kadonotakashi	0:8fdf9a60065b	1903
kadonotakashi	0:8fdf9a60065b	1904
kadonotakashi	0:8fdf9a60065b	1905	/**
kadonotakashi	0:8fdf9a60065b	1906	\brief Get Interrupt Enable status
kadonotakashi	0:8fdf9a60065b	1907	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
kadonotakashi	0:8fdf9a60065b	1908	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1909	\return 0 Interrupt is not enabled.
kadonotakashi	0:8fdf9a60065b	1910	\return 1 Interrupt is enabled.
kadonotakashi	0:8fdf9a60065b	1911	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1912	*/
kadonotakashi	0:8fdf9a60065b	1913	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1914	{
kadonotakashi	0:8fdf9a60065b	1915	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1916	{
kadonotakashi	0:8fdf9a60065b	1917	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kadonotakashi	0:8fdf9a60065b	1918	}
kadonotakashi	0:8fdf9a60065b	1919	else
kadonotakashi	0:8fdf9a60065b	1920	{
kadonotakashi	0:8fdf9a60065b	1921	return(0U);
kadonotakashi	0:8fdf9a60065b	1922	}
kadonotakashi	0:8fdf9a60065b	1923	}
kadonotakashi	0:8fdf9a60065b	1924
kadonotakashi	0:8fdf9a60065b	1925
kadonotakashi	0:8fdf9a60065b	1926	/**
kadonotakashi	0:8fdf9a60065b	1927	\brief Disable Interrupt
kadonotakashi	0:8fdf9a60065b	1928	\details Disables a device specific interrupt in the NVIC interrupt controller.
kadonotakashi	0:8fdf9a60065b	1929	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1930	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1931	*/
kadonotakashi	0:8fdf9a60065b	1932	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1933	{
kadonotakashi	0:8fdf9a60065b	1934	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1935	{
kadonotakashi	0:8fdf9a60065b	1936	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kadonotakashi	0:8fdf9a60065b	1937	__DSB();
kadonotakashi	0:8fdf9a60065b	1938	__ISB();
kadonotakashi	0:8fdf9a60065b	1939	}
kadonotakashi	0:8fdf9a60065b	1940	}
kadonotakashi	0:8fdf9a60065b	1941
kadonotakashi	0:8fdf9a60065b	1942
kadonotakashi	0:8fdf9a60065b	1943	/**
kadonotakashi	0:8fdf9a60065b	1944	\brief Get Pending Interrupt
kadonotakashi	0:8fdf9a60065b	1945	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
kadonotakashi	0:8fdf9a60065b	1946	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1947	\return 0 Interrupt status is not pending.
kadonotakashi	0:8fdf9a60065b	1948	\return 1 Interrupt status is pending.
kadonotakashi	0:8fdf9a60065b	1949	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1950	*/
kadonotakashi	0:8fdf9a60065b	1951	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1952	{
kadonotakashi	0:8fdf9a60065b	1953	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1954	{
kadonotakashi	0:8fdf9a60065b	1955	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kadonotakashi	0:8fdf9a60065b	1956	}
kadonotakashi	0:8fdf9a60065b	1957	else
kadonotakashi	0:8fdf9a60065b	1958	{
kadonotakashi	0:8fdf9a60065b	1959	return(0U);
kadonotakashi	0:8fdf9a60065b	1960	}
kadonotakashi	0:8fdf9a60065b	1961	}
kadonotakashi	0:8fdf9a60065b	1962
kadonotakashi	0:8fdf9a60065b	1963
kadonotakashi	0:8fdf9a60065b	1964	/**
kadonotakashi	0:8fdf9a60065b	1965	\brief Set Pending Interrupt
kadonotakashi	0:8fdf9a60065b	1966	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
kadonotakashi	0:8fdf9a60065b	1967	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1968	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1969	*/
kadonotakashi	0:8fdf9a60065b	1970	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1971	{
kadonotakashi	0:8fdf9a60065b	1972	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1973	{
kadonotakashi	0:8fdf9a60065b	1974	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kadonotakashi	0:8fdf9a60065b	1975	}
kadonotakashi	0:8fdf9a60065b	1976	}
kadonotakashi	0:8fdf9a60065b	1977
kadonotakashi	0:8fdf9a60065b	1978
kadonotakashi	0:8fdf9a60065b	1979	/**
kadonotakashi	0:8fdf9a60065b	1980	\brief Clear Pending Interrupt
kadonotakashi	0:8fdf9a60065b	1981	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
kadonotakashi	0:8fdf9a60065b	1982	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1983	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1984	*/
kadonotakashi	0:8fdf9a60065b	1985	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1986	{
kadonotakashi	0:8fdf9a60065b	1987	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1988	{
kadonotakashi	0:8fdf9a60065b	1989	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kadonotakashi	0:8fdf9a60065b	1990	}
kadonotakashi	0:8fdf9a60065b	1991	}
kadonotakashi	0:8fdf9a60065b	1992
kadonotakashi	0:8fdf9a60065b	1993
kadonotakashi	0:8fdf9a60065b	1994	/**
kadonotakashi	0:8fdf9a60065b	1995	\brief Get Active Interrupt
kadonotakashi	0:8fdf9a60065b	1996	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
kadonotakashi	0:8fdf9a60065b	1997	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1998	\return 0 Interrupt status is not active.
kadonotakashi	0:8fdf9a60065b	1999	\return 1 Interrupt status is active.
kadonotakashi	0:8fdf9a60065b	2000	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	2001	*/
kadonotakashi	0:8fdf9a60065b	2002	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	2003	{
kadonotakashi	0:8fdf9a60065b	2004	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	2005	{
kadonotakashi	0:8fdf9a60065b	2006	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kadonotakashi	0:8fdf9a60065b	2007	}
kadonotakashi	0:8fdf9a60065b	2008	else
kadonotakashi	0:8fdf9a60065b	2009	{
kadonotakashi	0:8fdf9a60065b	2010	return(0U);
kadonotakashi	0:8fdf9a60065b	2011	}
kadonotakashi	0:8fdf9a60065b	2012	}
kadonotakashi	0:8fdf9a60065b	2013
kadonotakashi	0:8fdf9a60065b	2014
kadonotakashi	0:8fdf9a60065b	2015	/**
kadonotakashi	0:8fdf9a60065b	2016	\brief Set Interrupt Priority
kadonotakashi	0:8fdf9a60065b	2017	\details Sets the priority of a device specific interrupt or a processor exception.
kadonotakashi	0:8fdf9a60065b	2018	The interrupt number can be positive to specify a device specific interrupt,
kadonotakashi	0:8fdf9a60065b	2019	or negative to specify a processor exception.
kadonotakashi	0:8fdf9a60065b	2020	\param [in] IRQn Interrupt number.
kadonotakashi	0:8fdf9a60065b	2021	\param [in] priority Priority to set.
kadonotakashi	0:8fdf9a60065b	2022	\note The priority cannot be set for every processor exception.
kadonotakashi	0:8fdf9a60065b	2023	*/
kadonotakashi	0:8fdf9a60065b	2024	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
kadonotakashi	0:8fdf9a60065b	2025	{
kadonotakashi	0:8fdf9a60065b	2026	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	2027	{
kadonotakashi	0:8fdf9a60065b	2028	NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kadonotakashi	0:8fdf9a60065b	2029	}
kadonotakashi	0:8fdf9a60065b	2030	else
kadonotakashi	0:8fdf9a60065b	2031	{
kadonotakashi	0:8fdf9a60065b	2032	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kadonotakashi	0:8fdf9a60065b	2033	}
kadonotakashi	0:8fdf9a60065b	2034	}
kadonotakashi	0:8fdf9a60065b	2035
kadonotakashi	0:8fdf9a60065b	2036
kadonotakashi	0:8fdf9a60065b	2037	/**
kadonotakashi	0:8fdf9a60065b	2038	\brief Get Interrupt Priority
kadonotakashi	0:8fdf9a60065b	2039	\details Reads the priority of a device specific interrupt or a processor exception.
kadonotakashi	0:8fdf9a60065b	2040	The interrupt number can be positive to specify a device specific interrupt,
kadonotakashi	0:8fdf9a60065b	2041	or negative to specify a processor exception.
kadonotakashi	0:8fdf9a60065b	2042	\param [in] IRQn Interrupt number.
kadonotakashi	0:8fdf9a60065b	2043	\return Interrupt Priority.
kadonotakashi	0:8fdf9a60065b	2044	Value is aligned automatically to the implemented priority bits of the microcontroller.
kadonotakashi	0:8fdf9a60065b	2045	*/
kadonotakashi	0:8fdf9a60065b	2046	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	2047	{
kadonotakashi	0:8fdf9a60065b	2048
kadonotakashi	0:8fdf9a60065b	2049	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	2050	{
kadonotakashi	0:8fdf9a60065b	2051	return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
kadonotakashi	0:8fdf9a60065b	2052	}
kadonotakashi	0:8fdf9a60065b	2053	else
kadonotakashi	0:8fdf9a60065b	2054	{
kadonotakashi	0:8fdf9a60065b	2055	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
kadonotakashi	0:8fdf9a60065b	2056	}
kadonotakashi	0:8fdf9a60065b	2057	}
kadonotakashi	0:8fdf9a60065b	2058
kadonotakashi	0:8fdf9a60065b	2059
kadonotakashi	0:8fdf9a60065b	2060	/**
kadonotakashi	0:8fdf9a60065b	2061	\brief Encode Priority
kadonotakashi	0:8fdf9a60065b	2062	\details Encodes the priority for an interrupt with the given priority group,
kadonotakashi	0:8fdf9a60065b	2063	preemptive priority value, and subpriority value.
kadonotakashi	0:8fdf9a60065b	2064	In case of a conflict between priority grouping and available
kadonotakashi	0:8fdf9a60065b	2065	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kadonotakashi	0:8fdf9a60065b	2066	\param [in] PriorityGroup Used priority group.
kadonotakashi	0:8fdf9a60065b	2067	\param [in] PreemptPriority Preemptive priority value (starting from 0).
kadonotakashi	0:8fdf9a60065b	2068	\param [in] SubPriority Subpriority value (starting from 0).
kadonotakashi	0:8fdf9a60065b	2069	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
kadonotakashi	0:8fdf9a60065b	2070	*/
kadonotakashi	0:8fdf9a60065b	2071	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
kadonotakashi	0:8fdf9a60065b	2072	{
kadonotakashi	0:8fdf9a60065b	2073	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kadonotakashi	0:8fdf9a60065b	2074	uint32_t PreemptPriorityBits;
kadonotakashi	0:8fdf9a60065b	2075	uint32_t SubPriorityBits;
kadonotakashi	0:8fdf9a60065b	2076
kadonotakashi	0:8fdf9a60065b	2077	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kadonotakashi	0:8fdf9a60065b	2078	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kadonotakashi	0:8fdf9a60065b	2079
kadonotakashi	0:8fdf9a60065b	2080	return (
kadonotakashi	0:8fdf9a60065b	2081	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
kadonotakashi	0:8fdf9a60065b	2082	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
kadonotakashi	0:8fdf9a60065b	2083	);
kadonotakashi	0:8fdf9a60065b	2084	}
kadonotakashi	0:8fdf9a60065b	2085
kadonotakashi	0:8fdf9a60065b	2086
kadonotakashi	0:8fdf9a60065b	2087	/**
kadonotakashi	0:8fdf9a60065b	2088	\brief Decode Priority
kadonotakashi	0:8fdf9a60065b	2089	\details Decodes an interrupt priority value with a given priority group to
kadonotakashi	0:8fdf9a60065b	2090	preemptive priority value and subpriority value.
kadonotakashi	0:8fdf9a60065b	2091	In case of a conflict between priority grouping and available
kadonotakashi	0:8fdf9a60065b	2092	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
kadonotakashi	0:8fdf9a60065b	2093	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
kadonotakashi	0:8fdf9a60065b	2094	\param [in] PriorityGroup Used priority group.
kadonotakashi	0:8fdf9a60065b	2095	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
kadonotakashi	0:8fdf9a60065b	2096	\param [out] pSubPriority Subpriority value (starting from 0).
kadonotakashi	0:8fdf9a60065b	2097	*/
kadonotakashi	0:8fdf9a60065b	2098	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
kadonotakashi	0:8fdf9a60065b	2099	{
kadonotakashi	0:8fdf9a60065b	2100	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kadonotakashi	0:8fdf9a60065b	2101	uint32_t PreemptPriorityBits;
kadonotakashi	0:8fdf9a60065b	2102	uint32_t SubPriorityBits;
kadonotakashi	0:8fdf9a60065b	2103
kadonotakashi	0:8fdf9a60065b	2104	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kadonotakashi	0:8fdf9a60065b	2105	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kadonotakashi	0:8fdf9a60065b	2106
kadonotakashi	0:8fdf9a60065b	2107	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
kadonotakashi	0:8fdf9a60065b	2108	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
kadonotakashi	0:8fdf9a60065b	2109	}
kadonotakashi	0:8fdf9a60065b	2110
kadonotakashi	0:8fdf9a60065b	2111
kadonotakashi	0:8fdf9a60065b	2112	/**
kadonotakashi	0:8fdf9a60065b	2113	\brief Set Interrupt Vector
kadonotakashi	0:8fdf9a60065b	2114	\details Sets an interrupt vector in SRAM based interrupt vector table.
kadonotakashi	0:8fdf9a60065b	2115	The interrupt number can be positive to specify a device specific interrupt,
kadonotakashi	0:8fdf9a60065b	2116	or negative to specify a processor exception.
kadonotakashi	0:8fdf9a60065b	2117	VTOR must been relocated to SRAM before.
kadonotakashi	0:8fdf9a60065b	2118	\param [in] IRQn Interrupt number
kadonotakashi	0:8fdf9a60065b	2119	\param [in] vector Address of interrupt handler function
kadonotakashi	0:8fdf9a60065b	2120	*/
kadonotakashi	0:8fdf9a60065b	2121	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
kadonotakashi	0:8fdf9a60065b	2122	{
kadonotakashi	0:8fdf9a60065b	2123	uint32_t vectors = (uint32_t )SCB->VTOR;
kadonotakashi	0:8fdf9a60065b	2124	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
kadonotakashi	0:8fdf9a60065b	2125	}
kadonotakashi	0:8fdf9a60065b	2126
kadonotakashi	0:8fdf9a60065b	2127
kadonotakashi	0:8fdf9a60065b	2128	/**
kadonotakashi	0:8fdf9a60065b	2129	\brief Get Interrupt Vector
kadonotakashi	0:8fdf9a60065b	2130	\details Reads an interrupt vector from interrupt vector table.
kadonotakashi	0:8fdf9a60065b	2131	The interrupt number can be positive to specify a device specific interrupt,
kadonotakashi	0:8fdf9a60065b	2132	or negative to specify a processor exception.
kadonotakashi	0:8fdf9a60065b	2133	\param [in] IRQn Interrupt number.
kadonotakashi	0:8fdf9a60065b	2134	\return Address of interrupt handler function
kadonotakashi	0:8fdf9a60065b	2135	*/
kadonotakashi	0:8fdf9a60065b	2136	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	2137	{
kadonotakashi	0:8fdf9a60065b	2138	uint32_t vectors = (uint32_t )SCB->VTOR;
kadonotakashi	0:8fdf9a60065b	2139	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
kadonotakashi	0:8fdf9a60065b	2140	}
kadonotakashi	0:8fdf9a60065b	2141
kadonotakashi	0:8fdf9a60065b	2142
kadonotakashi	0:8fdf9a60065b	2143	/**
kadonotakashi	0:8fdf9a60065b	2144	\brief System Reset
kadonotakashi	0:8fdf9a60065b	2145	\details Initiates a system reset request to reset the MCU.
kadonotakashi	0:8fdf9a60065b	2146	*/
kadonotakashi	0:8fdf9a60065b	2147	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
kadonotakashi	0:8fdf9a60065b	2148	{
kadonotakashi	0:8fdf9a60065b	2149	__DSB(); /* Ensure all outstanding memory accesses included
kadonotakashi	0:8fdf9a60065b	2150	buffered write are completed before reset */
kadonotakashi	0:8fdf9a60065b	2151	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
kadonotakashi	0:8fdf9a60065b	2152	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
kadonotakashi	0:8fdf9a60065b	2153	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
kadonotakashi	0:8fdf9a60065b	2154	__DSB(); /* Ensure completion of memory access */
kadonotakashi	0:8fdf9a60065b	2155
kadonotakashi	0:8fdf9a60065b	2156	for(;;) /* wait until reset */
kadonotakashi	0:8fdf9a60065b	2157	{
kadonotakashi	0:8fdf9a60065b	2158	__NOP();
kadonotakashi	0:8fdf9a60065b	2159	}
kadonotakashi	0:8fdf9a60065b	2160	}
kadonotakashi	0:8fdf9a60065b	2161
kadonotakashi	0:8fdf9a60065b	2162	/@} end of CMSIS_Core_NVICFunctions /
kadonotakashi	0:8fdf9a60065b	2163
kadonotakashi	0:8fdf9a60065b	2164	/* ########################## MPU functions #################################### */
kadonotakashi	0:8fdf9a60065b	2165
kadonotakashi	0:8fdf9a60065b	2166	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2167
kadonotakashi	0:8fdf9a60065b	2168	#include "mpu_armv7.h"
kadonotakashi	0:8fdf9a60065b	2169
kadonotakashi	0:8fdf9a60065b	2170	#endif
kadonotakashi	0:8fdf9a60065b	2171
kadonotakashi	0:8fdf9a60065b	2172	/* ########################## FPU functions #################################### */
kadonotakashi	0:8fdf9a60065b	2173	/**
kadonotakashi	0:8fdf9a60065b	2174	\ingroup CMSIS_Core_FunctionInterface
kadonotakashi	0:8fdf9a60065b	2175	\defgroup CMSIS_Core_FpuFunctions FPU Functions
kadonotakashi	0:8fdf9a60065b	2176	\brief Function that provides FPU type.
kadonotakashi	0:8fdf9a60065b	2177	@{
kadonotakashi	0:8fdf9a60065b	2178	*/
kadonotakashi	0:8fdf9a60065b	2179
kadonotakashi	0:8fdf9a60065b	2180	/**
kadonotakashi	0:8fdf9a60065b	2181	\brief get FPU type
kadonotakashi	0:8fdf9a60065b	2182	\details returns the FPU type
kadonotakashi	0:8fdf9a60065b	2183	\returns
kadonotakashi	0:8fdf9a60065b	2184	- \b 0: No FPU
kadonotakashi	0:8fdf9a60065b	2185	- \b 1: Single precision FPU
kadonotakashi	0:8fdf9a60065b	2186	- \b 2: Double + Single precision FPU
kadonotakashi	0:8fdf9a60065b	2187	*/
kadonotakashi	0:8fdf9a60065b	2188	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
kadonotakashi	0:8fdf9a60065b	2189	{
kadonotakashi	0:8fdf9a60065b	2190	uint32_t mvfr0;
kadonotakashi	0:8fdf9a60065b	2191
kadonotakashi	0:8fdf9a60065b	2192	mvfr0 = SCB->MVFR0;
kadonotakashi	0:8fdf9a60065b	2193	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
kadonotakashi	0:8fdf9a60065b	2194	{
kadonotakashi	0:8fdf9a60065b	2195	return 2U; /* Double + Single precision FPU */
kadonotakashi	0:8fdf9a60065b	2196	}
kadonotakashi	0:8fdf9a60065b	2197	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
kadonotakashi	0:8fdf9a60065b	2198	{
kadonotakashi	0:8fdf9a60065b	2199	return 1U; /* Single precision FPU */
kadonotakashi	0:8fdf9a60065b	2200	}
kadonotakashi	0:8fdf9a60065b	2201	else
kadonotakashi	0:8fdf9a60065b	2202	{
kadonotakashi	0:8fdf9a60065b	2203	return 0U; /* No FPU */
kadonotakashi	0:8fdf9a60065b	2204	}
kadonotakashi	0:8fdf9a60065b	2205	}
kadonotakashi	0:8fdf9a60065b	2206
kadonotakashi	0:8fdf9a60065b	2207
kadonotakashi	0:8fdf9a60065b	2208	/@} end of CMSIS_Core_FpuFunctions /
kadonotakashi	0:8fdf9a60065b	2209
kadonotakashi	0:8fdf9a60065b	2210
kadonotakashi	0:8fdf9a60065b	2211
kadonotakashi	0:8fdf9a60065b	2212	/* ########################## Cache functions #################################### */
kadonotakashi	0:8fdf9a60065b	2213	/**
kadonotakashi	0:8fdf9a60065b	2214	\ingroup CMSIS_Core_FunctionInterface
kadonotakashi	0:8fdf9a60065b	2215	\defgroup CMSIS_Core_CacheFunctions Cache Functions
kadonotakashi	0:8fdf9a60065b	2216	\brief Functions that configure Instruction and Data cache.
kadonotakashi	0:8fdf9a60065b	2217	@{
kadonotakashi	0:8fdf9a60065b	2218	*/
kadonotakashi	0:8fdf9a60065b	2219
kadonotakashi	0:8fdf9a60065b	2220	/* Cache Size ID Register Macros */
kadonotakashi	0:8fdf9a60065b	2221	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
kadonotakashi	0:8fdf9a60065b	2222	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
kadonotakashi	0:8fdf9a60065b	2223
kadonotakashi	0:8fdf9a60065b	2224
kadonotakashi	0:8fdf9a60065b	2225	/**
kadonotakashi	0:8fdf9a60065b	2226	\brief Enable I-Cache
kadonotakashi	0:8fdf9a60065b	2227	\details Turns on I-Cache
kadonotakashi	0:8fdf9a60065b	2228	*/
kadonotakashi	0:8fdf9a60065b	2229	__STATIC_INLINE void SCB_EnableICache (void)
kadonotakashi	0:8fdf9a60065b	2230	{
kadonotakashi	0:8fdf9a60065b	2231	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2232	__DSB();
kadonotakashi	0:8fdf9a60065b	2233	__ISB();
kadonotakashi	0:8fdf9a60065b	2234	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
kadonotakashi	0:8fdf9a60065b	2235	__DSB();
kadonotakashi	0:8fdf9a60065b	2236	__ISB();
kadonotakashi	0:8fdf9a60065b	2237	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
kadonotakashi	0:8fdf9a60065b	2238	__DSB();
kadonotakashi	0:8fdf9a60065b	2239	__ISB();
kadonotakashi	0:8fdf9a60065b	2240	#endif
kadonotakashi	0:8fdf9a60065b	2241	}
kadonotakashi	0:8fdf9a60065b	2242
kadonotakashi	0:8fdf9a60065b	2243
kadonotakashi	0:8fdf9a60065b	2244	/**
kadonotakashi	0:8fdf9a60065b	2245	\brief Disable I-Cache
kadonotakashi	0:8fdf9a60065b	2246	\details Turns off I-Cache
kadonotakashi	0:8fdf9a60065b	2247	*/
kadonotakashi	0:8fdf9a60065b	2248	__STATIC_INLINE void SCB_DisableICache (void)
kadonotakashi	0:8fdf9a60065b	2249	{
kadonotakashi	0:8fdf9a60065b	2250	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2251	__DSB();
kadonotakashi	0:8fdf9a60065b	2252	__ISB();
kadonotakashi	0:8fdf9a60065b	2253	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
kadonotakashi	0:8fdf9a60065b	2254	SCB->ICIALLU = 0UL; /* invalidate I-Cache */
kadonotakashi	0:8fdf9a60065b	2255	__DSB();
kadonotakashi	0:8fdf9a60065b	2256	__ISB();
kadonotakashi	0:8fdf9a60065b	2257	#endif
kadonotakashi	0:8fdf9a60065b	2258	}
kadonotakashi	0:8fdf9a60065b	2259
kadonotakashi	0:8fdf9a60065b	2260
kadonotakashi	0:8fdf9a60065b	2261	/**
kadonotakashi	0:8fdf9a60065b	2262	\brief Invalidate I-Cache
kadonotakashi	0:8fdf9a60065b	2263	\details Invalidates I-Cache
kadonotakashi	0:8fdf9a60065b	2264	*/
kadonotakashi	0:8fdf9a60065b	2265	__STATIC_INLINE void SCB_InvalidateICache (void)
kadonotakashi	0:8fdf9a60065b	2266	{
kadonotakashi	0:8fdf9a60065b	2267	#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2268	__DSB();
kadonotakashi	0:8fdf9a60065b	2269	__ISB();
kadonotakashi	0:8fdf9a60065b	2270	SCB->ICIALLU = 0UL;
kadonotakashi	0:8fdf9a60065b	2271	__DSB();
kadonotakashi	0:8fdf9a60065b	2272	__ISB();
kadonotakashi	0:8fdf9a60065b	2273	#endif
kadonotakashi	0:8fdf9a60065b	2274	}
kadonotakashi	0:8fdf9a60065b	2275
kadonotakashi	0:8fdf9a60065b	2276
kadonotakashi	0:8fdf9a60065b	2277	/**
kadonotakashi	0:8fdf9a60065b	2278	\brief Enable D-Cache
kadonotakashi	0:8fdf9a60065b	2279	\details Turns on D-Cache
kadonotakashi	0:8fdf9a60065b	2280	*/
kadonotakashi	0:8fdf9a60065b	2281	__STATIC_INLINE void SCB_EnableDCache (void)
kadonotakashi	0:8fdf9a60065b	2282	{
kadonotakashi	0:8fdf9a60065b	2283	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2284	uint32_t ccsidr;
kadonotakashi	0:8fdf9a60065b	2285	uint32_t sets;
kadonotakashi	0:8fdf9a60065b	2286	uint32_t ways;
kadonotakashi	0:8fdf9a60065b	2287
kadonotakashi	0:8fdf9a60065b	2288	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
kadonotakashi	0:8fdf9a60065b	2289	__DSB();
kadonotakashi	0:8fdf9a60065b	2290
kadonotakashi	0:8fdf9a60065b	2291	ccsidr = SCB->CCSIDR;
kadonotakashi	0:8fdf9a60065b	2292
kadonotakashi	0:8fdf9a60065b	2293	/* invalidate D-Cache */
kadonotakashi	0:8fdf9a60065b	2294	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
kadonotakashi	0:8fdf9a60065b	2295	do {
kadonotakashi	0:8fdf9a60065b	2296	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
kadonotakashi	0:8fdf9a60065b	2297	do {
kadonotakashi	0:8fdf9a60065b	2298	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
kadonotakashi	0:8fdf9a60065b	2299	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
kadonotakashi	0:8fdf9a60065b	2300	#if defined ( __CC_ARM )
kadonotakashi	0:8fdf9a60065b	2301	__schedule_barrier();
kadonotakashi	0:8fdf9a60065b	2302	#endif
kadonotakashi	0:8fdf9a60065b	2303	} while (ways-- != 0U);
kadonotakashi	0:8fdf9a60065b	2304	} while(sets-- != 0U);
kadonotakashi	0:8fdf9a60065b	2305	__DSB();
kadonotakashi	0:8fdf9a60065b	2306
kadonotakashi	0:8fdf9a60065b	2307	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
kadonotakashi	0:8fdf9a60065b	2308
kadonotakashi	0:8fdf9a60065b	2309	__DSB();
kadonotakashi	0:8fdf9a60065b	2310	__ISB();
kadonotakashi	0:8fdf9a60065b	2311	#endif
kadonotakashi	0:8fdf9a60065b	2312	}
kadonotakashi	0:8fdf9a60065b	2313
kadonotakashi	0:8fdf9a60065b	2314
kadonotakashi	0:8fdf9a60065b	2315	/**
kadonotakashi	0:8fdf9a60065b	2316	\brief Disable D-Cache
kadonotakashi	0:8fdf9a60065b	2317	\details Turns off D-Cache
kadonotakashi	0:8fdf9a60065b	2318	*/
kadonotakashi	0:8fdf9a60065b	2319	__STATIC_INLINE void SCB_DisableDCache (void)
kadonotakashi	0:8fdf9a60065b	2320	{
kadonotakashi	0:8fdf9a60065b	2321	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2322	uint32_t ccsidr;
kadonotakashi	0:8fdf9a60065b	2323	uint32_t sets;
kadonotakashi	0:8fdf9a60065b	2324	uint32_t ways;
kadonotakashi	0:8fdf9a60065b	2325
kadonotakashi	0:8fdf9a60065b	2326	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
kadonotakashi	0:8fdf9a60065b	2327	__DSB();
kadonotakashi	0:8fdf9a60065b	2328
kadonotakashi	0:8fdf9a60065b	2329	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
kadonotakashi	0:8fdf9a60065b	2330	__DSB();
kadonotakashi	0:8fdf9a60065b	2331
kadonotakashi	0:8fdf9a60065b	2332	ccsidr = SCB->CCSIDR;
kadonotakashi	0:8fdf9a60065b	2333
kadonotakashi	0:8fdf9a60065b	2334	/* clean & invalidate D-Cache */
kadonotakashi	0:8fdf9a60065b	2335	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
kadonotakashi	0:8fdf9a60065b	2336	do {
kadonotakashi	0:8fdf9a60065b	2337	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
kadonotakashi	0:8fdf9a60065b	2338	do {
kadonotakashi	0:8fdf9a60065b	2339	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
kadonotakashi	0:8fdf9a60065b	2340	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
kadonotakashi	0:8fdf9a60065b	2341	#if defined ( __CC_ARM )
kadonotakashi	0:8fdf9a60065b	2342	__schedule_barrier();
kadonotakashi	0:8fdf9a60065b	2343	#endif
kadonotakashi	0:8fdf9a60065b	2344	} while (ways-- != 0U);
kadonotakashi	0:8fdf9a60065b	2345	} while(sets-- != 0U);
kadonotakashi	0:8fdf9a60065b	2346
kadonotakashi	0:8fdf9a60065b	2347	__DSB();
kadonotakashi	0:8fdf9a60065b	2348	__ISB();
kadonotakashi	0:8fdf9a60065b	2349	#endif
kadonotakashi	0:8fdf9a60065b	2350	}
kadonotakashi	0:8fdf9a60065b	2351
kadonotakashi	0:8fdf9a60065b	2352
kadonotakashi	0:8fdf9a60065b	2353	/**
kadonotakashi	0:8fdf9a60065b	2354	\brief Invalidate D-Cache
kadonotakashi	0:8fdf9a60065b	2355	\details Invalidates D-Cache
kadonotakashi	0:8fdf9a60065b	2356	*/
kadonotakashi	0:8fdf9a60065b	2357	__STATIC_INLINE void SCB_InvalidateDCache (void)
kadonotakashi	0:8fdf9a60065b	2358	{
kadonotakashi	0:8fdf9a60065b	2359	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2360	uint32_t ccsidr;
kadonotakashi	0:8fdf9a60065b	2361	uint32_t sets;
kadonotakashi	0:8fdf9a60065b	2362	uint32_t ways;
kadonotakashi	0:8fdf9a60065b	2363
kadonotakashi	0:8fdf9a60065b	2364	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
kadonotakashi	0:8fdf9a60065b	2365	__DSB();
kadonotakashi	0:8fdf9a60065b	2366
kadonotakashi	0:8fdf9a60065b	2367	ccsidr = SCB->CCSIDR;
kadonotakashi	0:8fdf9a60065b	2368
kadonotakashi	0:8fdf9a60065b	2369	/* invalidate D-Cache */
kadonotakashi	0:8fdf9a60065b	2370	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
kadonotakashi	0:8fdf9a60065b	2371	do {
kadonotakashi	0:8fdf9a60065b	2372	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
kadonotakashi	0:8fdf9a60065b	2373	do {
kadonotakashi	0:8fdf9a60065b	2374	SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) \|
kadonotakashi	0:8fdf9a60065b	2375	((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
kadonotakashi	0:8fdf9a60065b	2376	#if defined ( __CC_ARM )
kadonotakashi	0:8fdf9a60065b	2377	__schedule_barrier();
kadonotakashi	0:8fdf9a60065b	2378	#endif
kadonotakashi	0:8fdf9a60065b	2379	} while (ways-- != 0U);
kadonotakashi	0:8fdf9a60065b	2380	} while(sets-- != 0U);
kadonotakashi	0:8fdf9a60065b	2381
kadonotakashi	0:8fdf9a60065b	2382	__DSB();
kadonotakashi	0:8fdf9a60065b	2383	__ISB();
kadonotakashi	0:8fdf9a60065b	2384	#endif
kadonotakashi	0:8fdf9a60065b	2385	}
kadonotakashi	0:8fdf9a60065b	2386
kadonotakashi	0:8fdf9a60065b	2387
kadonotakashi	0:8fdf9a60065b	2388	/**
kadonotakashi	0:8fdf9a60065b	2389	\brief Clean D-Cache
kadonotakashi	0:8fdf9a60065b	2390	\details Cleans D-Cache
kadonotakashi	0:8fdf9a60065b	2391	*/
kadonotakashi	0:8fdf9a60065b	2392	__STATIC_INLINE void SCB_CleanDCache (void)
kadonotakashi	0:8fdf9a60065b	2393	{
kadonotakashi	0:8fdf9a60065b	2394	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2395	uint32_t ccsidr;
kadonotakashi	0:8fdf9a60065b	2396	uint32_t sets;
kadonotakashi	0:8fdf9a60065b	2397	uint32_t ways;
kadonotakashi	0:8fdf9a60065b	2398
kadonotakashi	0:8fdf9a60065b	2399	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
kadonotakashi	0:8fdf9a60065b	2400	__DSB();
kadonotakashi	0:8fdf9a60065b	2401
kadonotakashi	0:8fdf9a60065b	2402	ccsidr = SCB->CCSIDR;
kadonotakashi	0:8fdf9a60065b	2403
kadonotakashi	0:8fdf9a60065b	2404	/* clean D-Cache */
kadonotakashi	0:8fdf9a60065b	2405	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
kadonotakashi	0:8fdf9a60065b	2406	do {
kadonotakashi	0:8fdf9a60065b	2407	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
kadonotakashi	0:8fdf9a60065b	2408	do {
kadonotakashi	0:8fdf9a60065b	2409	SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) \|
kadonotakashi	0:8fdf9a60065b	2410	((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
kadonotakashi	0:8fdf9a60065b	2411	#if defined ( __CC_ARM )
kadonotakashi	0:8fdf9a60065b	2412	__schedule_barrier();
kadonotakashi	0:8fdf9a60065b	2413	#endif
kadonotakashi	0:8fdf9a60065b	2414	} while (ways-- != 0U);
kadonotakashi	0:8fdf9a60065b	2415	} while(sets-- != 0U);
kadonotakashi	0:8fdf9a60065b	2416
kadonotakashi	0:8fdf9a60065b	2417	__DSB();
kadonotakashi	0:8fdf9a60065b	2418	__ISB();
kadonotakashi	0:8fdf9a60065b	2419	#endif
kadonotakashi	0:8fdf9a60065b	2420	}
kadonotakashi	0:8fdf9a60065b	2421
kadonotakashi	0:8fdf9a60065b	2422
kadonotakashi	0:8fdf9a60065b	2423	/**
kadonotakashi	0:8fdf9a60065b	2424	\brief Clean & Invalidate D-Cache
kadonotakashi	0:8fdf9a60065b	2425	\details Cleans and Invalidates D-Cache
kadonotakashi	0:8fdf9a60065b	2426	*/
kadonotakashi	0:8fdf9a60065b	2427	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
kadonotakashi	0:8fdf9a60065b	2428	{
kadonotakashi	0:8fdf9a60065b	2429	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2430	uint32_t ccsidr;
kadonotakashi	0:8fdf9a60065b	2431	uint32_t sets;
kadonotakashi	0:8fdf9a60065b	2432	uint32_t ways;
kadonotakashi	0:8fdf9a60065b	2433
kadonotakashi	0:8fdf9a60065b	2434	SCB->CSSELR = 0U; /(0U << 1U) \| 0U;/ /* Level 1 data cache */
kadonotakashi	0:8fdf9a60065b	2435	__DSB();
kadonotakashi	0:8fdf9a60065b	2436
kadonotakashi	0:8fdf9a60065b	2437	ccsidr = SCB->CCSIDR;
kadonotakashi	0:8fdf9a60065b	2438
kadonotakashi	0:8fdf9a60065b	2439	/* clean & invalidate D-Cache */
kadonotakashi	0:8fdf9a60065b	2440	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
kadonotakashi	0:8fdf9a60065b	2441	do {
kadonotakashi	0:8fdf9a60065b	2442	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
kadonotakashi	0:8fdf9a60065b	2443	do {
kadonotakashi	0:8fdf9a60065b	2444	SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) \|
kadonotakashi	0:8fdf9a60065b	2445	((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
kadonotakashi	0:8fdf9a60065b	2446	#if defined ( __CC_ARM )
kadonotakashi	0:8fdf9a60065b	2447	__schedule_barrier();
kadonotakashi	0:8fdf9a60065b	2448	#endif
kadonotakashi	0:8fdf9a60065b	2449	} while (ways-- != 0U);
kadonotakashi	0:8fdf9a60065b	2450	} while(sets-- != 0U);
kadonotakashi	0:8fdf9a60065b	2451
kadonotakashi	0:8fdf9a60065b	2452	__DSB();
kadonotakashi	0:8fdf9a60065b	2453	__ISB();
kadonotakashi	0:8fdf9a60065b	2454	#endif
kadonotakashi	0:8fdf9a60065b	2455	}
kadonotakashi	0:8fdf9a60065b	2456
kadonotakashi	0:8fdf9a60065b	2457
kadonotakashi	0:8fdf9a60065b	2458	/**
kadonotakashi	0:8fdf9a60065b	2459	\brief D-Cache Invalidate by address
kadonotakashi	0:8fdf9a60065b	2460	\details Invalidates D-Cache for the given address
kadonotakashi	0:8fdf9a60065b	2461	\param[in] addr address (aligned to 32-byte boundary)
kadonotakashi	0:8fdf9a60065b	2462	\param[in] dsize size of memory block (in number of bytes)
kadonotakashi	0:8fdf9a60065b	2463	*/
kadonotakashi	0:8fdf9a60065b	2464	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
kadonotakashi	0:8fdf9a60065b	2465	{
kadonotakashi	0:8fdf9a60065b	2466	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2467	int32_t op_size = dsize;
kadonotakashi	0:8fdf9a60065b	2468	uint32_t op_addr = (uint32_t)addr;
kadonotakashi	0:8fdf9a60065b	2469	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
kadonotakashi	0:8fdf9a60065b	2470
kadonotakashi	0:8fdf9a60065b	2471	__DSB();
kadonotakashi	0:8fdf9a60065b	2472
kadonotakashi	0:8fdf9a60065b	2473	while (op_size > 0) {
kadonotakashi	0:8fdf9a60065b	2474	SCB->DCIMVAC = op_addr;
kadonotakashi	0:8fdf9a60065b	2475	op_addr += (uint32_t)linesize;
kadonotakashi	0:8fdf9a60065b	2476	op_size -= linesize;
kadonotakashi	0:8fdf9a60065b	2477	}
kadonotakashi	0:8fdf9a60065b	2478
kadonotakashi	0:8fdf9a60065b	2479	__DSB();
kadonotakashi	0:8fdf9a60065b	2480	__ISB();
kadonotakashi	0:8fdf9a60065b	2481	#endif
kadonotakashi	0:8fdf9a60065b	2482	}
kadonotakashi	0:8fdf9a60065b	2483
kadonotakashi	0:8fdf9a60065b	2484
kadonotakashi	0:8fdf9a60065b	2485	/**
kadonotakashi	0:8fdf9a60065b	2486	\brief D-Cache Clean by address
kadonotakashi	0:8fdf9a60065b	2487	\details Cleans D-Cache for the given address
kadonotakashi	0:8fdf9a60065b	2488	\param[in] addr address (aligned to 32-byte boundary)
kadonotakashi	0:8fdf9a60065b	2489	\param[in] dsize size of memory block (in number of bytes)
kadonotakashi	0:8fdf9a60065b	2490	*/
kadonotakashi	0:8fdf9a60065b	2491	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
kadonotakashi	0:8fdf9a60065b	2492	{
kadonotakashi	0:8fdf9a60065b	2493	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2494	int32_t op_size = dsize;
kadonotakashi	0:8fdf9a60065b	2495	uint32_t op_addr = (uint32_t) addr;
kadonotakashi	0:8fdf9a60065b	2496	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
kadonotakashi	0:8fdf9a60065b	2497
kadonotakashi	0:8fdf9a60065b	2498	__DSB();
kadonotakashi	0:8fdf9a60065b	2499
kadonotakashi	0:8fdf9a60065b	2500	while (op_size > 0) {
kadonotakashi	0:8fdf9a60065b	2501	SCB->DCCMVAC = op_addr;
kadonotakashi	0:8fdf9a60065b	2502	op_addr += (uint32_t)linesize;
kadonotakashi	0:8fdf9a60065b	2503	op_size -= linesize;
kadonotakashi	0:8fdf9a60065b	2504	}
kadonotakashi	0:8fdf9a60065b	2505
kadonotakashi	0:8fdf9a60065b	2506	__DSB();
kadonotakashi	0:8fdf9a60065b	2507	__ISB();
kadonotakashi	0:8fdf9a60065b	2508	#endif
kadonotakashi	0:8fdf9a60065b	2509	}
kadonotakashi	0:8fdf9a60065b	2510
kadonotakashi	0:8fdf9a60065b	2511
kadonotakashi	0:8fdf9a60065b	2512	/**
kadonotakashi	0:8fdf9a60065b	2513	\brief D-Cache Clean and Invalidate by address
kadonotakashi	0:8fdf9a60065b	2514	\details Cleans and invalidates D_Cache for the given address
kadonotakashi	0:8fdf9a60065b	2515	\param[in] addr address (aligned to 32-byte boundary)
kadonotakashi	0:8fdf9a60065b	2516	\param[in] dsize size of memory block (in number of bytes)
kadonotakashi	0:8fdf9a60065b	2517	*/
kadonotakashi	0:8fdf9a60065b	2518	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
kadonotakashi	0:8fdf9a60065b	2519	{
kadonotakashi	0:8fdf9a60065b	2520	#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	2521	int32_t op_size = dsize;
kadonotakashi	0:8fdf9a60065b	2522	uint32_t op_addr = (uint32_t) addr;
kadonotakashi	0:8fdf9a60065b	2523	int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
kadonotakashi	0:8fdf9a60065b	2524
kadonotakashi	0:8fdf9a60065b	2525	__DSB();
kadonotakashi	0:8fdf9a60065b	2526
kadonotakashi	0:8fdf9a60065b	2527	while (op_size > 0) {
kadonotakashi	0:8fdf9a60065b	2528	SCB->DCCIMVAC = op_addr;
kadonotakashi	0:8fdf9a60065b	2529	op_addr += (uint32_t)linesize;
kadonotakashi	0:8fdf9a60065b	2530	op_size -= linesize;
kadonotakashi	0:8fdf9a60065b	2531	}
kadonotakashi	0:8fdf9a60065b	2532
kadonotakashi	0:8fdf9a60065b	2533	__DSB();
kadonotakashi	0:8fdf9a60065b	2534	__ISB();
kadonotakashi	0:8fdf9a60065b	2535	#endif
kadonotakashi	0:8fdf9a60065b	2536	}
kadonotakashi	0:8fdf9a60065b	2537
kadonotakashi	0:8fdf9a60065b	2538
kadonotakashi	0:8fdf9a60065b	2539	/@} end of CMSIS_Core_CacheFunctions /
kadonotakashi	0:8fdf9a60065b	2540
kadonotakashi	0:8fdf9a60065b	2541
kadonotakashi	0:8fdf9a60065b	2542
kadonotakashi	0:8fdf9a60065b	2543	/* ################################## SysTick function ############################################ */
kadonotakashi	0:8fdf9a60065b	2544	/**
kadonotakashi	0:8fdf9a60065b	2545	\ingroup CMSIS_Core_FunctionInterface
kadonotakashi	0:8fdf9a60065b	2546	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
kadonotakashi	0:8fdf9a60065b	2547	\brief Functions that configure the System.
kadonotakashi	0:8fdf9a60065b	2548	@{
kadonotakashi	0:8fdf9a60065b	2549	*/
kadonotakashi	0:8fdf9a60065b	2550
kadonotakashi	0:8fdf9a60065b	2551	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
kadonotakashi	0:8fdf9a60065b	2552
kadonotakashi	0:8fdf9a60065b	2553	/**
kadonotakashi	0:8fdf9a60065b	2554	\brief System Tick Configuration
kadonotakashi	0:8fdf9a60065b	2555	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
kadonotakashi	0:8fdf9a60065b	2556	Counter is in free running mode to generate periodic interrupts.
kadonotakashi	0:8fdf9a60065b	2557	\param [in] ticks Number of ticks between two interrupts.
kadonotakashi	0:8fdf9a60065b	2558	\return 0 Function succeeded.
kadonotakashi	0:8fdf9a60065b	2559	\return 1 Function failed.
kadonotakashi	0:8fdf9a60065b	2560	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
kadonotakashi	0:8fdf9a60065b	2561	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
kadonotakashi	0:8fdf9a60065b	2562	must contain a vendor-specific implementation of this function.
kadonotakashi	0:8fdf9a60065b	2563	*/
kadonotakashi	0:8fdf9a60065b	2564	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
kadonotakashi	0:8fdf9a60065b	2565	{
kadonotakashi	0:8fdf9a60065b	2566	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
kadonotakashi	0:8fdf9a60065b	2567	{
kadonotakashi	0:8fdf9a60065b	2568	return (1UL); /* Reload value impossible */
kadonotakashi	0:8fdf9a60065b	2569	}
kadonotakashi	0:8fdf9a60065b	2570
kadonotakashi	0:8fdf9a60065b	2571	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
kadonotakashi	0:8fdf9a60065b	2572	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
kadonotakashi	0:8fdf9a60065b	2573	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
kadonotakashi	0:8fdf9a60065b	2574	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
kadonotakashi	0:8fdf9a60065b	2575	SysTick_CTRL_TICKINT_Msk \|
kadonotakashi	0:8fdf9a60065b	2576	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
kadonotakashi	0:8fdf9a60065b	2577	return (0UL); /* Function successful */
kadonotakashi	0:8fdf9a60065b	2578	}
kadonotakashi	0:8fdf9a60065b	2579
kadonotakashi	0:8fdf9a60065b	2580	#endif
kadonotakashi	0:8fdf9a60065b	2581
kadonotakashi	0:8fdf9a60065b	2582	/@} end of CMSIS_Core_SysTickFunctions /
kadonotakashi	0:8fdf9a60065b	2583
kadonotakashi	0:8fdf9a60065b	2584
kadonotakashi	0:8fdf9a60065b	2585
kadonotakashi	0:8fdf9a60065b	2586	/* ##################################### Debug In/Output function ########################################### */
kadonotakashi	0:8fdf9a60065b	2587	/**
kadonotakashi	0:8fdf9a60065b	2588	\ingroup CMSIS_Core_FunctionInterface
kadonotakashi	0:8fdf9a60065b	2589	\defgroup CMSIS_core_DebugFunctions ITM Functions
kadonotakashi	0:8fdf9a60065b	2590	\brief Functions that access the ITM debug interface.
kadonotakashi	0:8fdf9a60065b	2591	@{
kadonotakashi	0:8fdf9a60065b	2592	*/
kadonotakashi	0:8fdf9a60065b	2593
kadonotakashi	0:8fdf9a60065b	2594	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
kadonotakashi	0:8fdf9a60065b	2595	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
kadonotakashi	0:8fdf9a60065b	2596
kadonotakashi	0:8fdf9a60065b	2597
kadonotakashi	0:8fdf9a60065b	2598	/**
kadonotakashi	0:8fdf9a60065b	2599	\brief ITM Send Character
kadonotakashi	0:8fdf9a60065b	2600	\details Transmits a character via the ITM channel 0, and
kadonotakashi	0:8fdf9a60065b	2601	\li Just returns when no debugger is connected that has booked the output.
kadonotakashi	0:8fdf9a60065b	2602	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
kadonotakashi	0:8fdf9a60065b	2603	\param [in] ch Character to transmit.
kadonotakashi	0:8fdf9a60065b	2604	\returns Character to transmit.
kadonotakashi	0:8fdf9a60065b	2605	*/
kadonotakashi	0:8fdf9a60065b	2606	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
kadonotakashi	0:8fdf9a60065b	2607	{
kadonotakashi	0:8fdf9a60065b	2608	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
kadonotakashi	0:8fdf9a60065b	2609	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
kadonotakashi	0:8fdf9a60065b	2610	{
kadonotakashi	0:8fdf9a60065b	2611	while (ITM->PORT[0U].u32 == 0UL)
kadonotakashi	0:8fdf9a60065b	2612	{
kadonotakashi	0:8fdf9a60065b	2613	__NOP();
kadonotakashi	0:8fdf9a60065b	2614	}
kadonotakashi	0:8fdf9a60065b	2615	ITM->PORT[0U].u8 = (uint8_t)ch;
kadonotakashi	0:8fdf9a60065b	2616	}
kadonotakashi	0:8fdf9a60065b	2617	return (ch);
kadonotakashi	0:8fdf9a60065b	2618	}
kadonotakashi	0:8fdf9a60065b	2619
kadonotakashi	0:8fdf9a60065b	2620
kadonotakashi	0:8fdf9a60065b	2621	/**
kadonotakashi	0:8fdf9a60065b	2622	\brief ITM Receive Character
kadonotakashi	0:8fdf9a60065b	2623	\details Inputs a character via the external variable \ref ITM_RxBuffer.
kadonotakashi	0:8fdf9a60065b	2624	\return Received character.
kadonotakashi	0:8fdf9a60065b	2625	\return -1 No character pending.
kadonotakashi	0:8fdf9a60065b	2626	*/
kadonotakashi	0:8fdf9a60065b	2627	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
kadonotakashi	0:8fdf9a60065b	2628	{
kadonotakashi	0:8fdf9a60065b	2629	int32_t ch = -1; /* no character available */
kadonotakashi	0:8fdf9a60065b	2630
kadonotakashi	0:8fdf9a60065b	2631	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
kadonotakashi	0:8fdf9a60065b	2632	{
kadonotakashi	0:8fdf9a60065b	2633	ch = ITM_RxBuffer;
kadonotakashi	0:8fdf9a60065b	2634	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
kadonotakashi	0:8fdf9a60065b	2635	}
kadonotakashi	0:8fdf9a60065b	2636
kadonotakashi	0:8fdf9a60065b	2637	return (ch);
kadonotakashi	0:8fdf9a60065b	2638	}
kadonotakashi	0:8fdf9a60065b	2639
kadonotakashi	0:8fdf9a60065b	2640
kadonotakashi	0:8fdf9a60065b	2641	/**
kadonotakashi	0:8fdf9a60065b	2642	\brief ITM Check Character
kadonotakashi	0:8fdf9a60065b	2643	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
kadonotakashi	0:8fdf9a60065b	2644	\return 0 No character available.
kadonotakashi	0:8fdf9a60065b	2645	\return 1 Character available.
kadonotakashi	0:8fdf9a60065b	2646	*/
kadonotakashi	0:8fdf9a60065b	2647	__STATIC_INLINE int32_t ITM_CheckChar (void)
kadonotakashi	0:8fdf9a60065b	2648	{
kadonotakashi	0:8fdf9a60065b	2649
kadonotakashi	0:8fdf9a60065b	2650	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
kadonotakashi	0:8fdf9a60065b	2651	{
kadonotakashi	0:8fdf9a60065b	2652	return (0); /* no character available */
kadonotakashi	0:8fdf9a60065b	2653	}
kadonotakashi	0:8fdf9a60065b	2654	else
kadonotakashi	0:8fdf9a60065b	2655	{
kadonotakashi	0:8fdf9a60065b	2656	return (1); /* character available */
kadonotakashi	0:8fdf9a60065b	2657	}
kadonotakashi	0:8fdf9a60065b	2658	}
kadonotakashi	0:8fdf9a60065b	2659
kadonotakashi	0:8fdf9a60065b	2660	/@} end of CMSIS_core_DebugFunctions /
kadonotakashi	0:8fdf9a60065b	2661
kadonotakashi	0:8fdf9a60065b	2662
kadonotakashi	0:8fdf9a60065b	2663
kadonotakashi	0:8fdf9a60065b	2664
kadonotakashi	0:8fdf9a60065b	2665	#ifdef __cplusplus
kadonotakashi	0:8fdf9a60065b	2666	}
kadonotakashi	0:8fdf9a60065b	2667	#endif
kadonotakashi	0:8fdf9a60065b	2668
kadonotakashi	0:8fdf9a60065b	2669	#endif /* __CORE_CM7_H_DEPENDANT */
kadonotakashi	0:8fdf9a60065b	2670
kadonotakashi	0:8fdf9a60065b	2671	#endif /* __CMSIS_GENERIC */

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Type:	Program
Mbed OS support:	Mbed OS
Created:	11 Oct 2018
Imports:	23
Forks:	0
Commits:	4
Dependents:	0
Dependencies:	1
Followers:	1

mbed-os/cmsis/TARGET_CORTEX_M/core_cm7.h@0:8fdf9a60065b, 2018-10-10 (annotated)

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