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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

mbed-os/cmsis/TARGET_CORTEX_M/core_cm3.h@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:: kadonotakashi
Date:: Wed Oct 10 00:33:53 2018 +0000
Revision:: 0:8fdf9a60065b

how to make mbed librry

Who changed what in which revision?

User	Revision	Line number	New contents of line
kadonotakashi	0:8fdf9a60065b	1	/************************************************************************//
kadonotakashi	0:8fdf9a60065b	2	* @file core_cm3.h
kadonotakashi	0:8fdf9a60065b	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
kadonotakashi	0:8fdf9a60065b	4	* @version V5.0.8
kadonotakashi	0:8fdf9a60065b	5	* @date 04. June 2018
kadonotakashi	0:8fdf9a60065b	6	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	7	/*
kadonotakashi	0:8fdf9a60065b	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
kadonotakashi	0:8fdf9a60065b	9	*
kadonotakashi	0:8fdf9a60065b	10	* SPDX-License-Identifier: Apache-2.0
kadonotakashi	0:8fdf9a60065b	11	*
kadonotakashi	0:8fdf9a60065b	12	* Licensed under the Apache License, Version 2.0 (the License); you may
kadonotakashi	0:8fdf9a60065b	13	* not use this file except in compliance with the License.
kadonotakashi	0:8fdf9a60065b	14	* You may obtain a copy of the License at
kadonotakashi	0:8fdf9a60065b	15	*
kadonotakashi	0:8fdf9a60065b	16	* www.apache.org/licenses/LICENSE-2.0
kadonotakashi	0:8fdf9a60065b	17	*
kadonotakashi	0:8fdf9a60065b	18	* Unless required by applicable law or agreed to in writing, software
kadonotakashi	0:8fdf9a60065b	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
kadonotakashi	0:8fdf9a60065b	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi	0:8fdf9a60065b	21	* See the License for the specific language governing permissions and
kadonotakashi	0:8fdf9a60065b	22	* limitations under the License.
kadonotakashi	0:8fdf9a60065b	23	*/
kadonotakashi	0:8fdf9a60065b	24
kadonotakashi	0:8fdf9a60065b	25	#if defined ( __ICCARM__ )
kadonotakashi	0:8fdf9a60065b	26	#pragma system_include /* treat file as system include file for MISRA check */
kadonotakashi	0:8fdf9a60065b	27	#elif defined (__clang__)
kadonotakashi	0:8fdf9a60065b	28	#pragma clang system_header /* treat file as system include file */
kadonotakashi	0:8fdf9a60065b	29	#endif
kadonotakashi	0:8fdf9a60065b	30
kadonotakashi	0:8fdf9a60065b	31	#ifndef __CORE_CM3_H_GENERIC
kadonotakashi	0:8fdf9a60065b	32	#define __CORE_CM3_H_GENERIC
kadonotakashi	0:8fdf9a60065b	33
kadonotakashi	0:8fdf9a60065b	34	#include <stdint.h>
kadonotakashi	0:8fdf9a60065b	35
kadonotakashi	0:8fdf9a60065b	36	#ifdef __cplusplus
kadonotakashi	0:8fdf9a60065b	37	extern "C" {
kadonotakashi	0:8fdf9a60065b	38	#endif
kadonotakashi	0:8fdf9a60065b	39
kadonotakashi	0:8fdf9a60065b	40	/**
kadonotakashi	0:8fdf9a60065b	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
kadonotakashi	0:8fdf9a60065b	42	CMSIS violates the following MISRA-C:2004 rules:
kadonotakashi	0:8fdf9a60065b	43
kadonotakashi	0:8fdf9a60065b	44	\li Required Rule 8.5, object/function definition in header file.<br>
kadonotakashi	0:8fdf9a60065b	45	Function definitions in header files are used to allow 'inlining'.
kadonotakashi	0:8fdf9a60065b	46
kadonotakashi	0:8fdf9a60065b	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
kadonotakashi	0:8fdf9a60065b	48	Unions are used for effective representation of core registers.
kadonotakashi	0:8fdf9a60065b	49
kadonotakashi	0:8fdf9a60065b	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
kadonotakashi	0:8fdf9a60065b	51	Function-like macros are used to allow more efficient code.
kadonotakashi	0:8fdf9a60065b	52	*/
kadonotakashi	0:8fdf9a60065b	53
kadonotakashi	0:8fdf9a60065b	54
kadonotakashi	0:8fdf9a60065b	55	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	56	* CMSIS definitions
kadonotakashi	0:8fdf9a60065b	57	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	58	/**
kadonotakashi	0:8fdf9a60065b	59	\ingroup Cortex_M3
kadonotakashi	0:8fdf9a60065b	60	@{
kadonotakashi	0:8fdf9a60065b	61	*/
kadonotakashi	0:8fdf9a60065b	62
kadonotakashi	0:8fdf9a60065b	63	#include "cmsis_version.h"
kadonotakashi	0:8fdf9a60065b	64
kadonotakashi	0:8fdf9a60065b	65	/* CMSIS CM3 definitions */
kadonotakashi	0:8fdf9a60065b	66	#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
kadonotakashi	0:8fdf9a60065b	67	#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
kadonotakashi	0:8fdf9a60065b	68	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) \| \
kadonotakashi	0:8fdf9a60065b	69	__CM3_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
kadonotakashi	0:8fdf9a60065b	70
kadonotakashi	0:8fdf9a60065b	71	#define __CORTEX_M (3U) /!< Cortex-M Core /
kadonotakashi	0:8fdf9a60065b	72
kadonotakashi	0:8fdf9a60065b	73	/** __FPU_USED indicates whether an FPU is used or not.
kadonotakashi	0:8fdf9a60065b	74	This core does not support an FPU at all
kadonotakashi	0:8fdf9a60065b	75	*/
kadonotakashi	0:8fdf9a60065b	76	#define __FPU_USED 0U
kadonotakashi	0:8fdf9a60065b	77
kadonotakashi	0:8fdf9a60065b	78	#if defined ( __CC_ARM )
kadonotakashi	0:8fdf9a60065b	79	#if defined __TARGET_FPU_VFP
kadonotakashi	0:8fdf9a60065b	80	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	81	#endif
kadonotakashi	0:8fdf9a60065b	82
kadonotakashi	0:8fdf9a60065b	83	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
kadonotakashi	0:8fdf9a60065b	84	#if defined __ARM_PCS_VFP
kadonotakashi	0:8fdf9a60065b	85	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	86	#endif
kadonotakashi	0:8fdf9a60065b	87
kadonotakashi	0:8fdf9a60065b	88	#elif defined ( __GNUC__ )
kadonotakashi	0:8fdf9a60065b	89	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
kadonotakashi	0:8fdf9a60065b	90	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	91	#endif
kadonotakashi	0:8fdf9a60065b	92
kadonotakashi	0:8fdf9a60065b	93	#elif defined ( __ICCARM__ )
kadonotakashi	0:8fdf9a60065b	94	#if defined __ARMVFP__
kadonotakashi	0:8fdf9a60065b	95	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	96	#endif
kadonotakashi	0:8fdf9a60065b	97
kadonotakashi	0:8fdf9a60065b	98	#elif defined ( __TI_ARM__ )
kadonotakashi	0:8fdf9a60065b	99	#if defined __TI_VFP_SUPPORT__
kadonotakashi	0:8fdf9a60065b	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	101	#endif
kadonotakashi	0:8fdf9a60065b	102
kadonotakashi	0:8fdf9a60065b	103	#elif defined ( __TASKING__ )
kadonotakashi	0:8fdf9a60065b	104	#if defined __FPU_VFP__
kadonotakashi	0:8fdf9a60065b	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	106	#endif
kadonotakashi	0:8fdf9a60065b	107
kadonotakashi	0:8fdf9a60065b	108	#elif defined ( __CSMC__ )
kadonotakashi	0:8fdf9a60065b	109	#if ( __CSMC__ & 0x400U)
kadonotakashi	0:8fdf9a60065b	110	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kadonotakashi	0:8fdf9a60065b	111	#endif
kadonotakashi	0:8fdf9a60065b	112
kadonotakashi	0:8fdf9a60065b	113	#endif
kadonotakashi	0:8fdf9a60065b	114
kadonotakashi	0:8fdf9a60065b	115	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
kadonotakashi	0:8fdf9a60065b	116
kadonotakashi	0:8fdf9a60065b	117
kadonotakashi	0:8fdf9a60065b	118	#ifdef __cplusplus
kadonotakashi	0:8fdf9a60065b	119	}
kadonotakashi	0:8fdf9a60065b	120	#endif
kadonotakashi	0:8fdf9a60065b	121
kadonotakashi	0:8fdf9a60065b	122	#endif /* __CORE_CM3_H_GENERIC */
kadonotakashi	0:8fdf9a60065b	123
kadonotakashi	0:8fdf9a60065b	124	#ifndef __CMSIS_GENERIC
kadonotakashi	0:8fdf9a60065b	125
kadonotakashi	0:8fdf9a60065b	126	#ifndef __CORE_CM3_H_DEPENDANT
kadonotakashi	0:8fdf9a60065b	127	#define __CORE_CM3_H_DEPENDANT
kadonotakashi	0:8fdf9a60065b	128
kadonotakashi	0:8fdf9a60065b	129	#ifdef __cplusplus
kadonotakashi	0:8fdf9a60065b	130	extern "C" {
kadonotakashi	0:8fdf9a60065b	131	#endif
kadonotakashi	0:8fdf9a60065b	132
kadonotakashi	0:8fdf9a60065b	133	/* check device defines and use defaults */
kadonotakashi	0:8fdf9a60065b	134	#if defined __CHECK_DEVICE_DEFINES
kadonotakashi	0:8fdf9a60065b	135	#ifndef __CM3_REV
kadonotakashi	0:8fdf9a60065b	136	#define __CM3_REV 0x0200U
kadonotakashi	0:8fdf9a60065b	137	#warning "__CM3_REV not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	138	#endif
kadonotakashi	0:8fdf9a60065b	139
kadonotakashi	0:8fdf9a60065b	140	#ifndef __MPU_PRESENT
kadonotakashi	0:8fdf9a60065b	141	#define __MPU_PRESENT 0U
kadonotakashi	0:8fdf9a60065b	142	#warning "__MPU_PRESENT not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	143	#endif
kadonotakashi	0:8fdf9a60065b	144
kadonotakashi	0:8fdf9a60065b	145	#ifndef __NVIC_PRIO_BITS
kadonotakashi	0:8fdf9a60065b	146	#define __NVIC_PRIO_BITS 3U
kadonotakashi	0:8fdf9a60065b	147	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	148	#endif
kadonotakashi	0:8fdf9a60065b	149
kadonotakashi	0:8fdf9a60065b	150	#ifndef __Vendor_SysTickConfig
kadonotakashi	0:8fdf9a60065b	151	#define __Vendor_SysTickConfig 0U
kadonotakashi	0:8fdf9a60065b	152	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
kadonotakashi	0:8fdf9a60065b	153	#endif
kadonotakashi	0:8fdf9a60065b	154	#endif
kadonotakashi	0:8fdf9a60065b	155
kadonotakashi	0:8fdf9a60065b	156	/* IO definitions (access restrictions to peripheral registers) */
kadonotakashi	0:8fdf9a60065b	157	/**
kadonotakashi	0:8fdf9a60065b	158	\defgroup CMSIS_glob_defs CMSIS Global Defines
kadonotakashi	0:8fdf9a60065b	159
kadonotakashi	0:8fdf9a60065b	160	<strong>IO Type Qualifiers</strong> are used
kadonotakashi	0:8fdf9a60065b	161	\li to specify the access to peripheral variables.
kadonotakashi	0:8fdf9a60065b	162	\li for automatic generation of peripheral register debug information.
kadonotakashi	0:8fdf9a60065b	163	*/
kadonotakashi	0:8fdf9a60065b	164	#ifdef __cplusplus
kadonotakashi	0:8fdf9a60065b	165	#define __I volatile /!< Defines 'read only' permissions /
kadonotakashi	0:8fdf9a60065b	166	#else
kadonotakashi	0:8fdf9a60065b	167	#define __I volatile const /!< Defines 'read only' permissions /
kadonotakashi	0:8fdf9a60065b	168	#endif
kadonotakashi	0:8fdf9a60065b	169	#define __O volatile /!< Defines 'write only' permissions /
kadonotakashi	0:8fdf9a60065b	170	#define __IO volatile /!< Defines 'read / write' permissions /
kadonotakashi	0:8fdf9a60065b	171
kadonotakashi	0:8fdf9a60065b	172	/* following defines should be used for structure members */
kadonotakashi	0:8fdf9a60065b	173	#define __IM volatile const /! Defines 'read only' structure member permissions /
kadonotakashi	0:8fdf9a60065b	174	#define __OM volatile /! Defines 'write only' structure member permissions /
kadonotakashi	0:8fdf9a60065b	175	#define __IOM volatile /! Defines 'read / write' structure member permissions /
kadonotakashi	0:8fdf9a60065b	176
kadonotakashi	0:8fdf9a60065b	177	/@} end of group Cortex_M3 /
kadonotakashi	0:8fdf9a60065b	178
kadonotakashi	0:8fdf9a60065b	179
kadonotakashi	0:8fdf9a60065b	180
kadonotakashi	0:8fdf9a60065b	181	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	182	* Register Abstraction
kadonotakashi	0:8fdf9a60065b	183	Core Register contain:
kadonotakashi	0:8fdf9a60065b	184	- Core Register
kadonotakashi	0:8fdf9a60065b	185	- Core NVIC Register
kadonotakashi	0:8fdf9a60065b	186	- Core SCB Register
kadonotakashi	0:8fdf9a60065b	187	- Core SysTick Register
kadonotakashi	0:8fdf9a60065b	188	- Core Debug Register
kadonotakashi	0:8fdf9a60065b	189	- Core MPU Register
kadonotakashi	0:8fdf9a60065b	190	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	191	/**
kadonotakashi	0:8fdf9a60065b	192	\defgroup CMSIS_core_register Defines and Type Definitions
kadonotakashi	0:8fdf9a60065b	193	\brief Type definitions and defines for Cortex-M processor based devices.
kadonotakashi	0:8fdf9a60065b	194	*/
kadonotakashi	0:8fdf9a60065b	195
kadonotakashi	0:8fdf9a60065b	196	/**
kadonotakashi	0:8fdf9a60065b	197	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	198	\defgroup CMSIS_CORE Status and Control Registers
kadonotakashi	0:8fdf9a60065b	199	\brief Core Register type definitions.
kadonotakashi	0:8fdf9a60065b	200	@{
kadonotakashi	0:8fdf9a60065b	201	*/
kadonotakashi	0:8fdf9a60065b	202
kadonotakashi	0:8fdf9a60065b	203	/**
kadonotakashi	0:8fdf9a60065b	204	\brief Union type to access the Application Program Status Register (APSR).
kadonotakashi	0:8fdf9a60065b	205	*/
kadonotakashi	0:8fdf9a60065b	206	typedef union
kadonotakashi	0:8fdf9a60065b	207	{
kadonotakashi	0:8fdf9a60065b	208	struct
kadonotakashi	0:8fdf9a60065b	209	{
kadonotakashi	0:8fdf9a60065b	210	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
kadonotakashi	0:8fdf9a60065b	211	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
kadonotakashi	0:8fdf9a60065b	212	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
kadonotakashi	0:8fdf9a60065b	213	uint32_t C:1; /!< bit: 29 Carry condition code flag /
kadonotakashi	0:8fdf9a60065b	214	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
kadonotakashi	0:8fdf9a60065b	215	uint32_t N:1; /!< bit: 31 Negative condition code flag /
kadonotakashi	0:8fdf9a60065b	216	} b; /!< Structure used for bit access /
kadonotakashi	0:8fdf9a60065b	217	uint32_t w; /!< Type used for word access /
kadonotakashi	0:8fdf9a60065b	218	} APSR_Type;
kadonotakashi	0:8fdf9a60065b	219
kadonotakashi	0:8fdf9a60065b	220	/* APSR Register Definitions */
kadonotakashi	0:8fdf9a60065b	221	#define APSR_N_Pos 31U /!< APSR: N Position /
kadonotakashi	0:8fdf9a60065b	222	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
kadonotakashi	0:8fdf9a60065b	223
kadonotakashi	0:8fdf9a60065b	224	#define APSR_Z_Pos 30U /!< APSR: Z Position /
kadonotakashi	0:8fdf9a60065b	225	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
kadonotakashi	0:8fdf9a60065b	226
kadonotakashi	0:8fdf9a60065b	227	#define APSR_C_Pos 29U /!< APSR: C Position /
kadonotakashi	0:8fdf9a60065b	228	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
kadonotakashi	0:8fdf9a60065b	229
kadonotakashi	0:8fdf9a60065b	230	#define APSR_V_Pos 28U /!< APSR: V Position /
kadonotakashi	0:8fdf9a60065b	231	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
kadonotakashi	0:8fdf9a60065b	232
kadonotakashi	0:8fdf9a60065b	233	#define APSR_Q_Pos 27U /!< APSR: Q Position /
kadonotakashi	0:8fdf9a60065b	234	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
kadonotakashi	0:8fdf9a60065b	235
kadonotakashi	0:8fdf9a60065b	236
kadonotakashi	0:8fdf9a60065b	237	/**
kadonotakashi	0:8fdf9a60065b	238	\brief Union type to access the Interrupt Program Status Register (IPSR).
kadonotakashi	0:8fdf9a60065b	239	*/
kadonotakashi	0:8fdf9a60065b	240	typedef union
kadonotakashi	0:8fdf9a60065b	241	{
kadonotakashi	0:8fdf9a60065b	242	struct
kadonotakashi	0:8fdf9a60065b	243	{
kadonotakashi	0:8fdf9a60065b	244	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
kadonotakashi	0:8fdf9a60065b	245	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
kadonotakashi	0:8fdf9a60065b	246	} b; /!< Structure used for bit access /
kadonotakashi	0:8fdf9a60065b	247	uint32_t w; /!< Type used for word access /
kadonotakashi	0:8fdf9a60065b	248	} IPSR_Type;
kadonotakashi	0:8fdf9a60065b	249
kadonotakashi	0:8fdf9a60065b	250	/* IPSR Register Definitions */
kadonotakashi	0:8fdf9a60065b	251	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
kadonotakashi	0:8fdf9a60065b	252	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
kadonotakashi	0:8fdf9a60065b	253
kadonotakashi	0:8fdf9a60065b	254
kadonotakashi	0:8fdf9a60065b	255	/**
kadonotakashi	0:8fdf9a60065b	256	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
kadonotakashi	0:8fdf9a60065b	257	*/
kadonotakashi	0:8fdf9a60065b	258	typedef union
kadonotakashi	0:8fdf9a60065b	259	{
kadonotakashi	0:8fdf9a60065b	260	struct
kadonotakashi	0:8fdf9a60065b	261	{
kadonotakashi	0:8fdf9a60065b	262	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
kadonotakashi	0:8fdf9a60065b	263	uint32_t _reserved0:1; /!< bit: 9 Reserved /
kadonotakashi	0:8fdf9a60065b	264	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
kadonotakashi	0:8fdf9a60065b	265	uint32_t _reserved1:8; /!< bit: 16..23 Reserved /
kadonotakashi	0:8fdf9a60065b	266	uint32_t T:1; /!< bit: 24 Thumb bit /
kadonotakashi	0:8fdf9a60065b	267	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
kadonotakashi	0:8fdf9a60065b	268	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
kadonotakashi	0:8fdf9a60065b	269	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
kadonotakashi	0:8fdf9a60065b	270	uint32_t C:1; /!< bit: 29 Carry condition code flag /
kadonotakashi	0:8fdf9a60065b	271	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
kadonotakashi	0:8fdf9a60065b	272	uint32_t N:1; /!< bit: 31 Negative condition code flag /
kadonotakashi	0:8fdf9a60065b	273	} b; /!< Structure used for bit access /
kadonotakashi	0:8fdf9a60065b	274	uint32_t w; /!< Type used for word access /
kadonotakashi	0:8fdf9a60065b	275	} xPSR_Type;
kadonotakashi	0:8fdf9a60065b	276
kadonotakashi	0:8fdf9a60065b	277	/* xPSR Register Definitions */
kadonotakashi	0:8fdf9a60065b	278	#define xPSR_N_Pos 31U /!< xPSR: N Position /
kadonotakashi	0:8fdf9a60065b	279	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
kadonotakashi	0:8fdf9a60065b	280
kadonotakashi	0:8fdf9a60065b	281	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
kadonotakashi	0:8fdf9a60065b	282	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
kadonotakashi	0:8fdf9a60065b	283
kadonotakashi	0:8fdf9a60065b	284	#define xPSR_C_Pos 29U /!< xPSR: C Position /
kadonotakashi	0:8fdf9a60065b	285	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
kadonotakashi	0:8fdf9a60065b	286
kadonotakashi	0:8fdf9a60065b	287	#define xPSR_V_Pos 28U /!< xPSR: V Position /
kadonotakashi	0:8fdf9a60065b	288	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
kadonotakashi	0:8fdf9a60065b	289
kadonotakashi	0:8fdf9a60065b	290	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
kadonotakashi	0:8fdf9a60065b	291	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
kadonotakashi	0:8fdf9a60065b	292
kadonotakashi	0:8fdf9a60065b	293	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
kadonotakashi	0:8fdf9a60065b	294	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
kadonotakashi	0:8fdf9a60065b	295
kadonotakashi	0:8fdf9a60065b	296	#define xPSR_T_Pos 24U /!< xPSR: T Position /
kadonotakashi	0:8fdf9a60065b	297	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
kadonotakashi	0:8fdf9a60065b	298
kadonotakashi	0:8fdf9a60065b	299	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
kadonotakashi	0:8fdf9a60065b	300	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
kadonotakashi	0:8fdf9a60065b	301
kadonotakashi	0:8fdf9a60065b	302	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
kadonotakashi	0:8fdf9a60065b	303	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
kadonotakashi	0:8fdf9a60065b	304
kadonotakashi	0:8fdf9a60065b	305
kadonotakashi	0:8fdf9a60065b	306	/**
kadonotakashi	0:8fdf9a60065b	307	\brief Union type to access the Control Registers (CONTROL).
kadonotakashi	0:8fdf9a60065b	308	*/
kadonotakashi	0:8fdf9a60065b	309	typedef union
kadonotakashi	0:8fdf9a60065b	310	{
kadonotakashi	0:8fdf9a60065b	311	struct
kadonotakashi	0:8fdf9a60065b	312	{
kadonotakashi	0:8fdf9a60065b	313	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
kadonotakashi	0:8fdf9a60065b	314	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
kadonotakashi	0:8fdf9a60065b	315	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
kadonotakashi	0:8fdf9a60065b	316	} b; /!< Structure used for bit access /
kadonotakashi	0:8fdf9a60065b	317	uint32_t w; /!< Type used for word access /
kadonotakashi	0:8fdf9a60065b	318	} CONTROL_Type;
kadonotakashi	0:8fdf9a60065b	319
kadonotakashi	0:8fdf9a60065b	320	/* CONTROL Register Definitions */
kadonotakashi	0:8fdf9a60065b	321	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
kadonotakashi	0:8fdf9a60065b	322	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
kadonotakashi	0:8fdf9a60065b	323
kadonotakashi	0:8fdf9a60065b	324	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
kadonotakashi	0:8fdf9a60065b	325	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
kadonotakashi	0:8fdf9a60065b	326
kadonotakashi	0:8fdf9a60065b	327	/@} end of group CMSIS_CORE /
kadonotakashi	0:8fdf9a60065b	328
kadonotakashi	0:8fdf9a60065b	329
kadonotakashi	0:8fdf9a60065b	330	/**
kadonotakashi	0:8fdf9a60065b	331	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	332	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
kadonotakashi	0:8fdf9a60065b	333	\brief Type definitions for the NVIC Registers
kadonotakashi	0:8fdf9a60065b	334	@{
kadonotakashi	0:8fdf9a60065b	335	*/
kadonotakashi	0:8fdf9a60065b	336
kadonotakashi	0:8fdf9a60065b	337	/**
kadonotakashi	0:8fdf9a60065b	338	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
kadonotakashi	0:8fdf9a60065b	339	*/
kadonotakashi	0:8fdf9a60065b	340	typedef struct
kadonotakashi	0:8fdf9a60065b	341	{
kadonotakashi	0:8fdf9a60065b	342	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
kadonotakashi	0:8fdf9a60065b	343	uint32_t RESERVED0[24U];
kadonotakashi	0:8fdf9a60065b	344	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
kadonotakashi	0:8fdf9a60065b	345	uint32_t RSERVED1[24U];
kadonotakashi	0:8fdf9a60065b	346	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
kadonotakashi	0:8fdf9a60065b	347	uint32_t RESERVED2[24U];
kadonotakashi	0:8fdf9a60065b	348	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
kadonotakashi	0:8fdf9a60065b	349	uint32_t RESERVED3[24U];
kadonotakashi	0:8fdf9a60065b	350	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
kadonotakashi	0:8fdf9a60065b	351	uint32_t RESERVED4[56U];
kadonotakashi	0:8fdf9a60065b	352	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
kadonotakashi	0:8fdf9a60065b	353	uint32_t RESERVED5[644U];
kadonotakashi	0:8fdf9a60065b	354	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
kadonotakashi	0:8fdf9a60065b	355	} NVIC_Type;
kadonotakashi	0:8fdf9a60065b	356
kadonotakashi	0:8fdf9a60065b	357	/* Software Triggered Interrupt Register Definitions */
kadonotakashi	0:8fdf9a60065b	358	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
kadonotakashi	0:8fdf9a60065b	359	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
kadonotakashi	0:8fdf9a60065b	360
kadonotakashi	0:8fdf9a60065b	361	/@} end of group CMSIS_NVIC /
kadonotakashi	0:8fdf9a60065b	362
kadonotakashi	0:8fdf9a60065b	363
kadonotakashi	0:8fdf9a60065b	364	/**
kadonotakashi	0:8fdf9a60065b	365	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	366	\defgroup CMSIS_SCB System Control Block (SCB)
kadonotakashi	0:8fdf9a60065b	367	\brief Type definitions for the System Control Block Registers
kadonotakashi	0:8fdf9a60065b	368	@{
kadonotakashi	0:8fdf9a60065b	369	*/
kadonotakashi	0:8fdf9a60065b	370
kadonotakashi	0:8fdf9a60065b	371	/**
kadonotakashi	0:8fdf9a60065b	372	\brief Structure type to access the System Control Block (SCB).
kadonotakashi	0:8fdf9a60065b	373	*/
kadonotakashi	0:8fdf9a60065b	374	typedef struct
kadonotakashi	0:8fdf9a60065b	375	{
kadonotakashi	0:8fdf9a60065b	376	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
kadonotakashi	0:8fdf9a60065b	377	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
kadonotakashi	0:8fdf9a60065b	378	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
kadonotakashi	0:8fdf9a60065b	379	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
kadonotakashi	0:8fdf9a60065b	380	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
kadonotakashi	0:8fdf9a60065b	381	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
kadonotakashi	0:8fdf9a60065b	382	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
kadonotakashi	0:8fdf9a60065b	383	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
kadonotakashi	0:8fdf9a60065b	384	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
kadonotakashi	0:8fdf9a60065b	385	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
kadonotakashi	0:8fdf9a60065b	386	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
kadonotakashi	0:8fdf9a60065b	387	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
kadonotakashi	0:8fdf9a60065b	388	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
kadonotakashi	0:8fdf9a60065b	389	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
kadonotakashi	0:8fdf9a60065b	390	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
kadonotakashi	0:8fdf9a60065b	391	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
kadonotakashi	0:8fdf9a60065b	392	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
kadonotakashi	0:8fdf9a60065b	393	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
kadonotakashi	0:8fdf9a60065b	394	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
kadonotakashi	0:8fdf9a60065b	395	uint32_t RESERVED0[5U];
kadonotakashi	0:8fdf9a60065b	396	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
kadonotakashi	0:8fdf9a60065b	397	} SCB_Type;
kadonotakashi	0:8fdf9a60065b	398
kadonotakashi	0:8fdf9a60065b	399	/* SCB CPUID Register Definitions */
kadonotakashi	0:8fdf9a60065b	400	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
kadonotakashi	0:8fdf9a60065b	401	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
kadonotakashi	0:8fdf9a60065b	402
kadonotakashi	0:8fdf9a60065b	403	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
kadonotakashi	0:8fdf9a60065b	404	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
kadonotakashi	0:8fdf9a60065b	405
kadonotakashi	0:8fdf9a60065b	406	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
kadonotakashi	0:8fdf9a60065b	407	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
kadonotakashi	0:8fdf9a60065b	408
kadonotakashi	0:8fdf9a60065b	409	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
kadonotakashi	0:8fdf9a60065b	410	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
kadonotakashi	0:8fdf9a60065b	411
kadonotakashi	0:8fdf9a60065b	412	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
kadonotakashi	0:8fdf9a60065b	413	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
kadonotakashi	0:8fdf9a60065b	414
kadonotakashi	0:8fdf9a60065b	415	/* SCB Interrupt Control State Register Definitions */
kadonotakashi	0:8fdf9a60065b	416	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
kadonotakashi	0:8fdf9a60065b	417	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
kadonotakashi	0:8fdf9a60065b	418
kadonotakashi	0:8fdf9a60065b	419	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
kadonotakashi	0:8fdf9a60065b	420	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
kadonotakashi	0:8fdf9a60065b	421
kadonotakashi	0:8fdf9a60065b	422	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
kadonotakashi	0:8fdf9a60065b	423	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
kadonotakashi	0:8fdf9a60065b	424
kadonotakashi	0:8fdf9a60065b	425	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
kadonotakashi	0:8fdf9a60065b	426	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
kadonotakashi	0:8fdf9a60065b	427
kadonotakashi	0:8fdf9a60065b	428	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
kadonotakashi	0:8fdf9a60065b	429	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
kadonotakashi	0:8fdf9a60065b	430
kadonotakashi	0:8fdf9a60065b	431	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
kadonotakashi	0:8fdf9a60065b	432	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
kadonotakashi	0:8fdf9a60065b	433
kadonotakashi	0:8fdf9a60065b	434	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
kadonotakashi	0:8fdf9a60065b	435	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
kadonotakashi	0:8fdf9a60065b	436
kadonotakashi	0:8fdf9a60065b	437	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
kadonotakashi	0:8fdf9a60065b	438	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
kadonotakashi	0:8fdf9a60065b	439
kadonotakashi	0:8fdf9a60065b	440	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
kadonotakashi	0:8fdf9a60065b	441	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
kadonotakashi	0:8fdf9a60065b	442
kadonotakashi	0:8fdf9a60065b	443	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
kadonotakashi	0:8fdf9a60065b	444	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
kadonotakashi	0:8fdf9a60065b	445
kadonotakashi	0:8fdf9a60065b	446	/* SCB Vector Table Offset Register Definitions */
kadonotakashi	0:8fdf9a60065b	447	#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
kadonotakashi	0:8fdf9a60065b	448	#define SCB_VTOR_TBLBASE_Pos 29U /!< SCB VTOR: TBLBASE Position /
kadonotakashi	0:8fdf9a60065b	449	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
kadonotakashi	0:8fdf9a60065b	450
kadonotakashi	0:8fdf9a60065b	451	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
kadonotakashi	0:8fdf9a60065b	452	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
kadonotakashi	0:8fdf9a60065b	453	#else
kadonotakashi	0:8fdf9a60065b	454	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
kadonotakashi	0:8fdf9a60065b	455	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
kadonotakashi	0:8fdf9a60065b	456	#endif
kadonotakashi	0:8fdf9a60065b	457
kadonotakashi	0:8fdf9a60065b	458	/* SCB Application Interrupt and Reset Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	459	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
kadonotakashi	0:8fdf9a60065b	460	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
kadonotakashi	0:8fdf9a60065b	461
kadonotakashi	0:8fdf9a60065b	462	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
kadonotakashi	0:8fdf9a60065b	463	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
kadonotakashi	0:8fdf9a60065b	464
kadonotakashi	0:8fdf9a60065b	465	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
kadonotakashi	0:8fdf9a60065b	466	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
kadonotakashi	0:8fdf9a60065b	467
kadonotakashi	0:8fdf9a60065b	468	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
kadonotakashi	0:8fdf9a60065b	469	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
kadonotakashi	0:8fdf9a60065b	470
kadonotakashi	0:8fdf9a60065b	471	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
kadonotakashi	0:8fdf9a60065b	472	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
kadonotakashi	0:8fdf9a60065b	473
kadonotakashi	0:8fdf9a60065b	474	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
kadonotakashi	0:8fdf9a60065b	475	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
kadonotakashi	0:8fdf9a60065b	476
kadonotakashi	0:8fdf9a60065b	477	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
kadonotakashi	0:8fdf9a60065b	478	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
kadonotakashi	0:8fdf9a60065b	479
kadonotakashi	0:8fdf9a60065b	480	/* SCB System Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	481	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
kadonotakashi	0:8fdf9a60065b	482	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
kadonotakashi	0:8fdf9a60065b	483
kadonotakashi	0:8fdf9a60065b	484	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
kadonotakashi	0:8fdf9a60065b	485	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
kadonotakashi	0:8fdf9a60065b	486
kadonotakashi	0:8fdf9a60065b	487	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
kadonotakashi	0:8fdf9a60065b	488	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
kadonotakashi	0:8fdf9a60065b	489
kadonotakashi	0:8fdf9a60065b	490	/* SCB Configuration Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	491	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
kadonotakashi	0:8fdf9a60065b	492	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
kadonotakashi	0:8fdf9a60065b	493
kadonotakashi	0:8fdf9a60065b	494	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
kadonotakashi	0:8fdf9a60065b	495	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
kadonotakashi	0:8fdf9a60065b	496
kadonotakashi	0:8fdf9a60065b	497	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
kadonotakashi	0:8fdf9a60065b	498	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
kadonotakashi	0:8fdf9a60065b	499
kadonotakashi	0:8fdf9a60065b	500	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
kadonotakashi	0:8fdf9a60065b	501	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
kadonotakashi	0:8fdf9a60065b	502
kadonotakashi	0:8fdf9a60065b	503	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
kadonotakashi	0:8fdf9a60065b	504	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
kadonotakashi	0:8fdf9a60065b	505
kadonotakashi	0:8fdf9a60065b	506	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
kadonotakashi	0:8fdf9a60065b	507	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
kadonotakashi	0:8fdf9a60065b	508
kadonotakashi	0:8fdf9a60065b	509	/* SCB System Handler Control and State Register Definitions */
kadonotakashi	0:8fdf9a60065b	510	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
kadonotakashi	0:8fdf9a60065b	511	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
kadonotakashi	0:8fdf9a60065b	512
kadonotakashi	0:8fdf9a60065b	513	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
kadonotakashi	0:8fdf9a60065b	514	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
kadonotakashi	0:8fdf9a60065b	515
kadonotakashi	0:8fdf9a60065b	516	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
kadonotakashi	0:8fdf9a60065b	517	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
kadonotakashi	0:8fdf9a60065b	518
kadonotakashi	0:8fdf9a60065b	519	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
kadonotakashi	0:8fdf9a60065b	520	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
kadonotakashi	0:8fdf9a60065b	521
kadonotakashi	0:8fdf9a60065b	522	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
kadonotakashi	0:8fdf9a60065b	523	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
kadonotakashi	0:8fdf9a60065b	524
kadonotakashi	0:8fdf9a60065b	525	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
kadonotakashi	0:8fdf9a60065b	526	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
kadonotakashi	0:8fdf9a60065b	527
kadonotakashi	0:8fdf9a60065b	528	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
kadonotakashi	0:8fdf9a60065b	529	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
kadonotakashi	0:8fdf9a60065b	530
kadonotakashi	0:8fdf9a60065b	531	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
kadonotakashi	0:8fdf9a60065b	532	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
kadonotakashi	0:8fdf9a60065b	533
kadonotakashi	0:8fdf9a60065b	534	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
kadonotakashi	0:8fdf9a60065b	535	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
kadonotakashi	0:8fdf9a60065b	536
kadonotakashi	0:8fdf9a60065b	537	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
kadonotakashi	0:8fdf9a60065b	538	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
kadonotakashi	0:8fdf9a60065b	539
kadonotakashi	0:8fdf9a60065b	540	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
kadonotakashi	0:8fdf9a60065b	541	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
kadonotakashi	0:8fdf9a60065b	542
kadonotakashi	0:8fdf9a60065b	543	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
kadonotakashi	0:8fdf9a60065b	544	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
kadonotakashi	0:8fdf9a60065b	545
kadonotakashi	0:8fdf9a60065b	546	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
kadonotakashi	0:8fdf9a60065b	547	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
kadonotakashi	0:8fdf9a60065b	548
kadonotakashi	0:8fdf9a60065b	549	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
kadonotakashi	0:8fdf9a60065b	550	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
kadonotakashi	0:8fdf9a60065b	551
kadonotakashi	0:8fdf9a60065b	552	/* SCB Configurable Fault Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	553	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
kadonotakashi	0:8fdf9a60065b	554	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
kadonotakashi	0:8fdf9a60065b	555
kadonotakashi	0:8fdf9a60065b	556	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
kadonotakashi	0:8fdf9a60065b	557	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
kadonotakashi	0:8fdf9a60065b	558
kadonotakashi	0:8fdf9a60065b	559	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
kadonotakashi	0:8fdf9a60065b	560	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
kadonotakashi	0:8fdf9a60065b	561
kadonotakashi	0:8fdf9a60065b	562	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
kadonotakashi	0:8fdf9a60065b	563	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
kadonotakashi	0:8fdf9a60065b	564	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
kadonotakashi	0:8fdf9a60065b	565
kadonotakashi	0:8fdf9a60065b	566	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
kadonotakashi	0:8fdf9a60065b	567	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
kadonotakashi	0:8fdf9a60065b	568
kadonotakashi	0:8fdf9a60065b	569	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
kadonotakashi	0:8fdf9a60065b	570	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
kadonotakashi	0:8fdf9a60065b	571
kadonotakashi	0:8fdf9a60065b	572	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
kadonotakashi	0:8fdf9a60065b	573	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
kadonotakashi	0:8fdf9a60065b	574
kadonotakashi	0:8fdf9a60065b	575	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
kadonotakashi	0:8fdf9a60065b	576	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
kadonotakashi	0:8fdf9a60065b	577
kadonotakashi	0:8fdf9a60065b	578	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
kadonotakashi	0:8fdf9a60065b	579	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
kadonotakashi	0:8fdf9a60065b	580	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
kadonotakashi	0:8fdf9a60065b	581
kadonotakashi	0:8fdf9a60065b	582	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
kadonotakashi	0:8fdf9a60065b	583	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
kadonotakashi	0:8fdf9a60065b	584
kadonotakashi	0:8fdf9a60065b	585	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
kadonotakashi	0:8fdf9a60065b	586	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
kadonotakashi	0:8fdf9a60065b	587
kadonotakashi	0:8fdf9a60065b	588	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
kadonotakashi	0:8fdf9a60065b	589	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
kadonotakashi	0:8fdf9a60065b	590
kadonotakashi	0:8fdf9a60065b	591	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
kadonotakashi	0:8fdf9a60065b	592	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
kadonotakashi	0:8fdf9a60065b	593
kadonotakashi	0:8fdf9a60065b	594	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
kadonotakashi	0:8fdf9a60065b	595	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
kadonotakashi	0:8fdf9a60065b	596
kadonotakashi	0:8fdf9a60065b	597	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
kadonotakashi	0:8fdf9a60065b	598	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
kadonotakashi	0:8fdf9a60065b	599	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
kadonotakashi	0:8fdf9a60065b	600
kadonotakashi	0:8fdf9a60065b	601	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
kadonotakashi	0:8fdf9a60065b	602	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
kadonotakashi	0:8fdf9a60065b	603
kadonotakashi	0:8fdf9a60065b	604	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
kadonotakashi	0:8fdf9a60065b	605	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
kadonotakashi	0:8fdf9a60065b	606
kadonotakashi	0:8fdf9a60065b	607	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
kadonotakashi	0:8fdf9a60065b	608	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
kadonotakashi	0:8fdf9a60065b	609
kadonotakashi	0:8fdf9a60065b	610	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
kadonotakashi	0:8fdf9a60065b	611	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
kadonotakashi	0:8fdf9a60065b	612
kadonotakashi	0:8fdf9a60065b	613	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
kadonotakashi	0:8fdf9a60065b	614	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
kadonotakashi	0:8fdf9a60065b	615
kadonotakashi	0:8fdf9a60065b	616	/* SCB Hard Fault Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	617	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
kadonotakashi	0:8fdf9a60065b	618	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
kadonotakashi	0:8fdf9a60065b	619
kadonotakashi	0:8fdf9a60065b	620	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
kadonotakashi	0:8fdf9a60065b	621	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
kadonotakashi	0:8fdf9a60065b	622
kadonotakashi	0:8fdf9a60065b	623	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
kadonotakashi	0:8fdf9a60065b	624	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
kadonotakashi	0:8fdf9a60065b	625
kadonotakashi	0:8fdf9a60065b	626	/* SCB Debug Fault Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	627	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
kadonotakashi	0:8fdf9a60065b	628	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
kadonotakashi	0:8fdf9a60065b	629
kadonotakashi	0:8fdf9a60065b	630	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
kadonotakashi	0:8fdf9a60065b	631	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
kadonotakashi	0:8fdf9a60065b	632
kadonotakashi	0:8fdf9a60065b	633	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
kadonotakashi	0:8fdf9a60065b	634	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
kadonotakashi	0:8fdf9a60065b	635
kadonotakashi	0:8fdf9a60065b	636	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
kadonotakashi	0:8fdf9a60065b	637	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
kadonotakashi	0:8fdf9a60065b	638
kadonotakashi	0:8fdf9a60065b	639	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
kadonotakashi	0:8fdf9a60065b	640	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
kadonotakashi	0:8fdf9a60065b	641
kadonotakashi	0:8fdf9a60065b	642	/@} end of group CMSIS_SCB /
kadonotakashi	0:8fdf9a60065b	643
kadonotakashi	0:8fdf9a60065b	644
kadonotakashi	0:8fdf9a60065b	645	/**
kadonotakashi	0:8fdf9a60065b	646	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	647	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
kadonotakashi	0:8fdf9a60065b	648	\brief Type definitions for the System Control and ID Register not in the SCB
kadonotakashi	0:8fdf9a60065b	649	@{
kadonotakashi	0:8fdf9a60065b	650	*/
kadonotakashi	0:8fdf9a60065b	651
kadonotakashi	0:8fdf9a60065b	652	/**
kadonotakashi	0:8fdf9a60065b	653	\brief Structure type to access the System Control and ID Register not in the SCB.
kadonotakashi	0:8fdf9a60065b	654	*/
kadonotakashi	0:8fdf9a60065b	655	typedef struct
kadonotakashi	0:8fdf9a60065b	656	{
kadonotakashi	0:8fdf9a60065b	657	uint32_t RESERVED0[1U];
kadonotakashi	0:8fdf9a60065b	658	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
kadonotakashi	0:8fdf9a60065b	659	#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
kadonotakashi	0:8fdf9a60065b	660	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
kadonotakashi	0:8fdf9a60065b	661	#else
kadonotakashi	0:8fdf9a60065b	662	uint32_t RESERVED1[1U];
kadonotakashi	0:8fdf9a60065b	663	#endif
kadonotakashi	0:8fdf9a60065b	664	} SCnSCB_Type;
kadonotakashi	0:8fdf9a60065b	665
kadonotakashi	0:8fdf9a60065b	666	/* Interrupt Controller Type Register Definitions */
kadonotakashi	0:8fdf9a60065b	667	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
kadonotakashi	0:8fdf9a60065b	668	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
kadonotakashi	0:8fdf9a60065b	669
kadonotakashi	0:8fdf9a60065b	670	/* Auxiliary Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	671
kadonotakashi	0:8fdf9a60065b	672	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
kadonotakashi	0:8fdf9a60065b	673	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
kadonotakashi	0:8fdf9a60065b	674
kadonotakashi	0:8fdf9a60065b	675	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /!< ACTLR: DISDEFWBUF Position /
kadonotakashi	0:8fdf9a60065b	676	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
kadonotakashi	0:8fdf9a60065b	677
kadonotakashi	0:8fdf9a60065b	678	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
kadonotakashi	0:8fdf9a60065b	679	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
kadonotakashi	0:8fdf9a60065b	680
kadonotakashi	0:8fdf9a60065b	681	/@} end of group CMSIS_SCnotSCB /
kadonotakashi	0:8fdf9a60065b	682
kadonotakashi	0:8fdf9a60065b	683
kadonotakashi	0:8fdf9a60065b	684	/**
kadonotakashi	0:8fdf9a60065b	685	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	686	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
kadonotakashi	0:8fdf9a60065b	687	\brief Type definitions for the System Timer Registers.
kadonotakashi	0:8fdf9a60065b	688	@{
kadonotakashi	0:8fdf9a60065b	689	*/
kadonotakashi	0:8fdf9a60065b	690
kadonotakashi	0:8fdf9a60065b	691	/**
kadonotakashi	0:8fdf9a60065b	692	\brief Structure type to access the System Timer (SysTick).
kadonotakashi	0:8fdf9a60065b	693	*/
kadonotakashi	0:8fdf9a60065b	694	typedef struct
kadonotakashi	0:8fdf9a60065b	695	{
kadonotakashi	0:8fdf9a60065b	696	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
kadonotakashi	0:8fdf9a60065b	697	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
kadonotakashi	0:8fdf9a60065b	698	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
kadonotakashi	0:8fdf9a60065b	699	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
kadonotakashi	0:8fdf9a60065b	700	} SysTick_Type;
kadonotakashi	0:8fdf9a60065b	701
kadonotakashi	0:8fdf9a60065b	702	/* SysTick Control / Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	703	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
kadonotakashi	0:8fdf9a60065b	704	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
kadonotakashi	0:8fdf9a60065b	705
kadonotakashi	0:8fdf9a60065b	706	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
kadonotakashi	0:8fdf9a60065b	707	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
kadonotakashi	0:8fdf9a60065b	708
kadonotakashi	0:8fdf9a60065b	709	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
kadonotakashi	0:8fdf9a60065b	710	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
kadonotakashi	0:8fdf9a60065b	711
kadonotakashi	0:8fdf9a60065b	712	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
kadonotakashi	0:8fdf9a60065b	713	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
kadonotakashi	0:8fdf9a60065b	714
kadonotakashi	0:8fdf9a60065b	715	/* SysTick Reload Register Definitions */
kadonotakashi	0:8fdf9a60065b	716	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
kadonotakashi	0:8fdf9a60065b	717	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
kadonotakashi	0:8fdf9a60065b	718
kadonotakashi	0:8fdf9a60065b	719	/* SysTick Current Register Definitions */
kadonotakashi	0:8fdf9a60065b	720	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
kadonotakashi	0:8fdf9a60065b	721	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
kadonotakashi	0:8fdf9a60065b	722
kadonotakashi	0:8fdf9a60065b	723	/* SysTick Calibration Register Definitions */
kadonotakashi	0:8fdf9a60065b	724	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
kadonotakashi	0:8fdf9a60065b	725	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
kadonotakashi	0:8fdf9a60065b	726
kadonotakashi	0:8fdf9a60065b	727	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
kadonotakashi	0:8fdf9a60065b	728	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
kadonotakashi	0:8fdf9a60065b	729
kadonotakashi	0:8fdf9a60065b	730	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
kadonotakashi	0:8fdf9a60065b	731	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
kadonotakashi	0:8fdf9a60065b	732
kadonotakashi	0:8fdf9a60065b	733	/@} end of group CMSIS_SysTick /
kadonotakashi	0:8fdf9a60065b	734
kadonotakashi	0:8fdf9a60065b	735
kadonotakashi	0:8fdf9a60065b	736	/**
kadonotakashi	0:8fdf9a60065b	737	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	738	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
kadonotakashi	0:8fdf9a60065b	739	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
kadonotakashi	0:8fdf9a60065b	740	@{
kadonotakashi	0:8fdf9a60065b	741	*/
kadonotakashi	0:8fdf9a60065b	742
kadonotakashi	0:8fdf9a60065b	743	/**
kadonotakashi	0:8fdf9a60065b	744	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
kadonotakashi	0:8fdf9a60065b	745	*/
kadonotakashi	0:8fdf9a60065b	746	typedef struct
kadonotakashi	0:8fdf9a60065b	747	{
kadonotakashi	0:8fdf9a60065b	748	__OM union
kadonotakashi	0:8fdf9a60065b	749	{
kadonotakashi	0:8fdf9a60065b	750	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
kadonotakashi	0:8fdf9a60065b	751	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
kadonotakashi	0:8fdf9a60065b	752	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
kadonotakashi	0:8fdf9a60065b	753	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
kadonotakashi	0:8fdf9a60065b	754	uint32_t RESERVED0[864U];
kadonotakashi	0:8fdf9a60065b	755	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
kadonotakashi	0:8fdf9a60065b	756	uint32_t RESERVED1[15U];
kadonotakashi	0:8fdf9a60065b	757	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
kadonotakashi	0:8fdf9a60065b	758	uint32_t RESERVED2[15U];
kadonotakashi	0:8fdf9a60065b	759	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
kadonotakashi	0:8fdf9a60065b	760	uint32_t RESERVED3[29U];
kadonotakashi	0:8fdf9a60065b	761	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
kadonotakashi	0:8fdf9a60065b	762	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
kadonotakashi	0:8fdf9a60065b	763	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
kadonotakashi	0:8fdf9a60065b	764	uint32_t RESERVED4[43U];
kadonotakashi	0:8fdf9a60065b	765	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
kadonotakashi	0:8fdf9a60065b	766	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
kadonotakashi	0:8fdf9a60065b	767	uint32_t RESERVED5[6U];
kadonotakashi	0:8fdf9a60065b	768	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
kadonotakashi	0:8fdf9a60065b	769	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
kadonotakashi	0:8fdf9a60065b	770	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
kadonotakashi	0:8fdf9a60065b	771	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
kadonotakashi	0:8fdf9a60065b	772	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
kadonotakashi	0:8fdf9a60065b	773	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
kadonotakashi	0:8fdf9a60065b	774	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
kadonotakashi	0:8fdf9a60065b	775	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
kadonotakashi	0:8fdf9a60065b	776	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
kadonotakashi	0:8fdf9a60065b	777	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
kadonotakashi	0:8fdf9a60065b	778	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
kadonotakashi	0:8fdf9a60065b	779	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
kadonotakashi	0:8fdf9a60065b	780	} ITM_Type;
kadonotakashi	0:8fdf9a60065b	781
kadonotakashi	0:8fdf9a60065b	782	/* ITM Trace Privilege Register Definitions */
kadonotakashi	0:8fdf9a60065b	783	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
kadonotakashi	0:8fdf9a60065b	784	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
kadonotakashi	0:8fdf9a60065b	785
kadonotakashi	0:8fdf9a60065b	786	/* ITM Trace Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	787	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
kadonotakashi	0:8fdf9a60065b	788	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
kadonotakashi	0:8fdf9a60065b	789
kadonotakashi	0:8fdf9a60065b	790	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
kadonotakashi	0:8fdf9a60065b	791	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
kadonotakashi	0:8fdf9a60065b	792
kadonotakashi	0:8fdf9a60065b	793	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
kadonotakashi	0:8fdf9a60065b	794	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
kadonotakashi	0:8fdf9a60065b	795
kadonotakashi	0:8fdf9a60065b	796	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
kadonotakashi	0:8fdf9a60065b	797	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
kadonotakashi	0:8fdf9a60065b	798
kadonotakashi	0:8fdf9a60065b	799	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
kadonotakashi	0:8fdf9a60065b	800	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
kadonotakashi	0:8fdf9a60065b	801
kadonotakashi	0:8fdf9a60065b	802	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
kadonotakashi	0:8fdf9a60065b	803	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
kadonotakashi	0:8fdf9a60065b	804
kadonotakashi	0:8fdf9a60065b	805	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
kadonotakashi	0:8fdf9a60065b	806	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
kadonotakashi	0:8fdf9a60065b	807
kadonotakashi	0:8fdf9a60065b	808	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
kadonotakashi	0:8fdf9a60065b	809	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
kadonotakashi	0:8fdf9a60065b	810
kadonotakashi	0:8fdf9a60065b	811	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
kadonotakashi	0:8fdf9a60065b	812	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
kadonotakashi	0:8fdf9a60065b	813
kadonotakashi	0:8fdf9a60065b	814	/* ITM Integration Write Register Definitions */
kadonotakashi	0:8fdf9a60065b	815	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
kadonotakashi	0:8fdf9a60065b	816	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
kadonotakashi	0:8fdf9a60065b	817
kadonotakashi	0:8fdf9a60065b	818	/* ITM Integration Read Register Definitions */
kadonotakashi	0:8fdf9a60065b	819	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
kadonotakashi	0:8fdf9a60065b	820	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
kadonotakashi	0:8fdf9a60065b	821
kadonotakashi	0:8fdf9a60065b	822	/* ITM Integration Mode Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	823	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
kadonotakashi	0:8fdf9a60065b	824	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
kadonotakashi	0:8fdf9a60065b	825
kadonotakashi	0:8fdf9a60065b	826	/* ITM Lock Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	827	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
kadonotakashi	0:8fdf9a60065b	828	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
kadonotakashi	0:8fdf9a60065b	829
kadonotakashi	0:8fdf9a60065b	830	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
kadonotakashi	0:8fdf9a60065b	831	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
kadonotakashi	0:8fdf9a60065b	832
kadonotakashi	0:8fdf9a60065b	833	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
kadonotakashi	0:8fdf9a60065b	834	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
kadonotakashi	0:8fdf9a60065b	835
kadonotakashi	0:8fdf9a60065b	836	/@}/ /* end of group CMSIS_ITM */
kadonotakashi	0:8fdf9a60065b	837
kadonotakashi	0:8fdf9a60065b	838
kadonotakashi	0:8fdf9a60065b	839	/**
kadonotakashi	0:8fdf9a60065b	840	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	841	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
kadonotakashi	0:8fdf9a60065b	842	\brief Type definitions for the Data Watchpoint and Trace (DWT)
kadonotakashi	0:8fdf9a60065b	843	@{
kadonotakashi	0:8fdf9a60065b	844	*/
kadonotakashi	0:8fdf9a60065b	845
kadonotakashi	0:8fdf9a60065b	846	/**
kadonotakashi	0:8fdf9a60065b	847	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
kadonotakashi	0:8fdf9a60065b	848	*/
kadonotakashi	0:8fdf9a60065b	849	typedef struct
kadonotakashi	0:8fdf9a60065b	850	{
kadonotakashi	0:8fdf9a60065b	851	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
kadonotakashi	0:8fdf9a60065b	852	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
kadonotakashi	0:8fdf9a60065b	853	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
kadonotakashi	0:8fdf9a60065b	854	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
kadonotakashi	0:8fdf9a60065b	855	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
kadonotakashi	0:8fdf9a60065b	856	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
kadonotakashi	0:8fdf9a60065b	857	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
kadonotakashi	0:8fdf9a60065b	858	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
kadonotakashi	0:8fdf9a60065b	859	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
kadonotakashi	0:8fdf9a60065b	860	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
kadonotakashi	0:8fdf9a60065b	861	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
kadonotakashi	0:8fdf9a60065b	862	uint32_t RESERVED0[1U];
kadonotakashi	0:8fdf9a60065b	863	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
kadonotakashi	0:8fdf9a60065b	864	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
kadonotakashi	0:8fdf9a60065b	865	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
kadonotakashi	0:8fdf9a60065b	866	uint32_t RESERVED1[1U];
kadonotakashi	0:8fdf9a60065b	867	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
kadonotakashi	0:8fdf9a60065b	868	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
kadonotakashi	0:8fdf9a60065b	869	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
kadonotakashi	0:8fdf9a60065b	870	uint32_t RESERVED2[1U];
kadonotakashi	0:8fdf9a60065b	871	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
kadonotakashi	0:8fdf9a60065b	872	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
kadonotakashi	0:8fdf9a60065b	873	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
kadonotakashi	0:8fdf9a60065b	874	} DWT_Type;
kadonotakashi	0:8fdf9a60065b	875
kadonotakashi	0:8fdf9a60065b	876	/* DWT Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	877	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
kadonotakashi	0:8fdf9a60065b	878	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
kadonotakashi	0:8fdf9a60065b	879
kadonotakashi	0:8fdf9a60065b	880	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
kadonotakashi	0:8fdf9a60065b	881	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
kadonotakashi	0:8fdf9a60065b	882
kadonotakashi	0:8fdf9a60065b	883	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
kadonotakashi	0:8fdf9a60065b	884	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
kadonotakashi	0:8fdf9a60065b	885
kadonotakashi	0:8fdf9a60065b	886	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
kadonotakashi	0:8fdf9a60065b	887	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
kadonotakashi	0:8fdf9a60065b	888
kadonotakashi	0:8fdf9a60065b	889	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
kadonotakashi	0:8fdf9a60065b	890	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
kadonotakashi	0:8fdf9a60065b	891
kadonotakashi	0:8fdf9a60065b	892	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
kadonotakashi	0:8fdf9a60065b	893	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	894
kadonotakashi	0:8fdf9a60065b	895	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
kadonotakashi	0:8fdf9a60065b	896	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	897
kadonotakashi	0:8fdf9a60065b	898	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
kadonotakashi	0:8fdf9a60065b	899	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	900
kadonotakashi	0:8fdf9a60065b	901	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
kadonotakashi	0:8fdf9a60065b	902	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	903
kadonotakashi	0:8fdf9a60065b	904	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
kadonotakashi	0:8fdf9a60065b	905	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	906
kadonotakashi	0:8fdf9a60065b	907	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
kadonotakashi	0:8fdf9a60065b	908	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
kadonotakashi	0:8fdf9a60065b	909
kadonotakashi	0:8fdf9a60065b	910	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
kadonotakashi	0:8fdf9a60065b	911	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
kadonotakashi	0:8fdf9a60065b	912
kadonotakashi	0:8fdf9a60065b	913	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
kadonotakashi	0:8fdf9a60065b	914	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
kadonotakashi	0:8fdf9a60065b	915
kadonotakashi	0:8fdf9a60065b	916	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
kadonotakashi	0:8fdf9a60065b	917	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
kadonotakashi	0:8fdf9a60065b	918
kadonotakashi	0:8fdf9a60065b	919	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
kadonotakashi	0:8fdf9a60065b	920	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
kadonotakashi	0:8fdf9a60065b	921
kadonotakashi	0:8fdf9a60065b	922	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
kadonotakashi	0:8fdf9a60065b	923	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
kadonotakashi	0:8fdf9a60065b	924
kadonotakashi	0:8fdf9a60065b	925	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
kadonotakashi	0:8fdf9a60065b	926	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
kadonotakashi	0:8fdf9a60065b	927
kadonotakashi	0:8fdf9a60065b	928	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
kadonotakashi	0:8fdf9a60065b	929	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
kadonotakashi	0:8fdf9a60065b	930
kadonotakashi	0:8fdf9a60065b	931	/* DWT CPI Count Register Definitions */
kadonotakashi	0:8fdf9a60065b	932	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
kadonotakashi	0:8fdf9a60065b	933	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
kadonotakashi	0:8fdf9a60065b	934
kadonotakashi	0:8fdf9a60065b	935	/* DWT Exception Overhead Count Register Definitions */
kadonotakashi	0:8fdf9a60065b	936	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
kadonotakashi	0:8fdf9a60065b	937	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
kadonotakashi	0:8fdf9a60065b	938
kadonotakashi	0:8fdf9a60065b	939	/* DWT Sleep Count Register Definitions */
kadonotakashi	0:8fdf9a60065b	940	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
kadonotakashi	0:8fdf9a60065b	941	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
kadonotakashi	0:8fdf9a60065b	942
kadonotakashi	0:8fdf9a60065b	943	/* DWT LSU Count Register Definitions */
kadonotakashi	0:8fdf9a60065b	944	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
kadonotakashi	0:8fdf9a60065b	945	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
kadonotakashi	0:8fdf9a60065b	946
kadonotakashi	0:8fdf9a60065b	947	/* DWT Folded-instruction Count Register Definitions */
kadonotakashi	0:8fdf9a60065b	948	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
kadonotakashi	0:8fdf9a60065b	949	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
kadonotakashi	0:8fdf9a60065b	950
kadonotakashi	0:8fdf9a60065b	951	/* DWT Comparator Mask Register Definitions */
kadonotakashi	0:8fdf9a60065b	952	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
kadonotakashi	0:8fdf9a60065b	953	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
kadonotakashi	0:8fdf9a60065b	954
kadonotakashi	0:8fdf9a60065b	955	/* DWT Comparator Function Register Definitions */
kadonotakashi	0:8fdf9a60065b	956	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
kadonotakashi	0:8fdf9a60065b	957	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
kadonotakashi	0:8fdf9a60065b	958
kadonotakashi	0:8fdf9a60065b	959	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
kadonotakashi	0:8fdf9a60065b	960	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
kadonotakashi	0:8fdf9a60065b	961
kadonotakashi	0:8fdf9a60065b	962	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
kadonotakashi	0:8fdf9a60065b	963	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
kadonotakashi	0:8fdf9a60065b	964
kadonotakashi	0:8fdf9a60065b	965	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
kadonotakashi	0:8fdf9a60065b	966	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
kadonotakashi	0:8fdf9a60065b	967
kadonotakashi	0:8fdf9a60065b	968	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
kadonotakashi	0:8fdf9a60065b	969	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
kadonotakashi	0:8fdf9a60065b	970
kadonotakashi	0:8fdf9a60065b	971	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
kadonotakashi	0:8fdf9a60065b	972	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
kadonotakashi	0:8fdf9a60065b	973
kadonotakashi	0:8fdf9a60065b	974	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
kadonotakashi	0:8fdf9a60065b	975	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
kadonotakashi	0:8fdf9a60065b	976
kadonotakashi	0:8fdf9a60065b	977	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
kadonotakashi	0:8fdf9a60065b	978	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
kadonotakashi	0:8fdf9a60065b	979
kadonotakashi	0:8fdf9a60065b	980	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
kadonotakashi	0:8fdf9a60065b	981	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
kadonotakashi	0:8fdf9a60065b	982
kadonotakashi	0:8fdf9a60065b	983	/@}/ /* end of group CMSIS_DWT */
kadonotakashi	0:8fdf9a60065b	984
kadonotakashi	0:8fdf9a60065b	985
kadonotakashi	0:8fdf9a60065b	986	/**
kadonotakashi	0:8fdf9a60065b	987	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	988	\defgroup CMSIS_TPI Trace Port Interface (TPI)
kadonotakashi	0:8fdf9a60065b	989	\brief Type definitions for the Trace Port Interface (TPI)
kadonotakashi	0:8fdf9a60065b	990	@{
kadonotakashi	0:8fdf9a60065b	991	*/
kadonotakashi	0:8fdf9a60065b	992
kadonotakashi	0:8fdf9a60065b	993	/**
kadonotakashi	0:8fdf9a60065b	994	\brief Structure type to access the Trace Port Interface Register (TPI).
kadonotakashi	0:8fdf9a60065b	995	*/
kadonotakashi	0:8fdf9a60065b	996	typedef struct
kadonotakashi	0:8fdf9a60065b	997	{
kadonotakashi	0:8fdf9a60065b	998	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
kadonotakashi	0:8fdf9a60065b	999	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
kadonotakashi	0:8fdf9a60065b	1000	uint32_t RESERVED0[2U];
kadonotakashi	0:8fdf9a60065b	1001	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
kadonotakashi	0:8fdf9a60065b	1002	uint32_t RESERVED1[55U];
kadonotakashi	0:8fdf9a60065b	1003	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
kadonotakashi	0:8fdf9a60065b	1004	uint32_t RESERVED2[131U];
kadonotakashi	0:8fdf9a60065b	1005	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
kadonotakashi	0:8fdf9a60065b	1006	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
kadonotakashi	0:8fdf9a60065b	1007	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
kadonotakashi	0:8fdf9a60065b	1008	uint32_t RESERVED3[759U];
kadonotakashi	0:8fdf9a60065b	1009	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER Register /
kadonotakashi	0:8fdf9a60065b	1010	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
kadonotakashi	0:8fdf9a60065b	1011	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
kadonotakashi	0:8fdf9a60065b	1012	uint32_t RESERVED4[1U];
kadonotakashi	0:8fdf9a60065b	1013	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
kadonotakashi	0:8fdf9a60065b	1014	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
kadonotakashi	0:8fdf9a60065b	1015	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
kadonotakashi	0:8fdf9a60065b	1016	uint32_t RESERVED5[39U];
kadonotakashi	0:8fdf9a60065b	1017	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
kadonotakashi	0:8fdf9a60065b	1018	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
kadonotakashi	0:8fdf9a60065b	1019	uint32_t RESERVED7[8U];
kadonotakashi	0:8fdf9a60065b	1020	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
kadonotakashi	0:8fdf9a60065b	1021	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
kadonotakashi	0:8fdf9a60065b	1022	} TPI_Type;
kadonotakashi	0:8fdf9a60065b	1023
kadonotakashi	0:8fdf9a60065b	1024	/* TPI Asynchronous Clock Prescaler Register Definitions */
kadonotakashi	0:8fdf9a60065b	1025	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
kadonotakashi	0:8fdf9a60065b	1026	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
kadonotakashi	0:8fdf9a60065b	1027
kadonotakashi	0:8fdf9a60065b	1028	/* TPI Selected Pin Protocol Register Definitions */
kadonotakashi	0:8fdf9a60065b	1029	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
kadonotakashi	0:8fdf9a60065b	1030	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
kadonotakashi	0:8fdf9a60065b	1031
kadonotakashi	0:8fdf9a60065b	1032	/* TPI Formatter and Flush Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	1033	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
kadonotakashi	0:8fdf9a60065b	1034	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
kadonotakashi	0:8fdf9a60065b	1035
kadonotakashi	0:8fdf9a60065b	1036	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
kadonotakashi	0:8fdf9a60065b	1037	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
kadonotakashi	0:8fdf9a60065b	1038
kadonotakashi	0:8fdf9a60065b	1039	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
kadonotakashi	0:8fdf9a60065b	1040	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
kadonotakashi	0:8fdf9a60065b	1041
kadonotakashi	0:8fdf9a60065b	1042	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
kadonotakashi	0:8fdf9a60065b	1043	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
kadonotakashi	0:8fdf9a60065b	1044
kadonotakashi	0:8fdf9a60065b	1045	/* TPI Formatter and Flush Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1046	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
kadonotakashi	0:8fdf9a60065b	1047	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
kadonotakashi	0:8fdf9a60065b	1048
kadonotakashi	0:8fdf9a60065b	1049	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
kadonotakashi	0:8fdf9a60065b	1050	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
kadonotakashi	0:8fdf9a60065b	1051
kadonotakashi	0:8fdf9a60065b	1052	/* TPI TRIGGER Register Definitions */
kadonotakashi	0:8fdf9a60065b	1053	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
kadonotakashi	0:8fdf9a60065b	1054	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
kadonotakashi	0:8fdf9a60065b	1055
kadonotakashi	0:8fdf9a60065b	1056	/* TPI Integration ETM Data Register Definitions (FIFO0) */
kadonotakashi	0:8fdf9a60065b	1057	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
kadonotakashi	0:8fdf9a60065b	1058	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
kadonotakashi	0:8fdf9a60065b	1059
kadonotakashi	0:8fdf9a60065b	1060	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
kadonotakashi	0:8fdf9a60065b	1061	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
kadonotakashi	0:8fdf9a60065b	1062
kadonotakashi	0:8fdf9a60065b	1063	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
kadonotakashi	0:8fdf9a60065b	1064	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
kadonotakashi	0:8fdf9a60065b	1065
kadonotakashi	0:8fdf9a60065b	1066	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
kadonotakashi	0:8fdf9a60065b	1067	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
kadonotakashi	0:8fdf9a60065b	1068
kadonotakashi	0:8fdf9a60065b	1069	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
kadonotakashi	0:8fdf9a60065b	1070	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
kadonotakashi	0:8fdf9a60065b	1071
kadonotakashi	0:8fdf9a60065b	1072	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
kadonotakashi	0:8fdf9a60065b	1073	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
kadonotakashi	0:8fdf9a60065b	1074
kadonotakashi	0:8fdf9a60065b	1075	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
kadonotakashi	0:8fdf9a60065b	1076	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
kadonotakashi	0:8fdf9a60065b	1077
kadonotakashi	0:8fdf9a60065b	1078	/* TPI ITATBCTR2 Register Definitions */
kadonotakashi	0:8fdf9a60065b	1079	#define TPI_ITATBCTR2_ATREADY2_Pos 0U /!< TPI ITATBCTR2: ATREADY2 Position /
kadonotakashi	0:8fdf9a60065b	1080	#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/) /!< TPI ITATBCTR2: ATREADY2 Mask /
kadonotakashi	0:8fdf9a60065b	1081
kadonotakashi	0:8fdf9a60065b	1082	#define TPI_ITATBCTR2_ATREADY1_Pos 0U /!< TPI ITATBCTR2: ATREADY1 Position /
kadonotakashi	0:8fdf9a60065b	1083	#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/) /!< TPI ITATBCTR2: ATREADY1 Mask /
kadonotakashi	0:8fdf9a60065b	1084
kadonotakashi	0:8fdf9a60065b	1085	/* TPI Integration ITM Data Register Definitions (FIFO1) */
kadonotakashi	0:8fdf9a60065b	1086	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
kadonotakashi	0:8fdf9a60065b	1087	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
kadonotakashi	0:8fdf9a60065b	1088
kadonotakashi	0:8fdf9a60065b	1089	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
kadonotakashi	0:8fdf9a60065b	1090	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
kadonotakashi	0:8fdf9a60065b	1091
kadonotakashi	0:8fdf9a60065b	1092	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
kadonotakashi	0:8fdf9a60065b	1093	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
kadonotakashi	0:8fdf9a60065b	1094
kadonotakashi	0:8fdf9a60065b	1095	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
kadonotakashi	0:8fdf9a60065b	1096	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
kadonotakashi	0:8fdf9a60065b	1097
kadonotakashi	0:8fdf9a60065b	1098	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
kadonotakashi	0:8fdf9a60065b	1099	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
kadonotakashi	0:8fdf9a60065b	1100
kadonotakashi	0:8fdf9a60065b	1101	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
kadonotakashi	0:8fdf9a60065b	1102	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
kadonotakashi	0:8fdf9a60065b	1103
kadonotakashi	0:8fdf9a60065b	1104	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
kadonotakashi	0:8fdf9a60065b	1105	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
kadonotakashi	0:8fdf9a60065b	1106
kadonotakashi	0:8fdf9a60065b	1107	/* TPI ITATBCTR0 Register Definitions */
kadonotakashi	0:8fdf9a60065b	1108	#define TPI_ITATBCTR0_ATREADY2_Pos 0U /!< TPI ITATBCTR0: ATREADY2 Position /
kadonotakashi	0:8fdf9a60065b	1109	#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/) /!< TPI ITATBCTR0: ATREADY2 Mask /
kadonotakashi	0:8fdf9a60065b	1110
kadonotakashi	0:8fdf9a60065b	1111	#define TPI_ITATBCTR0_ATREADY1_Pos 0U /!< TPI ITATBCTR0: ATREADY1 Position /
kadonotakashi	0:8fdf9a60065b	1112	#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/) /!< TPI ITATBCTR0: ATREADY1 Mask /
kadonotakashi	0:8fdf9a60065b	1113
kadonotakashi	0:8fdf9a60065b	1114	/* TPI Integration Mode Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1115	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
kadonotakashi	0:8fdf9a60065b	1116	#define TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
kadonotakashi	0:8fdf9a60065b	1117
kadonotakashi	0:8fdf9a60065b	1118	/* TPI DEVID Register Definitions */
kadonotakashi	0:8fdf9a60065b	1119	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
kadonotakashi	0:8fdf9a60065b	1120	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
kadonotakashi	0:8fdf9a60065b	1121
kadonotakashi	0:8fdf9a60065b	1122	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
kadonotakashi	0:8fdf9a60065b	1123	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
kadonotakashi	0:8fdf9a60065b	1124
kadonotakashi	0:8fdf9a60065b	1125	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
kadonotakashi	0:8fdf9a60065b	1126	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
kadonotakashi	0:8fdf9a60065b	1127
kadonotakashi	0:8fdf9a60065b	1128	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
kadonotakashi	0:8fdf9a60065b	1129	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
kadonotakashi	0:8fdf9a60065b	1130
kadonotakashi	0:8fdf9a60065b	1131	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
kadonotakashi	0:8fdf9a60065b	1132	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
kadonotakashi	0:8fdf9a60065b	1133
kadonotakashi	0:8fdf9a60065b	1134	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
kadonotakashi	0:8fdf9a60065b	1135	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
kadonotakashi	0:8fdf9a60065b	1136
kadonotakashi	0:8fdf9a60065b	1137	/* TPI DEVTYPE Register Definitions */
kadonotakashi	0:8fdf9a60065b	1138	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
kadonotakashi	0:8fdf9a60065b	1139	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
kadonotakashi	0:8fdf9a60065b	1140
kadonotakashi	0:8fdf9a60065b	1141	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
kadonotakashi	0:8fdf9a60065b	1142	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
kadonotakashi	0:8fdf9a60065b	1143
kadonotakashi	0:8fdf9a60065b	1144	/@}/ /* end of group CMSIS_TPI */
kadonotakashi	0:8fdf9a60065b	1145
kadonotakashi	0:8fdf9a60065b	1146
kadonotakashi	0:8fdf9a60065b	1147	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	1148	/**
kadonotakashi	0:8fdf9a60065b	1149	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1150	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
kadonotakashi	0:8fdf9a60065b	1151	\brief Type definitions for the Memory Protection Unit (MPU)
kadonotakashi	0:8fdf9a60065b	1152	@{
kadonotakashi	0:8fdf9a60065b	1153	*/
kadonotakashi	0:8fdf9a60065b	1154
kadonotakashi	0:8fdf9a60065b	1155	/**
kadonotakashi	0:8fdf9a60065b	1156	\brief Structure type to access the Memory Protection Unit (MPU).
kadonotakashi	0:8fdf9a60065b	1157	*/
kadonotakashi	0:8fdf9a60065b	1158	typedef struct
kadonotakashi	0:8fdf9a60065b	1159	{
kadonotakashi	0:8fdf9a60065b	1160	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
kadonotakashi	0:8fdf9a60065b	1161	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
kadonotakashi	0:8fdf9a60065b	1162	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
kadonotakashi	0:8fdf9a60065b	1163	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
kadonotakashi	0:8fdf9a60065b	1164	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
kadonotakashi	0:8fdf9a60065b	1165	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
kadonotakashi	0:8fdf9a60065b	1166	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
kadonotakashi	0:8fdf9a60065b	1167	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
kadonotakashi	0:8fdf9a60065b	1168	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
kadonotakashi	0:8fdf9a60065b	1169	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
kadonotakashi	0:8fdf9a60065b	1170	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
kadonotakashi	0:8fdf9a60065b	1171	} MPU_Type;
kadonotakashi	0:8fdf9a60065b	1172
kadonotakashi	0:8fdf9a60065b	1173	#define MPU_TYPE_RALIASES 4U
kadonotakashi	0:8fdf9a60065b	1174
kadonotakashi	0:8fdf9a60065b	1175	/* MPU Type Register Definitions */
kadonotakashi	0:8fdf9a60065b	1176	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
kadonotakashi	0:8fdf9a60065b	1177	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
kadonotakashi	0:8fdf9a60065b	1178
kadonotakashi	0:8fdf9a60065b	1179	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
kadonotakashi	0:8fdf9a60065b	1180	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
kadonotakashi	0:8fdf9a60065b	1181
kadonotakashi	0:8fdf9a60065b	1182	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
kadonotakashi	0:8fdf9a60065b	1183	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
kadonotakashi	0:8fdf9a60065b	1184
kadonotakashi	0:8fdf9a60065b	1185	/* MPU Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1186	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
kadonotakashi	0:8fdf9a60065b	1187	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
kadonotakashi	0:8fdf9a60065b	1188
kadonotakashi	0:8fdf9a60065b	1189	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
kadonotakashi	0:8fdf9a60065b	1190	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
kadonotakashi	0:8fdf9a60065b	1191
kadonotakashi	0:8fdf9a60065b	1192	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
kadonotakashi	0:8fdf9a60065b	1193	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
kadonotakashi	0:8fdf9a60065b	1194
kadonotakashi	0:8fdf9a60065b	1195	/* MPU Region Number Register Definitions */
kadonotakashi	0:8fdf9a60065b	1196	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
kadonotakashi	0:8fdf9a60065b	1197	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
kadonotakashi	0:8fdf9a60065b	1198
kadonotakashi	0:8fdf9a60065b	1199	/* MPU Region Base Address Register Definitions */
kadonotakashi	0:8fdf9a60065b	1200	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
kadonotakashi	0:8fdf9a60065b	1201	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
kadonotakashi	0:8fdf9a60065b	1202
kadonotakashi	0:8fdf9a60065b	1203	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
kadonotakashi	0:8fdf9a60065b	1204	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
kadonotakashi	0:8fdf9a60065b	1205
kadonotakashi	0:8fdf9a60065b	1206	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
kadonotakashi	0:8fdf9a60065b	1207	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
kadonotakashi	0:8fdf9a60065b	1208
kadonotakashi	0:8fdf9a60065b	1209	/* MPU Region Attribute and Size Register Definitions */
kadonotakashi	0:8fdf9a60065b	1210	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
kadonotakashi	0:8fdf9a60065b	1211	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
kadonotakashi	0:8fdf9a60065b	1212
kadonotakashi	0:8fdf9a60065b	1213	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
kadonotakashi	0:8fdf9a60065b	1214	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
kadonotakashi	0:8fdf9a60065b	1215
kadonotakashi	0:8fdf9a60065b	1216	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
kadonotakashi	0:8fdf9a60065b	1217	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
kadonotakashi	0:8fdf9a60065b	1218
kadonotakashi	0:8fdf9a60065b	1219	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
kadonotakashi	0:8fdf9a60065b	1220	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
kadonotakashi	0:8fdf9a60065b	1221
kadonotakashi	0:8fdf9a60065b	1222	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
kadonotakashi	0:8fdf9a60065b	1223	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
kadonotakashi	0:8fdf9a60065b	1224
kadonotakashi	0:8fdf9a60065b	1225	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
kadonotakashi	0:8fdf9a60065b	1226	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
kadonotakashi	0:8fdf9a60065b	1227
kadonotakashi	0:8fdf9a60065b	1228	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
kadonotakashi	0:8fdf9a60065b	1229	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
kadonotakashi	0:8fdf9a60065b	1230
kadonotakashi	0:8fdf9a60065b	1231	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
kadonotakashi	0:8fdf9a60065b	1232	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
kadonotakashi	0:8fdf9a60065b	1233
kadonotakashi	0:8fdf9a60065b	1234	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
kadonotakashi	0:8fdf9a60065b	1235	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
kadonotakashi	0:8fdf9a60065b	1236
kadonotakashi	0:8fdf9a60065b	1237	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
kadonotakashi	0:8fdf9a60065b	1238	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
kadonotakashi	0:8fdf9a60065b	1239
kadonotakashi	0:8fdf9a60065b	1240	/@} end of group CMSIS_MPU /
kadonotakashi	0:8fdf9a60065b	1241	#endif
kadonotakashi	0:8fdf9a60065b	1242
kadonotakashi	0:8fdf9a60065b	1243
kadonotakashi	0:8fdf9a60065b	1244	/**
kadonotakashi	0:8fdf9a60065b	1245	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1246	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
kadonotakashi	0:8fdf9a60065b	1247	\brief Type definitions for the Core Debug Registers
kadonotakashi	0:8fdf9a60065b	1248	@{
kadonotakashi	0:8fdf9a60065b	1249	*/
kadonotakashi	0:8fdf9a60065b	1250
kadonotakashi	0:8fdf9a60065b	1251	/**
kadonotakashi	0:8fdf9a60065b	1252	\brief Structure type to access the Core Debug Register (CoreDebug).
kadonotakashi	0:8fdf9a60065b	1253	*/
kadonotakashi	0:8fdf9a60065b	1254	typedef struct
kadonotakashi	0:8fdf9a60065b	1255	{
kadonotakashi	0:8fdf9a60065b	1256	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
kadonotakashi	0:8fdf9a60065b	1257	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
kadonotakashi	0:8fdf9a60065b	1258	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
kadonotakashi	0:8fdf9a60065b	1259	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
kadonotakashi	0:8fdf9a60065b	1260	} CoreDebug_Type;
kadonotakashi	0:8fdf9a60065b	1261
kadonotakashi	0:8fdf9a60065b	1262	/* Debug Halting Control and Status Register Definitions */
kadonotakashi	0:8fdf9a60065b	1263	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
kadonotakashi	0:8fdf9a60065b	1264	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
kadonotakashi	0:8fdf9a60065b	1265
kadonotakashi	0:8fdf9a60065b	1266	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
kadonotakashi	0:8fdf9a60065b	1267	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
kadonotakashi	0:8fdf9a60065b	1268
kadonotakashi	0:8fdf9a60065b	1269	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
kadonotakashi	0:8fdf9a60065b	1270	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
kadonotakashi	0:8fdf9a60065b	1271
kadonotakashi	0:8fdf9a60065b	1272	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
kadonotakashi	0:8fdf9a60065b	1273	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
kadonotakashi	0:8fdf9a60065b	1274
kadonotakashi	0:8fdf9a60065b	1275	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
kadonotakashi	0:8fdf9a60065b	1276	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
kadonotakashi	0:8fdf9a60065b	1277
kadonotakashi	0:8fdf9a60065b	1278	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
kadonotakashi	0:8fdf9a60065b	1279	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
kadonotakashi	0:8fdf9a60065b	1280
kadonotakashi	0:8fdf9a60065b	1281	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
kadonotakashi	0:8fdf9a60065b	1282	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
kadonotakashi	0:8fdf9a60065b	1283
kadonotakashi	0:8fdf9a60065b	1284	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
kadonotakashi	0:8fdf9a60065b	1285	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
kadonotakashi	0:8fdf9a60065b	1286
kadonotakashi	0:8fdf9a60065b	1287	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
kadonotakashi	0:8fdf9a60065b	1288	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
kadonotakashi	0:8fdf9a60065b	1289
kadonotakashi	0:8fdf9a60065b	1290	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
kadonotakashi	0:8fdf9a60065b	1291	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
kadonotakashi	0:8fdf9a60065b	1292
kadonotakashi	0:8fdf9a60065b	1293	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
kadonotakashi	0:8fdf9a60065b	1294	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
kadonotakashi	0:8fdf9a60065b	1295
kadonotakashi	0:8fdf9a60065b	1296	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
kadonotakashi	0:8fdf9a60065b	1297	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
kadonotakashi	0:8fdf9a60065b	1298
kadonotakashi	0:8fdf9a60065b	1299	/* Debug Core Register Selector Register Definitions */
kadonotakashi	0:8fdf9a60065b	1300	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
kadonotakashi	0:8fdf9a60065b	1301	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
kadonotakashi	0:8fdf9a60065b	1302
kadonotakashi	0:8fdf9a60065b	1303	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
kadonotakashi	0:8fdf9a60065b	1304	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1305
kadonotakashi	0:8fdf9a60065b	1306	/* Debug Exception and Monitor Control Register Definitions */
kadonotakashi	0:8fdf9a60065b	1307	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
kadonotakashi	0:8fdf9a60065b	1308	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
kadonotakashi	0:8fdf9a60065b	1309
kadonotakashi	0:8fdf9a60065b	1310	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
kadonotakashi	0:8fdf9a60065b	1311	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
kadonotakashi	0:8fdf9a60065b	1312
kadonotakashi	0:8fdf9a60065b	1313	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
kadonotakashi	0:8fdf9a60065b	1314	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
kadonotakashi	0:8fdf9a60065b	1315
kadonotakashi	0:8fdf9a60065b	1316	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
kadonotakashi	0:8fdf9a60065b	1317	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
kadonotakashi	0:8fdf9a60065b	1318
kadonotakashi	0:8fdf9a60065b	1319	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
kadonotakashi	0:8fdf9a60065b	1320	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
kadonotakashi	0:8fdf9a60065b	1321
kadonotakashi	0:8fdf9a60065b	1322	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
kadonotakashi	0:8fdf9a60065b	1323	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
kadonotakashi	0:8fdf9a60065b	1324
kadonotakashi	0:8fdf9a60065b	1325	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
kadonotakashi	0:8fdf9a60065b	1326	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
kadonotakashi	0:8fdf9a60065b	1327
kadonotakashi	0:8fdf9a60065b	1328	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
kadonotakashi	0:8fdf9a60065b	1329	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
kadonotakashi	0:8fdf9a60065b	1330
kadonotakashi	0:8fdf9a60065b	1331	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
kadonotakashi	0:8fdf9a60065b	1332	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
kadonotakashi	0:8fdf9a60065b	1333
kadonotakashi	0:8fdf9a60065b	1334	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
kadonotakashi	0:8fdf9a60065b	1335	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
kadonotakashi	0:8fdf9a60065b	1336
kadonotakashi	0:8fdf9a60065b	1337	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
kadonotakashi	0:8fdf9a60065b	1338	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
kadonotakashi	0:8fdf9a60065b	1339
kadonotakashi	0:8fdf9a60065b	1340	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
kadonotakashi	0:8fdf9a60065b	1341	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
kadonotakashi	0:8fdf9a60065b	1342
kadonotakashi	0:8fdf9a60065b	1343	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
kadonotakashi	0:8fdf9a60065b	1344	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
kadonotakashi	0:8fdf9a60065b	1345
kadonotakashi	0:8fdf9a60065b	1346	/@} end of group CMSIS_CoreDebug /
kadonotakashi	0:8fdf9a60065b	1347
kadonotakashi	0:8fdf9a60065b	1348
kadonotakashi	0:8fdf9a60065b	1349	/**
kadonotakashi	0:8fdf9a60065b	1350	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1351	\defgroup CMSIS_core_bitfield Core register bit field macros
kadonotakashi	0:8fdf9a60065b	1352	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
kadonotakashi	0:8fdf9a60065b	1353	@{
kadonotakashi	0:8fdf9a60065b	1354	*/
kadonotakashi	0:8fdf9a60065b	1355
kadonotakashi	0:8fdf9a60065b	1356	/**
kadonotakashi	0:8fdf9a60065b	1357	\brief Mask and shift a bit field value for use in a register bit range.
kadonotakashi	0:8fdf9a60065b	1358	\param[in] field Name of the register bit field.
kadonotakashi	0:8fdf9a60065b	1359	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
kadonotakashi	0:8fdf9a60065b	1360	\return Masked and shifted value.
kadonotakashi	0:8fdf9a60065b	1361	*/
kadonotakashi	0:8fdf9a60065b	1362	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
kadonotakashi	0:8fdf9a60065b	1363
kadonotakashi	0:8fdf9a60065b	1364	/**
kadonotakashi	0:8fdf9a60065b	1365	\brief Mask and shift a register value to extract a bit filed value.
kadonotakashi	0:8fdf9a60065b	1366	\param[in] field Name of the register bit field.
kadonotakashi	0:8fdf9a60065b	1367	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
kadonotakashi	0:8fdf9a60065b	1368	\return Masked and shifted bit field value.
kadonotakashi	0:8fdf9a60065b	1369	*/
kadonotakashi	0:8fdf9a60065b	1370	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
kadonotakashi	0:8fdf9a60065b	1371
kadonotakashi	0:8fdf9a60065b	1372	/@} end of group CMSIS_core_bitfield /
kadonotakashi	0:8fdf9a60065b	1373
kadonotakashi	0:8fdf9a60065b	1374
kadonotakashi	0:8fdf9a60065b	1375	/**
kadonotakashi	0:8fdf9a60065b	1376	\ingroup CMSIS_core_register
kadonotakashi	0:8fdf9a60065b	1377	\defgroup CMSIS_core_base Core Definitions
kadonotakashi	0:8fdf9a60065b	1378	\brief Definitions for base addresses, unions, and structures.
kadonotakashi	0:8fdf9a60065b	1379	@{
kadonotakashi	0:8fdf9a60065b	1380	*/
kadonotakashi	0:8fdf9a60065b	1381
kadonotakashi	0:8fdf9a60065b	1382	/* Memory mapping of Core Hardware */
kadonotakashi	0:8fdf9a60065b	1383	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
kadonotakashi	0:8fdf9a60065b	1384	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
kadonotakashi	0:8fdf9a60065b	1385	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
kadonotakashi	0:8fdf9a60065b	1386	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
kadonotakashi	0:8fdf9a60065b	1387	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
kadonotakashi	0:8fdf9a60065b	1388	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
kadonotakashi	0:8fdf9a60065b	1389	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
kadonotakashi	0:8fdf9a60065b	1390	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
kadonotakashi	0:8fdf9a60065b	1391
kadonotakashi	0:8fdf9a60065b	1392	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
kadonotakashi	0:8fdf9a60065b	1393	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
kadonotakashi	0:8fdf9a60065b	1394	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
kadonotakashi	0:8fdf9a60065b	1395	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
kadonotakashi	0:8fdf9a60065b	1396	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
kadonotakashi	0:8fdf9a60065b	1397	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
kadonotakashi	0:8fdf9a60065b	1398	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
kadonotakashi	0:8fdf9a60065b	1399	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
kadonotakashi	0:8fdf9a60065b	1400
kadonotakashi	0:8fdf9a60065b	1401	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	1402	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
kadonotakashi	0:8fdf9a60065b	1403	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
kadonotakashi	0:8fdf9a60065b	1404	#endif
kadonotakashi	0:8fdf9a60065b	1405
kadonotakashi	0:8fdf9a60065b	1406	/@} /
kadonotakashi	0:8fdf9a60065b	1407
kadonotakashi	0:8fdf9a60065b	1408
kadonotakashi	0:8fdf9a60065b	1409
kadonotakashi	0:8fdf9a60065b	1410	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	1411	* Hardware Abstraction Layer
kadonotakashi	0:8fdf9a60065b	1412	Core Function Interface contains:
kadonotakashi	0:8fdf9a60065b	1413	- Core NVIC Functions
kadonotakashi	0:8fdf9a60065b	1414	- Core SysTick Functions
kadonotakashi	0:8fdf9a60065b	1415	- Core Debug Functions
kadonotakashi	0:8fdf9a60065b	1416	- Core Register Access Functions
kadonotakashi	0:8fdf9a60065b	1417	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	1418	/**
kadonotakashi	0:8fdf9a60065b	1419	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
kadonotakashi	0:8fdf9a60065b	1420	*/
kadonotakashi	0:8fdf9a60065b	1421
kadonotakashi	0:8fdf9a60065b	1422
kadonotakashi	0:8fdf9a60065b	1423
kadonotakashi	0:8fdf9a60065b	1424	/* ########################## NVIC functions #################################### */
kadonotakashi	0:8fdf9a60065b	1425	/**
kadonotakashi	0:8fdf9a60065b	1426	\ingroup CMSIS_Core_FunctionInterface
kadonotakashi	0:8fdf9a60065b	1427	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
kadonotakashi	0:8fdf9a60065b	1428	\brief Functions that manage interrupts and exceptions via the NVIC.
kadonotakashi	0:8fdf9a60065b	1429	@{
kadonotakashi	0:8fdf9a60065b	1430	*/
kadonotakashi	0:8fdf9a60065b	1431
kadonotakashi	0:8fdf9a60065b	1432	#ifdef CMSIS_NVIC_VIRTUAL
kadonotakashi	0:8fdf9a60065b	1433	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
kadonotakashi	0:8fdf9a60065b	1434	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
kadonotakashi	0:8fdf9a60065b	1435	#endif
kadonotakashi	0:8fdf9a60065b	1436	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
kadonotakashi	0:8fdf9a60065b	1437	#else
kadonotakashi	0:8fdf9a60065b	1438	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
kadonotakashi	0:8fdf9a60065b	1439	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
kadonotakashi	0:8fdf9a60065b	1440	#define NVIC_EnableIRQ __NVIC_EnableIRQ
kadonotakashi	0:8fdf9a60065b	1441	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
kadonotakashi	0:8fdf9a60065b	1442	#define NVIC_DisableIRQ __NVIC_DisableIRQ
kadonotakashi	0:8fdf9a60065b	1443	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
kadonotakashi	0:8fdf9a60065b	1444	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
kadonotakashi	0:8fdf9a60065b	1445	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
kadonotakashi	0:8fdf9a60065b	1446	#define NVIC_GetActive __NVIC_GetActive
kadonotakashi	0:8fdf9a60065b	1447	#define NVIC_SetPriority __NVIC_SetPriority
kadonotakashi	0:8fdf9a60065b	1448	#define NVIC_GetPriority __NVIC_GetPriority
kadonotakashi	0:8fdf9a60065b	1449	#define NVIC_SystemReset __NVIC_SystemReset
kadonotakashi	0:8fdf9a60065b	1450	#endif /* CMSIS_NVIC_VIRTUAL */
kadonotakashi	0:8fdf9a60065b	1451
kadonotakashi	0:8fdf9a60065b	1452	#ifdef CMSIS_VECTAB_VIRTUAL
kadonotakashi	0:8fdf9a60065b	1453	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kadonotakashi	0:8fdf9a60065b	1454	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
kadonotakashi	0:8fdf9a60065b	1455	#endif
kadonotakashi	0:8fdf9a60065b	1456	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kadonotakashi	0:8fdf9a60065b	1457	#else
kadonotakashi	0:8fdf9a60065b	1458	#define NVIC_SetVector __NVIC_SetVector
kadonotakashi	0:8fdf9a60065b	1459	#define NVIC_GetVector __NVIC_GetVector
kadonotakashi	0:8fdf9a60065b	1460	#endif /* (CMSIS_VECTAB_VIRTUAL) */
kadonotakashi	0:8fdf9a60065b	1461
kadonotakashi	0:8fdf9a60065b	1462	#define NVIC_USER_IRQ_OFFSET 16
kadonotakashi	0:8fdf9a60065b	1463
kadonotakashi	0:8fdf9a60065b	1464
kadonotakashi	0:8fdf9a60065b	1465	/* The following EXC_RETURN values are saved the LR on exception entry */
kadonotakashi	0:8fdf9a60065b	1466	#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
kadonotakashi	0:8fdf9a60065b	1467	#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
kadonotakashi	0:8fdf9a60065b	1468	#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
kadonotakashi	0:8fdf9a60065b	1469
kadonotakashi	0:8fdf9a60065b	1470
kadonotakashi	0:8fdf9a60065b	1471	/**
kadonotakashi	0:8fdf9a60065b	1472	\brief Set Priority Grouping
kadonotakashi	0:8fdf9a60065b	1473	\details Sets the priority grouping field using the required unlock sequence.
kadonotakashi	0:8fdf9a60065b	1474	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
kadonotakashi	0:8fdf9a60065b	1475	Only values from 0..7 are used.
kadonotakashi	0:8fdf9a60065b	1476	In case of a conflict between priority grouping and available
kadonotakashi	0:8fdf9a60065b	1477	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kadonotakashi	0:8fdf9a60065b	1478	\param [in] PriorityGroup Priority grouping field.
kadonotakashi	0:8fdf9a60065b	1479	*/
kadonotakashi	0:8fdf9a60065b	1480	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
kadonotakashi	0:8fdf9a60065b	1481	{
kadonotakashi	0:8fdf9a60065b	1482	uint32_t reg_value;
kadonotakashi	0:8fdf9a60065b	1483	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kadonotakashi	0:8fdf9a60065b	1484
kadonotakashi	0:8fdf9a60065b	1485	reg_value = SCB->AIRCR; /* read old register configuration */
kadonotakashi	0:8fdf9a60065b	1486	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
kadonotakashi	0:8fdf9a60065b	1487	reg_value = (reg_value \|
kadonotakashi	0:8fdf9a60065b	1488	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
kadonotakashi	0:8fdf9a60065b	1489	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
kadonotakashi	0:8fdf9a60065b	1490	SCB->AIRCR = reg_value;
kadonotakashi	0:8fdf9a60065b	1491	}
kadonotakashi	0:8fdf9a60065b	1492
kadonotakashi	0:8fdf9a60065b	1493
kadonotakashi	0:8fdf9a60065b	1494	/**
kadonotakashi	0:8fdf9a60065b	1495	\brief Get Priority Grouping
kadonotakashi	0:8fdf9a60065b	1496	\details Reads the priority grouping field from the NVIC Interrupt Controller.
kadonotakashi	0:8fdf9a60065b	1497	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
kadonotakashi	0:8fdf9a60065b	1498	*/
kadonotakashi	0:8fdf9a60065b	1499	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
kadonotakashi	0:8fdf9a60065b	1500	{
kadonotakashi	0:8fdf9a60065b	1501	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
kadonotakashi	0:8fdf9a60065b	1502	}
kadonotakashi	0:8fdf9a60065b	1503
kadonotakashi	0:8fdf9a60065b	1504
kadonotakashi	0:8fdf9a60065b	1505	/**
kadonotakashi	0:8fdf9a60065b	1506	\brief Enable Interrupt
kadonotakashi	0:8fdf9a60065b	1507	\details Enables a device specific interrupt in the NVIC interrupt controller.
kadonotakashi	0:8fdf9a60065b	1508	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1509	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1510	*/
kadonotakashi	0:8fdf9a60065b	1511	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1512	{
kadonotakashi	0:8fdf9a60065b	1513	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1514	{
kadonotakashi	0:8fdf9a60065b	1515	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kadonotakashi	0:8fdf9a60065b	1516	}
kadonotakashi	0:8fdf9a60065b	1517	}
kadonotakashi	0:8fdf9a60065b	1518
kadonotakashi	0:8fdf9a60065b	1519
kadonotakashi	0:8fdf9a60065b	1520	/**
kadonotakashi	0:8fdf9a60065b	1521	\brief Get Interrupt Enable status
kadonotakashi	0:8fdf9a60065b	1522	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
kadonotakashi	0:8fdf9a60065b	1523	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1524	\return 0 Interrupt is not enabled.
kadonotakashi	0:8fdf9a60065b	1525	\return 1 Interrupt is enabled.
kadonotakashi	0:8fdf9a60065b	1526	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1527	*/
kadonotakashi	0:8fdf9a60065b	1528	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1529	{
kadonotakashi	0:8fdf9a60065b	1530	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1531	{
kadonotakashi	0:8fdf9a60065b	1532	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kadonotakashi	0:8fdf9a60065b	1533	}
kadonotakashi	0:8fdf9a60065b	1534	else
kadonotakashi	0:8fdf9a60065b	1535	{
kadonotakashi	0:8fdf9a60065b	1536	return(0U);
kadonotakashi	0:8fdf9a60065b	1537	}
kadonotakashi	0:8fdf9a60065b	1538	}
kadonotakashi	0:8fdf9a60065b	1539
kadonotakashi	0:8fdf9a60065b	1540
kadonotakashi	0:8fdf9a60065b	1541	/**
kadonotakashi	0:8fdf9a60065b	1542	\brief Disable Interrupt
kadonotakashi	0:8fdf9a60065b	1543	\details Disables a device specific interrupt in the NVIC interrupt controller.
kadonotakashi	0:8fdf9a60065b	1544	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1545	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1546	*/
kadonotakashi	0:8fdf9a60065b	1547	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1548	{
kadonotakashi	0:8fdf9a60065b	1549	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1550	{
kadonotakashi	0:8fdf9a60065b	1551	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kadonotakashi	0:8fdf9a60065b	1552	__DSB();
kadonotakashi	0:8fdf9a60065b	1553	__ISB();
kadonotakashi	0:8fdf9a60065b	1554	}
kadonotakashi	0:8fdf9a60065b	1555	}
kadonotakashi	0:8fdf9a60065b	1556
kadonotakashi	0:8fdf9a60065b	1557
kadonotakashi	0:8fdf9a60065b	1558	/**
kadonotakashi	0:8fdf9a60065b	1559	\brief Get Pending Interrupt
kadonotakashi	0:8fdf9a60065b	1560	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
kadonotakashi	0:8fdf9a60065b	1561	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1562	\return 0 Interrupt status is not pending.
kadonotakashi	0:8fdf9a60065b	1563	\return 1 Interrupt status is pending.
kadonotakashi	0:8fdf9a60065b	1564	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1565	*/
kadonotakashi	0:8fdf9a60065b	1566	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1567	{
kadonotakashi	0:8fdf9a60065b	1568	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1569	{
kadonotakashi	0:8fdf9a60065b	1570	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kadonotakashi	0:8fdf9a60065b	1571	}
kadonotakashi	0:8fdf9a60065b	1572	else
kadonotakashi	0:8fdf9a60065b	1573	{
kadonotakashi	0:8fdf9a60065b	1574	return(0U);
kadonotakashi	0:8fdf9a60065b	1575	}
kadonotakashi	0:8fdf9a60065b	1576	}
kadonotakashi	0:8fdf9a60065b	1577
kadonotakashi	0:8fdf9a60065b	1578
kadonotakashi	0:8fdf9a60065b	1579	/**
kadonotakashi	0:8fdf9a60065b	1580	\brief Set Pending Interrupt
kadonotakashi	0:8fdf9a60065b	1581	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
kadonotakashi	0:8fdf9a60065b	1582	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1583	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1584	*/
kadonotakashi	0:8fdf9a60065b	1585	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1586	{
kadonotakashi	0:8fdf9a60065b	1587	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1588	{
kadonotakashi	0:8fdf9a60065b	1589	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kadonotakashi	0:8fdf9a60065b	1590	}
kadonotakashi	0:8fdf9a60065b	1591	}
kadonotakashi	0:8fdf9a60065b	1592
kadonotakashi	0:8fdf9a60065b	1593
kadonotakashi	0:8fdf9a60065b	1594	/**
kadonotakashi	0:8fdf9a60065b	1595	\brief Clear Pending Interrupt
kadonotakashi	0:8fdf9a60065b	1596	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
kadonotakashi	0:8fdf9a60065b	1597	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1598	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1599	*/
kadonotakashi	0:8fdf9a60065b	1600	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1601	{
kadonotakashi	0:8fdf9a60065b	1602	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1603	{
kadonotakashi	0:8fdf9a60065b	1604	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kadonotakashi	0:8fdf9a60065b	1605	}
kadonotakashi	0:8fdf9a60065b	1606	}
kadonotakashi	0:8fdf9a60065b	1607
kadonotakashi	0:8fdf9a60065b	1608
kadonotakashi	0:8fdf9a60065b	1609	/**
kadonotakashi	0:8fdf9a60065b	1610	\brief Get Active Interrupt
kadonotakashi	0:8fdf9a60065b	1611	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
kadonotakashi	0:8fdf9a60065b	1612	\param [in] IRQn Device specific interrupt number.
kadonotakashi	0:8fdf9a60065b	1613	\return 0 Interrupt status is not active.
kadonotakashi	0:8fdf9a60065b	1614	\return 1 Interrupt status is active.
kadonotakashi	0:8fdf9a60065b	1615	\note IRQn must not be negative.
kadonotakashi	0:8fdf9a60065b	1616	*/
kadonotakashi	0:8fdf9a60065b	1617	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1618	{
kadonotakashi	0:8fdf9a60065b	1619	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1620	{
kadonotakashi	0:8fdf9a60065b	1621	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kadonotakashi	0:8fdf9a60065b	1622	}
kadonotakashi	0:8fdf9a60065b	1623	else
kadonotakashi	0:8fdf9a60065b	1624	{
kadonotakashi	0:8fdf9a60065b	1625	return(0U);
kadonotakashi	0:8fdf9a60065b	1626	}
kadonotakashi	0:8fdf9a60065b	1627	}
kadonotakashi	0:8fdf9a60065b	1628
kadonotakashi	0:8fdf9a60065b	1629
kadonotakashi	0:8fdf9a60065b	1630	/**
kadonotakashi	0:8fdf9a60065b	1631	\brief Set Interrupt Priority
kadonotakashi	0:8fdf9a60065b	1632	\details Sets the priority of a device specific interrupt or a processor exception.
kadonotakashi	0:8fdf9a60065b	1633	The interrupt number can be positive to specify a device specific interrupt,
kadonotakashi	0:8fdf9a60065b	1634	or negative to specify a processor exception.
kadonotakashi	0:8fdf9a60065b	1635	\param [in] IRQn Interrupt number.
kadonotakashi	0:8fdf9a60065b	1636	\param [in] priority Priority to set.
kadonotakashi	0:8fdf9a60065b	1637	\note The priority cannot be set for every processor exception.
kadonotakashi	0:8fdf9a60065b	1638	*/
kadonotakashi	0:8fdf9a60065b	1639	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
kadonotakashi	0:8fdf9a60065b	1640	{
kadonotakashi	0:8fdf9a60065b	1641	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1642	{
kadonotakashi	0:8fdf9a60065b	1643	NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kadonotakashi	0:8fdf9a60065b	1644	}
kadonotakashi	0:8fdf9a60065b	1645	else
kadonotakashi	0:8fdf9a60065b	1646	{
kadonotakashi	0:8fdf9a60065b	1647	SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kadonotakashi	0:8fdf9a60065b	1648	}
kadonotakashi	0:8fdf9a60065b	1649	}
kadonotakashi	0:8fdf9a60065b	1650
kadonotakashi	0:8fdf9a60065b	1651
kadonotakashi	0:8fdf9a60065b	1652	/**
kadonotakashi	0:8fdf9a60065b	1653	\brief Get Interrupt Priority
kadonotakashi	0:8fdf9a60065b	1654	\details Reads the priority of a device specific interrupt or a processor exception.
kadonotakashi	0:8fdf9a60065b	1655	The interrupt number can be positive to specify a device specific interrupt,
kadonotakashi	0:8fdf9a60065b	1656	or negative to specify a processor exception.
kadonotakashi	0:8fdf9a60065b	1657	\param [in] IRQn Interrupt number.
kadonotakashi	0:8fdf9a60065b	1658	\return Interrupt Priority.
kadonotakashi	0:8fdf9a60065b	1659	Value is aligned automatically to the implemented priority bits of the microcontroller.
kadonotakashi	0:8fdf9a60065b	1660	*/
kadonotakashi	0:8fdf9a60065b	1661	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1662	{
kadonotakashi	0:8fdf9a60065b	1663
kadonotakashi	0:8fdf9a60065b	1664	if ((int32_t)(IRQn) >= 0)
kadonotakashi	0:8fdf9a60065b	1665	{
kadonotakashi	0:8fdf9a60065b	1666	return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
kadonotakashi	0:8fdf9a60065b	1667	}
kadonotakashi	0:8fdf9a60065b	1668	else
kadonotakashi	0:8fdf9a60065b	1669	{
kadonotakashi	0:8fdf9a60065b	1670	return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
kadonotakashi	0:8fdf9a60065b	1671	}
kadonotakashi	0:8fdf9a60065b	1672	}
kadonotakashi	0:8fdf9a60065b	1673
kadonotakashi	0:8fdf9a60065b	1674
kadonotakashi	0:8fdf9a60065b	1675	/**
kadonotakashi	0:8fdf9a60065b	1676	\brief Encode Priority
kadonotakashi	0:8fdf9a60065b	1677	\details Encodes the priority for an interrupt with the given priority group,
kadonotakashi	0:8fdf9a60065b	1678	preemptive priority value, and subpriority value.
kadonotakashi	0:8fdf9a60065b	1679	In case of a conflict between priority grouping and available
kadonotakashi	0:8fdf9a60065b	1680	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kadonotakashi	0:8fdf9a60065b	1681	\param [in] PriorityGroup Used priority group.
kadonotakashi	0:8fdf9a60065b	1682	\param [in] PreemptPriority Preemptive priority value (starting from 0).
kadonotakashi	0:8fdf9a60065b	1683	\param [in] SubPriority Subpriority value (starting from 0).
kadonotakashi	0:8fdf9a60065b	1684	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
kadonotakashi	0:8fdf9a60065b	1685	*/
kadonotakashi	0:8fdf9a60065b	1686	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
kadonotakashi	0:8fdf9a60065b	1687	{
kadonotakashi	0:8fdf9a60065b	1688	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kadonotakashi	0:8fdf9a60065b	1689	uint32_t PreemptPriorityBits;
kadonotakashi	0:8fdf9a60065b	1690	uint32_t SubPriorityBits;
kadonotakashi	0:8fdf9a60065b	1691
kadonotakashi	0:8fdf9a60065b	1692	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kadonotakashi	0:8fdf9a60065b	1693	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kadonotakashi	0:8fdf9a60065b	1694
kadonotakashi	0:8fdf9a60065b	1695	return (
kadonotakashi	0:8fdf9a60065b	1696	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
kadonotakashi	0:8fdf9a60065b	1697	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
kadonotakashi	0:8fdf9a60065b	1698	);
kadonotakashi	0:8fdf9a60065b	1699	}
kadonotakashi	0:8fdf9a60065b	1700
kadonotakashi	0:8fdf9a60065b	1701
kadonotakashi	0:8fdf9a60065b	1702	/**
kadonotakashi	0:8fdf9a60065b	1703	\brief Decode Priority
kadonotakashi	0:8fdf9a60065b	1704	\details Decodes an interrupt priority value with a given priority group to
kadonotakashi	0:8fdf9a60065b	1705	preemptive priority value and subpriority value.
kadonotakashi	0:8fdf9a60065b	1706	In case of a conflict between priority grouping and available
kadonotakashi	0:8fdf9a60065b	1707	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
kadonotakashi	0:8fdf9a60065b	1708	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
kadonotakashi	0:8fdf9a60065b	1709	\param [in] PriorityGroup Used priority group.
kadonotakashi	0:8fdf9a60065b	1710	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
kadonotakashi	0:8fdf9a60065b	1711	\param [out] pSubPriority Subpriority value (starting from 0).
kadonotakashi	0:8fdf9a60065b	1712	*/
kadonotakashi	0:8fdf9a60065b	1713	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
kadonotakashi	0:8fdf9a60065b	1714	{
kadonotakashi	0:8fdf9a60065b	1715	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kadonotakashi	0:8fdf9a60065b	1716	uint32_t PreemptPriorityBits;
kadonotakashi	0:8fdf9a60065b	1717	uint32_t SubPriorityBits;
kadonotakashi	0:8fdf9a60065b	1718
kadonotakashi	0:8fdf9a60065b	1719	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kadonotakashi	0:8fdf9a60065b	1720	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kadonotakashi	0:8fdf9a60065b	1721
kadonotakashi	0:8fdf9a60065b	1722	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
kadonotakashi	0:8fdf9a60065b	1723	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
kadonotakashi	0:8fdf9a60065b	1724	}
kadonotakashi	0:8fdf9a60065b	1725
kadonotakashi	0:8fdf9a60065b	1726
kadonotakashi	0:8fdf9a60065b	1727	/**
kadonotakashi	0:8fdf9a60065b	1728	\brief Set Interrupt Vector
kadonotakashi	0:8fdf9a60065b	1729	\details Sets an interrupt vector in SRAM based interrupt vector table.
kadonotakashi	0:8fdf9a60065b	1730	The interrupt number can be positive to specify a device specific interrupt,
kadonotakashi	0:8fdf9a60065b	1731	or negative to specify a processor exception.
kadonotakashi	0:8fdf9a60065b	1732	VTOR must been relocated to SRAM before.
kadonotakashi	0:8fdf9a60065b	1733	\param [in] IRQn Interrupt number
kadonotakashi	0:8fdf9a60065b	1734	\param [in] vector Address of interrupt handler function
kadonotakashi	0:8fdf9a60065b	1735	*/
kadonotakashi	0:8fdf9a60065b	1736	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
kadonotakashi	0:8fdf9a60065b	1737	{
kadonotakashi	0:8fdf9a60065b	1738	uint32_t vectors = (uint32_t )SCB->VTOR;
kadonotakashi	0:8fdf9a60065b	1739	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
kadonotakashi	0:8fdf9a60065b	1740	}
kadonotakashi	0:8fdf9a60065b	1741
kadonotakashi	0:8fdf9a60065b	1742
kadonotakashi	0:8fdf9a60065b	1743	/**
kadonotakashi	0:8fdf9a60065b	1744	\brief Get Interrupt Vector
kadonotakashi	0:8fdf9a60065b	1745	\details Reads an interrupt vector from interrupt vector table.
kadonotakashi	0:8fdf9a60065b	1746	The interrupt number can be positive to specify a device specific interrupt,
kadonotakashi	0:8fdf9a60065b	1747	or negative to specify a processor exception.
kadonotakashi	0:8fdf9a60065b	1748	\param [in] IRQn Interrupt number.
kadonotakashi	0:8fdf9a60065b	1749	\return Address of interrupt handler function
kadonotakashi	0:8fdf9a60065b	1750	*/
kadonotakashi	0:8fdf9a60065b	1751	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
kadonotakashi	0:8fdf9a60065b	1752	{
kadonotakashi	0:8fdf9a60065b	1753	uint32_t vectors = (uint32_t )SCB->VTOR;
kadonotakashi	0:8fdf9a60065b	1754	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
kadonotakashi	0:8fdf9a60065b	1755	}
kadonotakashi	0:8fdf9a60065b	1756
kadonotakashi	0:8fdf9a60065b	1757
kadonotakashi	0:8fdf9a60065b	1758	/**
kadonotakashi	0:8fdf9a60065b	1759	\brief System Reset
kadonotakashi	0:8fdf9a60065b	1760	\details Initiates a system reset request to reset the MCU.
kadonotakashi	0:8fdf9a60065b	1761	*/
kadonotakashi	0:8fdf9a60065b	1762	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
kadonotakashi	0:8fdf9a60065b	1763	{
kadonotakashi	0:8fdf9a60065b	1764	__DSB(); /* Ensure all outstanding memory accesses included
kadonotakashi	0:8fdf9a60065b	1765	buffered write are completed before reset */
kadonotakashi	0:8fdf9a60065b	1766	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
kadonotakashi	0:8fdf9a60065b	1767	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
kadonotakashi	0:8fdf9a60065b	1768	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
kadonotakashi	0:8fdf9a60065b	1769	__DSB(); /* Ensure completion of memory access */
kadonotakashi	0:8fdf9a60065b	1770
kadonotakashi	0:8fdf9a60065b	1771	for(;;) /* wait until reset */
kadonotakashi	0:8fdf9a60065b	1772	{
kadonotakashi	0:8fdf9a60065b	1773	__NOP();
kadonotakashi	0:8fdf9a60065b	1774	}
kadonotakashi	0:8fdf9a60065b	1775	}
kadonotakashi	0:8fdf9a60065b	1776
kadonotakashi	0:8fdf9a60065b	1777	/@} end of CMSIS_Core_NVICFunctions /
kadonotakashi	0:8fdf9a60065b	1778
kadonotakashi	0:8fdf9a60065b	1779	/* ########################## MPU functions #################################### */
kadonotakashi	0:8fdf9a60065b	1780
kadonotakashi	0:8fdf9a60065b	1781	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kadonotakashi	0:8fdf9a60065b	1782
kadonotakashi	0:8fdf9a60065b	1783	#include "mpu_armv7.h"
kadonotakashi	0:8fdf9a60065b	1784
kadonotakashi	0:8fdf9a60065b	1785	#endif
kadonotakashi	0:8fdf9a60065b	1786
kadonotakashi	0:8fdf9a60065b	1787	/* ########################## FPU functions #################################### */
kadonotakashi	0:8fdf9a60065b	1788	/**
kadonotakashi	0:8fdf9a60065b	1789	\ingroup CMSIS_Core_FunctionInterface
kadonotakashi	0:8fdf9a60065b	1790	\defgroup CMSIS_Core_FpuFunctions FPU Functions
kadonotakashi	0:8fdf9a60065b	1791	\brief Function that provides FPU type.
kadonotakashi	0:8fdf9a60065b	1792	@{
kadonotakashi	0:8fdf9a60065b	1793	*/
kadonotakashi	0:8fdf9a60065b	1794
kadonotakashi	0:8fdf9a60065b	1795	/**
kadonotakashi	0:8fdf9a60065b	1796	\brief get FPU type
kadonotakashi	0:8fdf9a60065b	1797	\details returns the FPU type
kadonotakashi	0:8fdf9a60065b	1798	\returns
kadonotakashi	0:8fdf9a60065b	1799	- \b 0: No FPU
kadonotakashi	0:8fdf9a60065b	1800	- \b 1: Single precision FPU
kadonotakashi	0:8fdf9a60065b	1801	- \b 2: Double + Single precision FPU
kadonotakashi	0:8fdf9a60065b	1802	*/
kadonotakashi	0:8fdf9a60065b	1803	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
kadonotakashi	0:8fdf9a60065b	1804	{
kadonotakashi	0:8fdf9a60065b	1805	return 0U; /* No FPU */
kadonotakashi	0:8fdf9a60065b	1806	}
kadonotakashi	0:8fdf9a60065b	1807
kadonotakashi	0:8fdf9a60065b	1808
kadonotakashi	0:8fdf9a60065b	1809	/@} end of CMSIS_Core_FpuFunctions /
kadonotakashi	0:8fdf9a60065b	1810
kadonotakashi	0:8fdf9a60065b	1811
kadonotakashi	0:8fdf9a60065b	1812
kadonotakashi	0:8fdf9a60065b	1813	/* ################################## SysTick function ############################################ */
kadonotakashi	0:8fdf9a60065b	1814	/**
kadonotakashi	0:8fdf9a60065b	1815	\ingroup CMSIS_Core_FunctionInterface
kadonotakashi	0:8fdf9a60065b	1816	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
kadonotakashi	0:8fdf9a60065b	1817	\brief Functions that configure the System.
kadonotakashi	0:8fdf9a60065b	1818	@{
kadonotakashi	0:8fdf9a60065b	1819	*/
kadonotakashi	0:8fdf9a60065b	1820
kadonotakashi	0:8fdf9a60065b	1821	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
kadonotakashi	0:8fdf9a60065b	1822
kadonotakashi	0:8fdf9a60065b	1823	/**
kadonotakashi	0:8fdf9a60065b	1824	\brief System Tick Configuration
kadonotakashi	0:8fdf9a60065b	1825	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
kadonotakashi	0:8fdf9a60065b	1826	Counter is in free running mode to generate periodic interrupts.
kadonotakashi	0:8fdf9a60065b	1827	\param [in] ticks Number of ticks between two interrupts.
kadonotakashi	0:8fdf9a60065b	1828	\return 0 Function succeeded.
kadonotakashi	0:8fdf9a60065b	1829	\return 1 Function failed.
kadonotakashi	0:8fdf9a60065b	1830	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
kadonotakashi	0:8fdf9a60065b	1831	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
kadonotakashi	0:8fdf9a60065b	1832	must contain a vendor-specific implementation of this function.
kadonotakashi	0:8fdf9a60065b	1833	*/
kadonotakashi	0:8fdf9a60065b	1834	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
kadonotakashi	0:8fdf9a60065b	1835	{
kadonotakashi	0:8fdf9a60065b	1836	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
kadonotakashi	0:8fdf9a60065b	1837	{
kadonotakashi	0:8fdf9a60065b	1838	return (1UL); /* Reload value impossible */
kadonotakashi	0:8fdf9a60065b	1839	}
kadonotakashi	0:8fdf9a60065b	1840
kadonotakashi	0:8fdf9a60065b	1841	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
kadonotakashi	0:8fdf9a60065b	1842	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
kadonotakashi	0:8fdf9a60065b	1843	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
kadonotakashi	0:8fdf9a60065b	1844	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
kadonotakashi	0:8fdf9a60065b	1845	SysTick_CTRL_TICKINT_Msk \|
kadonotakashi	0:8fdf9a60065b	1846	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
kadonotakashi	0:8fdf9a60065b	1847	return (0UL); /* Function successful */
kadonotakashi	0:8fdf9a60065b	1848	}
kadonotakashi	0:8fdf9a60065b	1849
kadonotakashi	0:8fdf9a60065b	1850	#endif
kadonotakashi	0:8fdf9a60065b	1851
kadonotakashi	0:8fdf9a60065b	1852	/@} end of CMSIS_Core_SysTickFunctions /
kadonotakashi	0:8fdf9a60065b	1853
kadonotakashi	0:8fdf9a60065b	1854
kadonotakashi	0:8fdf9a60065b	1855
kadonotakashi	0:8fdf9a60065b	1856	/* ##################################### Debug In/Output function ########################################### */
kadonotakashi	0:8fdf9a60065b	1857	/**
kadonotakashi	0:8fdf9a60065b	1858	\ingroup CMSIS_Core_FunctionInterface
kadonotakashi	0:8fdf9a60065b	1859	\defgroup CMSIS_core_DebugFunctions ITM Functions
kadonotakashi	0:8fdf9a60065b	1860	\brief Functions that access the ITM debug interface.
kadonotakashi	0:8fdf9a60065b	1861	@{
kadonotakashi	0:8fdf9a60065b	1862	*/
kadonotakashi	0:8fdf9a60065b	1863
kadonotakashi	0:8fdf9a60065b	1864	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
kadonotakashi	0:8fdf9a60065b	1865	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
kadonotakashi	0:8fdf9a60065b	1866
kadonotakashi	0:8fdf9a60065b	1867
kadonotakashi	0:8fdf9a60065b	1868	/**
kadonotakashi	0:8fdf9a60065b	1869	\brief ITM Send Character
kadonotakashi	0:8fdf9a60065b	1870	\details Transmits a character via the ITM channel 0, and
kadonotakashi	0:8fdf9a60065b	1871	\li Just returns when no debugger is connected that has booked the output.
kadonotakashi	0:8fdf9a60065b	1872	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
kadonotakashi	0:8fdf9a60065b	1873	\param [in] ch Character to transmit.
kadonotakashi	0:8fdf9a60065b	1874	\returns Character to transmit.
kadonotakashi	0:8fdf9a60065b	1875	*/
kadonotakashi	0:8fdf9a60065b	1876	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
kadonotakashi	0:8fdf9a60065b	1877	{
kadonotakashi	0:8fdf9a60065b	1878	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
kadonotakashi	0:8fdf9a60065b	1879	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
kadonotakashi	0:8fdf9a60065b	1880	{
kadonotakashi	0:8fdf9a60065b	1881	while (ITM->PORT[0U].u32 == 0UL)
kadonotakashi	0:8fdf9a60065b	1882	{
kadonotakashi	0:8fdf9a60065b	1883	__NOP();
kadonotakashi	0:8fdf9a60065b	1884	}
kadonotakashi	0:8fdf9a60065b	1885	ITM->PORT[0U].u8 = (uint8_t)ch;
kadonotakashi	0:8fdf9a60065b	1886	}
kadonotakashi	0:8fdf9a60065b	1887	return (ch);
kadonotakashi	0:8fdf9a60065b	1888	}
kadonotakashi	0:8fdf9a60065b	1889
kadonotakashi	0:8fdf9a60065b	1890
kadonotakashi	0:8fdf9a60065b	1891	/**
kadonotakashi	0:8fdf9a60065b	1892	\brief ITM Receive Character
kadonotakashi	0:8fdf9a60065b	1893	\details Inputs a character via the external variable \ref ITM_RxBuffer.
kadonotakashi	0:8fdf9a60065b	1894	\return Received character.
kadonotakashi	0:8fdf9a60065b	1895	\return -1 No character pending.
kadonotakashi	0:8fdf9a60065b	1896	*/
kadonotakashi	0:8fdf9a60065b	1897	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
kadonotakashi	0:8fdf9a60065b	1898	{
kadonotakashi	0:8fdf9a60065b	1899	int32_t ch = -1; /* no character available */
kadonotakashi	0:8fdf9a60065b	1900
kadonotakashi	0:8fdf9a60065b	1901	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
kadonotakashi	0:8fdf9a60065b	1902	{
kadonotakashi	0:8fdf9a60065b	1903	ch = ITM_RxBuffer;
kadonotakashi	0:8fdf9a60065b	1904	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
kadonotakashi	0:8fdf9a60065b	1905	}
kadonotakashi	0:8fdf9a60065b	1906
kadonotakashi	0:8fdf9a60065b	1907	return (ch);
kadonotakashi	0:8fdf9a60065b	1908	}
kadonotakashi	0:8fdf9a60065b	1909
kadonotakashi	0:8fdf9a60065b	1910
kadonotakashi	0:8fdf9a60065b	1911	/**
kadonotakashi	0:8fdf9a60065b	1912	\brief ITM Check Character
kadonotakashi	0:8fdf9a60065b	1913	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
kadonotakashi	0:8fdf9a60065b	1914	\return 0 No character available.
kadonotakashi	0:8fdf9a60065b	1915	\return 1 Character available.
kadonotakashi	0:8fdf9a60065b	1916	*/
kadonotakashi	0:8fdf9a60065b	1917	__STATIC_INLINE int32_t ITM_CheckChar (void)
kadonotakashi	0:8fdf9a60065b	1918	{
kadonotakashi	0:8fdf9a60065b	1919
kadonotakashi	0:8fdf9a60065b	1920	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
kadonotakashi	0:8fdf9a60065b	1921	{
kadonotakashi	0:8fdf9a60065b	1922	return (0); /* no character available */
kadonotakashi	0:8fdf9a60065b	1923	}
kadonotakashi	0:8fdf9a60065b	1924	else
kadonotakashi	0:8fdf9a60065b	1925	{
kadonotakashi	0:8fdf9a60065b	1926	return (1); /* character available */
kadonotakashi	0:8fdf9a60065b	1927	}
kadonotakashi	0:8fdf9a60065b	1928	}
kadonotakashi	0:8fdf9a60065b	1929
kadonotakashi	0:8fdf9a60065b	1930	/@} end of CMSIS_core_DebugFunctions /
kadonotakashi	0:8fdf9a60065b	1931
kadonotakashi	0:8fdf9a60065b	1932
kadonotakashi	0:8fdf9a60065b	1933
kadonotakashi	0:8fdf9a60065b	1934
kadonotakashi	0:8fdf9a60065b	1935	#ifdef __cplusplus
kadonotakashi	0:8fdf9a60065b	1936	}
kadonotakashi	0:8fdf9a60065b	1937	#endif
kadonotakashi	0:8fdf9a60065b	1938
kadonotakashi	0:8fdf9a60065b	1939	#endif /* __CORE_CM3_H_DEPENDANT */
kadonotakashi	0:8fdf9a60065b	1940
kadonotakashi	0:8fdf9a60065b	1941	#endif /* __CMSIS_GENERIC */

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Type:	Program
Mbed OS support:	Mbed OS
Created:	11 Oct 2018
Imports:	23
Forks:	0
Commits:	4
Dependents:	0
Dependencies:	1
Followers:	1

mbed-os/cmsis/TARGET_CORTEX_M/core_cm3.h@0:8fdf9a60065b, 2018-10-10 (annotated)

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