takashi kadono / Mbed OS Nucleo_446

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:
kadonotakashi
Date:
Wed Oct 10 00:33:53 2018 +0000
Revision:
0:8fdf9a60065b
how to make mbed librry

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /**************************************************************************//**
kadonotakashi 0:8fdf9a60065b 2 * @file cmsis_iccarm.h
kadonotakashi 0:8fdf9a60065b 3 * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
kadonotakashi 0:8fdf9a60065b 4 * @version V5.0.7
kadonotakashi 0:8fdf9a60065b 5 * @date 19. June 2018
kadonotakashi 0:8fdf9a60065b 6 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 7
kadonotakashi 0:8fdf9a60065b 8 //------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 9 //
kadonotakashi 0:8fdf9a60065b 10 // Copyright (c) 2017-2018 IAR Systems
kadonotakashi 0:8fdf9a60065b 11 //
kadonotakashi 0:8fdf9a60065b 12 // Licensed under the Apache License, Version 2.0 (the "License")
kadonotakashi 0:8fdf9a60065b 13 // you may not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 14 // You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 15 // http://www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 16 //
kadonotakashi 0:8fdf9a60065b 17 // Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 18 // distributed under the License is distributed on an "AS IS" BASIS,
kadonotakashi 0:8fdf9a60065b 19 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 20 // See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 21 // limitations under the License.
kadonotakashi 0:8fdf9a60065b 22 //
kadonotakashi 0:8fdf9a60065b 23 //------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 24
kadonotakashi 0:8fdf9a60065b 25
kadonotakashi 0:8fdf9a60065b 26 #ifndef __CMSIS_ICCARM_H__
kadonotakashi 0:8fdf9a60065b 27 #define __CMSIS_ICCARM_H__
kadonotakashi 0:8fdf9a60065b 28
kadonotakashi 0:8fdf9a60065b 29 #ifndef __ICCARM__
kadonotakashi 0:8fdf9a60065b 30 #error This file should only be compiled by ICCARM
kadonotakashi 0:8fdf9a60065b 31 #endif
kadonotakashi 0:8fdf9a60065b 32
kadonotakashi 0:8fdf9a60065b 33 #pragma system_include
kadonotakashi 0:8fdf9a60065b 34
kadonotakashi 0:8fdf9a60065b 35 #define __IAR_FT _Pragma("inline=forced") __intrinsic
kadonotakashi 0:8fdf9a60065b 36
kadonotakashi 0:8fdf9a60065b 37 #if (__VER__ >= 8000000)
kadonotakashi 0:8fdf9a60065b 38 #define __ICCARM_V8 1
kadonotakashi 0:8fdf9a60065b 39 #else
kadonotakashi 0:8fdf9a60065b 40 #define __ICCARM_V8 0
kadonotakashi 0:8fdf9a60065b 41 #endif
kadonotakashi 0:8fdf9a60065b 42
kadonotakashi 0:8fdf9a60065b 43 #ifndef __ALIGNED
kadonotakashi 0:8fdf9a60065b 44 #if __ICCARM_V8
kadonotakashi 0:8fdf9a60065b 45 #define __ALIGNED(x) __attribute__((aligned(x)))
kadonotakashi 0:8fdf9a60065b 46 #elif (__VER__ >= 7080000)
kadonotakashi 0:8fdf9a60065b 47 /* Needs IAR language extensions */
kadonotakashi 0:8fdf9a60065b 48 #define __ALIGNED(x) __attribute__((aligned(x)))
kadonotakashi 0:8fdf9a60065b 49 #else
kadonotakashi 0:8fdf9a60065b 50 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
kadonotakashi 0:8fdf9a60065b 51 #define __ALIGNED(x)
kadonotakashi 0:8fdf9a60065b 52 #endif
kadonotakashi 0:8fdf9a60065b 53 #endif
kadonotakashi 0:8fdf9a60065b 54
kadonotakashi 0:8fdf9a60065b 55
kadonotakashi 0:8fdf9a60065b 56 /* Define compiler macros for CPU architecture, used in CMSIS 5.
kadonotakashi 0:8fdf9a60065b 57 */
kadonotakashi 0:8fdf9a60065b 58 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
kadonotakashi 0:8fdf9a60065b 59 /* Macros already defined */
kadonotakashi 0:8fdf9a60065b 60 #else
kadonotakashi 0:8fdf9a60065b 61 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
kadonotakashi 0:8fdf9a60065b 62 #define __ARM_ARCH_8M_MAIN__ 1
kadonotakashi 0:8fdf9a60065b 63 #elif defined(__ARM8M_BASELINE__)
kadonotakashi 0:8fdf9a60065b 64 #define __ARM_ARCH_8M_BASE__ 1
kadonotakashi 0:8fdf9a60065b 65 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
kadonotakashi 0:8fdf9a60065b 66 #if __ARM_ARCH == 6
kadonotakashi 0:8fdf9a60065b 67 #define __ARM_ARCH_6M__ 1
kadonotakashi 0:8fdf9a60065b 68 #elif __ARM_ARCH == 7
kadonotakashi 0:8fdf9a60065b 69 #if __ARM_FEATURE_DSP
kadonotakashi 0:8fdf9a60065b 70 #define __ARM_ARCH_7EM__ 1
kadonotakashi 0:8fdf9a60065b 71 #else
kadonotakashi 0:8fdf9a60065b 72 #define __ARM_ARCH_7M__ 1
kadonotakashi 0:8fdf9a60065b 73 #endif
kadonotakashi 0:8fdf9a60065b 74 #endif /* __ARM_ARCH */
kadonotakashi 0:8fdf9a60065b 75 #endif /* __ARM_ARCH_PROFILE == 'M' */
kadonotakashi 0:8fdf9a60065b 76 #endif
kadonotakashi 0:8fdf9a60065b 77
kadonotakashi 0:8fdf9a60065b 78 /* Alternativ core deduction for older ICCARM's */
kadonotakashi 0:8fdf9a60065b 79 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
kadonotakashi 0:8fdf9a60065b 80 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
kadonotakashi 0:8fdf9a60065b 81 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
kadonotakashi 0:8fdf9a60065b 82 #define __ARM_ARCH_6M__ 1
kadonotakashi 0:8fdf9a60065b 83 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
kadonotakashi 0:8fdf9a60065b 84 #define __ARM_ARCH_7M__ 1
kadonotakashi 0:8fdf9a60065b 85 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
kadonotakashi 0:8fdf9a60065b 86 #define __ARM_ARCH_7EM__ 1
kadonotakashi 0:8fdf9a60065b 87 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
kadonotakashi 0:8fdf9a60065b 88 #define __ARM_ARCH_8M_BASE__ 1
kadonotakashi 0:8fdf9a60065b 89 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
kadonotakashi 0:8fdf9a60065b 90 #define __ARM_ARCH_8M_MAIN__ 1
kadonotakashi 0:8fdf9a60065b 91 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
kadonotakashi 0:8fdf9a60065b 92 #define __ARM_ARCH_8M_MAIN__ 1
kadonotakashi 0:8fdf9a60065b 93 #else
kadonotakashi 0:8fdf9a60065b 94 #error "Unknown target."
kadonotakashi 0:8fdf9a60065b 95 #endif
kadonotakashi 0:8fdf9a60065b 96 #endif
kadonotakashi 0:8fdf9a60065b 97
kadonotakashi 0:8fdf9a60065b 98
kadonotakashi 0:8fdf9a60065b 99
kadonotakashi 0:8fdf9a60065b 100 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
kadonotakashi 0:8fdf9a60065b 101 #define __IAR_M0_FAMILY 1
kadonotakashi 0:8fdf9a60065b 102 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
kadonotakashi 0:8fdf9a60065b 103 #define __IAR_M0_FAMILY 1
kadonotakashi 0:8fdf9a60065b 104 #else
kadonotakashi 0:8fdf9a60065b 105 #define __IAR_M0_FAMILY 0
kadonotakashi 0:8fdf9a60065b 106 #endif
kadonotakashi 0:8fdf9a60065b 107
kadonotakashi 0:8fdf9a60065b 108
kadonotakashi 0:8fdf9a60065b 109 #ifndef __ASM
kadonotakashi 0:8fdf9a60065b 110 #define __ASM __asm
kadonotakashi 0:8fdf9a60065b 111 #endif
kadonotakashi 0:8fdf9a60065b 112
kadonotakashi 0:8fdf9a60065b 113 #ifndef __INLINE
kadonotakashi 0:8fdf9a60065b 114 #define __INLINE inline
kadonotakashi 0:8fdf9a60065b 115 #endif
kadonotakashi 0:8fdf9a60065b 116
kadonotakashi 0:8fdf9a60065b 117 #ifndef __NO_RETURN
kadonotakashi 0:8fdf9a60065b 118 #if __ICCARM_V8
kadonotakashi 0:8fdf9a60065b 119 #define __NO_RETURN __attribute__((__noreturn__))
kadonotakashi 0:8fdf9a60065b 120 #else
kadonotakashi 0:8fdf9a60065b 121 #define __NO_RETURN _Pragma("object_attribute=__noreturn")
kadonotakashi 0:8fdf9a60065b 122 #endif
kadonotakashi 0:8fdf9a60065b 123 #endif
kadonotakashi 0:8fdf9a60065b 124
kadonotakashi 0:8fdf9a60065b 125 #ifndef __PACKED
kadonotakashi 0:8fdf9a60065b 126 #if __ICCARM_V8
kadonotakashi 0:8fdf9a60065b 127 #define __PACKED __attribute__((packed, aligned(1)))
kadonotakashi 0:8fdf9a60065b 128 #else
kadonotakashi 0:8fdf9a60065b 129 /* Needs IAR language extensions */
kadonotakashi 0:8fdf9a60065b 130 #define __PACKED __packed
kadonotakashi 0:8fdf9a60065b 131 #endif
kadonotakashi 0:8fdf9a60065b 132 #endif
kadonotakashi 0:8fdf9a60065b 133
kadonotakashi 0:8fdf9a60065b 134 #ifndef __PACKED_STRUCT
kadonotakashi 0:8fdf9a60065b 135 #if __ICCARM_V8
kadonotakashi 0:8fdf9a60065b 136 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
kadonotakashi 0:8fdf9a60065b 137 #else
kadonotakashi 0:8fdf9a60065b 138 /* Needs IAR language extensions */
kadonotakashi 0:8fdf9a60065b 139 #define __PACKED_STRUCT __packed struct
kadonotakashi 0:8fdf9a60065b 140 #endif
kadonotakashi 0:8fdf9a60065b 141 #endif
kadonotakashi 0:8fdf9a60065b 142
kadonotakashi 0:8fdf9a60065b 143 #ifndef __PACKED_UNION
kadonotakashi 0:8fdf9a60065b 144 #if __ICCARM_V8
kadonotakashi 0:8fdf9a60065b 145 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
kadonotakashi 0:8fdf9a60065b 146 #else
kadonotakashi 0:8fdf9a60065b 147 /* Needs IAR language extensions */
kadonotakashi 0:8fdf9a60065b 148 #define __PACKED_UNION __packed union
kadonotakashi 0:8fdf9a60065b 149 #endif
kadonotakashi 0:8fdf9a60065b 150 #endif
kadonotakashi 0:8fdf9a60065b 151
kadonotakashi 0:8fdf9a60065b 152 #ifndef __RESTRICT
kadonotakashi 0:8fdf9a60065b 153 #define __RESTRICT restrict
kadonotakashi 0:8fdf9a60065b 154 #endif
kadonotakashi 0:8fdf9a60065b 155
kadonotakashi 0:8fdf9a60065b 156 #ifndef __STATIC_INLINE
kadonotakashi 0:8fdf9a60065b 157 #define __STATIC_INLINE static inline
kadonotakashi 0:8fdf9a60065b 158 #endif
kadonotakashi 0:8fdf9a60065b 159
kadonotakashi 0:8fdf9a60065b 160 #ifndef __FORCEINLINE
kadonotakashi 0:8fdf9a60065b 161 #define __FORCEINLINE _Pragma("inline=forced")
kadonotakashi 0:8fdf9a60065b 162 #endif
kadonotakashi 0:8fdf9a60065b 163
kadonotakashi 0:8fdf9a60065b 164 #ifndef __STATIC_FORCEINLINE
kadonotakashi 0:8fdf9a60065b 165 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
kadonotakashi 0:8fdf9a60065b 166 #endif
kadonotakashi 0:8fdf9a60065b 167
kadonotakashi 0:8fdf9a60065b 168 #ifndef __UNALIGNED_UINT16_READ
kadonotakashi 0:8fdf9a60065b 169 #pragma language=save
kadonotakashi 0:8fdf9a60065b 170 #pragma language=extended
kadonotakashi 0:8fdf9a60065b 171 __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
kadonotakashi 0:8fdf9a60065b 172 {
kadonotakashi 0:8fdf9a60065b 173 return *(__packed uint16_t*)(ptr);
kadonotakashi 0:8fdf9a60065b 174 }
kadonotakashi 0:8fdf9a60065b 175 #pragma language=restore
kadonotakashi 0:8fdf9a60065b 176 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
kadonotakashi 0:8fdf9a60065b 177 #endif
kadonotakashi 0:8fdf9a60065b 178
kadonotakashi 0:8fdf9a60065b 179
kadonotakashi 0:8fdf9a60065b 180 #ifndef __UNALIGNED_UINT16_WRITE
kadonotakashi 0:8fdf9a60065b 181 #pragma language=save
kadonotakashi 0:8fdf9a60065b 182 #pragma language=extended
kadonotakashi 0:8fdf9a60065b 183 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
kadonotakashi 0:8fdf9a60065b 184 {
kadonotakashi 0:8fdf9a60065b 185 *(__packed uint16_t*)(ptr) = val;;
kadonotakashi 0:8fdf9a60065b 186 }
kadonotakashi 0:8fdf9a60065b 187 #pragma language=restore
kadonotakashi 0:8fdf9a60065b 188 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
kadonotakashi 0:8fdf9a60065b 189 #endif
kadonotakashi 0:8fdf9a60065b 190
kadonotakashi 0:8fdf9a60065b 191 #ifndef __UNALIGNED_UINT32_READ
kadonotakashi 0:8fdf9a60065b 192 #pragma language=save
kadonotakashi 0:8fdf9a60065b 193 #pragma language=extended
kadonotakashi 0:8fdf9a60065b 194 __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
kadonotakashi 0:8fdf9a60065b 195 {
kadonotakashi 0:8fdf9a60065b 196 return *(__packed uint32_t*)(ptr);
kadonotakashi 0:8fdf9a60065b 197 }
kadonotakashi 0:8fdf9a60065b 198 #pragma language=restore
kadonotakashi 0:8fdf9a60065b 199 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
kadonotakashi 0:8fdf9a60065b 200 #endif
kadonotakashi 0:8fdf9a60065b 201
kadonotakashi 0:8fdf9a60065b 202 #ifndef __UNALIGNED_UINT32_WRITE
kadonotakashi 0:8fdf9a60065b 203 #pragma language=save
kadonotakashi 0:8fdf9a60065b 204 #pragma language=extended
kadonotakashi 0:8fdf9a60065b 205 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
kadonotakashi 0:8fdf9a60065b 206 {
kadonotakashi 0:8fdf9a60065b 207 *(__packed uint32_t*)(ptr) = val;;
kadonotakashi 0:8fdf9a60065b 208 }
kadonotakashi 0:8fdf9a60065b 209 #pragma language=restore
kadonotakashi 0:8fdf9a60065b 210 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
kadonotakashi 0:8fdf9a60065b 211 #endif
kadonotakashi 0:8fdf9a60065b 212
kadonotakashi 0:8fdf9a60065b 213 #ifndef __UNALIGNED_UINT32 /* deprecated */
kadonotakashi 0:8fdf9a60065b 214 #pragma language=save
kadonotakashi 0:8fdf9a60065b 215 #pragma language=extended
kadonotakashi 0:8fdf9a60065b 216 __packed struct __iar_u32 { uint32_t v; };
kadonotakashi 0:8fdf9a60065b 217 #pragma language=restore
kadonotakashi 0:8fdf9a60065b 218 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
kadonotakashi 0:8fdf9a60065b 219 #endif
kadonotakashi 0:8fdf9a60065b 220
kadonotakashi 0:8fdf9a60065b 221 #ifndef __USED
kadonotakashi 0:8fdf9a60065b 222 #if __ICCARM_V8
kadonotakashi 0:8fdf9a60065b 223 #define __USED __attribute__((used))
kadonotakashi 0:8fdf9a60065b 224 #else
kadonotakashi 0:8fdf9a60065b 225 #define __USED _Pragma("__root")
kadonotakashi 0:8fdf9a60065b 226 #endif
kadonotakashi 0:8fdf9a60065b 227 #endif
kadonotakashi 0:8fdf9a60065b 228
kadonotakashi 0:8fdf9a60065b 229 #ifndef __WEAK
kadonotakashi 0:8fdf9a60065b 230 #if __ICCARM_V8
kadonotakashi 0:8fdf9a60065b 231 #define __WEAK __attribute__((weak))
kadonotakashi 0:8fdf9a60065b 232 #else
kadonotakashi 0:8fdf9a60065b 233 #define __WEAK _Pragma("__weak")
kadonotakashi 0:8fdf9a60065b 234 #endif
kadonotakashi 0:8fdf9a60065b 235 #endif
kadonotakashi 0:8fdf9a60065b 236
kadonotakashi 0:8fdf9a60065b 237
kadonotakashi 0:8fdf9a60065b 238 #ifndef __ICCARM_INTRINSICS_VERSION__
kadonotakashi 0:8fdf9a60065b 239 #define __ICCARM_INTRINSICS_VERSION__ 0
kadonotakashi 0:8fdf9a60065b 240 #endif
kadonotakashi 0:8fdf9a60065b 241
kadonotakashi 0:8fdf9a60065b 242 #if __ICCARM_INTRINSICS_VERSION__ == 2
kadonotakashi 0:8fdf9a60065b 243
kadonotakashi 0:8fdf9a60065b 244 #if defined(__CLZ)
kadonotakashi 0:8fdf9a60065b 245 #undef __CLZ
kadonotakashi 0:8fdf9a60065b 246 #endif
kadonotakashi 0:8fdf9a60065b 247 #if defined(__REVSH)
kadonotakashi 0:8fdf9a60065b 248 #undef __REVSH
kadonotakashi 0:8fdf9a60065b 249 #endif
kadonotakashi 0:8fdf9a60065b 250 #if defined(__RBIT)
kadonotakashi 0:8fdf9a60065b 251 #undef __RBIT
kadonotakashi 0:8fdf9a60065b 252 #endif
kadonotakashi 0:8fdf9a60065b 253 #if defined(__SSAT)
kadonotakashi 0:8fdf9a60065b 254 #undef __SSAT
kadonotakashi 0:8fdf9a60065b 255 #endif
kadonotakashi 0:8fdf9a60065b 256 #if defined(__USAT)
kadonotakashi 0:8fdf9a60065b 257 #undef __USAT
kadonotakashi 0:8fdf9a60065b 258 #endif
kadonotakashi 0:8fdf9a60065b 259
kadonotakashi 0:8fdf9a60065b 260 #include "iccarm_builtin.h"
kadonotakashi 0:8fdf9a60065b 261
kadonotakashi 0:8fdf9a60065b 262 #define __disable_fault_irq __iar_builtin_disable_fiq
kadonotakashi 0:8fdf9a60065b 263 #define __disable_irq __iar_builtin_disable_interrupt
kadonotakashi 0:8fdf9a60065b 264 #define __enable_fault_irq __iar_builtin_enable_fiq
kadonotakashi 0:8fdf9a60065b 265 #define __enable_irq __iar_builtin_enable_interrupt
kadonotakashi 0:8fdf9a60065b 266 #define __arm_rsr __iar_builtin_rsr
kadonotakashi 0:8fdf9a60065b 267 #define __arm_wsr __iar_builtin_wsr
kadonotakashi 0:8fdf9a60065b 268
kadonotakashi 0:8fdf9a60065b 269
kadonotakashi 0:8fdf9a60065b 270 #define __get_APSR() (__arm_rsr("APSR"))
kadonotakashi 0:8fdf9a60065b 271 #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
kadonotakashi 0:8fdf9a60065b 272 #define __get_CONTROL() (__arm_rsr("CONTROL"))
kadonotakashi 0:8fdf9a60065b 273 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
kadonotakashi 0:8fdf9a60065b 274
kadonotakashi 0:8fdf9a60065b 275 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
kadonotakashi 0:8fdf9a60065b 276 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
kadonotakashi 0:8fdf9a60065b 277 #define __get_FPSCR() (__arm_rsr("FPSCR"))
kadonotakashi 0:8fdf9a60065b 278 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
kadonotakashi 0:8fdf9a60065b 279 #else
kadonotakashi 0:8fdf9a60065b 280 #define __get_FPSCR() ( 0 )
kadonotakashi 0:8fdf9a60065b 281 #define __set_FPSCR(VALUE) ((void)VALUE)
kadonotakashi 0:8fdf9a60065b 282 #endif
kadonotakashi 0:8fdf9a60065b 283
kadonotakashi 0:8fdf9a60065b 284 #define __get_IPSR() (__arm_rsr("IPSR"))
kadonotakashi 0:8fdf9a60065b 285 #define __get_MSP() (__arm_rsr("MSP"))
kadonotakashi 0:8fdf9a60065b 286 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
kadonotakashi 0:8fdf9a60065b 287 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
kadonotakashi 0:8fdf9a60065b 288 // without main extensions, the non-secure MSPLIM is RAZ/WI
kadonotakashi 0:8fdf9a60065b 289 #define __get_MSPLIM() (0U)
kadonotakashi 0:8fdf9a60065b 290 #else
kadonotakashi 0:8fdf9a60065b 291 #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
kadonotakashi 0:8fdf9a60065b 292 #endif
kadonotakashi 0:8fdf9a60065b 293 #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
kadonotakashi 0:8fdf9a60065b 294 #define __get_PSP() (__arm_rsr("PSP"))
kadonotakashi 0:8fdf9a60065b 295
kadonotakashi 0:8fdf9a60065b 296 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
kadonotakashi 0:8fdf9a60065b 297 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
kadonotakashi 0:8fdf9a60065b 298 // without main extensions, the non-secure PSPLIM is RAZ/WI
kadonotakashi 0:8fdf9a60065b 299 #define __get_PSPLIM() (0U)
kadonotakashi 0:8fdf9a60065b 300 #else
kadonotakashi 0:8fdf9a60065b 301 #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
kadonotakashi 0:8fdf9a60065b 302 #endif
kadonotakashi 0:8fdf9a60065b 303
kadonotakashi 0:8fdf9a60065b 304 #define __get_xPSR() (__arm_rsr("xPSR"))
kadonotakashi 0:8fdf9a60065b 305
kadonotakashi 0:8fdf9a60065b 306 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
kadonotakashi 0:8fdf9a60065b 307 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
kadonotakashi 0:8fdf9a60065b 308 #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
kadonotakashi 0:8fdf9a60065b 309 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
kadonotakashi 0:8fdf9a60065b 310 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
kadonotakashi 0:8fdf9a60065b 311
kadonotakashi 0:8fdf9a60065b 312 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
kadonotakashi 0:8fdf9a60065b 313 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
kadonotakashi 0:8fdf9a60065b 314 // without main extensions, the non-secure MSPLIM is RAZ/WI
kadonotakashi 0:8fdf9a60065b 315 #define __set_MSPLIM(VALUE) ((void)(VALUE))
kadonotakashi 0:8fdf9a60065b 316 #else
kadonotakashi 0:8fdf9a60065b 317 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
kadonotakashi 0:8fdf9a60065b 318 #endif
kadonotakashi 0:8fdf9a60065b 319 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
kadonotakashi 0:8fdf9a60065b 320 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
kadonotakashi 0:8fdf9a60065b 321 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
kadonotakashi 0:8fdf9a60065b 322 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
kadonotakashi 0:8fdf9a60065b 323 // without main extensions, the non-secure PSPLIM is RAZ/WI
kadonotakashi 0:8fdf9a60065b 324 #define __set_PSPLIM(VALUE) ((void)(VALUE))
kadonotakashi 0:8fdf9a60065b 325 #else
kadonotakashi 0:8fdf9a60065b 326 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
kadonotakashi 0:8fdf9a60065b 327 #endif
kadonotakashi 0:8fdf9a60065b 328
kadonotakashi 0:8fdf9a60065b 329 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
kadonotakashi 0:8fdf9a60065b 330 #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
kadonotakashi 0:8fdf9a60065b 331 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
kadonotakashi 0:8fdf9a60065b 332 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
kadonotakashi 0:8fdf9a60065b 333 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
kadonotakashi 0:8fdf9a60065b 334 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
kadonotakashi 0:8fdf9a60065b 335 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
kadonotakashi 0:8fdf9a60065b 336 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
kadonotakashi 0:8fdf9a60065b 337 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
kadonotakashi 0:8fdf9a60065b 338 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
kadonotakashi 0:8fdf9a60065b 339 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
kadonotakashi 0:8fdf9a60065b 340 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
kadonotakashi 0:8fdf9a60065b 341 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
kadonotakashi 0:8fdf9a60065b 342 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
kadonotakashi 0:8fdf9a60065b 343
kadonotakashi 0:8fdf9a60065b 344 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
kadonotakashi 0:8fdf9a60065b 345 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
kadonotakashi 0:8fdf9a60065b 346 // without main extensions, the non-secure PSPLIM is RAZ/WI
kadonotakashi 0:8fdf9a60065b 347 #define __TZ_get_PSPLIM_NS() (0U)
kadonotakashi 0:8fdf9a60065b 348 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
kadonotakashi 0:8fdf9a60065b 349 #else
kadonotakashi 0:8fdf9a60065b 350 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
kadonotakashi 0:8fdf9a60065b 351 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
kadonotakashi 0:8fdf9a60065b 352 #endif
kadonotakashi 0:8fdf9a60065b 353
kadonotakashi 0:8fdf9a60065b 354 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
kadonotakashi 0:8fdf9a60065b 355 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
kadonotakashi 0:8fdf9a60065b 356
kadonotakashi 0:8fdf9a60065b 357 #define __NOP __iar_builtin_no_operation
kadonotakashi 0:8fdf9a60065b 358
kadonotakashi 0:8fdf9a60065b 359 #define __CLZ __iar_builtin_CLZ
kadonotakashi 0:8fdf9a60065b 360 #define __CLREX __iar_builtin_CLREX
kadonotakashi 0:8fdf9a60065b 361
kadonotakashi 0:8fdf9a60065b 362 #define __DMB __iar_builtin_DMB
kadonotakashi 0:8fdf9a60065b 363 #define __DSB __iar_builtin_DSB
kadonotakashi 0:8fdf9a60065b 364 #define __ISB __iar_builtin_ISB
kadonotakashi 0:8fdf9a60065b 365
kadonotakashi 0:8fdf9a60065b 366 #define __LDREXB __iar_builtin_LDREXB
kadonotakashi 0:8fdf9a60065b 367 #define __LDREXH __iar_builtin_LDREXH
kadonotakashi 0:8fdf9a60065b 368 #define __LDREXW __iar_builtin_LDREX
kadonotakashi 0:8fdf9a60065b 369
kadonotakashi 0:8fdf9a60065b 370 #define __RBIT __iar_builtin_RBIT
kadonotakashi 0:8fdf9a60065b 371 #define __REV __iar_builtin_REV
kadonotakashi 0:8fdf9a60065b 372 #define __REV16 __iar_builtin_REV16
kadonotakashi 0:8fdf9a60065b 373
kadonotakashi 0:8fdf9a60065b 374 __IAR_FT int16_t __REVSH(int16_t val)
kadonotakashi 0:8fdf9a60065b 375 {
kadonotakashi 0:8fdf9a60065b 376 return (int16_t) __iar_builtin_REVSH(val);
kadonotakashi 0:8fdf9a60065b 377 }
kadonotakashi 0:8fdf9a60065b 378
kadonotakashi 0:8fdf9a60065b 379 #define __ROR __iar_builtin_ROR
kadonotakashi 0:8fdf9a60065b 380 #define __RRX __iar_builtin_RRX
kadonotakashi 0:8fdf9a60065b 381
kadonotakashi 0:8fdf9a60065b 382 #define __SEV __iar_builtin_SEV
kadonotakashi 0:8fdf9a60065b 383
kadonotakashi 0:8fdf9a60065b 384 #if !__IAR_M0_FAMILY
kadonotakashi 0:8fdf9a60065b 385 #define __SSAT __iar_builtin_SSAT
kadonotakashi 0:8fdf9a60065b 386 #endif
kadonotakashi 0:8fdf9a60065b 387
kadonotakashi 0:8fdf9a60065b 388 #define __STREXB __iar_builtin_STREXB
kadonotakashi 0:8fdf9a60065b 389 #define __STREXH __iar_builtin_STREXH
kadonotakashi 0:8fdf9a60065b 390 #define __STREXW __iar_builtin_STREX
kadonotakashi 0:8fdf9a60065b 391
kadonotakashi 0:8fdf9a60065b 392 #if !__IAR_M0_FAMILY
kadonotakashi 0:8fdf9a60065b 393 #define __USAT __iar_builtin_USAT
kadonotakashi 0:8fdf9a60065b 394 #endif
kadonotakashi 0:8fdf9a60065b 395
kadonotakashi 0:8fdf9a60065b 396 #define __WFE __iar_builtin_WFE
kadonotakashi 0:8fdf9a60065b 397 #define __WFI __iar_builtin_WFI
kadonotakashi 0:8fdf9a60065b 398
kadonotakashi 0:8fdf9a60065b 399 #if __ARM_MEDIA__
kadonotakashi 0:8fdf9a60065b 400 #define __SADD8 __iar_builtin_SADD8
kadonotakashi 0:8fdf9a60065b 401 #define __QADD8 __iar_builtin_QADD8
kadonotakashi 0:8fdf9a60065b 402 #define __SHADD8 __iar_builtin_SHADD8
kadonotakashi 0:8fdf9a60065b 403 #define __UADD8 __iar_builtin_UADD8
kadonotakashi 0:8fdf9a60065b 404 #define __UQADD8 __iar_builtin_UQADD8
kadonotakashi 0:8fdf9a60065b 405 #define __UHADD8 __iar_builtin_UHADD8
kadonotakashi 0:8fdf9a60065b 406 #define __SSUB8 __iar_builtin_SSUB8
kadonotakashi 0:8fdf9a60065b 407 #define __QSUB8 __iar_builtin_QSUB8
kadonotakashi 0:8fdf9a60065b 408 #define __SHSUB8 __iar_builtin_SHSUB8
kadonotakashi 0:8fdf9a60065b 409 #define __USUB8 __iar_builtin_USUB8
kadonotakashi 0:8fdf9a60065b 410 #define __UQSUB8 __iar_builtin_UQSUB8
kadonotakashi 0:8fdf9a60065b 411 #define __UHSUB8 __iar_builtin_UHSUB8
kadonotakashi 0:8fdf9a60065b 412 #define __SADD16 __iar_builtin_SADD16
kadonotakashi 0:8fdf9a60065b 413 #define __QADD16 __iar_builtin_QADD16
kadonotakashi 0:8fdf9a60065b 414 #define __SHADD16 __iar_builtin_SHADD16
kadonotakashi 0:8fdf9a60065b 415 #define __UADD16 __iar_builtin_UADD16
kadonotakashi 0:8fdf9a60065b 416 #define __UQADD16 __iar_builtin_UQADD16
kadonotakashi 0:8fdf9a60065b 417 #define __UHADD16 __iar_builtin_UHADD16
kadonotakashi 0:8fdf9a60065b 418 #define __SSUB16 __iar_builtin_SSUB16
kadonotakashi 0:8fdf9a60065b 419 #define __QSUB16 __iar_builtin_QSUB16
kadonotakashi 0:8fdf9a60065b 420 #define __SHSUB16 __iar_builtin_SHSUB16
kadonotakashi 0:8fdf9a60065b 421 #define __USUB16 __iar_builtin_USUB16
kadonotakashi 0:8fdf9a60065b 422 #define __UQSUB16 __iar_builtin_UQSUB16
kadonotakashi 0:8fdf9a60065b 423 #define __UHSUB16 __iar_builtin_UHSUB16
kadonotakashi 0:8fdf9a60065b 424 #define __SASX __iar_builtin_SASX
kadonotakashi 0:8fdf9a60065b 425 #define __QASX __iar_builtin_QASX
kadonotakashi 0:8fdf9a60065b 426 #define __SHASX __iar_builtin_SHASX
kadonotakashi 0:8fdf9a60065b 427 #define __UASX __iar_builtin_UASX
kadonotakashi 0:8fdf9a60065b 428 #define __UQASX __iar_builtin_UQASX
kadonotakashi 0:8fdf9a60065b 429 #define __UHASX __iar_builtin_UHASX
kadonotakashi 0:8fdf9a60065b 430 #define __SSAX __iar_builtin_SSAX
kadonotakashi 0:8fdf9a60065b 431 #define __QSAX __iar_builtin_QSAX
kadonotakashi 0:8fdf9a60065b 432 #define __SHSAX __iar_builtin_SHSAX
kadonotakashi 0:8fdf9a60065b 433 #define __USAX __iar_builtin_USAX
kadonotakashi 0:8fdf9a60065b 434 #define __UQSAX __iar_builtin_UQSAX
kadonotakashi 0:8fdf9a60065b 435 #define __UHSAX __iar_builtin_UHSAX
kadonotakashi 0:8fdf9a60065b 436 #define __USAD8 __iar_builtin_USAD8
kadonotakashi 0:8fdf9a60065b 437 #define __USADA8 __iar_builtin_USADA8
kadonotakashi 0:8fdf9a60065b 438 #define __SSAT16 __iar_builtin_SSAT16
kadonotakashi 0:8fdf9a60065b 439 #define __USAT16 __iar_builtin_USAT16
kadonotakashi 0:8fdf9a60065b 440 #define __UXTB16 __iar_builtin_UXTB16
kadonotakashi 0:8fdf9a60065b 441 #define __UXTAB16 __iar_builtin_UXTAB16
kadonotakashi 0:8fdf9a60065b 442 #define __SXTB16 __iar_builtin_SXTB16
kadonotakashi 0:8fdf9a60065b 443 #define __SXTAB16 __iar_builtin_SXTAB16
kadonotakashi 0:8fdf9a60065b 444 #define __SMUAD __iar_builtin_SMUAD
kadonotakashi 0:8fdf9a60065b 445 #define __SMUADX __iar_builtin_SMUADX
kadonotakashi 0:8fdf9a60065b 446 #define __SMMLA __iar_builtin_SMMLA
kadonotakashi 0:8fdf9a60065b 447 #define __SMLAD __iar_builtin_SMLAD
kadonotakashi 0:8fdf9a60065b 448 #define __SMLADX __iar_builtin_SMLADX
kadonotakashi 0:8fdf9a60065b 449 #define __SMLALD __iar_builtin_SMLALD
kadonotakashi 0:8fdf9a60065b 450 #define __SMLALDX __iar_builtin_SMLALDX
kadonotakashi 0:8fdf9a60065b 451 #define __SMUSD __iar_builtin_SMUSD
kadonotakashi 0:8fdf9a60065b 452 #define __SMUSDX __iar_builtin_SMUSDX
kadonotakashi 0:8fdf9a60065b 453 #define __SMLSD __iar_builtin_SMLSD
kadonotakashi 0:8fdf9a60065b 454 #define __SMLSDX __iar_builtin_SMLSDX
kadonotakashi 0:8fdf9a60065b 455 #define __SMLSLD __iar_builtin_SMLSLD
kadonotakashi 0:8fdf9a60065b 456 #define __SMLSLDX __iar_builtin_SMLSLDX
kadonotakashi 0:8fdf9a60065b 457 #define __SEL __iar_builtin_SEL
kadonotakashi 0:8fdf9a60065b 458 #define __QADD __iar_builtin_QADD
kadonotakashi 0:8fdf9a60065b 459 #define __QSUB __iar_builtin_QSUB
kadonotakashi 0:8fdf9a60065b 460 #define __PKHBT __iar_builtin_PKHBT
kadonotakashi 0:8fdf9a60065b 461 #define __PKHTB __iar_builtin_PKHTB
kadonotakashi 0:8fdf9a60065b 462 #endif
kadonotakashi 0:8fdf9a60065b 463
kadonotakashi 0:8fdf9a60065b 464 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
kadonotakashi 0:8fdf9a60065b 465
kadonotakashi 0:8fdf9a60065b 466 #if __IAR_M0_FAMILY
kadonotakashi 0:8fdf9a60065b 467 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
kadonotakashi 0:8fdf9a60065b 468 #define __CLZ __cmsis_iar_clz_not_active
kadonotakashi 0:8fdf9a60065b 469 #define __SSAT __cmsis_iar_ssat_not_active
kadonotakashi 0:8fdf9a60065b 470 #define __USAT __cmsis_iar_usat_not_active
kadonotakashi 0:8fdf9a60065b 471 #define __RBIT __cmsis_iar_rbit_not_active
kadonotakashi 0:8fdf9a60065b 472 #define __get_APSR __cmsis_iar_get_APSR_not_active
kadonotakashi 0:8fdf9a60065b 473 #endif
kadonotakashi 0:8fdf9a60065b 474
kadonotakashi 0:8fdf9a60065b 475
kadonotakashi 0:8fdf9a60065b 476 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
kadonotakashi 0:8fdf9a60065b 477 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
kadonotakashi 0:8fdf9a60065b 478 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
kadonotakashi 0:8fdf9a60065b 479 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
kadonotakashi 0:8fdf9a60065b 480 #endif
kadonotakashi 0:8fdf9a60065b 481
kadonotakashi 0:8fdf9a60065b 482 #ifdef __INTRINSICS_INCLUDED
kadonotakashi 0:8fdf9a60065b 483 #error intrinsics.h is already included previously!
kadonotakashi 0:8fdf9a60065b 484 #endif
kadonotakashi 0:8fdf9a60065b 485
kadonotakashi 0:8fdf9a60065b 486 #include <intrinsics.h>
kadonotakashi 0:8fdf9a60065b 487
kadonotakashi 0:8fdf9a60065b 488 #if __IAR_M0_FAMILY
kadonotakashi 0:8fdf9a60065b 489 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
kadonotakashi 0:8fdf9a60065b 490 #undef __CLZ
kadonotakashi 0:8fdf9a60065b 491 #undef __SSAT
kadonotakashi 0:8fdf9a60065b 492 #undef __USAT
kadonotakashi 0:8fdf9a60065b 493 #undef __RBIT
kadonotakashi 0:8fdf9a60065b 494 #undef __get_APSR
kadonotakashi 0:8fdf9a60065b 495
kadonotakashi 0:8fdf9a60065b 496 __STATIC_INLINE uint8_t __CLZ(uint32_t data)
kadonotakashi 0:8fdf9a60065b 497 {
kadonotakashi 0:8fdf9a60065b 498 if (data == 0U) { return 32U; }
kadonotakashi 0:8fdf9a60065b 499
kadonotakashi 0:8fdf9a60065b 500 uint32_t count = 0U;
kadonotakashi 0:8fdf9a60065b 501 uint32_t mask = 0x80000000U;
kadonotakashi 0:8fdf9a60065b 502
kadonotakashi 0:8fdf9a60065b 503 while ((data & mask) == 0U)
kadonotakashi 0:8fdf9a60065b 504 {
kadonotakashi 0:8fdf9a60065b 505 count += 1U;
kadonotakashi 0:8fdf9a60065b 506 mask = mask >> 1U;
kadonotakashi 0:8fdf9a60065b 507 }
kadonotakashi 0:8fdf9a60065b 508 return count;
kadonotakashi 0:8fdf9a60065b 509 }
kadonotakashi 0:8fdf9a60065b 510
kadonotakashi 0:8fdf9a60065b 511 __STATIC_INLINE uint32_t __RBIT(uint32_t v)
kadonotakashi 0:8fdf9a60065b 512 {
kadonotakashi 0:8fdf9a60065b 513 uint8_t sc = 31U;
kadonotakashi 0:8fdf9a60065b 514 uint32_t r = v;
kadonotakashi 0:8fdf9a60065b 515 for (v >>= 1U; v; v >>= 1U)
kadonotakashi 0:8fdf9a60065b 516 {
kadonotakashi 0:8fdf9a60065b 517 r <<= 1U;
kadonotakashi 0:8fdf9a60065b 518 r |= v & 1U;
kadonotakashi 0:8fdf9a60065b 519 sc--;
kadonotakashi 0:8fdf9a60065b 520 }
kadonotakashi 0:8fdf9a60065b 521 return (r << sc);
kadonotakashi 0:8fdf9a60065b 522 }
kadonotakashi 0:8fdf9a60065b 523
kadonotakashi 0:8fdf9a60065b 524 __STATIC_INLINE uint32_t __get_APSR(void)
kadonotakashi 0:8fdf9a60065b 525 {
kadonotakashi 0:8fdf9a60065b 526 uint32_t res;
kadonotakashi 0:8fdf9a60065b 527 __asm("MRS %0,APSR" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 528 return res;
kadonotakashi 0:8fdf9a60065b 529 }
kadonotakashi 0:8fdf9a60065b 530
kadonotakashi 0:8fdf9a60065b 531 #endif
kadonotakashi 0:8fdf9a60065b 532
kadonotakashi 0:8fdf9a60065b 533 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
kadonotakashi 0:8fdf9a60065b 534 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
kadonotakashi 0:8fdf9a60065b 535 #undef __get_FPSCR
kadonotakashi 0:8fdf9a60065b 536 #undef __set_FPSCR
kadonotakashi 0:8fdf9a60065b 537 #define __get_FPSCR() (0)
kadonotakashi 0:8fdf9a60065b 538 #define __set_FPSCR(VALUE) ((void)VALUE)
kadonotakashi 0:8fdf9a60065b 539 #endif
kadonotakashi 0:8fdf9a60065b 540
kadonotakashi 0:8fdf9a60065b 541 #pragma diag_suppress=Pe940
kadonotakashi 0:8fdf9a60065b 542 #pragma diag_suppress=Pe177
kadonotakashi 0:8fdf9a60065b 543
kadonotakashi 0:8fdf9a60065b 544 #define __enable_irq __enable_interrupt
kadonotakashi 0:8fdf9a60065b 545 #define __disable_irq __disable_interrupt
kadonotakashi 0:8fdf9a60065b 546 #define __NOP __no_operation
kadonotakashi 0:8fdf9a60065b 547
kadonotakashi 0:8fdf9a60065b 548 #define __get_xPSR __get_PSR
kadonotakashi 0:8fdf9a60065b 549
kadonotakashi 0:8fdf9a60065b 550 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
kadonotakashi 0:8fdf9a60065b 551
kadonotakashi 0:8fdf9a60065b 552 __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
kadonotakashi 0:8fdf9a60065b 553 {
kadonotakashi 0:8fdf9a60065b 554 return __LDREX((unsigned long *)ptr);
kadonotakashi 0:8fdf9a60065b 555 }
kadonotakashi 0:8fdf9a60065b 556
kadonotakashi 0:8fdf9a60065b 557 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
kadonotakashi 0:8fdf9a60065b 558 {
kadonotakashi 0:8fdf9a60065b 559 return __STREX(value, (unsigned long *)ptr);
kadonotakashi 0:8fdf9a60065b 560 }
kadonotakashi 0:8fdf9a60065b 561 #endif
kadonotakashi 0:8fdf9a60065b 562
kadonotakashi 0:8fdf9a60065b 563
kadonotakashi 0:8fdf9a60065b 564 /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
kadonotakashi 0:8fdf9a60065b 565 #if (__CORTEX_M >= 0x03)
kadonotakashi 0:8fdf9a60065b 566
kadonotakashi 0:8fdf9a60065b 567 __IAR_FT uint32_t __RRX(uint32_t value)
kadonotakashi 0:8fdf9a60065b 568 {
kadonotakashi 0:8fdf9a60065b 569 uint32_t result;
kadonotakashi 0:8fdf9a60065b 570 __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
kadonotakashi 0:8fdf9a60065b 571 return(result);
kadonotakashi 0:8fdf9a60065b 572 }
kadonotakashi 0:8fdf9a60065b 573
kadonotakashi 0:8fdf9a60065b 574 __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
kadonotakashi 0:8fdf9a60065b 575 {
kadonotakashi 0:8fdf9a60065b 576 __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
kadonotakashi 0:8fdf9a60065b 577 }
kadonotakashi 0:8fdf9a60065b 578
kadonotakashi 0:8fdf9a60065b 579
kadonotakashi 0:8fdf9a60065b 580 #define __enable_fault_irq __enable_fiq
kadonotakashi 0:8fdf9a60065b 581 #define __disable_fault_irq __disable_fiq
kadonotakashi 0:8fdf9a60065b 582
kadonotakashi 0:8fdf9a60065b 583
kadonotakashi 0:8fdf9a60065b 584 #endif /* (__CORTEX_M >= 0x03) */
kadonotakashi 0:8fdf9a60065b 585
kadonotakashi 0:8fdf9a60065b 586 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
kadonotakashi 0:8fdf9a60065b 587 {
kadonotakashi 0:8fdf9a60065b 588 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
kadonotakashi 0:8fdf9a60065b 589 }
kadonotakashi 0:8fdf9a60065b 590
kadonotakashi 0:8fdf9a60065b 591 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
kadonotakashi 0:8fdf9a60065b 592 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
kadonotakashi 0:8fdf9a60065b 593
kadonotakashi 0:8fdf9a60065b 594 __IAR_FT uint32_t __get_MSPLIM(void)
kadonotakashi 0:8fdf9a60065b 595 {
kadonotakashi 0:8fdf9a60065b 596 uint32_t res;
kadonotakashi 0:8fdf9a60065b 597 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
kadonotakashi 0:8fdf9a60065b 598 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
kadonotakashi 0:8fdf9a60065b 599 // without main extensions, the non-secure MSPLIM is RAZ/WI
kadonotakashi 0:8fdf9a60065b 600 res = 0U;
kadonotakashi 0:8fdf9a60065b 601 #else
kadonotakashi 0:8fdf9a60065b 602 __asm volatile("MRS %0,MSPLIM" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 603 #endif
kadonotakashi 0:8fdf9a60065b 604 return res;
kadonotakashi 0:8fdf9a60065b 605 }
kadonotakashi 0:8fdf9a60065b 606
kadonotakashi 0:8fdf9a60065b 607 __IAR_FT void __set_MSPLIM(uint32_t value)
kadonotakashi 0:8fdf9a60065b 608 {
kadonotakashi 0:8fdf9a60065b 609 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
kadonotakashi 0:8fdf9a60065b 610 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
kadonotakashi 0:8fdf9a60065b 611 // without main extensions, the non-secure MSPLIM is RAZ/WI
kadonotakashi 0:8fdf9a60065b 612 (void)value;
kadonotakashi 0:8fdf9a60065b 613 #else
kadonotakashi 0:8fdf9a60065b 614 __asm volatile("MSR MSPLIM,%0" :: "r" (value));
kadonotakashi 0:8fdf9a60065b 615 #endif
kadonotakashi 0:8fdf9a60065b 616 }
kadonotakashi 0:8fdf9a60065b 617
kadonotakashi 0:8fdf9a60065b 618 __IAR_FT uint32_t __get_PSPLIM(void)
kadonotakashi 0:8fdf9a60065b 619 {
kadonotakashi 0:8fdf9a60065b 620 uint32_t res;
kadonotakashi 0:8fdf9a60065b 621 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
kadonotakashi 0:8fdf9a60065b 622 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
kadonotakashi 0:8fdf9a60065b 623 // without main extensions, the non-secure PSPLIM is RAZ/WI
kadonotakashi 0:8fdf9a60065b 624 res = 0U;
kadonotakashi 0:8fdf9a60065b 625 #else
kadonotakashi 0:8fdf9a60065b 626 __asm volatile("MRS %0,PSPLIM" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 627 #endif
kadonotakashi 0:8fdf9a60065b 628 return res;
kadonotakashi 0:8fdf9a60065b 629 }
kadonotakashi 0:8fdf9a60065b 630
kadonotakashi 0:8fdf9a60065b 631 __IAR_FT void __set_PSPLIM(uint32_t value)
kadonotakashi 0:8fdf9a60065b 632 {
kadonotakashi 0:8fdf9a60065b 633 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
kadonotakashi 0:8fdf9a60065b 634 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
kadonotakashi 0:8fdf9a60065b 635 // without main extensions, the non-secure PSPLIM is RAZ/WI
kadonotakashi 0:8fdf9a60065b 636 (void)value;
kadonotakashi 0:8fdf9a60065b 637 #else
kadonotakashi 0:8fdf9a60065b 638 __asm volatile("MSR PSPLIM,%0" :: "r" (value));
kadonotakashi 0:8fdf9a60065b 639 #endif
kadonotakashi 0:8fdf9a60065b 640 }
kadonotakashi 0:8fdf9a60065b 641
kadonotakashi 0:8fdf9a60065b 642 __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
kadonotakashi 0:8fdf9a60065b 643 {
kadonotakashi 0:8fdf9a60065b 644 uint32_t res;
kadonotakashi 0:8fdf9a60065b 645 __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 646 return res;
kadonotakashi 0:8fdf9a60065b 647 }
kadonotakashi 0:8fdf9a60065b 648
kadonotakashi 0:8fdf9a60065b 649 __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
kadonotakashi 0:8fdf9a60065b 650 {
kadonotakashi 0:8fdf9a60065b 651 __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
kadonotakashi 0:8fdf9a60065b 652 }
kadonotakashi 0:8fdf9a60065b 653
kadonotakashi 0:8fdf9a60065b 654 __IAR_FT uint32_t __TZ_get_PSP_NS(void)
kadonotakashi 0:8fdf9a60065b 655 {
kadonotakashi 0:8fdf9a60065b 656 uint32_t res;
kadonotakashi 0:8fdf9a60065b 657 __asm volatile("MRS %0,PSP_NS" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 658 return res;
kadonotakashi 0:8fdf9a60065b 659 }
kadonotakashi 0:8fdf9a60065b 660
kadonotakashi 0:8fdf9a60065b 661 __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
kadonotakashi 0:8fdf9a60065b 662 {
kadonotakashi 0:8fdf9a60065b 663 __asm volatile("MSR PSP_NS,%0" :: "r" (value));
kadonotakashi 0:8fdf9a60065b 664 }
kadonotakashi 0:8fdf9a60065b 665
kadonotakashi 0:8fdf9a60065b 666 __IAR_FT uint32_t __TZ_get_MSP_NS(void)
kadonotakashi 0:8fdf9a60065b 667 {
kadonotakashi 0:8fdf9a60065b 668 uint32_t res;
kadonotakashi 0:8fdf9a60065b 669 __asm volatile("MRS %0,MSP_NS" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 670 return res;
kadonotakashi 0:8fdf9a60065b 671 }
kadonotakashi 0:8fdf9a60065b 672
kadonotakashi 0:8fdf9a60065b 673 __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
kadonotakashi 0:8fdf9a60065b 674 {
kadonotakashi 0:8fdf9a60065b 675 __asm volatile("MSR MSP_NS,%0" :: "r" (value));
kadonotakashi 0:8fdf9a60065b 676 }
kadonotakashi 0:8fdf9a60065b 677
kadonotakashi 0:8fdf9a60065b 678 __IAR_FT uint32_t __TZ_get_SP_NS(void)
kadonotakashi 0:8fdf9a60065b 679 {
kadonotakashi 0:8fdf9a60065b 680 uint32_t res;
kadonotakashi 0:8fdf9a60065b 681 __asm volatile("MRS %0,SP_NS" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 682 return res;
kadonotakashi 0:8fdf9a60065b 683 }
kadonotakashi 0:8fdf9a60065b 684 __IAR_FT void __TZ_set_SP_NS(uint32_t value)
kadonotakashi 0:8fdf9a60065b 685 {
kadonotakashi 0:8fdf9a60065b 686 __asm volatile("MSR SP_NS,%0" :: "r" (value));
kadonotakashi 0:8fdf9a60065b 687 }
kadonotakashi 0:8fdf9a60065b 688
kadonotakashi 0:8fdf9a60065b 689 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
kadonotakashi 0:8fdf9a60065b 690 {
kadonotakashi 0:8fdf9a60065b 691 uint32_t res;
kadonotakashi 0:8fdf9a60065b 692 __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 693 return res;
kadonotakashi 0:8fdf9a60065b 694 }
kadonotakashi 0:8fdf9a60065b 695
kadonotakashi 0:8fdf9a60065b 696 __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
kadonotakashi 0:8fdf9a60065b 697 {
kadonotakashi 0:8fdf9a60065b 698 __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
kadonotakashi 0:8fdf9a60065b 699 }
kadonotakashi 0:8fdf9a60065b 700
kadonotakashi 0:8fdf9a60065b 701 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
kadonotakashi 0:8fdf9a60065b 702 {
kadonotakashi 0:8fdf9a60065b 703 uint32_t res;
kadonotakashi 0:8fdf9a60065b 704 __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 705 return res;
kadonotakashi 0:8fdf9a60065b 706 }
kadonotakashi 0:8fdf9a60065b 707
kadonotakashi 0:8fdf9a60065b 708 __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
kadonotakashi 0:8fdf9a60065b 709 {
kadonotakashi 0:8fdf9a60065b 710 __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
kadonotakashi 0:8fdf9a60065b 711 }
kadonotakashi 0:8fdf9a60065b 712
kadonotakashi 0:8fdf9a60065b 713 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
kadonotakashi 0:8fdf9a60065b 714 {
kadonotakashi 0:8fdf9a60065b 715 uint32_t res;
kadonotakashi 0:8fdf9a60065b 716 __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 717 return res;
kadonotakashi 0:8fdf9a60065b 718 }
kadonotakashi 0:8fdf9a60065b 719
kadonotakashi 0:8fdf9a60065b 720 __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
kadonotakashi 0:8fdf9a60065b 721 {
kadonotakashi 0:8fdf9a60065b 722 __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
kadonotakashi 0:8fdf9a60065b 723 }
kadonotakashi 0:8fdf9a60065b 724
kadonotakashi 0:8fdf9a60065b 725 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
kadonotakashi 0:8fdf9a60065b 726 {
kadonotakashi 0:8fdf9a60065b 727 uint32_t res;
kadonotakashi 0:8fdf9a60065b 728 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
kadonotakashi 0:8fdf9a60065b 729 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
kadonotakashi 0:8fdf9a60065b 730 // without main extensions, the non-secure PSPLIM is RAZ/WI
kadonotakashi 0:8fdf9a60065b 731 res = 0U;
kadonotakashi 0:8fdf9a60065b 732 #else
kadonotakashi 0:8fdf9a60065b 733 __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 734 #endif
kadonotakashi 0:8fdf9a60065b 735 return res;
kadonotakashi 0:8fdf9a60065b 736 }
kadonotakashi 0:8fdf9a60065b 737
kadonotakashi 0:8fdf9a60065b 738 __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
kadonotakashi 0:8fdf9a60065b 739 {
kadonotakashi 0:8fdf9a60065b 740 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
kadonotakashi 0:8fdf9a60065b 741 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
kadonotakashi 0:8fdf9a60065b 742 // without main extensions, the non-secure PSPLIM is RAZ/WI
kadonotakashi 0:8fdf9a60065b 743 (void)value;
kadonotakashi 0:8fdf9a60065b 744 #else
kadonotakashi 0:8fdf9a60065b 745 __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
kadonotakashi 0:8fdf9a60065b 746 #endif
kadonotakashi 0:8fdf9a60065b 747 }
kadonotakashi 0:8fdf9a60065b 748
kadonotakashi 0:8fdf9a60065b 749 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
kadonotakashi 0:8fdf9a60065b 750 {
kadonotakashi 0:8fdf9a60065b 751 uint32_t res;
kadonotakashi 0:8fdf9a60065b 752 __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
kadonotakashi 0:8fdf9a60065b 753 return res;
kadonotakashi 0:8fdf9a60065b 754 }
kadonotakashi 0:8fdf9a60065b 755
kadonotakashi 0:8fdf9a60065b 756 __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
kadonotakashi 0:8fdf9a60065b 757 {
kadonotakashi 0:8fdf9a60065b 758 __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
kadonotakashi 0:8fdf9a60065b 759 }
kadonotakashi 0:8fdf9a60065b 760
kadonotakashi 0:8fdf9a60065b 761 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
kadonotakashi 0:8fdf9a60065b 762
kadonotakashi 0:8fdf9a60065b 763 #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
kadonotakashi 0:8fdf9a60065b 764
kadonotakashi 0:8fdf9a60065b 765 #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
kadonotakashi 0:8fdf9a60065b 766
kadonotakashi 0:8fdf9a60065b 767 #if __IAR_M0_FAMILY
kadonotakashi 0:8fdf9a60065b 768 __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
kadonotakashi 0:8fdf9a60065b 769 {
kadonotakashi 0:8fdf9a60065b 770 if ((sat >= 1U) && (sat <= 32U))
kadonotakashi 0:8fdf9a60065b 771 {
kadonotakashi 0:8fdf9a60065b 772 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
kadonotakashi 0:8fdf9a60065b 773 const int32_t min = -1 - max ;
kadonotakashi 0:8fdf9a60065b 774 if (val > max)
kadonotakashi 0:8fdf9a60065b 775 {
kadonotakashi 0:8fdf9a60065b 776 return max;
kadonotakashi 0:8fdf9a60065b 777 }
kadonotakashi 0:8fdf9a60065b 778 else if (val < min)
kadonotakashi 0:8fdf9a60065b 779 {
kadonotakashi 0:8fdf9a60065b 780 return min;
kadonotakashi 0:8fdf9a60065b 781 }
kadonotakashi 0:8fdf9a60065b 782 }
kadonotakashi 0:8fdf9a60065b 783 return val;
kadonotakashi 0:8fdf9a60065b 784 }
kadonotakashi 0:8fdf9a60065b 785
kadonotakashi 0:8fdf9a60065b 786 __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
kadonotakashi 0:8fdf9a60065b 787 {
kadonotakashi 0:8fdf9a60065b 788 if (sat <= 31U)
kadonotakashi 0:8fdf9a60065b 789 {
kadonotakashi 0:8fdf9a60065b 790 const uint32_t max = ((1U << sat) - 1U);
kadonotakashi 0:8fdf9a60065b 791 if (val > (int32_t)max)
kadonotakashi 0:8fdf9a60065b 792 {
kadonotakashi 0:8fdf9a60065b 793 return max;
kadonotakashi 0:8fdf9a60065b 794 }
kadonotakashi 0:8fdf9a60065b 795 else if (val < 0)
kadonotakashi 0:8fdf9a60065b 796 {
kadonotakashi 0:8fdf9a60065b 797 return 0U;
kadonotakashi 0:8fdf9a60065b 798 }
kadonotakashi 0:8fdf9a60065b 799 }
kadonotakashi 0:8fdf9a60065b 800 return (uint32_t)val;
kadonotakashi 0:8fdf9a60065b 801 }
kadonotakashi 0:8fdf9a60065b 802 #endif
kadonotakashi 0:8fdf9a60065b 803
kadonotakashi 0:8fdf9a60065b 804 #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
kadonotakashi 0:8fdf9a60065b 805
kadonotakashi 0:8fdf9a60065b 806 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
kadonotakashi 0:8fdf9a60065b 807 {
kadonotakashi 0:8fdf9a60065b 808 uint32_t res;
kadonotakashi 0:8fdf9a60065b 809 __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
kadonotakashi 0:8fdf9a60065b 810 return ((uint8_t)res);
kadonotakashi 0:8fdf9a60065b 811 }
kadonotakashi 0:8fdf9a60065b 812
kadonotakashi 0:8fdf9a60065b 813 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
kadonotakashi 0:8fdf9a60065b 814 {
kadonotakashi 0:8fdf9a60065b 815 uint32_t res;
kadonotakashi 0:8fdf9a60065b 816 __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
kadonotakashi 0:8fdf9a60065b 817 return ((uint16_t)res);
kadonotakashi 0:8fdf9a60065b 818 }
kadonotakashi 0:8fdf9a60065b 819
kadonotakashi 0:8fdf9a60065b 820 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
kadonotakashi 0:8fdf9a60065b 821 {
kadonotakashi 0:8fdf9a60065b 822 uint32_t res;
kadonotakashi 0:8fdf9a60065b 823 __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
kadonotakashi 0:8fdf9a60065b 824 return res;
kadonotakashi 0:8fdf9a60065b 825 }
kadonotakashi 0:8fdf9a60065b 826
kadonotakashi 0:8fdf9a60065b 827 __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
kadonotakashi 0:8fdf9a60065b 828 {
kadonotakashi 0:8fdf9a60065b 829 __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
kadonotakashi 0:8fdf9a60065b 830 }
kadonotakashi 0:8fdf9a60065b 831
kadonotakashi 0:8fdf9a60065b 832 __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
kadonotakashi 0:8fdf9a60065b 833 {
kadonotakashi 0:8fdf9a60065b 834 __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
kadonotakashi 0:8fdf9a60065b 835 }
kadonotakashi 0:8fdf9a60065b 836
kadonotakashi 0:8fdf9a60065b 837 __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
kadonotakashi 0:8fdf9a60065b 838 {
kadonotakashi 0:8fdf9a60065b 839 __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
kadonotakashi 0:8fdf9a60065b 840 }
kadonotakashi 0:8fdf9a60065b 841
kadonotakashi 0:8fdf9a60065b 842 #endif /* (__CORTEX_M >= 0x03) */
kadonotakashi 0:8fdf9a60065b 843
kadonotakashi 0:8fdf9a60065b 844 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
kadonotakashi 0:8fdf9a60065b 845 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
kadonotakashi 0:8fdf9a60065b 846
kadonotakashi 0:8fdf9a60065b 847
kadonotakashi 0:8fdf9a60065b 848 __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
kadonotakashi 0:8fdf9a60065b 849 {
kadonotakashi 0:8fdf9a60065b 850 uint32_t res;
kadonotakashi 0:8fdf9a60065b 851 __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
kadonotakashi 0:8fdf9a60065b 852 return ((uint8_t)res);
kadonotakashi 0:8fdf9a60065b 853 }
kadonotakashi 0:8fdf9a60065b 854
kadonotakashi 0:8fdf9a60065b 855 __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
kadonotakashi 0:8fdf9a60065b 856 {
kadonotakashi 0:8fdf9a60065b 857 uint32_t res;
kadonotakashi 0:8fdf9a60065b 858 __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
kadonotakashi 0:8fdf9a60065b 859 return ((uint16_t)res);
kadonotakashi 0:8fdf9a60065b 860 }
kadonotakashi 0:8fdf9a60065b 861
kadonotakashi 0:8fdf9a60065b 862 __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
kadonotakashi 0:8fdf9a60065b 863 {
kadonotakashi 0:8fdf9a60065b 864 uint32_t res;
kadonotakashi 0:8fdf9a60065b 865 __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
kadonotakashi 0:8fdf9a60065b 866 return res;
kadonotakashi 0:8fdf9a60065b 867 }
kadonotakashi 0:8fdf9a60065b 868
kadonotakashi 0:8fdf9a60065b 869 __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
kadonotakashi 0:8fdf9a60065b 870 {
kadonotakashi 0:8fdf9a60065b 871 __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
kadonotakashi 0:8fdf9a60065b 872 }
kadonotakashi 0:8fdf9a60065b 873
kadonotakashi 0:8fdf9a60065b 874 __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
kadonotakashi 0:8fdf9a60065b 875 {
kadonotakashi 0:8fdf9a60065b 876 __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
kadonotakashi 0:8fdf9a60065b 877 }
kadonotakashi 0:8fdf9a60065b 878
kadonotakashi 0:8fdf9a60065b 879 __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
kadonotakashi 0:8fdf9a60065b 880 {
kadonotakashi 0:8fdf9a60065b 881 __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
kadonotakashi 0:8fdf9a60065b 882 }
kadonotakashi 0:8fdf9a60065b 883
kadonotakashi 0:8fdf9a60065b 884 __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
kadonotakashi 0:8fdf9a60065b 885 {
kadonotakashi 0:8fdf9a60065b 886 uint32_t res;
kadonotakashi 0:8fdf9a60065b 887 __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
kadonotakashi 0:8fdf9a60065b 888 return ((uint8_t)res);
kadonotakashi 0:8fdf9a60065b 889 }
kadonotakashi 0:8fdf9a60065b 890
kadonotakashi 0:8fdf9a60065b 891 __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
kadonotakashi 0:8fdf9a60065b 892 {
kadonotakashi 0:8fdf9a60065b 893 uint32_t res;
kadonotakashi 0:8fdf9a60065b 894 __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
kadonotakashi 0:8fdf9a60065b 895 return ((uint16_t)res);
kadonotakashi 0:8fdf9a60065b 896 }
kadonotakashi 0:8fdf9a60065b 897
kadonotakashi 0:8fdf9a60065b 898 __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
kadonotakashi 0:8fdf9a60065b 899 {
kadonotakashi 0:8fdf9a60065b 900 uint32_t res;
kadonotakashi 0:8fdf9a60065b 901 __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
kadonotakashi 0:8fdf9a60065b 902 return res;
kadonotakashi 0:8fdf9a60065b 903 }
kadonotakashi 0:8fdf9a60065b 904
kadonotakashi 0:8fdf9a60065b 905 __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
kadonotakashi 0:8fdf9a60065b 906 {
kadonotakashi 0:8fdf9a60065b 907 uint32_t res;
kadonotakashi 0:8fdf9a60065b 908 __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
kadonotakashi 0:8fdf9a60065b 909 return res;
kadonotakashi 0:8fdf9a60065b 910 }
kadonotakashi 0:8fdf9a60065b 911
kadonotakashi 0:8fdf9a60065b 912 __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
kadonotakashi 0:8fdf9a60065b 913 {
kadonotakashi 0:8fdf9a60065b 914 uint32_t res;
kadonotakashi 0:8fdf9a60065b 915 __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
kadonotakashi 0:8fdf9a60065b 916 return res;
kadonotakashi 0:8fdf9a60065b 917 }
kadonotakashi 0:8fdf9a60065b 918
kadonotakashi 0:8fdf9a60065b 919 __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
kadonotakashi 0:8fdf9a60065b 920 {
kadonotakashi 0:8fdf9a60065b 921 uint32_t res;
kadonotakashi 0:8fdf9a60065b 922 __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
kadonotakashi 0:8fdf9a60065b 923 return res;
kadonotakashi 0:8fdf9a60065b 924 }
kadonotakashi 0:8fdf9a60065b 925
kadonotakashi 0:8fdf9a60065b 926 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
kadonotakashi 0:8fdf9a60065b 927
kadonotakashi 0:8fdf9a60065b 928 #undef __IAR_FT
kadonotakashi 0:8fdf9a60065b 929 #undef __IAR_M0_FAMILY
kadonotakashi 0:8fdf9a60065b 930 #undef __ICCARM_V8
kadonotakashi 0:8fdf9a60065b 931
kadonotakashi 0:8fdf9a60065b 932 #pragma diag_default=Pe940
kadonotakashi 0:8fdf9a60065b 933 #pragma diag_default=Pe177
kadonotakashi 0:8fdf9a60065b 934
kadonotakashi 0:8fdf9a60065b 935 #endif /* __CMSIS_ICCARM_H__ */