takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_NUVOTON/TARGET_NUC472/device/system_NUC472_442.c@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /**************************************************************************//**
kadonotakashi 0:8fdf9a60065b 2 * @file system_NUC472_442.c
kadonotakashi 0:8fdf9a60065b 3 * @version V1.00
kadonotakashi 0:8fdf9a60065b 4 * $Revision: 15 $
kadonotakashi 0:8fdf9a60065b 5 * $Date: 14/05/29 1:13p $
kadonotakashi 0:8fdf9a60065b 6 * @brief NUC472/NUC442 system clock init code and assert handler
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * @note
kadonotakashi 0:8fdf9a60065b 9 * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
kadonotakashi 0:8fdf9a60065b 10 *****************************************************************************/
kadonotakashi 0:8fdf9a60065b 11
kadonotakashi 0:8fdf9a60065b 12 #include "NUC472_442.h"
kadonotakashi 0:8fdf9a60065b 13 //#include "rtc.h"
kadonotakashi 0:8fdf9a60065b 14
kadonotakashi 0:8fdf9a60065b 15 /*----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 16 Clock Variable definitions
kadonotakashi 0:8fdf9a60065b 17 *----------------------------------------------------------------------------*/
kadonotakashi 0:8fdf9a60065b 18 uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock)*/
kadonotakashi 0:8fdf9a60065b 19 uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
kadonotakashi 0:8fdf9a60065b 20 uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC}; /*!< System clock source table */
kadonotakashi 0:8fdf9a60065b 21
kadonotakashi 0:8fdf9a60065b 22 #if defined TARGET_NU_XRAM_SUPPORTED
kadonotakashi 0:8fdf9a60065b 23 static void nu_ebi_init(void);
kadonotakashi 0:8fdf9a60065b 24 #endif
kadonotakashi 0:8fdf9a60065b 25
kadonotakashi 0:8fdf9a60065b 26 /*----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 27 Clock functions
kadonotakashi 0:8fdf9a60065b 28 *----------------------------------------------------------------------------*/
kadonotakashi 0:8fdf9a60065b 29 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
kadonotakashi 0:8fdf9a60065b 30 {
kadonotakashi 0:8fdf9a60065b 31 uint32_t u32Freq, u32ClkSrc;
kadonotakashi 0:8fdf9a60065b 32 uint32_t u32HclkDiv;
kadonotakashi 0:8fdf9a60065b 33
kadonotakashi 0:8fdf9a60065b 34 u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
kadonotakashi 0:8fdf9a60065b 35
kadonotakashi 0:8fdf9a60065b 36 if(u32ClkSrc != CLK_CLKSEL0_HCLKSEL_PLL) {
kadonotakashi 0:8fdf9a60065b 37 /* Use the clock sources directly */
kadonotakashi 0:8fdf9a60065b 38 u32Freq = gau32ClkSrcTbl[u32ClkSrc];
kadonotakashi 0:8fdf9a60065b 39 } else {
kadonotakashi 0:8fdf9a60065b 40 /* Use PLL clock */
kadonotakashi 0:8fdf9a60065b 41 u32Freq = CLK_GetPLLClockFreq();
kadonotakashi 0:8fdf9a60065b 42 }
kadonotakashi 0:8fdf9a60065b 43
kadonotakashi 0:8fdf9a60065b 44 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
kadonotakashi 0:8fdf9a60065b 45
kadonotakashi 0:8fdf9a60065b 46 /* Update System Core Clock */
kadonotakashi 0:8fdf9a60065b 47 SystemCoreClock = u32Freq/u32HclkDiv;
kadonotakashi 0:8fdf9a60065b 48
kadonotakashi 0:8fdf9a60065b 49 CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
kadonotakashi 0:8fdf9a60065b 50 }
kadonotakashi 0:8fdf9a60065b 51
kadonotakashi 0:8fdf9a60065b 52 /**
kadonotakashi 0:8fdf9a60065b 53 * Initialize the system
kadonotakashi 0:8fdf9a60065b 54 *
kadonotakashi 0:8fdf9a60065b 55 * @return none
kadonotakashi 0:8fdf9a60065b 56 *
kadonotakashi 0:8fdf9a60065b 57 * @brief Setup the microcontroller system.
kadonotakashi 0:8fdf9a60065b 58 */
kadonotakashi 0:8fdf9a60065b 59 void SystemInit (void)
kadonotakashi 0:8fdf9a60065b 60 {
kadonotakashi 0:8fdf9a60065b 61 //uint32_t u32RTC_EN_Flag = 0;
kadonotakashi 0:8fdf9a60065b 62
kadonotakashi 0:8fdf9a60065b 63 /* FPU settings ------------------------------------------------------------*/
kadonotakashi 0:8fdf9a60065b 64 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
kadonotakashi 0:8fdf9a60065b 65 SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
kadonotakashi 0:8fdf9a60065b 66 (3UL << 11*2) ); /* set CP11 Full Access */
kadonotakashi 0:8fdf9a60065b 67 #endif
kadonotakashi 0:8fdf9a60065b 68
kadonotakashi 0:8fdf9a60065b 69 /* The code snippet below is for old-version chip and has potential risk, e.g. program reboots and hangs in it with the call to NVIC_SystemReset(). Remove it for new-version chip. */
kadonotakashi 0:8fdf9a60065b 70 #if 0
kadonotakashi 0:8fdf9a60065b 71 /* ------------------ Release Tamper pin ---------------------------------*/
kadonotakashi 0:8fdf9a60065b 72 /* Waiting for 10kHz clock ready */
kadonotakashi 0:8fdf9a60065b 73 CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
kadonotakashi 0:8fdf9a60065b 74
kadonotakashi 0:8fdf9a60065b 75 u32RTC_EN_Flag = ((CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk) >> CLK_APBCLK0_RTCCKEN_Pos);
kadonotakashi 0:8fdf9a60065b 76
kadonotakashi 0:8fdf9a60065b 77 if(!u32RTC_EN_Flag) {
kadonotakashi 0:8fdf9a60065b 78 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; // RTC Clock Enable
kadonotakashi 0:8fdf9a60065b 79 }
kadonotakashi 0:8fdf9a60065b 80
kadonotakashi 0:8fdf9a60065b 81 RTC->INIT = RTC_INIT_KEY;
kadonotakashi 0:8fdf9a60065b 82 while(RTC->INIT != 0x1);
kadonotakashi 0:8fdf9a60065b 83
kadonotakashi 0:8fdf9a60065b 84 if(!(RTC->TAMPCTL & RTC_TAMPCTL_TIEN_Msk)) {
kadonotakashi 0:8fdf9a60065b 85 RTC->RWEN = RTC_WRITE_KEY;
kadonotakashi 0:8fdf9a60065b 86 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
kadonotakashi 0:8fdf9a60065b 87
kadonotakashi 0:8fdf9a60065b 88 RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
kadonotakashi 0:8fdf9a60065b 89
kadonotakashi 0:8fdf9a60065b 90 while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
kadonotakashi 0:8fdf9a60065b 91
kadonotakashi 0:8fdf9a60065b 92 RTC->RWEN = RTC_WRITE_KEY;
kadonotakashi 0:8fdf9a60065b 93 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
kadonotakashi 0:8fdf9a60065b 94
kadonotakashi 0:8fdf9a60065b 95 RTC->SPR[23] = RTC->SPR[23];
kadonotakashi 0:8fdf9a60065b 96 while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
kadonotakashi 0:8fdf9a60065b 97
kadonotakashi 0:8fdf9a60065b 98 RTC->RWEN = RTC_WRITE_KEY;
kadonotakashi 0:8fdf9a60065b 99 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
kadonotakashi 0:8fdf9a60065b 100
kadonotakashi 0:8fdf9a60065b 101 RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
kadonotakashi 0:8fdf9a60065b 102 while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
kadonotakashi 0:8fdf9a60065b 103
kadonotakashi 0:8fdf9a60065b 104 RTC->RWEN = RTC_WRITE_KEY;
kadonotakashi 0:8fdf9a60065b 105 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
kadonotakashi 0:8fdf9a60065b 106
kadonotakashi 0:8fdf9a60065b 107 RTC->INTSTS = RTC_INTSTS_TICKIF_Msk;
kadonotakashi 0:8fdf9a60065b 108 }
kadonotakashi 0:8fdf9a60065b 109
kadonotakashi 0:8fdf9a60065b 110 if(!u32RTC_EN_Flag) {
kadonotakashi 0:8fdf9a60065b 111 CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; // RTC Clock Disable
kadonotakashi 0:8fdf9a60065b 112 }
kadonotakashi 0:8fdf9a60065b 113 /*------------------------------------------------------------------------*/
kadonotakashi 0:8fdf9a60065b 114 #endif
kadonotakashi 0:8fdf9a60065b 115
kadonotakashi 0:8fdf9a60065b 116 #if defined TARGET_NU_XRAM_SUPPORTED
kadonotakashi 0:8fdf9a60065b 117 // NOTE: C-runtime not initialized yet. Ensure no static memory (global variable) are accessed in this function.
kadonotakashi 0:8fdf9a60065b 118 nu_ebi_init();
kadonotakashi 0:8fdf9a60065b 119 #endif
kadonotakashi 0:8fdf9a60065b 120 }
kadonotakashi 0:8fdf9a60065b 121
kadonotakashi 0:8fdf9a60065b 122 #if defined TARGET_NU_XRAM_SUPPORTED
kadonotakashi 0:8fdf9a60065b 123 void nu_ebi_init(void)
kadonotakashi 0:8fdf9a60065b 124 {
kadonotakashi 0:8fdf9a60065b 125 /* Enable IP clock */
kadonotakashi 0:8fdf9a60065b 126 CLK_EnableModuleClock(EBI_MODULE);
kadonotakashi 0:8fdf9a60065b 127
kadonotakashi 0:8fdf9a60065b 128 /* Configure EBI multi-function pins */
kadonotakashi 0:8fdf9a60065b 129 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA10MFP_Msk) ) | SYS_GPA_MFPH_PA10MFP_EBI_A20; /* A20. = PA10 */
kadonotakashi 0:8fdf9a60065b 130 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA9MFP_Msk) ) | SYS_GPA_MFPH_PA9MFP_EBI_A19; /* A19. = PA9 */
kadonotakashi 0:8fdf9a60065b 131 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA8MFP_Msk) ) | SYS_GPA_MFPH_PA8MFP_EBI_A18; /* A18. = PA8 */
kadonotakashi 0:8fdf9a60065b 132 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA7MFP_Msk) ) | SYS_GPA_MFPL_PA7MFP_EBI_A17; /* A17. = PA7 */
kadonotakashi 0:8fdf9a60065b 133 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA6MFP_Msk) ) | SYS_GPA_MFPL_PA6MFP_EBI_A16; /* A16. = PA6 */
kadonotakashi 0:8fdf9a60065b 134 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB13MFP_Msk) ) | SYS_GPB_MFPH_PB13MFP_EBI_AD15; /* AD15 = PB13 */
kadonotakashi 0:8fdf9a60065b 135
kadonotakashi 0:8fdf9a60065b 136 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB12MFP_Msk) ) | SYS_GPB_MFPH_PB12MFP_EBI_AD14; /* AD14 = PB12 */
kadonotakashi 0:8fdf9a60065b 137 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB11MFP_Msk) ) | SYS_GPB_MFPH_PB11MFP_EBI_AD13; /* AD13 = PB11 */
kadonotakashi 0:8fdf9a60065b 138 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB10MFP_Msk) ) | SYS_GPB_MFPH_PB10MFP_EBI_AD12; /* AD12 = PB10 */
kadonotakashi 0:8fdf9a60065b 139 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB9MFP_Msk) ) | SYS_GPB_MFPH_PB9MFP_EBI_AD11; /* AD11 = PB9 */
kadonotakashi 0:8fdf9a60065b 140 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB8MFP_Msk) ) | SYS_GPB_MFPH_PB8MFP_EBI_AD10; /* AD10 = PB8 */
kadonotakashi 0:8fdf9a60065b 141
kadonotakashi 0:8fdf9a60065b 142 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB7MFP_Msk) ) | SYS_GPB_MFPL_PB7MFP_EBI_AD9; /* AD9 = PB7 */
kadonotakashi 0:8fdf9a60065b 143 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB6MFP_Msk) ) | SYS_GPB_MFPL_PB6MFP_EBI_AD8; /* AD8 = PB6 */
kadonotakashi 0:8fdf9a60065b 144 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB5MFP_Msk) ) | SYS_GPB_MFPL_PB5MFP_EBI_AD7; /* AD7 = PB5 */
kadonotakashi 0:8fdf9a60065b 145 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB4MFP_Msk) ) | SYS_GPB_MFPL_PB4MFP_EBI_AD6; /* AD6 = PB4 */
kadonotakashi 0:8fdf9a60065b 146 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB3MFP_Msk) ) | SYS_GPB_MFPL_PB3MFP_EBI_AD5; /* AD5 = PB3 */
kadonotakashi 0:8fdf9a60065b 147 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB2MFP_Msk) ) | SYS_GPB_MFPL_PB2MFP_EBI_AD4; /* AD4 = PB2 */
kadonotakashi 0:8fdf9a60065b 148
kadonotakashi 0:8fdf9a60065b 149 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA14MFP_Msk) ) | SYS_GPA_MFPH_PA14MFP_EBI_AD3; /* AD3. = PA14 */
kadonotakashi 0:8fdf9a60065b 150 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA13MFP_Msk) ) | SYS_GPA_MFPH_PA13MFP_EBI_AD2; /* AD2. = PA13 */
kadonotakashi 0:8fdf9a60065b 151 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA12MFP_Msk) ) | SYS_GPA_MFPH_PA12MFP_EBI_AD1; /* AD1. = PA12 */
kadonotakashi 0:8fdf9a60065b 152 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA11MFP_Msk) ) | SYS_GPA_MFPH_PA11MFP_EBI_AD0; /* AD0. = PA11 */
kadonotakashi 0:8fdf9a60065b 153
kadonotakashi 0:8fdf9a60065b 154 SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SYS_GPE_MFPL_PE6MFP_Msk) ) | SYS_GPE_MFPL_PE6MFP_EBI_nWR; /* PE.6 = nWR */
kadonotakashi 0:8fdf9a60065b 155 SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SYS_GPE_MFPL_PE7MFP_Msk) ) | SYS_GPE_MFPL_PE7MFP_EBI_nRD; /* PE.7 = nRD */
kadonotakashi 0:8fdf9a60065b 156 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE8MFP_Msk) ) | SYS_GPE_MFPH_PE8MFP_EBI_ALE; /* PE.8 = ALE */
kadonotakashi 0:8fdf9a60065b 157 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE9MFP_Msk) ) | SYS_GPE_MFPH_PE9MFP_EBI_nWRH; /* PE.9 = WRH */
kadonotakashi 0:8fdf9a60065b 158 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE10MFP_Msk) ) | SYS_GPE_MFPH_PE10MFP_EBI_nWRL; /* PE.10 = WRL */
kadonotakashi 0:8fdf9a60065b 159
kadonotakashi 0:8fdf9a60065b 160 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE11MFP_Msk) ) | SYS_GPE_MFPH_PE11MFP_EBI_nCS0; /* PE.11 = nCS0 */
kadonotakashi 0:8fdf9a60065b 161 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE12MFP_Msk) ) | SYS_GPE_MFPH_PE12MFP_EBI_nCS1; /* PE.12 = nCS1 */
kadonotakashi 0:8fdf9a60065b 162 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE13MFP_Msk) ) | SYS_GPE_MFPH_PE13MFP_EBI_nCS2; /* PE.13 = nCS2 */
kadonotakashi 0:8fdf9a60065b 163 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE14MFP_Msk) ) | SYS_GPE_MFPH_PE14MFP_EBI_nCS3; /* PE.14 = nCS3 */
kadonotakashi 0:8fdf9a60065b 164
kadonotakashi 0:8fdf9a60065b 165 const uint32_t u32Timing = 0x21C;
kadonotakashi 0:8fdf9a60065b 166
kadonotakashi 0:8fdf9a60065b 167 /* Open EBI interface */
kadonotakashi 0:8fdf9a60065b 168 EBI_Open(EBI_BANK0, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
kadonotakashi 0:8fdf9a60065b 169 EBI_Open(EBI_BANK1, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
kadonotakashi 0:8fdf9a60065b 170 EBI_Open(EBI_BANK2, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
kadonotakashi 0:8fdf9a60065b 171 EBI_Open(EBI_BANK3, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
kadonotakashi 0:8fdf9a60065b 172
kadonotakashi 0:8fdf9a60065b 173 /* Configure EBI timing */
kadonotakashi 0:8fdf9a60065b 174 EBI_SetBusTiming(EBI_BANK0, u32Timing, EBI_MCLKDIV_2);
kadonotakashi 0:8fdf9a60065b 175 EBI_SetBusTiming(EBI_BANK1, u32Timing, EBI_MCLKDIV_2);
kadonotakashi 0:8fdf9a60065b 176 EBI_SetBusTiming(EBI_BANK2, u32Timing, EBI_MCLKDIV_2);
kadonotakashi 0:8fdf9a60065b 177 EBI_SetBusTiming(EBI_BANK3, u32Timing, EBI_MCLKDIV_2);
kadonotakashi 0:8fdf9a60065b 178 }
kadonotakashi 0:8fdf9a60065b 179 #endif
kadonotakashi 0:8fdf9a60065b 180 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/