takashi kadono
Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/sc_reg.h@3:f3764f852aa8, 2018-10-11 (annotated)
- Committer:
- kadonotakashi
- Date:
- Thu Oct 11 02:27:46 2018 +0000
- Revision:
- 3:f3764f852aa8
- Parent:
- 0:8fdf9a60065b
Nucreo 446 + SSD1331 test version;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
| kadonotakashi | 0:8fdf9a60065b | 2 | * @file sc_reg.h |
| kadonotakashi | 0:8fdf9a60065b | 3 | * @version V1.00 |
| kadonotakashi | 0:8fdf9a60065b | 4 | * @brief SC register definition header file |
| kadonotakashi | 0:8fdf9a60065b | 5 | * |
| kadonotakashi | 0:8fdf9a60065b | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
| kadonotakashi | 0:8fdf9a60065b | 7 | *****************************************************************************/ |
| kadonotakashi | 0:8fdf9a60065b | 8 | #ifndef __SC_REG_H__ |
| kadonotakashi | 0:8fdf9a60065b | 9 | #define __SC_REG_H__ |
| kadonotakashi | 0:8fdf9a60065b | 10 | |
| kadonotakashi | 0:8fdf9a60065b | 11 | |
| kadonotakashi | 0:8fdf9a60065b | 12 | /*---------------------- Smart Card Host Interface Controller -------------------------*/ |
| kadonotakashi | 0:8fdf9a60065b | 13 | /** |
| kadonotakashi | 0:8fdf9a60065b | 14 | @addtogroup SC Smart Card Host Interface Controller(SC) |
| kadonotakashi | 0:8fdf9a60065b | 15 | Memory Mapped Structure for SC Controller |
| kadonotakashi | 0:8fdf9a60065b | 16 | @{ */ |
| kadonotakashi | 0:8fdf9a60065b | 17 | |
| kadonotakashi | 0:8fdf9a60065b | 18 | typedef struct |
| kadonotakashi | 0:8fdf9a60065b | 19 | { |
| kadonotakashi | 0:8fdf9a60065b | 20 | |
| kadonotakashi | 0:8fdf9a60065b | 21 | |
| kadonotakashi | 0:8fdf9a60065b | 22 | /** |
| kadonotakashi | 0:8fdf9a60065b | 23 | * @var SC_T::DAT |
| kadonotakashi | 0:8fdf9a60065b | 24 | * Offset: 0x00 SC Receive/Transmit Holding Buffer Register |
| kadonotakashi | 0:8fdf9a60065b | 25 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 26 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 27 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 28 | * |[7:0] |DAT |Receive/Transmit Holding Buffer |
| kadonotakashi | 0:8fdf9a60065b | 29 | * | | |Write Operation: |
| kadonotakashi | 0:8fdf9a60065b | 30 | * | | |By writing data to DAT, the SC will send out an 8-bit data. |
| kadonotakashi | 0:8fdf9a60065b | 31 | * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed. |
| kadonotakashi | 0:8fdf9a60065b | 32 | * | | |Read Operation: |
| kadonotakashi | 0:8fdf9a60065b | 33 | * | | |By reading DAT, the SC will return an 8-bit received data. |
| kadonotakashi | 0:8fdf9a60065b | 34 | * @var SC_T::CTL |
| kadonotakashi | 0:8fdf9a60065b | 35 | * Offset: 0x04 SC Control Register |
| kadonotakashi | 0:8fdf9a60065b | 36 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 37 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 38 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 39 | * |[0] |SCEN |SC Controller Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 40 | * | | |Set this bit to 1 to enable SC operation. |
| kadonotakashi | 0:8fdf9a60065b | 41 | * | | |0 = SC will force all transition to IDLE state. |
| kadonotakashi | 0:8fdf9a60065b | 42 | * | | |1 = SC controller is enabled and all function can work correctly. |
| kadonotakashi | 0:8fdf9a60065b | 43 | * | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. |
| kadonotakashi | 0:8fdf9a60065b | 44 | * |[1] |RXOFF |RX Transition Disable Control Bit |
| kadonotakashi | 0:8fdf9a60065b | 45 | * | | |This bit is used for disable Rx transition function. |
| kadonotakashi | 0:8fdf9a60065b | 46 | * | | |0 = The receiver Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 47 | * | | |1 = The receiver Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 48 | * | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. |
| kadonotakashi | 0:8fdf9a60065b | 49 | * |[2] |TXOFF |TX Transition Disable Control Bit |
| kadonotakashi | 0:8fdf9a60065b | 50 | * | | |This bit is used for disable Tx transition function. |
| kadonotakashi | 0:8fdf9a60065b | 51 | * | | |0 = The transceiver Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 52 | * | | |1 = The transceiver Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 53 | * |[3] |AUTOCEN |Auto Convention Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 54 | * | | |This bit is used for enable auto convention function. |
| kadonotakashi | 0:8fdf9a60065b | 55 | * | | |0 = Auto-convention Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 56 | * | | |1 = Auto-convention Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 57 | * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F |
| kadonotakashi | 0:8fdf9a60065b | 58 | * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F |
| kadonotakashi | 0:8fdf9a60065b | 59 | * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11. |
| kadonotakashi | 0:8fdf9a60065b | 60 | * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. |
| kadonotakashi | 0:8fdf9a60065b | 61 | * |[5:4] |CONSEL |Convention Selection |
| kadonotakashi | 0:8fdf9a60065b | 62 | * | | |00 = Direct convention. |
| kadonotakashi | 0:8fdf9a60065b | 63 | * | | |01 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 64 | * | | |10 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 65 | * | | |11 = Inverse convention. |
| kadonotakashi | 0:8fdf9a60065b | 66 | * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. |
| kadonotakashi | 0:8fdf9a60065b | 67 | * |[7:6] |RXTRGLV |Rx Buffer Trigger Level |
| kadonotakashi | 0:8fdf9a60065b | 68 | * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set |
| kadonotakashi | 0:8fdf9a60065b | 69 | * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. |
| kadonotakashi | 0:8fdf9a60065b | 70 | * | | |00 = Rx Buffer Trigger Level with 01 bytes. |
| kadonotakashi | 0:8fdf9a60065b | 71 | * | | |01 = Rx Buffer Trigger Level with 02 bytes. |
| kadonotakashi | 0:8fdf9a60065b | 72 | * | | |10 = Rx Buffer Trigger Level with 03 bytes. |
| kadonotakashi | 0:8fdf9a60065b | 73 | * | | |11 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 74 | * |[12:8] |BGT |Block Guard Time (BGT) |
| kadonotakashi | 0:8fdf9a60065b | 75 | * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions |
| kadonotakashi | 0:8fdf9a60065b | 76 | * | | |This field indicates the counter for the bit length of block guard time |
| kadonotakashi | 0:8fdf9a60065b | 77 | * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it. |
| kadonotakashi | 0:8fdf9a60065b | 78 | * | | |Note: The real block guard time is BGT + 1. |
| kadonotakashi | 0:8fdf9a60065b | 79 | * |[14:13] |TMRSEL |Timer Channel Selection |
| kadonotakashi | 0:8fdf9a60065b | 80 | * | | |00 = All internal timer function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 81 | * | | |. |
| kadonotakashi | 0:8fdf9a60065b | 82 | * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled |
| kadonotakashi | 0:8fdf9a60065b | 83 | * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]. |
| kadonotakashi | 0:8fdf9a60065b | 84 | * | | |Other configurations are reserve |
| kadonotakashi | 0:8fdf9a60065b | 85 | * |[15] |NSB |Stop Bit Length |
| kadonotakashi | 0:8fdf9a60065b | 86 | * | | |This field indicates the length of stop bit. |
| kadonotakashi | 0:8fdf9a60065b | 87 | * | | |0 = The stop bit length is 2 ETU.(for ISO 7816-3 T=0 mode). |
| kadonotakashi | 0:8fdf9a60065b | 88 | * | | |1= The stop bit length is 1 ETU.(for ISO 7816-3 T=1 mode). |
| kadonotakashi | 0:8fdf9a60065b | 89 | * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. |
| kadonotakashi | 0:8fdf9a60065b | 90 | * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. |
| kadonotakashi | 0:8fdf9a60065b | 91 | * |[18:16] |RXRTY |RX Error Retry Count Number |
| kadonotakashi | 0:8fdf9a60065b | 92 | * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred |
| kadonotakashi | 0:8fdf9a60065b | 93 | * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. |
| kadonotakashi | 0:8fdf9a60065b | 94 | * | | |Note2: This field cannot be changed when RXRTYEN enabled |
| kadonotakashi | 0:8fdf9a60065b | 95 | * | | |The change flow is to disable RXRTYEN first and then fill in new retry value. |
| kadonotakashi | 0:8fdf9a60065b | 96 | * |[19] |RXRTYEN |RX Error Retry Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 97 | * | | |This bit enables receiver retry function when parity error has occurred. |
| kadonotakashi | 0:8fdf9a60065b | 98 | * | | |0 = RX error retry function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 99 | * | | |1 = RX error retry function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 100 | * | | |Note: User must fill in the RXRTY value before enabling this bit. |
| kadonotakashi | 0:8fdf9a60065b | 101 | * |[22:20] |TXRTY |TX Error Retry Count Number |
| kadonotakashi | 0:8fdf9a60065b | 102 | * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. |
| kadonotakashi | 0:8fdf9a60065b | 103 | * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. |
| kadonotakashi | 0:8fdf9a60065b | 104 | * | | |Note2: This field cannot be changed when TXRTYEN enabled |
| kadonotakashi | 0:8fdf9a60065b | 105 | * | | |The change flow is to disable TXRTYEN first and then fill in new retry value. |
| kadonotakashi | 0:8fdf9a60065b | 106 | * |[23] |TXRTYEN |TX Error Retry Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 107 | * | | |This bit enables transmitter retry function when parity error has occurred. |
| kadonotakashi | 0:8fdf9a60065b | 108 | * | | |0 = TX error retry function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 109 | * | | |1 = TX error retry function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 110 | * |[25:24] |CDDBSEL |Card Detect De-bounce Selection |
| kadonotakashi | 0:8fdf9a60065b | 111 | * | | |This field indicates the card detect de-bounce selection. |
| kadonotakashi | 0:8fdf9a60065b | 112 | * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks. |
| kadonotakashi | 0:8fdf9a60065b | 113 | * | | |Other configurations are reserved. |
| kadonotakashi | 0:8fdf9a60065b | 114 | * |[26] |CDLV |Card Detect Level Selection |
| kadonotakashi | 0:8fdf9a60065b | 115 | * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected. |
| kadonotakashi | 0:8fdf9a60065b | 116 | * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected. |
| kadonotakashi | 0:8fdf9a60065b | 117 | * | | |Note: User must select card detect level before Smart Card controller enabled. |
| kadonotakashi | 0:8fdf9a60065b | 118 | * |[30] |SYNC |SYNC Flag Indicator (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 119 | * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. |
| kadonotakashi | 0:8fdf9a60065b | 120 | * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. |
| kadonotakashi | 0:8fdf9a60065b | 121 | * | | |1 = Last value is synchronizing. |
| kadonotakashi | 0:8fdf9a60065b | 122 | * @var SC_T::ALTCTL |
| kadonotakashi | 0:8fdf9a60065b | 123 | * Offset: 0x08 SC Alternate Control Register |
| kadonotakashi | 0:8fdf9a60065b | 124 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 125 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 126 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 127 | * |[0] |TXRST |TX Software Reset |
| kadonotakashi | 0:8fdf9a60065b | 128 | * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. |
| kadonotakashi | 0:8fdf9a60065b | 129 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 130 | * | | |1 = Reset the TX internal state machine and pointers. |
| kadonotakashi | 0:8fdf9a60065b | 131 | * | | |Note: This bit will be auto cleared after reset is complete. |
| kadonotakashi | 0:8fdf9a60065b | 132 | * |[1] |RXRST |Rx Software Reset |
| kadonotakashi | 0:8fdf9a60065b | 133 | * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared. |
| kadonotakashi | 0:8fdf9a60065b | 134 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 135 | * | | |1 = Reset the Rx internal state machine and pointers. |
| kadonotakashi | 0:8fdf9a60065b | 136 | * | | |Note: This bit will be auto cleared after reset is complete. |
| kadonotakashi | 0:8fdf9a60065b | 137 | * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 138 | * | | |This bit enables SC controller to initiate the card by deactivation sequence. |
| kadonotakashi | 0:8fdf9a60065b | 139 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 140 | * | | |1 = Deactivation sequence generator Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 141 | * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 142 | * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) |
| kadonotakashi | 0:8fdf9a60065b | 143 | * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time. |
| kadonotakashi | 0:8fdf9a60065b | 144 | * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. |
| kadonotakashi | 0:8fdf9a60065b | 145 | * |[3] |ACTEN |Activation Sequence Generator Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 146 | * | | |This bit enables SC controller to initiate the card by activation sequence. |
| kadonotakashi | 0:8fdf9a60065b | 147 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 148 | * | | |1 = Activation sequence generator Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 149 | * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 150 | * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) |
| kadonotakashi | 0:8fdf9a60065b | 151 | * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time. |
| kadonotakashi | 0:8fdf9a60065b | 152 | * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. |
| kadonotakashi | 0:8fdf9a60065b | 153 | * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data |
| kadonotakashi | 0:8fdf9a60065b | 154 | * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. |
| kadonotakashi | 0:8fdf9a60065b | 155 | * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 156 | * | | |This bit enables SC controller to initiate the card by warm reset sequence. |
| kadonotakashi | 0:8fdf9a60065b | 157 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 158 | * | | |1 = Warm reset sequence generator Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 159 | * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 160 | * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) |
| kadonotakashi | 0:8fdf9a60065b | 161 | * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time. |
| kadonotakashi | 0:8fdf9a60065b | 162 | * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. |
| kadonotakashi | 0:8fdf9a60065b | 163 | * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data |
| kadonotakashi | 0:8fdf9a60065b | 164 | * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence. |
| kadonotakashi | 0:8fdf9a60065b | 165 | * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 166 | * | | |This bit enables Timer 0 to start counting |
| kadonotakashi | 0:8fdf9a60065b | 167 | * | | |User can fill 0 to stop it and set 1 to reload and count |
| kadonotakashi | 0:8fdf9a60065b | 168 | * | | |The counter unit is ETU base. |
| kadonotakashi | 0:8fdf9a60065b | 169 | * | | |0 = Stops counting. |
| kadonotakashi | 0:8fdf9a60065b | 170 | * | | |1 = Start counting. |
| kadonotakashi | 0:8fdf9a60065b | 171 | * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only. |
| kadonotakashi | 0:8fdf9a60065b | 172 | * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware. |
| kadonotakashi | 0:8fdf9a60065b | 173 | * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed |
| kadonotakashi | 0:8fdf9a60065b | 174 | * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 175 | * | | |This bit enables Timer 1 to start counting |
| kadonotakashi | 0:8fdf9a60065b | 176 | * | | |User can fill 0 to stop it and set 1 to reload and count |
| kadonotakashi | 0:8fdf9a60065b | 177 | * | | |The counter unit is ETU base. |
| kadonotakashi | 0:8fdf9a60065b | 178 | * | | |0 = Stops counting. |
| kadonotakashi | 0:8fdf9a60065b | 179 | * | | |1 = Start counting. |
| kadonotakashi | 0:8fdf9a60065b | 180 | * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only |
| kadonotakashi | 0:8fdf9a60065b | 181 | * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. |
| kadonotakashi | 0:8fdf9a60065b | 182 | * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware. |
| kadonotakashi | 0:8fdf9a60065b | 183 | * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. |
| kadonotakashi | 0:8fdf9a60065b | 184 | * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 185 | * | | |This bit enables Timer 2 to start counting |
| kadonotakashi | 0:8fdf9a60065b | 186 | * | | |User can fill 0 to stop it and set 1 to reload and count |
| kadonotakashi | 0:8fdf9a60065b | 187 | * | | |The counter unit is ETU base. |
| kadonotakashi | 0:8fdf9a60065b | 188 | * | | |0 = Stops counting. |
| kadonotakashi | 0:8fdf9a60065b | 189 | * | | |1 = Start counting. |
| kadonotakashi | 0:8fdf9a60065b | 190 | * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only |
| kadonotakashi | 0:8fdf9a60065b | 191 | * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. |
| kadonotakashi | 0:8fdf9a60065b | 192 | * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware. |
| kadonotakashi | 0:8fdf9a60065b | 193 | * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. |
| kadonotakashi | 0:8fdf9a60065b | 194 | * |[9:8] |INITSEL |Initial Timing Selection |
| kadonotakashi | 0:8fdf9a60065b | 195 | * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation. |
| kadonotakashi | 0:8fdf9a60065b | 196 | * | | |The unit of initial timing is SC module clock. |
| kadonotakashi | 0:8fdf9a60065b | 197 | * | | |Activation: refer to SC Activation Sequence in Figure 6.17-4 SC Activation Sequence. |
| kadonotakashi | 0:8fdf9a60065b | 198 | * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5 SC Warm Reset Sequence. |
| kadonotakashi | 0:8fdf9a60065b | 199 | * | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6 SC Deactivation Sequence. |
| kadonotakashi | 0:8fdf9a60065b | 200 | * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles. |
| kadonotakashi | 0:8fdf9a60065b | 201 | * |[11] |ADACEN |Auto Deactivation When Card Removal |
| kadonotakashi | 0:8fdf9a60065b | 202 | * | | |This bit is used for enable hardware auto deactivation when smart card is removed. |
| kadonotakashi | 0:8fdf9a60065b | 203 | * | | |0 = Auto deactivation Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 204 | * | | |1 = Auto deactivation Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 205 | * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set |
| kadonotakashi | 0:8fdf9a60065b | 206 | * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. |
| kadonotakashi | 0:8fdf9a60065b | 207 | * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 208 | * | | |This bit enables the receiver block guard time function. |
| kadonotakashi | 0:8fdf9a60065b | 209 | * | | |0 = Receiver block guard time function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 210 | * | | |1 = Receiver block guard time function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 211 | * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 212 | * | | |This bit indicates the timer counter status of timer0. |
| kadonotakashi | 0:8fdf9a60065b | 213 | * | | |0 = Timer0 is not active. |
| kadonotakashi | 0:8fdf9a60065b | 214 | * | | |1 = Timer0 is active. |
| kadonotakashi | 0:8fdf9a60065b | 215 | * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). |
| kadonotakashi | 0:8fdf9a60065b | 216 | * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 217 | * | | |This bit indicates the timer counter status of timer1. |
| kadonotakashi | 0:8fdf9a60065b | 218 | * | | |0 = Timer1 is not active. |
| kadonotakashi | 0:8fdf9a60065b | 219 | * | | |1 = Timer1 is active. |
| kadonotakashi | 0:8fdf9a60065b | 220 | * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). |
| kadonotakashi | 0:8fdf9a60065b | 221 | * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 222 | * | | |This bit indicates the timer counter status of timer2. |
| kadonotakashi | 0:8fdf9a60065b | 223 | * | | |0 = Timer2 is not active. |
| kadonotakashi | 0:8fdf9a60065b | 224 | * | | |1 = Timer2 is active. |
| kadonotakashi | 0:8fdf9a60065b | 225 | * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). |
| kadonotakashi | 0:8fdf9a60065b | 226 | * |[31] |SYNC |SYNC Flag Indicator (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 227 | * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. |
| kadonotakashi | 0:8fdf9a60065b | 228 | * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register. |
| kadonotakashi | 0:8fdf9a60065b | 229 | * | | |1 = Last value is synchronizing. |
| kadonotakashi | 0:8fdf9a60065b | 230 | * @var SC_T::EGT |
| kadonotakashi | 0:8fdf9a60065b | 231 | * Offset: 0x0C SC Extra Guard Time Register |
| kadonotakashi | 0:8fdf9a60065b | 232 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 233 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 234 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 235 | * |[7:0] |EGT |Extra Guard Time |
| kadonotakashi | 0:8fdf9a60065b | 236 | * | | |This field indicates the extra guard time value. |
| kadonotakashi | 0:8fdf9a60065b | 237 | * | | |Note: The extra guard time unit is ETU base. |
| kadonotakashi | 0:8fdf9a60065b | 238 | * @var SC_T::RXTOUT |
| kadonotakashi | 0:8fdf9a60065b | 239 | * Offset: 0x10 SC Receive Buffer Time-out Counter Register |
| kadonotakashi | 0:8fdf9a60065b | 240 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 241 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 242 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 243 | * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter |
| kadonotakashi | 0:8fdf9a60065b | 244 | * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data |
| kadonotakashi | 0:8fdf9a60065b | 245 | * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled. |
| kadonotakashi | 0:8fdf9a60065b | 246 | * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5. |
| kadonotakashi | 0:8fdf9a60065b | 247 | * | | |Note2: Filling in all 0 to this field indicates to disable this function. |
| kadonotakashi | 0:8fdf9a60065b | 248 | * @var SC_T::ETUCTL |
| kadonotakashi | 0:8fdf9a60065b | 249 | * Offset: 0x14 SC Element Time Unit Control Register |
| kadonotakashi | 0:8fdf9a60065b | 250 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 251 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 252 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 253 | * |[11:0] |ETURDIV |ETU Rate Divider |
| kadonotakashi | 0:8fdf9a60065b | 254 | * | | |The field is used for ETU clock rate divider. |
| kadonotakashi | 0:8fdf9a60065b | 255 | * | | |The real ETU is ETURDIV + 1. |
| kadonotakashi | 0:8fdf9a60065b | 256 | * | | |Note: User can configure this field, but this field must be greater than 0x04. |
| kadonotakashi | 0:8fdf9a60065b | 257 | * @var SC_T::INTEN |
| kadonotakashi | 0:8fdf9a60065b | 258 | * Offset: 0x18 SC Interrupt Enable Control Register |
| kadonotakashi | 0:8fdf9a60065b | 259 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 260 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 261 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 262 | * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 263 | * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 264 | * | | |0 = Receive data reach trigger level interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 265 | * | | |1 = Receive data reach trigger level interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 266 | * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 267 | * | | |This field is used to enable transmit buffer empty interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 268 | * | | |0 = Transmit buffer empty interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 269 | * | | |1 = Transmit buffer empty interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 270 | * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 271 | * | | |This field is used to enable transfer error interrupt |
| kadonotakashi | 0:8fdf9a60065b | 272 | * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]). |
| kadonotakashi | 0:8fdf9a60065b | 273 | * | | |0 = Transfer error interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 274 | * | | |1 = Transfer error interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 275 | * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 276 | * | | |This field is used to enable Timer0 interrupt function. |
| kadonotakashi | 0:8fdf9a60065b | 277 | * | | |0 = Timer0 interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 278 | * | | |1 = Timer0 interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 279 | * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 280 | * | | |This field is used to enable the Timer1 interrupt function. |
| kadonotakashi | 0:8fdf9a60065b | 281 | * | | |0 = Timer1 interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 282 | * | | |1 = Timer1 interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 283 | * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 284 | * | | |This field is used to enable Timer2 interrupt function. |
| kadonotakashi | 0:8fdf9a60065b | 285 | * | | |0 = Timer2 interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 286 | * | | |1 = Timer2 interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 287 | * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 288 | * | | |This field is used to enable block guard time interrupt in receive direction. |
| kadonotakashi | 0:8fdf9a60065b | 289 | * | | |0 = Block guard time interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 290 | * | | |1 = Block guard time interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 291 | * | | |Note: This bit is valid only for receive receive direction block guard time. |
| kadonotakashi | 0:8fdf9a60065b | 292 | * |[7] |CDIEN |Card Detect Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 293 | * | | |This field is used to enable card detect interrupt |
| kadonotakashi | 0:8fdf9a60065b | 294 | * | | |The card detect status is CDPINSTS (SCn_STATUS[13]). |
| kadonotakashi | 0:8fdf9a60065b | 295 | * | | |0 = Card detect interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 296 | * | | |1 = Card detect interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 297 | * |[8] |INITIEN |Initial End Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 298 | * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 299 | * | | |0 = Initial end interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 300 | * | | |1 = Initial end interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 301 | * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 302 | * | | |This field is used to enable receiver buffer time-out interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 303 | * | | |0 = Receiver buffer time-out interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 304 | * | | |1 = Receiver buffer time-out interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 305 | * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 306 | * | | |This field is used to enable auto-convention error interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 307 | * | | |0 = Auto-convention error interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 308 | * | | |1 = Auto-convention error interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 309 | * @var SC_T::INTSTS |
| kadonotakashi | 0:8fdf9a60065b | 310 | * Offset: 0x1C SC Interrupt Status Register |
| kadonotakashi | 0:8fdf9a60065b | 311 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 312 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 313 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 314 | * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 315 | * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag. |
| kadonotakashi | 0:8fdf9a60065b | 316 | * | | |0 = Number of receive buffer is less than RXTRGLV setting. |
| kadonotakashi | 0:8fdf9a60065b | 317 | * | | |1 = Number of receive buffer data equals the RXTRGLV setting. |
| kadonotakashi | 0:8fdf9a60065b | 318 | * | | |Note: This bit is read only |
| kadonotakashi | 0:8fdf9a60065b | 319 | * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically. |
| kadonotakashi | 0:8fdf9a60065b | 320 | * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 321 | * | | |This field is used for transmit buffer empty interrupt status flag. |
| kadonotakashi | 0:8fdf9a60065b | 322 | * | | |0 = Transmit buffer is not empty. |
| kadonotakashi | 0:8fdf9a60065b | 323 | * | | |1 = Transmit buffer is empty. |
| kadonotakashi | 0:8fdf9a60065b | 324 | * | | |Note: This bit is read only |
| kadonotakashi | 0:8fdf9a60065b | 325 | * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically. |
| kadonotakashi | 0:8fdf9a60065b | 326 | * |[2] |TERRIF |Transfer Error Interrupt Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 327 | * | | |This field is used for transfer error interrupt status flag |
| kadonotakashi | 0:8fdf9a60065b | 328 | * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]). |
| kadonotakashi | 0:8fdf9a60065b | 329 | * | | |0 = Transfer error interrupt did not occur. |
| kadonotakashi | 0:8fdf9a60065b | 330 | * | | |1 = Transfer error interrupt occurred. |
| kadonotakashi | 0:8fdf9a60065b | 331 | * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR. |
| kadonotakashi | 0:8fdf9a60065b | 332 | * | | |Note2: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 333 | * |[3] |TMR0IF |Timer0 Interrupt Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 334 | * | | |This field is used for Timer0 interrupt status flag. |
| kadonotakashi | 0:8fdf9a60065b | 335 | * | | |0 = Timer0 interrupt did not occur. |
| kadonotakashi | 0:8fdf9a60065b | 336 | * | | |1 = Timer0 interrupt occurred. |
| kadonotakashi | 0:8fdf9a60065b | 337 | * | | |Note: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 338 | * |[4] |TMR1IF |Timer1 Interrupt Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 339 | * | | |This field is used for Timer1 interrupt status flag. |
| kadonotakashi | 0:8fdf9a60065b | 340 | * | | |0 = Timer1 interrupt did not occur. |
| kadonotakashi | 0:8fdf9a60065b | 341 | * | | |1 = Timer1 interrupt occurred. |
| kadonotakashi | 0:8fdf9a60065b | 342 | * | | |Note: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 343 | * |[5] |TMR2IF |Timer2 Interrupt Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 344 | * | | |This field is used for Timer2 interrupt status flag. |
| kadonotakashi | 0:8fdf9a60065b | 345 | * | | |0 = Timer2 interrupt did not occur. |
| kadonotakashi | 0:8fdf9a60065b | 346 | * | | |1 = Timer2 interrupt occurred. |
| kadonotakashi | 0:8fdf9a60065b | 347 | * | | |Note: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 348 | * |[6] |BGTIF |Block Guard Time Interrupt Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 349 | * | | |This field is used for indicate block guard time interrupt status flag in receive direction. |
| kadonotakashi | 0:8fdf9a60065b | 350 | * | | |0 = Block guard time interrupt did not occur. |
| kadonotakashi | 0:8fdf9a60065b | 351 | * | | |1 = Block guard time interrupt occurred. |
| kadonotakashi | 0:8fdf9a60065b | 352 | * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled. |
| kadonotakashi | 0:8fdf9a60065b | 353 | * | | |Note2: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 354 | * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 355 | * | | |This field is used for card detect interrupt status flag |
| kadonotakashi | 0:8fdf9a60065b | 356 | * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]). |
| kadonotakashi | 0:8fdf9a60065b | 357 | * | | |0 = Card detect event did not occur. |
| kadonotakashi | 0:8fdf9a60065b | 358 | * | | |1 = Card detect event occurred. |
| kadonotakashi | 0:8fdf9a60065b | 359 | * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. |
| kadonotakashi | 0:8fdf9a60065b | 360 | * |[8] |INITIF |Initial End Interrupt Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 361 | * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag. |
| kadonotakashi | 0:8fdf9a60065b | 362 | * | | |0 = Initial sequence is not complete. |
| kadonotakashi | 0:8fdf9a60065b | 363 | * | | |1 = Initial sequence is completed. |
| kadonotakashi | 0:8fdf9a60065b | 364 | * | | |Note: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 365 | * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 366 | * | | |This field is used for indicate receive buffer time-out interrupt status flag. |
| kadonotakashi | 0:8fdf9a60065b | 367 | * | | |0 = Receive buffer time-out interrupt did not occur. |
| kadonotakashi | 0:8fdf9a60065b | 368 | * | | |1 = Receive buffer time-out interrupt occurred. |
| kadonotakashi | 0:8fdf9a60065b | 369 | * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it. |
| kadonotakashi | 0:8fdf9a60065b | 370 | * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 371 | * | | |This field indicates auto convention sequence error. |
| kadonotakashi | 0:8fdf9a60065b | 372 | * | | |0 = Received TS at ATR state is 0x3B or 0x3F. |
| kadonotakashi | 0:8fdf9a60065b | 373 | * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F. |
| kadonotakashi | 0:8fdf9a60065b | 374 | * | | |Note: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 375 | * @var SC_T::STATUS |
| kadonotakashi | 0:8fdf9a60065b | 376 | * Offset: 0x20 SC Transfer Status Register |
| kadonotakashi | 0:8fdf9a60065b | 377 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 378 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 379 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 380 | * |[0] |RXOV |Receive Overflow Error Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 381 | * | | |This bit is set when Rx buffer overflow. |
| kadonotakashi | 0:8fdf9a60065b | 382 | * | | |0 = Rx buffer is not overflow. |
| kadonotakashi | 0:8fdf9a60065b | 383 | * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes). |
| kadonotakashi | 0:8fdf9a60065b | 384 | * | | |Note: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 385 | * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 386 | * | | |This bit indicates Rx buffer empty or not. |
| kadonotakashi | 0:8fdf9a60065b | 387 | * | | |0 = Rx buffer is not empty. |
| kadonotakashi | 0:8fdf9a60065b | 388 | * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU. |
| kadonotakashi | 0:8fdf9a60065b | 389 | * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 390 | * | | |This bit indicates Rx buffer full or not. |
| kadonotakashi | 0:8fdf9a60065b | 391 | * | | |0 = Rx buffer count is less than 4. |
| kadonotakashi | 0:8fdf9a60065b | 392 | * | | |1 = Rx buffer count equals to 4. |
| kadonotakashi | 0:8fdf9a60065b | 393 | * |[4] |PEF |Receiver Parity Error Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 394 | * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. |
| kadonotakashi | 0:8fdf9a60065b | 395 | * | | |0 = Receiver parity error flag did not occur. |
| kadonotakashi | 0:8fdf9a60065b | 396 | * | | |1 = Receiver parity error flag occurred. |
| kadonotakashi | 0:8fdf9a60065b | 397 | * | | |Note1: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 398 | * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. |
| kadonotakashi | 0:8fdf9a60065b | 399 | * |[5] |FEF |Receiver Frame Error Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 400 | * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). |
| kadonotakashi | 0:8fdf9a60065b | 401 | * | | |0 = Receiver frame error flag did not occur. |
| kadonotakashi | 0:8fdf9a60065b | 402 | * | | |1 = Receiver frame error flag occurred. |
| kadonotakashi | 0:8fdf9a60065b | 403 | * | | |Note1: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 404 | * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. |
| kadonotakashi | 0:8fdf9a60065b | 405 | * |[6] |BEF |Receiver Break Error Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 406 | * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bits). |
| kadonotakashi | 0:8fdf9a60065b | 407 | * | | |0 = Receiver break error flag did not occur. |
| kadonotakashi | 0:8fdf9a60065b | 408 | * | | |1 = Receiver break error flag occurred. |
| kadonotakashi | 0:8fdf9a60065b | 409 | * | | |Note1: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 410 | * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. |
| kadonotakashi | 0:8fdf9a60065b | 411 | * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag |
| kadonotakashi | 0:8fdf9a60065b | 412 | * | | |This bit is set when Tx buffer overflow. |
| kadonotakashi | 0:8fdf9a60065b | 413 | * | | |0 = Tx buffer is not overflow. |
| kadonotakashi | 0:8fdf9a60065b | 414 | * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]). |
| kadonotakashi | 0:8fdf9a60065b | 415 | * | | |Note: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 416 | * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 417 | * | | |This bit indicates TX buffer empty or not. |
| kadonotakashi | 0:8fdf9a60065b | 418 | * | | |0 = Tx buffer is not empty. |
| kadonotakashi | 0:8fdf9a60065b | 419 | * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register. |
| kadonotakashi | 0:8fdf9a60065b | 420 | * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). |
| kadonotakashi | 0:8fdf9a60065b | 421 | * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 422 | * | | |This bit indicates Tx buffer full or not. |
| kadonotakashi | 0:8fdf9a60065b | 423 | * | | |0 = Tx buffer count is less than 4. |
| kadonotakashi | 0:8fdf9a60065b | 424 | * | | |1 = Tx buffer count equals to 4. |
| kadonotakashi | 0:8fdf9a60065b | 425 | * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin |
| kadonotakashi | 0:8fdf9a60065b | 426 | * | | |This bit is set whenever card has been removal. |
| kadonotakashi | 0:8fdf9a60065b | 427 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 428 | * | | |1 = Card removed. |
| kadonotakashi | 0:8fdf9a60065b | 429 | * | | |Note1: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 430 | * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set. |
| kadonotakashi | 0:8fdf9a60065b | 431 | * |[12] |CINSERT |Card Insert Status of SCn_CD Pin |
| kadonotakashi | 0:8fdf9a60065b | 432 | * | | |This bit is set whenever card has been inserted. |
| kadonotakashi | 0:8fdf9a60065b | 433 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 434 | * | | |1 = Card insert. |
| kadonotakashi | 0:8fdf9a60065b | 435 | * | | |Note1: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 436 | * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set. |
| kadonotakashi | 0:8fdf9a60065b | 437 | * |[13] |CDPINSTS |Card Detect Pin Status (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 438 | * | | |This bit is the pin status of SCn_CD. |
| kadonotakashi | 0:8fdf9a60065b | 439 | * | | |0 = The SCn_CD pin state at low. |
| kadonotakashi | 0:8fdf9a60065b | 440 | * | | |1 = The SCn_CD pin state at high. |
| kadonotakashi | 0:8fdf9a60065b | 441 | * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 442 | * | | |This field indicates the Rx buffer pointer status |
| kadonotakashi | 0:8fdf9a60065b | 443 | * | | |When SC controller receives one byte from external device, RXPOINT increases one |
| kadonotakashi | 0:8fdf9a60065b | 444 | * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one. |
| kadonotakashi | 0:8fdf9a60065b | 445 | * |[21] |RXRERR |Receiver Retry Error |
| kadonotakashi | 0:8fdf9a60065b | 446 | * | | |This bit is used for receiver error retry and set by hardware. |
| kadonotakashi | 0:8fdf9a60065b | 447 | * | | |0 = No Rx retry transfer. |
| kadonotakashi | 0:8fdf9a60065b | 448 | * | | |1 = Rx has any error and retries transfer. |
| kadonotakashi | 0:8fdf9a60065b | 449 | * | | |Note1: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 450 | * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. |
| kadonotakashi | 0:8fdf9a60065b | 451 | * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. |
| kadonotakashi | 0:8fdf9a60065b | 452 | * |[22] |RXOVERR |Receiver over Retry Error |
| kadonotakashi | 0:8fdf9a60065b | 453 | * | | |This bit is used for receiver retry counts over than retry number limitation. |
| kadonotakashi | 0:8fdf9a60065b | 454 | * | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1. |
| kadonotakashi | 0:8fdf9a60065b | 455 | * | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1. |
| kadonotakashi | 0:8fdf9a60065b | 456 | * | | |Note1: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 457 | * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. |
| kadonotakashi | 0:8fdf9a60065b | 458 | * |[23] |RXACT |Receiver in Active Status Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 459 | * | | |This bit indicates Rx transfer status. |
| kadonotakashi | 0:8fdf9a60065b | 460 | * | | |0 = This bit is cleared automatically when Rx transfer is finished. |
| kadonotakashi | 0:8fdf9a60065b | 461 | * | | |1 = This bit is set by hardware when Rx transfer is in active. |
| kadonotakashi | 0:8fdf9a60065b | 462 | * | | |Note: This bit is read only. |
| kadonotakashi | 0:8fdf9a60065b | 463 | * | | |Note2: |
| kadonotakashi | 0:8fdf9a60065b | 464 | * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 465 | * | | |This field indicates the Tx buffer pointer status |
| kadonotakashi | 0:8fdf9a60065b | 466 | * | | |When CPU writes data into SCn_DAT, TXPOINT increases one |
| kadonotakashi | 0:8fdf9a60065b | 467 | * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. |
| kadonotakashi | 0:8fdf9a60065b | 468 | * |[29] |TXRERR |Transmitter Retry Error |
| kadonotakashi | 0:8fdf9a60065b | 469 | * | | |This bit is used for indicate transmitter error retry and set by hardware.. |
| kadonotakashi | 0:8fdf9a60065b | 470 | * | | |0 = No Tx retry transfer. |
| kadonotakashi | 0:8fdf9a60065b | 471 | * | | |1 = Tx has any error and retries transfer. |
| kadonotakashi | 0:8fdf9a60065b | 472 | * | | |Note1: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 473 | * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU. |
| kadonotakashi | 0:8fdf9a60065b | 474 | * |[30] |TXOVERR |Transmitter over Retry Error |
| kadonotakashi | 0:8fdf9a60065b | 475 | * | | |This bit is used for transmitter retry counts over than retry number limitation. |
| kadonotakashi | 0:8fdf9a60065b | 476 | * | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1. |
| kadonotakashi | 0:8fdf9a60065b | 477 | * | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1. |
| kadonotakashi | 0:8fdf9a60065b | 478 | * | | |Note: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 479 | * |[31] |TXACT |Transmit in Active Status Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 480 | * | | |This bit indicates Tx transmit status. |
| kadonotakashi | 0:8fdf9a60065b | 481 | * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed. |
| kadonotakashi | 0:8fdf9a60065b | 482 | * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted. |
| kadonotakashi | 0:8fdf9a60065b | 483 | * | | |Note: This bit is read only. |
| kadonotakashi | 0:8fdf9a60065b | 484 | * @var SC_T::PINCTL |
| kadonotakashi | 0:8fdf9a60065b | 485 | * Offset: 0x24 SC Pin Control State Register |
| kadonotakashi | 0:8fdf9a60065b | 486 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 487 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 488 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 489 | * |[0] |PWREN |SCn_PWR Pin Signal |
| kadonotakashi | 0:8fdf9a60065b | 490 | * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level. |
| kadonotakashi | 0:8fdf9a60065b | 491 | * | | |Write this field to drive SCn_PWR pin |
| kadonotakashi | 0:8fdf9a60065b | 492 | * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. |
| kadonotakashi | 0:8fdf9a60065b | 493 | * | | |Read this field to get SCn_PWR signal status. |
| kadonotakashi | 0:8fdf9a60065b | 494 | * | | |0 = SCn_PWR signal status is low. |
| kadonotakashi | 0:8fdf9a60065b | 495 | * | | |1 = SCn_PWR signal status is high. |
| kadonotakashi | 0:8fdf9a60065b | 496 | * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically |
| kadonotakashi | 0:8fdf9a60065b | 497 | * | | |Thus, do not fill in this field when operating in these modes. |
| kadonotakashi | 0:8fdf9a60065b | 498 | * |[1] |RSTEN |SCn_RST Pin Signal |
| kadonotakashi | 0:8fdf9a60065b | 499 | * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level. |
| kadonotakashi | 0:8fdf9a60065b | 500 | * | | |Write this field to drive SCn_RST pin. |
| kadonotakashi | 0:8fdf9a60065b | 501 | * | | |0 = Drive SCn_RST pin to low. |
| kadonotakashi | 0:8fdf9a60065b | 502 | * | | |1 = Drive SCn_RST pin to high. |
| kadonotakashi | 0:8fdf9a60065b | 503 | * | | |Read this field to get SCn_RST signal status. |
| kadonotakashi | 0:8fdf9a60065b | 504 | * | | |0 = SCn_RST signal status is low. |
| kadonotakashi | 0:8fdf9a60065b | 505 | * | | |1 = SCn_RST signal status is high. |
| kadonotakashi | 0:8fdf9a60065b | 506 | * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically |
| kadonotakashi | 0:8fdf9a60065b | 507 | * | | |Thus, do not fill in this field when operating in these modes. |
| kadonotakashi | 0:8fdf9a60065b | 508 | * |[5] |CSTOPLV |SCn_CLK Pin Stop Level |
| kadonotakashi | 0:8fdf9a60065b | 509 | * | | |This field indicates the SCn_CLK pin status when SC clock in clock stop mode. |
| kadonotakashi | 0:8fdf9a60065b | 510 | * | | |0 = SCn_CLK pin keeps at low when SC clock stopped. |
| kadonotakashi | 0:8fdf9a60065b | 511 | * | | |1 = SCn_CLK pin keeps at high when SC clock stopped. |
| kadonotakashi | 0:8fdf9a60065b | 512 | * |[6] |CLKKEEP |SC Clock Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 513 | * | | |0 = SC clock generation Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 514 | * | | |1 = SC clock always keeps free running. |
| kadonotakashi | 0:8fdf9a60065b | 515 | * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically |
| kadonotakashi | 0:8fdf9a60065b | 516 | * | | |Thus, do not fill in this field when operating in these modes. |
| kadonotakashi | 0:8fdf9a60065b | 517 | * |[9] |SCDATA |SCn_DATA Pin Signal |
| kadonotakashi | 0:8fdf9a60065b | 518 | * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit. |
| kadonotakashi | 0:8fdf9a60065b | 519 | * | | |0 = Drive SCn_DATA pin to low. |
| kadonotakashi | 0:8fdf9a60065b | 520 | * | | |1 = Drive SCn_DATA pin to high. |
| kadonotakashi | 0:8fdf9a60065b | 521 | * | | |Read this field to get SCn_DATA signal status. |
| kadonotakashi | 0:8fdf9a60065b | 522 | * | | |0 = SCn_DATA signal status is low. |
| kadonotakashi | 0:8fdf9a60065b | 523 | * | | |1 = SCn_DATA signal status is high. |
| kadonotakashi | 0:8fdf9a60065b | 524 | * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically |
| kadonotakashi | 0:8fdf9a60065b | 525 | * | | |Thus, do not fill in this field when SC is in these modes. |
| kadonotakashi | 0:8fdf9a60065b | 526 | * |[11] |PWRINV |SCn_PWR Pin Inverse |
| kadonotakashi | 0:8fdf9a60065b | 527 | * | | |This bit is used for inverse the SCn_PWR pin. |
| kadonotakashi | 0:8fdf9a60065b | 528 | * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). |
| kadonotakashi | 0:8fdf9a60065b | 529 | * | | |0 = SCn_PWR pin inverse Disabled |
| kadonotakashi | 0:8fdf9a60065b | 530 | * | | |If PWREN is 1, SCn_PWR pin status is 1; if PWREN is 0, SCn_PWR pin status is 0. |
| kadonotakashi | 0:8fdf9a60065b | 531 | * | | |1 = SCn_PWR pin inverse Enabled |
| kadonotakashi | 0:8fdf9a60065b | 532 | * | | |If PWREN is 1, SCn_PWR pin status is 0; if PWREN is 0, SCn_PWR pin status is 1. |
| kadonotakashi | 0:8fdf9a60065b | 533 | * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). |
| kadonotakashi | 0:8fdf9a60065b | 534 | * |[16] |DATASTS |SCn_DATA Pin Status (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 535 | * | | |This bit is the pin status of SCn_DATA. |
| kadonotakashi | 0:8fdf9a60065b | 536 | * | | |0 = The SCn_DATA pin status is low. |
| kadonotakashi | 0:8fdf9a60065b | 537 | * | | |1 = The SCn_DATA pin status is high. |
| kadonotakashi | 0:8fdf9a60065b | 538 | * | | |Note: |
| kadonotakashi | 0:8fdf9a60065b | 539 | * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 540 | * | | |This bit is the pin status of SCn_PWR. |
| kadonotakashi | 0:8fdf9a60065b | 541 | * | | |0 = SCn_PWR pin to low. |
| kadonotakashi | 0:8fdf9a60065b | 542 | * | | |1 = SCn_PWR pin to high. |
| kadonotakashi | 0:8fdf9a60065b | 543 | * |[18] |RSTSTS |SCn_RST Pin Status (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 544 | * | | |This bit is the pin status of SCn_RST. |
| kadonotakashi | 0:8fdf9a60065b | 545 | * | | |0 = SCn_RST pin is low. |
| kadonotakashi | 0:8fdf9a60065b | 546 | * | | |1 = SCn_RST pin is high. |
| kadonotakashi | 0:8fdf9a60065b | 547 | * |[30] |SYNC |SYNC Flag Indicator (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 548 | * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. |
| kadonotakashi | 0:8fdf9a60065b | 549 | * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register. |
| kadonotakashi | 0:8fdf9a60065b | 550 | * | | |1 = Last value is synchronizing. |
| kadonotakashi | 0:8fdf9a60065b | 551 | * @var SC_T::TMRCTL0 |
| kadonotakashi | 0:8fdf9a60065b | 552 | * Offset: 0x28 SC Internal Timer0 Control Register |
| kadonotakashi | 0:8fdf9a60065b | 553 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 554 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 555 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 556 | * |[23:0] |CNT |Timer0 Counter Value |
| kadonotakashi | 0:8fdf9a60065b | 557 | * | | |This field indicates the internal Timer0 counter values. |
| kadonotakashi | 0:8fdf9a60065b | 558 | * | | |Note: Unit of Timer0 counter is ETU base. |
| kadonotakashi | 0:8fdf9a60065b | 559 | * |[27:24] |OPMODE |Timer0 Operation Mode Selection |
| kadonotakashi | 0:8fdf9a60065b | 560 | * | | |This field indicates the internal 24-bit Timer0 operation selection. |
| kadonotakashi | 0:8fdf9a60065b | 561 | * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer0. |
| kadonotakashi | 0:8fdf9a60065b | 562 | * |[31] |SYNC |SYNC Flag Indicator (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 563 | * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. |
| kadonotakashi | 0:8fdf9a60065b | 564 | * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register. |
| kadonotakashi | 0:8fdf9a60065b | 565 | * | | |1 = Last value is synchronizing. |
| kadonotakashi | 0:8fdf9a60065b | 566 | * @var SC_T::TMRCTL1 |
| kadonotakashi | 0:8fdf9a60065b | 567 | * Offset: 0x2C SC Internal Timer1 Control Register |
| kadonotakashi | 0:8fdf9a60065b | 568 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 569 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 570 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 571 | * |[7:0] |CNT |Timer 1 Counter Value |
| kadonotakashi | 0:8fdf9a60065b | 572 | * | | |This field indicates the internal Timer1 counter values. |
| kadonotakashi | 0:8fdf9a60065b | 573 | * | | |Note: Unit of Timer1 counter is ETU base. |
| kadonotakashi | 0:8fdf9a60065b | 574 | * |[27:24] |OPMODE |Timer 1 Operation Mode Selection |
| kadonotakashi | 0:8fdf9a60065b | 575 | * | | |This field indicates the internal 8-bit Timer1 operation selection. |
| kadonotakashi | 0:8fdf9a60065b | 576 | * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer1. |
| kadonotakashi | 0:8fdf9a60065b | 577 | * |[31] |SYNC |SYNC Flag Indicator (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 578 | * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. |
| kadonotakashi | 0:8fdf9a60065b | 579 | * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register. |
| kadonotakashi | 0:8fdf9a60065b | 580 | * | | |1 = Last value is synchronizing. |
| kadonotakashi | 0:8fdf9a60065b | 581 | * @var SC_T::TMRCTL2 |
| kadonotakashi | 0:8fdf9a60065b | 582 | * Offset: 0x30 SC Internal Timer2 Control Register |
| kadonotakashi | 0:8fdf9a60065b | 583 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 584 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 585 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 586 | * |[7:0] |CNT |Timer 2 Counter Value |
| kadonotakashi | 0:8fdf9a60065b | 587 | * | | |This field indicates the internal Timer2 counter values. |
| kadonotakashi | 0:8fdf9a60065b | 588 | * | | |Note: Unit of Timer2 counter is ETU base. |
| kadonotakashi | 0:8fdf9a60065b | 589 | * |[27:24] |OPMODE |Timer 2 Operation Mode Selection |
| kadonotakashi | 0:8fdf9a60065b | 590 | * | | |This field indicates the internal 8-bit Timer2 operation selection |
| kadonotakashi | 0:8fdf9a60065b | 591 | * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer2. |
| kadonotakashi | 0:8fdf9a60065b | 592 | * |[31] |SYNC |SYNC Flag Indicator (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 593 | * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. |
| kadonotakashi | 0:8fdf9a60065b | 594 | * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register. |
| kadonotakashi | 0:8fdf9a60065b | 595 | * | | |1 = Last value is synchronizing. |
| kadonotakashi | 0:8fdf9a60065b | 596 | * @var SC_T::UARTCTL |
| kadonotakashi | 0:8fdf9a60065b | 597 | * Offset: 0x34 SC UART Mode Control Register |
| kadonotakashi | 0:8fdf9a60065b | 598 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 599 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 600 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 601 | * |[0] |UARTEN |UART Mode Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 602 | * | | |Sets this bit to enable UART mode function. |
| kadonotakashi | 0:8fdf9a60065b | 603 | * | | |0 = Smart Card mode. |
| kadonotakashi | 0:8fdf9a60065b | 604 | * | | |1 = UART mode. |
| kadonotakashi | 0:8fdf9a60065b | 605 | * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0. |
| kadonotakashi | 0:8fdf9a60065b | 606 | * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0. |
| kadonotakashi | 0:8fdf9a60065b | 607 | * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. |
| kadonotakashi | 0:8fdf9a60065b | 608 | * |[5:4] |WLS |Word Length Selection |
| kadonotakashi | 0:8fdf9a60065b | 609 | * | | |This field is used for select UART data length. |
| kadonotakashi | 0:8fdf9a60065b | 610 | * | | |00 = Word length is 8 bits. |
| kadonotakashi | 0:8fdf9a60065b | 611 | * | | |01 = Word length is 7 bits. |
| kadonotakashi | 0:8fdf9a60065b | 612 | * | | |10 = Word length is 6 bits. |
| kadonotakashi | 0:8fdf9a60065b | 613 | * | | |11 = Word length is 5 bits. |
| kadonotakashi | 0:8fdf9a60065b | 614 | * | | |Note: In smart card mode, this WLS must be u201800'. |
| kadonotakashi | 0:8fdf9a60065b | 615 | * |[6] |PBOFF |Parity Bit Disable Control |
| kadonotakashi | 0:8fdf9a60065b | 616 | * | | |Sets this bit is used for disable parity check function. |
| kadonotakashi | 0:8fdf9a60065b | 617 | * | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. |
| kadonotakashi | 0:8fdf9a60065b | 618 | * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. |
| kadonotakashi | 0:8fdf9a60065b | 619 | * | | |Note: In smart card mode, this field must be u20180' (default setting is with parity bit). |
| kadonotakashi | 0:8fdf9a60065b | 620 | * |[7] |OPE |Odd Parity Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 621 | * | | |This is used for odd/even parity selection. |
| kadonotakashi | 0:8fdf9a60065b | 622 | * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. |
| kadonotakashi | 0:8fdf9a60065b | 623 | * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. |
| kadonotakashi | 0:8fdf9a60065b | 624 | * | | |Note: This bit has effect only when PBOFF bit is u20180'. |
| kadonotakashi | 0:8fdf9a60065b | 625 | * @var SC_T::ACTCTL |
| kadonotakashi | 0:8fdf9a60065b | 626 | * Offset: 0x4C SC Activation Control Register |
| kadonotakashi | 0:8fdf9a60065b | 627 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 628 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 629 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 630 | * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation |
| kadonotakashi | 0:8fdf9a60065b | 631 | * | | |This field provide the configurable cycles to extend the activation time T1 period. |
| kadonotakashi | 0:8fdf9a60065b | 632 | * | | |The cycle scaling factor is 2048. |
| kadonotakashi | 0:8fdf9a60065b | 633 | * | | |Extend cycles = (filled value * 2048) cycles. |
| kadonotakashi | 0:8fdf9a60065b | 634 | * | | |Refer to SC activation sequence in Figure 6.17-4 SC Activation Sequence. |
| kadonotakashi | 0:8fdf9a60065b | 635 | * | | |For example, |
| kadonotakashi | 0:8fdf9a60065b | 636 | * | | |SCLK = 4MHz, each cycle = 0.25us,. |
| kadonotakashi | 0:8fdf9a60065b | 637 | * | | |Filled 20 to this field |
| kadonotakashi | 0:8fdf9a60065b | 638 | * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms. |
| kadonotakashi | 0:8fdf9a60065b | 639 | * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 |
| kadonotakashi | 0:8fdf9a60065b | 640 | */ |
| kadonotakashi | 0:8fdf9a60065b | 641 | __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */ |
| kadonotakashi | 0:8fdf9a60065b | 642 | __IO uint32_t CTL; /*!< [0x0004] SC Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 643 | __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 644 | __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */ |
| kadonotakashi | 0:8fdf9a60065b | 645 | __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */ |
| kadonotakashi | 0:8fdf9a60065b | 646 | __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 647 | __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 648 | __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */ |
| kadonotakashi | 0:8fdf9a60065b | 649 | __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */ |
| kadonotakashi | 0:8fdf9a60065b | 650 | __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */ |
| kadonotakashi | 0:8fdf9a60065b | 651 | __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 652 | __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 653 | __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 654 | __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 655 | __I uint32_t RESERVE0[5]; |
| kadonotakashi | 0:8fdf9a60065b | 656 | __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 657 | |
| kadonotakashi | 0:8fdf9a60065b | 658 | } SC_T; |
| kadonotakashi | 0:8fdf9a60065b | 659 | |
| kadonotakashi | 0:8fdf9a60065b | 660 | /** |
| kadonotakashi | 0:8fdf9a60065b | 661 | @addtogroup SC_CONST SC Bit Field Definition |
| kadonotakashi | 0:8fdf9a60065b | 662 | Constant Definitions for SC Controller |
| kadonotakashi | 0:8fdf9a60065b | 663 | @{ */ |
| kadonotakashi | 0:8fdf9a60065b | 664 | |
| kadonotakashi | 0:8fdf9a60065b | 665 | #define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 666 | #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 667 | |
| kadonotakashi | 0:8fdf9a60065b | 668 | #define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 669 | #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 670 | |
| kadonotakashi | 0:8fdf9a60065b | 671 | #define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 672 | #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 673 | |
| kadonotakashi | 0:8fdf9a60065b | 674 | #define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 675 | #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 676 | |
| kadonotakashi | 0:8fdf9a60065b | 677 | #define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 678 | #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 679 | |
| kadonotakashi | 0:8fdf9a60065b | 680 | #define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 681 | #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 682 | |
| kadonotakashi | 0:8fdf9a60065b | 683 | #define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 684 | #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 685 | |
| kadonotakashi | 0:8fdf9a60065b | 686 | #define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 687 | #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 688 | |
| kadonotakashi | 0:8fdf9a60065b | 689 | #define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 690 | #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 691 | |
| kadonotakashi | 0:8fdf9a60065b | 692 | #define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */ |
| kadonotakashi | 0:8fdf9a60065b | 693 | #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 694 | |
| kadonotakashi | 0:8fdf9a60065b | 695 | #define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */ |
| kadonotakashi | 0:8fdf9a60065b | 696 | #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 697 | |
| kadonotakashi | 0:8fdf9a60065b | 698 | #define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 699 | #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 700 | |
| kadonotakashi | 0:8fdf9a60065b | 701 | #define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */ |
| kadonotakashi | 0:8fdf9a60065b | 702 | #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 703 | |
| kadonotakashi | 0:8fdf9a60065b | 704 | #define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 705 | #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 706 | |
| kadonotakashi | 0:8fdf9a60065b | 707 | #define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 708 | #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 709 | |
| kadonotakashi | 0:8fdf9a60065b | 710 | #define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 711 | #define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 712 | |
| kadonotakashi | 0:8fdf9a60065b | 713 | #define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */ |
| kadonotakashi | 0:8fdf9a60065b | 714 | #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 715 | |
| kadonotakashi | 0:8fdf9a60065b | 716 | #define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */ |
| kadonotakashi | 0:8fdf9a60065b | 717 | #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 718 | |
| kadonotakashi | 0:8fdf9a60065b | 719 | #define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */ |
| kadonotakashi | 0:8fdf9a60065b | 720 | #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 721 | |
| kadonotakashi | 0:8fdf9a60065b | 722 | #define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 723 | #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 724 | |
| kadonotakashi | 0:8fdf9a60065b | 725 | #define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 726 | #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 727 | |
| kadonotakashi | 0:8fdf9a60065b | 728 | #define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 729 | #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 730 | |
| kadonotakashi | 0:8fdf9a60065b | 731 | #define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 732 | #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 733 | |
| kadonotakashi | 0:8fdf9a60065b | 734 | #define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 735 | #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 736 | |
| kadonotakashi | 0:8fdf9a60065b | 737 | #define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 738 | #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 739 | |
| kadonotakashi | 0:8fdf9a60065b | 740 | #define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 741 | #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 742 | |
| kadonotakashi | 0:8fdf9a60065b | 743 | #define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 744 | #define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 745 | |
| kadonotakashi | 0:8fdf9a60065b | 746 | #define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 747 | #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 748 | |
| kadonotakashi | 0:8fdf9a60065b | 749 | #define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 750 | #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 751 | |
| kadonotakashi | 0:8fdf9a60065b | 752 | #define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 753 | #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 754 | |
| kadonotakashi | 0:8fdf9a60065b | 755 | #define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 756 | #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 757 | |
| kadonotakashi | 0:8fdf9a60065b | 758 | #define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */ |
| kadonotakashi | 0:8fdf9a60065b | 759 | #define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 760 | |
| kadonotakashi | 0:8fdf9a60065b | 761 | #define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 762 | #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 763 | |
| kadonotakashi | 0:8fdf9a60065b | 764 | #define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */ |
| kadonotakashi | 0:8fdf9a60065b | 765 | #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 766 | |
| kadonotakashi | 0:8fdf9a60065b | 767 | #define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 768 | #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 769 | |
| kadonotakashi | 0:8fdf9a60065b | 770 | #define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 771 | #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 772 | |
| kadonotakashi | 0:8fdf9a60065b | 773 | #define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 774 | #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 775 | |
| kadonotakashi | 0:8fdf9a60065b | 776 | #define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 777 | #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 778 | |
| kadonotakashi | 0:8fdf9a60065b | 779 | #define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 780 | #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 781 | |
| kadonotakashi | 0:8fdf9a60065b | 782 | #define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 783 | #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 784 | |
| kadonotakashi | 0:8fdf9a60065b | 785 | #define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 786 | #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 787 | |
| kadonotakashi | 0:8fdf9a60065b | 788 | #define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 789 | #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 790 | |
| kadonotakashi | 0:8fdf9a60065b | 791 | #define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 792 | #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 793 | |
| kadonotakashi | 0:8fdf9a60065b | 794 | #define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 795 | #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 796 | |
| kadonotakashi | 0:8fdf9a60065b | 797 | #define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 798 | #define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 799 | |
| kadonotakashi | 0:8fdf9a60065b | 800 | #define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 801 | #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 802 | |
| kadonotakashi | 0:8fdf9a60065b | 803 | #define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 804 | #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 805 | |
| kadonotakashi | 0:8fdf9a60065b | 806 | #define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 807 | #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 808 | |
| kadonotakashi | 0:8fdf9a60065b | 809 | #define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 810 | #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 811 | |
| kadonotakashi | 0:8fdf9a60065b | 812 | #define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 813 | #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 814 | |
| kadonotakashi | 0:8fdf9a60065b | 815 | #define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 816 | #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 817 | |
| kadonotakashi | 0:8fdf9a60065b | 818 | #define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 819 | #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 820 | |
| kadonotakashi | 0:8fdf9a60065b | 821 | #define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 822 | #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 823 | |
| kadonotakashi | 0:8fdf9a60065b | 824 | #define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 825 | #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 826 | |
| kadonotakashi | 0:8fdf9a60065b | 827 | #define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 828 | #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 829 | |
| kadonotakashi | 0:8fdf9a60065b | 830 | #define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 831 | #define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 832 | |
| kadonotakashi | 0:8fdf9a60065b | 833 | #define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 834 | #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 835 | |
| kadonotakashi | 0:8fdf9a60065b | 836 | #define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 837 | #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 838 | |
| kadonotakashi | 0:8fdf9a60065b | 839 | #define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */ |
| kadonotakashi | 0:8fdf9a60065b | 840 | #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 841 | |
| kadonotakashi | 0:8fdf9a60065b | 842 | #define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 843 | #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 844 | |
| kadonotakashi | 0:8fdf9a60065b | 845 | #define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 846 | #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 847 | |
| kadonotakashi | 0:8fdf9a60065b | 848 | #define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 849 | #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 850 | |
| kadonotakashi | 0:8fdf9a60065b | 851 | #define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 852 | #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 853 | |
| kadonotakashi | 0:8fdf9a60065b | 854 | #define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 855 | #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 856 | |
| kadonotakashi | 0:8fdf9a60065b | 857 | #define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */ |
| kadonotakashi | 0:8fdf9a60065b | 858 | #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 859 | |
| kadonotakashi | 0:8fdf9a60065b | 860 | #define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 861 | #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 862 | |
| kadonotakashi | 0:8fdf9a60065b | 863 | #define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */ |
| kadonotakashi | 0:8fdf9a60065b | 864 | #define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 865 | |
| kadonotakashi | 0:8fdf9a60065b | 866 | #define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 867 | #define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 868 | |
| kadonotakashi | 0:8fdf9a60065b | 869 | #define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */ |
| kadonotakashi | 0:8fdf9a60065b | 870 | #define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 871 | |
| kadonotakashi | 0:8fdf9a60065b | 872 | #define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 873 | #define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 874 | |
| kadonotakashi | 0:8fdf9a60065b | 875 | #define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */ |
| kadonotakashi | 0:8fdf9a60065b | 876 | #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 877 | |
| kadonotakashi | 0:8fdf9a60065b | 878 | #define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */ |
| kadonotakashi | 0:8fdf9a60065b | 879 | #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 880 | |
| kadonotakashi | 0:8fdf9a60065b | 881 | #define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 882 | #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 883 | |
| kadonotakashi | 0:8fdf9a60065b | 884 | #define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 885 | #define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 886 | |
| kadonotakashi | 0:8fdf9a60065b | 887 | #define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */ |
| kadonotakashi | 0:8fdf9a60065b | 888 | #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 889 | |
| kadonotakashi | 0:8fdf9a60065b | 890 | #define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */ |
| kadonotakashi | 0:8fdf9a60065b | 891 | #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 892 | |
| kadonotakashi | 0:8fdf9a60065b | 893 | #define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 894 | #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 895 | |
| kadonotakashi | 0:8fdf9a60065b | 896 | #define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 897 | #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 898 | |
| kadonotakashi | 0:8fdf9a60065b | 899 | #define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 900 | #define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 901 | |
| kadonotakashi | 0:8fdf9a60065b | 902 | #define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 903 | #define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 904 | |
| kadonotakashi | 0:8fdf9a60065b | 905 | #define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */ |
| kadonotakashi | 0:8fdf9a60065b | 906 | #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 907 | |
| kadonotakashi | 0:8fdf9a60065b | 908 | #define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */ |
| kadonotakashi | 0:8fdf9a60065b | 909 | #define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 910 | |
| kadonotakashi | 0:8fdf9a60065b | 911 | #define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 912 | #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 913 | |
| kadonotakashi | 0:8fdf9a60065b | 914 | #define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */ |
| kadonotakashi | 0:8fdf9a60065b | 915 | #define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 916 | |
| kadonotakashi | 0:8fdf9a60065b | 917 | #define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */ |
| kadonotakashi | 0:8fdf9a60065b | 918 | #define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 919 | |
| kadonotakashi | 0:8fdf9a60065b | 920 | #define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */ |
| kadonotakashi | 0:8fdf9a60065b | 921 | #define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 922 | |
| kadonotakashi | 0:8fdf9a60065b | 923 | #define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */ |
| kadonotakashi | 0:8fdf9a60065b | 924 | #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 925 | |
| kadonotakashi | 0:8fdf9a60065b | 926 | #define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 927 | #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 928 | |
| kadonotakashi | 0:8fdf9a60065b | 929 | #define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */ |
| kadonotakashi | 0:8fdf9a60065b | 930 | #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 931 | |
| kadonotakashi | 0:8fdf9a60065b | 932 | #define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */ |
| kadonotakashi | 0:8fdf9a60065b | 933 | #define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 934 | |
| kadonotakashi | 0:8fdf9a60065b | 935 | #define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 936 | #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 937 | |
| kadonotakashi | 0:8fdf9a60065b | 938 | #define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */ |
| kadonotakashi | 0:8fdf9a60065b | 939 | #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 940 | |
| kadonotakashi | 0:8fdf9a60065b | 941 | #define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */ |
| kadonotakashi | 0:8fdf9a60065b | 942 | #define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 943 | |
| kadonotakashi | 0:8fdf9a60065b | 944 | #define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 945 | #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 946 | |
| kadonotakashi | 0:8fdf9a60065b | 947 | #define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */ |
| kadonotakashi | 0:8fdf9a60065b | 948 | #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 949 | |
| kadonotakashi | 0:8fdf9a60065b | 950 | #define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */ |
| kadonotakashi | 0:8fdf9a60065b | 951 | #define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 952 | |
| kadonotakashi | 0:8fdf9a60065b | 953 | #define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 954 | #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 955 | |
| kadonotakashi | 0:8fdf9a60065b | 956 | #define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */ |
| kadonotakashi | 0:8fdf9a60065b | 957 | #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 958 | |
| kadonotakashi | 0:8fdf9a60065b | 959 | #define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 960 | #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 961 | |
| kadonotakashi | 0:8fdf9a60065b | 962 | #define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */ |
| kadonotakashi | 0:8fdf9a60065b | 963 | #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 964 | |
| kadonotakashi | 0:8fdf9a60065b | 965 | #define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 966 | #define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 967 | |
| kadonotakashi | 0:8fdf9a60065b | 968 | /**@}*/ /* SC_CONST */ |
| kadonotakashi | 0:8fdf9a60065b | 969 | /**@}*/ /* end of SC register group */ |
| kadonotakashi | 0:8fdf9a60065b | 970 | |
| kadonotakashi | 0:8fdf9a60065b | 971 | |
| kadonotakashi | 0:8fdf9a60065b | 972 | |
| kadonotakashi | 0:8fdf9a60065b | 973 | #endif /* __SC_REG_H__ */ |