takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/bpwm_reg.h@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /**************************************************************************//**
kadonotakashi 0:8fdf9a60065b 2 * @file bpwm_reg.h
kadonotakashi 0:8fdf9a60065b 3 * @version V1.00
kadonotakashi 0:8fdf9a60065b 4 * @brief BPWM register definition header file
kadonotakashi 0:8fdf9a60065b 5 *
kadonotakashi 0:8fdf9a60065b 6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
kadonotakashi 0:8fdf9a60065b 7 *****************************************************************************/
kadonotakashi 0:8fdf9a60065b 8 #ifndef __BPWM_REG_H__
kadonotakashi 0:8fdf9a60065b 9 #define __BPWM_REG_H__
kadonotakashi 0:8fdf9a60065b 10
kadonotakashi 0:8fdf9a60065b 11
kadonotakashi 0:8fdf9a60065b 12 /*---------------------- Basic Pulse Width Modulation Controller -------------------------*/
kadonotakashi 0:8fdf9a60065b 13 /**
kadonotakashi 0:8fdf9a60065b 14 @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM)
kadonotakashi 0:8fdf9a60065b 15 Memory Mapped Structure for BPWM Controller
kadonotakashi 0:8fdf9a60065b 16 @{ */
kadonotakashi 0:8fdf9a60065b 17
kadonotakashi 0:8fdf9a60065b 18 typedef struct
kadonotakashi 0:8fdf9a60065b 19 {
kadonotakashi 0:8fdf9a60065b 20 /**
kadonotakashi 0:8fdf9a60065b 21 * @var BCAPDAT_T::RCAPDAT
kadonotakashi 0:8fdf9a60065b 22 * Offset: 0x20C BPWM Rising Capture Data Register 0~5
kadonotakashi 0:8fdf9a60065b 23 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 24 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 25 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 26 * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only)
kadonotakashi 0:8fdf9a60065b 27 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 28 * @var BCAPDAT_T::FCAPDAT
kadonotakashi 0:8fdf9a60065b 29 * Offset: 0x210 BPWM Falling Capture Data Register 0~5
kadonotakashi 0:8fdf9a60065b 30 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 31 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 32 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 33 * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only)
kadonotakashi 0:8fdf9a60065b 34 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 35 */
kadonotakashi 0:8fdf9a60065b 36 __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */
kadonotakashi 0:8fdf9a60065b 37 __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */
kadonotakashi 0:8fdf9a60065b 38 } BCAPDAT_T;
kadonotakashi 0:8fdf9a60065b 39
kadonotakashi 0:8fdf9a60065b 40
kadonotakashi 0:8fdf9a60065b 41 typedef struct
kadonotakashi 0:8fdf9a60065b 42 {
kadonotakashi 0:8fdf9a60065b 43 /**
kadonotakashi 0:8fdf9a60065b 44 * @var BPWM_T::CTL0
kadonotakashi 0:8fdf9a60065b 45 * Offset: 0x00 BPWM Control Register 0
kadonotakashi 0:8fdf9a60065b 46 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 47 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 48 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 49 * |[0] |CTRLD0 |Center Re-load
kadonotakashi 0:8fdf9a60065b 50 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 51 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 52 * | | |CMPDAT will load to CMPBUF at the center point of a period
kadonotakashi 0:8fdf9a60065b 53 * |[1] |CTRLD1 |Center Re-load
kadonotakashi 0:8fdf9a60065b 54 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 55 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 56 * | | |CMPDAT will load to CMPBUF at the center point of a period
kadonotakashi 0:8fdf9a60065b 57 * |[2] |CTRLD2 |Center Re-load
kadonotakashi 0:8fdf9a60065b 58 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 59 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 60 * | | |CMPDAT will load to CMPBUF at the center point of a period
kadonotakashi 0:8fdf9a60065b 61 * |[3] |CTRLD3 |Center Re-load
kadonotakashi 0:8fdf9a60065b 62 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 63 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 64 * | | |CMPDAT will load to CMPBUF at the center point of a period
kadonotakashi 0:8fdf9a60065b 65 * |[4] |CTRLD4 |Center Re-load
kadonotakashi 0:8fdf9a60065b 66 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 67 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 68 * | | |CMPDAT will load to CMPBUF at the center point of a period
kadonotakashi 0:8fdf9a60065b 69 * |[5] |CTRLD5 |Center Re-load
kadonotakashi 0:8fdf9a60065b 70 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 71 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 72 * | | |CMPDAT will load to CMPBUF at the center point of a period
kadonotakashi 0:8fdf9a60065b 73 * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S)
kadonotakashi 0:8fdf9a60065b 74 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 75 * | | |0 = PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 76 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
kadonotakashi 0:8fdf9a60065b 77 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
kadonotakashi 0:8fdf9a60065b 78 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
kadonotakashi 0:8fdf9a60065b 79 * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S)
kadonotakashi 0:8fdf9a60065b 80 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 81 * | | |0 = PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 82 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
kadonotakashi 0:8fdf9a60065b 83 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
kadonotakashi 0:8fdf9a60065b 84 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
kadonotakashi 0:8fdf9a60065b 85 * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S)
kadonotakashi 0:8fdf9a60065b 86 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 87 * | | |0 = PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 88 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
kadonotakashi 0:8fdf9a60065b 89 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
kadonotakashi 0:8fdf9a60065b 90 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
kadonotakashi 0:8fdf9a60065b 91 * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S)
kadonotakashi 0:8fdf9a60065b 92 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 93 * | | |0 = PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 94 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
kadonotakashi 0:8fdf9a60065b 95 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
kadonotakashi 0:8fdf9a60065b 96 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
kadonotakashi 0:8fdf9a60065b 97 * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S)
kadonotakashi 0:8fdf9a60065b 98 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 99 * | | |0 = PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 100 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
kadonotakashi 0:8fdf9a60065b 101 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
kadonotakashi 0:8fdf9a60065b 102 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
kadonotakashi 0:8fdf9a60065b 103 * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S)
kadonotakashi 0:8fdf9a60065b 104 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 105 * | | |0 = PERIOD will load to PBUF at the end point of each period
kadonotakashi 0:8fdf9a60065b 106 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
kadonotakashi 0:8fdf9a60065b 107 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
kadonotakashi 0:8fdf9a60065b 108 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
kadonotakashi 0:8fdf9a60065b 109 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
kadonotakashi 0:8fdf9a60065b 110 * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
kadonotakashi 0:8fdf9a60065b 111 * | | |0 = ICE debug mode counter halt Disable.
kadonotakashi 0:8fdf9a60065b 112 * | | |1 = ICE debug mode counter halt Enable.
kadonotakashi 0:8fdf9a60065b 113 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
kadonotakashi 0:8fdf9a60065b 114 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
kadonotakashi 0:8fdf9a60065b 115 * | | |0 = ICE debug mode acknowledgement effects BPWM output.
kadonotakashi 0:8fdf9a60065b 116 * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged.
kadonotakashi 0:8fdf9a60065b 117 * | | |1 = ICE debug mode acknowledgement Disabled.
kadonotakashi 0:8fdf9a60065b 118 * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not.
kadonotakashi 0:8fdf9a60065b 119 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
kadonotakashi 0:8fdf9a60065b 120 * @var BPWM_T::CTL1
kadonotakashi 0:8fdf9a60065b 121 * Offset: 0x04 BPWM Control Register 1
kadonotakashi 0:8fdf9a60065b 122 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 123 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 124 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 125 * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0
kadonotakashi 0:8fdf9a60065b 126 * | | |Each bit n controls corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 127 * | | |00 = Up counter type (supports in capture mode).
kadonotakashi 0:8fdf9a60065b 128 * | | |01 = Down count type (supports in capture mode).
kadonotakashi 0:8fdf9a60065b 129 * | | |10 = Up-down counter type.
kadonotakashi 0:8fdf9a60065b 130 * | | |11 = Reserved.
kadonotakashi 0:8fdf9a60065b 131 * @var BPWM_T::CLKSRC
kadonotakashi 0:8fdf9a60065b 132 * Offset: 0x10 BPWM Clock Source Register
kadonotakashi 0:8fdf9a60065b 133 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 134 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 135 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 136 * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select
kadonotakashi 0:8fdf9a60065b 137 * | | |000 = BPWMx_CLK, x denotes 0 or 1.
kadonotakashi 0:8fdf9a60065b 138 * | | |001 = TIMER0 overflow.
kadonotakashi 0:8fdf9a60065b 139 * | | |010 = TIMER1 overflow.
kadonotakashi 0:8fdf9a60065b 140 * | | |011 = TIMER2 overflow.
kadonotakashi 0:8fdf9a60065b 141 * | | |100 = TIMER3 overflow.
kadonotakashi 0:8fdf9a60065b 142 * | | |Others = Reserved.
kadonotakashi 0:8fdf9a60065b 143 * @var BPWM_T::CLKPSC
kadonotakashi 0:8fdf9a60065b 144 * Offset: 0x14 BPWM Clock Prescale Register
kadonotakashi 0:8fdf9a60065b 145 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 146 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 147 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 148 * |[11:0] |CLKPSC |BPWM Counter Clock Prescale
kadonotakashi 0:8fdf9a60065b 149 * | | |The clock of BPWM counter is decided by clock prescaler
kadonotakashi 0:8fdf9a60065b 150 * | | |Each BPWM pair share one BPWM counter clock prescaler
kadonotakashi 0:8fdf9a60065b 151 * | | |The clock of BPWM counter is divided by (CLKPSC+ 1)
kadonotakashi 0:8fdf9a60065b 152 * @var BPWM_T::CNTEN
kadonotakashi 0:8fdf9a60065b 153 * Offset: 0x20 BPWM Counter Enable Register
kadonotakashi 0:8fdf9a60065b 154 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 155 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 156 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 157 * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit
kadonotakashi 0:8fdf9a60065b 158 * | | |0 = BPWM Counter and clock prescaler stop running.
kadonotakashi 0:8fdf9a60065b 159 * | | |1 = BPWM Counter and clock prescaler start running.
kadonotakashi 0:8fdf9a60065b 160 * @var BPWM_T::CNTCLR
kadonotakashi 0:8fdf9a60065b 161 * Offset: 0x24 BPWM Clear Counter Register
kadonotakashi 0:8fdf9a60065b 162 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 163 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 164 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 165 * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0
kadonotakashi 0:8fdf9a60065b 166 * | | |It is automatically cleared by hardware.
kadonotakashi 0:8fdf9a60065b 167 * | | |0 = No effect.
kadonotakashi 0:8fdf9a60065b 168 * | | |1 = Clear 16-bit BPWM counter to 0000H.
kadonotakashi 0:8fdf9a60065b 169 * @var BPWM_T::PERIOD
kadonotakashi 0:8fdf9a60065b 170 * Offset: 0x30 BPWM Period Register
kadonotakashi 0:8fdf9a60065b 171 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 172 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 173 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 174 * |[15:0] |PERIOD |BPWM Period Register
kadonotakashi 0:8fdf9a60065b 175 * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
kadonotakashi 0:8fdf9a60065b 176 * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
kadonotakashi 0:8fdf9a60065b 177 * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period.
kadonotakashi 0:8fdf9a60065b 178 * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
kadonotakashi 0:8fdf9a60065b 179 * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period.
kadonotakashi 0:8fdf9a60065b 180 * @var BPWM_T::CMPDAT[6]
kadonotakashi 0:8fdf9a60065b 181 * Offset: 0x50 BPWM Comparator Register 0~5
kadonotakashi 0:8fdf9a60065b 182 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 183 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 184 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 185 * |[15:0] |CMPDAT |BPWM Comparator Register
kadonotakashi 0:8fdf9a60065b 186 * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC.
kadonotakashi 0:8fdf9a60065b 187 * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
kadonotakashi 0:8fdf9a60065b 188 * @var BPWM_T::CNT
kadonotakashi 0:8fdf9a60065b 189 * Offset: 0x90 BPWM Counter Register
kadonotakashi 0:8fdf9a60065b 190 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 191 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 192 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 193 * |[15:0] |CNT |BPWM Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 194 * | | |User can monitor CNTR to know the current value in 16-bit period counter.
kadonotakashi 0:8fdf9a60065b 195 * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only)
kadonotakashi 0:8fdf9a60065b 196 * | | |0 = Counter is Down count.
kadonotakashi 0:8fdf9a60065b 197 * | | |1 = Counter is UP count.
kadonotakashi 0:8fdf9a60065b 198 * @var BPWM_T::WGCTL0
kadonotakashi 0:8fdf9a60065b 199 * Offset: 0xB0 BPWM Generation Register 0
kadonotakashi 0:8fdf9a60065b 200 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 201 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 202 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 203 * |[1:0] |ZPCTL0 |BPWM Zero Point Control
kadonotakashi 0:8fdf9a60065b 204 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 205 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 206 * | | |01 = BPWM zero point output Low.
kadonotakashi 0:8fdf9a60065b 207 * | | |10 = BPWM zero point output High.
kadonotakashi 0:8fdf9a60065b 208 * | | |11 = BPWM zero point output Toggle.
kadonotakashi 0:8fdf9a60065b 209 * | | |BPWM can control output level when BPWM counter count to zero.
kadonotakashi 0:8fdf9a60065b 210 * |[3:2] |ZPCTL1 |BPWM Zero Point Control
kadonotakashi 0:8fdf9a60065b 211 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 212 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 213 * | | |01 = BPWM zero point output Low.
kadonotakashi 0:8fdf9a60065b 214 * | | |10 = BPWM zero point output High.
kadonotakashi 0:8fdf9a60065b 215 * | | |11 = BPWM zero point output Toggle.
kadonotakashi 0:8fdf9a60065b 216 * | | |BPWM can control output level when BPWM counter count to zero.
kadonotakashi 0:8fdf9a60065b 217 * |[5:4] |ZPCTL2 |BPWM Zero Point Control
kadonotakashi 0:8fdf9a60065b 218 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 219 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 220 * | | |01 = BPWM zero point output Low.
kadonotakashi 0:8fdf9a60065b 221 * | | |10 = BPWM zero point output High.
kadonotakashi 0:8fdf9a60065b 222 * | | |11 = BPWM zero point output Toggle.
kadonotakashi 0:8fdf9a60065b 223 * | | |BPWM can control output level when BPWM counter count to zero.
kadonotakashi 0:8fdf9a60065b 224 * |[7:6] |ZPCTL3 |BPWM Zero Point Control
kadonotakashi 0:8fdf9a60065b 225 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 226 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 227 * | | |01 = BPWM zero point output Low.
kadonotakashi 0:8fdf9a60065b 228 * | | |10 = BPWM zero point output High.
kadonotakashi 0:8fdf9a60065b 229 * | | |11 = BPWM zero point output Toggle.
kadonotakashi 0:8fdf9a60065b 230 * | | |BPWM can control output level when BPWM counter count to zero.
kadonotakashi 0:8fdf9a60065b 231 * |[9:8] |ZPCTL4 |BPWM Zero Point Control
kadonotakashi 0:8fdf9a60065b 232 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 233 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 234 * | | |01 = BPWM zero point output Low.
kadonotakashi 0:8fdf9a60065b 235 * | | |10 = BPWM zero point output High.
kadonotakashi 0:8fdf9a60065b 236 * | | |11 = BPWM zero point output Toggle.
kadonotakashi 0:8fdf9a60065b 237 * | | |BPWM can control output level when BPWM counter count to zero.
kadonotakashi 0:8fdf9a60065b 238 * |[11:10] |ZPCTL5 |BPWM Zero Point Control
kadonotakashi 0:8fdf9a60065b 239 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 240 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 241 * | | |01 = BPWM zero point output Low.
kadonotakashi 0:8fdf9a60065b 242 * | | |10 = BPWM zero point output High.
kadonotakashi 0:8fdf9a60065b 243 * | | |11 = BPWM zero point output Toggle.
kadonotakashi 0:8fdf9a60065b 244 * | | |BPWM can control output level when BPWM counter count to zero.
kadonotakashi 0:8fdf9a60065b 245 * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control
kadonotakashi 0:8fdf9a60065b 246 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 247 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 248 * | | |01 = BPWM period (center) point output Low.
kadonotakashi 0:8fdf9a60065b 249 * | | |10 = BPWM period (center) point output High.
kadonotakashi 0:8fdf9a60065b 250 * | | |11 = BPWM period (center) point output Toggle.
kadonotakashi 0:8fdf9a60065b 251 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
kadonotakashi 0:8fdf9a60065b 252 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
kadonotakashi 0:8fdf9a60065b 253 * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control
kadonotakashi 0:8fdf9a60065b 254 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 255 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 256 * | | |01 = BPWM period (center) point output Low.
kadonotakashi 0:8fdf9a60065b 257 * | | |10 = BPWM period (center) point output High.
kadonotakashi 0:8fdf9a60065b 258 * | | |11 = BPWM period (center) point output Toggle.
kadonotakashi 0:8fdf9a60065b 259 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
kadonotakashi 0:8fdf9a60065b 260 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
kadonotakashi 0:8fdf9a60065b 261 * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control
kadonotakashi 0:8fdf9a60065b 262 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 263 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 264 * | | |01 = BPWM period (center) point output Low.
kadonotakashi 0:8fdf9a60065b 265 * | | |10 = BPWM period (center) point output High.
kadonotakashi 0:8fdf9a60065b 266 * | | |11 = BPWM period (center) point output Toggle.
kadonotakashi 0:8fdf9a60065b 267 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
kadonotakashi 0:8fdf9a60065b 268 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
kadonotakashi 0:8fdf9a60065b 269 * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control
kadonotakashi 0:8fdf9a60065b 270 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 271 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 272 * | | |01 = BPWM period (center) point output Low.
kadonotakashi 0:8fdf9a60065b 273 * | | |10 = BPWM period (center) point output High.
kadonotakashi 0:8fdf9a60065b 274 * | | |11 = BPWM period (center) point output Toggle.
kadonotakashi 0:8fdf9a60065b 275 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
kadonotakashi 0:8fdf9a60065b 276 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
kadonotakashi 0:8fdf9a60065b 277 * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control
kadonotakashi 0:8fdf9a60065b 278 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 279 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 280 * | | |01 = BPWM period (center) point output Low.
kadonotakashi 0:8fdf9a60065b 281 * | | |10 = BPWM period (center) point output High.
kadonotakashi 0:8fdf9a60065b 282 * | | |11 = BPWM period (center) point output Toggle.
kadonotakashi 0:8fdf9a60065b 283 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
kadonotakashi 0:8fdf9a60065b 284 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
kadonotakashi 0:8fdf9a60065b 285 * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control
kadonotakashi 0:8fdf9a60065b 286 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 287 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 288 * | | |01 = BPWM period (center) point output Low.
kadonotakashi 0:8fdf9a60065b 289 * | | |10 = BPWM period (center) point output High.
kadonotakashi 0:8fdf9a60065b 290 * | | |11 = BPWM period (center) point output Toggle.
kadonotakashi 0:8fdf9a60065b 291 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
kadonotakashi 0:8fdf9a60065b 292 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
kadonotakashi 0:8fdf9a60065b 293 * @var BPWM_T::WGCTL1
kadonotakashi 0:8fdf9a60065b 294 * Offset: 0xB4 BPWM Generation Register 1
kadonotakashi 0:8fdf9a60065b 295 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 296 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 297 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 298 * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control
kadonotakashi 0:8fdf9a60065b 299 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 300 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 301 * | | |01 = BPWM compare up point output Low.
kadonotakashi 0:8fdf9a60065b 302 * | | |10 = BPWM compare up point output High.
kadonotakashi 0:8fdf9a60065b 303 * | | |11 = BPWM compare up point output Toggle.
kadonotakashi 0:8fdf9a60065b 304 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 305 * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control
kadonotakashi 0:8fdf9a60065b 306 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 307 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 308 * | | |01 = BPWM compare up point output Low.
kadonotakashi 0:8fdf9a60065b 309 * | | |10 = BPWM compare up point output High.
kadonotakashi 0:8fdf9a60065b 310 * | | |11 = BPWM compare up point output Toggle.
kadonotakashi 0:8fdf9a60065b 311 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 312 * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control
kadonotakashi 0:8fdf9a60065b 313 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 314 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 315 * | | |01 = BPWM compare up point output Low.
kadonotakashi 0:8fdf9a60065b 316 * | | |10 = BPWM compare up point output High.
kadonotakashi 0:8fdf9a60065b 317 * | | |11 = BPWM compare up point output Toggle.
kadonotakashi 0:8fdf9a60065b 318 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 319 * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control
kadonotakashi 0:8fdf9a60065b 320 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 321 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 322 * | | |01 = BPWM compare up point output Low.
kadonotakashi 0:8fdf9a60065b 323 * | | |10 = BPWM compare up point output High.
kadonotakashi 0:8fdf9a60065b 324 * | | |11 = BPWM compare up point output Toggle.
kadonotakashi 0:8fdf9a60065b 325 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 326 * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control
kadonotakashi 0:8fdf9a60065b 327 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 328 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 329 * | | |01 = BPWM compare up point output Low.
kadonotakashi 0:8fdf9a60065b 330 * | | |10 = BPWM compare up point output High.
kadonotakashi 0:8fdf9a60065b 331 * | | |11 = BPWM compare up point output Toggle.
kadonotakashi 0:8fdf9a60065b 332 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 333 * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control
kadonotakashi 0:8fdf9a60065b 334 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 335 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 336 * | | |01 = BPWM compare up point output Low.
kadonotakashi 0:8fdf9a60065b 337 * | | |10 = BPWM compare up point output High.
kadonotakashi 0:8fdf9a60065b 338 * | | |11 = BPWM compare up point output Toggle.
kadonotakashi 0:8fdf9a60065b 339 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 340 * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control
kadonotakashi 0:8fdf9a60065b 341 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 342 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 343 * | | |01 = BPWM compare down point output Low.
kadonotakashi 0:8fdf9a60065b 344 * | | |10 = BPWM compare down point output High.
kadonotakashi 0:8fdf9a60065b 345 * | | |11 = BPWM compare down point output Toggle.
kadonotakashi 0:8fdf9a60065b 346 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 347 * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control
kadonotakashi 0:8fdf9a60065b 348 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 349 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 350 * | | |01 = BPWM compare down point output Low.
kadonotakashi 0:8fdf9a60065b 351 * | | |10 = BPWM compare down point output High.
kadonotakashi 0:8fdf9a60065b 352 * | | |11 = BPWM compare down point output Toggle.
kadonotakashi 0:8fdf9a60065b 353 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 354 * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control
kadonotakashi 0:8fdf9a60065b 355 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 356 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 357 * | | |01 = BPWM compare down point output Low.
kadonotakashi 0:8fdf9a60065b 358 * | | |10 = BPWM compare down point output High.
kadonotakashi 0:8fdf9a60065b 359 * | | |11 = BPWM compare down point output Toggle.
kadonotakashi 0:8fdf9a60065b 360 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 361 * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control
kadonotakashi 0:8fdf9a60065b 362 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 363 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 364 * | | |01 = BPWM compare down point output Low.
kadonotakashi 0:8fdf9a60065b 365 * | | |10 = BPWM compare down point output High.
kadonotakashi 0:8fdf9a60065b 366 * | | |11 = BPWM compare down point output Toggle.
kadonotakashi 0:8fdf9a60065b 367 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 368 * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control
kadonotakashi 0:8fdf9a60065b 369 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 370 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 371 * | | |01 = BPWM compare down point output Low.
kadonotakashi 0:8fdf9a60065b 372 * | | |10 = BPWM compare down point output High.
kadonotakashi 0:8fdf9a60065b 373 * | | |11 = BPWM compare down point output Toggle.
kadonotakashi 0:8fdf9a60065b 374 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 375 * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control
kadonotakashi 0:8fdf9a60065b 376 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 377 * | | |00 = Do nothing.
kadonotakashi 0:8fdf9a60065b 378 * | | |01 = BPWM compare down point output Low.
kadonotakashi 0:8fdf9a60065b 379 * | | |10 = BPWM compare down point output High.
kadonotakashi 0:8fdf9a60065b 380 * | | |11 = BPWM compare down point output Toggle.
kadonotakashi 0:8fdf9a60065b 381 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
kadonotakashi 0:8fdf9a60065b 382 * @var BPWM_T::MSKEN
kadonotakashi 0:8fdf9a60065b 383 * Offset: 0xB8 BPWM Mask Enable Register
kadonotakashi 0:8fdf9a60065b 384 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 385 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 386 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 387 * |[0] |MSKEN0 |BPWM Mask Enable Bits
kadonotakashi 0:8fdf9a60065b 388 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 389 * | | |The BPWM output signal will be masked when this bit is enabled
kadonotakashi 0:8fdf9a60065b 390 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
kadonotakashi 0:8fdf9a60065b 391 * | | |0 = BPWM output signal is non-masked.
kadonotakashi 0:8fdf9a60065b 392 * | | |1 = BPWM output signal is masked and output MSKDATn data.
kadonotakashi 0:8fdf9a60065b 393 * |[1] |MSKEN1 |BPWM Mask Enable Bits
kadonotakashi 0:8fdf9a60065b 394 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 395 * | | |The BPWM output signal will be masked when this bit is enabled
kadonotakashi 0:8fdf9a60065b 396 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
kadonotakashi 0:8fdf9a60065b 397 * | | |0 = BPWM output signal is non-masked.
kadonotakashi 0:8fdf9a60065b 398 * | | |1 = BPWM output signal is masked and output MSKDATn data.
kadonotakashi 0:8fdf9a60065b 399 * |[2] |MSKEN2 |BPWM Mask Enable Bits
kadonotakashi 0:8fdf9a60065b 400 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 401 * | | |The BPWM output signal will be masked when this bit is enabled
kadonotakashi 0:8fdf9a60065b 402 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
kadonotakashi 0:8fdf9a60065b 403 * | | |0 = BPWM output signal is non-masked.
kadonotakashi 0:8fdf9a60065b 404 * | | |1 = BPWM output signal is masked and output MSKDATn data.
kadonotakashi 0:8fdf9a60065b 405 * |[3] |MSKEN3 |BPWM Mask Enable Bits
kadonotakashi 0:8fdf9a60065b 406 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 407 * | | |The BPWM output signal will be masked when this bit is enabled
kadonotakashi 0:8fdf9a60065b 408 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
kadonotakashi 0:8fdf9a60065b 409 * | | |0 = BPWM output signal is non-masked.
kadonotakashi 0:8fdf9a60065b 410 * | | |1 = BPWM output signal is masked and output MSKDATn data.
kadonotakashi 0:8fdf9a60065b 411 * |[4] |MSKEN4 |BPWM Mask Enable Bits
kadonotakashi 0:8fdf9a60065b 412 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 413 * | | |The BPWM output signal will be masked when this bit is enabled
kadonotakashi 0:8fdf9a60065b 414 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
kadonotakashi 0:8fdf9a60065b 415 * | | |0 = BPWM output signal is non-masked.
kadonotakashi 0:8fdf9a60065b 416 * | | |1 = BPWM output signal is masked and output MSKDATn data.
kadonotakashi 0:8fdf9a60065b 417 * |[5] |MSKEN5 |BPWM Mask Enable Bits
kadonotakashi 0:8fdf9a60065b 418 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 419 * | | |The BPWM output signal will be masked when this bit is enabled
kadonotakashi 0:8fdf9a60065b 420 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
kadonotakashi 0:8fdf9a60065b 421 * | | |0 = BPWM output signal is non-masked.
kadonotakashi 0:8fdf9a60065b 422 * | | |1 = BPWM output signal is masked and output MSKDATn data.
kadonotakashi 0:8fdf9a60065b 423 * @var BPWM_T::MSK
kadonotakashi 0:8fdf9a60065b 424 * Offset: 0xBC BPWM Mask Data Register
kadonotakashi 0:8fdf9a60065b 425 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 426 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 427 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 428 * |[0] |MSKDAT0 |BPWM Mask Data Bit
kadonotakashi 0:8fdf9a60065b 429 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
kadonotakashi 0:8fdf9a60065b 430 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 431 * | | |0 = Output logic low to BPWMn.
kadonotakashi 0:8fdf9a60065b 432 * | | |1 = Output logic high to BPWMn.
kadonotakashi 0:8fdf9a60065b 433 * |[1] |MSKDAT1 |BPWM Mask Data Bit
kadonotakashi 0:8fdf9a60065b 434 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
kadonotakashi 0:8fdf9a60065b 435 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 436 * | | |0 = Output logic low to BPWMn.
kadonotakashi 0:8fdf9a60065b 437 * | | |1 = Output logic high to BPWMn.
kadonotakashi 0:8fdf9a60065b 438 * |[2] |MSKDAT2 |BPWM Mask Data Bit
kadonotakashi 0:8fdf9a60065b 439 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
kadonotakashi 0:8fdf9a60065b 440 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 441 * | | |0 = Output logic low to BPWMn.
kadonotakashi 0:8fdf9a60065b 442 * | | |1 = Output logic high to BPWMn.
kadonotakashi 0:8fdf9a60065b 443 * |[3] |MSKDAT3 |BPWM Mask Data Bit
kadonotakashi 0:8fdf9a60065b 444 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
kadonotakashi 0:8fdf9a60065b 445 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 446 * | | |0 = Output logic low to BPWMn.
kadonotakashi 0:8fdf9a60065b 447 * | | |1 = Output logic high to BPWMn.
kadonotakashi 0:8fdf9a60065b 448 * |[4] |MSKDAT4 |BPWM Mask Data Bit
kadonotakashi 0:8fdf9a60065b 449 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
kadonotakashi 0:8fdf9a60065b 450 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 451 * | | |0 = Output logic low to BPWMn.
kadonotakashi 0:8fdf9a60065b 452 * | | |1 = Output logic high to BPWMn.
kadonotakashi 0:8fdf9a60065b 453 * |[5] |MSKDAT5 |BPWM Mask Data Bit
kadonotakashi 0:8fdf9a60065b 454 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
kadonotakashi 0:8fdf9a60065b 455 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 456 * | | |0 = Output logic low to BPWMn.
kadonotakashi 0:8fdf9a60065b 457 * | | |1 = Output logic high to BPWMn.
kadonotakashi 0:8fdf9a60065b 458 * @var BPWM_T::POLCTL
kadonotakashi 0:8fdf9a60065b 459 * Offset: 0xD4 BPWM Pin Polar Inverse Register
kadonotakashi 0:8fdf9a60065b 460 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 461 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 462 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 463 * |[0] |PINV0 |BPWM PIN Polar Inverse Control
kadonotakashi 0:8fdf9a60065b 464 * | | |The register controls polarity state of BPWM output
kadonotakashi 0:8fdf9a60065b 465 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 466 * | | |0 = BPWM output polar inverse Disabled.
kadonotakashi 0:8fdf9a60065b 467 * | | |1 = BPWM output polar inverse Enabled.
kadonotakashi 0:8fdf9a60065b 468 * |[1] |PINV1 |BPWM PIN Polar Inverse Control
kadonotakashi 0:8fdf9a60065b 469 * | | |The register controls polarity state of BPWM output
kadonotakashi 0:8fdf9a60065b 470 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 471 * | | |0 = BPWM output polar inverse Disabled.
kadonotakashi 0:8fdf9a60065b 472 * | | |1 = BPWM output polar inverse Enabled.
kadonotakashi 0:8fdf9a60065b 473 * |[2] |PINV2 |BPWM PIN Polar Inverse Control
kadonotakashi 0:8fdf9a60065b 474 * | | |The register controls polarity state of BPWM output
kadonotakashi 0:8fdf9a60065b 475 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 476 * | | |0 = BPWM output polar inverse Disabled.
kadonotakashi 0:8fdf9a60065b 477 * | | |1 = BPWM output polar inverse Enabled.
kadonotakashi 0:8fdf9a60065b 478 * |[3] |PINV3 |BPWM PIN Polar Inverse Control
kadonotakashi 0:8fdf9a60065b 479 * | | |The register controls polarity state of BPWM output
kadonotakashi 0:8fdf9a60065b 480 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 481 * | | |0 = BPWM output polar inverse Disabled.
kadonotakashi 0:8fdf9a60065b 482 * | | |1 = BPWM output polar inverse Enabled.
kadonotakashi 0:8fdf9a60065b 483 * |[4] |PINV4 |BPWM PIN Polar Inverse Control
kadonotakashi 0:8fdf9a60065b 484 * | | |The register controls polarity state of BPWM output
kadonotakashi 0:8fdf9a60065b 485 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 486 * | | |0 = BPWM output polar inverse Disabled.
kadonotakashi 0:8fdf9a60065b 487 * | | |1 = BPWM output polar inverse Enabled.
kadonotakashi 0:8fdf9a60065b 488 * |[5] |PINV5 |BPWM PIN Polar Inverse Control
kadonotakashi 0:8fdf9a60065b 489 * | | |The register controls polarity state of BPWM output
kadonotakashi 0:8fdf9a60065b 490 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 491 * | | |0 = BPWM output polar inverse Disabled.
kadonotakashi 0:8fdf9a60065b 492 * | | |1 = BPWM output polar inverse Enabled.
kadonotakashi 0:8fdf9a60065b 493 * @var BPWM_T::POEN
kadonotakashi 0:8fdf9a60065b 494 * Offset: 0xD8 BPWM Output Enable Register
kadonotakashi 0:8fdf9a60065b 495 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 496 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 497 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 498 * |[0] |POEN0 |BPWM Pin Output Enable Bits
kadonotakashi 0:8fdf9a60065b 499 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 500 * | | |0 = BPWM pin at tri-state.
kadonotakashi 0:8fdf9a60065b 501 * | | |1 = BPWM pin in output mode.
kadonotakashi 0:8fdf9a60065b 502 * |[1] |POEN1 |BPWM Pin Output Enable Bits
kadonotakashi 0:8fdf9a60065b 503 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 504 * | | |0 = BPWM pin at tri-state.
kadonotakashi 0:8fdf9a60065b 505 * | | |1 = BPWM pin in output mode.
kadonotakashi 0:8fdf9a60065b 506 * |[2] |POEN2 |BPWM Pin Output Enable Bits
kadonotakashi 0:8fdf9a60065b 507 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 508 * | | |0 = BPWM pin at tri-state.
kadonotakashi 0:8fdf9a60065b 509 * | | |1 = BPWM pin in output mode.
kadonotakashi 0:8fdf9a60065b 510 * |[3] |POEN3 |BPWM Pin Output Enable Bits
kadonotakashi 0:8fdf9a60065b 511 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 512 * | | |0 = BPWM pin at tri-state.
kadonotakashi 0:8fdf9a60065b 513 * | | |1 = BPWM pin in output mode.
kadonotakashi 0:8fdf9a60065b 514 * |[4] |POEN4 |BPWM Pin Output Enable Bits
kadonotakashi 0:8fdf9a60065b 515 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 516 * | | |0 = BPWM pin at tri-state.
kadonotakashi 0:8fdf9a60065b 517 * | | |1 = BPWM pin in output mode.
kadonotakashi 0:8fdf9a60065b 518 * |[5] |POEN5 |BPWM Pin Output Enable Bits
kadonotakashi 0:8fdf9a60065b 519 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 520 * | | |0 = BPWM pin at tri-state.
kadonotakashi 0:8fdf9a60065b 521 * | | |1 = BPWM pin in output mode.
kadonotakashi 0:8fdf9a60065b 522 * @var BPWM_T::INTEN
kadonotakashi 0:8fdf9a60065b 523 * Offset: 0xE0 BPWM Interrupt Enable Register
kadonotakashi 0:8fdf9a60065b 524 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 525 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 526 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 527 * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit
kadonotakashi 0:8fdf9a60065b 528 * | | |0 = Zero point interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 529 * | | |1 = Zero point interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 530 * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit
kadonotakashi 0:8fdf9a60065b 531 * | | |0 = Period point interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 532 * | | |1 = Period point interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 533 * | | |Note: When up-down counter type period point means center point.
kadonotakashi 0:8fdf9a60065b 534 * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 535 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 536 * | | |0 = Compare up count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 537 * | | |1 = Compare up count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 538 * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 539 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 540 * | | |0 = Compare up count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 541 * | | |1 = Compare up count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 542 * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 543 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 544 * | | |0 = Compare up count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 545 * | | |1 = Compare up count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 546 * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 547 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 548 * | | |0 = Compare up count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 549 * | | |1 = Compare up count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 550 * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 551 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 552 * | | |0 = Compare up count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 553 * | | |1 = Compare up count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 554 * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 555 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 556 * | | |0 = Compare up count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 557 * | | |1 = Compare up count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 558 * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 559 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 560 * | | |0 = Compare down count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 561 * | | |1 = Compare down count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 562 * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 563 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 564 * | | |0 = Compare down count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 565 * | | |1 = Compare down count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 566 * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 567 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 568 * | | |0 = Compare down count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 569 * | | |1 = Compare down count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 570 * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 571 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 572 * | | |0 = Compare down count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 573 * | | |1 = Compare down count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 574 * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 575 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 576 * | | |0 = Compare down count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 577 * | | |1 = Compare down count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 578 * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 579 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 580 * | | |0 = Compare down count interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 581 * | | |1 = Compare down count interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 582 * @var BPWM_T::INTSTS
kadonotakashi 0:8fdf9a60065b 583 * Offset: 0xE8 BPWM Interrupt Flag Register
kadonotakashi 0:8fdf9a60065b 584 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 585 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 586 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 587 * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0
kadonotakashi 0:8fdf9a60065b 588 * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero.
kadonotakashi 0:8fdf9a60065b 589 * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0
kadonotakashi 0:8fdf9a60065b 590 * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero.
kadonotakashi 0:8fdf9a60065b 591 * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 592 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
kadonotakashi 0:8fdf9a60065b 593 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 594 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
kadonotakashi 0:8fdf9a60065b 595 * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 596 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
kadonotakashi 0:8fdf9a60065b 597 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 598 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
kadonotakashi 0:8fdf9a60065b 599 * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 600 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
kadonotakashi 0:8fdf9a60065b 601 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 602 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
kadonotakashi 0:8fdf9a60065b 603 * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 604 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
kadonotakashi 0:8fdf9a60065b 605 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 606 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
kadonotakashi 0:8fdf9a60065b 607 * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 608 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
kadonotakashi 0:8fdf9a60065b 609 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 610 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
kadonotakashi 0:8fdf9a60065b 611 * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 612 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
kadonotakashi 0:8fdf9a60065b 613 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 614 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
kadonotakashi 0:8fdf9a60065b 615 * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 616 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 617 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
kadonotakashi 0:8fdf9a60065b 618 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
kadonotakashi 0:8fdf9a60065b 619 * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 620 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 621 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
kadonotakashi 0:8fdf9a60065b 622 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
kadonotakashi 0:8fdf9a60065b 623 * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 624 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 625 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
kadonotakashi 0:8fdf9a60065b 626 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
kadonotakashi 0:8fdf9a60065b 627 * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 628 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 629 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
kadonotakashi 0:8fdf9a60065b 630 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
kadonotakashi 0:8fdf9a60065b 631 * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 632 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 633 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
kadonotakashi 0:8fdf9a60065b 634 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
kadonotakashi 0:8fdf9a60065b 635 * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag
kadonotakashi 0:8fdf9a60065b 636 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 637 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
kadonotakashi 0:8fdf9a60065b 638 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
kadonotakashi 0:8fdf9a60065b 639 * @var BPWM_T::EADCTS0
kadonotakashi 0:8fdf9a60065b 640 * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0
kadonotakashi 0:8fdf9a60065b 641 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 642 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 643 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 644 * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select
kadonotakashi 0:8fdf9a60065b 645 * | | |0000 = BPWM_CH0 zero point.
kadonotakashi 0:8fdf9a60065b 646 * | | |0001 = BPWM_CH0 period point.
kadonotakashi 0:8fdf9a60065b 647 * | | |0010 = BPWM_CH0 zero or period point.
kadonotakashi 0:8fdf9a60065b 648 * | | |0011 = BPWM_CH0 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 649 * | | |0100 = BPWM_CH0 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 650 * | | |0101 = Reserved.
kadonotakashi 0:8fdf9a60065b 651 * | | |0110 = Reserved.
kadonotakashi 0:8fdf9a60065b 652 * | | |0111 = Reserved.
kadonotakashi 0:8fdf9a60065b 653 * | | |1000 = BPWM_CH1 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 654 * | | |1001 = BPWM_CH1 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 655 * | | |Others reserved
kadonotakashi 0:8fdf9a60065b 656 * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit
kadonotakashi 0:8fdf9a60065b 657 * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select
kadonotakashi 0:8fdf9a60065b 658 * | | |0000 = BPWM_CH0 zero point.
kadonotakashi 0:8fdf9a60065b 659 * | | |0001 = BPWM_CH0 period point.
kadonotakashi 0:8fdf9a60065b 660 * | | |0010 = BPWM_CH0 zero or period point.
kadonotakashi 0:8fdf9a60065b 661 * | | |0011 = BPWM_CH0 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 662 * | | |0100 = BPWM_CH0 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 663 * | | |0101 = Reserved.
kadonotakashi 0:8fdf9a60065b 664 * | | |0110 = Reserved.
kadonotakashi 0:8fdf9a60065b 665 * | | |0111 = Reserved.
kadonotakashi 0:8fdf9a60065b 666 * | | |1000 = BPWM_CH1 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 667 * | | |1001 = BPWM_CH1 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 668 * | | |Others reserved
kadonotakashi 0:8fdf9a60065b 669 * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit
kadonotakashi 0:8fdf9a60065b 670 * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select
kadonotakashi 0:8fdf9a60065b 671 * | | |0000 = BPWM_CH2 zero point.
kadonotakashi 0:8fdf9a60065b 672 * | | |0001 = BPWM_CH2 period point.
kadonotakashi 0:8fdf9a60065b 673 * | | |0010 = BPWM_CH2 zero or period point.
kadonotakashi 0:8fdf9a60065b 674 * | | |0011 = BPWM_CH2 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 675 * | | |0100 = BPWM_CH2 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 676 * | | |0101 = Reserved.
kadonotakashi 0:8fdf9a60065b 677 * | | |0110 = Reserved.
kadonotakashi 0:8fdf9a60065b 678 * | | |0111 = Reserved.
kadonotakashi 0:8fdf9a60065b 679 * | | |1000 = BPWM_CH3 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 680 * | | |1001 = BPWM_CH3 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 681 * | | |Others reserved
kadonotakashi 0:8fdf9a60065b 682 * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit
kadonotakashi 0:8fdf9a60065b 683 * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select
kadonotakashi 0:8fdf9a60065b 684 * | | |0000 = BPWM_CH2 zero point.
kadonotakashi 0:8fdf9a60065b 685 * | | |0001 = BPWM_CH2 period point.
kadonotakashi 0:8fdf9a60065b 686 * | | |0010 = BPWM_CH2 zero or period point.
kadonotakashi 0:8fdf9a60065b 687 * | | |0011 = BPWM_CH2 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 688 * | | |0100 = BPWM_CH2 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 689 * | | |0101 = Reserved.
kadonotakashi 0:8fdf9a60065b 690 * | | |0110 = Reserved.
kadonotakashi 0:8fdf9a60065b 691 * | | |0111 = Reserved.
kadonotakashi 0:8fdf9a60065b 692 * | | |1000 = BPWM_CH3 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 693 * | | |1001 = BPWM_CH3 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 694 * | | |Others reserved.
kadonotakashi 0:8fdf9a60065b 695 * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit
kadonotakashi 0:8fdf9a60065b 696 * @var BPWM_T::EADCTS1
kadonotakashi 0:8fdf9a60065b 697 * Offset: 0xFC BPWM Trigger EADC Source Select Register 1
kadonotakashi 0:8fdf9a60065b 698 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 699 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 700 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 701 * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select
kadonotakashi 0:8fdf9a60065b 702 * | | |0000 = BPWM_CH4 zero point.
kadonotakashi 0:8fdf9a60065b 703 * | | |0001 = BPWM_CH4 period point.
kadonotakashi 0:8fdf9a60065b 704 * | | |0010 = BPWM_CH4 zero or period point.
kadonotakashi 0:8fdf9a60065b 705 * | | |0011 = BPWM_CH4 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 706 * | | |0100 = BPWM_CH4 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 707 * | | |0101 = Reserved.
kadonotakashi 0:8fdf9a60065b 708 * | | |0110 = Reserved.
kadonotakashi 0:8fdf9a60065b 709 * | | |0111 = Reserved.
kadonotakashi 0:8fdf9a60065b 710 * | | |1000 = BPWM_CH5 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 711 * | | |1001 = BPWM_CH5 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 712 * | | |Others reserved
kadonotakashi 0:8fdf9a60065b 713 * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit
kadonotakashi 0:8fdf9a60065b 714 * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select
kadonotakashi 0:8fdf9a60065b 715 * | | |0000 = BPWM_CH4 zero point.
kadonotakashi 0:8fdf9a60065b 716 * | | |0001 = BPWM_CH4 period point.
kadonotakashi 0:8fdf9a60065b 717 * | | |0010 = BPWM_CH4 zero or period point.
kadonotakashi 0:8fdf9a60065b 718 * | | |0011 = BPWM_CH4 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 719 * | | |0100 = BPWM_CH4 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 720 * | | |0101 = Reserved.
kadonotakashi 0:8fdf9a60065b 721 * | | |0110 = Reserved.
kadonotakashi 0:8fdf9a60065b 722 * | | |0111 = Reserved.
kadonotakashi 0:8fdf9a60065b 723 * | | |1000 = BPWM_CH5 up-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 724 * | | |1001 = BPWM_CH5 down-count CMPDAT point.
kadonotakashi 0:8fdf9a60065b 725 * | | |Others reserved
kadonotakashi 0:8fdf9a60065b 726 * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit
kadonotakashi 0:8fdf9a60065b 727 * @var BPWM_T::SSCTL
kadonotakashi 0:8fdf9a60065b 728 * Offset: 0x110 BPWM Synchronous Start Control Register
kadonotakashi 0:8fdf9a60065b 729 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 730 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 731 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 732 * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit
kadonotakashi 0:8fdf9a60065b 733 * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
kadonotakashi 0:8fdf9a60065b 734 * | | |0 = BPWM synchronous start function Disabled.
kadonotakashi 0:8fdf9a60065b 735 * | | |1 = BPWM synchronous start function Enabled.
kadonotakashi 0:8fdf9a60065b 736 * |[9:8] |SSRC |BPWM Synchronous Start Source Select
kadonotakashi 0:8fdf9a60065b 737 * | | |00 = Synchronous start source come from PWM0.
kadonotakashi 0:8fdf9a60065b 738 * | | |01 = Synchronous start source come from PWM1.
kadonotakashi 0:8fdf9a60065b 739 * | | |10 = Synchronous start source come from BPWM0.
kadonotakashi 0:8fdf9a60065b 740 * | | |11 = Synchronous start source come from BPWM1.
kadonotakashi 0:8fdf9a60065b 741 * @var BPWM_T::SSTRG
kadonotakashi 0:8fdf9a60065b 742 * Offset: 0x114 BPWM Synchronous Start Trigger Register
kadonotakashi 0:8fdf9a60065b 743 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 744 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 745 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 746 * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only)
kadonotakashi 0:8fdf9a60065b 747 * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.
kadonotakashi 0:8fdf9a60065b 748 * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
kadonotakashi 0:8fdf9a60065b 749 * @var BPWM_T::STATUS
kadonotakashi 0:8fdf9a60065b 750 * Offset: 0x120 BPWM Status Register
kadonotakashi 0:8fdf9a60065b 751 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 752 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 753 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 754 * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status
kadonotakashi 0:8fdf9a60065b 755 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
kadonotakashi 0:8fdf9a60065b 756 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
kadonotakashi 0:8fdf9a60065b 757 * |[16] |EADCTRG0 |EADC Start of Conversion Status
kadonotakashi 0:8fdf9a60065b 758 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 759 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
kadonotakashi 0:8fdf9a60065b 760 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
kadonotakashi 0:8fdf9a60065b 761 * |[17] |EADCTRG1 |EADC Start of Conversion Status
kadonotakashi 0:8fdf9a60065b 762 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 763 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
kadonotakashi 0:8fdf9a60065b 764 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
kadonotakashi 0:8fdf9a60065b 765 * |[18] |EADCTRG2 |EADC Start of Conversion Status
kadonotakashi 0:8fdf9a60065b 766 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 767 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
kadonotakashi 0:8fdf9a60065b 768 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
kadonotakashi 0:8fdf9a60065b 769 * |[19] |EADCTRG3 |EADC Start of Conversion Status
kadonotakashi 0:8fdf9a60065b 770 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 771 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
kadonotakashi 0:8fdf9a60065b 772 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
kadonotakashi 0:8fdf9a60065b 773 * |[20] |EADCTRG4 |EADC Start of Conversion Status
kadonotakashi 0:8fdf9a60065b 774 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 775 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
kadonotakashi 0:8fdf9a60065b 776 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
kadonotakashi 0:8fdf9a60065b 777 * |[21] |EADCTRG5 |EADC Start of Conversion Status
kadonotakashi 0:8fdf9a60065b 778 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 779 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
kadonotakashi 0:8fdf9a60065b 780 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
kadonotakashi 0:8fdf9a60065b 781 * @var BPWM_T::CAPINEN
kadonotakashi 0:8fdf9a60065b 782 * Offset: 0x200 BPWM Capture Input Enable Register
kadonotakashi 0:8fdf9a60065b 783 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 784 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 785 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 786 * |[0] |CAPINEN0 |Capture Input Enable Bits
kadonotakashi 0:8fdf9a60065b 787 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 788 * | | |0 = BPWM Channel capture input path Disabled
kadonotakashi 0:8fdf9a60065b 789 * | | |The input of BPWM channel capture function is always regarded as 0.
kadonotakashi 0:8fdf9a60065b 790 * | | |1 = BPWM Channel capture input path Enabled
kadonotakashi 0:8fdf9a60065b 791 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
kadonotakashi 0:8fdf9a60065b 792 * |[1] |CAPINEN1 |Capture Input Enable Bits
kadonotakashi 0:8fdf9a60065b 793 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 794 * | | |0 = BPWM Channel capture input path Disabled
kadonotakashi 0:8fdf9a60065b 795 * | | |The input of BPWM channel capture function is always regarded as 0.
kadonotakashi 0:8fdf9a60065b 796 * | | |1 = BPWM Channel capture input path Enabled
kadonotakashi 0:8fdf9a60065b 797 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
kadonotakashi 0:8fdf9a60065b 798 * |[2] |CAPINEN2 |Capture Input Enable Bits
kadonotakashi 0:8fdf9a60065b 799 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 800 * | | |0 = BPWM Channel capture input path Disabled
kadonotakashi 0:8fdf9a60065b 801 * | | |The input of BPWM channel capture function is always regarded as 0.
kadonotakashi 0:8fdf9a60065b 802 * | | |1 = BPWM Channel capture input path Enabled
kadonotakashi 0:8fdf9a60065b 803 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
kadonotakashi 0:8fdf9a60065b 804 * |[3] |CAPINEN3 |Capture Input Enable Bits
kadonotakashi 0:8fdf9a60065b 805 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 806 * | | |0 = BPWM Channel capture input path Disabled
kadonotakashi 0:8fdf9a60065b 807 * | | |The input of BPWM channel capture function is always regarded as 0.
kadonotakashi 0:8fdf9a60065b 808 * | | |1 = BPWM Channel capture input path Enabled
kadonotakashi 0:8fdf9a60065b 809 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
kadonotakashi 0:8fdf9a60065b 810 * |[4] |CAPINEN4 |Capture Input Enable Bits
kadonotakashi 0:8fdf9a60065b 811 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 812 * | | |0 = BPWM Channel capture input path Disabled
kadonotakashi 0:8fdf9a60065b 813 * | | |The input of BPWM channel capture function is always regarded as 0.
kadonotakashi 0:8fdf9a60065b 814 * | | |1 = BPWM Channel capture input path Enabled
kadonotakashi 0:8fdf9a60065b 815 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
kadonotakashi 0:8fdf9a60065b 816 * |[5] |CAPINEN5 |Capture Input Enable Bits
kadonotakashi 0:8fdf9a60065b 817 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 818 * | | |0 = BPWM Channel capture input path Disabled
kadonotakashi 0:8fdf9a60065b 819 * | | |The input of BPWM channel capture function is always regarded as 0.
kadonotakashi 0:8fdf9a60065b 820 * | | |1 = BPWM Channel capture input path Enabled
kadonotakashi 0:8fdf9a60065b 821 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
kadonotakashi 0:8fdf9a60065b 822 * @var BPWM_T::CAPCTL
kadonotakashi 0:8fdf9a60065b 823 * Offset: 0x204 BPWM Capture Control Register
kadonotakashi 0:8fdf9a60065b 824 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 825 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 826 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 827 * |[0] |CAPEN0 |Capture Function Enable Bits
kadonotakashi 0:8fdf9a60065b 828 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 829 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
kadonotakashi 0:8fdf9a60065b 830 * | | |1 = Capture function Enabled
kadonotakashi 0:8fdf9a60065b 831 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
kadonotakashi 0:8fdf9a60065b 832 * |[1] |CAPEN1 |Capture Function Enable Bits
kadonotakashi 0:8fdf9a60065b 833 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 834 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
kadonotakashi 0:8fdf9a60065b 835 * | | |1 = Capture function Enabled
kadonotakashi 0:8fdf9a60065b 836 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
kadonotakashi 0:8fdf9a60065b 837 * |[2] |CAPEN2 |Capture Function Enable Bits
kadonotakashi 0:8fdf9a60065b 838 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 839 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
kadonotakashi 0:8fdf9a60065b 840 * | | |1 = Capture function Enabled
kadonotakashi 0:8fdf9a60065b 841 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
kadonotakashi 0:8fdf9a60065b 842 * |[3] |CAPEN3 |Capture Function Enable Bits
kadonotakashi 0:8fdf9a60065b 843 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 844 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
kadonotakashi 0:8fdf9a60065b 845 * | | |1 = Capture function Enabled
kadonotakashi 0:8fdf9a60065b 846 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
kadonotakashi 0:8fdf9a60065b 847 * |[4] |CAPEN4 |Capture Function Enable Bits
kadonotakashi 0:8fdf9a60065b 848 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 849 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
kadonotakashi 0:8fdf9a60065b 850 * | | |1 = Capture function Enabled
kadonotakashi 0:8fdf9a60065b 851 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
kadonotakashi 0:8fdf9a60065b 852 * |[5] |CAPEN5 |Capture Function Enable Bits
kadonotakashi 0:8fdf9a60065b 853 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 854 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
kadonotakashi 0:8fdf9a60065b 855 * | | |1 = Capture function Enabled
kadonotakashi 0:8fdf9a60065b 856 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
kadonotakashi 0:8fdf9a60065b 857 * |[8] |CAPINV0 |Capture Inverter Enable Bits
kadonotakashi 0:8fdf9a60065b 858 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 859 * | | |0 = Capture source inverter Disabled.
kadonotakashi 0:8fdf9a60065b 860 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
kadonotakashi 0:8fdf9a60065b 861 * |[9] |CAPINV1 |Capture Inverter Enable Bits
kadonotakashi 0:8fdf9a60065b 862 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 863 * | | |0 = Capture source inverter Disabled.
kadonotakashi 0:8fdf9a60065b 864 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
kadonotakashi 0:8fdf9a60065b 865 * |[10] |CAPINV2 |Capture Inverter Enable Bits
kadonotakashi 0:8fdf9a60065b 866 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 867 * | | |0 = Capture source inverter Disabled.
kadonotakashi 0:8fdf9a60065b 868 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
kadonotakashi 0:8fdf9a60065b 869 * |[11] |CAPINV3 |Capture Inverter Enable Bits
kadonotakashi 0:8fdf9a60065b 870 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 871 * | | |0 = Capture source inverter Disabled.
kadonotakashi 0:8fdf9a60065b 872 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
kadonotakashi 0:8fdf9a60065b 873 * |[12] |CAPINV4 |Capture Inverter Enable Bits
kadonotakashi 0:8fdf9a60065b 874 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 875 * | | |0 = Capture source inverter Disabled.
kadonotakashi 0:8fdf9a60065b 876 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
kadonotakashi 0:8fdf9a60065b 877 * |[13] |CAPINV5 |Capture Inverter Enable Bits
kadonotakashi 0:8fdf9a60065b 878 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 879 * | | |0 = Capture source inverter Disabled.
kadonotakashi 0:8fdf9a60065b 880 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
kadonotakashi 0:8fdf9a60065b 881 * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 882 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 883 * | | |0 = Rising capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 884 * | | |1 = Rising capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 885 * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 886 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 887 * | | |0 = Rising capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 888 * | | |1 = Rising capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 889 * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 890 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 891 * | | |0 = Rising capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 892 * | | |1 = Rising capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 893 * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 894 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 895 * | | |0 = Rising capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 896 * | | |1 = Rising capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 897 * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 898 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 899 * | | |0 = Rising capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 900 * | | |1 = Rising capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 901 * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 902 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 903 * | | |0 = Rising capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 904 * | | |1 = Rising capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 905 * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 906 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 907 * | | |0 = Falling capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 908 * | | |1 = Falling capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 909 * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 910 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 911 * | | |0 = Falling capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 912 * | | |1 = Falling capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 913 * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 914 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 915 * | | |0 = Falling capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 916 * | | |1 = Falling capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 917 * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 918 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 919 * | | |0 = Falling capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 920 * | | |1 = Falling capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 921 * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 922 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 923 * | | |0 = Falling capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 924 * | | |1 = Falling capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 925 * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits
kadonotakashi 0:8fdf9a60065b 926 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 927 * | | |0 = Falling capture reload counter Disabled.
kadonotakashi 0:8fdf9a60065b 928 * | | |1 = Falling capture reload counter Enabled.
kadonotakashi 0:8fdf9a60065b 929 * @var BPWM_T::CAPSTS
kadonotakashi 0:8fdf9a60065b 930 * Offset: 0x208 BPWM Capture Status Register
kadonotakashi 0:8fdf9a60065b 931 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 932 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 933 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 934 * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 935 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
kadonotakashi 0:8fdf9a60065b 936 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 937 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
kadonotakashi 0:8fdf9a60065b 938 * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 939 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
kadonotakashi 0:8fdf9a60065b 940 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 941 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
kadonotakashi 0:8fdf9a60065b 942 * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 943 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
kadonotakashi 0:8fdf9a60065b 944 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 945 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
kadonotakashi 0:8fdf9a60065b 946 * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 947 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
kadonotakashi 0:8fdf9a60065b 948 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 949 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
kadonotakashi 0:8fdf9a60065b 950 * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 951 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
kadonotakashi 0:8fdf9a60065b 952 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 953 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
kadonotakashi 0:8fdf9a60065b 954 * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 955 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
kadonotakashi 0:8fdf9a60065b 956 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 957 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
kadonotakashi 0:8fdf9a60065b 958 * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 959 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
kadonotakashi 0:8fdf9a60065b 960 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 961 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
kadonotakashi 0:8fdf9a60065b 962 * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 963 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
kadonotakashi 0:8fdf9a60065b 964 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 965 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
kadonotakashi 0:8fdf9a60065b 966 * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 967 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
kadonotakashi 0:8fdf9a60065b 968 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 969 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
kadonotakashi 0:8fdf9a60065b 970 * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 971 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
kadonotakashi 0:8fdf9a60065b 972 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 973 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
kadonotakashi 0:8fdf9a60065b 974 * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 975 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
kadonotakashi 0:8fdf9a60065b 976 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 977 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
kadonotakashi 0:8fdf9a60065b 978 * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only)
kadonotakashi 0:8fdf9a60065b 979 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
kadonotakashi 0:8fdf9a60065b 980 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 981 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
kadonotakashi 0:8fdf9a60065b 982 * @var BPWM_T::RCAPDAT0
kadonotakashi 0:8fdf9a60065b 983 * Offset: 0x20C BPWM Rising Capture Data Register 0
kadonotakashi 0:8fdf9a60065b 984 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 985 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 986 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 987 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 988 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 989 * @var BPWM_T::FCAPDAT0
kadonotakashi 0:8fdf9a60065b 990 * Offset: 0x210 BPWM Falling Capture Data Register 0
kadonotakashi 0:8fdf9a60065b 991 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 992 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 993 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 994 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 995 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 996 * @var BPWM_T::RCAPDAT1
kadonotakashi 0:8fdf9a60065b 997 * Offset: 0x214 BPWM Rising Capture Data Register 1
kadonotakashi 0:8fdf9a60065b 998 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 999 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1000 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1001 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 1002 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 1003 * @var BPWM_T::FCAPDAT1
kadonotakashi 0:8fdf9a60065b 1004 * Offset: 0x218 BPWM Falling Capture Data Register 1
kadonotakashi 0:8fdf9a60065b 1005 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1006 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1007 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1008 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 1009 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 1010 * @var BPWM_T::RCAPDAT2
kadonotakashi 0:8fdf9a60065b 1011 * Offset: 0x21C BPWM Rising Capture Data Register 2
kadonotakashi 0:8fdf9a60065b 1012 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1013 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1014 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1015 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 1016 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 1017 * @var BPWM_T::FCAPDAT2
kadonotakashi 0:8fdf9a60065b 1018 * Offset: 0x220 BPWM Falling Capture Data Register 2
kadonotakashi 0:8fdf9a60065b 1019 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1020 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1021 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1022 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 1023 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 1024 * @var BPWM_T::RCAPDAT3
kadonotakashi 0:8fdf9a60065b 1025 * Offset: 0x224 BPWM Rising Capture Data Register 3
kadonotakashi 0:8fdf9a60065b 1026 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1027 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1028 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1029 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 1030 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 1031 * @var BPWM_T::FCAPDAT3
kadonotakashi 0:8fdf9a60065b 1032 * Offset: 0x228 BPWM Falling Capture Data Register 3
kadonotakashi 0:8fdf9a60065b 1033 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1034 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1035 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1036 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 1037 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 1038 * @var BPWM_T::RCAPDAT4
kadonotakashi 0:8fdf9a60065b 1039 * Offset: 0x22C BPWM Rising Capture Data Register 4
kadonotakashi 0:8fdf9a60065b 1040 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1041 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1042 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1043 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 1044 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 1045 * @var BPWM_T::FCAPDAT4
kadonotakashi 0:8fdf9a60065b 1046 * Offset: 0x230 BPWM Falling Capture Data Register 4
kadonotakashi 0:8fdf9a60065b 1047 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1048 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1049 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1050 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 1051 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 1052 * @var BPWM_T::RCAPDAT5
kadonotakashi 0:8fdf9a60065b 1053 * Offset: 0x234 BPWM Rising Capture Data Register 5
kadonotakashi 0:8fdf9a60065b 1054 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1055 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1056 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1057 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 1058 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 1059 * @var BPWM_T::FCAPDAT5
kadonotakashi 0:8fdf9a60065b 1060 * Offset: 0x238 BPWM Falling Capture Data Register 5
kadonotakashi 0:8fdf9a60065b 1061 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1062 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1063 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1064 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 1065 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
kadonotakashi 0:8fdf9a60065b 1066 * @var BPWM_T::CAPIEN
kadonotakashi 0:8fdf9a60065b 1067 * Offset: 0x250 BPWM Capture Interrupt Enable Register
kadonotakashi 0:8fdf9a60065b 1068 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1069 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1070 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1071 * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 1072 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1073 * | | |0 = Capture rising edge latch interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 1074 * | | |1 = Capture rising edge latch interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 1075 * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits
kadonotakashi 0:8fdf9a60065b 1076 * | | |Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1077 * | | |0 = Capture falling edge latch interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 1078 * | | |1 = Capture falling edge latch interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 1079 * @var BPWM_T::CAPIF
kadonotakashi 0:8fdf9a60065b 1080 * Offset: 0x254 BPWM Capture Interrupt Flag Register
kadonotakashi 0:8fdf9a60065b 1081 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1082 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1083 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1084 * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1085 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1086 * | | |0 = No capture rising latch condition happened.
kadonotakashi 0:8fdf9a60065b 1087 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1088 * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1089 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1090 * | | |0 = No capture rising latch condition happened.
kadonotakashi 0:8fdf9a60065b 1091 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1092 * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1093 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1094 * | | |0 = No capture rising latch condition happened.
kadonotakashi 0:8fdf9a60065b 1095 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1096 * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1097 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1098 * | | |0 = No capture rising latch condition happened.
kadonotakashi 0:8fdf9a60065b 1099 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1100 * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1101 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1102 * | | |0 = No capture rising latch condition happened.
kadonotakashi 0:8fdf9a60065b 1103 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1104 * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1105 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1106 * | | |0 = No capture rising latch condition happened.
kadonotakashi 0:8fdf9a60065b 1107 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1108 * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1109 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1110 * | | |0 = No capture falling latch condition happened.
kadonotakashi 0:8fdf9a60065b 1111 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1112 * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1113 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1114 * | | |0 = No capture falling latch condition happened.
kadonotakashi 0:8fdf9a60065b 1115 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1116 * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1117 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1118 * | | |0 = No capture falling latch condition happened.
kadonotakashi 0:8fdf9a60065b 1119 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1120 * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1121 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1122 * | | |0 = No capture falling latch condition happened.
kadonotakashi 0:8fdf9a60065b 1123 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1124 * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1125 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1126 * | | |0 = No capture falling latch condition happened.
kadonotakashi 0:8fdf9a60065b 1127 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1128 * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag
kadonotakashi 0:8fdf9a60065b 1129 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
kadonotakashi 0:8fdf9a60065b 1130 * | | |0 = No capture falling latch condition happened.
kadonotakashi 0:8fdf9a60065b 1131 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
kadonotakashi 0:8fdf9a60065b 1132 * @var BPWM_T::PBUF
kadonotakashi 0:8fdf9a60065b 1133 * Offset: 0x304 BPWM PERIOD Buffer
kadonotakashi 0:8fdf9a60065b 1134 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1135 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1136 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1137 * |[15:0] |PBUF |BPWM Period Buffer (Read Only)
kadonotakashi 0:8fdf9a60065b 1138 * | | |Used as PERIOD active register.
kadonotakashi 0:8fdf9a60065b 1139 * @var BPWM_T::CMPBUF[6]
kadonotakashi 0:8fdf9a60065b 1140 * Offset: 0x31C BPWM CMPDAT 0~5 Buffer
kadonotakashi 0:8fdf9a60065b 1141 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 1142 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 1143 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 1144 * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only)
kadonotakashi 0:8fdf9a60065b 1145 * | | |Used as CMP active register.
kadonotakashi 0:8fdf9a60065b 1146 */
kadonotakashi 0:8fdf9a60065b 1147 __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */
kadonotakashi 0:8fdf9a60065b 1148 __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */
kadonotakashi 0:8fdf9a60065b 1149 __I uint32_t RESERVED0[2];
kadonotakashi 0:8fdf9a60065b 1150 __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */
kadonotakashi 0:8fdf9a60065b 1151 __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */
kadonotakashi 0:8fdf9a60065b 1152 __I uint32_t RESERVED1[2];
kadonotakashi 0:8fdf9a60065b 1153 __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */
kadonotakashi 0:8fdf9a60065b 1154 __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */
kadonotakashi 0:8fdf9a60065b 1155 __I uint32_t RESERVED2[2];
kadonotakashi 0:8fdf9a60065b 1156 __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */
kadonotakashi 0:8fdf9a60065b 1157 __I uint32_t RESERVED3[7];
kadonotakashi 0:8fdf9a60065b 1158 __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] BPWM Comparator Register 0~5 */
kadonotakashi 0:8fdf9a60065b 1159 __I uint32_t RESERVED4[10];
kadonotakashi 0:8fdf9a60065b 1160 __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */
kadonotakashi 0:8fdf9a60065b 1161 __I uint32_t RESERVED5[7];
kadonotakashi 0:8fdf9a60065b 1162 __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */
kadonotakashi 0:8fdf9a60065b 1163 __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */
kadonotakashi 0:8fdf9a60065b 1164 __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */
kadonotakashi 0:8fdf9a60065b 1165 __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */
kadonotakashi 0:8fdf9a60065b 1166 __I uint32_t RESERVED6[5];
kadonotakashi 0:8fdf9a60065b 1167 __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */
kadonotakashi 0:8fdf9a60065b 1168 __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */
kadonotakashi 0:8fdf9a60065b 1169 __I uint32_t RESERVED7[1];
kadonotakashi 0:8fdf9a60065b 1170 __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */
kadonotakashi 0:8fdf9a60065b 1171 __I uint32_t RESERVED8[1];
kadonotakashi 0:8fdf9a60065b 1172 __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */
kadonotakashi 0:8fdf9a60065b 1173 __I uint32_t RESERVED9[3];
kadonotakashi 0:8fdf9a60065b 1174 __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */
kadonotakashi 0:8fdf9a60065b 1175 __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */
kadonotakashi 0:8fdf9a60065b 1176 __I uint32_t RESERVED10[4];
kadonotakashi 0:8fdf9a60065b 1177 __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */
kadonotakashi 0:8fdf9a60065b 1178 __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */
kadonotakashi 0:8fdf9a60065b 1179 __I uint32_t RESERVED11[2];
kadonotakashi 0:8fdf9a60065b 1180 __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */
kadonotakashi 0:8fdf9a60065b 1181 __I uint32_t RESERVED12[55];
kadonotakashi 0:8fdf9a60065b 1182 __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */
kadonotakashi 0:8fdf9a60065b 1183 __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */
kadonotakashi 0:8fdf9a60065b 1184 __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */
kadonotakashi 0:8fdf9a60065b 1185 BCAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] BPWM Rising and Falling Capture Data Register 0~5 */
kadonotakashi 0:8fdf9a60065b 1186 __I uint32_t RESERVED13[5];
kadonotakashi 0:8fdf9a60065b 1187 __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */
kadonotakashi 0:8fdf9a60065b 1188 __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */
kadonotakashi 0:8fdf9a60065b 1189 __I uint32_t RESERVED14[43];
kadonotakashi 0:8fdf9a60065b 1190 __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */
kadonotakashi 0:8fdf9a60065b 1191 __I uint32_t RESERVED15[5];
kadonotakashi 0:8fdf9a60065b 1192 __I uint32_t CMPBUF[6]; /*!< [0x031c~0x0330] BPWM CMPDAT 0~5 Buffer */
kadonotakashi 0:8fdf9a60065b 1193
kadonotakashi 0:8fdf9a60065b 1194 } BPWM_T;
kadonotakashi 0:8fdf9a60065b 1195
kadonotakashi 0:8fdf9a60065b 1196 /**
kadonotakashi 0:8fdf9a60065b 1197 @addtogroup BPWM_CONST BPWM Bit Field Definition
kadonotakashi 0:8fdf9a60065b 1198 Constant Definitions for BPWM Controller
kadonotakashi 0:8fdf9a60065b 1199 @{ */
kadonotakashi 0:8fdf9a60065b 1200
kadonotakashi 0:8fdf9a60065b 1201 #define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */
kadonotakashi 0:8fdf9a60065b 1202 #define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */
kadonotakashi 0:8fdf9a60065b 1203
kadonotakashi 0:8fdf9a60065b 1204 #define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */
kadonotakashi 0:8fdf9a60065b 1205 #define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */
kadonotakashi 0:8fdf9a60065b 1206
kadonotakashi 0:8fdf9a60065b 1207 #define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */
kadonotakashi 0:8fdf9a60065b 1208 #define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */
kadonotakashi 0:8fdf9a60065b 1209
kadonotakashi 0:8fdf9a60065b 1210 #define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */
kadonotakashi 0:8fdf9a60065b 1211 #define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */
kadonotakashi 0:8fdf9a60065b 1212
kadonotakashi 0:8fdf9a60065b 1213 #define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */
kadonotakashi 0:8fdf9a60065b 1214 #define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */
kadonotakashi 0:8fdf9a60065b 1215
kadonotakashi 0:8fdf9a60065b 1216 #define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */
kadonotakashi 0:8fdf9a60065b 1217 #define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */
kadonotakashi 0:8fdf9a60065b 1218
kadonotakashi 0:8fdf9a60065b 1219 #define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */
kadonotakashi 0:8fdf9a60065b 1220 #define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1221
kadonotakashi 0:8fdf9a60065b 1222 #define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */
kadonotakashi 0:8fdf9a60065b 1223 #define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */
kadonotakashi 0:8fdf9a60065b 1224
kadonotakashi 0:8fdf9a60065b 1225 #define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */
kadonotakashi 0:8fdf9a60065b 1226 #define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */
kadonotakashi 0:8fdf9a60065b 1227
kadonotakashi 0:8fdf9a60065b 1228 #define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */
kadonotakashi 0:8fdf9a60065b 1229 #define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */
kadonotakashi 0:8fdf9a60065b 1230
kadonotakashi 0:8fdf9a60065b 1231 #define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */
kadonotakashi 0:8fdf9a60065b 1232 #define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */
kadonotakashi 0:8fdf9a60065b 1233
kadonotakashi 0:8fdf9a60065b 1234 #define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */
kadonotakashi 0:8fdf9a60065b 1235 #define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */
kadonotakashi 0:8fdf9a60065b 1236
kadonotakashi 0:8fdf9a60065b 1237 #define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */
kadonotakashi 0:8fdf9a60065b 1238 #define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */
kadonotakashi 0:8fdf9a60065b 1239
kadonotakashi 0:8fdf9a60065b 1240 #define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */
kadonotakashi 0:8fdf9a60065b 1241 #define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */
kadonotakashi 0:8fdf9a60065b 1242
kadonotakashi 0:8fdf9a60065b 1243 #define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */
kadonotakashi 0:8fdf9a60065b 1244 #define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */
kadonotakashi 0:8fdf9a60065b 1245
kadonotakashi 0:8fdf9a60065b 1246 #define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */
kadonotakashi 0:8fdf9a60065b 1247 #define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */
kadonotakashi 0:8fdf9a60065b 1248
kadonotakashi 0:8fdf9a60065b 1249 #define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */
kadonotakashi 0:8fdf9a60065b 1250 #define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */
kadonotakashi 0:8fdf9a60065b 1251
kadonotakashi 0:8fdf9a60065b 1252 #define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */
kadonotakashi 0:8fdf9a60065b 1253 #define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1254
kadonotakashi 0:8fdf9a60065b 1255 #define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */
kadonotakashi 0:8fdf9a60065b 1256 #define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */
kadonotakashi 0:8fdf9a60065b 1257
kadonotakashi 0:8fdf9a60065b 1258 #define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */
kadonotakashi 0:8fdf9a60065b 1259 #define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */
kadonotakashi 0:8fdf9a60065b 1260
kadonotakashi 0:8fdf9a60065b 1261 #define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */
kadonotakashi 0:8fdf9a60065b 1262 #define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1263
kadonotakashi 0:8fdf9a60065b 1264 #define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */
kadonotakashi 0:8fdf9a60065b 1265 #define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1266
kadonotakashi 0:8fdf9a60065b 1267 #define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */
kadonotakashi 0:8fdf9a60065b 1268 #define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1269
kadonotakashi 0:8fdf9a60065b 1270 #define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */
kadonotakashi 0:8fdf9a60065b 1271 #define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1272
kadonotakashi 0:8fdf9a60065b 1273 #define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */
kadonotakashi 0:8fdf9a60065b 1274 #define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1275
kadonotakashi 0:8fdf9a60065b 1276 #define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */
kadonotakashi 0:8fdf9a60065b 1277 #define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1278
kadonotakashi 0:8fdf9a60065b 1279 #define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */
kadonotakashi 0:8fdf9a60065b 1280 #define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */
kadonotakashi 0:8fdf9a60065b 1281
kadonotakashi 0:8fdf9a60065b 1282 #define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */
kadonotakashi 0:8fdf9a60065b 1283 #define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */
kadonotakashi 0:8fdf9a60065b 1284
kadonotakashi 0:8fdf9a60065b 1285 #define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */
kadonotakashi 0:8fdf9a60065b 1286 #define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */
kadonotakashi 0:8fdf9a60065b 1287
kadonotakashi 0:8fdf9a60065b 1288 #define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */
kadonotakashi 0:8fdf9a60065b 1289 #define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */
kadonotakashi 0:8fdf9a60065b 1290
kadonotakashi 0:8fdf9a60065b 1291 #define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */
kadonotakashi 0:8fdf9a60065b 1292 #define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */
kadonotakashi 0:8fdf9a60065b 1293
kadonotakashi 0:8fdf9a60065b 1294 #define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */
kadonotakashi 0:8fdf9a60065b 1295 #define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */
kadonotakashi 0:8fdf9a60065b 1296
kadonotakashi 0:8fdf9a60065b 1297 #define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */
kadonotakashi 0:8fdf9a60065b 1298 #define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */
kadonotakashi 0:8fdf9a60065b 1299
kadonotakashi 0:8fdf9a60065b 1300 #define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */
kadonotakashi 0:8fdf9a60065b 1301 #define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */
kadonotakashi 0:8fdf9a60065b 1302
kadonotakashi 0:8fdf9a60065b 1303 #define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */
kadonotakashi 0:8fdf9a60065b 1304 #define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */
kadonotakashi 0:8fdf9a60065b 1305
kadonotakashi 0:8fdf9a60065b 1306 #define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */
kadonotakashi 0:8fdf9a60065b 1307 #define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */
kadonotakashi 0:8fdf9a60065b 1308
kadonotakashi 0:8fdf9a60065b 1309 #define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */
kadonotakashi 0:8fdf9a60065b 1310 #define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */
kadonotakashi 0:8fdf9a60065b 1311
kadonotakashi 0:8fdf9a60065b 1312 #define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */
kadonotakashi 0:8fdf9a60065b 1313 #define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */
kadonotakashi 0:8fdf9a60065b 1314
kadonotakashi 0:8fdf9a60065b 1315 #define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */
kadonotakashi 0:8fdf9a60065b 1316 #define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */
kadonotakashi 0:8fdf9a60065b 1317
kadonotakashi 0:8fdf9a60065b 1318 #define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */
kadonotakashi 0:8fdf9a60065b 1319 #define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */
kadonotakashi 0:8fdf9a60065b 1320
kadonotakashi 0:8fdf9a60065b 1321 #define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */
kadonotakashi 0:8fdf9a60065b 1322 #define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */
kadonotakashi 0:8fdf9a60065b 1323
kadonotakashi 0:8fdf9a60065b 1324 #define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */
kadonotakashi 0:8fdf9a60065b 1325 #define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */
kadonotakashi 0:8fdf9a60065b 1326
kadonotakashi 0:8fdf9a60065b 1327 #define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */
kadonotakashi 0:8fdf9a60065b 1328 #define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */
kadonotakashi 0:8fdf9a60065b 1329
kadonotakashi 0:8fdf9a60065b 1330 #define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */
kadonotakashi 0:8fdf9a60065b 1331 #define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */
kadonotakashi 0:8fdf9a60065b 1332
kadonotakashi 0:8fdf9a60065b 1333 #define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */
kadonotakashi 0:8fdf9a60065b 1334 #define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */
kadonotakashi 0:8fdf9a60065b 1335
kadonotakashi 0:8fdf9a60065b 1336 #define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */
kadonotakashi 0:8fdf9a60065b 1337 #define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */
kadonotakashi 0:8fdf9a60065b 1338
kadonotakashi 0:8fdf9a60065b 1339 #define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */
kadonotakashi 0:8fdf9a60065b 1340 #define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */
kadonotakashi 0:8fdf9a60065b 1341
kadonotakashi 0:8fdf9a60065b 1342 #define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */
kadonotakashi 0:8fdf9a60065b 1343 #define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */
kadonotakashi 0:8fdf9a60065b 1344
kadonotakashi 0:8fdf9a60065b 1345 #define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */
kadonotakashi 0:8fdf9a60065b 1346 #define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */
kadonotakashi 0:8fdf9a60065b 1347
kadonotakashi 0:8fdf9a60065b 1348 #define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */
kadonotakashi 0:8fdf9a60065b 1349 #define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */
kadonotakashi 0:8fdf9a60065b 1350
kadonotakashi 0:8fdf9a60065b 1351 #define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */
kadonotakashi 0:8fdf9a60065b 1352 #define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */
kadonotakashi 0:8fdf9a60065b 1353
kadonotakashi 0:8fdf9a60065b 1354 #define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */
kadonotakashi 0:8fdf9a60065b 1355 #define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */
kadonotakashi 0:8fdf9a60065b 1356
kadonotakashi 0:8fdf9a60065b 1357 #define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */
kadonotakashi 0:8fdf9a60065b 1358 #define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */
kadonotakashi 0:8fdf9a60065b 1359
kadonotakashi 0:8fdf9a60065b 1360 #define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */
kadonotakashi 0:8fdf9a60065b 1361 #define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */
kadonotakashi 0:8fdf9a60065b 1362
kadonotakashi 0:8fdf9a60065b 1363 #define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */
kadonotakashi 0:8fdf9a60065b 1364 #define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */
kadonotakashi 0:8fdf9a60065b 1365
kadonotakashi 0:8fdf9a60065b 1366 #define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */
kadonotakashi 0:8fdf9a60065b 1367 #define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */
kadonotakashi 0:8fdf9a60065b 1368
kadonotakashi 0:8fdf9a60065b 1369 #define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */
kadonotakashi 0:8fdf9a60065b 1370 #define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1371
kadonotakashi 0:8fdf9a60065b 1372 #define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */
kadonotakashi 0:8fdf9a60065b 1373 #define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */
kadonotakashi 0:8fdf9a60065b 1374
kadonotakashi 0:8fdf9a60065b 1375 #define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */
kadonotakashi 0:8fdf9a60065b 1376 #define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */
kadonotakashi 0:8fdf9a60065b 1377
kadonotakashi 0:8fdf9a60065b 1378 #define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */
kadonotakashi 0:8fdf9a60065b 1379 #define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */
kadonotakashi 0:8fdf9a60065b 1380
kadonotakashi 0:8fdf9a60065b 1381 #define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */
kadonotakashi 0:8fdf9a60065b 1382 #define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */
kadonotakashi 0:8fdf9a60065b 1383
kadonotakashi 0:8fdf9a60065b 1384 #define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */
kadonotakashi 0:8fdf9a60065b 1385 #define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */
kadonotakashi 0:8fdf9a60065b 1386
kadonotakashi 0:8fdf9a60065b 1387 #define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */
kadonotakashi 0:8fdf9a60065b 1388 #define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */
kadonotakashi 0:8fdf9a60065b 1389
kadonotakashi 0:8fdf9a60065b 1390 #define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */
kadonotakashi 0:8fdf9a60065b 1391 #define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */
kadonotakashi 0:8fdf9a60065b 1392
kadonotakashi 0:8fdf9a60065b 1393 #define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */
kadonotakashi 0:8fdf9a60065b 1394 #define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */
kadonotakashi 0:8fdf9a60065b 1395
kadonotakashi 0:8fdf9a60065b 1396 #define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */
kadonotakashi 0:8fdf9a60065b 1397 #define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */
kadonotakashi 0:8fdf9a60065b 1398
kadonotakashi 0:8fdf9a60065b 1399 #define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */
kadonotakashi 0:8fdf9a60065b 1400 #define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */
kadonotakashi 0:8fdf9a60065b 1401
kadonotakashi 0:8fdf9a60065b 1402 #define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */
kadonotakashi 0:8fdf9a60065b 1403 #define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */
kadonotakashi 0:8fdf9a60065b 1404
kadonotakashi 0:8fdf9a60065b 1405 #define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */
kadonotakashi 0:8fdf9a60065b 1406 #define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */
kadonotakashi 0:8fdf9a60065b 1407
kadonotakashi 0:8fdf9a60065b 1408 #define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */
kadonotakashi 0:8fdf9a60065b 1409 #define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */
kadonotakashi 0:8fdf9a60065b 1410
kadonotakashi 0:8fdf9a60065b 1411 #define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */
kadonotakashi 0:8fdf9a60065b 1412 #define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */
kadonotakashi 0:8fdf9a60065b 1413
kadonotakashi 0:8fdf9a60065b 1414 #define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */
kadonotakashi 0:8fdf9a60065b 1415 #define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */
kadonotakashi 0:8fdf9a60065b 1416
kadonotakashi 0:8fdf9a60065b 1417 #define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */
kadonotakashi 0:8fdf9a60065b 1418 #define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */
kadonotakashi 0:8fdf9a60065b 1419
kadonotakashi 0:8fdf9a60065b 1420 #define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */
kadonotakashi 0:8fdf9a60065b 1421 #define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */
kadonotakashi 0:8fdf9a60065b 1422
kadonotakashi 0:8fdf9a60065b 1423 #define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */
kadonotakashi 0:8fdf9a60065b 1424 #define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */
kadonotakashi 0:8fdf9a60065b 1425
kadonotakashi 0:8fdf9a60065b 1426 #define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */
kadonotakashi 0:8fdf9a60065b 1427 #define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */
kadonotakashi 0:8fdf9a60065b 1428
kadonotakashi 0:8fdf9a60065b 1429 #define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */
kadonotakashi 0:8fdf9a60065b 1430 #define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */
kadonotakashi 0:8fdf9a60065b 1431
kadonotakashi 0:8fdf9a60065b 1432 #define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */
kadonotakashi 0:8fdf9a60065b 1433 #define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1434
kadonotakashi 0:8fdf9a60065b 1435 #define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */
kadonotakashi 0:8fdf9a60065b 1436 #define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */
kadonotakashi 0:8fdf9a60065b 1437
kadonotakashi 0:8fdf9a60065b 1438 #define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */
kadonotakashi 0:8fdf9a60065b 1439 #define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */
kadonotakashi 0:8fdf9a60065b 1440
kadonotakashi 0:8fdf9a60065b 1441 #define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */
kadonotakashi 0:8fdf9a60065b 1442 #define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */
kadonotakashi 0:8fdf9a60065b 1443
kadonotakashi 0:8fdf9a60065b 1444 #define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */
kadonotakashi 0:8fdf9a60065b 1445 #define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */
kadonotakashi 0:8fdf9a60065b 1446
kadonotakashi 0:8fdf9a60065b 1447 #define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */
kadonotakashi 0:8fdf9a60065b 1448 #define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */
kadonotakashi 0:8fdf9a60065b 1449
kadonotakashi 0:8fdf9a60065b 1450 #define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */
kadonotakashi 0:8fdf9a60065b 1451 #define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */
kadonotakashi 0:8fdf9a60065b 1452
kadonotakashi 0:8fdf9a60065b 1453 #define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */
kadonotakashi 0:8fdf9a60065b 1454 #define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1455
kadonotakashi 0:8fdf9a60065b 1456 #define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */
kadonotakashi 0:8fdf9a60065b 1457 #define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1458
kadonotakashi 0:8fdf9a60065b 1459 #define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */
kadonotakashi 0:8fdf9a60065b 1460 #define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1461
kadonotakashi 0:8fdf9a60065b 1462 #define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */
kadonotakashi 0:8fdf9a60065b 1463 #define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */
kadonotakashi 0:8fdf9a60065b 1464
kadonotakashi 0:8fdf9a60065b 1465 #define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */
kadonotakashi 0:8fdf9a60065b 1466 #define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */
kadonotakashi 0:8fdf9a60065b 1467
kadonotakashi 0:8fdf9a60065b 1468 #define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */
kadonotakashi 0:8fdf9a60065b 1469 #define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */
kadonotakashi 0:8fdf9a60065b 1470
kadonotakashi 0:8fdf9a60065b 1471 #define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */
kadonotakashi 0:8fdf9a60065b 1472 #define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */
kadonotakashi 0:8fdf9a60065b 1473
kadonotakashi 0:8fdf9a60065b 1474 #define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */
kadonotakashi 0:8fdf9a60065b 1475 #define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */
kadonotakashi 0:8fdf9a60065b 1476
kadonotakashi 0:8fdf9a60065b 1477 #define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */
kadonotakashi 0:8fdf9a60065b 1478 #define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */
kadonotakashi 0:8fdf9a60065b 1479
kadonotakashi 0:8fdf9a60065b 1480 #define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */
kadonotakashi 0:8fdf9a60065b 1481 #define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1482
kadonotakashi 0:8fdf9a60065b 1483 #define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */
kadonotakashi 0:8fdf9a60065b 1484 #define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */
kadonotakashi 0:8fdf9a60065b 1485
kadonotakashi 0:8fdf9a60065b 1486 #define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */
kadonotakashi 0:8fdf9a60065b 1487 #define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */
kadonotakashi 0:8fdf9a60065b 1488
kadonotakashi 0:8fdf9a60065b 1489 #define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */
kadonotakashi 0:8fdf9a60065b 1490 #define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */
kadonotakashi 0:8fdf9a60065b 1491
kadonotakashi 0:8fdf9a60065b 1492 #define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */
kadonotakashi 0:8fdf9a60065b 1493 #define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */
kadonotakashi 0:8fdf9a60065b 1494
kadonotakashi 0:8fdf9a60065b 1495 #define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */
kadonotakashi 0:8fdf9a60065b 1496 #define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */
kadonotakashi 0:8fdf9a60065b 1497
kadonotakashi 0:8fdf9a60065b 1498 #define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */
kadonotakashi 0:8fdf9a60065b 1499 #define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */
kadonotakashi 0:8fdf9a60065b 1500
kadonotakashi 0:8fdf9a60065b 1501 #define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */
kadonotakashi 0:8fdf9a60065b 1502 #define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */
kadonotakashi 0:8fdf9a60065b 1503
kadonotakashi 0:8fdf9a60065b 1504 #define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */
kadonotakashi 0:8fdf9a60065b 1505 #define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */
kadonotakashi 0:8fdf9a60065b 1506
kadonotakashi 0:8fdf9a60065b 1507 #define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */
kadonotakashi 0:8fdf9a60065b 1508 #define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */
kadonotakashi 0:8fdf9a60065b 1509
kadonotakashi 0:8fdf9a60065b 1510 #define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */
kadonotakashi 0:8fdf9a60065b 1511 #define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */
kadonotakashi 0:8fdf9a60065b 1512
kadonotakashi 0:8fdf9a60065b 1513 #define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */
kadonotakashi 0:8fdf9a60065b 1514 #define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */
kadonotakashi 0:8fdf9a60065b 1515
kadonotakashi 0:8fdf9a60065b 1516 #define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */
kadonotakashi 0:8fdf9a60065b 1517 #define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */
kadonotakashi 0:8fdf9a60065b 1518
kadonotakashi 0:8fdf9a60065b 1519 #define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */
kadonotakashi 0:8fdf9a60065b 1520 #define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */
kadonotakashi 0:8fdf9a60065b 1521
kadonotakashi 0:8fdf9a60065b 1522 #define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */
kadonotakashi 0:8fdf9a60065b 1523 #define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */
kadonotakashi 0:8fdf9a60065b 1524
kadonotakashi 0:8fdf9a60065b 1525 #define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */
kadonotakashi 0:8fdf9a60065b 1526 #define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */
kadonotakashi 0:8fdf9a60065b 1527
kadonotakashi 0:8fdf9a60065b 1528 #define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */
kadonotakashi 0:8fdf9a60065b 1529 #define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */
kadonotakashi 0:8fdf9a60065b 1530
kadonotakashi 0:8fdf9a60065b 1531 #define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */
kadonotakashi 0:8fdf9a60065b 1532 #define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */
kadonotakashi 0:8fdf9a60065b 1533
kadonotakashi 0:8fdf9a60065b 1534 #define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */
kadonotakashi 0:8fdf9a60065b 1535 #define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */
kadonotakashi 0:8fdf9a60065b 1536
kadonotakashi 0:8fdf9a60065b 1537 #define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */
kadonotakashi 0:8fdf9a60065b 1538 #define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */
kadonotakashi 0:8fdf9a60065b 1539
kadonotakashi 0:8fdf9a60065b 1540 #define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */
kadonotakashi 0:8fdf9a60065b 1541 #define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */
kadonotakashi 0:8fdf9a60065b 1542
kadonotakashi 0:8fdf9a60065b 1543 #define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */
kadonotakashi 0:8fdf9a60065b 1544 #define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */
kadonotakashi 0:8fdf9a60065b 1545
kadonotakashi 0:8fdf9a60065b 1546 #define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */
kadonotakashi 0:8fdf9a60065b 1547 #define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */
kadonotakashi 0:8fdf9a60065b 1548
kadonotakashi 0:8fdf9a60065b 1549 #define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */
kadonotakashi 0:8fdf9a60065b 1550 #define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */
kadonotakashi 0:8fdf9a60065b 1551
kadonotakashi 0:8fdf9a60065b 1552 #define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */
kadonotakashi 0:8fdf9a60065b 1553 #define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1554
kadonotakashi 0:8fdf9a60065b 1555 #define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */
kadonotakashi 0:8fdf9a60065b 1556 #define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */
kadonotakashi 0:8fdf9a60065b 1557
kadonotakashi 0:8fdf9a60065b 1558 #define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */
kadonotakashi 0:8fdf9a60065b 1559 #define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */
kadonotakashi 0:8fdf9a60065b 1560
kadonotakashi 0:8fdf9a60065b 1561 #define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */
kadonotakashi 0:8fdf9a60065b 1562 #define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */
kadonotakashi 0:8fdf9a60065b 1563
kadonotakashi 0:8fdf9a60065b 1564 #define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */
kadonotakashi 0:8fdf9a60065b 1565 #define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */
kadonotakashi 0:8fdf9a60065b 1566
kadonotakashi 0:8fdf9a60065b 1567 #define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */
kadonotakashi 0:8fdf9a60065b 1568 #define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */
kadonotakashi 0:8fdf9a60065b 1569
kadonotakashi 0:8fdf9a60065b 1570 #define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */
kadonotakashi 0:8fdf9a60065b 1571 #define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */
kadonotakashi 0:8fdf9a60065b 1572
kadonotakashi 0:8fdf9a60065b 1573 #define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */
kadonotakashi 0:8fdf9a60065b 1574 #define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */
kadonotakashi 0:8fdf9a60065b 1575
kadonotakashi 0:8fdf9a60065b 1576 #define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */
kadonotakashi 0:8fdf9a60065b 1577 #define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */
kadonotakashi 0:8fdf9a60065b 1578
kadonotakashi 0:8fdf9a60065b 1579 #define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */
kadonotakashi 0:8fdf9a60065b 1580 #define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */
kadonotakashi 0:8fdf9a60065b 1581
kadonotakashi 0:8fdf9a60065b 1582 #define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */
kadonotakashi 0:8fdf9a60065b 1583 #define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */
kadonotakashi 0:8fdf9a60065b 1584
kadonotakashi 0:8fdf9a60065b 1585 #define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */
kadonotakashi 0:8fdf9a60065b 1586 #define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1587
kadonotakashi 0:8fdf9a60065b 1588 #define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */
kadonotakashi 0:8fdf9a60065b 1589 #define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */
kadonotakashi 0:8fdf9a60065b 1590
kadonotakashi 0:8fdf9a60065b 1591 #define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */
kadonotakashi 0:8fdf9a60065b 1592 #define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */
kadonotakashi 0:8fdf9a60065b 1593
kadonotakashi 0:8fdf9a60065b 1594 #define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */
kadonotakashi 0:8fdf9a60065b 1595 #define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */
kadonotakashi 0:8fdf9a60065b 1596
kadonotakashi 0:8fdf9a60065b 1597 #define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */
kadonotakashi 0:8fdf9a60065b 1598 #define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */
kadonotakashi 0:8fdf9a60065b 1599
kadonotakashi 0:8fdf9a60065b 1600 #define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */
kadonotakashi 0:8fdf9a60065b 1601 #define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */
kadonotakashi 0:8fdf9a60065b 1602
kadonotakashi 0:8fdf9a60065b 1603 #define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */
kadonotakashi 0:8fdf9a60065b 1604 #define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */
kadonotakashi 0:8fdf9a60065b 1605
kadonotakashi 0:8fdf9a60065b 1606 #define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */
kadonotakashi 0:8fdf9a60065b 1607 #define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */
kadonotakashi 0:8fdf9a60065b 1608
kadonotakashi 0:8fdf9a60065b 1609 #define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */
kadonotakashi 0:8fdf9a60065b 1610 #define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */
kadonotakashi 0:8fdf9a60065b 1611
kadonotakashi 0:8fdf9a60065b 1612 #define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */
kadonotakashi 0:8fdf9a60065b 1613 #define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */
kadonotakashi 0:8fdf9a60065b 1614
kadonotakashi 0:8fdf9a60065b 1615 #define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */
kadonotakashi 0:8fdf9a60065b 1616 #define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */
kadonotakashi 0:8fdf9a60065b 1617
kadonotakashi 0:8fdf9a60065b 1618 #define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */
kadonotakashi 0:8fdf9a60065b 1619 #define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1620
kadonotakashi 0:8fdf9a60065b 1621 #define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */
kadonotakashi 0:8fdf9a60065b 1622 #define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */
kadonotakashi 0:8fdf9a60065b 1623
kadonotakashi 0:8fdf9a60065b 1624 #define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */
kadonotakashi 0:8fdf9a60065b 1625 #define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */
kadonotakashi 0:8fdf9a60065b 1626
kadonotakashi 0:8fdf9a60065b 1627 #define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */
kadonotakashi 0:8fdf9a60065b 1628 #define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */
kadonotakashi 0:8fdf9a60065b 1629
kadonotakashi 0:8fdf9a60065b 1630 #define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */
kadonotakashi 0:8fdf9a60065b 1631 #define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */
kadonotakashi 0:8fdf9a60065b 1632
kadonotakashi 0:8fdf9a60065b 1633 #define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */
kadonotakashi 0:8fdf9a60065b 1634 #define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */
kadonotakashi 0:8fdf9a60065b 1635
kadonotakashi 0:8fdf9a60065b 1636 #define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */
kadonotakashi 0:8fdf9a60065b 1637 #define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */
kadonotakashi 0:8fdf9a60065b 1638
kadonotakashi 0:8fdf9a60065b 1639 #define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */
kadonotakashi 0:8fdf9a60065b 1640 #define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1641
kadonotakashi 0:8fdf9a60065b 1642 #define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */
kadonotakashi 0:8fdf9a60065b 1643 #define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */
kadonotakashi 0:8fdf9a60065b 1644
kadonotakashi 0:8fdf9a60065b 1645 #define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */
kadonotakashi 0:8fdf9a60065b 1646 #define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */
kadonotakashi 0:8fdf9a60065b 1647
kadonotakashi 0:8fdf9a60065b 1648 #define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */
kadonotakashi 0:8fdf9a60065b 1649 #define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */
kadonotakashi 0:8fdf9a60065b 1650
kadonotakashi 0:8fdf9a60065b 1651 #define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */
kadonotakashi 0:8fdf9a60065b 1652 #define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */
kadonotakashi 0:8fdf9a60065b 1653
kadonotakashi 0:8fdf9a60065b 1654 #define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */
kadonotakashi 0:8fdf9a60065b 1655 #define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */
kadonotakashi 0:8fdf9a60065b 1656
kadonotakashi 0:8fdf9a60065b 1657 #define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */
kadonotakashi 0:8fdf9a60065b 1658 #define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */
kadonotakashi 0:8fdf9a60065b 1659
kadonotakashi 0:8fdf9a60065b 1660 #define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */
kadonotakashi 0:8fdf9a60065b 1661 #define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */
kadonotakashi 0:8fdf9a60065b 1662
kadonotakashi 0:8fdf9a60065b 1663 #define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */
kadonotakashi 0:8fdf9a60065b 1664 #define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */
kadonotakashi 0:8fdf9a60065b 1665
kadonotakashi 0:8fdf9a60065b 1666 #define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */
kadonotakashi 0:8fdf9a60065b 1667 #define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */
kadonotakashi 0:8fdf9a60065b 1668
kadonotakashi 0:8fdf9a60065b 1669 #define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */
kadonotakashi 0:8fdf9a60065b 1670 #define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */
kadonotakashi 0:8fdf9a60065b 1671
kadonotakashi 0:8fdf9a60065b 1672 #define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */
kadonotakashi 0:8fdf9a60065b 1673 #define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */
kadonotakashi 0:8fdf9a60065b 1674
kadonotakashi 0:8fdf9a60065b 1675 #define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */
kadonotakashi 0:8fdf9a60065b 1676 #define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */
kadonotakashi 0:8fdf9a60065b 1677
kadonotakashi 0:8fdf9a60065b 1678 #define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */
kadonotakashi 0:8fdf9a60065b 1679 #define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */
kadonotakashi 0:8fdf9a60065b 1680
kadonotakashi 0:8fdf9a60065b 1681 #define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */
kadonotakashi 0:8fdf9a60065b 1682 #define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1683
kadonotakashi 0:8fdf9a60065b 1684 #define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */
kadonotakashi 0:8fdf9a60065b 1685 #define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */
kadonotakashi 0:8fdf9a60065b 1686
kadonotakashi 0:8fdf9a60065b 1687 #define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */
kadonotakashi 0:8fdf9a60065b 1688 #define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */
kadonotakashi 0:8fdf9a60065b 1689
kadonotakashi 0:8fdf9a60065b 1690 #define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */
kadonotakashi 0:8fdf9a60065b 1691 #define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */
kadonotakashi 0:8fdf9a60065b 1692
kadonotakashi 0:8fdf9a60065b 1693 #define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */
kadonotakashi 0:8fdf9a60065b 1694 #define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */
kadonotakashi 0:8fdf9a60065b 1695
kadonotakashi 0:8fdf9a60065b 1696 #define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */
kadonotakashi 0:8fdf9a60065b 1697 #define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */
kadonotakashi 0:8fdf9a60065b 1698
kadonotakashi 0:8fdf9a60065b 1699 #define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */
kadonotakashi 0:8fdf9a60065b 1700 #define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */
kadonotakashi 0:8fdf9a60065b 1701
kadonotakashi 0:8fdf9a60065b 1702 #define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */
kadonotakashi 0:8fdf9a60065b 1703 #define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */
kadonotakashi 0:8fdf9a60065b 1704
kadonotakashi 0:8fdf9a60065b 1705 #define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */
kadonotakashi 0:8fdf9a60065b 1706 #define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */
kadonotakashi 0:8fdf9a60065b 1707
kadonotakashi 0:8fdf9a60065b 1708 #define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */
kadonotakashi 0:8fdf9a60065b 1709 #define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */
kadonotakashi 0:8fdf9a60065b 1710
kadonotakashi 0:8fdf9a60065b 1711 #define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */
kadonotakashi 0:8fdf9a60065b 1712 #define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */
kadonotakashi 0:8fdf9a60065b 1713
kadonotakashi 0:8fdf9a60065b 1714 #define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */
kadonotakashi 0:8fdf9a60065b 1715 #define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */
kadonotakashi 0:8fdf9a60065b 1716
kadonotakashi 0:8fdf9a60065b 1717 #define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */
kadonotakashi 0:8fdf9a60065b 1718 #define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */
kadonotakashi 0:8fdf9a60065b 1719
kadonotakashi 0:8fdf9a60065b 1720 #define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */
kadonotakashi 0:8fdf9a60065b 1721 #define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */
kadonotakashi 0:8fdf9a60065b 1722
kadonotakashi 0:8fdf9a60065b 1723 #define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */
kadonotakashi 0:8fdf9a60065b 1724 #define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */
kadonotakashi 0:8fdf9a60065b 1725
kadonotakashi 0:8fdf9a60065b 1726 #define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */
kadonotakashi 0:8fdf9a60065b 1727 #define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */
kadonotakashi 0:8fdf9a60065b 1728
kadonotakashi 0:8fdf9a60065b 1729 #define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */
kadonotakashi 0:8fdf9a60065b 1730 #define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */
kadonotakashi 0:8fdf9a60065b 1731
kadonotakashi 0:8fdf9a60065b 1732 #define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */
kadonotakashi 0:8fdf9a60065b 1733 #define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */
kadonotakashi 0:8fdf9a60065b 1734
kadonotakashi 0:8fdf9a60065b 1735 #define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */
kadonotakashi 0:8fdf9a60065b 1736 #define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */
kadonotakashi 0:8fdf9a60065b 1737
kadonotakashi 0:8fdf9a60065b 1738 #define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */
kadonotakashi 0:8fdf9a60065b 1739 #define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */
kadonotakashi 0:8fdf9a60065b 1740
kadonotakashi 0:8fdf9a60065b 1741 #define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */
kadonotakashi 0:8fdf9a60065b 1742 #define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */
kadonotakashi 0:8fdf9a60065b 1743
kadonotakashi 0:8fdf9a60065b 1744 #define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */
kadonotakashi 0:8fdf9a60065b 1745 #define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */
kadonotakashi 0:8fdf9a60065b 1746
kadonotakashi 0:8fdf9a60065b 1747 #define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */
kadonotakashi 0:8fdf9a60065b 1748 #define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */
kadonotakashi 0:8fdf9a60065b 1749
kadonotakashi 0:8fdf9a60065b 1750 #define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */
kadonotakashi 0:8fdf9a60065b 1751 #define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */
kadonotakashi 0:8fdf9a60065b 1752
kadonotakashi 0:8fdf9a60065b 1753 #define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */
kadonotakashi 0:8fdf9a60065b 1754 #define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */
kadonotakashi 0:8fdf9a60065b 1755
kadonotakashi 0:8fdf9a60065b 1756 #define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */
kadonotakashi 0:8fdf9a60065b 1757 #define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */
kadonotakashi 0:8fdf9a60065b 1758
kadonotakashi 0:8fdf9a60065b 1759 #define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */
kadonotakashi 0:8fdf9a60065b 1760 #define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */
kadonotakashi 0:8fdf9a60065b 1761
kadonotakashi 0:8fdf9a60065b 1762 #define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */
kadonotakashi 0:8fdf9a60065b 1763 #define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */
kadonotakashi 0:8fdf9a60065b 1764
kadonotakashi 0:8fdf9a60065b 1765 #define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1766 #define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1767
kadonotakashi 0:8fdf9a60065b 1768 #define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1769 #define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1770
kadonotakashi 0:8fdf9a60065b 1771 #define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1772 #define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1773
kadonotakashi 0:8fdf9a60065b 1774 #define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1775 #define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1776
kadonotakashi 0:8fdf9a60065b 1777 #define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1778 #define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1779
kadonotakashi 0:8fdf9a60065b 1780 #define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1781 #define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1782
kadonotakashi 0:8fdf9a60065b 1783 #define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1784 #define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1785
kadonotakashi 0:8fdf9a60065b 1786 #define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1787 #define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1788
kadonotakashi 0:8fdf9a60065b 1789 #define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1790 #define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1791
kadonotakashi 0:8fdf9a60065b 1792 #define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1793 #define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1794
kadonotakashi 0:8fdf9a60065b 1795 #define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1796 #define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1797
kadonotakashi 0:8fdf9a60065b 1798 #define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */
kadonotakashi 0:8fdf9a60065b 1799 #define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */
kadonotakashi 0:8fdf9a60065b 1800
kadonotakashi 0:8fdf9a60065b 1801 #define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */
kadonotakashi 0:8fdf9a60065b 1802 #define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */
kadonotakashi 0:8fdf9a60065b 1803
kadonotakashi 0:8fdf9a60065b 1804 #define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */
kadonotakashi 0:8fdf9a60065b 1805 #define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */
kadonotakashi 0:8fdf9a60065b 1806
kadonotakashi 0:8fdf9a60065b 1807 #define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */
kadonotakashi 0:8fdf9a60065b 1808 #define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */
kadonotakashi 0:8fdf9a60065b 1809
kadonotakashi 0:8fdf9a60065b 1810 #define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */
kadonotakashi 0:8fdf9a60065b 1811 #define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */
kadonotakashi 0:8fdf9a60065b 1812
kadonotakashi 0:8fdf9a60065b 1813 #define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */
kadonotakashi 0:8fdf9a60065b 1814 #define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */
kadonotakashi 0:8fdf9a60065b 1815
kadonotakashi 0:8fdf9a60065b 1816 #define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */
kadonotakashi 0:8fdf9a60065b 1817 #define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */
kadonotakashi 0:8fdf9a60065b 1818
kadonotakashi 0:8fdf9a60065b 1819 #define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */
kadonotakashi 0:8fdf9a60065b 1820 #define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */
kadonotakashi 0:8fdf9a60065b 1821
kadonotakashi 0:8fdf9a60065b 1822 #define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */
kadonotakashi 0:8fdf9a60065b 1823 #define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */
kadonotakashi 0:8fdf9a60065b 1824
kadonotakashi 0:8fdf9a60065b 1825 #define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */
kadonotakashi 0:8fdf9a60065b 1826 #define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */
kadonotakashi 0:8fdf9a60065b 1827
kadonotakashi 0:8fdf9a60065b 1828 #define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */
kadonotakashi 0:8fdf9a60065b 1829 #define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */
kadonotakashi 0:8fdf9a60065b 1830
kadonotakashi 0:8fdf9a60065b 1831 #define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */
kadonotakashi 0:8fdf9a60065b 1832 #define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */
kadonotakashi 0:8fdf9a60065b 1833
kadonotakashi 0:8fdf9a60065b 1834 #define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */
kadonotakashi 0:8fdf9a60065b 1835 #define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */
kadonotakashi 0:8fdf9a60065b 1836
kadonotakashi 0:8fdf9a60065b 1837 #define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */
kadonotakashi 0:8fdf9a60065b 1838 #define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */
kadonotakashi 0:8fdf9a60065b 1839
kadonotakashi 0:8fdf9a60065b 1840 #define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */
kadonotakashi 0:8fdf9a60065b 1841 #define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */
kadonotakashi 0:8fdf9a60065b 1842
kadonotakashi 0:8fdf9a60065b 1843 #define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */
kadonotakashi 0:8fdf9a60065b 1844 #define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */
kadonotakashi 0:8fdf9a60065b 1845
kadonotakashi 0:8fdf9a60065b 1846 #define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */
kadonotakashi 0:8fdf9a60065b 1847 #define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */
kadonotakashi 0:8fdf9a60065b 1848
kadonotakashi 0:8fdf9a60065b 1849 #define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */
kadonotakashi 0:8fdf9a60065b 1850 #define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */
kadonotakashi 0:8fdf9a60065b 1851
kadonotakashi 0:8fdf9a60065b 1852 #define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */
kadonotakashi 0:8fdf9a60065b 1853 #define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */
kadonotakashi 0:8fdf9a60065b 1854
kadonotakashi 0:8fdf9a60065b 1855 #define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */
kadonotakashi 0:8fdf9a60065b 1856 #define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */
kadonotakashi 0:8fdf9a60065b 1857
kadonotakashi 0:8fdf9a60065b 1858 #define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */
kadonotakashi 0:8fdf9a60065b 1859 #define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */
kadonotakashi 0:8fdf9a60065b 1860
kadonotakashi 0:8fdf9a60065b 1861 #define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */
kadonotakashi 0:8fdf9a60065b 1862 #define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */
kadonotakashi 0:8fdf9a60065b 1863
kadonotakashi 0:8fdf9a60065b 1864 #define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */
kadonotakashi 0:8fdf9a60065b 1865 #define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */
kadonotakashi 0:8fdf9a60065b 1866
kadonotakashi 0:8fdf9a60065b 1867 #define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */
kadonotakashi 0:8fdf9a60065b 1868 #define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */
kadonotakashi 0:8fdf9a60065b 1869
kadonotakashi 0:8fdf9a60065b 1870 /**@}*/ /* BPWM_CONST */
kadonotakashi 0:8fdf9a60065b 1871 /**@}*/ /* end of BPWM register group */
kadonotakashi 0:8fdf9a60065b 1872
kadonotakashi 0:8fdf9a60065b 1873
kadonotakashi 0:8fdf9a60065b 1874 #endif /* __BPWM_REG_H__ */