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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /* mbed Microcontroller Library |
kadonotakashi | 0:8fdf9a60065b | 2 | * Copyright (c) 2015-2016 Nuvoton |
kadonotakashi | 0:8fdf9a60065b | 3 | * |
kadonotakashi | 0:8fdf9a60065b | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
kadonotakashi | 0:8fdf9a60065b | 5 | * you may not use this file except in compliance with the License. |
kadonotakashi | 0:8fdf9a60065b | 6 | * You may obtain a copy of the License at |
kadonotakashi | 0:8fdf9a60065b | 7 | * |
kadonotakashi | 0:8fdf9a60065b | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
kadonotakashi | 0:8fdf9a60065b | 9 | * |
kadonotakashi | 0:8fdf9a60065b | 10 | * Unless required by applicable law or agreed to in writing, software |
kadonotakashi | 0:8fdf9a60065b | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
kadonotakashi | 0:8fdf9a60065b | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
kadonotakashi | 0:8fdf9a60065b | 13 | * See the License for the specific language governing permissions and |
kadonotakashi | 0:8fdf9a60065b | 14 | * limitations under the License. |
kadonotakashi | 0:8fdf9a60065b | 15 | */ |
kadonotakashi | 0:8fdf9a60065b | 16 | |
kadonotakashi | 0:8fdf9a60065b | 17 | #include "gpio_irq_api.h" |
kadonotakashi | 0:8fdf9a60065b | 18 | |
kadonotakashi | 0:8fdf9a60065b | 19 | #if DEVICE_INTERRUPTIN |
kadonotakashi | 0:8fdf9a60065b | 20 | |
kadonotakashi | 0:8fdf9a60065b | 21 | #include "gpio_api.h" |
kadonotakashi | 0:8fdf9a60065b | 22 | #include "cmsis.h" |
kadonotakashi | 0:8fdf9a60065b | 23 | #include "pinmap.h" |
kadonotakashi | 0:8fdf9a60065b | 24 | #include "PeripheralPins.h" |
kadonotakashi | 0:8fdf9a60065b | 25 | #include "nu_bitutil.h" |
kadonotakashi | 0:8fdf9a60065b | 26 | |
kadonotakashi | 0:8fdf9a60065b | 27 | #define NU_MAX_PIN_PER_PORT 16 |
kadonotakashi | 0:8fdf9a60065b | 28 | |
kadonotakashi | 0:8fdf9a60065b | 29 | struct nu_gpio_irq_var { |
kadonotakashi | 0:8fdf9a60065b | 30 | gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT]; |
kadonotakashi | 0:8fdf9a60065b | 31 | IRQn_Type irq_n; |
kadonotakashi | 0:8fdf9a60065b | 32 | void (*vec)(void); |
kadonotakashi | 0:8fdf9a60065b | 33 | }; |
kadonotakashi | 0:8fdf9a60065b | 34 | |
kadonotakashi | 0:8fdf9a60065b | 35 | static void gpio_irq_0_vec(void); |
kadonotakashi | 0:8fdf9a60065b | 36 | static void gpio_irq_1_vec(void); |
kadonotakashi | 0:8fdf9a60065b | 37 | static void gpio_irq_2_vec(void); |
kadonotakashi | 0:8fdf9a60065b | 38 | static void gpio_irq_3_vec(void); |
kadonotakashi | 0:8fdf9a60065b | 39 | static void gpio_irq_4_vec(void); |
kadonotakashi | 0:8fdf9a60065b | 40 | static void gpio_irq_5_vec(void); |
kadonotakashi | 0:8fdf9a60065b | 41 | static void gpio_irq(struct nu_gpio_irq_var *var); |
kadonotakashi | 0:8fdf9a60065b | 42 | |
kadonotakashi | 0:8fdf9a60065b | 43 | //EINT0_IRQn |
kadonotakashi | 0:8fdf9a60065b | 44 | static struct nu_gpio_irq_var gpio_irq_var_arr[] = { |
kadonotakashi | 0:8fdf9a60065b | 45 | {{NULL}, GPA_IRQn, gpio_irq_0_vec}, |
kadonotakashi | 0:8fdf9a60065b | 46 | {{NULL}, GPB_IRQn, gpio_irq_1_vec}, |
kadonotakashi | 0:8fdf9a60065b | 47 | {{NULL}, GPC_IRQn, gpio_irq_2_vec}, |
kadonotakashi | 0:8fdf9a60065b | 48 | {{NULL}, GPD_IRQn, gpio_irq_3_vec}, |
kadonotakashi | 0:8fdf9a60065b | 49 | {{NULL}, GPE_IRQn, gpio_irq_4_vec}, |
kadonotakashi | 0:8fdf9a60065b | 50 | {{NULL}, GPF_IRQn, gpio_irq_5_vec} |
kadonotakashi | 0:8fdf9a60065b | 51 | }; |
kadonotakashi | 0:8fdf9a60065b | 52 | |
kadonotakashi | 0:8fdf9a60065b | 53 | #define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0])) |
kadonotakashi | 0:8fdf9a60065b | 54 | |
kadonotakashi | 0:8fdf9a60065b | 55 | #ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE |
kadonotakashi | 0:8fdf9a60065b | 56 | #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE 0 |
kadonotakashi | 0:8fdf9a60065b | 57 | #endif |
kadonotakashi | 0:8fdf9a60065b | 58 | |
kadonotakashi | 0:8fdf9a60065b | 59 | #ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST |
kadonotakashi | 0:8fdf9a60065b | 60 | #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC |
kadonotakashi | 0:8fdf9a60065b | 61 | #endif |
kadonotakashi | 0:8fdf9a60065b | 62 | static PinName gpio_irq_debounce_arr[] = { |
kadonotakashi | 0:8fdf9a60065b | 63 | MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST |
kadonotakashi | 0:8fdf9a60065b | 64 | }; |
kadonotakashi | 0:8fdf9a60065b | 65 | |
kadonotakashi | 0:8fdf9a60065b | 66 | #ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE |
kadonotakashi | 0:8fdf9a60065b | 67 | #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC |
kadonotakashi | 0:8fdf9a60065b | 68 | #endif |
kadonotakashi | 0:8fdf9a60065b | 69 | |
kadonotakashi | 0:8fdf9a60065b | 70 | #ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE |
kadonotakashi | 0:8fdf9a60065b | 71 | #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16 |
kadonotakashi | 0:8fdf9a60065b | 72 | #endif |
kadonotakashi | 0:8fdf9a60065b | 73 | |
kadonotakashi | 0:8fdf9a60065b | 74 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) |
kadonotakashi | 0:8fdf9a60065b | 75 | { |
kadonotakashi | 0:8fdf9a60065b | 76 | if (pin == NC) { |
kadonotakashi | 0:8fdf9a60065b | 77 | return -1; |
kadonotakashi | 0:8fdf9a60065b | 78 | } |
kadonotakashi | 0:8fdf9a60065b | 79 | |
kadonotakashi | 0:8fdf9a60065b | 80 | uint32_t pin_index = NU_PINNAME_TO_PIN(pin); |
kadonotakashi | 0:8fdf9a60065b | 81 | uint32_t port_index = NU_PINNAME_TO_PORT(pin); |
kadonotakashi | 0:8fdf9a60065b | 82 | if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) { |
kadonotakashi | 0:8fdf9a60065b | 83 | return -1; |
kadonotakashi | 0:8fdf9a60065b | 84 | } |
kadonotakashi | 0:8fdf9a60065b | 85 | |
kadonotakashi | 0:8fdf9a60065b | 86 | obj->pin = pin; |
kadonotakashi | 0:8fdf9a60065b | 87 | obj->irq_handler = (uint32_t) handler; |
kadonotakashi | 0:8fdf9a60065b | 88 | obj->irq_id = id; |
kadonotakashi | 0:8fdf9a60065b | 89 | |
kadonotakashi | 0:8fdf9a60065b | 90 | GPIO_T *gpio_base = NU_PORT_BASE(port_index); |
kadonotakashi | 0:8fdf9a60065b | 91 | // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting. |
kadonotakashi | 0:8fdf9a60065b | 92 | //gpio_set(pin); |
kadonotakashi | 0:8fdf9a60065b | 93 | |
kadonotakashi | 0:8fdf9a60065b | 94 | { |
kadonotakashi | 0:8fdf9a60065b | 95 | #if MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE |
kadonotakashi | 0:8fdf9a60065b | 96 | // Suppress compiler warning |
kadonotakashi | 0:8fdf9a60065b | 97 | (void) gpio_irq_debounce_arr; |
kadonotakashi | 0:8fdf9a60065b | 98 | |
kadonotakashi | 0:8fdf9a60065b | 99 | // Configure de-bounce clock source and sampling cycle time |
kadonotakashi | 0:8fdf9a60065b | 100 | GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); |
kadonotakashi | 0:8fdf9a60065b | 101 | GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index); |
kadonotakashi | 0:8fdf9a60065b | 102 | #else |
kadonotakashi | 0:8fdf9a60065b | 103 | // Enable de-bounce if the pin is in the de-bounce enable list |
kadonotakashi | 0:8fdf9a60065b | 104 | |
kadonotakashi | 0:8fdf9a60065b | 105 | // De-bounce defaults to disabled. |
kadonotakashi | 0:8fdf9a60065b | 106 | GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index); |
kadonotakashi | 0:8fdf9a60065b | 107 | |
kadonotakashi | 0:8fdf9a60065b | 108 | PinName *debounce_pos = gpio_irq_debounce_arr; |
kadonotakashi | 0:8fdf9a60065b | 109 | PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]); |
kadonotakashi | 0:8fdf9a60065b | 110 | for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) { |
kadonotakashi | 0:8fdf9a60065b | 111 | uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos); |
kadonotakashi | 0:8fdf9a60065b | 112 | uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos); |
kadonotakashi | 0:8fdf9a60065b | 113 | |
kadonotakashi | 0:8fdf9a60065b | 114 | if (pin_index == pin_index_debunce && |
kadonotakashi | 0:8fdf9a60065b | 115 | port_index == port_index_debounce) { |
kadonotakashi | 0:8fdf9a60065b | 116 | // Configure de-bounce clock source and sampling cycle time |
kadonotakashi | 0:8fdf9a60065b | 117 | GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); |
kadonotakashi | 0:8fdf9a60065b | 118 | GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index); |
kadonotakashi | 0:8fdf9a60065b | 119 | break; |
kadonotakashi | 0:8fdf9a60065b | 120 | } |
kadonotakashi | 0:8fdf9a60065b | 121 | } |
kadonotakashi | 0:8fdf9a60065b | 122 | #endif |
kadonotakashi | 0:8fdf9a60065b | 123 | } |
kadonotakashi | 0:8fdf9a60065b | 124 | |
kadonotakashi | 0:8fdf9a60065b | 125 | struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; |
kadonotakashi | 0:8fdf9a60065b | 126 | |
kadonotakashi | 0:8fdf9a60065b | 127 | var->obj_arr[pin_index] = obj; |
kadonotakashi | 0:8fdf9a60065b | 128 | |
kadonotakashi | 0:8fdf9a60065b | 129 | // NOTE: InterruptIn requires IRQ enabled by default. |
kadonotakashi | 0:8fdf9a60065b | 130 | gpio_irq_enable(obj); |
kadonotakashi | 0:8fdf9a60065b | 131 | |
kadonotakashi | 0:8fdf9a60065b | 132 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 133 | } |
kadonotakashi | 0:8fdf9a60065b | 134 | |
kadonotakashi | 0:8fdf9a60065b | 135 | void gpio_irq_free(gpio_irq_t *obj) |
kadonotakashi | 0:8fdf9a60065b | 136 | { |
kadonotakashi | 0:8fdf9a60065b | 137 | uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); |
kadonotakashi | 0:8fdf9a60065b | 138 | uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); |
kadonotakashi | 0:8fdf9a60065b | 139 | struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; |
kadonotakashi | 0:8fdf9a60065b | 140 | |
kadonotakashi | 0:8fdf9a60065b | 141 | NVIC_DisableIRQ(var->irq_n); |
kadonotakashi | 0:8fdf9a60065b | 142 | NU_PORT_BASE(port_index)->INTEN = 0; |
kadonotakashi | 0:8fdf9a60065b | 143 | |
kadonotakashi | 0:8fdf9a60065b | 144 | MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT); |
kadonotakashi | 0:8fdf9a60065b | 145 | var->obj_arr[pin_index] = NULL; |
kadonotakashi | 0:8fdf9a60065b | 146 | } |
kadonotakashi | 0:8fdf9a60065b | 147 | |
kadonotakashi | 0:8fdf9a60065b | 148 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) |
kadonotakashi | 0:8fdf9a60065b | 149 | { |
kadonotakashi | 0:8fdf9a60065b | 150 | uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); |
kadonotakashi | 0:8fdf9a60065b | 151 | uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); |
kadonotakashi | 0:8fdf9a60065b | 152 | GPIO_T *gpio_base = NU_PORT_BASE(port_index); |
kadonotakashi | 0:8fdf9a60065b | 153 | |
kadonotakashi | 0:8fdf9a60065b | 154 | switch (event) { |
kadonotakashi | 0:8fdf9a60065b | 155 | case IRQ_RISE: |
kadonotakashi | 0:8fdf9a60065b | 156 | if (enable) { |
kadonotakashi | 0:8fdf9a60065b | 157 | GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING); |
kadonotakashi | 0:8fdf9a60065b | 158 | } |
kadonotakashi | 0:8fdf9a60065b | 159 | else { |
kadonotakashi | 0:8fdf9a60065b | 160 | gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index); |
kadonotakashi | 0:8fdf9a60065b | 161 | } |
kadonotakashi | 0:8fdf9a60065b | 162 | break; |
kadonotakashi | 0:8fdf9a60065b | 163 | |
kadonotakashi | 0:8fdf9a60065b | 164 | case IRQ_FALL: |
kadonotakashi | 0:8fdf9a60065b | 165 | if (enable) { |
kadonotakashi | 0:8fdf9a60065b | 166 | GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING); |
kadonotakashi | 0:8fdf9a60065b | 167 | } |
kadonotakashi | 0:8fdf9a60065b | 168 | else { |
kadonotakashi | 0:8fdf9a60065b | 169 | gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index); |
kadonotakashi | 0:8fdf9a60065b | 170 | } |
kadonotakashi | 0:8fdf9a60065b | 171 | break; |
kadonotakashi | 0:8fdf9a60065b | 172 | } |
kadonotakashi | 0:8fdf9a60065b | 173 | } |
kadonotakashi | 0:8fdf9a60065b | 174 | |
kadonotakashi | 0:8fdf9a60065b | 175 | void gpio_irq_enable(gpio_irq_t *obj) |
kadonotakashi | 0:8fdf9a60065b | 176 | { |
kadonotakashi | 0:8fdf9a60065b | 177 | //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); |
kadonotakashi | 0:8fdf9a60065b | 178 | uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); |
kadonotakashi | 0:8fdf9a60065b | 179 | struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; |
kadonotakashi | 0:8fdf9a60065b | 180 | |
kadonotakashi | 0:8fdf9a60065b | 181 | NVIC_SetVector(var->irq_n, (uint32_t) var->vec); |
kadonotakashi | 0:8fdf9a60065b | 182 | NVIC_EnableIRQ(var->irq_n); |
kadonotakashi | 0:8fdf9a60065b | 183 | } |
kadonotakashi | 0:8fdf9a60065b | 184 | |
kadonotakashi | 0:8fdf9a60065b | 185 | void gpio_irq_disable(gpio_irq_t *obj) |
kadonotakashi | 0:8fdf9a60065b | 186 | { |
kadonotakashi | 0:8fdf9a60065b | 187 | //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); |
kadonotakashi | 0:8fdf9a60065b | 188 | uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); |
kadonotakashi | 0:8fdf9a60065b | 189 | struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; |
kadonotakashi | 0:8fdf9a60065b | 190 | |
kadonotakashi | 0:8fdf9a60065b | 191 | NVIC_DisableIRQ(var->irq_n); |
kadonotakashi | 0:8fdf9a60065b | 192 | } |
kadonotakashi | 0:8fdf9a60065b | 193 | |
kadonotakashi | 0:8fdf9a60065b | 194 | static void gpio_irq_0_vec(void) |
kadonotakashi | 0:8fdf9a60065b | 195 | { |
kadonotakashi | 0:8fdf9a60065b | 196 | gpio_irq(gpio_irq_var_arr + 0); |
kadonotakashi | 0:8fdf9a60065b | 197 | } |
kadonotakashi | 0:8fdf9a60065b | 198 | static void gpio_irq_1_vec(void) |
kadonotakashi | 0:8fdf9a60065b | 199 | { |
kadonotakashi | 0:8fdf9a60065b | 200 | gpio_irq(gpio_irq_var_arr + 1); |
kadonotakashi | 0:8fdf9a60065b | 201 | } |
kadonotakashi | 0:8fdf9a60065b | 202 | static void gpio_irq_2_vec(void) |
kadonotakashi | 0:8fdf9a60065b | 203 | { |
kadonotakashi | 0:8fdf9a60065b | 204 | gpio_irq(gpio_irq_var_arr + 2); |
kadonotakashi | 0:8fdf9a60065b | 205 | } |
kadonotakashi | 0:8fdf9a60065b | 206 | static void gpio_irq_3_vec(void) |
kadonotakashi | 0:8fdf9a60065b | 207 | { |
kadonotakashi | 0:8fdf9a60065b | 208 | gpio_irq(gpio_irq_var_arr + 3); |
kadonotakashi | 0:8fdf9a60065b | 209 | } |
kadonotakashi | 0:8fdf9a60065b | 210 | static void gpio_irq_4_vec(void) |
kadonotakashi | 0:8fdf9a60065b | 211 | { |
kadonotakashi | 0:8fdf9a60065b | 212 | gpio_irq(gpio_irq_var_arr + 4); |
kadonotakashi | 0:8fdf9a60065b | 213 | } |
kadonotakashi | 0:8fdf9a60065b | 214 | static void gpio_irq_5_vec(void) |
kadonotakashi | 0:8fdf9a60065b | 215 | { |
kadonotakashi | 0:8fdf9a60065b | 216 | gpio_irq(gpio_irq_var_arr + 5); |
kadonotakashi | 0:8fdf9a60065b | 217 | } |
kadonotakashi | 0:8fdf9a60065b | 218 | |
kadonotakashi | 0:8fdf9a60065b | 219 | static void gpio_irq(struct nu_gpio_irq_var *var) |
kadonotakashi | 0:8fdf9a60065b | 220 | { |
kadonotakashi | 0:8fdf9a60065b | 221 | uint32_t port_index = var->irq_n - GPA_IRQn; |
kadonotakashi | 0:8fdf9a60065b | 222 | GPIO_T *gpio_base = NU_PORT_BASE(port_index); |
kadonotakashi | 0:8fdf9a60065b | 223 | |
kadonotakashi | 0:8fdf9a60065b | 224 | uint32_t intsrc = gpio_base->INTSRC; |
kadonotakashi | 0:8fdf9a60065b | 225 | uint32_t inten = gpio_base->INTEN; |
kadonotakashi | 0:8fdf9a60065b | 226 | while (intsrc) { |
kadonotakashi | 0:8fdf9a60065b | 227 | int pin_index = nu_ctz(intsrc); |
kadonotakashi | 0:8fdf9a60065b | 228 | gpio_irq_t *obj = var->obj_arr[pin_index]; |
kadonotakashi | 0:8fdf9a60065b | 229 | if (inten & (GPIO_INT_RISING << pin_index)) { |
kadonotakashi | 0:8fdf9a60065b | 230 | if (GPIO_PIN_DATA(port_index, pin_index)) { |
kadonotakashi | 0:8fdf9a60065b | 231 | if (obj->irq_handler) { |
kadonotakashi | 0:8fdf9a60065b | 232 | ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE); |
kadonotakashi | 0:8fdf9a60065b | 233 | } |
kadonotakashi | 0:8fdf9a60065b | 234 | } |
kadonotakashi | 0:8fdf9a60065b | 235 | } |
kadonotakashi | 0:8fdf9a60065b | 236 | |
kadonotakashi | 0:8fdf9a60065b | 237 | if (inten & (GPIO_INT_FALLING << pin_index)) { |
kadonotakashi | 0:8fdf9a60065b | 238 | if (! GPIO_PIN_DATA(port_index, pin_index)) { |
kadonotakashi | 0:8fdf9a60065b | 239 | if (obj->irq_handler) { |
kadonotakashi | 0:8fdf9a60065b | 240 | ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL); |
kadonotakashi | 0:8fdf9a60065b | 241 | } |
kadonotakashi | 0:8fdf9a60065b | 242 | } |
kadonotakashi | 0:8fdf9a60065b | 243 | } |
kadonotakashi | 0:8fdf9a60065b | 244 | |
kadonotakashi | 0:8fdf9a60065b | 245 | intsrc &= ~(1 << pin_index); |
kadonotakashi | 0:8fdf9a60065b | 246 | } |
kadonotakashi | 0:8fdf9a60065b | 247 | // Clear all interrupt flags |
kadonotakashi | 0:8fdf9a60065b | 248 | gpio_base->INTSRC = gpio_base->INTSRC; |
kadonotakashi | 0:8fdf9a60065b | 249 | } |
kadonotakashi | 0:8fdf9a60065b | 250 | |
kadonotakashi | 0:8fdf9a60065b | 251 | #endif |