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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_smc.c@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /* |
kadonotakashi | 0:8fdf9a60065b | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
kadonotakashi | 0:8fdf9a60065b | 3 | * All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 4 | * |
kadonotakashi | 0:8fdf9a60065b | 5 | * Redistribution and use in source and binary forms, with or without modification, |
kadonotakashi | 0:8fdf9a60065b | 6 | * are permitted provided that the following conditions are met: |
kadonotakashi | 0:8fdf9a60065b | 7 | * |
kadonotakashi | 0:8fdf9a60065b | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
kadonotakashi | 0:8fdf9a60065b | 9 | * of conditions and the following disclaimer. |
kadonotakashi | 0:8fdf9a60065b | 10 | * |
kadonotakashi | 0:8fdf9a60065b | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
kadonotakashi | 0:8fdf9a60065b | 12 | * list of conditions and the following disclaimer in the documentation and/or |
kadonotakashi | 0:8fdf9a60065b | 13 | * other materials provided with the distribution. |
kadonotakashi | 0:8fdf9a60065b | 14 | * |
kadonotakashi | 0:8fdf9a60065b | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
kadonotakashi | 0:8fdf9a60065b | 16 | * contributors may be used to endorse or promote products derived from this |
kadonotakashi | 0:8fdf9a60065b | 17 | * software without specific prior written permission. |
kadonotakashi | 0:8fdf9a60065b | 18 | * |
kadonotakashi | 0:8fdf9a60065b | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
kadonotakashi | 0:8fdf9a60065b | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
kadonotakashi | 0:8fdf9a60065b | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
kadonotakashi | 0:8fdf9a60065b | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
kadonotakashi | 0:8fdf9a60065b | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
kadonotakashi | 0:8fdf9a60065b | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
kadonotakashi | 0:8fdf9a60065b | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
kadonotakashi | 0:8fdf9a60065b | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
kadonotakashi | 0:8fdf9a60065b | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
kadonotakashi | 0:8fdf9a60065b | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
kadonotakashi | 0:8fdf9a60065b | 29 | */ |
kadonotakashi | 0:8fdf9a60065b | 30 | |
kadonotakashi | 0:8fdf9a60065b | 31 | #include "fsl_smc.h" |
kadonotakashi | 0:8fdf9a60065b | 32 | |
kadonotakashi | 0:8fdf9a60065b | 33 | #if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) |
kadonotakashi | 0:8fdf9a60065b | 34 | void SMC_GetParam(SMC_Type *base, smc_param_t *param) |
kadonotakashi | 0:8fdf9a60065b | 35 | { |
kadonotakashi | 0:8fdf9a60065b | 36 | uint32_t reg = base->PARAM; |
kadonotakashi | 0:8fdf9a60065b | 37 | param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK); |
kadonotakashi | 0:8fdf9a60065b | 38 | param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK); |
kadonotakashi | 0:8fdf9a60065b | 39 | param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK); |
kadonotakashi | 0:8fdf9a60065b | 40 | param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK); |
kadonotakashi | 0:8fdf9a60065b | 41 | } |
kadonotakashi | 0:8fdf9a60065b | 42 | #endif /* FSL_FEATURE_SMC_HAS_PARAM */ |
kadonotakashi | 0:8fdf9a60065b | 43 | |
kadonotakashi | 0:8fdf9a60065b | 44 | status_t SMC_SetPowerModeRun(SMC_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 45 | { |
kadonotakashi | 0:8fdf9a60065b | 46 | uint8_t reg; |
kadonotakashi | 0:8fdf9a60065b | 47 | |
kadonotakashi | 0:8fdf9a60065b | 48 | reg = base->PMCTRL; |
kadonotakashi | 0:8fdf9a60065b | 49 | /* configure Normal RUN mode */ |
kadonotakashi | 0:8fdf9a60065b | 50 | reg &= ~SMC_PMCTRL_RUNM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 51 | reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 52 | base->PMCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 53 | |
kadonotakashi | 0:8fdf9a60065b | 54 | return kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 55 | } |
kadonotakashi | 0:8fdf9a60065b | 56 | |
kadonotakashi | 0:8fdf9a60065b | 57 | #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) |
kadonotakashi | 0:8fdf9a60065b | 58 | status_t SMC_SetPowerModeHsrun(SMC_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 59 | { |
kadonotakashi | 0:8fdf9a60065b | 60 | uint8_t reg; |
kadonotakashi | 0:8fdf9a60065b | 61 | |
kadonotakashi | 0:8fdf9a60065b | 62 | reg = base->PMCTRL; |
kadonotakashi | 0:8fdf9a60065b | 63 | /* configure High Speed RUN mode */ |
kadonotakashi | 0:8fdf9a60065b | 64 | reg &= ~SMC_PMCTRL_RUNM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 65 | reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 66 | base->PMCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 67 | |
kadonotakashi | 0:8fdf9a60065b | 68 | return kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 69 | } |
kadonotakashi | 0:8fdf9a60065b | 70 | #endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ |
kadonotakashi | 0:8fdf9a60065b | 71 | |
kadonotakashi | 0:8fdf9a60065b | 72 | status_t SMC_SetPowerModeWait(SMC_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 73 | { |
kadonotakashi | 0:8fdf9a60065b | 74 | /* configure Normal Wait mode */ |
kadonotakashi | 0:8fdf9a60065b | 75 | SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; |
kadonotakashi | 0:8fdf9a60065b | 76 | __WFI(); |
kadonotakashi | 0:8fdf9a60065b | 77 | |
kadonotakashi | 0:8fdf9a60065b | 78 | return kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 79 | } |
kadonotakashi | 0:8fdf9a60065b | 80 | |
kadonotakashi | 0:8fdf9a60065b | 81 | status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) |
kadonotakashi | 0:8fdf9a60065b | 82 | { |
kadonotakashi | 0:8fdf9a60065b | 83 | uint8_t reg; |
kadonotakashi | 0:8fdf9a60065b | 84 | |
kadonotakashi | 0:8fdf9a60065b | 85 | #if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO) |
kadonotakashi | 0:8fdf9a60065b | 86 | /* configure the Partial Stop mode in Noraml Stop mode */ |
kadonotakashi | 0:8fdf9a60065b | 87 | reg = base->STOPCTRL; |
kadonotakashi | 0:8fdf9a60065b | 88 | reg &= ~SMC_STOPCTRL_PSTOPO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 89 | reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 90 | base->STOPCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 91 | #endif |
kadonotakashi | 0:8fdf9a60065b | 92 | |
kadonotakashi | 0:8fdf9a60065b | 93 | /* configure Normal Stop mode */ |
kadonotakashi | 0:8fdf9a60065b | 94 | reg = base->PMCTRL; |
kadonotakashi | 0:8fdf9a60065b | 95 | reg &= ~SMC_PMCTRL_STOPM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 96 | reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 97 | base->PMCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 98 | |
kadonotakashi | 0:8fdf9a60065b | 99 | /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */ |
kadonotakashi | 0:8fdf9a60065b | 100 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
kadonotakashi | 0:8fdf9a60065b | 101 | |
kadonotakashi | 0:8fdf9a60065b | 102 | /* read back to make sure the configuration valid before enter stop mode */ |
kadonotakashi | 0:8fdf9a60065b | 103 | (void)base->PMCTRL; |
kadonotakashi | 0:8fdf9a60065b | 104 | __WFI(); |
kadonotakashi | 0:8fdf9a60065b | 105 | |
kadonotakashi | 0:8fdf9a60065b | 106 | /* check whether the power mode enter Stop mode succeed */ |
kadonotakashi | 0:8fdf9a60065b | 107 | if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) |
kadonotakashi | 0:8fdf9a60065b | 108 | { |
kadonotakashi | 0:8fdf9a60065b | 109 | return kStatus_SMC_StopAbort; |
kadonotakashi | 0:8fdf9a60065b | 110 | } |
kadonotakashi | 0:8fdf9a60065b | 111 | else |
kadonotakashi | 0:8fdf9a60065b | 112 | { |
kadonotakashi | 0:8fdf9a60065b | 113 | return kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 114 | } |
kadonotakashi | 0:8fdf9a60065b | 115 | } |
kadonotakashi | 0:8fdf9a60065b | 116 | |
kadonotakashi | 0:8fdf9a60065b | 117 | status_t SMC_SetPowerModeVlpr(SMC_Type *base |
kadonotakashi | 0:8fdf9a60065b | 118 | #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) |
kadonotakashi | 0:8fdf9a60065b | 119 | , |
kadonotakashi | 0:8fdf9a60065b | 120 | bool wakeupMode |
kadonotakashi | 0:8fdf9a60065b | 121 | #endif |
kadonotakashi | 0:8fdf9a60065b | 122 | ) |
kadonotakashi | 0:8fdf9a60065b | 123 | { |
kadonotakashi | 0:8fdf9a60065b | 124 | uint8_t reg; |
kadonotakashi | 0:8fdf9a60065b | 125 | |
kadonotakashi | 0:8fdf9a60065b | 126 | reg = base->PMCTRL; |
kadonotakashi | 0:8fdf9a60065b | 127 | #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) |
kadonotakashi | 0:8fdf9a60065b | 128 | /* configure whether the system remains in VLP mode on an interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 129 | if (wakeupMode) |
kadonotakashi | 0:8fdf9a60065b | 130 | { |
kadonotakashi | 0:8fdf9a60065b | 131 | /* exits to RUN mode on an interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 132 | reg |= SMC_PMCTRL_LPWUI_MASK; |
kadonotakashi | 0:8fdf9a60065b | 133 | } |
kadonotakashi | 0:8fdf9a60065b | 134 | else |
kadonotakashi | 0:8fdf9a60065b | 135 | { |
kadonotakashi | 0:8fdf9a60065b | 136 | /* remains in VLP mode on an interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 137 | reg &= ~SMC_PMCTRL_LPWUI_MASK; |
kadonotakashi | 0:8fdf9a60065b | 138 | } |
kadonotakashi | 0:8fdf9a60065b | 139 | #endif /* FSL_FEATURE_SMC_HAS_LPWUI */ |
kadonotakashi | 0:8fdf9a60065b | 140 | |
kadonotakashi | 0:8fdf9a60065b | 141 | /* configure VLPR mode */ |
kadonotakashi | 0:8fdf9a60065b | 142 | reg &= ~SMC_PMCTRL_RUNM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 143 | reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 144 | base->PMCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 145 | |
kadonotakashi | 0:8fdf9a60065b | 146 | return kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 147 | } |
kadonotakashi | 0:8fdf9a60065b | 148 | |
kadonotakashi | 0:8fdf9a60065b | 149 | status_t SMC_SetPowerModeVlpw(SMC_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 150 | { |
kadonotakashi | 0:8fdf9a60065b | 151 | /* Power mode transaction to VLPW can only happen in VLPR mode */ |
kadonotakashi | 0:8fdf9a60065b | 152 | if (kSMC_PowerStateVlpr != SMC_GetPowerModeState(base)) |
kadonotakashi | 0:8fdf9a60065b | 153 | { |
kadonotakashi | 0:8fdf9a60065b | 154 | return kStatus_Fail; |
kadonotakashi | 0:8fdf9a60065b | 155 | } |
kadonotakashi | 0:8fdf9a60065b | 156 | |
kadonotakashi | 0:8fdf9a60065b | 157 | /* configure VLPW mode */ |
kadonotakashi | 0:8fdf9a60065b | 158 | /* Set the SLEEPDEEP bit to enable deep sleep mode */ |
kadonotakashi | 0:8fdf9a60065b | 159 | SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; |
kadonotakashi | 0:8fdf9a60065b | 160 | __WFI(); |
kadonotakashi | 0:8fdf9a60065b | 161 | |
kadonotakashi | 0:8fdf9a60065b | 162 | return kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 163 | } |
kadonotakashi | 0:8fdf9a60065b | 164 | |
kadonotakashi | 0:8fdf9a60065b | 165 | status_t SMC_SetPowerModeVlps(SMC_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 166 | { |
kadonotakashi | 0:8fdf9a60065b | 167 | uint8_t reg; |
kadonotakashi | 0:8fdf9a60065b | 168 | |
kadonotakashi | 0:8fdf9a60065b | 169 | /* configure VLPS mode */ |
kadonotakashi | 0:8fdf9a60065b | 170 | reg = base->PMCTRL; |
kadonotakashi | 0:8fdf9a60065b | 171 | reg &= ~SMC_PMCTRL_STOPM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 172 | reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 173 | base->PMCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 174 | |
kadonotakashi | 0:8fdf9a60065b | 175 | /* Set the SLEEPDEEP bit to enable deep sleep mode */ |
kadonotakashi | 0:8fdf9a60065b | 176 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
kadonotakashi | 0:8fdf9a60065b | 177 | |
kadonotakashi | 0:8fdf9a60065b | 178 | /* read back to make sure the configuration valid before enter stop mode */ |
kadonotakashi | 0:8fdf9a60065b | 179 | (void)base->PMCTRL; |
kadonotakashi | 0:8fdf9a60065b | 180 | __WFI(); |
kadonotakashi | 0:8fdf9a60065b | 181 | |
kadonotakashi | 0:8fdf9a60065b | 182 | /* check whether the power mode enter VLPS mode succeed */ |
kadonotakashi | 0:8fdf9a60065b | 183 | if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) |
kadonotakashi | 0:8fdf9a60065b | 184 | { |
kadonotakashi | 0:8fdf9a60065b | 185 | return kStatus_SMC_StopAbort; |
kadonotakashi | 0:8fdf9a60065b | 186 | } |
kadonotakashi | 0:8fdf9a60065b | 187 | else |
kadonotakashi | 0:8fdf9a60065b | 188 | { |
kadonotakashi | 0:8fdf9a60065b | 189 | return kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 190 | } |
kadonotakashi | 0:8fdf9a60065b | 191 | } |
kadonotakashi | 0:8fdf9a60065b | 192 | |
kadonotakashi | 0:8fdf9a60065b | 193 | #if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) |
kadonotakashi | 0:8fdf9a60065b | 194 | status_t SMC_SetPowerModeLls(SMC_Type *base |
kadonotakashi | 0:8fdf9a60065b | 195 | #if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ |
kadonotakashi | 0:8fdf9a60065b | 196 | (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) |
kadonotakashi | 0:8fdf9a60065b | 197 | , |
kadonotakashi | 0:8fdf9a60065b | 198 | const smc_power_mode_lls_config_t *config |
kadonotakashi | 0:8fdf9a60065b | 199 | #endif |
kadonotakashi | 0:8fdf9a60065b | 200 | ) |
kadonotakashi | 0:8fdf9a60065b | 201 | { |
kadonotakashi | 0:8fdf9a60065b | 202 | uint8_t reg; |
kadonotakashi | 0:8fdf9a60065b | 203 | |
kadonotakashi | 0:8fdf9a60065b | 204 | /* configure to LLS mode */ |
kadonotakashi | 0:8fdf9a60065b | 205 | reg = base->PMCTRL; |
kadonotakashi | 0:8fdf9a60065b | 206 | reg &= ~SMC_PMCTRL_STOPM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 207 | reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 208 | base->PMCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 209 | |
kadonotakashi | 0:8fdf9a60065b | 210 | /* configure LLS sub-mode*/ |
kadonotakashi | 0:8fdf9a60065b | 211 | #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) |
kadonotakashi | 0:8fdf9a60065b | 212 | reg = base->STOPCTRL; |
kadonotakashi | 0:8fdf9a60065b | 213 | reg &= ~SMC_STOPCTRL_LLSM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 214 | reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 215 | base->STOPCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 216 | #endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ |
kadonotakashi | 0:8fdf9a60065b | 217 | |
kadonotakashi | 0:8fdf9a60065b | 218 | #if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) |
kadonotakashi | 0:8fdf9a60065b | 219 | if (config->enableLpoClock) |
kadonotakashi | 0:8fdf9a60065b | 220 | { |
kadonotakashi | 0:8fdf9a60065b | 221 | base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 222 | } |
kadonotakashi | 0:8fdf9a60065b | 223 | else |
kadonotakashi | 0:8fdf9a60065b | 224 | { |
kadonotakashi | 0:8fdf9a60065b | 225 | base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 226 | } |
kadonotakashi | 0:8fdf9a60065b | 227 | #endif /* FSL_FEATURE_SMC_HAS_LPOPO */ |
kadonotakashi | 0:8fdf9a60065b | 228 | |
kadonotakashi | 0:8fdf9a60065b | 229 | /* Set the SLEEPDEEP bit to enable deep sleep mode */ |
kadonotakashi | 0:8fdf9a60065b | 230 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
kadonotakashi | 0:8fdf9a60065b | 231 | |
kadonotakashi | 0:8fdf9a60065b | 232 | /* read back to make sure the configuration valid before enter stop mode */ |
kadonotakashi | 0:8fdf9a60065b | 233 | (void)base->PMCTRL; |
kadonotakashi | 0:8fdf9a60065b | 234 | __WFI(); |
kadonotakashi | 0:8fdf9a60065b | 235 | |
kadonotakashi | 0:8fdf9a60065b | 236 | /* check whether the power mode enter LLS mode succeed */ |
kadonotakashi | 0:8fdf9a60065b | 237 | if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) |
kadonotakashi | 0:8fdf9a60065b | 238 | { |
kadonotakashi | 0:8fdf9a60065b | 239 | return kStatus_SMC_StopAbort; |
kadonotakashi | 0:8fdf9a60065b | 240 | } |
kadonotakashi | 0:8fdf9a60065b | 241 | else |
kadonotakashi | 0:8fdf9a60065b | 242 | { |
kadonotakashi | 0:8fdf9a60065b | 243 | return kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 244 | } |
kadonotakashi | 0:8fdf9a60065b | 245 | } |
kadonotakashi | 0:8fdf9a60065b | 246 | #endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ |
kadonotakashi | 0:8fdf9a60065b | 247 | |
kadonotakashi | 0:8fdf9a60065b | 248 | #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) |
kadonotakashi | 0:8fdf9a60065b | 249 | status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config) |
kadonotakashi | 0:8fdf9a60065b | 250 | { |
kadonotakashi | 0:8fdf9a60065b | 251 | uint8_t reg; |
kadonotakashi | 0:8fdf9a60065b | 252 | |
kadonotakashi | 0:8fdf9a60065b | 253 | #if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) |
kadonotakashi | 0:8fdf9a60065b | 254 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ |
kadonotakashi | 0:8fdf9a60065b | 255 | (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ |
kadonotakashi | 0:8fdf9a60065b | 256 | (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) |
kadonotakashi | 0:8fdf9a60065b | 257 | if (config->subMode == kSMC_StopSub0) |
kadonotakashi | 0:8fdf9a60065b | 258 | #endif |
kadonotakashi | 0:8fdf9a60065b | 259 | { |
kadonotakashi | 0:8fdf9a60065b | 260 | /* configure whether the Por Detect work in Vlls0 mode */ |
kadonotakashi | 0:8fdf9a60065b | 261 | if (config->enablePorDetectInVlls0) |
kadonotakashi | 0:8fdf9a60065b | 262 | { |
kadonotakashi | 0:8fdf9a60065b | 263 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) |
kadonotakashi | 0:8fdf9a60065b | 264 | base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 265 | #else |
kadonotakashi | 0:8fdf9a60065b | 266 | base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 267 | #endif |
kadonotakashi | 0:8fdf9a60065b | 268 | } |
kadonotakashi | 0:8fdf9a60065b | 269 | else |
kadonotakashi | 0:8fdf9a60065b | 270 | { |
kadonotakashi | 0:8fdf9a60065b | 271 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) |
kadonotakashi | 0:8fdf9a60065b | 272 | base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 273 | #else |
kadonotakashi | 0:8fdf9a60065b | 274 | base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 275 | #endif |
kadonotakashi | 0:8fdf9a60065b | 276 | } |
kadonotakashi | 0:8fdf9a60065b | 277 | } |
kadonotakashi | 0:8fdf9a60065b | 278 | #endif /* FSL_FEATURE_SMC_HAS_PORPO */ |
kadonotakashi | 0:8fdf9a60065b | 279 | |
kadonotakashi | 0:8fdf9a60065b | 280 | #if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) |
kadonotakashi | 0:8fdf9a60065b | 281 | else if (config->subMode == kSMC_StopSub2) |
kadonotakashi | 0:8fdf9a60065b | 282 | { |
kadonotakashi | 0:8fdf9a60065b | 283 | /* configure whether the Por Detect work in Vlls0 mode */ |
kadonotakashi | 0:8fdf9a60065b | 284 | if (config->enableRam2InVlls2) |
kadonotakashi | 0:8fdf9a60065b | 285 | { |
kadonotakashi | 0:8fdf9a60065b | 286 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) |
kadonotakashi | 0:8fdf9a60065b | 287 | base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 288 | #else |
kadonotakashi | 0:8fdf9a60065b | 289 | base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 290 | #endif |
kadonotakashi | 0:8fdf9a60065b | 291 | } |
kadonotakashi | 0:8fdf9a60065b | 292 | else |
kadonotakashi | 0:8fdf9a60065b | 293 | { |
kadonotakashi | 0:8fdf9a60065b | 294 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) |
kadonotakashi | 0:8fdf9a60065b | 295 | base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 296 | #else |
kadonotakashi | 0:8fdf9a60065b | 297 | base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 298 | #endif |
kadonotakashi | 0:8fdf9a60065b | 299 | } |
kadonotakashi | 0:8fdf9a60065b | 300 | } |
kadonotakashi | 0:8fdf9a60065b | 301 | else |
kadonotakashi | 0:8fdf9a60065b | 302 | { |
kadonotakashi | 0:8fdf9a60065b | 303 | } |
kadonotakashi | 0:8fdf9a60065b | 304 | #endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */ |
kadonotakashi | 0:8fdf9a60065b | 305 | |
kadonotakashi | 0:8fdf9a60065b | 306 | /* configure to VLLS mode */ |
kadonotakashi | 0:8fdf9a60065b | 307 | reg = base->PMCTRL; |
kadonotakashi | 0:8fdf9a60065b | 308 | reg &= ~SMC_PMCTRL_STOPM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 309 | reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 310 | base->PMCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 311 | |
kadonotakashi | 0:8fdf9a60065b | 312 | /* configure the VLLS sub-mode */ |
kadonotakashi | 0:8fdf9a60065b | 313 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) |
kadonotakashi | 0:8fdf9a60065b | 314 | reg = base->VLLSCTRL; |
kadonotakashi | 0:8fdf9a60065b | 315 | reg &= ~SMC_VLLSCTRL_VLLSM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 316 | reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 317 | base->VLLSCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 318 | #else |
kadonotakashi | 0:8fdf9a60065b | 319 | #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) |
kadonotakashi | 0:8fdf9a60065b | 320 | reg = base->STOPCTRL; |
kadonotakashi | 0:8fdf9a60065b | 321 | reg &= ~SMC_STOPCTRL_LLSM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 322 | reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 323 | base->STOPCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 324 | #else |
kadonotakashi | 0:8fdf9a60065b | 325 | reg = base->STOPCTRL; |
kadonotakashi | 0:8fdf9a60065b | 326 | reg &= ~SMC_STOPCTRL_VLLSM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 327 | reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT); |
kadonotakashi | 0:8fdf9a60065b | 328 | base->STOPCTRL = reg; |
kadonotakashi | 0:8fdf9a60065b | 329 | #endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ |
kadonotakashi | 0:8fdf9a60065b | 330 | #endif |
kadonotakashi | 0:8fdf9a60065b | 331 | |
kadonotakashi | 0:8fdf9a60065b | 332 | #if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) |
kadonotakashi | 0:8fdf9a60065b | 333 | if (config->enableLpoClock) |
kadonotakashi | 0:8fdf9a60065b | 334 | { |
kadonotakashi | 0:8fdf9a60065b | 335 | base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 336 | } |
kadonotakashi | 0:8fdf9a60065b | 337 | else |
kadonotakashi | 0:8fdf9a60065b | 338 | { |
kadonotakashi | 0:8fdf9a60065b | 339 | base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; |
kadonotakashi | 0:8fdf9a60065b | 340 | } |
kadonotakashi | 0:8fdf9a60065b | 341 | #endif /* FSL_FEATURE_SMC_HAS_LPOPO */ |
kadonotakashi | 0:8fdf9a60065b | 342 | |
kadonotakashi | 0:8fdf9a60065b | 343 | /* Set the SLEEPDEEP bit to enable deep sleep mode */ |
kadonotakashi | 0:8fdf9a60065b | 344 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
kadonotakashi | 0:8fdf9a60065b | 345 | |
kadonotakashi | 0:8fdf9a60065b | 346 | /* read back to make sure the configuration valid before enter stop mode */ |
kadonotakashi | 0:8fdf9a60065b | 347 | (void)base->PMCTRL; |
kadonotakashi | 0:8fdf9a60065b | 348 | __WFI(); |
kadonotakashi | 0:8fdf9a60065b | 349 | |
kadonotakashi | 0:8fdf9a60065b | 350 | /* check whether the power mode enter LLS mode succeed */ |
kadonotakashi | 0:8fdf9a60065b | 351 | if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) |
kadonotakashi | 0:8fdf9a60065b | 352 | { |
kadonotakashi | 0:8fdf9a60065b | 353 | return kStatus_SMC_StopAbort; |
kadonotakashi | 0:8fdf9a60065b | 354 | } |
kadonotakashi | 0:8fdf9a60065b | 355 | else |
kadonotakashi | 0:8fdf9a60065b | 356 | { |
kadonotakashi | 0:8fdf9a60065b | 357 | return kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 358 | } |
kadonotakashi | 0:8fdf9a60065b | 359 | } |
kadonotakashi | 0:8fdf9a60065b | 360 | #endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ |