![](/media/cache/img/default_profile.jpg.50x50_q85.jpg)
Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/pmc.c@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /** |
kadonotakashi | 0:8fdf9a60065b | 2 | * \file |
kadonotakashi | 0:8fdf9a60065b | 3 | * |
kadonotakashi | 0:8fdf9a60065b | 4 | * \brief Power Management Controller (PMC) driver for SAM. |
kadonotakashi | 0:8fdf9a60065b | 5 | * |
kadonotakashi | 0:8fdf9a60065b | 6 | * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 7 | * |
kadonotakashi | 0:8fdf9a60065b | 8 | * \asf_license_start |
kadonotakashi | 0:8fdf9a60065b | 9 | * |
kadonotakashi | 0:8fdf9a60065b | 10 | * \page License |
kadonotakashi | 0:8fdf9a60065b | 11 | * |
kadonotakashi | 0:8fdf9a60065b | 12 | * Redistribution and use in source and binary forms, with or without |
kadonotakashi | 0:8fdf9a60065b | 13 | * modification, are permitted provided that the following conditions are met: |
kadonotakashi | 0:8fdf9a60065b | 14 | * |
kadonotakashi | 0:8fdf9a60065b | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
kadonotakashi | 0:8fdf9a60065b | 16 | * this list of conditions and the following disclaimer. |
kadonotakashi | 0:8fdf9a60065b | 17 | * |
kadonotakashi | 0:8fdf9a60065b | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
kadonotakashi | 0:8fdf9a60065b | 19 | * this list of conditions and the following disclaimer in the documentation |
kadonotakashi | 0:8fdf9a60065b | 20 | * and/or other materials provided with the distribution. |
kadonotakashi | 0:8fdf9a60065b | 21 | * |
kadonotakashi | 0:8fdf9a60065b | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
kadonotakashi | 0:8fdf9a60065b | 23 | * from this software without specific prior written permission. |
kadonotakashi | 0:8fdf9a60065b | 24 | * |
kadonotakashi | 0:8fdf9a60065b | 25 | * 4. This software may only be redistributed and used in connection with an |
kadonotakashi | 0:8fdf9a60065b | 26 | * Atmel microcontroller product. |
kadonotakashi | 0:8fdf9a60065b | 27 | * |
kadonotakashi | 0:8fdf9a60065b | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
kadonotakashi | 0:8fdf9a60065b | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
kadonotakashi | 0:8fdf9a60065b | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
kadonotakashi | 0:8fdf9a60065b | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
kadonotakashi | 0:8fdf9a60065b | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
kadonotakashi | 0:8fdf9a60065b | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
kadonotakashi | 0:8fdf9a60065b | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
kadonotakashi | 0:8fdf9a60065b | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
kadonotakashi | 0:8fdf9a60065b | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
kadonotakashi | 0:8fdf9a60065b | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
kadonotakashi | 0:8fdf9a60065b | 38 | * POSSIBILITY OF SUCH DAMAGE. |
kadonotakashi | 0:8fdf9a60065b | 39 | * |
kadonotakashi | 0:8fdf9a60065b | 40 | * \asf_license_stop |
kadonotakashi | 0:8fdf9a60065b | 41 | * |
kadonotakashi | 0:8fdf9a60065b | 42 | */ |
kadonotakashi | 0:8fdf9a60065b | 43 | /* |
kadonotakashi | 0:8fdf9a60065b | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
kadonotakashi | 0:8fdf9a60065b | 45 | */ |
kadonotakashi | 0:8fdf9a60065b | 46 | |
kadonotakashi | 0:8fdf9a60065b | 47 | #include "pmc.h" |
kadonotakashi | 0:8fdf9a60065b | 48 | |
kadonotakashi | 0:8fdf9a60065b | 49 | #if (SAM3N) |
kadonotakashi | 0:8fdf9a60065b | 50 | # define MAX_PERIPH_ID 31 |
kadonotakashi | 0:8fdf9a60065b | 51 | #elif (SAM3XA) |
kadonotakashi | 0:8fdf9a60065b | 52 | # define MAX_PERIPH_ID 44 |
kadonotakashi | 0:8fdf9a60065b | 53 | #elif (SAM3U) |
kadonotakashi | 0:8fdf9a60065b | 54 | # define MAX_PERIPH_ID 29 |
kadonotakashi | 0:8fdf9a60065b | 55 | #elif (SAM3S || SAM4S) |
kadonotakashi | 0:8fdf9a60065b | 56 | # define MAX_PERIPH_ID 34 |
kadonotakashi | 0:8fdf9a60065b | 57 | #elif (SAM4E) |
kadonotakashi | 0:8fdf9a60065b | 58 | # define MAX_PERIPH_ID 47 |
kadonotakashi | 0:8fdf9a60065b | 59 | #elif (SAMV71) |
kadonotakashi | 0:8fdf9a60065b | 60 | # define MAX_PERIPH_ID 63 |
kadonotakashi | 0:8fdf9a60065b | 61 | #elif (SAMV70) |
kadonotakashi | 0:8fdf9a60065b | 62 | # define MAX_PERIPH_ID 63 |
kadonotakashi | 0:8fdf9a60065b | 63 | #elif (SAME70) |
kadonotakashi | 0:8fdf9a60065b | 64 | # define MAX_PERIPH_ID 63 |
kadonotakashi | 0:8fdf9a60065b | 65 | #elif (SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 66 | # define MAX_PERIPH_ID 63 |
kadonotakashi | 0:8fdf9a60065b | 67 | #elif (SAM4N) |
kadonotakashi | 0:8fdf9a60065b | 68 | # define MAX_PERIPH_ID 31 |
kadonotakashi | 0:8fdf9a60065b | 69 | #elif (SAM4C || SAM4CM || SAM4CP) |
kadonotakashi | 0:8fdf9a60065b | 70 | # define MAX_PERIPH_ID 43 |
kadonotakashi | 0:8fdf9a60065b | 71 | #elif (SAMG51) |
kadonotakashi | 0:8fdf9a60065b | 72 | # define MAX_PERIPH_ID 47 |
kadonotakashi | 0:8fdf9a60065b | 73 | #elif (SAMG53) |
kadonotakashi | 0:8fdf9a60065b | 74 | # define MAX_PERIPH_ID 47 |
kadonotakashi | 0:8fdf9a60065b | 75 | #elif (SAMG54) |
kadonotakashi | 0:8fdf9a60065b | 76 | # define MAX_PERIPH_ID 47 |
kadonotakashi | 0:8fdf9a60065b | 77 | #elif (SAMG55) |
kadonotakashi | 0:8fdf9a60065b | 78 | # define MAX_PERIPH_ID 50 |
kadonotakashi | 0:8fdf9a60065b | 79 | #endif |
kadonotakashi | 0:8fdf9a60065b | 80 | |
kadonotakashi | 0:8fdf9a60065b | 81 | /// @cond 0 |
kadonotakashi | 0:8fdf9a60065b | 82 | /**INDENT-OFF**/ |
kadonotakashi | 0:8fdf9a60065b | 83 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 84 | extern "C" { |
kadonotakashi | 0:8fdf9a60065b | 85 | #endif |
kadonotakashi | 0:8fdf9a60065b | 86 | /**INDENT-ON**/ |
kadonotakashi | 0:8fdf9a60065b | 87 | /// @endcond |
kadonotakashi | 0:8fdf9a60065b | 88 | |
kadonotakashi | 0:8fdf9a60065b | 89 | /** |
kadonotakashi | 0:8fdf9a60065b | 90 | * \defgroup sam_drivers_pmc_group Power Management Controller (PMC) |
kadonotakashi | 0:8fdf9a60065b | 91 | * |
kadonotakashi | 0:8fdf9a60065b | 92 | * \par Purpose |
kadonotakashi | 0:8fdf9a60065b | 93 | * |
kadonotakashi | 0:8fdf9a60065b | 94 | * The Power Management Controller (PMC) optimizes power consumption by |
kadonotakashi | 0:8fdf9a60065b | 95 | * controlling all system and user peripheral clocks. The PMC enables/disables |
kadonotakashi | 0:8fdf9a60065b | 96 | * the clock inputs to many of the peripherals and the Cortex-M Processor. |
kadonotakashi | 0:8fdf9a60065b | 97 | * |
kadonotakashi | 0:8fdf9a60065b | 98 | * @{ |
kadonotakashi | 0:8fdf9a60065b | 99 | */ |
kadonotakashi | 0:8fdf9a60065b | 100 | |
kadonotakashi | 0:8fdf9a60065b | 101 | /** |
kadonotakashi | 0:8fdf9a60065b | 102 | * \brief Set the prescaler of the MCK. |
kadonotakashi | 0:8fdf9a60065b | 103 | * |
kadonotakashi | 0:8fdf9a60065b | 104 | * \param ul_pres Prescaler value. |
kadonotakashi | 0:8fdf9a60065b | 105 | */ |
kadonotakashi | 0:8fdf9a60065b | 106 | void pmc_mck_set_prescaler(uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 107 | { |
kadonotakashi | 0:8fdf9a60065b | 108 | PMC->PMC_MCKR = |
kadonotakashi | 0:8fdf9a60065b | 109 | (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 110 | while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); |
kadonotakashi | 0:8fdf9a60065b | 111 | } |
kadonotakashi | 0:8fdf9a60065b | 112 | |
kadonotakashi | 0:8fdf9a60065b | 113 | #if SAMV71 || SAMV70 || SAME70 || SAMS70 |
kadonotakashi | 0:8fdf9a60065b | 114 | /** |
kadonotakashi | 0:8fdf9a60065b | 115 | * \brief Set the division of the MCK. |
kadonotakashi | 0:8fdf9a60065b | 116 | * |
kadonotakashi | 0:8fdf9a60065b | 117 | * \param ul_div Division value. |
kadonotakashi | 0:8fdf9a60065b | 118 | */ |
kadonotakashi | 0:8fdf9a60065b | 119 | void pmc_mck_set_division(uint32_t ul_div) |
kadonotakashi | 0:8fdf9a60065b | 120 | { |
kadonotakashi | 0:8fdf9a60065b | 121 | switch (ul_div) { |
kadonotakashi | 0:8fdf9a60065b | 122 | case 1: |
kadonotakashi | 0:8fdf9a60065b | 123 | ul_div = PMC_MCKR_MDIV_EQ_PCK; |
kadonotakashi | 0:8fdf9a60065b | 124 | break; |
kadonotakashi | 0:8fdf9a60065b | 125 | case 2: |
kadonotakashi | 0:8fdf9a60065b | 126 | ul_div = PMC_MCKR_MDIV_PCK_DIV2; |
kadonotakashi | 0:8fdf9a60065b | 127 | break; |
kadonotakashi | 0:8fdf9a60065b | 128 | case 3: |
kadonotakashi | 0:8fdf9a60065b | 129 | ul_div = PMC_MCKR_MDIV_PCK_DIV3; |
kadonotakashi | 0:8fdf9a60065b | 130 | break; |
kadonotakashi | 0:8fdf9a60065b | 131 | case 4: |
kadonotakashi | 0:8fdf9a60065b | 132 | ul_div = PMC_MCKR_MDIV_PCK_DIV4; |
kadonotakashi | 0:8fdf9a60065b | 133 | break; |
kadonotakashi | 0:8fdf9a60065b | 134 | default: |
kadonotakashi | 0:8fdf9a60065b | 135 | ul_div = PMC_MCKR_MDIV_EQ_PCK; |
kadonotakashi | 0:8fdf9a60065b | 136 | break; |
kadonotakashi | 0:8fdf9a60065b | 137 | } |
kadonotakashi | 0:8fdf9a60065b | 138 | PMC->PMC_MCKR = |
kadonotakashi | 0:8fdf9a60065b | 139 | (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div; |
kadonotakashi | 0:8fdf9a60065b | 140 | while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); |
kadonotakashi | 0:8fdf9a60065b | 141 | } |
kadonotakashi | 0:8fdf9a60065b | 142 | #endif |
kadonotakashi | 0:8fdf9a60065b | 143 | |
kadonotakashi | 0:8fdf9a60065b | 144 | /** |
kadonotakashi | 0:8fdf9a60065b | 145 | * \brief Set the source of the MCK. |
kadonotakashi | 0:8fdf9a60065b | 146 | * |
kadonotakashi | 0:8fdf9a60065b | 147 | * \param ul_source Source selection value. |
kadonotakashi | 0:8fdf9a60065b | 148 | */ |
kadonotakashi | 0:8fdf9a60065b | 149 | void pmc_mck_set_source(uint32_t ul_source) |
kadonotakashi | 0:8fdf9a60065b | 150 | { |
kadonotakashi | 0:8fdf9a60065b | 151 | PMC->PMC_MCKR = |
kadonotakashi | 0:8fdf9a60065b | 152 | (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source; |
kadonotakashi | 0:8fdf9a60065b | 153 | while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); |
kadonotakashi | 0:8fdf9a60065b | 154 | } |
kadonotakashi | 0:8fdf9a60065b | 155 | |
kadonotakashi | 0:8fdf9a60065b | 156 | /** |
kadonotakashi | 0:8fdf9a60065b | 157 | * \brief Switch master clock source selection to slow clock. |
kadonotakashi | 0:8fdf9a60065b | 158 | * |
kadonotakashi | 0:8fdf9a60065b | 159 | * \param ul_pres Processor clock prescaler. |
kadonotakashi | 0:8fdf9a60065b | 160 | * |
kadonotakashi | 0:8fdf9a60065b | 161 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 162 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 163 | */ |
kadonotakashi | 0:8fdf9a60065b | 164 | uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 165 | { |
kadonotakashi | 0:8fdf9a60065b | 166 | uint32_t ul_timeout; |
kadonotakashi | 0:8fdf9a60065b | 167 | |
kadonotakashi | 0:8fdf9a60065b | 168 | PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | |
kadonotakashi | 0:8fdf9a60065b | 169 | PMC_MCKR_CSS_SLOW_CLK; |
kadonotakashi | 0:8fdf9a60065b | 170 | for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); |
kadonotakashi | 0:8fdf9a60065b | 171 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 172 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 173 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 174 | } |
kadonotakashi | 0:8fdf9a60065b | 175 | } |
kadonotakashi | 0:8fdf9a60065b | 176 | |
kadonotakashi | 0:8fdf9a60065b | 177 | PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 178 | for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); |
kadonotakashi | 0:8fdf9a60065b | 179 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 180 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 181 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 182 | } |
kadonotakashi | 0:8fdf9a60065b | 183 | } |
kadonotakashi | 0:8fdf9a60065b | 184 | |
kadonotakashi | 0:8fdf9a60065b | 185 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 186 | } |
kadonotakashi | 0:8fdf9a60065b | 187 | |
kadonotakashi | 0:8fdf9a60065b | 188 | /** |
kadonotakashi | 0:8fdf9a60065b | 189 | * \brief Switch master clock source selection to main clock. |
kadonotakashi | 0:8fdf9a60065b | 190 | * |
kadonotakashi | 0:8fdf9a60065b | 191 | * \param ul_pres Processor clock prescaler. |
kadonotakashi | 0:8fdf9a60065b | 192 | * |
kadonotakashi | 0:8fdf9a60065b | 193 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 194 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 195 | */ |
kadonotakashi | 0:8fdf9a60065b | 196 | uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 197 | { |
kadonotakashi | 0:8fdf9a60065b | 198 | uint32_t ul_timeout; |
kadonotakashi | 0:8fdf9a60065b | 199 | |
kadonotakashi | 0:8fdf9a60065b | 200 | PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | |
kadonotakashi | 0:8fdf9a60065b | 201 | PMC_MCKR_CSS_MAIN_CLK; |
kadonotakashi | 0:8fdf9a60065b | 202 | for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); |
kadonotakashi | 0:8fdf9a60065b | 203 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 204 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 205 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 206 | } |
kadonotakashi | 0:8fdf9a60065b | 207 | } |
kadonotakashi | 0:8fdf9a60065b | 208 | |
kadonotakashi | 0:8fdf9a60065b | 209 | PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 210 | for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); |
kadonotakashi | 0:8fdf9a60065b | 211 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 212 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 213 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 214 | } |
kadonotakashi | 0:8fdf9a60065b | 215 | } |
kadonotakashi | 0:8fdf9a60065b | 216 | |
kadonotakashi | 0:8fdf9a60065b | 217 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 218 | } |
kadonotakashi | 0:8fdf9a60065b | 219 | |
kadonotakashi | 0:8fdf9a60065b | 220 | /** |
kadonotakashi | 0:8fdf9a60065b | 221 | * \brief Switch master clock source selection to PLLA clock. |
kadonotakashi | 0:8fdf9a60065b | 222 | * |
kadonotakashi | 0:8fdf9a60065b | 223 | * \param ul_pres Processor clock prescaler. |
kadonotakashi | 0:8fdf9a60065b | 224 | * |
kadonotakashi | 0:8fdf9a60065b | 225 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 226 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 227 | */ |
kadonotakashi | 0:8fdf9a60065b | 228 | uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 229 | { |
kadonotakashi | 0:8fdf9a60065b | 230 | uint32_t ul_timeout; |
kadonotakashi | 0:8fdf9a60065b | 231 | |
kadonotakashi | 0:8fdf9a60065b | 232 | PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 233 | for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); |
kadonotakashi | 0:8fdf9a60065b | 234 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 235 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 236 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 237 | } |
kadonotakashi | 0:8fdf9a60065b | 238 | } |
kadonotakashi | 0:8fdf9a60065b | 239 | |
kadonotakashi | 0:8fdf9a60065b | 240 | PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | |
kadonotakashi | 0:8fdf9a60065b | 241 | PMC_MCKR_CSS_PLLA_CLK; |
kadonotakashi | 0:8fdf9a60065b | 242 | |
kadonotakashi | 0:8fdf9a60065b | 243 | for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); |
kadonotakashi | 0:8fdf9a60065b | 244 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 245 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 246 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 247 | } |
kadonotakashi | 0:8fdf9a60065b | 248 | } |
kadonotakashi | 0:8fdf9a60065b | 249 | |
kadonotakashi | 0:8fdf9a60065b | 250 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 251 | } |
kadonotakashi | 0:8fdf9a60065b | 252 | |
kadonotakashi | 0:8fdf9a60065b | 253 | #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) |
kadonotakashi | 0:8fdf9a60065b | 254 | /** |
kadonotakashi | 0:8fdf9a60065b | 255 | * \brief Switch master clock source selection to PLLB clock. |
kadonotakashi | 0:8fdf9a60065b | 256 | * |
kadonotakashi | 0:8fdf9a60065b | 257 | * \param ul_pres Processor clock prescaler. |
kadonotakashi | 0:8fdf9a60065b | 258 | * |
kadonotakashi | 0:8fdf9a60065b | 259 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 260 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 261 | */ |
kadonotakashi | 0:8fdf9a60065b | 262 | uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 263 | { |
kadonotakashi | 0:8fdf9a60065b | 264 | uint32_t ul_timeout; |
kadonotakashi | 0:8fdf9a60065b | 265 | |
kadonotakashi | 0:8fdf9a60065b | 266 | PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 267 | for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); |
kadonotakashi | 0:8fdf9a60065b | 268 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 269 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 270 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 271 | } |
kadonotakashi | 0:8fdf9a60065b | 272 | } |
kadonotakashi | 0:8fdf9a60065b | 273 | |
kadonotakashi | 0:8fdf9a60065b | 274 | PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | |
kadonotakashi | 0:8fdf9a60065b | 275 | PMC_MCKR_CSS_PLLB_CLK; |
kadonotakashi | 0:8fdf9a60065b | 276 | for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); |
kadonotakashi | 0:8fdf9a60065b | 277 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 278 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 279 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 280 | } |
kadonotakashi | 0:8fdf9a60065b | 281 | } |
kadonotakashi | 0:8fdf9a60065b | 282 | |
kadonotakashi | 0:8fdf9a60065b | 283 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 284 | } |
kadonotakashi | 0:8fdf9a60065b | 285 | #endif |
kadonotakashi | 0:8fdf9a60065b | 286 | |
kadonotakashi | 0:8fdf9a60065b | 287 | #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 288 | /** |
kadonotakashi | 0:8fdf9a60065b | 289 | * \brief Switch master clock source selection to UPLL clock. |
kadonotakashi | 0:8fdf9a60065b | 290 | * |
kadonotakashi | 0:8fdf9a60065b | 291 | * \param ul_pres Processor clock prescaler. |
kadonotakashi | 0:8fdf9a60065b | 292 | * |
kadonotakashi | 0:8fdf9a60065b | 293 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 294 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 295 | */ |
kadonotakashi | 0:8fdf9a60065b | 296 | uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 297 | { |
kadonotakashi | 0:8fdf9a60065b | 298 | uint32_t ul_timeout; |
kadonotakashi | 0:8fdf9a60065b | 299 | |
kadonotakashi | 0:8fdf9a60065b | 300 | PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 301 | for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); |
kadonotakashi | 0:8fdf9a60065b | 302 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 303 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 304 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 305 | } |
kadonotakashi | 0:8fdf9a60065b | 306 | } |
kadonotakashi | 0:8fdf9a60065b | 307 | |
kadonotakashi | 0:8fdf9a60065b | 308 | PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | |
kadonotakashi | 0:8fdf9a60065b | 309 | PMC_MCKR_CSS_UPLL_CLK; |
kadonotakashi | 0:8fdf9a60065b | 310 | for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); |
kadonotakashi | 0:8fdf9a60065b | 311 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 312 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 313 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 314 | } |
kadonotakashi | 0:8fdf9a60065b | 315 | } |
kadonotakashi | 0:8fdf9a60065b | 316 | |
kadonotakashi | 0:8fdf9a60065b | 317 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 318 | } |
kadonotakashi | 0:8fdf9a60065b | 319 | #endif |
kadonotakashi | 0:8fdf9a60065b | 320 | |
kadonotakashi | 0:8fdf9a60065b | 321 | /** |
kadonotakashi | 0:8fdf9a60065b | 322 | * \brief Switch slow clock source selection to external 32k (Xtal or Bypass). |
kadonotakashi | 0:8fdf9a60065b | 323 | * |
kadonotakashi | 0:8fdf9a60065b | 324 | * \note Switching SCLK back to 32krc is only possible by shutting down the |
kadonotakashi | 0:8fdf9a60065b | 325 | * VDDIO power supply. |
kadonotakashi | 0:8fdf9a60065b | 326 | * |
kadonotakashi | 0:8fdf9a60065b | 327 | * \param ul_bypass 0 for Xtal, 1 for bypass. |
kadonotakashi | 0:8fdf9a60065b | 328 | */ |
kadonotakashi | 0:8fdf9a60065b | 329 | void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass) |
kadonotakashi | 0:8fdf9a60065b | 330 | { |
kadonotakashi | 0:8fdf9a60065b | 331 | /* Set Bypass mode if required */ |
kadonotakashi | 0:8fdf9a60065b | 332 | if (ul_bypass == 1) { |
kadonotakashi | 0:8fdf9a60065b | 333 | SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD | |
kadonotakashi | 0:8fdf9a60065b | 334 | SUPC_MR_OSCBYPASS; |
kadonotakashi | 0:8fdf9a60065b | 335 | } |
kadonotakashi | 0:8fdf9a60065b | 336 | |
kadonotakashi | 0:8fdf9a60065b | 337 | SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; |
kadonotakashi | 0:8fdf9a60065b | 338 | } |
kadonotakashi | 0:8fdf9a60065b | 339 | |
kadonotakashi | 0:8fdf9a60065b | 340 | /** |
kadonotakashi | 0:8fdf9a60065b | 341 | * \brief Check if the external 32k Xtal is ready. |
kadonotakashi | 0:8fdf9a60065b | 342 | * |
kadonotakashi | 0:8fdf9a60065b | 343 | * \retval 1 External 32k Xtal is ready. |
kadonotakashi | 0:8fdf9a60065b | 344 | * \retval 0 External 32k Xtal is not ready. |
kadonotakashi | 0:8fdf9a60065b | 345 | */ |
kadonotakashi | 0:8fdf9a60065b | 346 | uint32_t pmc_osc_is_ready_32kxtal(void) |
kadonotakashi | 0:8fdf9a60065b | 347 | { |
kadonotakashi | 0:8fdf9a60065b | 348 | return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) |
kadonotakashi | 0:8fdf9a60065b | 349 | && (PMC->PMC_SR & PMC_SR_OSCSELS)); |
kadonotakashi | 0:8fdf9a60065b | 350 | } |
kadonotakashi | 0:8fdf9a60065b | 351 | |
kadonotakashi | 0:8fdf9a60065b | 352 | /** |
kadonotakashi | 0:8fdf9a60065b | 353 | * \brief Switch main clock source selection to internal fast RC. |
kadonotakashi | 0:8fdf9a60065b | 354 | * |
kadonotakashi | 0:8fdf9a60065b | 355 | * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz). |
kadonotakashi | 0:8fdf9a60065b | 356 | * |
kadonotakashi | 0:8fdf9a60065b | 357 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 358 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 359 | * \retval 2 Invalid frequency. |
kadonotakashi | 0:8fdf9a60065b | 360 | */ |
kadonotakashi | 0:8fdf9a60065b | 361 | void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf) |
kadonotakashi | 0:8fdf9a60065b | 362 | { |
kadonotakashi | 0:8fdf9a60065b | 363 | /* Enable Fast RC oscillator but DO NOT switch to RC now */ |
kadonotakashi | 0:8fdf9a60065b | 364 | PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN); |
kadonotakashi | 0:8fdf9a60065b | 365 | |
kadonotakashi | 0:8fdf9a60065b | 366 | /* Wait the Fast RC to stabilize */ |
kadonotakashi | 0:8fdf9a60065b | 367 | while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); |
kadonotakashi | 0:8fdf9a60065b | 368 | |
kadonotakashi | 0:8fdf9a60065b | 369 | /* Change Fast RC oscillator frequency */ |
kadonotakashi | 0:8fdf9a60065b | 370 | PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | |
kadonotakashi | 0:8fdf9a60065b | 371 | CKGR_MOR_KEY_PASSWD | ul_moscrcf; |
kadonotakashi | 0:8fdf9a60065b | 372 | |
kadonotakashi | 0:8fdf9a60065b | 373 | /* Wait the Fast RC to stabilize */ |
kadonotakashi | 0:8fdf9a60065b | 374 | while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); |
kadonotakashi | 0:8fdf9a60065b | 375 | |
kadonotakashi | 0:8fdf9a60065b | 376 | /* Switch to Fast RC */ |
kadonotakashi | 0:8fdf9a60065b | 377 | PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | |
kadonotakashi | 0:8fdf9a60065b | 378 | CKGR_MOR_KEY_PASSWD; |
kadonotakashi | 0:8fdf9a60065b | 379 | } |
kadonotakashi | 0:8fdf9a60065b | 380 | |
kadonotakashi | 0:8fdf9a60065b | 381 | /** |
kadonotakashi | 0:8fdf9a60065b | 382 | * \brief Enable fast RC oscillator. |
kadonotakashi | 0:8fdf9a60065b | 383 | * |
kadonotakashi | 0:8fdf9a60065b | 384 | * \param ul_rc Fast RC oscillator(4/8/12Mhz). |
kadonotakashi | 0:8fdf9a60065b | 385 | */ |
kadonotakashi | 0:8fdf9a60065b | 386 | void pmc_osc_enable_fastrc(uint32_t ul_rc) |
kadonotakashi | 0:8fdf9a60065b | 387 | { |
kadonotakashi | 0:8fdf9a60065b | 388 | /* Enable Fast RC oscillator but DO NOT switch to RC */ |
kadonotakashi | 0:8fdf9a60065b | 389 | PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN); |
kadonotakashi | 0:8fdf9a60065b | 390 | /* Wait the Fast RC to stabilize */ |
kadonotakashi | 0:8fdf9a60065b | 391 | while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); |
kadonotakashi | 0:8fdf9a60065b | 392 | |
kadonotakashi | 0:8fdf9a60065b | 393 | /* Change Fast RC oscillator frequency */ |
kadonotakashi | 0:8fdf9a60065b | 394 | PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | |
kadonotakashi | 0:8fdf9a60065b | 395 | CKGR_MOR_KEY_PASSWD | ul_rc; |
kadonotakashi | 0:8fdf9a60065b | 396 | /* Wait the Fast RC to stabilize */ |
kadonotakashi | 0:8fdf9a60065b | 397 | while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); |
kadonotakashi | 0:8fdf9a60065b | 398 | } |
kadonotakashi | 0:8fdf9a60065b | 399 | |
kadonotakashi | 0:8fdf9a60065b | 400 | /** |
kadonotakashi | 0:8fdf9a60065b | 401 | * \brief Disable the internal fast RC. |
kadonotakashi | 0:8fdf9a60065b | 402 | */ |
kadonotakashi | 0:8fdf9a60065b | 403 | void pmc_osc_disable_fastrc(void) |
kadonotakashi | 0:8fdf9a60065b | 404 | { |
kadonotakashi | 0:8fdf9a60065b | 405 | /* Disable Fast RC oscillator */ |
kadonotakashi | 0:8fdf9a60065b | 406 | PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & |
kadonotakashi | 0:8fdf9a60065b | 407 | ~CKGR_MOR_MOSCRCF_Msk) |
kadonotakashi | 0:8fdf9a60065b | 408 | | CKGR_MOR_KEY_PASSWD; |
kadonotakashi | 0:8fdf9a60065b | 409 | } |
kadonotakashi | 0:8fdf9a60065b | 410 | |
kadonotakashi | 0:8fdf9a60065b | 411 | /** |
kadonotakashi | 0:8fdf9a60065b | 412 | * \brief Check if the main fastrc is ready. |
kadonotakashi | 0:8fdf9a60065b | 413 | * |
kadonotakashi | 0:8fdf9a60065b | 414 | * \retval 0 Xtal is not ready, otherwise ready. |
kadonotakashi | 0:8fdf9a60065b | 415 | */ |
kadonotakashi | 0:8fdf9a60065b | 416 | uint32_t pmc_osc_is_ready_fastrc(void) |
kadonotakashi | 0:8fdf9a60065b | 417 | { |
kadonotakashi | 0:8fdf9a60065b | 418 | return (PMC->PMC_SR & PMC_SR_MOSCRCS); |
kadonotakashi | 0:8fdf9a60065b | 419 | } |
kadonotakashi | 0:8fdf9a60065b | 420 | |
kadonotakashi | 0:8fdf9a60065b | 421 | /** |
kadonotakashi | 0:8fdf9a60065b | 422 | * \brief Enable main XTAL oscillator. |
kadonotakashi | 0:8fdf9a60065b | 423 | * |
kadonotakashi | 0:8fdf9a60065b | 424 | * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks. |
kadonotakashi | 0:8fdf9a60065b | 425 | */ |
kadonotakashi | 0:8fdf9a60065b | 426 | void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time) |
kadonotakashi | 0:8fdf9a60065b | 427 | { |
kadonotakashi | 0:8fdf9a60065b | 428 | uint32_t mor = PMC->CKGR_MOR; |
kadonotakashi | 0:8fdf9a60065b | 429 | mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); |
kadonotakashi | 0:8fdf9a60065b | 430 | mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | |
kadonotakashi | 0:8fdf9a60065b | 431 | CKGR_MOR_MOSCXTST(ul_xtal_startup_time); |
kadonotakashi | 0:8fdf9a60065b | 432 | PMC->CKGR_MOR = mor; |
kadonotakashi | 0:8fdf9a60065b | 433 | /* Wait the main Xtal to stabilize */ |
kadonotakashi | 0:8fdf9a60065b | 434 | while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); |
kadonotakashi | 0:8fdf9a60065b | 435 | } |
kadonotakashi | 0:8fdf9a60065b | 436 | |
kadonotakashi | 0:8fdf9a60065b | 437 | /** |
kadonotakashi | 0:8fdf9a60065b | 438 | * \brief Bypass main XTAL. |
kadonotakashi | 0:8fdf9a60065b | 439 | */ |
kadonotakashi | 0:8fdf9a60065b | 440 | void pmc_osc_bypass_main_xtal(void) |
kadonotakashi | 0:8fdf9a60065b | 441 | { |
kadonotakashi | 0:8fdf9a60065b | 442 | uint32_t mor = PMC->CKGR_MOR; |
kadonotakashi | 0:8fdf9a60065b | 443 | mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); |
kadonotakashi | 0:8fdf9a60065b | 444 | mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY; |
kadonotakashi | 0:8fdf9a60065b | 445 | /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */ |
kadonotakashi | 0:8fdf9a60065b | 446 | PMC->CKGR_MOR = mor; |
kadonotakashi | 0:8fdf9a60065b | 447 | /* The MOSCXTS in PMC_SR is automatically set */ |
kadonotakashi | 0:8fdf9a60065b | 448 | } |
kadonotakashi | 0:8fdf9a60065b | 449 | |
kadonotakashi | 0:8fdf9a60065b | 450 | /** |
kadonotakashi | 0:8fdf9a60065b | 451 | * \brief Disable the main Xtal. |
kadonotakashi | 0:8fdf9a60065b | 452 | */ |
kadonotakashi | 0:8fdf9a60065b | 453 | void pmc_osc_disable_main_xtal(void) |
kadonotakashi | 0:8fdf9a60065b | 454 | { |
kadonotakashi | 0:8fdf9a60065b | 455 | uint32_t mor = PMC->CKGR_MOR; |
kadonotakashi | 0:8fdf9a60065b | 456 | mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); |
kadonotakashi | 0:8fdf9a60065b | 457 | PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor; |
kadonotakashi | 0:8fdf9a60065b | 458 | } |
kadonotakashi | 0:8fdf9a60065b | 459 | |
kadonotakashi | 0:8fdf9a60065b | 460 | /** |
kadonotakashi | 0:8fdf9a60065b | 461 | * \brief Check if the main crystal is bypassed. |
kadonotakashi | 0:8fdf9a60065b | 462 | * |
kadonotakashi | 0:8fdf9a60065b | 463 | * \retval 0 Xtal is bypassed, otherwise not. |
kadonotakashi | 0:8fdf9a60065b | 464 | */ |
kadonotakashi | 0:8fdf9a60065b | 465 | uint32_t pmc_osc_is_bypassed_main_xtal(void) |
kadonotakashi | 0:8fdf9a60065b | 466 | { |
kadonotakashi | 0:8fdf9a60065b | 467 | return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY); |
kadonotakashi | 0:8fdf9a60065b | 468 | } |
kadonotakashi | 0:8fdf9a60065b | 469 | |
kadonotakashi | 0:8fdf9a60065b | 470 | /** |
kadonotakashi | 0:8fdf9a60065b | 471 | * \brief Check if the main crystal is ready. |
kadonotakashi | 0:8fdf9a60065b | 472 | * |
kadonotakashi | 0:8fdf9a60065b | 473 | * \note If main crystal is bypassed, it's always ready. |
kadonotakashi | 0:8fdf9a60065b | 474 | * |
kadonotakashi | 0:8fdf9a60065b | 475 | * \retval 0 main crystal is not ready, otherwise ready. |
kadonotakashi | 0:8fdf9a60065b | 476 | */ |
kadonotakashi | 0:8fdf9a60065b | 477 | uint32_t pmc_osc_is_ready_main_xtal(void) |
kadonotakashi | 0:8fdf9a60065b | 478 | { |
kadonotakashi | 0:8fdf9a60065b | 479 | return (PMC->PMC_SR & PMC_SR_MOSCXTS); |
kadonotakashi | 0:8fdf9a60065b | 480 | } |
kadonotakashi | 0:8fdf9a60065b | 481 | |
kadonotakashi | 0:8fdf9a60065b | 482 | /** |
kadonotakashi | 0:8fdf9a60065b | 483 | * \brief Switch main clock source selection to external Xtal/Bypass. |
kadonotakashi | 0:8fdf9a60065b | 484 | * |
kadonotakashi | 0:8fdf9a60065b | 485 | * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid |
kadonotakashi | 0:8fdf9a60065b | 486 | * any system crash. |
kadonotakashi | 0:8fdf9a60065b | 487 | * |
kadonotakashi | 0:8fdf9a60065b | 488 | * \note If used in Xtal mode, the Xtal is automatically enabled. |
kadonotakashi | 0:8fdf9a60065b | 489 | * |
kadonotakashi | 0:8fdf9a60065b | 490 | * \param ul_bypass 0 for Xtal, 1 for bypass. |
kadonotakashi | 0:8fdf9a60065b | 491 | * |
kadonotakashi | 0:8fdf9a60065b | 492 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 493 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 494 | */ |
kadonotakashi | 0:8fdf9a60065b | 495 | void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, |
kadonotakashi | 0:8fdf9a60065b | 496 | uint32_t ul_xtal_startup_time) |
kadonotakashi | 0:8fdf9a60065b | 497 | { |
kadonotakashi | 0:8fdf9a60065b | 498 | /* Enable Main Xtal oscillator */ |
kadonotakashi | 0:8fdf9a60065b | 499 | if (ul_bypass) { |
kadonotakashi | 0:8fdf9a60065b | 500 | PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | |
kadonotakashi | 0:8fdf9a60065b | 501 | CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | |
kadonotakashi | 0:8fdf9a60065b | 502 | CKGR_MOR_MOSCSEL; |
kadonotakashi | 0:8fdf9a60065b | 503 | } else { |
kadonotakashi | 0:8fdf9a60065b | 504 | PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | |
kadonotakashi | 0:8fdf9a60065b | 505 | CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | |
kadonotakashi | 0:8fdf9a60065b | 506 | CKGR_MOR_MOSCXTST(ul_xtal_startup_time); |
kadonotakashi | 0:8fdf9a60065b | 507 | /* Wait the Xtal to stabilize */ |
kadonotakashi | 0:8fdf9a60065b | 508 | while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); |
kadonotakashi | 0:8fdf9a60065b | 509 | |
kadonotakashi | 0:8fdf9a60065b | 510 | PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; |
kadonotakashi | 0:8fdf9a60065b | 511 | } |
kadonotakashi | 0:8fdf9a60065b | 512 | } |
kadonotakashi | 0:8fdf9a60065b | 513 | |
kadonotakashi | 0:8fdf9a60065b | 514 | /** |
kadonotakashi | 0:8fdf9a60065b | 515 | * \brief Disable the external Xtal. |
kadonotakashi | 0:8fdf9a60065b | 516 | * |
kadonotakashi | 0:8fdf9a60065b | 517 | * \param ul_bypass 0 for Xtal, 1 for bypass. |
kadonotakashi | 0:8fdf9a60065b | 518 | */ |
kadonotakashi | 0:8fdf9a60065b | 519 | void pmc_osc_disable_xtal(uint32_t ul_bypass) |
kadonotakashi | 0:8fdf9a60065b | 520 | { |
kadonotakashi | 0:8fdf9a60065b | 521 | /* Disable xtal oscillator */ |
kadonotakashi | 0:8fdf9a60065b | 522 | if (ul_bypass) { |
kadonotakashi | 0:8fdf9a60065b | 523 | PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | |
kadonotakashi | 0:8fdf9a60065b | 524 | CKGR_MOR_KEY_PASSWD; |
kadonotakashi | 0:8fdf9a60065b | 525 | } else { |
kadonotakashi | 0:8fdf9a60065b | 526 | PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | |
kadonotakashi | 0:8fdf9a60065b | 527 | CKGR_MOR_KEY_PASSWD; |
kadonotakashi | 0:8fdf9a60065b | 528 | } |
kadonotakashi | 0:8fdf9a60065b | 529 | } |
kadonotakashi | 0:8fdf9a60065b | 530 | |
kadonotakashi | 0:8fdf9a60065b | 531 | /** |
kadonotakashi | 0:8fdf9a60065b | 532 | * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one |
kadonotakashi | 0:8fdf9a60065b | 533 | * of Xtal, bypass or internal RC. |
kadonotakashi | 0:8fdf9a60065b | 534 | * |
kadonotakashi | 0:8fdf9a60065b | 535 | * \retval 1 Xtal is ready. |
kadonotakashi | 0:8fdf9a60065b | 536 | * \retval 0 Xtal is not ready. |
kadonotakashi | 0:8fdf9a60065b | 537 | */ |
kadonotakashi | 0:8fdf9a60065b | 538 | uint32_t pmc_osc_is_ready_mainck(void) |
kadonotakashi | 0:8fdf9a60065b | 539 | { |
kadonotakashi | 0:8fdf9a60065b | 540 | return PMC->PMC_SR & PMC_SR_MOSCSELS; |
kadonotakashi | 0:8fdf9a60065b | 541 | } |
kadonotakashi | 0:8fdf9a60065b | 542 | |
kadonotakashi | 0:8fdf9a60065b | 543 | /** |
kadonotakashi | 0:8fdf9a60065b | 544 | * \brief Select Main Crystal or internal RC as main clock source. |
kadonotakashi | 0:8fdf9a60065b | 545 | * |
kadonotakashi | 0:8fdf9a60065b | 546 | * \note This function will not enable/disable RC or Main Crystal. |
kadonotakashi | 0:8fdf9a60065b | 547 | * |
kadonotakashi | 0:8fdf9a60065b | 548 | * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal. |
kadonotakashi | 0:8fdf9a60065b | 549 | */ |
kadonotakashi | 0:8fdf9a60065b | 550 | void pmc_mainck_osc_select(uint32_t ul_xtal_rc) |
kadonotakashi | 0:8fdf9a60065b | 551 | { |
kadonotakashi | 0:8fdf9a60065b | 552 | uint32_t mor = PMC->CKGR_MOR; |
kadonotakashi | 0:8fdf9a60065b | 553 | if (ul_xtal_rc) { |
kadonotakashi | 0:8fdf9a60065b | 554 | mor |= CKGR_MOR_MOSCSEL; |
kadonotakashi | 0:8fdf9a60065b | 555 | } else { |
kadonotakashi | 0:8fdf9a60065b | 556 | mor &= ~CKGR_MOR_MOSCSEL; |
kadonotakashi | 0:8fdf9a60065b | 557 | } |
kadonotakashi | 0:8fdf9a60065b | 558 | PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor; |
kadonotakashi | 0:8fdf9a60065b | 559 | } |
kadonotakashi | 0:8fdf9a60065b | 560 | |
kadonotakashi | 0:8fdf9a60065b | 561 | /** |
kadonotakashi | 0:8fdf9a60065b | 562 | * \brief Enable PLLA clock. |
kadonotakashi | 0:8fdf9a60065b | 563 | * |
kadonotakashi | 0:8fdf9a60065b | 564 | * \param mula PLLA multiplier. |
kadonotakashi | 0:8fdf9a60065b | 565 | * \param pllacount PLLA counter. |
kadonotakashi | 0:8fdf9a60065b | 566 | * \param diva Divider. |
kadonotakashi | 0:8fdf9a60065b | 567 | */ |
kadonotakashi | 0:8fdf9a60065b | 568 | void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva) |
kadonotakashi | 0:8fdf9a60065b | 569 | { |
kadonotakashi | 0:8fdf9a60065b | 570 | /* first disable the PLL to unlock the lock */ |
kadonotakashi | 0:8fdf9a60065b | 571 | pmc_disable_pllack(); |
kadonotakashi | 0:8fdf9a60065b | 572 | |
kadonotakashi | 0:8fdf9a60065b | 573 | #if (SAM4C || SAM4CM || SAM4CP || SAMG) |
kadonotakashi | 0:8fdf9a60065b | 574 | PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) | |
kadonotakashi | 0:8fdf9a60065b | 575 | CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); |
kadonotakashi | 0:8fdf9a60065b | 576 | #else |
kadonotakashi | 0:8fdf9a60065b | 577 | PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) | |
kadonotakashi | 0:8fdf9a60065b | 578 | CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); |
kadonotakashi | 0:8fdf9a60065b | 579 | #endif |
kadonotakashi | 0:8fdf9a60065b | 580 | while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0); |
kadonotakashi | 0:8fdf9a60065b | 581 | } |
kadonotakashi | 0:8fdf9a60065b | 582 | |
kadonotakashi | 0:8fdf9a60065b | 583 | /** |
kadonotakashi | 0:8fdf9a60065b | 584 | * \brief Disable PLLA clock. |
kadonotakashi | 0:8fdf9a60065b | 585 | */ |
kadonotakashi | 0:8fdf9a60065b | 586 | void pmc_disable_pllack(void) |
kadonotakashi | 0:8fdf9a60065b | 587 | { |
kadonotakashi | 0:8fdf9a60065b | 588 | #if (SAM4C || SAM4CM || SAM4CP || SAMG) |
kadonotakashi | 0:8fdf9a60065b | 589 | PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0); |
kadonotakashi | 0:8fdf9a60065b | 590 | #else |
kadonotakashi | 0:8fdf9a60065b | 591 | PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0); |
kadonotakashi | 0:8fdf9a60065b | 592 | #endif |
kadonotakashi | 0:8fdf9a60065b | 593 | } |
kadonotakashi | 0:8fdf9a60065b | 594 | |
kadonotakashi | 0:8fdf9a60065b | 595 | /** |
kadonotakashi | 0:8fdf9a60065b | 596 | * \brief Is PLLA locked? |
kadonotakashi | 0:8fdf9a60065b | 597 | * |
kadonotakashi | 0:8fdf9a60065b | 598 | * \retval 0 Not locked. |
kadonotakashi | 0:8fdf9a60065b | 599 | * \retval 1 Locked. |
kadonotakashi | 0:8fdf9a60065b | 600 | */ |
kadonotakashi | 0:8fdf9a60065b | 601 | uint32_t pmc_is_locked_pllack(void) |
kadonotakashi | 0:8fdf9a60065b | 602 | { |
kadonotakashi | 0:8fdf9a60065b | 603 | return (PMC->PMC_SR & PMC_SR_LOCKA); |
kadonotakashi | 0:8fdf9a60065b | 604 | } |
kadonotakashi | 0:8fdf9a60065b | 605 | |
kadonotakashi | 0:8fdf9a60065b | 606 | #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) |
kadonotakashi | 0:8fdf9a60065b | 607 | /** |
kadonotakashi | 0:8fdf9a60065b | 608 | * \brief Enable PLLB clock. |
kadonotakashi | 0:8fdf9a60065b | 609 | * |
kadonotakashi | 0:8fdf9a60065b | 610 | * \param mulb PLLB multiplier. |
kadonotakashi | 0:8fdf9a60065b | 611 | * \param pllbcount PLLB counter. |
kadonotakashi | 0:8fdf9a60065b | 612 | * \param divb Divider. |
kadonotakashi | 0:8fdf9a60065b | 613 | */ |
kadonotakashi | 0:8fdf9a60065b | 614 | void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb) |
kadonotakashi | 0:8fdf9a60065b | 615 | { |
kadonotakashi | 0:8fdf9a60065b | 616 | /* first disable the PLL to unlock the lock */ |
kadonotakashi | 0:8fdf9a60065b | 617 | pmc_disable_pllbck(); |
kadonotakashi | 0:8fdf9a60065b | 618 | |
kadonotakashi | 0:8fdf9a60065b | 619 | #if SAMG55 |
kadonotakashi | 0:8fdf9a60065b | 620 | PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) | |
kadonotakashi | 0:8fdf9a60065b | 621 | CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb); |
kadonotakashi | 0:8fdf9a60065b | 622 | #else |
kadonotakashi | 0:8fdf9a60065b | 623 | PMC->CKGR_PLLBR = |
kadonotakashi | 0:8fdf9a60065b | 624 | CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount) |
kadonotakashi | 0:8fdf9a60065b | 625 | | CKGR_PLLBR_MULB(mulb); |
kadonotakashi | 0:8fdf9a60065b | 626 | #endif |
kadonotakashi | 0:8fdf9a60065b | 627 | while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0); |
kadonotakashi | 0:8fdf9a60065b | 628 | } |
kadonotakashi | 0:8fdf9a60065b | 629 | |
kadonotakashi | 0:8fdf9a60065b | 630 | /** |
kadonotakashi | 0:8fdf9a60065b | 631 | * \brief Disable PLLB clock. |
kadonotakashi | 0:8fdf9a60065b | 632 | */ |
kadonotakashi | 0:8fdf9a60065b | 633 | void pmc_disable_pllbck(void) |
kadonotakashi | 0:8fdf9a60065b | 634 | { |
kadonotakashi | 0:8fdf9a60065b | 635 | PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0); |
kadonotakashi | 0:8fdf9a60065b | 636 | } |
kadonotakashi | 0:8fdf9a60065b | 637 | |
kadonotakashi | 0:8fdf9a60065b | 638 | /** |
kadonotakashi | 0:8fdf9a60065b | 639 | * \brief Is PLLB locked? |
kadonotakashi | 0:8fdf9a60065b | 640 | * |
kadonotakashi | 0:8fdf9a60065b | 641 | * \retval 0 Not locked. |
kadonotakashi | 0:8fdf9a60065b | 642 | * \retval 1 Locked. |
kadonotakashi | 0:8fdf9a60065b | 643 | */ |
kadonotakashi | 0:8fdf9a60065b | 644 | uint32_t pmc_is_locked_pllbck(void) |
kadonotakashi | 0:8fdf9a60065b | 645 | { |
kadonotakashi | 0:8fdf9a60065b | 646 | return (PMC->PMC_SR & PMC_SR_LOCKB); |
kadonotakashi | 0:8fdf9a60065b | 647 | } |
kadonotakashi | 0:8fdf9a60065b | 648 | #endif |
kadonotakashi | 0:8fdf9a60065b | 649 | |
kadonotakashi | 0:8fdf9a60065b | 650 | #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 651 | /** |
kadonotakashi | 0:8fdf9a60065b | 652 | * \brief Enable UPLL clock. |
kadonotakashi | 0:8fdf9a60065b | 653 | */ |
kadonotakashi | 0:8fdf9a60065b | 654 | void pmc_enable_upll_clock(void) |
kadonotakashi | 0:8fdf9a60065b | 655 | { |
kadonotakashi | 0:8fdf9a60065b | 656 | PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN; |
kadonotakashi | 0:8fdf9a60065b | 657 | |
kadonotakashi | 0:8fdf9a60065b | 658 | /* Wait UTMI PLL Lock Status */ |
kadonotakashi | 0:8fdf9a60065b | 659 | while (!(PMC->PMC_SR & PMC_SR_LOCKU)); |
kadonotakashi | 0:8fdf9a60065b | 660 | } |
kadonotakashi | 0:8fdf9a60065b | 661 | |
kadonotakashi | 0:8fdf9a60065b | 662 | /** |
kadonotakashi | 0:8fdf9a60065b | 663 | * \brief Disable UPLL clock. |
kadonotakashi | 0:8fdf9a60065b | 664 | */ |
kadonotakashi | 0:8fdf9a60065b | 665 | void pmc_disable_upll_clock(void) |
kadonotakashi | 0:8fdf9a60065b | 666 | { |
kadonotakashi | 0:8fdf9a60065b | 667 | PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; |
kadonotakashi | 0:8fdf9a60065b | 668 | } |
kadonotakashi | 0:8fdf9a60065b | 669 | |
kadonotakashi | 0:8fdf9a60065b | 670 | /** |
kadonotakashi | 0:8fdf9a60065b | 671 | * \brief Is UPLL locked? |
kadonotakashi | 0:8fdf9a60065b | 672 | * |
kadonotakashi | 0:8fdf9a60065b | 673 | * \retval 0 Not locked. |
kadonotakashi | 0:8fdf9a60065b | 674 | * \retval 1 Locked. |
kadonotakashi | 0:8fdf9a60065b | 675 | */ |
kadonotakashi | 0:8fdf9a60065b | 676 | uint32_t pmc_is_locked_upll(void) |
kadonotakashi | 0:8fdf9a60065b | 677 | { |
kadonotakashi | 0:8fdf9a60065b | 678 | return (PMC->PMC_SR & PMC_SR_LOCKU); |
kadonotakashi | 0:8fdf9a60065b | 679 | } |
kadonotakashi | 0:8fdf9a60065b | 680 | #endif |
kadonotakashi | 0:8fdf9a60065b | 681 | |
kadonotakashi | 0:8fdf9a60065b | 682 | /** |
kadonotakashi | 0:8fdf9a60065b | 683 | * \brief Enable the specified peripheral clock. |
kadonotakashi | 0:8fdf9a60065b | 684 | * |
kadonotakashi | 0:8fdf9a60065b | 685 | * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). |
kadonotakashi | 0:8fdf9a60065b | 686 | * |
kadonotakashi | 0:8fdf9a60065b | 687 | * \param ul_id Peripheral ID (ID_xxx). |
kadonotakashi | 0:8fdf9a60065b | 688 | * |
kadonotakashi | 0:8fdf9a60065b | 689 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 690 | * \retval 1 Invalid parameter. |
kadonotakashi | 0:8fdf9a60065b | 691 | */ |
kadonotakashi | 0:8fdf9a60065b | 692 | uint32_t pmc_enable_periph_clk(uint32_t ul_id) |
kadonotakashi | 0:8fdf9a60065b | 693 | { |
kadonotakashi | 0:8fdf9a60065b | 694 | if (ul_id > MAX_PERIPH_ID) { |
kadonotakashi | 0:8fdf9a60065b | 695 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 696 | } |
kadonotakashi | 0:8fdf9a60065b | 697 | |
kadonotakashi | 0:8fdf9a60065b | 698 | if (ul_id < 32) { |
kadonotakashi | 0:8fdf9a60065b | 699 | if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) { |
kadonotakashi | 0:8fdf9a60065b | 700 | PMC->PMC_PCER0 = 1 << ul_id; |
kadonotakashi | 0:8fdf9a60065b | 701 | } |
kadonotakashi | 0:8fdf9a60065b | 702 | #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 703 | } else { |
kadonotakashi | 0:8fdf9a60065b | 704 | ul_id -= 32; |
kadonotakashi | 0:8fdf9a60065b | 705 | if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) { |
kadonotakashi | 0:8fdf9a60065b | 706 | PMC->PMC_PCER1 = 1 << ul_id; |
kadonotakashi | 0:8fdf9a60065b | 707 | } |
kadonotakashi | 0:8fdf9a60065b | 708 | #endif |
kadonotakashi | 0:8fdf9a60065b | 709 | } |
kadonotakashi | 0:8fdf9a60065b | 710 | |
kadonotakashi | 0:8fdf9a60065b | 711 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 712 | } |
kadonotakashi | 0:8fdf9a60065b | 713 | |
kadonotakashi | 0:8fdf9a60065b | 714 | /** |
kadonotakashi | 0:8fdf9a60065b | 715 | * \brief Disable the specified peripheral clock. |
kadonotakashi | 0:8fdf9a60065b | 716 | * |
kadonotakashi | 0:8fdf9a60065b | 717 | * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). |
kadonotakashi | 0:8fdf9a60065b | 718 | * |
kadonotakashi | 0:8fdf9a60065b | 719 | * \param ul_id Peripheral ID (ID_xxx). |
kadonotakashi | 0:8fdf9a60065b | 720 | * |
kadonotakashi | 0:8fdf9a60065b | 721 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 722 | * \retval 1 Invalid parameter. |
kadonotakashi | 0:8fdf9a60065b | 723 | */ |
kadonotakashi | 0:8fdf9a60065b | 724 | uint32_t pmc_disable_periph_clk(uint32_t ul_id) |
kadonotakashi | 0:8fdf9a60065b | 725 | { |
kadonotakashi | 0:8fdf9a60065b | 726 | if (ul_id > MAX_PERIPH_ID) { |
kadonotakashi | 0:8fdf9a60065b | 727 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 728 | } |
kadonotakashi | 0:8fdf9a60065b | 729 | |
kadonotakashi | 0:8fdf9a60065b | 730 | if (ul_id < 32) { |
kadonotakashi | 0:8fdf9a60065b | 731 | if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) { |
kadonotakashi | 0:8fdf9a60065b | 732 | PMC->PMC_PCDR0 = 1 << ul_id; |
kadonotakashi | 0:8fdf9a60065b | 733 | } |
kadonotakashi | 0:8fdf9a60065b | 734 | #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \ |
kadonotakashi | 0:8fdf9a60065b | 735 | || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 736 | } else { |
kadonotakashi | 0:8fdf9a60065b | 737 | ul_id -= 32; |
kadonotakashi | 0:8fdf9a60065b | 738 | if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) { |
kadonotakashi | 0:8fdf9a60065b | 739 | PMC->PMC_PCDR1 = 1 << ul_id; |
kadonotakashi | 0:8fdf9a60065b | 740 | } |
kadonotakashi | 0:8fdf9a60065b | 741 | #endif |
kadonotakashi | 0:8fdf9a60065b | 742 | } |
kadonotakashi | 0:8fdf9a60065b | 743 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 744 | } |
kadonotakashi | 0:8fdf9a60065b | 745 | |
kadonotakashi | 0:8fdf9a60065b | 746 | /** |
kadonotakashi | 0:8fdf9a60065b | 747 | * \brief Enable all peripheral clocks. |
kadonotakashi | 0:8fdf9a60065b | 748 | */ |
kadonotakashi | 0:8fdf9a60065b | 749 | void pmc_enable_all_periph_clk(void) |
kadonotakashi | 0:8fdf9a60065b | 750 | { |
kadonotakashi | 0:8fdf9a60065b | 751 | PMC->PMC_PCER0 = PMC_MASK_STATUS0; |
kadonotakashi | 0:8fdf9a60065b | 752 | while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0); |
kadonotakashi | 0:8fdf9a60065b | 753 | |
kadonotakashi | 0:8fdf9a60065b | 754 | #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ |
kadonotakashi | 0:8fdf9a60065b | 755 | || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 756 | PMC->PMC_PCER1 = PMC_MASK_STATUS1; |
kadonotakashi | 0:8fdf9a60065b | 757 | while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1); |
kadonotakashi | 0:8fdf9a60065b | 758 | #endif |
kadonotakashi | 0:8fdf9a60065b | 759 | } |
kadonotakashi | 0:8fdf9a60065b | 760 | |
kadonotakashi | 0:8fdf9a60065b | 761 | /** |
kadonotakashi | 0:8fdf9a60065b | 762 | * \brief Disable all peripheral clocks. |
kadonotakashi | 0:8fdf9a60065b | 763 | */ |
kadonotakashi | 0:8fdf9a60065b | 764 | void pmc_disable_all_periph_clk(void) |
kadonotakashi | 0:8fdf9a60065b | 765 | { |
kadonotakashi | 0:8fdf9a60065b | 766 | PMC->PMC_PCDR0 = PMC_MASK_STATUS0; |
kadonotakashi | 0:8fdf9a60065b | 767 | while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0); |
kadonotakashi | 0:8fdf9a60065b | 768 | |
kadonotakashi | 0:8fdf9a60065b | 769 | #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ |
kadonotakashi | 0:8fdf9a60065b | 770 | || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 771 | PMC->PMC_PCDR1 = PMC_MASK_STATUS1; |
kadonotakashi | 0:8fdf9a60065b | 772 | while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0); |
kadonotakashi | 0:8fdf9a60065b | 773 | #endif |
kadonotakashi | 0:8fdf9a60065b | 774 | } |
kadonotakashi | 0:8fdf9a60065b | 775 | |
kadonotakashi | 0:8fdf9a60065b | 776 | /** |
kadonotakashi | 0:8fdf9a60065b | 777 | * \brief Check if the specified peripheral clock is enabled. |
kadonotakashi | 0:8fdf9a60065b | 778 | * |
kadonotakashi | 0:8fdf9a60065b | 779 | * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). |
kadonotakashi | 0:8fdf9a60065b | 780 | * |
kadonotakashi | 0:8fdf9a60065b | 781 | * \param ul_id Peripheral ID (ID_xxx). |
kadonotakashi | 0:8fdf9a60065b | 782 | * |
kadonotakashi | 0:8fdf9a60065b | 783 | * \retval 0 Peripheral clock is disabled or unknown. |
kadonotakashi | 0:8fdf9a60065b | 784 | * \retval 1 Peripheral clock is enabled. |
kadonotakashi | 0:8fdf9a60065b | 785 | */ |
kadonotakashi | 0:8fdf9a60065b | 786 | uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id) |
kadonotakashi | 0:8fdf9a60065b | 787 | { |
kadonotakashi | 0:8fdf9a60065b | 788 | if (ul_id > MAX_PERIPH_ID) { |
kadonotakashi | 0:8fdf9a60065b | 789 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 790 | } |
kadonotakashi | 0:8fdf9a60065b | 791 | |
kadonotakashi | 0:8fdf9a60065b | 792 | #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ |
kadonotakashi | 0:8fdf9a60065b | 793 | || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 794 | if (ul_id < 32) { |
kadonotakashi | 0:8fdf9a60065b | 795 | #endif |
kadonotakashi | 0:8fdf9a60065b | 796 | if ((PMC->PMC_PCSR0 & (1u << ul_id))) { |
kadonotakashi | 0:8fdf9a60065b | 797 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 798 | } else { |
kadonotakashi | 0:8fdf9a60065b | 799 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 800 | } |
kadonotakashi | 0:8fdf9a60065b | 801 | #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ |
kadonotakashi | 0:8fdf9a60065b | 802 | || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 803 | } else { |
kadonotakashi | 0:8fdf9a60065b | 804 | ul_id -= 32; |
kadonotakashi | 0:8fdf9a60065b | 805 | if ((PMC->PMC_PCSR1 & (1u << ul_id))) { |
kadonotakashi | 0:8fdf9a60065b | 806 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 807 | } else { |
kadonotakashi | 0:8fdf9a60065b | 808 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 809 | } |
kadonotakashi | 0:8fdf9a60065b | 810 | } |
kadonotakashi | 0:8fdf9a60065b | 811 | #endif |
kadonotakashi | 0:8fdf9a60065b | 812 | } |
kadonotakashi | 0:8fdf9a60065b | 813 | |
kadonotakashi | 0:8fdf9a60065b | 814 | /** |
kadonotakashi | 0:8fdf9a60065b | 815 | * \brief Set the prescaler for the specified programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 816 | * |
kadonotakashi | 0:8fdf9a60065b | 817 | * \param ul_id Peripheral ID. |
kadonotakashi | 0:8fdf9a60065b | 818 | * \param ul_pres Prescaler value. |
kadonotakashi | 0:8fdf9a60065b | 819 | */ |
kadonotakashi | 0:8fdf9a60065b | 820 | void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 821 | { |
kadonotakashi | 0:8fdf9a60065b | 822 | PMC->PMC_PCK[ul_id] = |
kadonotakashi | 0:8fdf9a60065b | 823 | (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 824 | while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) |
kadonotakashi | 0:8fdf9a60065b | 825 | && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); |
kadonotakashi | 0:8fdf9a60065b | 826 | } |
kadonotakashi | 0:8fdf9a60065b | 827 | |
kadonotakashi | 0:8fdf9a60065b | 828 | /** |
kadonotakashi | 0:8fdf9a60065b | 829 | * \brief Set the source oscillator for the specified programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 830 | * |
kadonotakashi | 0:8fdf9a60065b | 831 | * \param ul_id Peripheral ID. |
kadonotakashi | 0:8fdf9a60065b | 832 | * \param ul_source Source selection value. |
kadonotakashi | 0:8fdf9a60065b | 833 | */ |
kadonotakashi | 0:8fdf9a60065b | 834 | void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source) |
kadonotakashi | 0:8fdf9a60065b | 835 | { |
kadonotakashi | 0:8fdf9a60065b | 836 | PMC->PMC_PCK[ul_id] = |
kadonotakashi | 0:8fdf9a60065b | 837 | (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source; |
kadonotakashi | 0:8fdf9a60065b | 838 | while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) |
kadonotakashi | 0:8fdf9a60065b | 839 | && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); |
kadonotakashi | 0:8fdf9a60065b | 840 | } |
kadonotakashi | 0:8fdf9a60065b | 841 | |
kadonotakashi | 0:8fdf9a60065b | 842 | /** |
kadonotakashi | 0:8fdf9a60065b | 843 | * \brief Switch programmable clock source selection to slow clock. |
kadonotakashi | 0:8fdf9a60065b | 844 | * |
kadonotakashi | 0:8fdf9a60065b | 845 | * \param ul_id Id of the programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 846 | * \param ul_pres Programmable clock prescaler. |
kadonotakashi | 0:8fdf9a60065b | 847 | * |
kadonotakashi | 0:8fdf9a60065b | 848 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 849 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 850 | */ |
kadonotakashi | 0:8fdf9a60065b | 851 | uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 852 | { |
kadonotakashi | 0:8fdf9a60065b | 853 | uint32_t ul_timeout; |
kadonotakashi | 0:8fdf9a60065b | 854 | |
kadonotakashi | 0:8fdf9a60065b | 855 | PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 856 | for (ul_timeout = PMC_TIMEOUT; |
kadonotakashi | 0:8fdf9a60065b | 857 | !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 858 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 859 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 860 | } |
kadonotakashi | 0:8fdf9a60065b | 861 | } |
kadonotakashi | 0:8fdf9a60065b | 862 | |
kadonotakashi | 0:8fdf9a60065b | 863 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 864 | } |
kadonotakashi | 0:8fdf9a60065b | 865 | |
kadonotakashi | 0:8fdf9a60065b | 866 | /** |
kadonotakashi | 0:8fdf9a60065b | 867 | * \brief Switch programmable clock source selection to main clock. |
kadonotakashi | 0:8fdf9a60065b | 868 | * |
kadonotakashi | 0:8fdf9a60065b | 869 | * \param ul_id Id of the programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 870 | * \param ul_pres Programmable clock prescaler. |
kadonotakashi | 0:8fdf9a60065b | 871 | * |
kadonotakashi | 0:8fdf9a60065b | 872 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 873 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 874 | */ |
kadonotakashi | 0:8fdf9a60065b | 875 | uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 876 | { |
kadonotakashi | 0:8fdf9a60065b | 877 | uint32_t ul_timeout; |
kadonotakashi | 0:8fdf9a60065b | 878 | |
kadonotakashi | 0:8fdf9a60065b | 879 | PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 880 | for (ul_timeout = PMC_TIMEOUT; |
kadonotakashi | 0:8fdf9a60065b | 881 | !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 882 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 883 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 884 | } |
kadonotakashi | 0:8fdf9a60065b | 885 | } |
kadonotakashi | 0:8fdf9a60065b | 886 | |
kadonotakashi | 0:8fdf9a60065b | 887 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 888 | } |
kadonotakashi | 0:8fdf9a60065b | 889 | |
kadonotakashi | 0:8fdf9a60065b | 890 | /** |
kadonotakashi | 0:8fdf9a60065b | 891 | * \brief Switch programmable clock source selection to PLLA clock. |
kadonotakashi | 0:8fdf9a60065b | 892 | * |
kadonotakashi | 0:8fdf9a60065b | 893 | * \param ul_id Id of the programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 894 | * \param ul_pres Programmable clock prescaler. |
kadonotakashi | 0:8fdf9a60065b | 895 | * |
kadonotakashi | 0:8fdf9a60065b | 896 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 897 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 898 | */ |
kadonotakashi | 0:8fdf9a60065b | 899 | uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 900 | { |
kadonotakashi | 0:8fdf9a60065b | 901 | uint32_t ul_timeout; |
kadonotakashi | 0:8fdf9a60065b | 902 | |
kadonotakashi | 0:8fdf9a60065b | 903 | PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 904 | for (ul_timeout = PMC_TIMEOUT; |
kadonotakashi | 0:8fdf9a60065b | 905 | !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 906 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 907 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 908 | } |
kadonotakashi | 0:8fdf9a60065b | 909 | } |
kadonotakashi | 0:8fdf9a60065b | 910 | |
kadonotakashi | 0:8fdf9a60065b | 911 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 912 | } |
kadonotakashi | 0:8fdf9a60065b | 913 | |
kadonotakashi | 0:8fdf9a60065b | 914 | #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) |
kadonotakashi | 0:8fdf9a60065b | 915 | /** |
kadonotakashi | 0:8fdf9a60065b | 916 | * \brief Switch programmable clock source selection to PLLB clock. |
kadonotakashi | 0:8fdf9a60065b | 917 | * |
kadonotakashi | 0:8fdf9a60065b | 918 | * \param ul_id Id of the programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 919 | * \param ul_pres Programmable clock prescaler. |
kadonotakashi | 0:8fdf9a60065b | 920 | * |
kadonotakashi | 0:8fdf9a60065b | 921 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 922 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 923 | */ |
kadonotakashi | 0:8fdf9a60065b | 924 | uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 925 | { |
kadonotakashi | 0:8fdf9a60065b | 926 | uint32_t ul_timeout; |
kadonotakashi | 0:8fdf9a60065b | 927 | |
kadonotakashi | 0:8fdf9a60065b | 928 | PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 929 | for (ul_timeout = PMC_TIMEOUT; |
kadonotakashi | 0:8fdf9a60065b | 930 | !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); |
kadonotakashi | 0:8fdf9a60065b | 931 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 932 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 933 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 934 | } |
kadonotakashi | 0:8fdf9a60065b | 935 | } |
kadonotakashi | 0:8fdf9a60065b | 936 | |
kadonotakashi | 0:8fdf9a60065b | 937 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 938 | } |
kadonotakashi | 0:8fdf9a60065b | 939 | #endif |
kadonotakashi | 0:8fdf9a60065b | 940 | |
kadonotakashi | 0:8fdf9a60065b | 941 | #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 942 | /** |
kadonotakashi | 0:8fdf9a60065b | 943 | * \brief Switch programmable clock source selection to UPLL clock. |
kadonotakashi | 0:8fdf9a60065b | 944 | * |
kadonotakashi | 0:8fdf9a60065b | 945 | * \param ul_id Id of the programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 946 | * \param ul_pres Programmable clock prescaler. |
kadonotakashi | 0:8fdf9a60065b | 947 | * |
kadonotakashi | 0:8fdf9a60065b | 948 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 949 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 950 | */ |
kadonotakashi | 0:8fdf9a60065b | 951 | uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 952 | { |
kadonotakashi | 0:8fdf9a60065b | 953 | uint32_t ul_timeout; |
kadonotakashi | 0:8fdf9a60065b | 954 | |
kadonotakashi | 0:8fdf9a60065b | 955 | PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 956 | for (ul_timeout = PMC_TIMEOUT; |
kadonotakashi | 0:8fdf9a60065b | 957 | !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); |
kadonotakashi | 0:8fdf9a60065b | 958 | --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 959 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 960 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 961 | } |
kadonotakashi | 0:8fdf9a60065b | 962 | } |
kadonotakashi | 0:8fdf9a60065b | 963 | |
kadonotakashi | 0:8fdf9a60065b | 964 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 965 | } |
kadonotakashi | 0:8fdf9a60065b | 966 | #endif |
kadonotakashi | 0:8fdf9a60065b | 967 | |
kadonotakashi | 0:8fdf9a60065b | 968 | /** |
kadonotakashi | 0:8fdf9a60065b | 969 | * \brief Switch programmable clock source selection to mck. |
kadonotakashi | 0:8fdf9a60065b | 970 | * |
kadonotakashi | 0:8fdf9a60065b | 971 | * \param ul_id Id of the programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 972 | * \param ul_pres Programmable clock prescaler. |
kadonotakashi | 0:8fdf9a60065b | 973 | * |
kadonotakashi | 0:8fdf9a60065b | 974 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 975 | * \retval 1 Timeout error. |
kadonotakashi | 0:8fdf9a60065b | 976 | */ |
kadonotakashi | 0:8fdf9a60065b | 977 | uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 978 | { |
kadonotakashi | 0:8fdf9a60065b | 979 | uint32_t ul_timeout; |
kadonotakashi | 0:8fdf9a60065b | 980 | |
kadonotakashi | 0:8fdf9a60065b | 981 | PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres; |
kadonotakashi | 0:8fdf9a60065b | 982 | for (ul_timeout = PMC_TIMEOUT; |
kadonotakashi | 0:8fdf9a60065b | 983 | !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { |
kadonotakashi | 0:8fdf9a60065b | 984 | if (ul_timeout == 0) { |
kadonotakashi | 0:8fdf9a60065b | 985 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 986 | } |
kadonotakashi | 0:8fdf9a60065b | 987 | } |
kadonotakashi | 0:8fdf9a60065b | 988 | |
kadonotakashi | 0:8fdf9a60065b | 989 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 990 | } |
kadonotakashi | 0:8fdf9a60065b | 991 | |
kadonotakashi | 0:8fdf9a60065b | 992 | /** |
kadonotakashi | 0:8fdf9a60065b | 993 | * \brief Enable the specified programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 994 | * |
kadonotakashi | 0:8fdf9a60065b | 995 | * \param ul_id Id of the programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 996 | */ |
kadonotakashi | 0:8fdf9a60065b | 997 | void pmc_enable_pck(uint32_t ul_id) |
kadonotakashi | 0:8fdf9a60065b | 998 | { |
kadonotakashi | 0:8fdf9a60065b | 999 | PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id; |
kadonotakashi | 0:8fdf9a60065b | 1000 | } |
kadonotakashi | 0:8fdf9a60065b | 1001 | |
kadonotakashi | 0:8fdf9a60065b | 1002 | /** |
kadonotakashi | 0:8fdf9a60065b | 1003 | * \brief Disable the specified programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 1004 | * |
kadonotakashi | 0:8fdf9a60065b | 1005 | * \param ul_id Id of the programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 1006 | */ |
kadonotakashi | 0:8fdf9a60065b | 1007 | void pmc_disable_pck(uint32_t ul_id) |
kadonotakashi | 0:8fdf9a60065b | 1008 | { |
kadonotakashi | 0:8fdf9a60065b | 1009 | PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id; |
kadonotakashi | 0:8fdf9a60065b | 1010 | } |
kadonotakashi | 0:8fdf9a60065b | 1011 | |
kadonotakashi | 0:8fdf9a60065b | 1012 | /** |
kadonotakashi | 0:8fdf9a60065b | 1013 | * \brief Enable all programmable clocks. |
kadonotakashi | 0:8fdf9a60065b | 1014 | */ |
kadonotakashi | 0:8fdf9a60065b | 1015 | void pmc_enable_all_pck(void) |
kadonotakashi | 0:8fdf9a60065b | 1016 | { |
kadonotakashi | 0:8fdf9a60065b | 1017 | PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2; |
kadonotakashi | 0:8fdf9a60065b | 1018 | } |
kadonotakashi | 0:8fdf9a60065b | 1019 | |
kadonotakashi | 0:8fdf9a60065b | 1020 | /** |
kadonotakashi | 0:8fdf9a60065b | 1021 | * \brief Disable all programmable clocks. |
kadonotakashi | 0:8fdf9a60065b | 1022 | */ |
kadonotakashi | 0:8fdf9a60065b | 1023 | void pmc_disable_all_pck(void) |
kadonotakashi | 0:8fdf9a60065b | 1024 | { |
kadonotakashi | 0:8fdf9a60065b | 1025 | PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2; |
kadonotakashi | 0:8fdf9a60065b | 1026 | } |
kadonotakashi | 0:8fdf9a60065b | 1027 | |
kadonotakashi | 0:8fdf9a60065b | 1028 | /** |
kadonotakashi | 0:8fdf9a60065b | 1029 | * \brief Check if the specified programmable clock is enabled. |
kadonotakashi | 0:8fdf9a60065b | 1030 | * |
kadonotakashi | 0:8fdf9a60065b | 1031 | * \param ul_id Id of the programmable clock. |
kadonotakashi | 0:8fdf9a60065b | 1032 | * |
kadonotakashi | 0:8fdf9a60065b | 1033 | * \retval 0 Programmable clock is disabled or unknown. |
kadonotakashi | 0:8fdf9a60065b | 1034 | * \retval 1 Programmable clock is enabled. |
kadonotakashi | 0:8fdf9a60065b | 1035 | */ |
kadonotakashi | 0:8fdf9a60065b | 1036 | uint32_t pmc_is_pck_enabled(uint32_t ul_id) |
kadonotakashi | 0:8fdf9a60065b | 1037 | { |
kadonotakashi | 0:8fdf9a60065b | 1038 | if (ul_id > 2) { |
kadonotakashi | 0:8fdf9a60065b | 1039 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 1040 | } |
kadonotakashi | 0:8fdf9a60065b | 1041 | |
kadonotakashi | 0:8fdf9a60065b | 1042 | return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id)); |
kadonotakashi | 0:8fdf9a60065b | 1043 | } |
kadonotakashi | 0:8fdf9a60065b | 1044 | |
kadonotakashi | 0:8fdf9a60065b | 1045 | #if (SAM4C || SAM4CM || SAM4CP) |
kadonotakashi | 0:8fdf9a60065b | 1046 | /** |
kadonotakashi | 0:8fdf9a60065b | 1047 | * \brief Enable Coprocessor Clocks. |
kadonotakashi | 0:8fdf9a60065b | 1048 | */ |
kadonotakashi | 0:8fdf9a60065b | 1049 | void pmc_enable_cpck(void) |
kadonotakashi | 0:8fdf9a60065b | 1050 | { |
kadonotakashi | 0:8fdf9a60065b | 1051 | PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD; |
kadonotakashi | 0:8fdf9a60065b | 1052 | } |
kadonotakashi | 0:8fdf9a60065b | 1053 | |
kadonotakashi | 0:8fdf9a60065b | 1054 | /** |
kadonotakashi | 0:8fdf9a60065b | 1055 | * \brief Disable Coprocessor Clocks. |
kadonotakashi | 0:8fdf9a60065b | 1056 | */ |
kadonotakashi | 0:8fdf9a60065b | 1057 | void pmc_disable_cpck(void) |
kadonotakashi | 0:8fdf9a60065b | 1058 | { |
kadonotakashi | 0:8fdf9a60065b | 1059 | PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD; |
kadonotakashi | 0:8fdf9a60065b | 1060 | } |
kadonotakashi | 0:8fdf9a60065b | 1061 | |
kadonotakashi | 0:8fdf9a60065b | 1062 | /** |
kadonotakashi | 0:8fdf9a60065b | 1063 | * \brief Check if the Coprocessor Clocks is enabled. |
kadonotakashi | 0:8fdf9a60065b | 1064 | * |
kadonotakashi | 0:8fdf9a60065b | 1065 | * \retval 0 Coprocessor Clocks is disabled. |
kadonotakashi | 0:8fdf9a60065b | 1066 | * \retval 1 Coprocessor Clocks is enabled. |
kadonotakashi | 0:8fdf9a60065b | 1067 | */ |
kadonotakashi | 0:8fdf9a60065b | 1068 | bool pmc_is_cpck_enabled(void) |
kadonotakashi | 0:8fdf9a60065b | 1069 | { |
kadonotakashi | 0:8fdf9a60065b | 1070 | if(PMC->PMC_SCSR & PMC_SCSR_CPCK) { |
kadonotakashi | 0:8fdf9a60065b | 1071 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 1072 | } else { |
kadonotakashi | 0:8fdf9a60065b | 1073 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 1074 | } |
kadonotakashi | 0:8fdf9a60065b | 1075 | } |
kadonotakashi | 0:8fdf9a60065b | 1076 | |
kadonotakashi | 0:8fdf9a60065b | 1077 | /** |
kadonotakashi | 0:8fdf9a60065b | 1078 | * \brief Enable Coprocessor Bus Master Clocks. |
kadonotakashi | 0:8fdf9a60065b | 1079 | */ |
kadonotakashi | 0:8fdf9a60065b | 1080 | void pmc_enable_cpbmck(void) |
kadonotakashi | 0:8fdf9a60065b | 1081 | { |
kadonotakashi | 0:8fdf9a60065b | 1082 | PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD; |
kadonotakashi | 0:8fdf9a60065b | 1083 | } |
kadonotakashi | 0:8fdf9a60065b | 1084 | |
kadonotakashi | 0:8fdf9a60065b | 1085 | /** |
kadonotakashi | 0:8fdf9a60065b | 1086 | * \brief Disable Coprocessor Bus Master Clocks. |
kadonotakashi | 0:8fdf9a60065b | 1087 | */ |
kadonotakashi | 0:8fdf9a60065b | 1088 | void pmc_disable_cpbmck(void) |
kadonotakashi | 0:8fdf9a60065b | 1089 | { |
kadonotakashi | 0:8fdf9a60065b | 1090 | PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD; |
kadonotakashi | 0:8fdf9a60065b | 1091 | } |
kadonotakashi | 0:8fdf9a60065b | 1092 | |
kadonotakashi | 0:8fdf9a60065b | 1093 | /** |
kadonotakashi | 0:8fdf9a60065b | 1094 | * \brief Check if the Coprocessor Bus Master Clocks is enabled. |
kadonotakashi | 0:8fdf9a60065b | 1095 | * |
kadonotakashi | 0:8fdf9a60065b | 1096 | * \retval 0 Coprocessor Bus Master Clocks is disabled. |
kadonotakashi | 0:8fdf9a60065b | 1097 | * \retval 1 Coprocessor Bus Master Clocks is enabled. |
kadonotakashi | 0:8fdf9a60065b | 1098 | */ |
kadonotakashi | 0:8fdf9a60065b | 1099 | bool pmc_is_cpbmck_enabled(void) |
kadonotakashi | 0:8fdf9a60065b | 1100 | { |
kadonotakashi | 0:8fdf9a60065b | 1101 | if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) { |
kadonotakashi | 0:8fdf9a60065b | 1102 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 1103 | } else { |
kadonotakashi | 0:8fdf9a60065b | 1104 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 1105 | } |
kadonotakashi | 0:8fdf9a60065b | 1106 | } |
kadonotakashi | 0:8fdf9a60065b | 1107 | |
kadonotakashi | 0:8fdf9a60065b | 1108 | /** |
kadonotakashi | 0:8fdf9a60065b | 1109 | * \brief Set the prescaler for the Coprocessor Master Clock. |
kadonotakashi | 0:8fdf9a60065b | 1110 | * |
kadonotakashi | 0:8fdf9a60065b | 1111 | * \param ul_pres Prescaler value. |
kadonotakashi | 0:8fdf9a60065b | 1112 | */ |
kadonotakashi | 0:8fdf9a60065b | 1113 | void pmc_cpck_set_prescaler(uint32_t ul_pres) |
kadonotakashi | 0:8fdf9a60065b | 1114 | { |
kadonotakashi | 0:8fdf9a60065b | 1115 | PMC->PMC_MCKR = |
kadonotakashi | 0:8fdf9a60065b | 1116 | (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres); |
kadonotakashi | 0:8fdf9a60065b | 1117 | } |
kadonotakashi | 0:8fdf9a60065b | 1118 | |
kadonotakashi | 0:8fdf9a60065b | 1119 | /** |
kadonotakashi | 0:8fdf9a60065b | 1120 | * \brief Set the source for the Coprocessor Master Clock. |
kadonotakashi | 0:8fdf9a60065b | 1121 | * |
kadonotakashi | 0:8fdf9a60065b | 1122 | * \param ul_source Source selection value. |
kadonotakashi | 0:8fdf9a60065b | 1123 | */ |
kadonotakashi | 0:8fdf9a60065b | 1124 | void pmc_cpck_set_source(uint32_t ul_source) |
kadonotakashi | 0:8fdf9a60065b | 1125 | { |
kadonotakashi | 0:8fdf9a60065b | 1126 | PMC->PMC_MCKR = |
kadonotakashi | 0:8fdf9a60065b | 1127 | (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source; |
kadonotakashi | 0:8fdf9a60065b | 1128 | } |
kadonotakashi | 0:8fdf9a60065b | 1129 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1130 | |
kadonotakashi | 0:8fdf9a60065b | 1131 | #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1132 | /** |
kadonotakashi | 0:8fdf9a60065b | 1133 | * \brief Switch UDP (USB) clock source selection to PLLA clock. |
kadonotakashi | 0:8fdf9a60065b | 1134 | * |
kadonotakashi | 0:8fdf9a60065b | 1135 | * \param ul_usbdiv Clock divisor. |
kadonotakashi | 0:8fdf9a60065b | 1136 | */ |
kadonotakashi | 0:8fdf9a60065b | 1137 | void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv) |
kadonotakashi | 0:8fdf9a60065b | 1138 | { |
kadonotakashi | 0:8fdf9a60065b | 1139 | PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); |
kadonotakashi | 0:8fdf9a60065b | 1140 | } |
kadonotakashi | 0:8fdf9a60065b | 1141 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1142 | |
kadonotakashi | 0:8fdf9a60065b | 1143 | #if (SAM3S || SAM4S || SAMG55) |
kadonotakashi | 0:8fdf9a60065b | 1144 | /** |
kadonotakashi | 0:8fdf9a60065b | 1145 | * \brief Switch UDP (USB) clock source selection to PLLB clock. |
kadonotakashi | 0:8fdf9a60065b | 1146 | * |
kadonotakashi | 0:8fdf9a60065b | 1147 | * \param ul_usbdiv Clock divisor. |
kadonotakashi | 0:8fdf9a60065b | 1148 | */ |
kadonotakashi | 0:8fdf9a60065b | 1149 | void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv) |
kadonotakashi | 0:8fdf9a60065b | 1150 | { |
kadonotakashi | 0:8fdf9a60065b | 1151 | PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; |
kadonotakashi | 0:8fdf9a60065b | 1152 | } |
kadonotakashi | 0:8fdf9a60065b | 1153 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1154 | |
kadonotakashi | 0:8fdf9a60065b | 1155 | #if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1156 | /** |
kadonotakashi | 0:8fdf9a60065b | 1157 | * \brief Switch UDP (USB) clock source selection to UPLL clock. |
kadonotakashi | 0:8fdf9a60065b | 1158 | * |
kadonotakashi | 0:8fdf9a60065b | 1159 | * \param ul_usbdiv Clock divisor. |
kadonotakashi | 0:8fdf9a60065b | 1160 | */ |
kadonotakashi | 0:8fdf9a60065b | 1161 | void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv) |
kadonotakashi | 0:8fdf9a60065b | 1162 | { |
kadonotakashi | 0:8fdf9a60065b | 1163 | PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv); |
kadonotakashi | 0:8fdf9a60065b | 1164 | } |
kadonotakashi | 0:8fdf9a60065b | 1165 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1166 | |
kadonotakashi | 0:8fdf9a60065b | 1167 | #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1168 | /** |
kadonotakashi | 0:8fdf9a60065b | 1169 | * \brief Enable UDP (USB) clock. |
kadonotakashi | 0:8fdf9a60065b | 1170 | */ |
kadonotakashi | 0:8fdf9a60065b | 1171 | void pmc_enable_udpck(void) |
kadonotakashi | 0:8fdf9a60065b | 1172 | { |
kadonotakashi | 0:8fdf9a60065b | 1173 | #if (SAM3S || SAM4S || SAM4E || SAMG55) |
kadonotakashi | 0:8fdf9a60065b | 1174 | PMC->PMC_SCER = PMC_SCER_UDP; |
kadonotakashi | 0:8fdf9a60065b | 1175 | #elif (SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1176 | PMC->PMC_SCER = PMC_SCER_USBCLK; |
kadonotakashi | 0:8fdf9a60065b | 1177 | #else |
kadonotakashi | 0:8fdf9a60065b | 1178 | PMC->PMC_SCER = PMC_SCER_UOTGCLK; |
kadonotakashi | 0:8fdf9a60065b | 1179 | # endif |
kadonotakashi | 0:8fdf9a60065b | 1180 | } |
kadonotakashi | 0:8fdf9a60065b | 1181 | |
kadonotakashi | 0:8fdf9a60065b | 1182 | /** |
kadonotakashi | 0:8fdf9a60065b | 1183 | * \brief Disable UDP (USB) clock. |
kadonotakashi | 0:8fdf9a60065b | 1184 | */ |
kadonotakashi | 0:8fdf9a60065b | 1185 | void pmc_disable_udpck(void) |
kadonotakashi | 0:8fdf9a60065b | 1186 | { |
kadonotakashi | 0:8fdf9a60065b | 1187 | #if (SAM3S || SAM4S || SAM4E || SAMG55) |
kadonotakashi | 0:8fdf9a60065b | 1188 | PMC->PMC_SCDR = PMC_SCDR_UDP; |
kadonotakashi | 0:8fdf9a60065b | 1189 | #elif (SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1190 | PMC->PMC_SCDR = PMC_SCDR_USBCLK; |
kadonotakashi | 0:8fdf9a60065b | 1191 | #else |
kadonotakashi | 0:8fdf9a60065b | 1192 | PMC->PMC_SCDR = PMC_SCDR_UOTGCLK; |
kadonotakashi | 0:8fdf9a60065b | 1193 | # endif |
kadonotakashi | 0:8fdf9a60065b | 1194 | } |
kadonotakashi | 0:8fdf9a60065b | 1195 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1196 | |
kadonotakashi | 0:8fdf9a60065b | 1197 | #if SAMG55 |
kadonotakashi | 0:8fdf9a60065b | 1198 | /** |
kadonotakashi | 0:8fdf9a60065b | 1199 | * \brief Switch UHP (USB) clock source selection to PLLA clock. |
kadonotakashi | 0:8fdf9a60065b | 1200 | * |
kadonotakashi | 0:8fdf9a60065b | 1201 | * \param ul_usbdiv Clock divisor. |
kadonotakashi | 0:8fdf9a60065b | 1202 | */ |
kadonotakashi | 0:8fdf9a60065b | 1203 | void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv) |
kadonotakashi | 0:8fdf9a60065b | 1204 | { |
kadonotakashi | 0:8fdf9a60065b | 1205 | PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); |
kadonotakashi | 0:8fdf9a60065b | 1206 | } |
kadonotakashi | 0:8fdf9a60065b | 1207 | |
kadonotakashi | 0:8fdf9a60065b | 1208 | /** |
kadonotakashi | 0:8fdf9a60065b | 1209 | * \brief Switch UHP (USB) clock source selection to PLLB clock. |
kadonotakashi | 0:8fdf9a60065b | 1210 | * |
kadonotakashi | 0:8fdf9a60065b | 1211 | * \param ul_usbdiv Clock divisor. |
kadonotakashi | 0:8fdf9a60065b | 1212 | */ |
kadonotakashi | 0:8fdf9a60065b | 1213 | void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv) |
kadonotakashi | 0:8fdf9a60065b | 1214 | { |
kadonotakashi | 0:8fdf9a60065b | 1215 | PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; |
kadonotakashi | 0:8fdf9a60065b | 1216 | } |
kadonotakashi | 0:8fdf9a60065b | 1217 | |
kadonotakashi | 0:8fdf9a60065b | 1218 | /** |
kadonotakashi | 0:8fdf9a60065b | 1219 | * \brief Enable UHP (USB) clock. |
kadonotakashi | 0:8fdf9a60065b | 1220 | */ |
kadonotakashi | 0:8fdf9a60065b | 1221 | void pmc_enable_uhpck(void) |
kadonotakashi | 0:8fdf9a60065b | 1222 | { |
kadonotakashi | 0:8fdf9a60065b | 1223 | PMC->PMC_SCER = PMC_SCER_UHP; |
kadonotakashi | 0:8fdf9a60065b | 1224 | } |
kadonotakashi | 0:8fdf9a60065b | 1225 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1226 | |
kadonotakashi | 0:8fdf9a60065b | 1227 | /** |
kadonotakashi | 0:8fdf9a60065b | 1228 | * \brief Enable PMC interrupts. |
kadonotakashi | 0:8fdf9a60065b | 1229 | * |
kadonotakashi | 0:8fdf9a60065b | 1230 | * \param ul_sources Interrupt sources bit map. |
kadonotakashi | 0:8fdf9a60065b | 1231 | */ |
kadonotakashi | 0:8fdf9a60065b | 1232 | void pmc_enable_interrupt(uint32_t ul_sources) |
kadonotakashi | 0:8fdf9a60065b | 1233 | { |
kadonotakashi | 0:8fdf9a60065b | 1234 | PMC->PMC_IER = ul_sources; |
kadonotakashi | 0:8fdf9a60065b | 1235 | } |
kadonotakashi | 0:8fdf9a60065b | 1236 | |
kadonotakashi | 0:8fdf9a60065b | 1237 | /** |
kadonotakashi | 0:8fdf9a60065b | 1238 | * \brief Disable PMC interrupts. |
kadonotakashi | 0:8fdf9a60065b | 1239 | * |
kadonotakashi | 0:8fdf9a60065b | 1240 | * \param ul_sources Interrupt sources bit map. |
kadonotakashi | 0:8fdf9a60065b | 1241 | */ |
kadonotakashi | 0:8fdf9a60065b | 1242 | void pmc_disable_interrupt(uint32_t ul_sources) |
kadonotakashi | 0:8fdf9a60065b | 1243 | { |
kadonotakashi | 0:8fdf9a60065b | 1244 | PMC->PMC_IDR = ul_sources; |
kadonotakashi | 0:8fdf9a60065b | 1245 | } |
kadonotakashi | 0:8fdf9a60065b | 1246 | |
kadonotakashi | 0:8fdf9a60065b | 1247 | /** |
kadonotakashi | 0:8fdf9a60065b | 1248 | * \brief Get PMC interrupt mask. |
kadonotakashi | 0:8fdf9a60065b | 1249 | * |
kadonotakashi | 0:8fdf9a60065b | 1250 | * \return The interrupt mask value. |
kadonotakashi | 0:8fdf9a60065b | 1251 | */ |
kadonotakashi | 0:8fdf9a60065b | 1252 | uint32_t pmc_get_interrupt_mask(void) |
kadonotakashi | 0:8fdf9a60065b | 1253 | { |
kadonotakashi | 0:8fdf9a60065b | 1254 | return PMC->PMC_IMR; |
kadonotakashi | 0:8fdf9a60065b | 1255 | } |
kadonotakashi | 0:8fdf9a60065b | 1256 | |
kadonotakashi | 0:8fdf9a60065b | 1257 | /** |
kadonotakashi | 0:8fdf9a60065b | 1258 | * \brief Get current status. |
kadonotakashi | 0:8fdf9a60065b | 1259 | * |
kadonotakashi | 0:8fdf9a60065b | 1260 | * \return The current PMC status. |
kadonotakashi | 0:8fdf9a60065b | 1261 | */ |
kadonotakashi | 0:8fdf9a60065b | 1262 | uint32_t pmc_get_status(void) |
kadonotakashi | 0:8fdf9a60065b | 1263 | { |
kadonotakashi | 0:8fdf9a60065b | 1264 | return PMC->PMC_SR; |
kadonotakashi | 0:8fdf9a60065b | 1265 | } |
kadonotakashi | 0:8fdf9a60065b | 1266 | |
kadonotakashi | 0:8fdf9a60065b | 1267 | /** |
kadonotakashi | 0:8fdf9a60065b | 1268 | * \brief Set the wake-up inputs for fast startup mode registers |
kadonotakashi | 0:8fdf9a60065b | 1269 | * (event generation). |
kadonotakashi | 0:8fdf9a60065b | 1270 | * |
kadonotakashi | 0:8fdf9a60065b | 1271 | * \param ul_inputs Wake up inputs to enable. |
kadonotakashi | 0:8fdf9a60065b | 1272 | */ |
kadonotakashi | 0:8fdf9a60065b | 1273 | void pmc_set_fast_startup_input(uint32_t ul_inputs) |
kadonotakashi | 0:8fdf9a60065b | 1274 | { |
kadonotakashi | 0:8fdf9a60065b | 1275 | ul_inputs &= PMC_FAST_STARTUP_Msk; |
kadonotakashi | 0:8fdf9a60065b | 1276 | PMC->PMC_FSMR |= ul_inputs; |
kadonotakashi | 0:8fdf9a60065b | 1277 | } |
kadonotakashi | 0:8fdf9a60065b | 1278 | |
kadonotakashi | 0:8fdf9a60065b | 1279 | /** |
kadonotakashi | 0:8fdf9a60065b | 1280 | * \brief Clear the wake-up inputs for fast startup mode registers |
kadonotakashi | 0:8fdf9a60065b | 1281 | * (remove event generation). |
kadonotakashi | 0:8fdf9a60065b | 1282 | * |
kadonotakashi | 0:8fdf9a60065b | 1283 | * \param ul_inputs Wake up inputs to disable. |
kadonotakashi | 0:8fdf9a60065b | 1284 | */ |
kadonotakashi | 0:8fdf9a60065b | 1285 | void pmc_clr_fast_startup_input(uint32_t ul_inputs) |
kadonotakashi | 0:8fdf9a60065b | 1286 | { |
kadonotakashi | 0:8fdf9a60065b | 1287 | ul_inputs &= PMC_FAST_STARTUP_Msk; |
kadonotakashi | 0:8fdf9a60065b | 1288 | PMC->PMC_FSMR &= ~ul_inputs; |
kadonotakashi | 0:8fdf9a60065b | 1289 | } |
kadonotakashi | 0:8fdf9a60065b | 1290 | |
kadonotakashi | 0:8fdf9a60065b | 1291 | #if (SAM4C || SAM4CM || SAM4CP) |
kadonotakashi | 0:8fdf9a60065b | 1292 | /** |
kadonotakashi | 0:8fdf9a60065b | 1293 | * \brief Set the wake-up inputs of coprocessor for fast startup mode registers |
kadonotakashi | 0:8fdf9a60065b | 1294 | * (event generation). |
kadonotakashi | 0:8fdf9a60065b | 1295 | * |
kadonotakashi | 0:8fdf9a60065b | 1296 | * \param ul_inputs Wake up inputs to enable. |
kadonotakashi | 0:8fdf9a60065b | 1297 | */ |
kadonotakashi | 0:8fdf9a60065b | 1298 | void pmc_cp_set_fast_startup_input(uint32_t ul_inputs) |
kadonotakashi | 0:8fdf9a60065b | 1299 | { |
kadonotakashi | 0:8fdf9a60065b | 1300 | ul_inputs &= PMC_FAST_STARTUP_Msk; |
kadonotakashi | 0:8fdf9a60065b | 1301 | PMC->PMC_CPFSMR |= ul_inputs; |
kadonotakashi | 0:8fdf9a60065b | 1302 | } |
kadonotakashi | 0:8fdf9a60065b | 1303 | |
kadonotakashi | 0:8fdf9a60065b | 1304 | /** |
kadonotakashi | 0:8fdf9a60065b | 1305 | * \brief Clear the wake-up inputs of coprocessor for fast startup mode registers |
kadonotakashi | 0:8fdf9a60065b | 1306 | * (remove event generation). |
kadonotakashi | 0:8fdf9a60065b | 1307 | * |
kadonotakashi | 0:8fdf9a60065b | 1308 | * \param ul_inputs Wake up inputs to disable. |
kadonotakashi | 0:8fdf9a60065b | 1309 | */ |
kadonotakashi | 0:8fdf9a60065b | 1310 | void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs) |
kadonotakashi | 0:8fdf9a60065b | 1311 | { |
kadonotakashi | 0:8fdf9a60065b | 1312 | ul_inputs &= PMC_FAST_STARTUP_Msk; |
kadonotakashi | 0:8fdf9a60065b | 1313 | PMC->PMC_CPFSMR &= ~ul_inputs; |
kadonotakashi | 0:8fdf9a60065b | 1314 | } |
kadonotakashi | 0:8fdf9a60065b | 1315 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1316 | |
kadonotakashi | 0:8fdf9a60065b | 1317 | #if (!(SAMG51 || SAMG53 || SAMG54)) |
kadonotakashi | 0:8fdf9a60065b | 1318 | /** |
kadonotakashi | 0:8fdf9a60065b | 1319 | * \brief Enable Sleep Mode. |
kadonotakashi | 0:8fdf9a60065b | 1320 | * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0) |
kadonotakashi | 0:8fdf9a60065b | 1321 | * |
kadonotakashi | 0:8fdf9a60065b | 1322 | * \param uc_type 0 for wait for interrupt, 1 for wait for event. |
kadonotakashi | 0:8fdf9a60065b | 1323 | * \note For SAM4S, SAM4C, SAM4CM, SAM4CP, SAMV71 and SAM4E series, |
kadonotakashi | 0:8fdf9a60065b | 1324 | * since only WFI is effective, uc_type = 1 will be treated as uc_type = 0. |
kadonotakashi | 0:8fdf9a60065b | 1325 | */ |
kadonotakashi | 0:8fdf9a60065b | 1326 | void pmc_enable_sleepmode(uint8_t uc_type) |
kadonotakashi | 0:8fdf9a60065b | 1327 | { |
kadonotakashi | 0:8fdf9a60065b | 1328 | #if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1329 | PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode |
kadonotakashi | 0:8fdf9a60065b | 1330 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1331 | SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep |
kadonotakashi | 0:8fdf9a60065b | 1332 | |
kadonotakashi | 0:8fdf9a60065b | 1333 | #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1334 | UNUSED(uc_type); |
kadonotakashi | 0:8fdf9a60065b | 1335 | __WFI(); |
kadonotakashi | 0:8fdf9a60065b | 1336 | #else |
kadonotakashi | 0:8fdf9a60065b | 1337 | if (uc_type == 0) { |
kadonotakashi | 0:8fdf9a60065b | 1338 | __WFI(); |
kadonotakashi | 0:8fdf9a60065b | 1339 | } else { |
kadonotakashi | 0:8fdf9a60065b | 1340 | __WFE(); |
kadonotakashi | 0:8fdf9a60065b | 1341 | } |
kadonotakashi | 0:8fdf9a60065b | 1342 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1343 | } |
kadonotakashi | 0:8fdf9a60065b | 1344 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1345 | |
kadonotakashi | 0:8fdf9a60065b | 1346 | #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1347 | static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN; |
kadonotakashi | 0:8fdf9a60065b | 1348 | /** |
kadonotakashi | 0:8fdf9a60065b | 1349 | * \brief Set the embedded flash state in wait mode |
kadonotakashi | 0:8fdf9a60065b | 1350 | * |
kadonotakashi | 0:8fdf9a60065b | 1351 | * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode, |
kadonotakashi | 0:8fdf9a60065b | 1352 | * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode. |
kadonotakashi | 0:8fdf9a60065b | 1353 | */ |
kadonotakashi | 0:8fdf9a60065b | 1354 | void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state) |
kadonotakashi | 0:8fdf9a60065b | 1355 | { |
kadonotakashi | 0:8fdf9a60065b | 1356 | ul_flash_in_wait_mode = ul_flash_state; |
kadonotakashi | 0:8fdf9a60065b | 1357 | } |
kadonotakashi | 0:8fdf9a60065b | 1358 | |
kadonotakashi | 0:8fdf9a60065b | 1359 | /** |
kadonotakashi | 0:8fdf9a60065b | 1360 | * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + FLPM |
kadonotakashi | 0:8fdf9a60065b | 1361 | * |
kadonotakashi | 0:8fdf9a60065b | 1362 | * \note In this function, FLPM will retain, WAITMODE bit will be set, |
kadonotakashi | 0:8fdf9a60065b | 1363 | * Generally, this function will be called by pmc_sleep() in order to |
kadonotakashi | 0:8fdf9a60065b | 1364 | * complete all sequence entering wait mode. |
kadonotakashi | 0:8fdf9a60065b | 1365 | * See \ref pmc_sleep() for entering different sleep modes. |
kadonotakashi | 0:8fdf9a60065b | 1366 | */ |
kadonotakashi | 0:8fdf9a60065b | 1367 | void pmc_enable_waitmode(void) |
kadonotakashi | 0:8fdf9a60065b | 1368 | { |
kadonotakashi | 0:8fdf9a60065b | 1369 | uint32_t i; |
kadonotakashi | 0:8fdf9a60065b | 1370 | |
kadonotakashi | 0:8fdf9a60065b | 1371 | /* Flash in wait mode */ |
kadonotakashi | 0:8fdf9a60065b | 1372 | i = PMC->PMC_FSMR; |
kadonotakashi | 0:8fdf9a60065b | 1373 | i &= ~PMC_FSMR_FLPM_Msk; |
kadonotakashi | 0:8fdf9a60065b | 1374 | i |= ul_flash_in_wait_mode; |
kadonotakashi | 0:8fdf9a60065b | 1375 | PMC->PMC_FSMR = i; |
kadonotakashi | 0:8fdf9a60065b | 1376 | |
kadonotakashi | 0:8fdf9a60065b | 1377 | /* Set the WAITMODE bit = 1 */ |
kadonotakashi | 0:8fdf9a60065b | 1378 | PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE; |
kadonotakashi | 0:8fdf9a60065b | 1379 | |
kadonotakashi | 0:8fdf9a60065b | 1380 | /* Waiting for Master Clock Ready MCKRDY = 1 */ |
kadonotakashi | 0:8fdf9a60065b | 1381 | while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); |
kadonotakashi | 0:8fdf9a60065b | 1382 | |
kadonotakashi | 0:8fdf9a60065b | 1383 | /* Waiting for MOSCRCEN bit cleared is strongly recommended |
kadonotakashi | 0:8fdf9a60065b | 1384 | * to ensure that the core will not execute undesired instructions |
kadonotakashi | 0:8fdf9a60065b | 1385 | */ |
kadonotakashi | 0:8fdf9a60065b | 1386 | for (i = 0; i < 500; i++) { |
kadonotakashi | 0:8fdf9a60065b | 1387 | __NOP(); |
kadonotakashi | 0:8fdf9a60065b | 1388 | } |
kadonotakashi | 0:8fdf9a60065b | 1389 | while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); |
kadonotakashi | 0:8fdf9a60065b | 1390 | |
kadonotakashi | 0:8fdf9a60065b | 1391 | #if (!SAMG) |
kadonotakashi | 0:8fdf9a60065b | 1392 | /* Restore Flash in idle mode */ |
kadonotakashi | 0:8fdf9a60065b | 1393 | i = PMC->PMC_FSMR; |
kadonotakashi | 0:8fdf9a60065b | 1394 | i &= ~PMC_FSMR_FLPM_Msk; |
kadonotakashi | 0:8fdf9a60065b | 1395 | i |= PMC_WAIT_MODE_FLASH_IDLE; |
kadonotakashi | 0:8fdf9a60065b | 1396 | PMC->PMC_FSMR = i; |
kadonotakashi | 0:8fdf9a60065b | 1397 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1398 | } |
kadonotakashi | 0:8fdf9a60065b | 1399 | #else |
kadonotakashi | 0:8fdf9a60065b | 1400 | /** |
kadonotakashi | 0:8fdf9a60065b | 1401 | * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) + |
kadonotakashi | 0:8fdf9a60065b | 1402 | * (LPM bit = 1) |
kadonotakashi | 0:8fdf9a60065b | 1403 | */ |
kadonotakashi | 0:8fdf9a60065b | 1404 | void pmc_enable_waitmode(void) |
kadonotakashi | 0:8fdf9a60065b | 1405 | { |
kadonotakashi | 0:8fdf9a60065b | 1406 | uint32_t i; |
kadonotakashi | 0:8fdf9a60065b | 1407 | |
kadonotakashi | 0:8fdf9a60065b | 1408 | PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */ |
kadonotakashi | 0:8fdf9a60065b | 1409 | SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */ |
kadonotakashi | 0:8fdf9a60065b | 1410 | |
kadonotakashi | 0:8fdf9a60065b | 1411 | __WFE(); |
kadonotakashi | 0:8fdf9a60065b | 1412 | |
kadonotakashi | 0:8fdf9a60065b | 1413 | /* Waiting for MOSCRCEN bit cleared is strongly recommended |
kadonotakashi | 0:8fdf9a60065b | 1414 | * to ensure that the core will not execute undesired instructions |
kadonotakashi | 0:8fdf9a60065b | 1415 | */ |
kadonotakashi | 0:8fdf9a60065b | 1416 | for (i = 0; i < 500; i++) { |
kadonotakashi | 0:8fdf9a60065b | 1417 | __NOP(); |
kadonotakashi | 0:8fdf9a60065b | 1418 | } |
kadonotakashi | 0:8fdf9a60065b | 1419 | while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); |
kadonotakashi | 0:8fdf9a60065b | 1420 | |
kadonotakashi | 0:8fdf9a60065b | 1421 | } |
kadonotakashi | 0:8fdf9a60065b | 1422 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1423 | |
kadonotakashi | 0:8fdf9a60065b | 1424 | #if (!(SAMG51 || SAMG53 || SAMG54)) |
kadonotakashi | 0:8fdf9a60065b | 1425 | /** |
kadonotakashi | 0:8fdf9a60065b | 1426 | * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) + |
kadonotakashi | 0:8fdf9a60065b | 1427 | * (SLEEPDEEP bit = 1) |
kadonotakashi | 0:8fdf9a60065b | 1428 | */ |
kadonotakashi | 0:8fdf9a60065b | 1429 | void pmc_enable_backupmode(void) |
kadonotakashi | 0:8fdf9a60065b | 1430 | { |
kadonotakashi | 0:8fdf9a60065b | 1431 | #if (SAM4C || SAM4CM || SAM4CP) |
kadonotakashi | 0:8fdf9a60065b | 1432 | uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk); |
kadonotakashi | 0:8fdf9a60065b | 1433 | SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD; |
kadonotakashi | 0:8fdf9a60065b | 1434 | while (SUPC->SUPC_SR & SUPC_SR_BUPPORS); |
kadonotakashi | 0:8fdf9a60065b | 1435 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1436 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
kadonotakashi | 0:8fdf9a60065b | 1437 | #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1438 | SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG; |
kadonotakashi | 0:8fdf9a60065b | 1439 | __WFE(); |
kadonotakashi | 0:8fdf9a60065b | 1440 | __WFI(); |
kadonotakashi | 0:8fdf9a60065b | 1441 | #else |
kadonotakashi | 0:8fdf9a60065b | 1442 | __WFE(); |
kadonotakashi | 0:8fdf9a60065b | 1443 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1444 | } |
kadonotakashi | 0:8fdf9a60065b | 1445 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1446 | |
kadonotakashi | 0:8fdf9a60065b | 1447 | /** |
kadonotakashi | 0:8fdf9a60065b | 1448 | * \brief Enable Clock Failure Detector. |
kadonotakashi | 0:8fdf9a60065b | 1449 | */ |
kadonotakashi | 0:8fdf9a60065b | 1450 | void pmc_enable_clock_failure_detector(void) |
kadonotakashi | 0:8fdf9a60065b | 1451 | { |
kadonotakashi | 0:8fdf9a60065b | 1452 | uint32_t ul_reg = PMC->CKGR_MOR; |
kadonotakashi | 0:8fdf9a60065b | 1453 | |
kadonotakashi | 0:8fdf9a60065b | 1454 | PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg; |
kadonotakashi | 0:8fdf9a60065b | 1455 | } |
kadonotakashi | 0:8fdf9a60065b | 1456 | |
kadonotakashi | 0:8fdf9a60065b | 1457 | /** |
kadonotakashi | 0:8fdf9a60065b | 1458 | * \brief Disable Clock Failure Detector. |
kadonotakashi | 0:8fdf9a60065b | 1459 | */ |
kadonotakashi | 0:8fdf9a60065b | 1460 | void pmc_disable_clock_failure_detector(void) |
kadonotakashi | 0:8fdf9a60065b | 1461 | { |
kadonotakashi | 0:8fdf9a60065b | 1462 | uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN); |
kadonotakashi | 0:8fdf9a60065b | 1463 | |
kadonotakashi | 0:8fdf9a60065b | 1464 | PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg; |
kadonotakashi | 0:8fdf9a60065b | 1465 | } |
kadonotakashi | 0:8fdf9a60065b | 1466 | |
kadonotakashi | 0:8fdf9a60065b | 1467 | #if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1468 | /** |
kadonotakashi | 0:8fdf9a60065b | 1469 | * \brief Enable Slow Crystal Oscillator Frequency Monitoring. |
kadonotakashi | 0:8fdf9a60065b | 1470 | */ |
kadonotakashi | 0:8fdf9a60065b | 1471 | void pmc_enable_sclk_osc_freq_monitor(void) |
kadonotakashi | 0:8fdf9a60065b | 1472 | { |
kadonotakashi | 0:8fdf9a60065b | 1473 | uint32_t ul_reg = PMC->CKGR_MOR; |
kadonotakashi | 0:8fdf9a60065b | 1474 | |
kadonotakashi | 0:8fdf9a60065b | 1475 | PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg; |
kadonotakashi | 0:8fdf9a60065b | 1476 | } |
kadonotakashi | 0:8fdf9a60065b | 1477 | |
kadonotakashi | 0:8fdf9a60065b | 1478 | /** |
kadonotakashi | 0:8fdf9a60065b | 1479 | * \brief Disable Slow Crystal Oscillator Frequency Monitoring. |
kadonotakashi | 0:8fdf9a60065b | 1480 | */ |
kadonotakashi | 0:8fdf9a60065b | 1481 | void pmc_disable_sclk_osc_freq_monitor(void) |
kadonotakashi | 0:8fdf9a60065b | 1482 | { |
kadonotakashi | 0:8fdf9a60065b | 1483 | uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME); |
kadonotakashi | 0:8fdf9a60065b | 1484 | |
kadonotakashi | 0:8fdf9a60065b | 1485 | PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg; |
kadonotakashi | 0:8fdf9a60065b | 1486 | } |
kadonotakashi | 0:8fdf9a60065b | 1487 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1488 | |
kadonotakashi | 0:8fdf9a60065b | 1489 | /** |
kadonotakashi | 0:8fdf9a60065b | 1490 | * \brief Enable or disable write protect of PMC registers. |
kadonotakashi | 0:8fdf9a60065b | 1491 | * |
kadonotakashi | 0:8fdf9a60065b | 1492 | * \param ul_enable 1 to enable, 0 to disable. |
kadonotakashi | 0:8fdf9a60065b | 1493 | */ |
kadonotakashi | 0:8fdf9a60065b | 1494 | void pmc_set_writeprotect(uint32_t ul_enable) |
kadonotakashi | 0:8fdf9a60065b | 1495 | { |
kadonotakashi | 0:8fdf9a60065b | 1496 | if (ul_enable) { |
kadonotakashi | 0:8fdf9a60065b | 1497 | PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN; |
kadonotakashi | 0:8fdf9a60065b | 1498 | } else { |
kadonotakashi | 0:8fdf9a60065b | 1499 | PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD; |
kadonotakashi | 0:8fdf9a60065b | 1500 | } |
kadonotakashi | 0:8fdf9a60065b | 1501 | } |
kadonotakashi | 0:8fdf9a60065b | 1502 | |
kadonotakashi | 0:8fdf9a60065b | 1503 | /** |
kadonotakashi | 0:8fdf9a60065b | 1504 | * \brief Return write protect status. |
kadonotakashi | 0:8fdf9a60065b | 1505 | * |
kadonotakashi | 0:8fdf9a60065b | 1506 | * \return Return write protect status. |
kadonotakashi | 0:8fdf9a60065b | 1507 | */ |
kadonotakashi | 0:8fdf9a60065b | 1508 | uint32_t pmc_get_writeprotect_status(void) |
kadonotakashi | 0:8fdf9a60065b | 1509 | { |
kadonotakashi | 0:8fdf9a60065b | 1510 | return PMC->PMC_WPSR; |
kadonotakashi | 0:8fdf9a60065b | 1511 | } |
kadonotakashi | 0:8fdf9a60065b | 1512 | |
kadonotakashi | 0:8fdf9a60065b | 1513 | #if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1514 | /** |
kadonotakashi | 0:8fdf9a60065b | 1515 | * \brief Enable the specified peripheral clock. |
kadonotakashi | 0:8fdf9a60065b | 1516 | * |
kadonotakashi | 0:8fdf9a60065b | 1517 | * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). |
kadonotakashi | 0:8fdf9a60065b | 1518 | * |
kadonotakashi | 0:8fdf9a60065b | 1519 | * \param ul_id Peripheral ID (ID_xxx). |
kadonotakashi | 0:8fdf9a60065b | 1520 | * |
kadonotakashi | 0:8fdf9a60065b | 1521 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 1522 | * \retval 1 Fail. |
kadonotakashi | 0:8fdf9a60065b | 1523 | */ |
kadonotakashi | 0:8fdf9a60065b | 1524 | uint32_t pmc_enable_sleepwalking(uint32_t ul_id) |
kadonotakashi | 0:8fdf9a60065b | 1525 | { |
kadonotakashi | 0:8fdf9a60065b | 1526 | uint32_t temp; |
kadonotakashi | 0:8fdf9a60065b | 1527 | #if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1528 | if ((7 <= ul_id) && (ul_id<= 29)) { |
kadonotakashi | 0:8fdf9a60065b | 1529 | #else |
kadonotakashi | 0:8fdf9a60065b | 1530 | if ((8 <= ul_id) && (ul_id<= 29)) { |
kadonotakashi | 0:8fdf9a60065b | 1531 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1532 | temp = pmc_get_active_status0(); |
kadonotakashi | 0:8fdf9a60065b | 1533 | if (temp & (1 << ul_id)) { |
kadonotakashi | 0:8fdf9a60065b | 1534 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 1535 | } |
kadonotakashi | 0:8fdf9a60065b | 1536 | PMC->PMC_SLPWK_ER0 = 1 << ul_id; |
kadonotakashi | 0:8fdf9a60065b | 1537 | temp = pmc_get_active_status0(); |
kadonotakashi | 0:8fdf9a60065b | 1538 | if (temp & (1 << ul_id)) { |
kadonotakashi | 0:8fdf9a60065b | 1539 | pmc_disable_sleepwalking(ul_id); |
kadonotakashi | 0:8fdf9a60065b | 1540 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 1541 | } |
kadonotakashi | 0:8fdf9a60065b | 1542 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 1543 | } |
kadonotakashi | 0:8fdf9a60065b | 1544 | #if (SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1545 | else if ((32 <= ul_id) && (ul_id<= 60)) { |
kadonotakashi | 0:8fdf9a60065b | 1546 | ul_id -= 32; |
kadonotakashi | 0:8fdf9a60065b | 1547 | temp = pmc_get_active_status1(); |
kadonotakashi | 0:8fdf9a60065b | 1548 | if (temp & (1 << ul_id)) { |
kadonotakashi | 0:8fdf9a60065b | 1549 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 1550 | } |
kadonotakashi | 0:8fdf9a60065b | 1551 | PMC->PMC_SLPWK_ER1 = 1 << ul_id; |
kadonotakashi | 0:8fdf9a60065b | 1552 | temp = pmc_get_active_status1(); |
kadonotakashi | 0:8fdf9a60065b | 1553 | if (temp & (1 << ul_id)) { |
kadonotakashi | 0:8fdf9a60065b | 1554 | pmc_disable_sleepwalking(ul_id); |
kadonotakashi | 0:8fdf9a60065b | 1555 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 1556 | } |
kadonotakashi | 0:8fdf9a60065b | 1557 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 1558 | } |
kadonotakashi | 0:8fdf9a60065b | 1559 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1560 | else { |
kadonotakashi | 0:8fdf9a60065b | 1561 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 1562 | } |
kadonotakashi | 0:8fdf9a60065b | 1563 | } |
kadonotakashi | 0:8fdf9a60065b | 1564 | |
kadonotakashi | 0:8fdf9a60065b | 1565 | /** |
kadonotakashi | 0:8fdf9a60065b | 1566 | * \brief Disable the sleepwalking of specified peripheral. |
kadonotakashi | 0:8fdf9a60065b | 1567 | * |
kadonotakashi | 0:8fdf9a60065b | 1568 | * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). |
kadonotakashi | 0:8fdf9a60065b | 1569 | * |
kadonotakashi | 0:8fdf9a60065b | 1570 | * \param ul_id Peripheral ID (ID_xxx). |
kadonotakashi | 0:8fdf9a60065b | 1571 | * |
kadonotakashi | 0:8fdf9a60065b | 1572 | * \retval 0 Success. |
kadonotakashi | 0:8fdf9a60065b | 1573 | * \retval 1 Invalid parameter. |
kadonotakashi | 0:8fdf9a60065b | 1574 | */ |
kadonotakashi | 0:8fdf9a60065b | 1575 | uint32_t pmc_disable_sleepwalking(uint32_t ul_id) |
kadonotakashi | 0:8fdf9a60065b | 1576 | { |
kadonotakashi | 0:8fdf9a60065b | 1577 | #if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1578 | if ((7 <= ul_id) && (ul_id<= 29)) { |
kadonotakashi | 0:8fdf9a60065b | 1579 | #else |
kadonotakashi | 0:8fdf9a60065b | 1580 | if ((8 <= ul_id) && (ul_id<= 29)) { |
kadonotakashi | 0:8fdf9a60065b | 1581 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1582 | PMC->PMC_SLPWK_DR0 = 1 << ul_id; |
kadonotakashi | 0:8fdf9a60065b | 1583 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 1584 | } |
kadonotakashi | 0:8fdf9a60065b | 1585 | #if (SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1586 | else if ((32 <= ul_id) && (ul_id<= 60)) { |
kadonotakashi | 0:8fdf9a60065b | 1587 | ul_id -= 32; |
kadonotakashi | 0:8fdf9a60065b | 1588 | PMC->PMC_SLPWK_DR1 = 1 << ul_id; |
kadonotakashi | 0:8fdf9a60065b | 1589 | return 0; |
kadonotakashi | 0:8fdf9a60065b | 1590 | } |
kadonotakashi | 0:8fdf9a60065b | 1591 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1592 | else { |
kadonotakashi | 0:8fdf9a60065b | 1593 | return 1; |
kadonotakashi | 0:8fdf9a60065b | 1594 | } |
kadonotakashi | 0:8fdf9a60065b | 1595 | } |
kadonotakashi | 0:8fdf9a60065b | 1596 | |
kadonotakashi | 0:8fdf9a60065b | 1597 | /** |
kadonotakashi | 0:8fdf9a60065b | 1598 | * \brief Return peripheral sleepwalking enable status. |
kadonotakashi | 0:8fdf9a60065b | 1599 | * |
kadonotakashi | 0:8fdf9a60065b | 1600 | * \return the status register value. |
kadonotakashi | 0:8fdf9a60065b | 1601 | */ |
kadonotakashi | 0:8fdf9a60065b | 1602 | uint32_t pmc_get_sleepwalking_status0(void) |
kadonotakashi | 0:8fdf9a60065b | 1603 | { |
kadonotakashi | 0:8fdf9a60065b | 1604 | return PMC->PMC_SLPWK_SR0; |
kadonotakashi | 0:8fdf9a60065b | 1605 | } |
kadonotakashi | 0:8fdf9a60065b | 1606 | |
kadonotakashi | 0:8fdf9a60065b | 1607 | /** |
kadonotakashi | 0:8fdf9a60065b | 1608 | * \brief Return peripheral active status. |
kadonotakashi | 0:8fdf9a60065b | 1609 | * |
kadonotakashi | 0:8fdf9a60065b | 1610 | * \return the status register value. |
kadonotakashi | 0:8fdf9a60065b | 1611 | */ |
kadonotakashi | 0:8fdf9a60065b | 1612 | uint32_t pmc_get_active_status0(void) |
kadonotakashi | 0:8fdf9a60065b | 1613 | { |
kadonotakashi | 0:8fdf9a60065b | 1614 | return PMC->PMC_SLPWK_ASR0; |
kadonotakashi | 0:8fdf9a60065b | 1615 | } |
kadonotakashi | 0:8fdf9a60065b | 1616 | |
kadonotakashi | 0:8fdf9a60065b | 1617 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1618 | |
kadonotakashi | 0:8fdf9a60065b | 1619 | #if (SAMV71 || SAMV70 || SAME70 || SAMS70) |
kadonotakashi | 0:8fdf9a60065b | 1620 | /** |
kadonotakashi | 0:8fdf9a60065b | 1621 | * \brief Return peripheral sleepwalking enable status. |
kadonotakashi | 0:8fdf9a60065b | 1622 | * |
kadonotakashi | 0:8fdf9a60065b | 1623 | * \return the status register value. |
kadonotakashi | 0:8fdf9a60065b | 1624 | */ |
kadonotakashi | 0:8fdf9a60065b | 1625 | uint32_t pmc_get_sleepwalking_status1(void) |
kadonotakashi | 0:8fdf9a60065b | 1626 | { |
kadonotakashi | 0:8fdf9a60065b | 1627 | return PMC->PMC_SLPWK_SR1; |
kadonotakashi | 0:8fdf9a60065b | 1628 | } |
kadonotakashi | 0:8fdf9a60065b | 1629 | |
kadonotakashi | 0:8fdf9a60065b | 1630 | /** |
kadonotakashi | 0:8fdf9a60065b | 1631 | * \brief Return peripheral active status. |
kadonotakashi | 0:8fdf9a60065b | 1632 | * |
kadonotakashi | 0:8fdf9a60065b | 1633 | * \return the status register value. |
kadonotakashi | 0:8fdf9a60065b | 1634 | */ |
kadonotakashi | 0:8fdf9a60065b | 1635 | uint32_t pmc_get_active_status1(void) |
kadonotakashi | 0:8fdf9a60065b | 1636 | { |
kadonotakashi | 0:8fdf9a60065b | 1637 | return PMC->PMC_SLPWK_ASR1; |
kadonotakashi | 0:8fdf9a60065b | 1638 | } |
kadonotakashi | 0:8fdf9a60065b | 1639 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1640 | |
kadonotakashi | 0:8fdf9a60065b | 1641 | /// @cond 0 |
kadonotakashi | 0:8fdf9a60065b | 1642 | /**INDENT-OFF**/ |
kadonotakashi | 0:8fdf9a60065b | 1643 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 1644 | } |
kadonotakashi | 0:8fdf9a60065b | 1645 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1646 | /**INDENT-ON**/ |
kadonotakashi | 0:8fdf9a60065b | 1647 | /// @endcond |