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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_NUVOTON/TARGET_NUC472/mbed_overrides.c
- Committer:
- kadonotakashi
- Date:
- 2018-10-10
- Revision:
- 0:8fdf9a60065b
File content as of revision 0:8fdf9a60065b:
/* mbed Microcontroller Library * Copyright (c) 2015-2016 Nuvoton * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "cmsis.h" #include "analogin_api.h" void mbed_sdk_init(void) { // NOTE: Support singleton semantics to be called from other init functions static int inited = 0; if (inited) { return; } inited = 1; /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Unlock protected registers */ SYS_UnlockReg(); /* Enable External XTAL (4~24 MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Enable LIRC for lp_ticker */ CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); /* Enable LXT for RTC */ CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk); /* Waiting for External XTAL (4~24 MHz) ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Waiting for LIRC ready */ CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); /* Waiting for LXT ready */ CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); /* Switch HCLK clock source to HXT */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1)); /* Set PLL to power down mode and PLLSTB bit in CLKSTATUS register will be cleared by hardware.*/ CLK->PLLCTL|= CLK_PLLCTL_PD_Msk; /* Set PLL frequency */ CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT; /* Waiting for clock ready */ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); /* Switch HCLK clock source to PLL */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1)); /* Enable IP clock */ //CLK_EnableModuleClock(UART0_MODULE); /* Select IP clock source */ //CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UARTSEL_HXT,CLK_CLKDIV0_UART(1)); #if DEVICE_ANALOGIN /* Vref connect to AVDD */ SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD; /* Switch ADC0 to EADC mode */ SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_ADCMODESEL_Msk) | SYS_VREFCTL_ADCMODESEL_EADC; #endif /* Update System Core Clock */ /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ SystemCoreClockUpdate(); /* Lock protected registers */ SYS_LockReg(); }