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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
Diff: mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct
- Revision:
- 0:8fdf9a60065b
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct Wed Oct 10 00:33:53 2018 +0000 @@ -0,0 +1,165 @@ +#! armcc -E + +/* Default flash/SRAM partition + * + * Default flash partition: + * Secure: 256KiB + * Non-secure: 256KiB + * + * Default SRAM partition: + * Secure: 32KiB + * Non-secure: 64KiB + */ +#if defined(DOMAIN_NS) && DOMAIN_NS + +#ifndef MBED_APP_START +#define MBED_APP_START 0x10040000 +#endif + +#ifndef MBED_APP_SIZE +#define MBED_APP_SIZE 0x40000 +#endif + +#ifndef MBED_RAM_START +#define MBED_RAM_START 0x30008000 +#endif + +#ifndef MBED_RAM_SIZE +#define MBED_RAM_SIZE 0x10000 +#endif + +#else + +#ifndef MBED_APP_START +#define MBED_APP_START 0x0 +#endif + +#ifndef MBED_APP_SIZE +#define MBED_APP_SIZE 0x40000 +#endif + +#ifndef MBED_RAM_START +#define MBED_RAM_START 0x20000000 +#endif + +#ifndef MBED_RAM_SIZE +#define MBED_RAM_SIZE 0x8000 +#endif + +#endif + +/* Requirements for NSC location + * + * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000. + * 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range. + * 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range. + * 4. NSC region size defaults to 4KiB if not defined. + */ +#ifndef NU_TZ_NSC_START +#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE) +#endif +#ifndef NU_TZ_NSC_SIZE +#define NU_TZ_NSC_SIZE 0x1000 +#endif + +/* Initial/ISR stack size */ +#if (! defined(NU_INITIAL_STACK_SIZE)) +#if defined(DOMAIN_NS) && DOMAIN_NS +#define NU_INITIAL_STACK_SIZE 0x800 +#else +#define NU_INITIAL_STACK_SIZE 0x800 +#endif +#endif + +#if defined(DOMAIN_NS) && DOMAIN_NS + +LR_IROM1 MBED_APP_START +{ + /* load address = execution address */ + ER_IROM1 +0 + { + *(RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ARM_LIB_STACK MBED_RAM_START EMPTY NU_INITIAL_STACK_SIZE + { + } + + /* Reserve for vectors + * + * Vector table base address is required to be 128-byte aligned at a minimum. + * A PE might impose further restrictions on it. */ + ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102)) + { + } + + /* 16 byte-aligned */ + RW_IRAM1 AlignExpr(+0, 16) + { + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) + { + } +} + +ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) +ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_START + MBED_RAM_SIZE) + +#else + +LR_IROM1 MBED_APP_START +{ + /* load address = execution address */ + ER_IROM1 +0 + { + *(RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ARM_LIB_STACK 0x20000000 EMPTY NU_INITIAL_STACK_SIZE + { + } + + /* Reserve for vectors + * + * Vector table base address is required to be 128-byte aligned at a minimum. + * A PE might impose further restrictions on it. */ + ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102)) + { + } + + /* 16 byte-aligned */ + RW_IRAM1 AlignExpr(+0, 16) + { + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) + { + } +} + +LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE +{ + ER_IROM_NSC +0 + { + *(Veneer$$CMSE) + } + + ER_IROM_NSC_PAD +0 FILL 0xFFFFFFFF (NU_TZ_NSC_START + NU_TZ_NSC_SIZE - ImageLimit(ER_IROM_NSC)) + { + } +} + +ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_START) +ScatterAssert(LoadLimit(LR_IROM_NSC) <= (NU_TZ_NSC_START + NU_TZ_NSC_SIZE)) +/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */ +ScatterAssert(LoadBase(LR_IROM_NSC) >= 0x4000) +ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_START + MBED_RAM_SIZE)) + +#endif