takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_NUVOTON/TARGET_NUC472/mbed_overrides.c@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /* mbed Microcontroller Library
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2015-2016 Nuvoton
kadonotakashi 0:8fdf9a60065b 3 *
kadonotakashi 0:8fdf9a60065b 4 * Licensed under the Apache License, Version 2.0 (the "License");
kadonotakashi 0:8fdf9a60065b 5 * you may not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 6 * You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * http://www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 11 * distributed under the License is distributed on an "AS IS" BASIS,
kadonotakashi 0:8fdf9a60065b 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 13 * See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 14 * limitations under the License.
kadonotakashi 0:8fdf9a60065b 15 */
kadonotakashi 0:8fdf9a60065b 16
kadonotakashi 0:8fdf9a60065b 17 #include "cmsis.h"
kadonotakashi 0:8fdf9a60065b 18 #include "analogin_api.h"
kadonotakashi 0:8fdf9a60065b 19
kadonotakashi 0:8fdf9a60065b 20 void mbed_sdk_init(void)
kadonotakashi 0:8fdf9a60065b 21 {
kadonotakashi 0:8fdf9a60065b 22 // NOTE: Support singleton semantics to be called from other init functions
kadonotakashi 0:8fdf9a60065b 23 static int inited = 0;
kadonotakashi 0:8fdf9a60065b 24 if (inited) {
kadonotakashi 0:8fdf9a60065b 25 return;
kadonotakashi 0:8fdf9a60065b 26 }
kadonotakashi 0:8fdf9a60065b 27 inited = 1;
kadonotakashi 0:8fdf9a60065b 28
kadonotakashi 0:8fdf9a60065b 29 /*---------------------------------------------------------------------------------------------------------*/
kadonotakashi 0:8fdf9a60065b 30 /* Init System Clock */
kadonotakashi 0:8fdf9a60065b 31 /*---------------------------------------------------------------------------------------------------------*/
kadonotakashi 0:8fdf9a60065b 32 /* Unlock protected registers */
kadonotakashi 0:8fdf9a60065b 33 SYS_UnlockReg();
kadonotakashi 0:8fdf9a60065b 34
kadonotakashi 0:8fdf9a60065b 35 /* Enable External XTAL (4~24 MHz) */
kadonotakashi 0:8fdf9a60065b 36 CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
kadonotakashi 0:8fdf9a60065b 37 /* Enable LIRC for lp_ticker */
kadonotakashi 0:8fdf9a60065b 38 CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
kadonotakashi 0:8fdf9a60065b 39 /* Enable LXT for RTC */
kadonotakashi 0:8fdf9a60065b 40 CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
kadonotakashi 0:8fdf9a60065b 41
kadonotakashi 0:8fdf9a60065b 42 /* Waiting for External XTAL (4~24 MHz) ready */
kadonotakashi 0:8fdf9a60065b 43 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
kadonotakashi 0:8fdf9a60065b 44 /* Waiting for LIRC ready */
kadonotakashi 0:8fdf9a60065b 45 CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
kadonotakashi 0:8fdf9a60065b 46 /* Waiting for LXT ready */
kadonotakashi 0:8fdf9a60065b 47 CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
kadonotakashi 0:8fdf9a60065b 48
kadonotakashi 0:8fdf9a60065b 49 /* Switch HCLK clock source to HXT */
kadonotakashi 0:8fdf9a60065b 50 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
kadonotakashi 0:8fdf9a60065b 51
kadonotakashi 0:8fdf9a60065b 52 /* Set PLL to power down mode and PLLSTB bit in CLKSTATUS register will be cleared by hardware.*/
kadonotakashi 0:8fdf9a60065b 53 CLK->PLLCTL|= CLK_PLLCTL_PD_Msk;
kadonotakashi 0:8fdf9a60065b 54
kadonotakashi 0:8fdf9a60065b 55 /* Set PLL frequency */
kadonotakashi 0:8fdf9a60065b 56 CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;
kadonotakashi 0:8fdf9a60065b 57
kadonotakashi 0:8fdf9a60065b 58 /* Waiting for clock ready */
kadonotakashi 0:8fdf9a60065b 59 CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
kadonotakashi 0:8fdf9a60065b 60
kadonotakashi 0:8fdf9a60065b 61 /* Switch HCLK clock source to PLL */
kadonotakashi 0:8fdf9a60065b 62 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));
kadonotakashi 0:8fdf9a60065b 63
kadonotakashi 0:8fdf9a60065b 64 /* Enable IP clock */
kadonotakashi 0:8fdf9a60065b 65 //CLK_EnableModuleClock(UART0_MODULE);
kadonotakashi 0:8fdf9a60065b 66
kadonotakashi 0:8fdf9a60065b 67 /* Select IP clock source */
kadonotakashi 0:8fdf9a60065b 68 //CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UARTSEL_HXT,CLK_CLKDIV0_UART(1));
kadonotakashi 0:8fdf9a60065b 69
kadonotakashi 0:8fdf9a60065b 70 #if DEVICE_ANALOGIN
kadonotakashi 0:8fdf9a60065b 71 /* Vref connect to AVDD */
kadonotakashi 0:8fdf9a60065b 72 SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD;
kadonotakashi 0:8fdf9a60065b 73 /* Switch ADC0 to EADC mode */
kadonotakashi 0:8fdf9a60065b 74 SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_ADCMODESEL_Msk) | SYS_VREFCTL_ADCMODESEL_EADC;
kadonotakashi 0:8fdf9a60065b 75 #endif
kadonotakashi 0:8fdf9a60065b 76
kadonotakashi 0:8fdf9a60065b 77 /* Update System Core Clock */
kadonotakashi 0:8fdf9a60065b 78 /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
kadonotakashi 0:8fdf9a60065b 79 SystemCoreClockUpdate();
kadonotakashi 0:8fdf9a60065b 80
kadonotakashi 0:8fdf9a60065b 81 /* Lock protected registers */
kadonotakashi 0:8fdf9a60065b 82 SYS_LockReg();
kadonotakashi 0:8fdf9a60065b 83 }