takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 #! armcc -E
kadonotakashi 0:8fdf9a60065b 2
kadonotakashi 0:8fdf9a60065b 3 /* Default flash/SRAM partition
kadonotakashi 0:8fdf9a60065b 4 *
kadonotakashi 0:8fdf9a60065b 5 * Default flash partition:
kadonotakashi 0:8fdf9a60065b 6 * Secure: 256KiB
kadonotakashi 0:8fdf9a60065b 7 * Non-secure: 256KiB
kadonotakashi 0:8fdf9a60065b 8 *
kadonotakashi 0:8fdf9a60065b 9 * Default SRAM partition:
kadonotakashi 0:8fdf9a60065b 10 * Secure: 32KiB
kadonotakashi 0:8fdf9a60065b 11 * Non-secure: 64KiB
kadonotakashi 0:8fdf9a60065b 12 */
kadonotakashi 0:8fdf9a60065b 13 #if defined(DOMAIN_NS) && DOMAIN_NS
kadonotakashi 0:8fdf9a60065b 14
kadonotakashi 0:8fdf9a60065b 15 #ifndef MBED_APP_START
kadonotakashi 0:8fdf9a60065b 16 #define MBED_APP_START 0x10040000
kadonotakashi 0:8fdf9a60065b 17 #endif
kadonotakashi 0:8fdf9a60065b 18
kadonotakashi 0:8fdf9a60065b 19 #ifndef MBED_APP_SIZE
kadonotakashi 0:8fdf9a60065b 20 #define MBED_APP_SIZE 0x40000
kadonotakashi 0:8fdf9a60065b 21 #endif
kadonotakashi 0:8fdf9a60065b 22
kadonotakashi 0:8fdf9a60065b 23 #ifndef MBED_RAM_START
kadonotakashi 0:8fdf9a60065b 24 #define MBED_RAM_START 0x30008000
kadonotakashi 0:8fdf9a60065b 25 #endif
kadonotakashi 0:8fdf9a60065b 26
kadonotakashi 0:8fdf9a60065b 27 #ifndef MBED_RAM_SIZE
kadonotakashi 0:8fdf9a60065b 28 #define MBED_RAM_SIZE 0x10000
kadonotakashi 0:8fdf9a60065b 29 #endif
kadonotakashi 0:8fdf9a60065b 30
kadonotakashi 0:8fdf9a60065b 31 #else
kadonotakashi 0:8fdf9a60065b 32
kadonotakashi 0:8fdf9a60065b 33 #ifndef MBED_APP_START
kadonotakashi 0:8fdf9a60065b 34 #define MBED_APP_START 0x0
kadonotakashi 0:8fdf9a60065b 35 #endif
kadonotakashi 0:8fdf9a60065b 36
kadonotakashi 0:8fdf9a60065b 37 #ifndef MBED_APP_SIZE
kadonotakashi 0:8fdf9a60065b 38 #define MBED_APP_SIZE 0x40000
kadonotakashi 0:8fdf9a60065b 39 #endif
kadonotakashi 0:8fdf9a60065b 40
kadonotakashi 0:8fdf9a60065b 41 #ifndef MBED_RAM_START
kadonotakashi 0:8fdf9a60065b 42 #define MBED_RAM_START 0x20000000
kadonotakashi 0:8fdf9a60065b 43 #endif
kadonotakashi 0:8fdf9a60065b 44
kadonotakashi 0:8fdf9a60065b 45 #ifndef MBED_RAM_SIZE
kadonotakashi 0:8fdf9a60065b 46 #define MBED_RAM_SIZE 0x8000
kadonotakashi 0:8fdf9a60065b 47 #endif
kadonotakashi 0:8fdf9a60065b 48
kadonotakashi 0:8fdf9a60065b 49 #endif
kadonotakashi 0:8fdf9a60065b 50
kadonotakashi 0:8fdf9a60065b 51 /* Requirements for NSC location
kadonotakashi 0:8fdf9a60065b 52 *
kadonotakashi 0:8fdf9a60065b 53 * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
kadonotakashi 0:8fdf9a60065b 54 * 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
kadonotakashi 0:8fdf9a60065b 55 * 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
kadonotakashi 0:8fdf9a60065b 56 * 4. NSC region size defaults to 4KiB if not defined.
kadonotakashi 0:8fdf9a60065b 57 */
kadonotakashi 0:8fdf9a60065b 58 #ifndef NU_TZ_NSC_START
kadonotakashi 0:8fdf9a60065b 59 #define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
kadonotakashi 0:8fdf9a60065b 60 #endif
kadonotakashi 0:8fdf9a60065b 61 #ifndef NU_TZ_NSC_SIZE
kadonotakashi 0:8fdf9a60065b 62 #define NU_TZ_NSC_SIZE 0x1000
kadonotakashi 0:8fdf9a60065b 63 #endif
kadonotakashi 0:8fdf9a60065b 64
kadonotakashi 0:8fdf9a60065b 65 /* Initial/ISR stack size */
kadonotakashi 0:8fdf9a60065b 66 #if (! defined(NU_INITIAL_STACK_SIZE))
kadonotakashi 0:8fdf9a60065b 67 #if defined(DOMAIN_NS) && DOMAIN_NS
kadonotakashi 0:8fdf9a60065b 68 #define NU_INITIAL_STACK_SIZE 0x800
kadonotakashi 0:8fdf9a60065b 69 #else
kadonotakashi 0:8fdf9a60065b 70 #define NU_INITIAL_STACK_SIZE 0x800
kadonotakashi 0:8fdf9a60065b 71 #endif
kadonotakashi 0:8fdf9a60065b 72 #endif
kadonotakashi 0:8fdf9a60065b 73
kadonotakashi 0:8fdf9a60065b 74 #if defined(DOMAIN_NS) && DOMAIN_NS
kadonotakashi 0:8fdf9a60065b 75
kadonotakashi 0:8fdf9a60065b 76 LR_IROM1 MBED_APP_START
kadonotakashi 0:8fdf9a60065b 77 {
kadonotakashi 0:8fdf9a60065b 78 /* load address = execution address */
kadonotakashi 0:8fdf9a60065b 79 ER_IROM1 +0
kadonotakashi 0:8fdf9a60065b 80 {
kadonotakashi 0:8fdf9a60065b 81 *(RESET, +First)
kadonotakashi 0:8fdf9a60065b 82 *(InRoot$$Sections)
kadonotakashi 0:8fdf9a60065b 83 .ANY (+RO)
kadonotakashi 0:8fdf9a60065b 84 }
kadonotakashi 0:8fdf9a60065b 85
kadonotakashi 0:8fdf9a60065b 86 ARM_LIB_STACK MBED_RAM_START EMPTY NU_INITIAL_STACK_SIZE
kadonotakashi 0:8fdf9a60065b 87 {
kadonotakashi 0:8fdf9a60065b 88 }
kadonotakashi 0:8fdf9a60065b 89
kadonotakashi 0:8fdf9a60065b 90 /* Reserve for vectors
kadonotakashi 0:8fdf9a60065b 91 *
kadonotakashi 0:8fdf9a60065b 92 * Vector table base address is required to be 128-byte aligned at a minimum.
kadonotakashi 0:8fdf9a60065b 93 * A PE might impose further restrictions on it. */
kadonotakashi 0:8fdf9a60065b 94 ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
kadonotakashi 0:8fdf9a60065b 95 {
kadonotakashi 0:8fdf9a60065b 96 }
kadonotakashi 0:8fdf9a60065b 97
kadonotakashi 0:8fdf9a60065b 98 /* 16 byte-aligned */
kadonotakashi 0:8fdf9a60065b 99 RW_IRAM1 AlignExpr(+0, 16)
kadonotakashi 0:8fdf9a60065b 100 {
kadonotakashi 0:8fdf9a60065b 101 .ANY (+RW +ZI)
kadonotakashi 0:8fdf9a60065b 102 }
kadonotakashi 0:8fdf9a60065b 103
kadonotakashi 0:8fdf9a60065b 104 ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
kadonotakashi 0:8fdf9a60065b 105 {
kadonotakashi 0:8fdf9a60065b 106 }
kadonotakashi 0:8fdf9a60065b 107 }
kadonotakashi 0:8fdf9a60065b 108
kadonotakashi 0:8fdf9a60065b 109 ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
kadonotakashi 0:8fdf9a60065b 110 ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_START + MBED_RAM_SIZE)
kadonotakashi 0:8fdf9a60065b 111
kadonotakashi 0:8fdf9a60065b 112 #else
kadonotakashi 0:8fdf9a60065b 113
kadonotakashi 0:8fdf9a60065b 114 LR_IROM1 MBED_APP_START
kadonotakashi 0:8fdf9a60065b 115 {
kadonotakashi 0:8fdf9a60065b 116 /* load address = execution address */
kadonotakashi 0:8fdf9a60065b 117 ER_IROM1 +0
kadonotakashi 0:8fdf9a60065b 118 {
kadonotakashi 0:8fdf9a60065b 119 *(RESET, +First)
kadonotakashi 0:8fdf9a60065b 120 *(InRoot$$Sections)
kadonotakashi 0:8fdf9a60065b 121 .ANY (+RO)
kadonotakashi 0:8fdf9a60065b 122 }
kadonotakashi 0:8fdf9a60065b 123
kadonotakashi 0:8fdf9a60065b 124 ARM_LIB_STACK 0x20000000 EMPTY NU_INITIAL_STACK_SIZE
kadonotakashi 0:8fdf9a60065b 125 {
kadonotakashi 0:8fdf9a60065b 126 }
kadonotakashi 0:8fdf9a60065b 127
kadonotakashi 0:8fdf9a60065b 128 /* Reserve for vectors
kadonotakashi 0:8fdf9a60065b 129 *
kadonotakashi 0:8fdf9a60065b 130 * Vector table base address is required to be 128-byte aligned at a minimum.
kadonotakashi 0:8fdf9a60065b 131 * A PE might impose further restrictions on it. */
kadonotakashi 0:8fdf9a60065b 132 ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
kadonotakashi 0:8fdf9a60065b 133 {
kadonotakashi 0:8fdf9a60065b 134 }
kadonotakashi 0:8fdf9a60065b 135
kadonotakashi 0:8fdf9a60065b 136 /* 16 byte-aligned */
kadonotakashi 0:8fdf9a60065b 137 RW_IRAM1 AlignExpr(+0, 16)
kadonotakashi 0:8fdf9a60065b 138 {
kadonotakashi 0:8fdf9a60065b 139 .ANY (+RW +ZI)
kadonotakashi 0:8fdf9a60065b 140 }
kadonotakashi 0:8fdf9a60065b 141
kadonotakashi 0:8fdf9a60065b 142 ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
kadonotakashi 0:8fdf9a60065b 143 {
kadonotakashi 0:8fdf9a60065b 144 }
kadonotakashi 0:8fdf9a60065b 145 }
kadonotakashi 0:8fdf9a60065b 146
kadonotakashi 0:8fdf9a60065b 147 LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
kadonotakashi 0:8fdf9a60065b 148 {
kadonotakashi 0:8fdf9a60065b 149 ER_IROM_NSC +0
kadonotakashi 0:8fdf9a60065b 150 {
kadonotakashi 0:8fdf9a60065b 151 *(Veneer$$CMSE)
kadonotakashi 0:8fdf9a60065b 152 }
kadonotakashi 0:8fdf9a60065b 153
kadonotakashi 0:8fdf9a60065b 154 ER_IROM_NSC_PAD +0 FILL 0xFFFFFFFF (NU_TZ_NSC_START + NU_TZ_NSC_SIZE - ImageLimit(ER_IROM_NSC))
kadonotakashi 0:8fdf9a60065b 155 {
kadonotakashi 0:8fdf9a60065b 156 }
kadonotakashi 0:8fdf9a60065b 157 }
kadonotakashi 0:8fdf9a60065b 158
kadonotakashi 0:8fdf9a60065b 159 ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_START)
kadonotakashi 0:8fdf9a60065b 160 ScatterAssert(LoadLimit(LR_IROM_NSC) <= (NU_TZ_NSC_START + NU_TZ_NSC_SIZE))
kadonotakashi 0:8fdf9a60065b 161 /* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */
kadonotakashi 0:8fdf9a60065b 162 ScatterAssert(LoadBase(LR_IROM_NSC) >= 0x4000)
kadonotakashi 0:8fdf9a60065b 163 ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_START + MBED_RAM_SIZE))
kadonotakashi 0:8fdf9a60065b 164
kadonotakashi 0:8fdf9a60065b 165 #endif