Nucleo446_SSD1331 - Color Oled(SSD1331) connect to STMicroelectronics…

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takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/usbh_reg.h@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:: kadonotakashi
Date:: Thu Oct 11 02:27:46 2018 +0000
Revision:: 3:f3764f852aa8
Parent:: 0:8fdf9a60065b

Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

User	Revision	Line number	New contents of line
kadonotakashi	0:8fdf9a60065b	1	/************************************************************************//
kadonotakashi	0:8fdf9a60065b	2	* @file usbh_reg.h
kadonotakashi	0:8fdf9a60065b	3	* @version V1.00
kadonotakashi	0:8fdf9a60065b	4	* @brief USBH register definition header file
kadonotakashi	0:8fdf9a60065b	5	*
kadonotakashi	0:8fdf9a60065b	6	* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
kadonotakashi	0:8fdf9a60065b	7	*****************************************************************************/
kadonotakashi	0:8fdf9a60065b	8	#ifndef __USBH_REG_H__
kadonotakashi	0:8fdf9a60065b	9	#define __USBH_REG_H__
kadonotakashi	0:8fdf9a60065b	10
kadonotakashi	0:8fdf9a60065b	11
kadonotakashi	0:8fdf9a60065b	12	/---------------------- USB Host Controller -------------------------/
kadonotakashi	0:8fdf9a60065b	13	/**
kadonotakashi	0:8fdf9a60065b	14	@addtogroup USBH USB Host Controller(USBH)
kadonotakashi	0:8fdf9a60065b	15	Memory Mapped Structure for USBH Controller
kadonotakashi	0:8fdf9a60065b	16	@{ */
kadonotakashi	0:8fdf9a60065b	17
kadonotakashi	0:8fdf9a60065b	18	typedef struct
kadonotakashi	0:8fdf9a60065b	19	{
kadonotakashi	0:8fdf9a60065b	20
kadonotakashi	0:8fdf9a60065b	21
kadonotakashi	0:8fdf9a60065b	22	/**
kadonotakashi	0:8fdf9a60065b	23	* @var USBH_T::HcRevision
kadonotakashi	0:8fdf9a60065b	24	* Offset: 0x00 Host Controller Revision Register
kadonotakashi	0:8fdf9a60065b	25	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	26	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	27	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	28	* \|[7:0] \|REV \|Revision Number
kadonotakashi	0:8fdf9a60065b	29	* \| \| \|Indicates the Open HCI Specification revision number implemented by the Hardware
kadonotakashi	0:8fdf9a60065b	30	* \| \| \|Host Controller supports 1.1 specification.
kadonotakashi	0:8fdf9a60065b	31	* \| \| \|(X.Y = XYh).
kadonotakashi	0:8fdf9a60065b	32	* @var USBH_T::HcControl
kadonotakashi	0:8fdf9a60065b	33	* Offset: 0x04 Host Controller Control Register
kadonotakashi	0:8fdf9a60065b	34	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	35	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	36	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	37	* \|[1:0] \|CBSR \|Control Bulk Service Ratio
kadonotakashi	0:8fdf9a60065b	38	* \| \| \|This specifies the service ratio between Control and Bulk EDs
kadonotakashi	0:8fdf9a60065b	39	* \| \| \|Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs
kadonotakashi	0:8fdf9a60065b	40	* \| \| \|The internal count will be retained when crossing the frame boundary
kadonotakashi	0:8fdf9a60065b	41	* \| \| \|In case of reset, HCD is responsible for restoring this
kadonotakashi	0:8fdf9a60065b	42	* \| \| \|Value.
kadonotakashi	0:8fdf9a60065b	43	* \| \| \|00 = Number of Control EDs over Bulk EDs served is 1:1.
kadonotakashi	0:8fdf9a60065b	44	* \| \| \|01 = Number of Control EDs over Bulk EDs served is 2:1.
kadonotakashi	0:8fdf9a60065b	45	* \| \| \|10 = Number of Control EDs over Bulk EDs served is 3:1.
kadonotakashi	0:8fdf9a60065b	46	* \| \| \|11 = Number of Control EDs over Bulk EDs served is 4:1.
kadonotakashi	0:8fdf9a60065b	47	* \|[2] \|PLE \|Periodic List Enable Bit
kadonotakashi	0:8fdf9a60065b	48	* \| \| \|When set, this bit enables processing of the Periodic (interrupt and isochronous) list
kadonotakashi	0:8fdf9a60065b	49	* \| \| \|The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
kadonotakashi	0:8fdf9a60065b	50	* \| \| \|0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled.
kadonotakashi	0:8fdf9a60065b	51	* \| \| \|1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled.
kadonotakashi	0:8fdf9a60065b	52	* \| \| \|Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
kadonotakashi	0:8fdf9a60065b	53	* \|[3] \|IE \|Isochronous List Enable Bit
kadonotakashi	0:8fdf9a60065b	54	* \| \| \|Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list
kadonotakashi	0:8fdf9a60065b	55	* \| \| \|Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
kadonotakashi	0:8fdf9a60065b	56	* \| \| \|0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled.
kadonotakashi	0:8fdf9a60065b	57	* \| \| \|1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too.
kadonotakashi	0:8fdf9a60065b	58	* \|[4] \|CLE \|Control List Enable Bit
kadonotakashi	0:8fdf9a60065b	59	* \| \| \|0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled.
kadonotakashi	0:8fdf9a60065b	60	* \| \| \|1 = Processing of the Control list in the next frame Enabled.
kadonotakashi	0:8fdf9a60065b	61	* \|[5] \|BLE \|Bulk List Enable Bit
kadonotakashi	0:8fdf9a60065b	62	* \| \| \|0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled.
kadonotakashi	0:8fdf9a60065b	63	* \| \| \|1 = Processing of the Bulk list in the next frame Enabled.
kadonotakashi	0:8fdf9a60065b	64	* \|[7:6] \|HCFS \|Host Controller Functional State
kadonotakashi	0:8fdf9a60065b	65	* \| \| \|This field sets the Host Controller state
kadonotakashi	0:8fdf9a60065b	66	* \| \| \|The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port
kadonotakashi	0:8fdf9a60065b	67	* \| \| \|States are:
kadonotakashi	0:8fdf9a60065b	68	* \| \| \|00 = USBSUSPEND.
kadonotakashi	0:8fdf9a60065b	69	* \| \| \|01 = USBOPERATIONAL.
kadonotakashi	0:8fdf9a60065b	70	* \| \| \|10 = USBRESUME.
kadonotakashi	0:8fdf9a60065b	71	* \| \| \|11 = USBRESET.
kadonotakashi	0:8fdf9a60065b	72	* @var USBH_T::HcCommandStatus
kadonotakashi	0:8fdf9a60065b	73	* Offset: 0x08 Host Controller Command Status Register
kadonotakashi	0:8fdf9a60065b	74	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	75	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	76	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	77	* \|[0] \|HCR \|Host Controller Reset
kadonotakashi	0:8fdf9a60065b	78	* \| \| \|This bit is set to initiate the software reset of Host Controller
kadonotakashi	0:8fdf9a60065b	79	* \| \| \|This bit is cleared by the Host Controller, upon completed of the reset operation.
kadonotakashi	0:8fdf9a60065b	80	* \| \| \|This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
kadonotakashi	0:8fdf9a60065b	81	* \| \| \|0 = Host Controller is not in software reset state.
kadonotakashi	0:8fdf9a60065b	82	* \| \| \|1 = Host Controller is in software reset state.
kadonotakashi	0:8fdf9a60065b	83	* \|[1] \|CLF \|Control List Filled
kadonotakashi	0:8fdf9a60065b	84	* \| \| \|Set high to indicate there is an active TD on the Control List
kadonotakashi	0:8fdf9a60065b	85	* \| \| \|It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
kadonotakashi	0:8fdf9a60065b	86	* \| \| \|0 = No active TD found or Host Controller begins to process the head of the Control list.
kadonotakashi	0:8fdf9a60065b	87	* \| \| \|1 = An active TD added or found on the Control list.
kadonotakashi	0:8fdf9a60065b	88	* \|[2] \|BLF \|Bulk List Filled
kadonotakashi	0:8fdf9a60065b	89	* \| \| \|Set high to indicate there is an active TD on the Bulk list
kadonotakashi	0:8fdf9a60065b	90	* \| \| \|This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
kadonotakashi	0:8fdf9a60065b	91	* \| \| \|0 = No active TD found or Host Controller begins to process the head of the Bulk list.
kadonotakashi	0:8fdf9a60065b	92	* \| \| \|1 = An active TD added or found on the Bulk list.
kadonotakashi	0:8fdf9a60065b	93	* \|[17:16] \|SOC \|Schedule Overrun Count
kadonotakashi	0:8fdf9a60065b	94	* \| \| \|These bits are incremented on each scheduling overrun error
kadonotakashi	0:8fdf9a60065b	95	* \| \| \|It is initialized to 00b and wraps around at 11b
kadonotakashi	0:8fdf9a60065b	96	* \| \| \|This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
kadonotakashi	0:8fdf9a60065b	97	* @var USBH_T::HcInterruptStatus
kadonotakashi	0:8fdf9a60065b	98	* Offset: 0x0C Host Controller Interrupt Status Register
kadonotakashi	0:8fdf9a60065b	99	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	100	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	101	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	102	* \|[0] \|SO \|Scheduling Overrun
kadonotakashi	0:8fdf9a60065b	103	* \| \| \|Set when the List Processor determines a Schedule Overrun has occurred.
kadonotakashi	0:8fdf9a60065b	104	* \| \| \|0 = Schedule Overrun didn't occur.
kadonotakashi	0:8fdf9a60065b	105	* \| \| \|1 = Schedule Overrun has occurred.
kadonotakashi	0:8fdf9a60065b	106	* \|[1] \|WDH \|Write Back Done Head
kadonotakashi	0:8fdf9a60065b	107	* \| \| \|Set after the Host Controller has written HcDoneHead to HccaDoneHead
kadonotakashi	0:8fdf9a60065b	108	* \| \| \|Further updates of the HccaDoneHead will not occur until this bit has been cleared.
kadonotakashi	0:8fdf9a60065b	109	* \| \| \|0 =.Host Controller didn't update HccaDoneHead.
kadonotakashi	0:8fdf9a60065b	110	* \| \| \|1 =.Host Controller has written HcDoneHead to HccaDoneHead.
kadonotakashi	0:8fdf9a60065b	111	* \|[2] \|SF \|Start of Frame
kadonotakashi	0:8fdf9a60065b	112	* \| \| \|Set when the Frame Management functional block signals a u2018Start of Frame' event
kadonotakashi	0:8fdf9a60065b	113	* \| \| \|Host Control generates a SOF token at the same time.
kadonotakashi	0:8fdf9a60065b	114	* \| \| \|0 =.Not the start of a frame.
kadonotakashi	0:8fdf9a60065b	115	* \| \| \|1 =.Indicate the start of a frame and Host Controller generates a SOF token.
kadonotakashi	0:8fdf9a60065b	116	* \|[3] \|RD \|Resume Detected
kadonotakashi	0:8fdf9a60065b	117	* \| \| \|Set when Host Controller detects resume signaling on a downstream port.
kadonotakashi	0:8fdf9a60065b	118	* \| \| \|0 = No resume signaling detected on a downstream port.
kadonotakashi	0:8fdf9a60065b	119	* \| \| \|1 = Resume signaling detected on a downstream port.
kadonotakashi	0:8fdf9a60065b	120	* \|[5] \|FNO \|Frame Number Overflow
kadonotakashi	0:8fdf9a60065b	121	* \| \| \|This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
kadonotakashi	0:8fdf9a60065b	122	* \| \| \|0 = The bit 15 of Frame Number didn't change.
kadonotakashi	0:8fdf9a60065b	123	* \| \| \|1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
kadonotakashi	0:8fdf9a60065b	124	* \|[6] \|RHSC \|Root Hub Status Change
kadonotakashi	0:8fdf9a60065b	125	* \| \| \|This bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed.
kadonotakashi	0:8fdf9a60065b	126	* \| \| \|0 = The content of HcRhStatus and the content of HcRhPortStatus1 register didn't change.
kadonotakashi	0:8fdf9a60065b	127	* \| \| \|1 = The content of HcRhStatus or the content of HcRhPortStatus1 register has changed.
kadonotakashi	0:8fdf9a60065b	128	* @var USBH_T::HcInterruptEnable
kadonotakashi	0:8fdf9a60065b	129	* Offset: 0x10 Host Controller Interrupt Enable Register
kadonotakashi	0:8fdf9a60065b	130	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	131	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	132	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	133	* \|[0] \|SO \|Scheduling Overrun Enable Bit
kadonotakashi	0:8fdf9a60065b	134	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	135	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	136	* \| \| \|1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
kadonotakashi	0:8fdf9a60065b	137	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	138	* \| \| \|0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
kadonotakashi	0:8fdf9a60065b	139	* \| \| \|1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
kadonotakashi	0:8fdf9a60065b	140	* \|[1] \|WDH \|Write Back Done Head Enable Bit
kadonotakashi	0:8fdf9a60065b	141	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	142	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	143	* \| \| \|1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
kadonotakashi	0:8fdf9a60065b	144	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	145	* \| \| \|0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
kadonotakashi	0:8fdf9a60065b	146	* \| \| \|1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
kadonotakashi	0:8fdf9a60065b	147	* \|[2] \|SF \|Start of Frame Enable Bit
kadonotakashi	0:8fdf9a60065b	148	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	149	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	150	* \| \| \|1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
kadonotakashi	0:8fdf9a60065b	151	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	152	* \| \| \|0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
kadonotakashi	0:8fdf9a60065b	153	* \| \| \|1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
kadonotakashi	0:8fdf9a60065b	154	* \|[3] \|RD \|Resume Detected Enable Bit
kadonotakashi	0:8fdf9a60065b	155	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	156	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	157	* \| \| \|1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
kadonotakashi	0:8fdf9a60065b	158	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	159	* \| \| \|0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
kadonotakashi	0:8fdf9a60065b	160	* \| \| \|1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
kadonotakashi	0:8fdf9a60065b	161	* \|[5] \|FNO \|Frame Number Overflow Enable Bit
kadonotakashi	0:8fdf9a60065b	162	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	163	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	164	* \| \| \|1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
kadonotakashi	0:8fdf9a60065b	165	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	166	* \| \| \|0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
kadonotakashi	0:8fdf9a60065b	167	* \| \| \|1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
kadonotakashi	0:8fdf9a60065b	168	* \|[6] \|RHSC \|Root Hub Status Change Enable Bit
kadonotakashi	0:8fdf9a60065b	169	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	170	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	171	* \| \| \|1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
kadonotakashi	0:8fdf9a60065b	172	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	173	* \| \| \|0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
kadonotakashi	0:8fdf9a60065b	174	* \| \| \|1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
kadonotakashi	0:8fdf9a60065b	175	* \|[31] \|MIE \|Master Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	176	* \| \| \|This bit is a global interrupt enable
kadonotakashi	0:8fdf9a60065b	177	* \| \| \|A write of u20181' allows interrupts to be enabled via the specific enable bits listed above.
kadonotakashi	0:8fdf9a60065b	178	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	179	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	180	* \| \| \|1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
kadonotakashi	0:8fdf9a60065b	181	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	182	* \| \| \|0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
kadonotakashi	0:8fdf9a60065b	183	* \| \| \|1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
kadonotakashi	0:8fdf9a60065b	184	* @var USBH_T::HcInterruptDisable
kadonotakashi	0:8fdf9a60065b	185	* Offset: 0x14 Host Controller Interrupt Disable Register
kadonotakashi	0:8fdf9a60065b	186	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	187	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	188	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	189	* \|[0] \|SO \|Scheduling Overrun Disable Bit
kadonotakashi	0:8fdf9a60065b	190	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	191	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	192	* \| \| \|1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
kadonotakashi	0:8fdf9a60065b	193	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	194	* \| \| \|0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
kadonotakashi	0:8fdf9a60065b	195	* \| \| \|1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
kadonotakashi	0:8fdf9a60065b	196	* \|[1] \|WDH \|Write Back Done Head Disable Bit
kadonotakashi	0:8fdf9a60065b	197	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	198	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	199	* \| \| \|1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
kadonotakashi	0:8fdf9a60065b	200	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	201	* \| \| \|0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
kadonotakashi	0:8fdf9a60065b	202	* \| \| \|1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
kadonotakashi	0:8fdf9a60065b	203	* \|[2] \|SF \|Start of Frame Disable Bit
kadonotakashi	0:8fdf9a60065b	204	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	205	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	206	* \| \| \|1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
kadonotakashi	0:8fdf9a60065b	207	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	208	* \| \| \|0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
kadonotakashi	0:8fdf9a60065b	209	* \| \| \|1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
kadonotakashi	0:8fdf9a60065b	210	* \|[3] \|RD \|Resume Detected Disable Bit
kadonotakashi	0:8fdf9a60065b	211	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	212	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	213	* \| \| \|1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
kadonotakashi	0:8fdf9a60065b	214	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	215	* \| \| \|0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
kadonotakashi	0:8fdf9a60065b	216	* \| \| \|1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
kadonotakashi	0:8fdf9a60065b	217	* \|[5] \|FNO \|Frame Number Overflow Disable Bit
kadonotakashi	0:8fdf9a60065b	218	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	219	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	220	* \| \| \|1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
kadonotakashi	0:8fdf9a60065b	221	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	222	* \| \| \|0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
kadonotakashi	0:8fdf9a60065b	223	* \| \| \|1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
kadonotakashi	0:8fdf9a60065b	224	* \|[6] \|RHSC \|Root Hub Status Change Disable Bit
kadonotakashi	0:8fdf9a60065b	225	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	226	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	227	* \| \| \|1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
kadonotakashi	0:8fdf9a60065b	228	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	229	* \| \| \|0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
kadonotakashi	0:8fdf9a60065b	230	* \| \| \|1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
kadonotakashi	0:8fdf9a60065b	231	* \|[31] \|MIE \|Master Interrupt Disable Bit
kadonotakashi	0:8fdf9a60065b	232	* \| \| \|Global interrupt disable. Writing u20181' to disable all interrupts.
kadonotakashi	0:8fdf9a60065b	233	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	234	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	235	* \| \| \|1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.
kadonotakashi	0:8fdf9a60065b	236	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	237	* \| \| \|0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
kadonotakashi	0:8fdf9a60065b	238	* \| \| \|1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
kadonotakashi	0:8fdf9a60065b	239	* @var USBH_T::HcHCCA
kadonotakashi	0:8fdf9a60065b	240	* Offset: 0x18 Host Controller Communication Area Register
kadonotakashi	0:8fdf9a60065b	241	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	242	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	243	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	244	* \|[31:8] \|HCCA \|Host Controller Communication Area
kadonotakashi	0:8fdf9a60065b	245	* \| \| \|Pointer to indicate base address of the Host Controller Communication Area (HCCA).
kadonotakashi	0:8fdf9a60065b	246	* @var USBH_T::HcPeriodCurrentED
kadonotakashi	0:8fdf9a60065b	247	* Offset: 0x1C Host Controller Period Current ED Register
kadonotakashi	0:8fdf9a60065b	248	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	249	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	250	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	251	* \|[31:4] \|PCED \|Periodic Current ED
kadonotakashi	0:8fdf9a60065b	252	* \| \| \|Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
kadonotakashi	0:8fdf9a60065b	253	* @var USBH_T::HcControlHeadED
kadonotakashi	0:8fdf9a60065b	254	* Offset: 0x20 Host Controller Control Head ED Register
kadonotakashi	0:8fdf9a60065b	255	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	256	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	257	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	258	* \|[31:4] \|CHED \|Control Head ED
kadonotakashi	0:8fdf9a60065b	259	* \| \| \|Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
kadonotakashi	0:8fdf9a60065b	260	* @var USBH_T::HcControlCurrentED
kadonotakashi	0:8fdf9a60065b	261	* Offset: 0x24 Host Controller Control Current ED Register
kadonotakashi	0:8fdf9a60065b	262	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	263	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	264	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	265	* \|[31:4] \|CCED \|Control Current Head ED
kadonotakashi	0:8fdf9a60065b	266	* \| \| \|Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
kadonotakashi	0:8fdf9a60065b	267	* @var USBH_T::HcBulkHeadED
kadonotakashi	0:8fdf9a60065b	268	* Offset: 0x28 Host Controller Bulk Head ED Register
kadonotakashi	0:8fdf9a60065b	269	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	270	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	271	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	272	* \|[31:4] \|BHED \|Bulk Head ED
kadonotakashi	0:8fdf9a60065b	273	* \| \| \|Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
kadonotakashi	0:8fdf9a60065b	274	* @var USBH_T::HcBulkCurrentED
kadonotakashi	0:8fdf9a60065b	275	* Offset: 0x2C Host Controller Bulk Current ED Register
kadonotakashi	0:8fdf9a60065b	276	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	277	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	278	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	279	* \|[31:4] \|BCED \|Bulk Current Head ED
kadonotakashi	0:8fdf9a60065b	280	* \| \| \|Pointer to indicate the physical address of the current endpoint of the Bulk list.
kadonotakashi	0:8fdf9a60065b	281	* @var USBH_T::HcDoneHead
kadonotakashi	0:8fdf9a60065b	282	* Offset: 0x30 Host Controller Done Head Register
kadonotakashi	0:8fdf9a60065b	283	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	284	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	285	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	286	* \|[31:4] \|DH \|Done Head
kadonotakashi	0:8fdf9a60065b	287	* \| \| \|Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
kadonotakashi	0:8fdf9a60065b	288	* @var USBH_T::HcFmInterval
kadonotakashi	0:8fdf9a60065b	289	* Offset: 0x34 Host Controller Frame Interval Register
kadonotakashi	0:8fdf9a60065b	290	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	291	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	292	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	293	* \|[13:0] \|FI \|Frame Interval
kadonotakashi	0:8fdf9a60065b	294	* \| \| \|This field specifies the length of a frame as (bit times - 1)
kadonotakashi	0:8fdf9a60065b	295	* \| \| \|For 12,000 bit times in a frame, a value of 11,999 is stored here.
kadonotakashi	0:8fdf9a60065b	296	* \|[30:16] \|FSMPS \|FS Largest Data Packet
kadonotakashi	0:8fdf9a60065b	297	* \| \| \|This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
kadonotakashi	0:8fdf9a60065b	298	* \|[31] \|FIT \|Frame Interval Toggle
kadonotakashi	0:8fdf9a60065b	299	* \| \| \|This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).
kadonotakashi	0:8fdf9a60065b	300	* \| \| \|0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]).
kadonotakashi	0:8fdf9a60065b	301	* \| \| \|1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]).
kadonotakashi	0:8fdf9a60065b	302	* @var USBH_T::HcFmRemaining
kadonotakashi	0:8fdf9a60065b	303	* Offset: 0x38 Host Controller Frame Remaining Register
kadonotakashi	0:8fdf9a60065b	304	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	305	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	306	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	307	* \|[13:0] \|FR \|Frame Remaining
kadonotakashi	0:8fdf9a60065b	308	* \| \| \|When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period
kadonotakashi	0:8fdf9a60065b	309	* \| \| \|When the count reaches 0, (end of frame) the counter reloads with Frame Interval
kadonotakashi	0:8fdf9a60065b	310	* \| \| \|In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
kadonotakashi	0:8fdf9a60065b	311	* \|[31] \|FRT \|Frame Remaining Toggle
kadonotakashi	0:8fdf9a60065b	312	* \| \| \|This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
kadonotakashi	0:8fdf9a60065b	313	* @var USBH_T::HcFmNumber
kadonotakashi	0:8fdf9a60065b	314	* Offset: 0x3C Host Controller Frame Number Register
kadonotakashi	0:8fdf9a60065b	315	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	316	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	317	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	318	* \|[15:0] \|FN \|Frame Number
kadonotakashi	0:8fdf9a60065b	319	* \| \| \|This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])
kadonotakashi	0:8fdf9a60065b	320	* \| \| \|The count rolls over from u2018FFFFh' to u20180h.'
kadonotakashi	0:8fdf9a60065b	321	* @var USBH_T::HcPeriodicStart
kadonotakashi	0:8fdf9a60065b	322	* Offset: 0x40 Host Controller Periodic Start Register
kadonotakashi	0:8fdf9a60065b	323	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	324	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	325	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	326	* \|[13:0] \|PS \|Periodic Start
kadonotakashi	0:8fdf9a60065b	327	* \| \| \|This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
kadonotakashi	0:8fdf9a60065b	328	* @var USBH_T::HcLSThreshold
kadonotakashi	0:8fdf9a60065b	329	* Offset: 0x44 Host Controller Low-speed Threshold Register
kadonotakashi	0:8fdf9a60065b	330	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	331	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	332	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	333	* \|[11:0] \|LST \|Low-speed Threshold
kadonotakashi	0:8fdf9a60065b	334	* \| \| \|This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction
kadonotakashi	0:8fdf9a60065b	335	* \| \| \|The transaction is started only if FR (HcFmRemaining[13:0]) >= this field
kadonotakashi	0:8fdf9a60065b	336	* \| \| \|The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
kadonotakashi	0:8fdf9a60065b	337	* @var USBH_T::HcRhDescriptorA
kadonotakashi	0:8fdf9a60065b	338	* Offset: 0x48 Host Controller Root Hub Descriptor A Register
kadonotakashi	0:8fdf9a60065b	339	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	340	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	341	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	342	* \|[7:0] \|NDP \|Number Downstream Ports
kadonotakashi	0:8fdf9a60065b	343	* \| \| \|USB host control supports two downstream ports and only one port is available in this series of chip.
kadonotakashi	0:8fdf9a60065b	344	* \|[8] \|PSM \|Power Switching Mode
kadonotakashi	0:8fdf9a60065b	345	* \| \| \|This bit is used to specify how the power switching of the Root Hub ports is controlled.
kadonotakashi	0:8fdf9a60065b	346	* \| \| \|0 = Global Switching.
kadonotakashi	0:8fdf9a60065b	347	* \| \| \|1 = Individual Switching.
kadonotakashi	0:8fdf9a60065b	348	* \|[11] \|OCPM \|over Current Protection Mode
kadonotakashi	0:8fdf9a60065b	349	* \| \| \|This bit describes how the over current status for the Root Hub ports reported
kadonotakashi	0:8fdf9a60065b	350	* \| \| \|This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.
kadonotakashi	0:8fdf9a60065b	351	* \| \| \|0 = Global Over current.
kadonotakashi	0:8fdf9a60065b	352	* \| \| \|1 = Individual Over current.
kadonotakashi	0:8fdf9a60065b	353	* \|[12] \|NOCP \|No over Current Protection
kadonotakashi	0:8fdf9a60065b	354	* \| \| \|This bit describes how the over current status for the Root Hub ports reported.
kadonotakashi	0:8fdf9a60065b	355	* \| \| \|0 = Over current status is reported.
kadonotakashi	0:8fdf9a60065b	356	* \| \| \|1 = Over current status is not reported.
kadonotakashi	0:8fdf9a60065b	357	* @var USBH_T::HcRhDescriptorB
kadonotakashi	0:8fdf9a60065b	358	* Offset: 0x4C Host Controller Root Hub Descriptor B Register
kadonotakashi	0:8fdf9a60065b	359	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	360	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	361	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	362	* \|[31:16] \|PPCM \|Port Power Control Mask
kadonotakashi	0:8fdf9a60065b	363	* \| \| \|Global power switching
kadonotakashi	0:8fdf9a60065b	364	* \| \| \|This field is only valid if PowerSwitchingMode is set (individual port switching)
kadonotakashi	0:8fdf9a60065b	365	* \| \| \|When set, the port only responds to individual port power switching commands (Set/ClearPortPower)
kadonotakashi	0:8fdf9a60065b	366	* \| \| \|When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
kadonotakashi	0:8fdf9a60065b	367	* \| \| \|0 = Port power controlled by global power switching.
kadonotakashi	0:8fdf9a60065b	368	* \| \| \|1 = Port power controlled by port power switching.
kadonotakashi	0:8fdf9a60065b	369	* \| \| \|Note: PPCM[15:2] and PPCM[0] are reserved.
kadonotakashi	0:8fdf9a60065b	370	* @var USBH_T::HcRhStatus
kadonotakashi	0:8fdf9a60065b	371	* Offset: 0x50 Host Controller Root Hub Status Register
kadonotakashi	0:8fdf9a60065b	372	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	373	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	374	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	375	* \|[0] \|LPS \|Clear Global Power
kadonotakashi	0:8fdf9a60065b	376	* \| \| \|In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power.
kadonotakashi	0:8fdf9a60065b	377	* \| \| \|This bit always read as zero.
kadonotakashi	0:8fdf9a60065b	378	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	379	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	380	* \| \| \|1 = Clear global power.
kadonotakashi	0:8fdf9a60065b	381	* \|[1] \|OCI \|over Current Indicator
kadonotakashi	0:8fdf9a60065b	382	* \| \| \|This bit reflects the state of the over current status pin
kadonotakashi	0:8fdf9a60065b	383	* \| \| \|This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
kadonotakashi	0:8fdf9a60065b	384	* \| \| \|0 = No over current condition.
kadonotakashi	0:8fdf9a60065b	385	* \| \| \|1 = Over current condition.
kadonotakashi	0:8fdf9a60065b	386	* \|[15] \|DRWE \|Device Remote Wakeup Enable Bit
kadonotakashi	0:8fdf9a60065b	387	* \| \| \|This bit controls if port's Connect Status Change as a remote wake-up event.
kadonotakashi	0:8fdf9a60065b	388	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	389	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	390	* \| \| \|1 = Connect Status Change as a remote wake-up event Enabled.
kadonotakashi	0:8fdf9a60065b	391	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	392	* \| \| \|0 = Connect Status Change as a remote wake-up event Disabled.
kadonotakashi	0:8fdf9a60065b	393	* \| \| \|1 = Connect Status Change as a remote wake-up event Enabled.
kadonotakashi	0:8fdf9a60065b	394	* \|[16] \|LPSC \|Set Global Power
kadonotakashi	0:8fdf9a60065b	395	* \| \| \|In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports.
kadonotakashi	0:8fdf9a60065b	396	* \| \| \|This bit always read as zero.
kadonotakashi	0:8fdf9a60065b	397	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	398	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	399	* \| \| \|1 = Set global power.
kadonotakashi	0:8fdf9a60065b	400	* \|[17] \|OCIC \|over Current Indicator Change
kadonotakashi	0:8fdf9a60065b	401	* \| \| \|This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).
kadonotakashi	0:8fdf9a60065b	402	* \| \| \|Write 1 to clear this bit to zero.
kadonotakashi	0:8fdf9a60065b	403	* \| \| \|0 = OCI (HcRhStatus[1]) didn't change.
kadonotakashi	0:8fdf9a60065b	404	* \| \| \|1 = OCI (HcRhStatus[1]) change.
kadonotakashi	0:8fdf9a60065b	405	* \|[31] \|CRWE \|Clear Remote Wake-up Enable Bit
kadonotakashi	0:8fdf9a60065b	406	* \| \| \|This bit is use to clear DRWE (HcRhStatus[15]).
kadonotakashi	0:8fdf9a60065b	407	* \| \| \|This bit always read as zero.
kadonotakashi	0:8fdf9a60065b	408	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	409	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	410	* \| \| \|1 = Clear DRWE (HcRhStatus[15]).
kadonotakashi	0:8fdf9a60065b	411	* @var USBH_T::HcRhPortStatus1
kadonotakashi	0:8fdf9a60065b	412	* Offset: 0x54 Host Controller Root Hub Port Status [1]
kadonotakashi	0:8fdf9a60065b	413	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	414	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	415	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	416	* \|[0] \|CCS \|CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)
kadonotakashi	0:8fdf9a60065b	417	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	418	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	419	* \| \| \|1 = Clear port enable.
kadonotakashi	0:8fdf9a60065b	420	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	421	* \| \| \|0 = No device connected.
kadonotakashi	0:8fdf9a60065b	422	* \| \| \|1 = Device connected.
kadonotakashi	0:8fdf9a60065b	423	* \|[1] \|PES \|Port Enable Status
kadonotakashi	0:8fdf9a60065b	424	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	425	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	426	* \| \| \|1 = Set port enable.
kadonotakashi	0:8fdf9a60065b	427	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	428	* \| \| \|0 = Port Disabled.
kadonotakashi	0:8fdf9a60065b	429	* \| \| \|1 = Port Enabled.
kadonotakashi	0:8fdf9a60065b	430	* \|[2] \|PSS \|Port Suspend Status
kadonotakashi	0:8fdf9a60065b	431	* \| \| \|This bit indicates the port is suspended
kadonotakashi	0:8fdf9a60065b	432	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	433	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	434	* \| \| \|1 = Set port suspend.
kadonotakashi	0:8fdf9a60065b	435	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	436	* \| \| \|0 = Port is not suspended.
kadonotakashi	0:8fdf9a60065b	437	* \| \| \|1 = Port is selectively suspended.
kadonotakashi	0:8fdf9a60065b	438	* \|[3] \|POCI \|Port over Current Indicator (Read) or Clear Port Suspend (Write)
kadonotakashi	0:8fdf9a60065b	439	* \| \| \|This bit reflects the state of the over current status pin dedicated to this port
kadonotakashi	0:8fdf9a60065b	440	* \| \| \|This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.
kadonotakashi	0:8fdf9a60065b	441	* \| \| \|This bit is also used to initiate the selective result sequence for the port.
kadonotakashi	0:8fdf9a60065b	442	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	443	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	444	* \| \| \|1 = Clear port suspend.
kadonotakashi	0:8fdf9a60065b	445	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	446	* \| \| \|0 = No over current condition.
kadonotakashi	0:8fdf9a60065b	447	* \| \| \|1 = Over current condition.
kadonotakashi	0:8fdf9a60065b	448	* \|[4] \|PRS \|Port Reset Status
kadonotakashi	0:8fdf9a60065b	449	* \| \| \|This bit reflects the reset state of the port.
kadonotakashi	0:8fdf9a60065b	450	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	451	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	452	* \| \| \|1 = Set port reset.
kadonotakashi	0:8fdf9a60065b	453	* \| \| \|Read Operation
kadonotakashi	0:8fdf9a60065b	454	* \| \| \|0 = Port reset signal is not active.
kadonotakashi	0:8fdf9a60065b	455	* \| \| \|1 = Port reset signal is active.
kadonotakashi	0:8fdf9a60065b	456	* \|[8] \|PPS \|Port Power Status
kadonotakashi	0:8fdf9a60065b	457	* \| \| \|This bit reflects the power state of the port regardless of the power switching mode.
kadonotakashi	0:8fdf9a60065b	458	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	459	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	460	* \| \| \|1 = Port Power Enabled.
kadonotakashi	0:8fdf9a60065b	461	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	462	* \| \| \|0 = Port power is Disabled.
kadonotakashi	0:8fdf9a60065b	463	* \| \| \|1 = Port power is Enabled.
kadonotakashi	0:8fdf9a60065b	464	* \|[9] \|LSDA \|Low Speed Device Attached (Read) or Clear Port Power (Write)
kadonotakashi	0:8fdf9a60065b	465	* \| \| \|This bit defines the speed (and bud idle) of the attached device
kadonotakashi	0:8fdf9a60065b	466	* \| \| \|It is only valid when CCS (HcRhPortStatus1[0]) is set.
kadonotakashi	0:8fdf9a60065b	467	* \| \| \|This bit is also used to clear port power.
kadonotakashi	0:8fdf9a60065b	468	* \| \| \|Write Operation:
kadonotakashi	0:8fdf9a60065b	469	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	470	* \| \| \|1 = Clear PPS (HcRhPortStatus1[8]).
kadonotakashi	0:8fdf9a60065b	471	* \| \| \|Read Operation:
kadonotakashi	0:8fdf9a60065b	472	* \| \| \|0 = Full Speed device.
kadonotakashi	0:8fdf9a60065b	473	* \| \| \|1 = Low-speed device.
kadonotakashi	0:8fdf9a60065b	474	* \|[16] \|CSC \|Connect Status Change
kadonotakashi	0:8fdf9a60065b	475	* \| \| \|This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).
kadonotakashi	0:8fdf9a60065b	476	* \| \| \|Write 1 to clear this bit to zero.
kadonotakashi	0:8fdf9a60065b	477	* \| \| \|0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change).
kadonotakashi	0:8fdf9a60065b	478	* \| \| \|1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed).
kadonotakashi	0:8fdf9a60065b	479	* \|[17] \|PESC \|Port Enable Status Change
kadonotakashi	0:8fdf9a60065b	480	* \| \| \|This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.
kadonotakashi	0:8fdf9a60065b	481	* \| \| \|Write 1 to clear this bit to zero.
kadonotakashi	0:8fdf9a60065b	482	* \| \| \|0 = PES (HcRhPortStatus1[1]) didn't change.
kadonotakashi	0:8fdf9a60065b	483	* \| \| \|1 = PES (HcRhPortStatus1[1]) changed.
kadonotakashi	0:8fdf9a60065b	484	* \|[18] \|PSSC \|Port Suspend Status Change
kadonotakashi	0:8fdf9a60065b	485	* \| \| \|This bit indicates the completion of the selective resume sequence for the port.
kadonotakashi	0:8fdf9a60065b	486	* \| \| \|Write 1 to clear this bit to zero.
kadonotakashi	0:8fdf9a60065b	487	* \| \| \|0 = Port resume is not completed.
kadonotakashi	0:8fdf9a60065b	488	* \| \| \|1 = Port resume completed.
kadonotakashi	0:8fdf9a60065b	489	* \|[19] \|OCIC \|Port over Current Indicator Change
kadonotakashi	0:8fdf9a60065b	490	* \| \| \|This bit is set when POCI (HcRhPortStatus1[3]) changes.
kadonotakashi	0:8fdf9a60065b	491	* \| \| \|Write 1 to clear this bit to zero.
kadonotakashi	0:8fdf9a60065b	492	* \| \| \|0 = POCI (HcRhPortStatus1[3]) didn't change.
kadonotakashi	0:8fdf9a60065b	493	* \| \| \|1 = POCI (HcRhPortStatus1[3]) changes.
kadonotakashi	0:8fdf9a60065b	494	* \|[20] \|PRSC \|Port Reset Status Change
kadonotakashi	0:8fdf9a60065b	495	* \| \| \|This bit indicates that the port reset signal has completed.
kadonotakashi	0:8fdf9a60065b	496	* \| \| \|Write 1 to clear this bit to zero.
kadonotakashi	0:8fdf9a60065b	497	* \| \| \|0 = Port reset is not complete.
kadonotakashi	0:8fdf9a60065b	498	* \| \| \|1 = Port reset is complete.
kadonotakashi	0:8fdf9a60065b	499	* @var USBH_T::HcPhyControl
kadonotakashi	0:8fdf9a60065b	500	* Offset: 0x200 Host Controller PHY Control Register
kadonotakashi	0:8fdf9a60065b	501	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	502	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	503	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	504	* \|[27] \|STBYEN \|USB Transceiver Standby Enable Bit
kadonotakashi	0:8fdf9a60065b	505	* \| \| \|This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
kadonotakashi	0:8fdf9a60065b	506	* \| \| \|0 = The USB transceiver would never enter the standby mode.
kadonotakashi	0:8fdf9a60065b	507	* \| \| \|1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
kadonotakashi	0:8fdf9a60065b	508	* @var USBH_T::HcMiscControl
kadonotakashi	0:8fdf9a60065b	509	* Offset: 0x204 Host Controller Miscellaneous Control Register
kadonotakashi	0:8fdf9a60065b	510	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	511	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	512	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	513	* \|[1] \|ABORT \|AHB Bus ERROR Response
kadonotakashi	0:8fdf9a60065b	514	* \| \| \|This bit indicates there is an ERROR response received in AHB bus.
kadonotakashi	0:8fdf9a60065b	515	* \| \| \|0 = No ERROR response received.
kadonotakashi	0:8fdf9a60065b	516	* \| \| \|1 = ERROR response received.
kadonotakashi	0:8fdf9a60065b	517	* \|[3] \|OCAL \|over Current Active Low
kadonotakashi	0:8fdf9a60065b	518	* \| \| \|This bit controls the polarity of over current flag from external power IC.
kadonotakashi	0:8fdf9a60065b	519	* \| \| \|0 = Over current flag is high active.
kadonotakashi	0:8fdf9a60065b	520	* \| \| \|1 = Over current flag is low active.
kadonotakashi	0:8fdf9a60065b	521	* \|[16] \|DPRT1 \|Disable Port 1
kadonotakashi	0:8fdf9a60065b	522	* \| \| \|This bit controls if the connection between USB host controller and transceiver of port 1 is disabled
kadonotakashi	0:8fdf9a60065b	523	* \| \| \|If the connection is disabled, the USB host controller will not recognize any event of USB bus.
kadonotakashi	0:8fdf9a60065b	524	* \| \| \|Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
kadonotakashi	0:8fdf9a60065b	525	* \| \| \|0 = The connection between USB host controller and transceiver of port 1 Enabled.
kadonotakashi	0:8fdf9a60065b	526	* \| \| \|1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode.
kadonotakashi	0:8fdf9a60065b	527	*/
kadonotakashi	0:8fdf9a60065b	528	__I uint32_t HcRevision; /!< [0x0000] Host Controller Revision Register /
kadonotakashi	0:8fdf9a60065b	529	__IO uint32_t HcControl; /!< [0x0004] Host Controller Control Register /
kadonotakashi	0:8fdf9a60065b	530	__IO uint32_t HcCommandStatus; /!< [0x0008] Host Controller Command Status Register /
kadonotakashi	0:8fdf9a60065b	531	__IO uint32_t HcInterruptStatus; /!< [0x000c] Host Controller Interrupt Status Register /
kadonotakashi	0:8fdf9a60065b	532	__IO uint32_t HcInterruptEnable; /!< [0x0010] Host Controller Interrupt Enable Register /
kadonotakashi	0:8fdf9a60065b	533	__IO uint32_t HcInterruptDisable; /!< [0x0014] Host Controller Interrupt Disable Register /
kadonotakashi	0:8fdf9a60065b	534	__IO uint32_t HcHCCA; /!< [0x0018] Host Controller Communication Area Register /
kadonotakashi	0:8fdf9a60065b	535	__IO uint32_t HcPeriodCurrentED; /!< [0x001c] Host Controller Period Current ED Register /
kadonotakashi	0:8fdf9a60065b	536	__IO uint32_t HcControlHeadED; /!< [0x0020] Host Controller Control Head ED Register /
kadonotakashi	0:8fdf9a60065b	537	__IO uint32_t HcControlCurrentED; /!< [0x0024] Host Controller Control Current ED Register /
kadonotakashi	0:8fdf9a60065b	538	__IO uint32_t HcBulkHeadED; /!< [0x0028] Host Controller Bulk Head ED Register /
kadonotakashi	0:8fdf9a60065b	539	__IO uint32_t HcBulkCurrentED; /!< [0x002c] Host Controller Bulk Current ED Register /
kadonotakashi	0:8fdf9a60065b	540	__IO uint32_t HcDoneHead; /!< [0x0030] Host Controller Done Head Register /
kadonotakashi	0:8fdf9a60065b	541	__IO uint32_t HcFmInterval; /!< [0x0034] Host Controller Frame Interval Register /
kadonotakashi	0:8fdf9a60065b	542	__I uint32_t HcFmRemaining; /!< [0x0038] Host Controller Frame Remaining Register /
kadonotakashi	0:8fdf9a60065b	543	__I uint32_t HcFmNumber; /!< [0x003c] Host Controller Frame Number Register /
kadonotakashi	0:8fdf9a60065b	544	__IO uint32_t HcPeriodicStart; /!< [0x0040] Host Controller Periodic Start Register /
kadonotakashi	0:8fdf9a60065b	545	__IO uint32_t HcLSThreshold; /!< [0x0044] Host Controller Low-speed Threshold Register /
kadonotakashi	0:8fdf9a60065b	546	__IO uint32_t HcRhDescriptorA; /!< [0x0048] Host Controller Root Hub Descriptor A Register /
kadonotakashi	0:8fdf9a60065b	547	__IO uint32_t HcRhDescriptorB; /!< [0x004c] Host Controller Root Hub Descriptor B Register /
kadonotakashi	0:8fdf9a60065b	548	__IO uint32_t HcRhStatus; /!< [0x0050] Host Controller Root Hub Status Register /
kadonotakashi	0:8fdf9a60065b	549	__IO uint32_t HcRhPortStatus1; /!< [0x0054] Host Controller Root Hub Port Status [1] /
kadonotakashi	0:8fdf9a60065b	550	__I uint32_t RESERVE0[106];
kadonotakashi	0:8fdf9a60065b	551	__IO uint32_t HcPhyControl; /!< [0x0200] Host Controller PHY Control Register /
kadonotakashi	0:8fdf9a60065b	552	__IO uint32_t HcMiscControl; /!< [0x0204] Host Controller Miscellaneous Control Register /
kadonotakashi	0:8fdf9a60065b	553
kadonotakashi	0:8fdf9a60065b	554	} USBH_T;
kadonotakashi	0:8fdf9a60065b	555
kadonotakashi	0:8fdf9a60065b	556	/**
kadonotakashi	0:8fdf9a60065b	557	@addtogroup USBH_CONST USBH Bit Field Definition
kadonotakashi	0:8fdf9a60065b	558	Constant Definitions for USBH Controller
kadonotakashi	0:8fdf9a60065b	559	@{ */
kadonotakashi	0:8fdf9a60065b	560
kadonotakashi	0:8fdf9a60065b	561	#define USBH_HcRevision_REV_Pos (0) /!< USBH_T::HcRevision: REV Position /
kadonotakashi	0:8fdf9a60065b	562	#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /!< USBH_T::HcRevision: REV Mask /
kadonotakashi	0:8fdf9a60065b	563
kadonotakashi	0:8fdf9a60065b	564	#define USBH_HcControl_CBSR_Pos (0) /!< USBH_T::HcControl: CBSR Position /
kadonotakashi	0:8fdf9a60065b	565	#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /!< USBH_T::HcControl: CBSR Mask /
kadonotakashi	0:8fdf9a60065b	566
kadonotakashi	0:8fdf9a60065b	567	#define USBH_HcControl_PLE_Pos (2) /!< USBH_T::HcControl: PLE Position /
kadonotakashi	0:8fdf9a60065b	568	#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /!< USBH_T::HcControl: PLE Mask /
kadonotakashi	0:8fdf9a60065b	569
kadonotakashi	0:8fdf9a60065b	570	#define USBH_HcControl_IE_Pos (3) /!< USBH_T::HcControl: IE Position /
kadonotakashi	0:8fdf9a60065b	571	#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /!< USBH_T::HcControl: IE Mask /
kadonotakashi	0:8fdf9a60065b	572
kadonotakashi	0:8fdf9a60065b	573	#define USBH_HcControl_CLE_Pos (4) /!< USBH_T::HcControl: CLE Position /
kadonotakashi	0:8fdf9a60065b	574	#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /!< USBH_T::HcControl: CLE Mask /
kadonotakashi	0:8fdf9a60065b	575
kadonotakashi	0:8fdf9a60065b	576	#define USBH_HcControl_BLE_Pos (5) /!< USBH_T::HcControl: BLE Position /
kadonotakashi	0:8fdf9a60065b	577	#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /!< USBH_T::HcControl: BLE Mask /
kadonotakashi	0:8fdf9a60065b	578
kadonotakashi	0:8fdf9a60065b	579	#define USBH_HcControl_HCFS_Pos (6) /!< USBH_T::HcControl: HCFS Position /
kadonotakashi	0:8fdf9a60065b	580	#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /!< USBH_T::HcControl: HCFS Mask /
kadonotakashi	0:8fdf9a60065b	581
kadonotakashi	0:8fdf9a60065b	582	#define USBH_HcCommandStatus_HCR_Pos (0) /!< USBH_T::HcCommandStatus: HCR Position /
kadonotakashi	0:8fdf9a60065b	583	#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /!< USBH_T::HcCommandStatus: HCR Mask /
kadonotakashi	0:8fdf9a60065b	584
kadonotakashi	0:8fdf9a60065b	585	#define USBH_HcCommandStatus_CLF_Pos (1) /!< USBH_T::HcCommandStatus: CLF Position /
kadonotakashi	0:8fdf9a60065b	586	#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /!< USBH_T::HcCommandStatus: CLF Mask /
kadonotakashi	0:8fdf9a60065b	587
kadonotakashi	0:8fdf9a60065b	588	#define USBH_HcCommandStatus_BLF_Pos (2) /!< USBH_T::HcCommandStatus: BLF Position /
kadonotakashi	0:8fdf9a60065b	589	#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /!< USBH_T::HcCommandStatus: BLF Mask /
kadonotakashi	0:8fdf9a60065b	590
kadonotakashi	0:8fdf9a60065b	591	#define USBH_HcCommandStatus_SOC_Pos (16) /!< USBH_T::HcCommandStatus: SOC Position /
kadonotakashi	0:8fdf9a60065b	592	#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /!< USBH_T::HcCommandStatus: SOC Mask /
kadonotakashi	0:8fdf9a60065b	593
kadonotakashi	0:8fdf9a60065b	594	#define USBH_HcInterruptStatus_SO_Pos (0) /!< USBH_T::HcInterruptStatus: SO Position /
kadonotakashi	0:8fdf9a60065b	595	#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /!< USBH_T::HcInterruptStatus: SO Mask /
kadonotakashi	0:8fdf9a60065b	596
kadonotakashi	0:8fdf9a60065b	597	#define USBH_HcInterruptStatus_WDH_Pos (1) /!< USBH_T::HcInterruptStatus: WDH Position/
kadonotakashi	0:8fdf9a60065b	598	#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /!< USBH_T::HcInterruptStatus: WDH Mask /
kadonotakashi	0:8fdf9a60065b	599
kadonotakashi	0:8fdf9a60065b	600	#define USBH_HcInterruptStatus_SF_Pos (2) /!< USBH_T::HcInterruptStatus: SF Position /
kadonotakashi	0:8fdf9a60065b	601	#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /!< USBH_T::HcInterruptStatus: SF Mask /
kadonotakashi	0:8fdf9a60065b	602
kadonotakashi	0:8fdf9a60065b	603	#define USBH_HcInterruptStatus_RD_Pos (3) /!< USBH_T::HcInterruptStatus: RD Position /
kadonotakashi	0:8fdf9a60065b	604	#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /!< USBH_T::HcInterruptStatus: RD Mask /
kadonotakashi	0:8fdf9a60065b	605
kadonotakashi	0:8fdf9a60065b	606	#define USBH_HcInterruptStatus_FNO_Pos (5) /!< USBH_T::HcInterruptStatus: FNO Position/
kadonotakashi	0:8fdf9a60065b	607	#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /!< USBH_T::HcInterruptStatus: FNO Mask /
kadonotakashi	0:8fdf9a60065b	608
kadonotakashi	0:8fdf9a60065b	609	#define USBH_HcInterruptStatus_RHSC_Pos (6) /!< USBH_T::HcInterruptStatus: RHSC Position/
kadonotakashi	0:8fdf9a60065b	610	#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /!< USBH_T::HcInterruptStatus: RHSC Mask /
kadonotakashi	0:8fdf9a60065b	611
kadonotakashi	0:8fdf9a60065b	612	#define USBH_HcInterruptEnable_SO_Pos (0) /!< USBH_T::HcInterruptEnable: SO Position /
kadonotakashi	0:8fdf9a60065b	613	#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /!< USBH_T::HcInterruptEnable: SO Mask /
kadonotakashi	0:8fdf9a60065b	614
kadonotakashi	0:8fdf9a60065b	615	#define USBH_HcInterruptEnable_WDH_Pos (1) /!< USBH_T::HcInterruptEnable: WDH Position/
kadonotakashi	0:8fdf9a60065b	616	#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /!< USBH_T::HcInterruptEnable: WDH Mask /
kadonotakashi	0:8fdf9a60065b	617
kadonotakashi	0:8fdf9a60065b	618	#define USBH_HcInterruptEnable_SF_Pos (2) /!< USBH_T::HcInterruptEnable: SF Position /
kadonotakashi	0:8fdf9a60065b	619	#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /!< USBH_T::HcInterruptEnable: SF Mask /
kadonotakashi	0:8fdf9a60065b	620
kadonotakashi	0:8fdf9a60065b	621	#define USBH_HcInterruptEnable_RD_Pos (3) /!< USBH_T::HcInterruptEnable: RD Position /
kadonotakashi	0:8fdf9a60065b	622	#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /!< USBH_T::HcInterruptEnable: RD Mask /
kadonotakashi	0:8fdf9a60065b	623
kadonotakashi	0:8fdf9a60065b	624	#define USBH_HcInterruptEnable_FNO_Pos (5) /!< USBH_T::HcInterruptEnable: FNO Position/
kadonotakashi	0:8fdf9a60065b	625	#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /!< USBH_T::HcInterruptEnable: FNO Mask /
kadonotakashi	0:8fdf9a60065b	626
kadonotakashi	0:8fdf9a60065b	627	#define USBH_HcInterruptEnable_RHSC_Pos (6) /!< USBH_T::HcInterruptEnable: RHSC Position/
kadonotakashi	0:8fdf9a60065b	628	#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /!< USBH_T::HcInterruptEnable: RHSC Mask /
kadonotakashi	0:8fdf9a60065b	629
kadonotakashi	0:8fdf9a60065b	630	#define USBH_HcInterruptEnable_MIE_Pos (31) /!< USBH_T::HcInterruptEnable: MIE Position/
kadonotakashi	0:8fdf9a60065b	631	#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /!< USBH_T::HcInterruptEnable: MIE Mask /
kadonotakashi	0:8fdf9a60065b	632
kadonotakashi	0:8fdf9a60065b	633	#define USBH_HcInterruptDisable_SO_Pos (0) /!< USBH_T::HcInterruptDisable: SO Position/
kadonotakashi	0:8fdf9a60065b	634	#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /!< USBH_T::HcInterruptDisable: SO Mask /
kadonotakashi	0:8fdf9a60065b	635
kadonotakashi	0:8fdf9a60065b	636	#define USBH_HcInterruptDisable_WDH_Pos (1) /!< USBH_T::HcInterruptDisable: WDH Position/
kadonotakashi	0:8fdf9a60065b	637	#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /!< USBH_T::HcInterruptDisable: WDH Mask /
kadonotakashi	0:8fdf9a60065b	638
kadonotakashi	0:8fdf9a60065b	639	#define USBH_HcInterruptDisable_SF_Pos (2) /!< USBH_T::HcInterruptDisable: SF Position/
kadonotakashi	0:8fdf9a60065b	640	#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /!< USBH_T::HcInterruptDisable: SF Mask /
kadonotakashi	0:8fdf9a60065b	641
kadonotakashi	0:8fdf9a60065b	642	#define USBH_HcInterruptDisable_RD_Pos (3) /!< USBH_T::HcInterruptDisable: RD Position/
kadonotakashi	0:8fdf9a60065b	643	#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /!< USBH_T::HcInterruptDisable: RD Mask /
kadonotakashi	0:8fdf9a60065b	644
kadonotakashi	0:8fdf9a60065b	645	#define USBH_HcInterruptDisable_FNO_Pos (5) /!< USBH_T::HcInterruptDisable: FNO Position/
kadonotakashi	0:8fdf9a60065b	646	#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /!< USBH_T::HcInterruptDisable: FNO Mask /
kadonotakashi	0:8fdf9a60065b	647
kadonotakashi	0:8fdf9a60065b	648	#define USBH_HcInterruptDisable_RHSC_Pos (6) /!< USBH_T::HcInterruptDisable: RHSC Position/
kadonotakashi	0:8fdf9a60065b	649	#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /!< USBH_T::HcInterruptDisable: RHSC Mask /
kadonotakashi	0:8fdf9a60065b	650
kadonotakashi	0:8fdf9a60065b	651	#define USBH_HcInterruptDisable_MIE_Pos (31) /!< USBH_T::HcInterruptDisable: MIE Position/
kadonotakashi	0:8fdf9a60065b	652	#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /!< USBH_T::HcInterruptDisable: MIE Mask /
kadonotakashi	0:8fdf9a60065b	653
kadonotakashi	0:8fdf9a60065b	654	#define USBH_HcHCCA_HCCA_Pos (8) /!< USBH_T::HcHCCA: HCCA Position /
kadonotakashi	0:8fdf9a60065b	655	#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /!< USBH_T::HcHCCA: HCCA Mask /
kadonotakashi	0:8fdf9a60065b	656
kadonotakashi	0:8fdf9a60065b	657	#define USBH_HcPeriodCurrentED_PCED_Pos (4) /!< USBH_T::HcPeriodCurrentED: PCED Position/
kadonotakashi	0:8fdf9a60065b	658	#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /!< USBH_T::HcPeriodCurrentED: PCED Mask /
kadonotakashi	0:8fdf9a60065b	659
kadonotakashi	0:8fdf9a60065b	660	#define USBH_HcControlHeadED_CHED_Pos (4) /!< USBH_T::HcControlHeadED: CHED Position /
kadonotakashi	0:8fdf9a60065b	661	#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /!< USBH_T::HcControlHeadED: CHED Mask /
kadonotakashi	0:8fdf9a60065b	662
kadonotakashi	0:8fdf9a60065b	663	#define USBH_HcControlCurrentED_CCED_Pos (4) /!< USBH_T::HcControlCurrentED: CCED Position/
kadonotakashi	0:8fdf9a60065b	664	#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /!< USBH_T::HcControlCurrentED: CCED Mask /
kadonotakashi	0:8fdf9a60065b	665
kadonotakashi	0:8fdf9a60065b	666	#define USBH_HcBulkHeadED_BHED_Pos (4) /!< USBH_T::HcBulkHeadED: BHED Position /
kadonotakashi	0:8fdf9a60065b	667	#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /!< USBH_T::HcBulkHeadED: BHED Mask /
kadonotakashi	0:8fdf9a60065b	668
kadonotakashi	0:8fdf9a60065b	669	#define USBH_HcBulkCurrentED_BCED_Pos (4) /!< USBH_T::HcBulkCurrentED: BCED Position /
kadonotakashi	0:8fdf9a60065b	670	#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /!< USBH_T::HcBulkCurrentED: BCED Mask /
kadonotakashi	0:8fdf9a60065b	671
kadonotakashi	0:8fdf9a60065b	672	#define USBH_HcDoneHead_DH_Pos (4) /!< USBH_T::HcDoneHead: DH Position /
kadonotakashi	0:8fdf9a60065b	673	#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /!< USBH_T::HcDoneHead: DH Mask /
kadonotakashi	0:8fdf9a60065b	674
kadonotakashi	0:8fdf9a60065b	675	#define USBH_HcFmInterval_FI_Pos (0) /!< USBH_T::HcFmInterval: FI Position /
kadonotakashi	0:8fdf9a60065b	676	#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /!< USBH_T::HcFmInterval: FI Mask /
kadonotakashi	0:8fdf9a60065b	677
kadonotakashi	0:8fdf9a60065b	678	#define USBH_HcFmInterval_FSMPS_Pos (16) /!< USBH_T::HcFmInterval: FSMPS Position /
kadonotakashi	0:8fdf9a60065b	679	#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /!< USBH_T::HcFmInterval: FSMPS Mask /
kadonotakashi	0:8fdf9a60065b	680
kadonotakashi	0:8fdf9a60065b	681	#define USBH_HcFmInterval_FIT_Pos (31) /!< USBH_T::HcFmInterval: FIT Position /
kadonotakashi	0:8fdf9a60065b	682	#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /!< USBH_T::HcFmInterval: FIT Mask /
kadonotakashi	0:8fdf9a60065b	683
kadonotakashi	0:8fdf9a60065b	684	#define USBH_HcFmRemaining_FR_Pos (0) /!< USBH_T::HcFmRemaining: FR Position /
kadonotakashi	0:8fdf9a60065b	685	#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /!< USBH_T::HcFmRemaining: FR Mask /
kadonotakashi	0:8fdf9a60065b	686
kadonotakashi	0:8fdf9a60065b	687	#define USBH_HcFmRemaining_FRT_Pos (31) /!< USBH_T::HcFmRemaining: FRT Position /
kadonotakashi	0:8fdf9a60065b	688	#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /!< USBH_T::HcFmRemaining: FRT Mask /
kadonotakashi	0:8fdf9a60065b	689
kadonotakashi	0:8fdf9a60065b	690	#define USBH_HcFmNumber_FN_Pos (0) /!< USBH_T::HcFmNumber: FN Position /
kadonotakashi	0:8fdf9a60065b	691	#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /!< USBH_T::HcFmNumber: FN Mask /
kadonotakashi	0:8fdf9a60065b	692
kadonotakashi	0:8fdf9a60065b	693	#define USBH_HcPeriodicStart_PS_Pos (0) /!< USBH_T::HcPeriodicStart: PS Position /
kadonotakashi	0:8fdf9a60065b	694	#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /!< USBH_T::HcPeriodicStart: PS Mask /
kadonotakashi	0:8fdf9a60065b	695
kadonotakashi	0:8fdf9a60065b	696	#define USBH_HcLSThreshold_LST_Pos (0) /!< USBH_T::HcLSThreshold: LST Position /
kadonotakashi	0:8fdf9a60065b	697	#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /!< USBH_T::HcLSThreshold: LST Mask /
kadonotakashi	0:8fdf9a60065b	698
kadonotakashi	0:8fdf9a60065b	699	#define USBH_HcRhDescriptorA_NDP_Pos (0) /!< USBH_T::HcRhDescriptorA: NDP Position /
kadonotakashi	0:8fdf9a60065b	700	#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /!< USBH_T::HcRhDescriptorA: NDP Mask /
kadonotakashi	0:8fdf9a60065b	701
kadonotakashi	0:8fdf9a60065b	702	#define USBH_HcRhDescriptorA_PSM_Pos (8) /!< USBH_T::HcRhDescriptorA: PSM Position /
kadonotakashi	0:8fdf9a60065b	703	#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /!< USBH_T::HcRhDescriptorA: PSM Mask /
kadonotakashi	0:8fdf9a60065b	704
kadonotakashi	0:8fdf9a60065b	705	#define USBH_HcRhDescriptorA_OCPM_Pos (11) /!< USBH_T::HcRhDescriptorA: OCPM Position /
kadonotakashi	0:8fdf9a60065b	706	#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /!< USBH_T::HcRhDescriptorA: OCPM Mask /
kadonotakashi	0:8fdf9a60065b	707
kadonotakashi	0:8fdf9a60065b	708	#define USBH_HcRhDescriptorA_NOCP_Pos (12) /!< USBH_T::HcRhDescriptorA: NOCP Position /
kadonotakashi	0:8fdf9a60065b	709	#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /!< USBH_T::HcRhDescriptorA: NOCP Mask /
kadonotakashi	0:8fdf9a60065b	710
kadonotakashi	0:8fdf9a60065b	711	#define USBH_HcRhDescriptorB_PPCM_Pos (16) /!< USBH_T::HcRhDescriptorB: PPCM Position /
kadonotakashi	0:8fdf9a60065b	712	#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /!< USBH_T::HcRhDescriptorB: PPCM Mask /
kadonotakashi	0:8fdf9a60065b	713
kadonotakashi	0:8fdf9a60065b	714	#define USBH_HcRhStatus_LPS_Pos (0) /!< USBH_T::HcRhStatus: LPS Position /
kadonotakashi	0:8fdf9a60065b	715	#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /!< USBH_T::HcRhStatus: LPS Mask /
kadonotakashi	0:8fdf9a60065b	716
kadonotakashi	0:8fdf9a60065b	717	#define USBH_HcRhStatus_OCI_Pos (1) /!< USBH_T::HcRhStatus: OCI Position /
kadonotakashi	0:8fdf9a60065b	718	#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /!< USBH_T::HcRhStatus: OCI Mask /
kadonotakashi	0:8fdf9a60065b	719
kadonotakashi	0:8fdf9a60065b	720	#define USBH_HcRhStatus_DRWE_Pos (15) /!< USBH_T::HcRhStatus: DRWE Position /
kadonotakashi	0:8fdf9a60065b	721	#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /!< USBH_T::HcRhStatus: DRWE Mask /
kadonotakashi	0:8fdf9a60065b	722
kadonotakashi	0:8fdf9a60065b	723	#define USBH_HcRhStatus_LPSC_Pos (16) /!< USBH_T::HcRhStatus: LPSC Position /
kadonotakashi	0:8fdf9a60065b	724	#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /!< USBH_T::HcRhStatus: LPSC Mask /
kadonotakashi	0:8fdf9a60065b	725
kadonotakashi	0:8fdf9a60065b	726	#define USBH_HcRhStatus_OCIC_Pos (17) /!< USBH_T::HcRhStatus: OCIC Position /
kadonotakashi	0:8fdf9a60065b	727	#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /!< USBH_T::HcRhStatus: OCIC Mask /
kadonotakashi	0:8fdf9a60065b	728
kadonotakashi	0:8fdf9a60065b	729	#define USBH_HcRhStatus_CRWE_Pos (31) /!< USBH_T::HcRhStatus: CRWE Position /
kadonotakashi	0:8fdf9a60065b	730	#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /!< USBH_T::HcRhStatus: CRWE Mask /
kadonotakashi	0:8fdf9a60065b	731
kadonotakashi	0:8fdf9a60065b	732	#define USBH_HcRhPortStatus1_CCS_Pos (0) /!< USBH_T::HcRhPortStatus1: CCS Position /
kadonotakashi	0:8fdf9a60065b	733	#define USBH_HcRhPortStatus1_CCS_Msk (0x1ul << USBH_HcRhPortStatus1_CCS_Pos) /!< USBH_T::HcRhPortStatus1: CCS Mask /
kadonotakashi	0:8fdf9a60065b	734
kadonotakashi	0:8fdf9a60065b	735	#define USBH_HcRhPortStatus1_PES_Pos (1) /!< USBH_T::HcRhPortStatus1: PES Position /
kadonotakashi	0:8fdf9a60065b	736	#define USBH_HcRhPortStatus1_PES_Msk (0x1ul << USBH_HcRhPortStatus1_PES_Pos) /!< USBH_T::HcRhPortStatus1: PES Mask /
kadonotakashi	0:8fdf9a60065b	737
kadonotakashi	0:8fdf9a60065b	738	#define USBH_HcRhPortStatus1_PSS_Pos (2) /!< USBH_T::HcRhPortStatus1: PSS Position /
kadonotakashi	0:8fdf9a60065b	739	#define USBH_HcRhPortStatus1_PSS_Msk (0x1ul << USBH_HcRhPortStatus1_PSS_Pos) /!< USBH_T::HcRhPortStatus1: PSS Mask /
kadonotakashi	0:8fdf9a60065b	740
kadonotakashi	0:8fdf9a60065b	741	#define USBH_HcRhPortStatus1_POCI_Pos (3) /!< USBH_T::HcRhPortStatus1: POCI Position /
kadonotakashi	0:8fdf9a60065b	742	#define USBH_HcRhPortStatus1_POCI_Msk (0x1ul << USBH_HcRhPortStatus1_POCI_Pos) /!< USBH_T::HcRhPortStatus1: POCI Mask /
kadonotakashi	0:8fdf9a60065b	743
kadonotakashi	0:8fdf9a60065b	744	#define USBH_HcRhPortStatus1_PRS_Pos (4) /!< USBH_T::HcRhPortStatus1: PRS Position /
kadonotakashi	0:8fdf9a60065b	745	#define USBH_HcRhPortStatus1_PRS_Msk (0x1ul << USBH_HcRhPortStatus1_PRS_Pos) /!< USBH_T::HcRhPortStatus1: PRS Mask /
kadonotakashi	0:8fdf9a60065b	746
kadonotakashi	0:8fdf9a60065b	747	#define USBH_HcRhPortStatus1_PPS_Pos (8) /!< USBH_T::HcRhPortStatus1: PPS Position /
kadonotakashi	0:8fdf9a60065b	748	#define USBH_HcRhPortStatus1_PPS_Msk (0x1ul << USBH_HcRhPortStatus1_PPS_Pos) /!< USBH_T::HcRhPortStatus1: PPS Mask /
kadonotakashi	0:8fdf9a60065b	749
kadonotakashi	0:8fdf9a60065b	750	#define USBH_HcRhPortStatus1_LSDA_Pos (9) /!< USBH_T::HcRhPortStatus1: LSDA Position /
kadonotakashi	0:8fdf9a60065b	751	#define USBH_HcRhPortStatus1_LSDA_Msk (0x1ul << USBH_HcRhPortStatus1_LSDA_Pos) /!< USBH_T::HcRhPortStatus1: LSDA Mask /
kadonotakashi	0:8fdf9a60065b	752
kadonotakashi	0:8fdf9a60065b	753	#define USBH_HcRhPortStatus1_CSC_Pos (16) /!< USBH_T::HcRhPortStatus1: CSC Position /
kadonotakashi	0:8fdf9a60065b	754	#define USBH_HcRhPortStatus1_CSC_Msk (0x1ul << USBH_HcRhPortStatus1_CSC_Pos) /!< USBH_T::HcRhPortStatus1: CSC Mask /
kadonotakashi	0:8fdf9a60065b	755
kadonotakashi	0:8fdf9a60065b	756	#define USBH_HcRhPortStatus1_PESC_Pos (17) /!< USBH_T::HcRhPortStatus1: PESC Position /
kadonotakashi	0:8fdf9a60065b	757	#define USBH_HcRhPortStatus1_PESC_Msk (0x1ul << USBH_HcRhPortStatus1_PESC_Pos) /!< USBH_T::HcRhPortStatus1: PESC Mask /
kadonotakashi	0:8fdf9a60065b	758
kadonotakashi	0:8fdf9a60065b	759	#define USBH_HcRhPortStatus1_PSSC_Pos (18) /!< USBH_T::HcRhPortStatus1: PSSC Position /
kadonotakashi	0:8fdf9a60065b	760	#define USBH_HcRhPortStatus1_PSSC_Msk (0x1ul << USBH_HcRhPortStatus1_PSSC_Pos) /!< USBH_T::HcRhPortStatus1: PSSC Mask /
kadonotakashi	0:8fdf9a60065b	761
kadonotakashi	0:8fdf9a60065b	762	#define USBH_HcRhPortStatus1_OCIC_Pos (19) /!< USBH_T::HcRhPortStatus1: OCIC Position /
kadonotakashi	0:8fdf9a60065b	763	#define USBH_HcRhPortStatus1_OCIC_Msk (0x1ul << USBH_HcRhPortStatus1_OCIC_Pos) /!< USBH_T::HcRhPortStatus1: OCIC Mask /
kadonotakashi	0:8fdf9a60065b	764
kadonotakashi	0:8fdf9a60065b	765	#define USBH_HcRhPortStatus1_PRSC_Pos (20) /!< USBH_T::HcRhPortStatus1: PRSC Position /
kadonotakashi	0:8fdf9a60065b	766	#define USBH_HcRhPortStatus1_PRSC_Msk (0x1ul << USBH_HcRhPortStatus1_PRSC_Pos) /!< USBH_T::HcRhPortStatus1: PRSC Mask /
kadonotakashi	0:8fdf9a60065b	767
kadonotakashi	0:8fdf9a60065b	768	#define USBH_HcPhyControl_STBYEN_Pos (27) /!< USBH_T::HcPhyControl: STBYEN Position /
kadonotakashi	0:8fdf9a60065b	769	#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /!< USBH_T::HcPhyControl: STBYEN Mask /
kadonotakashi	0:8fdf9a60065b	770
kadonotakashi	0:8fdf9a60065b	771	#define USBH_HcMiscControl_ABORT_Pos (1) /!< USBH_T::HcMiscControl: ABORT Position /
kadonotakashi	0:8fdf9a60065b	772	#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /!< USBH_T::HcMiscControl: ABORT Mask /
kadonotakashi	0:8fdf9a60065b	773
kadonotakashi	0:8fdf9a60065b	774	#define USBH_HcMiscControl_OCAL_Pos (3) /!< USBH_T::HcMiscControl: OCAL Position /
kadonotakashi	0:8fdf9a60065b	775	#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /!< USBH_T::HcMiscControl: OCAL Mask /
kadonotakashi	0:8fdf9a60065b	776
kadonotakashi	0:8fdf9a60065b	777	#define USBH_HcMiscControl_DPRT1_Pos (16) /!< USBH_T::HcMiscControl: DPRT1 Position /
kadonotakashi	0:8fdf9a60065b	778	#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /!< USBH_T::HcMiscControl: DPRT1 Mask /
kadonotakashi	0:8fdf9a60065b	779
kadonotakashi	0:8fdf9a60065b	780	/*@}/ /* USBH_CONST */
kadonotakashi	0:8fdf9a60065b	781	/*@}/ /* end of USBH register group */
kadonotakashi	0:8fdf9a60065b	782
kadonotakashi	0:8fdf9a60065b	783	#endif /* __USBH_REG_H__ */

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Type:	Program
Mbed OS support:	Mbed OS
Created:	11 Oct 2018
Imports:	15
Forks:	0
Commits:	4
Dependents:	0
Dependencies:	1
Followers:	1

mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/usbh_reg.h@3:f3764f852aa8, 2018-10-11 (annotated)

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