takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/spi5_reg.h@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /**************************************************************************//**
kadonotakashi 0:8fdf9a60065b 2 * @file spi5_reg.h
kadonotakashi 0:8fdf9a60065b 3 * @version V1.00
kadonotakashi 0:8fdf9a60065b 4 * @brief SPI5 register definition header file
kadonotakashi 0:8fdf9a60065b 5 *
kadonotakashi 0:8fdf9a60065b 6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
kadonotakashi 0:8fdf9a60065b 7 *****************************************************************************/
kadonotakashi 0:8fdf9a60065b 8 #ifndef __SPI5_REG_H__
kadonotakashi 0:8fdf9a60065b 9 #define __SPI5_REG_H__
kadonotakashi 0:8fdf9a60065b 10
kadonotakashi 0:8fdf9a60065b 11 /*---------------------- DSRC Serial Peripheral Interface Controller -------------------------*/
kadonotakashi 0:8fdf9a60065b 12 /**
kadonotakashi 0:8fdf9a60065b 13 @addtogroup SPI5 DSRC Serial Peripheral Interface Controller(SPI5)
kadonotakashi 0:8fdf9a60065b 14 Memory Mapped Structure for SPI5 Controller
kadonotakashi 0:8fdf9a60065b 15 @{ */
kadonotakashi 0:8fdf9a60065b 16
kadonotakashi 0:8fdf9a60065b 17 typedef struct
kadonotakashi 0:8fdf9a60065b 18 {
kadonotakashi 0:8fdf9a60065b 19
kadonotakashi 0:8fdf9a60065b 20
kadonotakashi 0:8fdf9a60065b 21 /**
kadonotakashi 0:8fdf9a60065b 22 * @var SPI5_T::CTL
kadonotakashi 0:8fdf9a60065b 23 * Offset: 0x00 SPI Control Register
kadonotakashi 0:8fdf9a60065b 24 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 25 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 26 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 27 * |[0] |GOBUSY |SPI Transfer Control Bit and Busy Status
kadonotakashi 0:8fdf9a60065b 28 * | | |0 = Writing this bit 0 will stop data transfer if SPI is transferring.
kadonotakashi 0:8fdf9a60065b 29 * | | |1 = In Master mode, writing 1 to this bit will start the SPI data transfer; In Slave mode, writing u20181' to this bit indicates that the slave is ready to communicate with a master.
kadonotakashi 0:8fdf9a60065b 30 * | | |If the FIFO mode is disabled, during the data transfer, this bit keeps the value of u20181'
kadonotakashi 0:8fdf9a60065b 31 * | | |As the transfer is finished, this bit will be cleared automatically
kadonotakashi 0:8fdf9a60065b 32 * | | |Software can read this bit to check if the SPI is in busy status.
kadonotakashi 0:8fdf9a60065b 33 * | | |In FIFO mode, this bit will be controlled by hardware
kadonotakashi 0:8fdf9a60065b 34 * | | |Software should not modify this bit
kadonotakashi 0:8fdf9a60065b 35 * | | |In slave mode, this bit always returns 1 when software reads this register
kadonotakashi 0:8fdf9a60065b 36 * | | |In master mode, this bit reflects the busy or idle status of SPI.
kadonotakashi 0:8fdf9a60065b 37 * | | |Note:
kadonotakashi 0:8fdf9a60065b 38 * | | |1.When FIFO mode is disabled, all configurations should be set before writing 1 to the GOBUSY bit in the SPI_CTL register.
kadonotakashi 0:8fdf9a60065b 39 * | | |2
kadonotakashi 0:8fdf9a60065b 40 * | | |When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer.
kadonotakashi 0:8fdf9a60065b 41 * |[1] |RXNEG |Receive on Negative Edge
kadonotakashi 0:8fdf9a60065b 42 * | | |0 = The received data is latched on the rising edge of SPI_CLK.
kadonotakashi 0:8fdf9a60065b 43 * | | |1 = The received data is latched on the falling edge of SPI_CLK.
kadonotakashi 0:8fdf9a60065b 44 * | | |Note: Refer to Edge section.
kadonotakashi 0:8fdf9a60065b 45 * | | |Note:
kadonotakashi 0:8fdf9a60065b 46 * |[2] |TXNEG |Transmit on Negative Edge
kadonotakashi 0:8fdf9a60065b 47 * | | |0 = The transmitted data output is changed on the rising edge of SPI_CLK.
kadonotakashi 0:8fdf9a60065b 48 * | | |1 = The transmitted data output is changed on the falling edge of SPI_CLK.
kadonotakashi 0:8fdf9a60065b 49 * | | |Note: Refer to Edge section.
kadonotakashi 0:8fdf9a60065b 50 * | | |Note:
kadonotakashi 0:8fdf9a60065b 51 * |[7:3] |DWIDTH |Data Width
kadonotakashi 0:8fdf9a60065b 52 * | | |This field specifies how many bits can be transmitted / received in one transaction
kadonotakashi 0:8fdf9a60065b 53 * | | |The minimum bit length is 8 bits and can be up to 32 bits.
kadonotakashi 0:8fdf9a60065b 54 * | | |0x1~0x7: reserved
kadonotakashi 0:8fdf9a60065b 55 * | | |0x8 = 8 bits are transmitted in one transaction.
kadonotakashi 0:8fdf9a60065b 56 * | | |0x9 = 9 bits are transmitted in one transaction.
kadonotakashi 0:8fdf9a60065b 57 * | | |0xA = 10 bits are transmitted in one transaction.
kadonotakashi 0:8fdf9a60065b 58 * | | |u2026
kadonotakashi 0:8fdf9a60065b 59 * | | |0x1F = 31 bits are transmitted in one transaction.
kadonotakashi 0:8fdf9a60065b 60 * | | |0x0 = 32 bits are transmitted in one transaction.
kadonotakashi 0:8fdf9a60065b 61 * | | |Note:
kadonotakashi 0:8fdf9a60065b 62 * |[10] |LSB |Send LSB First
kadonotakashi 0:8fdf9a60065b 63 * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH (SPI_CTL[7:3]), is transmitted/received first.
kadonotakashi 0:8fdf9a60065b 64 * | | |1 = The LSB, bit 0 of the SPI_TX, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (SPI_RX
kadonotakashi 0:8fdf9a60065b 65 * | | |Note: Refer to LSB first section.
kadonotakashi 0:8fdf9a60065b 66 * |[11] |CLKPOL |Clock Polarity
kadonotakashi 0:8fdf9a60065b 67 * | | |0 = The default level of SPI_CLK is low.
kadonotakashi 0:8fdf9a60065b 68 * | | |1 = The default level of SPI_CLK is high.
kadonotakashi 0:8fdf9a60065b 69 * | | |Note: Refer to Clock Parity section.
kadonotakashi 0:8fdf9a60065b 70 * | | |Note:
kadonotakashi 0:8fdf9a60065b 71 * |[15:12] |SUSPITV |Suspend Interval (Master Only)
kadonotakashi 0:8fdf9a60065b 72 * | | |These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
kadonotakashi 0:8fdf9a60065b 73 * | | |The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKPOL = 0
kadonotakashi 0:8fdf9a60065b 74 * | | |If CLKPOL = 1, the interval is from the rising clock edge to the falling clock edge.
kadonotakashi 0:8fdf9a60065b 75 * | | |The default value is 0x3
kadonotakashi 0:8fdf9a60065b 76 * | | |The desired suspend interval is obtained according to the following equation: (SUSPITV[3:0] + 0.5) * period of SPI_CLK
kadonotakashi 0:8fdf9a60065b 77 * | | |For example,
kadonotakashi 0:8fdf9a60065b 78 * | | |SUSPITV = 0x0 u2026. 0.5 SPI_CLK clock cycle.
kadonotakashi 0:8fdf9a60065b 79 * | | |SUSPITV = 0x1 u2026. 1.5 SPI_CLK clock cycle.
kadonotakashi 0:8fdf9a60065b 80 * | | |u2026u2026
kadonotakashi 0:8fdf9a60065b 81 * | | |SUSPITV = 0xE u2026. 14.5 SPI_CLK clock cycle.
kadonotakashi 0:8fdf9a60065b 82 * | | |SUSPITV = 0xF u2026. 15.5 SPI_CLK clock cycle.
kadonotakashi 0:8fdf9a60065b 83 * | | |Note:
kadonotakashi 0:8fdf9a60065b 84 * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
kadonotakashi 0:8fdf9a60065b 85 * | | |0 = SPI unit transfer interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 86 * | | |1 = SPI unit transfer interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 87 * |[18] |SLAVE |Slave Mode Selection
kadonotakashi 0:8fdf9a60065b 88 * | | |0 = SPI controller set as Master mode.
kadonotakashi 0:8fdf9a60065b 89 * | | |1 = SPI controller set as Slave mode.
kadonotakashi 0:8fdf9a60065b 90 * | | |Note: Refer to Slave Selection section
kadonotakashi 0:8fdf9a60065b 91 * | | |Note:
kadonotakashi 0:8fdf9a60065b 92 * |[19] |REORDER |Byte Reorder Function Enable Bit
kadonotakashi 0:8fdf9a60065b 93 * | | |0 = Byte reorder function Disabled.
kadonotakashi 0:8fdf9a60065b 94 * | | |1 = Enable byte reorder function and insert a byte suspend interval among each byte
kadonotakashi 0:8fdf9a60065b 95 * | | |The byte reorder function is only available when DWIDTH is configured as 16, 24, and 32 bits.
kadonotakashi 0:8fdf9a60065b 96 * | | |Note: The suspend interval is defined in SUSPITV. Refer to Byte Reorder section.
kadonotakashi 0:8fdf9a60065b 97 * | | |Note: Byte Suspend is only used in SPI Byte Reorder mode.
kadonotakashi 0:8fdf9a60065b 98 * |[21] |FIFOM |FIFO Mode Enable Bit
kadonotakashi 0:8fdf9a60065b 99 * | | |0 = FIFO mode Disabled (in Normal mode).
kadonotakashi 0:8fdf9a60065b 100 * | | |1 = FIFO mode Enabled.
kadonotakashi 0:8fdf9a60065b 101 * | | |Note: Refer to FIFO Mode section.
kadonotakashi 0:8fdf9a60065b 102 * | | |Note:
kadonotakashi 0:8fdf9a60065b 103 * |[30] |WKSSEN |Wake-up by Slave Select Enable Bit
kadonotakashi 0:8fdf9a60065b 104 * | | |0 = Wake-up function Disabled.
kadonotakashi 0:8fdf9a60065b 105 * | | |1 = Wake-up function Enabled.
kadonotakashi 0:8fdf9a60065b 106 * | | |Note: The Slave select wake-up function is only available in SPI Slave mode
kadonotakashi 0:8fdf9a60065b 107 * | | |When the system enters power-down mode, the system can be wake-up from the SPI controller if this bit and PDWKIEN (CLK_PWRCTL[5]) are enabled and there is any toggle on the SPI_SS port
kadonotakashi 0:8fdf9a60065b 108 * | | |After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
kadonotakashi 0:8fdf9a60065b 109 * | | |Note: The wake up event will not assert the SPI interrupt, but user can read the corresponding status bit to check its occurrence.
kadonotakashi 0:8fdf9a60065b 110 * |[31] |WKCLKEN |Wake-up by SPI Clock Enable Bit
kadonotakashi 0:8fdf9a60065b 111 * | | |0 = Wake-up function Disabled.
kadonotakashi 0:8fdf9a60065b 112 * | | |1 = Wake-up function Enabled.
kadonotakashi 0:8fdf9a60065b 113 * | | |Note: When the system enters power-down mode, the system can be wake-up from the SPI controller if this bit and PDWKIEN (CLK_PWRCTL[5]) are enabled and there is any toggle on the SPI_CLK port
kadonotakashi 0:8fdf9a60065b 114 * | | |After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
kadonotakashi 0:8fdf9a60065b 115 * | | |Note: The wake up event will not assert the SPI interrupt, but user can read the corresponding status bit to check its occurrence.
kadonotakashi 0:8fdf9a60065b 116 * @var SPI5_T::STATUS
kadonotakashi 0:8fdf9a60065b 117 * Offset: 0x04 SPI Status Register
kadonotakashi 0:8fdf9a60065b 118 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 119 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 120 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 121 * |[0] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
kadonotakashi 0:8fdf9a60065b 122 * | | |0 = Received data FIFO is not empty in the FIFO mode.
kadonotakashi 0:8fdf9a60065b 123 * | | |1 = Received data FIFO is empty in the FIFO mode.
kadonotakashi 0:8fdf9a60065b 124 * |[1] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
kadonotakashi 0:8fdf9a60065b 125 * | | |0 = Received data FIFO is not full in FIFO mode.
kadonotakashi 0:8fdf9a60065b 126 * | | |1 = Received data FIFO is full in the FIFO mode.
kadonotakashi 0:8fdf9a60065b 127 * |[2] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
kadonotakashi 0:8fdf9a60065b 128 * | | |0 = Transmitted data FIFO is not empty in the FIFO mode.
kadonotakashi 0:8fdf9a60065b 129 * | | |1 =Transmitted data FIFO is empty in the FIFO mode.
kadonotakashi 0:8fdf9a60065b 130 * |[3] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
kadonotakashi 0:8fdf9a60065b 131 * | | |0 = Transmitted data FIFO is not full in the FIFO mode.
kadonotakashi 0:8fdf9a60065b 132 * | | |1 = Transmitted data FIFO is full in the FIFO mode.
kadonotakashi 0:8fdf9a60065b 133 * |[4] |LTRIGF |Level Trigger Accomplish Flag (Read Only)
kadonotakashi 0:8fdf9a60065b 134 * | | |In Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.
kadonotakashi 0:8fdf9a60065b 135 * | | |0 = The transferred bit length of one transaction does not meet the specified requirement.
kadonotakashi 0:8fdf9a60065b 136 * | | |1 = The transferred bit length meets the specified requirement which defined in DWIDTH.
kadonotakashi 0:8fdf9a60065b 137 * | | |Note: This bit is read only
kadonotakashi 0:8fdf9a60065b 138 * | | |As the software sets the GOBUSY bit to 1, the LTRIGF will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period
kadonotakashi 0:8fdf9a60065b 139 * | | |In FIFO mode, this bit is unmeaning.
kadonotakashi 0:8fdf9a60065b 140 * |[6] |SLVSTAIF |Slave Start Interrupt Flag
kadonotakashi 0:8fdf9a60065b 141 * | | |It is used to dedicate that the transfer has started in Slave mode with no slave select.
kadonotakashi 0:8fdf9a60065b 142 * | | |0 = Slave started transfer no active.
kadonotakashi 0:8fdf9a60065b 143 * | | |1 = Transfer has started in Slave mode with no slave select
kadonotakashi 0:8fdf9a60065b 144 * | | |It is automatically cleared by transfer done or writing u20181'.
kadonotakashi 0:8fdf9a60065b 145 * |[7] |UNITIF |Unit Transfer Interrupt Flag
kadonotakashi 0:8fdf9a60065b 146 * | | |0 = No transaction has been finished since this bit was cleared to 0.
kadonotakashi 0:8fdf9a60065b 147 * | | |1 = SPI controller has finished one unit transfer.
kadonotakashi 0:8fdf9a60065b 148 * | | |Note 1: If SSINAIEN (SPI_SSCTL[16]) is set to 1, this bit will be asserted again when transfer is done and the slave select signal becomes inactive from active condition.
kadonotakashi 0:8fdf9a60065b 149 * | | |Note 2: This bit will be cleared by writing 1 to it.
kadonotakashi 0:8fdf9a60065b 150 * |[8] |RXTHIF |RX FIFO Threshold Interrupt Flag (Read Only)
kadonotakashi 0:8fdf9a60065b 151 * | | |0 = RX valid data counts are less than or equal to RXTH (SPI_FIFOCTL[26:24]).
kadonotakashi 0:8fdf9a60065b 152 * | | |1 = RX valid data counts are larger than RXTH.
kadonotakashi 0:8fdf9a60065b 153 * | | |Note: If RXTHIEN (SPI_FIFOCTL[2]) = 1 and RXTHIF = 1, SPI will generate interrupt.
kadonotakashi 0:8fdf9a60065b 154 * |[9] |RXOVIF |Receive FIFO Overrun Interrupt Flag
kadonotakashi 0:8fdf9a60065b 155 * | | |0 = No FIFO overrun.
kadonotakashi 0:8fdf9a60065b 156 * | | |1 = Receive FIFO overrun.
kadonotakashi 0:8fdf9a60065b 157 * | | |Note 1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will be dropped.
kadonotakashi 0:8fdf9a60065b 158 * | | |Note 2: This bit will be cleared by writing 1 to it.
kadonotakashi 0:8fdf9a60065b 159 * |[10] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
kadonotakashi 0:8fdf9a60065b 160 * | | |0 = TX valid data counts are larger than TXTH (SPI_FIFOCTL[30:28]).
kadonotakashi 0:8fdf9a60065b 161 * | | |1 = TX valid data counts are less than or equal to TXTH.
kadonotakashi 0:8fdf9a60065b 162 * |[12] |RXTOIF |Receive Time-out Interrupt Flag
kadonotakashi 0:8fdf9a60065b 163 * | | |0 = There is not time-out event on the received buffer.
kadonotakashi 0:8fdf9a60065b 164 * | | |1 = Time-out event active in RX FIFO is not empty.
kadonotakashi 0:8fdf9a60065b 165 * | | |Refer to Time Out section.
kadonotakashi 0:8fdf9a60065b 166 * | | |Note: This bit will be cleared by writing 1 to it.
kadonotakashi 0:8fdf9a60065b 167 * |[13] |SLVTOIF |Slave Time-out Interrupt Flag
kadonotakashi 0:8fdf9a60065b 168 * | | |If SLVTOIEN (SPI_SSCTL[6]) is set to 1, this bit will be asserted when slave time-out event occur
kadonotakashi 0:8fdf9a60065b 169 * | | |Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit.
kadonotakashi 0:8fdf9a60065b 170 * | | |0 = Slave time-out does not occur yet.
kadonotakashi 0:8fdf9a60065b 171 * | | |1 = Slave time-out has occurred.
kadonotakashi 0:8fdf9a60065b 172 * |[15] |SLVTXSKE |Slave Mode Transmit Skew Buffer Empty Status
kadonotakashi 0:8fdf9a60065b 173 * | | |This bit indicates the empty status of transmit skew buffer which is used in Slave mode.
kadonotakashi 0:8fdf9a60065b 174 * |[19:16] |RXCNT |Receive FIFO Data Counts (Read Only)
kadonotakashi 0:8fdf9a60065b 175 * | | |This bit field indicates the valid data count of receive FIFO buffer.
kadonotakashi 0:8fdf9a60065b 176 * |[23:20] |TXCNT |Transmit FIFO Data Counts (Read Only)
kadonotakashi 0:8fdf9a60065b 177 * | | |This bit field indicates the valid data count of transmit FIFO buffer.
kadonotakashi 0:8fdf9a60065b 178 * |[30] |WKSSIF |Wake-up by Slave Select Interrupt Flag
kadonotakashi 0:8fdf9a60065b 179 * | | |When chip is woken up from power-down mode by the toggle event on SPI_SS port, this bit is set to 1
kadonotakashi 0:8fdf9a60065b 180 * | | |This bit can be cleared by writing u20181' to it.
kadonotakashi 0:8fdf9a60065b 181 * |[31] |WKCLKIF |Wake-up by SPI Clock Interrupt Flag
kadonotakashi 0:8fdf9a60065b 182 * | | |When chip is woken up from power-down mode by the toggle event on SPI_CLK port, this bit is set to 1
kadonotakashi 0:8fdf9a60065b 183 * | | |This bit can be cleared by writing u20181' to it.
kadonotakashi 0:8fdf9a60065b 184 * @var SPI5_T::CLKDIV
kadonotakashi 0:8fdf9a60065b 185 * Offset: 0x08 SPI Clock Divider Register
kadonotakashi 0:8fdf9a60065b 186 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 187 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 188 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 189 * |[7:0] |DIVIDER |Clock Divider
kadonotakashi 0:8fdf9a60065b 190 * | | |The value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_CLK
kadonotakashi 0:8fdf9a60065b 191 * | | |The desired frequency is obtained according to the following equation:
kadonotakashi 0:8fdf9a60065b 192 * | | |Where
kadonotakashi 0:8fdf9a60065b 193 * | | |is the SPI peripheral clock source
kadonotakashi 0:8fdf9a60065b 194 * | | |It is defined in the CLK_CLKSEL2[15:14] in Clock control section (CLK_BA + 0x18).
kadonotakashi 0:8fdf9a60065b 195 * | | |Note:
kadonotakashi 0:8fdf9a60065b 196 * @var SPI5_T::SSCTL
kadonotakashi 0:8fdf9a60065b 197 * Offset: 0x0C SPI Slave Select Control Register
kadonotakashi 0:8fdf9a60065b 198 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 199 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 200 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 201 * |[0] |SS |Slave Selection Control (Master Only)
kadonotakashi 0:8fdf9a60065b 202 * | | |If AUTOSS bit (SPI_SSCTL[3]) is cleared, writing 1 to SS (SPI_SSCTL[0]) bit sets the SPI_SS line to an active state and writing 0 sets the line back to inactive state
kadonotakashi 0:8fdf9a60065b 203 * | | |If AUTOSS = 0,.
kadonotakashi 0:8fdf9a60065b 204 * | | |0 = SPI_SS is inactive.
kadonotakashi 0:8fdf9a60065b 205 * | | |1 =SPI_SS is active.
kadonotakashi 0:8fdf9a60065b 206 * | | |If AUTOSS bit is set, writing 1 to this field will select appropriate SPI_SS line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time
kadonotakashi 0:8fdf9a60065b 207 * | | |(The active level of SPI_SS is specified in SSACTPOL).
kadonotakashi 0:8fdf9a60065b 208 * | | |If AUTOSS =1,.
kadonotakashi 0:8fdf9a60065b 209 * | | |0 = SPI_SS is inactive.
kadonotakashi 0:8fdf9a60065b 210 * | | |1 = SPI_SS is active on the duration of transaction.
kadonotakashi 0:8fdf9a60065b 211 * | | |Note:
kadonotakashi 0:8fdf9a60065b 212 * | | |1
kadonotakashi 0:8fdf9a60065b 213 * | | |This interface can only drive one device/slave at a given time
kadonotakashi 0:8fdf9a60065b 214 * | | |Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer.
kadonotakashi 0:8fdf9a60065b 215 * | | |2
kadonotakashi 0:8fdf9a60065b 216 * | | |SPI_SS is also defined as device/slave select input in Slave mode
kadonotakashi 0:8fdf9a60065b 217 * | | |And that the slave select input must be driven by edge active trigger which level depend on the SSACTPOL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software
kadonotakashi 0:8fdf9a60065b 218 * |[2] |SSACTPOL |Slave Selection Active Polarity
kadonotakashi 0:8fdf9a60065b 219 * | | |It defines the active polarity of slave selection signal (SPI_SS).
kadonotakashi 0:8fdf9a60065b 220 * | | |0 = The SPI_SS slave select signal is active Low.
kadonotakashi 0:8fdf9a60065b 221 * | | |1 = The SPI_SS slave select signal is active High.
kadonotakashi 0:8fdf9a60065b 222 * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
kadonotakashi 0:8fdf9a60065b 223 * | | |0 = If this bit is set as 0, slave select signals are asserted and de-asserted by setting and clearing related bits in SS (SPI_SSCTL[0]).
kadonotakashi 0:8fdf9a60065b 224 * | | |1 = If this bit is set as 1, SPI_SS signals are generated automatically
kadonotakashi 0:8fdf9a60065b 225 * | | |It means that device/slave select signal, which is set in SS (SPI_SSCTL[0]) is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done.
kadonotakashi 0:8fdf9a60065b 226 * |[4] |SSLTRIG |Slave Select Level Trigger Control
kadonotakashi 0:8fdf9a60065b 227 * | | |0 = The input slave select signal is edge-trigger.
kadonotakashi 0:8fdf9a60065b 228 * | | |1 = The slave select signal will be level-trigger
kadonotakashi 0:8fdf9a60065b 229 * | | |It depends on SSACTPOL to decide the signal is active low or active high.
kadonotakashi 0:8fdf9a60065b 230 * |[5] |SLV3WIRE |Slave 3-wire Mode Enable Bit
kadonotakashi 0:8fdf9a60065b 231 * | | |This bit is used to ignore the slave select signal in Slave mode
kadonotakashi 0:8fdf9a60065b 232 * | | |The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.
kadonotakashi 0:8fdf9a60065b 233 * | | |0 = The controller is 4-wire bi-direction interface.
kadonotakashi 0:8fdf9a60065b 234 * | | |1 = The controller is 3-wire bi-direction interface in Slave mode
kadonotakashi 0:8fdf9a60065b 235 * | | |When this bit is set as 1, the controller start to transmit/receive data after the GOBUSY bit active and the SPI clock input.
kadonotakashi 0:8fdf9a60065b 236 * | | |Note 1: Refer to No Slave Select Mode.
kadonotakashi 0:8fdf9a60065b 237 * | | |Note 2: In no slave select signal mode, hardware will set the SSLTRIG (SPI_SSCTL[4]) as 1 automatically.
kadonotakashi 0:8fdf9a60065b 238 * |[6] |SLVTOIEN |Slave Time-out Interrupt Enable Bit
kadonotakashi 0:8fdf9a60065b 239 * | | |This bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur
kadonotakashi 0:8fdf9a60065b 240 * | | |0 = Slave time-out function and interrupt both Disabled.
kadonotakashi 0:8fdf9a60065b 241 * | | |1 = Slave time-out function and interrupt both Enabled.
kadonotakashi 0:8fdf9a60065b 242 * |[8] |SLVABORT |Abort in Slave Mode with No Slave Selected
kadonotakashi 0:8fdf9a60065b 243 * | | |0 = No force the slave abort.
kadonotakashi 0:8fdf9a60065b 244 * | | |1 = Force the current transfer done in no slave select mode.
kadonotakashi 0:8fdf9a60065b 245 * | | |Refer to No Slave Select Mode.
kadonotakashi 0:8fdf9a60065b 246 * | | |Note: It is auto cleared to 0 by hardware when the abort event is active.
kadonotakashi 0:8fdf9a60065b 247 * |[9] |SSTAIEN |Slave Start Interrupt Enable Bit
kadonotakashi 0:8fdf9a60065b 248 * | | |0 = Transfer start interrupt Disabled in no slave select mode.
kadonotakashi 0:8fdf9a60065b 249 * | | |1 = Transaction start interrupt Enabled in no slave select mode
kadonotakashi 0:8fdf9a60065b 250 * | | |It is cleared when the current transfer done or the SLVSTAIF bit cleared (write 1 clear).
kadonotakashi 0:8fdf9a60065b 251 * | | |Refer to No Slave Select Mode.
kadonotakashi 0:8fdf9a60065b 252 * |[16] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
kadonotakashi 0:8fdf9a60065b 253 * | | |It is used to enable the interrupt when the transfer has done in slave mode.
kadonotakashi 0:8fdf9a60065b 254 * | | |0 = No any interrupt, even there is slave select inactive event.
kadonotakashi 0:8fdf9a60065b 255 * | | |1 = There is interrupt event when the slave select signal becomes inactive from active condition
kadonotakashi 0:8fdf9a60065b 256 * | | |It is used to inform the user to know that the transaction has finished and the slave select into the inactive state.
kadonotakashi 0:8fdf9a60065b 257 * |[29:20] |SLVTOCNT |Slave Mode Time-out Period
kadonotakashi 0:8fdf9a60065b 258 * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
kadonotakashi 0:8fdf9a60065b 259 * | | |The clock source of the time-out counter is Slave peripheral clock
kadonotakashi 0:8fdf9a60065b 260 * | | |If the value is 0, it indicates the slave mode time-out function is disabled.
kadonotakashi 0:8fdf9a60065b 261 * @var SPI5_T::RX
kadonotakashi 0:8fdf9a60065b 262 * Offset: 0x10 SPI Receive Data FIFO Register
kadonotakashi 0:8fdf9a60065b 263 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 264 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 265 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 266 * |[31:0] |RX |Receive Data Register (Read Only)
kadonotakashi 0:8fdf9a60065b 267 * | | |The received data can be read on it
kadonotakashi 0:8fdf9a60065b 268 * | | |If the FIFO bit is set as 1, the user also checks the RXEMPTY (SPI_STATUS[0]), to check if there is any more received data or not.
kadonotakashi 0:8fdf9a60065b 269 * @var SPI5_T::TX
kadonotakashi 0:8fdf9a60065b 270 * Offset: 0x20 SPI Transmit Data FIFO Register
kadonotakashi 0:8fdf9a60065b 271 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 272 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 273 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 274 * |[31:0] |TX |Transmit Data Register (Write Only)
kadonotakashi 0:8fdf9a60065b 275 * | | |The Data Transmit Registers hold the data to be transmitted in the next transfer
kadonotakashi 0:8fdf9a60065b 276 * | | |The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.
kadonotakashi 0:8fdf9a60065b 277 * | | |For example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer
kadonotakashi 0:8fdf9a60065b 278 * | | |If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer.
kadonotakashi 0:8fdf9a60065b 279 * | | |Note:
kadonotakashi 0:8fdf9a60065b 280 * | | |If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1
kadonotakashi 0:8fdf9a60065b 281 * @var SPI5_T::PDMACTL
kadonotakashi 0:8fdf9a60065b 282 * Offset: 0x38 SPI PDMA Control Register
kadonotakashi 0:8fdf9a60065b 283 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 284 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 285 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 286 * |[0] |TXPDMAEN |Transmit PDMA Enable Bit
kadonotakashi 0:8fdf9a60065b 287 * | | |0 = Transmit PDMA function Disabled.
kadonotakashi 0:8fdf9a60065b 288 * | | |1 = Transmit PDMA function Enabled.
kadonotakashi 0:8fdf9a60065b 289 * | | |Refer to PDMA section for more detail information.
kadonotakashi 0:8fdf9a60065b 290 * | | |Note:
kadonotakashi 0:8fdf9a60065b 291 * | | |1
kadonotakashi 0:8fdf9a60065b 292 * | | |Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.
kadonotakashi 0:8fdf9a60065b 293 * | | |Hardware will clear this bit to 0 automatically after PDMA transfer done.
kadonotakashi 0:8fdf9a60065b 294 * |[1] |RXPDMAEN |Receiving PDMA Enable Bit
kadonotakashi 0:8fdf9a60065b 295 * | | |0 = Receiver PDMA function Disabled.
kadonotakashi 0:8fdf9a60065b 296 * | | |1 = Receiver PDMA function Enabled.
kadonotakashi 0:8fdf9a60065b 297 * | | |Refer to PDMA section for more detail information.
kadonotakashi 0:8fdf9a60065b 298 * | | |Note:
kadonotakashi 0:8fdf9a60065b 299 * | | |Hardware will clear this bit to 0 automatically after PDMA transfer done.
kadonotakashi 0:8fdf9a60065b 300 * | | |In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock
kadonotakashi 0:8fdf9a60065b 301 * |[2] |PDMARST |PDMA Reset
kadonotakashi 0:8fdf9a60065b 302 * | | |It is used to reset the SPI PDMA function into default state.
kadonotakashi 0:8fdf9a60065b 303 * | | |0 = After reset PDMA function or in normal operation.
kadonotakashi 0:8fdf9a60065b 304 * | | |1 = Reset PDMA function.
kadonotakashi 0:8fdf9a60065b 305 * | | |Note: It is auto cleared to 0 after the reset function has done.
kadonotakashi 0:8fdf9a60065b 306 * @var SPI5_T::FIFOCTL
kadonotakashi 0:8fdf9a60065b 307 * Offset: 0x3C SPI FIFO Control Register
kadonotakashi 0:8fdf9a60065b 308 * ---------------------------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 309 * |Bits |Field |Descriptions
kadonotakashi 0:8fdf9a60065b 310 * | :----: | :----: | :---- |
kadonotakashi 0:8fdf9a60065b 311 * |[0] |RXFBCLR |Receive FIFO Buffer Clear
kadonotakashi 0:8fdf9a60065b 312 * | | |0 = No clear the received FIFO.
kadonotakashi 0:8fdf9a60065b 313 * | | |1 = Clear the received FIFO.
kadonotakashi 0:8fdf9a60065b 314 * | | |Note: This bit is used to clear the receiver counter in FIFO Mode
kadonotakashi 0:8fdf9a60065b 315 * | | |This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter
kadonotakashi 0:8fdf9a60065b 316 * | | |After the clear operation, the flag of RXEMPTY in SPI_STATUS[0] will be set to 1.
kadonotakashi 0:8fdf9a60065b 317 * |[1] |TXFBCLR |Transmit FIFO Buffer Clear
kadonotakashi 0:8fdf9a60065b 318 * | | |0 = Not clear the transmitted FIFO.
kadonotakashi 0:8fdf9a60065b 319 * | | |1 = Clear the transmitted FIFO.
kadonotakashi 0:8fdf9a60065b 320 * | | |Note: This bit is used to clear the transmit counter in FIFO Mode
kadonotakashi 0:8fdf9a60065b 321 * | | |This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter
kadonotakashi 0:8fdf9a60065b 322 * | | |After the clear operation, the flag of TXEMPTY in SPI_STATUS[2] will be set to 1.
kadonotakashi 0:8fdf9a60065b 323 * |[2] |RXTHIEN |Receive Threshold Interrupt Enable Bit
kadonotakashi 0:8fdf9a60065b 324 * | | |0 = RX threshold interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 325 * | | |1 = RX threshold interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 326 * |[3] |TXTHIEN |Transmit Threshold Interrupt Enable Bit
kadonotakashi 0:8fdf9a60065b 327 * | | |0 = TX threshold interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 328 * | | |1 = TX threshold interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 329 * |[4] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
kadonotakashi 0:8fdf9a60065b 330 * | | |0 = RX FIFO overrun interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 331 * | | |1 = RX FIFO overrun interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 332 * |[7] |RXTOIEN |RX Read Time Out Interrupt Enable Bit
kadonotakashi 0:8fdf9a60065b 333 * | | |0 = RX read Timeout Interrupt Disabled.
kadonotakashi 0:8fdf9a60065b 334 * | | |1 = RX read Timeout Interrupt Enabled.
kadonotakashi 0:8fdf9a60065b 335 * |[26:24] |RXTH |Received FIFO Threshold
kadonotakashi 0:8fdf9a60065b 336 * | | |If RX valid data counts are larger than RXTH, RXTHIF (SPI_STATUS[8]) will be set to 1..
kadonotakashi 0:8fdf9a60065b 337 * |[30:28] |TXTH |Transmit FIFO Threshold
kadonotakashi 0:8fdf9a60065b 338 * | | |If TX valid data counts are less than or equal to TXTH, TXTHIF (SPI_STATUS[10]) will be set to 1.
kadonotakashi 0:8fdf9a60065b 339 */
kadonotakashi 0:8fdf9a60065b 340 __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */
kadonotakashi 0:8fdf9a60065b 341 __IO uint32_t STATUS; /*!< [0x0004] SPI Status Register */
kadonotakashi 0:8fdf9a60065b 342 __IO uint32_t CLKDIV; /*!< [0x0008] SPI Clock Divider Register */
kadonotakashi 0:8fdf9a60065b 343 __IO uint32_t SSCTL; /*!< [0x000c] SPI Slave Select Control Register */
kadonotakashi 0:8fdf9a60065b 344 __I uint32_t RX; /*!< [0x0010] SPI Receive Data FIFO Register */
kadonotakashi 0:8fdf9a60065b 345 __I uint32_t RESERVE0[3];
kadonotakashi 0:8fdf9a60065b 346 __O uint32_t TX; /*!< [0x0020] SPI Transmit Data FIFO Register */
kadonotakashi 0:8fdf9a60065b 347 __I uint32_t RESERVE1[5];
kadonotakashi 0:8fdf9a60065b 348 __IO uint32_t PDMACTL; /*!< [0x0038] SPI PDMA Control Register */
kadonotakashi 0:8fdf9a60065b 349 __IO uint32_t FIFOCTL; /*!< [0x003c] SPI FIFO Control Register */
kadonotakashi 0:8fdf9a60065b 350
kadonotakashi 0:8fdf9a60065b 351 } SPI5_T;
kadonotakashi 0:8fdf9a60065b 352
kadonotakashi 0:8fdf9a60065b 353 /**
kadonotakashi 0:8fdf9a60065b 354 @addtogroup SPI5_CONST SPI5 Bit Field Definition
kadonotakashi 0:8fdf9a60065b 355 Constant Definitions for SPI5 Controller
kadonotakashi 0:8fdf9a60065b 356 @{ */
kadonotakashi 0:8fdf9a60065b 357
kadonotakashi 0:8fdf9a60065b 358 #define SPI5_CTL_GOBUSY_Pos (0) /*!< SPI5_T::CTL: GOBUSY Position */
kadonotakashi 0:8fdf9a60065b 359 #define SPI5_CTL_GOBUSY_Msk (0x1ul << SPI5_CTL_GOBUSY_Pos) /*!< SPI5_T::CTL: GOBUSY Mask */
kadonotakashi 0:8fdf9a60065b 360
kadonotakashi 0:8fdf9a60065b 361 #define SPI5_CTL_RXNEG_Pos (1) /*!< SPI5_T::CTL: RXNEG Position */
kadonotakashi 0:8fdf9a60065b 362 #define SPI5_CTL_RXNEG_Msk (0x1ul << SPI5_CTL_RXNEG_Pos) /*!< SPI5_T::CTL: RXNEG Mask */
kadonotakashi 0:8fdf9a60065b 363
kadonotakashi 0:8fdf9a60065b 364 #define SPI5_CTL_TXNEG_Pos (2) /*!< SPI5_T::CTL: TXNEG Position */
kadonotakashi 0:8fdf9a60065b 365 #define SPI5_CTL_TXNEG_Msk (0x1ul << SPI5_CTL_TXNEG_Pos) /*!< SPI5_T::CTL: TXNEG Mask */
kadonotakashi 0:8fdf9a60065b 366
kadonotakashi 0:8fdf9a60065b 367 #define SPI5_CTL_DWIDTH_Pos (3) /*!< SPI5_T::CTL: DWIDTH Position */
kadonotakashi 0:8fdf9a60065b 368 #define SPI5_CTL_DWIDTH_Msk (0x1ful << SPI5_CTL_DWIDTH_Pos) /*!< SPI5_T::CTL: DWIDTH Mask */
kadonotakashi 0:8fdf9a60065b 369
kadonotakashi 0:8fdf9a60065b 370 #define SPI5_CTL_LSB_Pos (10) /*!< SPI5_T::CTL: LSB Position */
kadonotakashi 0:8fdf9a60065b 371 #define SPI5_CTL_LSB_Msk (0x1ul << SPI5_CTL_LSB_Pos) /*!< SPI5_T::CTL: LSB Mask */
kadonotakashi 0:8fdf9a60065b 372
kadonotakashi 0:8fdf9a60065b 373 #define SPI5_CTL_CLKPOL_Pos (11) /*!< SPI5_T::CTL: CLKPOL Position */
kadonotakashi 0:8fdf9a60065b 374 #define SPI5_CTL_CLKPOL_Msk (0x1ul << SPI5_CTL_CLKPOL_Pos) /*!< SPI5_T::CTL: CLKPOL Mask */
kadonotakashi 0:8fdf9a60065b 375
kadonotakashi 0:8fdf9a60065b 376 #define SPI5_CTL_SUSPITV_Pos (12) /*!< SPI5_T::CTL: SUSPITV Position */
kadonotakashi 0:8fdf9a60065b 377 #define SPI5_CTL_SUSPITV_Msk (0xful << SPI5_CTL_SUSPITV_Pos) /*!< SPI5_T::CTL: SUSPITV Mask */
kadonotakashi 0:8fdf9a60065b 378
kadonotakashi 0:8fdf9a60065b 379 #define SPI5_CTL_UNITIEN_Pos (17) /*!< SPI5_T::CTL: UNITIEN Position */
kadonotakashi 0:8fdf9a60065b 380 #define SPI5_CTL_UNITIEN_Msk (0x1ul << SPI5_CTL_UNITIEN_Pos) /*!< SPI5_T::CTL: UNITIEN Mask */
kadonotakashi 0:8fdf9a60065b 381
kadonotakashi 0:8fdf9a60065b 382 #define SPI5_CTL_SLAVE_Pos (18) /*!< SPI5_T::CTL: SLAVE Position */
kadonotakashi 0:8fdf9a60065b 383 #define SPI5_CTL_SLAVE_Msk (0x1ul << SPI5_CTL_SLAVE_Pos) /*!< SPI5_T::CTL: SLAVE Mask */
kadonotakashi 0:8fdf9a60065b 384
kadonotakashi 0:8fdf9a60065b 385 #define SPI5_CTL_REORDER_Pos (19) /*!< SPI5_T::CTL: REORDER Position */
kadonotakashi 0:8fdf9a60065b 386 #define SPI5_CTL_REORDER_Msk (0x1ul << SPI5_CTL_REORDER_Pos) /*!< SPI5_T::CTL: REORDER Mask */
kadonotakashi 0:8fdf9a60065b 387
kadonotakashi 0:8fdf9a60065b 388 #define SPI5_CTL_FIFOM_Pos (21) /*!< SPI5_T::CTL: FIFOM Position */
kadonotakashi 0:8fdf9a60065b 389 #define SPI5_CTL_FIFOM_Msk (0x1ul << SPI5_CTL_FIFOM_Pos) /*!< SPI5_T::CTL: FIFOM Mask */
kadonotakashi 0:8fdf9a60065b 390
kadonotakashi 0:8fdf9a60065b 391 #define SPI5_CTL_WKSSEN_Pos (30) /*!< SPI5_T::CTL: WKSSEN Position */
kadonotakashi 0:8fdf9a60065b 392 #define SPI5_CTL_WKSSEN_Msk (0x1ul << SPI5_CTL_WKSSEN_Pos) /*!< SPI5_T::CTL: WKSSEN Mask */
kadonotakashi 0:8fdf9a60065b 393
kadonotakashi 0:8fdf9a60065b 394 #define SPI5_CTL_WKCLKEN_Pos (31) /*!< SPI5_T::CTL: WKCLKEN Position */
kadonotakashi 0:8fdf9a60065b 395 #define SPI5_CTL_WKCLKEN_Msk (0x1ul << SPI5_CTL_WKCLKEN_Pos) /*!< SPI5_T::CTL: WKCLKEN Mask */
kadonotakashi 0:8fdf9a60065b 396
kadonotakashi 0:8fdf9a60065b 397 #define SPI5_STATUS_RXEMPTY_Pos (0) /*!< SPI5_T::STATUS: RXEMPTY Position */
kadonotakashi 0:8fdf9a60065b 398 #define SPI5_STATUS_RXEMPTY_Msk (0x1ul << SPI5_STATUS_RXEMPTY_Pos) /*!< SPI5_T::STATUS: RXEMPTY Mask */
kadonotakashi 0:8fdf9a60065b 399
kadonotakashi 0:8fdf9a60065b 400 #define SPI5_STATUS_RXFULL_Pos (1) /*!< SPI5_T::STATUS: RXFULL Position */
kadonotakashi 0:8fdf9a60065b 401 #define SPI5_STATUS_RXFULL_Msk (0x1ul << SPI5_STATUS_RXFULL_Pos) /*!< SPI5_T::STATUS: RXFULL Mask */
kadonotakashi 0:8fdf9a60065b 402
kadonotakashi 0:8fdf9a60065b 403 #define SPI5_STATUS_TXEMPTY_Pos (2) /*!< SPI5_T::STATUS: TXEMPTY Position */
kadonotakashi 0:8fdf9a60065b 404 #define SPI5_STATUS_TXEMPTY_Msk (0x1ul << SPI5_STATUS_TXEMPTY_Pos) /*!< SPI5_T::STATUS: TXEMPTY Mask */
kadonotakashi 0:8fdf9a60065b 405
kadonotakashi 0:8fdf9a60065b 406 #define SPI5_STATUS_TXFULL_Pos (3) /*!< SPI5_T::STATUS: TXFULL Position */
kadonotakashi 0:8fdf9a60065b 407 #define SPI5_STATUS_TXFULL_Msk (0x1ul << SPI5_STATUS_TXFULL_Pos) /*!< SPI5_T::STATUS: TXFULL Mask */
kadonotakashi 0:8fdf9a60065b 408
kadonotakashi 0:8fdf9a60065b 409 #define SPI5_STATUS_LTRIGF_Pos (4) /*!< SPI5_T::STATUS: LTRIGF Position */
kadonotakashi 0:8fdf9a60065b 410 #define SPI5_STATUS_LTRIGF_Msk (0x1ul << SPI5_STATUS_LTRIGF_Pos) /*!< SPI5_T::STATUS: LTRIGF Mask */
kadonotakashi 0:8fdf9a60065b 411
kadonotakashi 0:8fdf9a60065b 412 #define SPI5_STATUS_SLVSTAIF_Pos (6) /*!< SPI5_T::STATUS: SLVSTAIF Position */
kadonotakashi 0:8fdf9a60065b 413 #define SPI5_STATUS_SLVSTAIF_Msk (0x1ul << SPI5_STATUS_SLVSTAIF_Pos) /*!< SPI5_T::STATUS: SLVSTAIF Mask */
kadonotakashi 0:8fdf9a60065b 414
kadonotakashi 0:8fdf9a60065b 415 #define SPI5_STATUS_UNITIF_Pos (7) /*!< SPI5_T::STATUS: UNITIF Position */
kadonotakashi 0:8fdf9a60065b 416 #define SPI5_STATUS_UNITIF_Msk (0x1ul << SPI5_STATUS_UNITIF_Pos) /*!< SPI5_T::STATUS: UNITIF Mask */
kadonotakashi 0:8fdf9a60065b 417
kadonotakashi 0:8fdf9a60065b 418 #define SPI5_STATUS_RXTHIF_Pos (8) /*!< SPI5_T::STATUS: RXTHIF Position */
kadonotakashi 0:8fdf9a60065b 419 #define SPI5_STATUS_RXTHIF_Msk (0x1ul << SPI5_STATUS_RXTHIF_Pos) /*!< SPI5_T::STATUS: RXTHIF Mask */
kadonotakashi 0:8fdf9a60065b 420
kadonotakashi 0:8fdf9a60065b 421 #define SPI5_STATUS_RXOVIF_Pos (9) /*!< SPI5_T::STATUS: RXOVIF Position */
kadonotakashi 0:8fdf9a60065b 422 #define SPI5_STATUS_RXOVIF_Msk (0x1ul << SPI5_STATUS_RXOVIF_Pos) /*!< SPI5_T::STATUS: RXOVIF Mask */
kadonotakashi 0:8fdf9a60065b 423
kadonotakashi 0:8fdf9a60065b 424 #define SPI5_STATUS_TXTHIF_Pos (10) /*!< SPI5_T::STATUS: TXTHIF Position */
kadonotakashi 0:8fdf9a60065b 425 #define SPI5_STATUS_TXTHIF_Msk (0x1ul << SPI5_STATUS_TXTHIF_Pos) /*!< SPI5_T::STATUS: TXTHIF Mask */
kadonotakashi 0:8fdf9a60065b 426
kadonotakashi 0:8fdf9a60065b 427 #define SPI5_STATUS_RXTOIF_Pos (12) /*!< SPI5_T::STATUS: RXTOIF Position */
kadonotakashi 0:8fdf9a60065b 428 #define SPI5_STATUS_RXTOIF_Msk (0x1ul << SPI5_STATUS_RXTOIF_Pos) /*!< SPI5_T::STATUS: RXTOIF Mask */
kadonotakashi 0:8fdf9a60065b 429
kadonotakashi 0:8fdf9a60065b 430 #define SPI5_STATUS_SLVTOIF_Pos (13) /*!< SPI5_T::STATUS: SLVTOIF Position */
kadonotakashi 0:8fdf9a60065b 431 #define SPI5_STATUS_SLVTOIF_Msk (0x1ul << SPI5_STATUS_SLVTOIF_Pos) /*!< SPI5_T::STATUS: SLVTOIF Mask */
kadonotakashi 0:8fdf9a60065b 432
kadonotakashi 0:8fdf9a60065b 433 #define SPI5_STATUS_SLVTXSKE_Pos (15) /*!< SPI5_T::STATUS: SLVTXSKE Position */
kadonotakashi 0:8fdf9a60065b 434 #define SPI5_STATUS_SLVTXSKE_Msk (0x1ul << SPI5_STATUS_SLVTXSKE_Pos) /*!< SPI5_T::STATUS: SLVTXSKE Mask */
kadonotakashi 0:8fdf9a60065b 435
kadonotakashi 0:8fdf9a60065b 436 #define SPI5_STATUS_RXCNT_Pos (16) /*!< SPI5_T::STATUS: RXCNT Position */
kadonotakashi 0:8fdf9a60065b 437 #define SPI5_STATUS_RXCNT_Msk (0xful << SPI5_STATUS_RXCNT_Pos) /*!< SPI5_T::STATUS: RXCNT Mask */
kadonotakashi 0:8fdf9a60065b 438
kadonotakashi 0:8fdf9a60065b 439 #define SPI5_STATUS_TXCNT_Pos (20) /*!< SPI5_T::STATUS: TXCNT Position */
kadonotakashi 0:8fdf9a60065b 440 #define SPI5_STATUS_TXCNT_Msk (0xful << SPI5_STATUS_TXCNT_Pos) /*!< SPI5_T::STATUS: TXCNT Mask */
kadonotakashi 0:8fdf9a60065b 441
kadonotakashi 0:8fdf9a60065b 442 #define SPI5_STATUS_WKSSIF_Pos (30) /*!< SPI5_T::STATUS: WKSSIF Position */
kadonotakashi 0:8fdf9a60065b 443 #define SPI5_STATUS_WKSSIF_Msk (0x1ul << SPI5_STATUS_WKSSIF_Pos) /*!< SPI5_T::STATUS: WKSSIF Mask */
kadonotakashi 0:8fdf9a60065b 444
kadonotakashi 0:8fdf9a60065b 445 #define SPI5_STATUS_WKCLKIF_Pos (31) /*!< SPI5_T::STATUS: WKCLKIF Position */
kadonotakashi 0:8fdf9a60065b 446 #define SPI5_STATUS_WKCLKIF_Msk (0x1ul << SPI5_STATUS_WKCLKIF_Pos) /*!< SPI5_T::STATUS: WKCLKIF Mask */
kadonotakashi 0:8fdf9a60065b 447
kadonotakashi 0:8fdf9a60065b 448 #define SPI5_CLKDIV_DIVIDER_Pos (0) /*!< SPI5_T::CLKDIV: DIVIDER Position */
kadonotakashi 0:8fdf9a60065b 449 #define SPI5_CLKDIV_DIVIDER_Msk (0xfful << SPI5_CLKDIV_DIVIDER_Pos) /*!< SPI5_T::CLKDIV: DIVIDER Mask */
kadonotakashi 0:8fdf9a60065b 450
kadonotakashi 0:8fdf9a60065b 451 #define SPI5_SSCTL_SS_Pos (0) /*!< SPI5_T::SSCTL: SS Position */
kadonotakashi 0:8fdf9a60065b 452 #define SPI5_SSCTL_SS_Msk (0x1ul << SPI5_SSCTL_SS_Pos) /*!< SPI5_T::SSCTL: SS Mask */
kadonotakashi 0:8fdf9a60065b 453
kadonotakashi 0:8fdf9a60065b 454 #define SPI5_SSCTL_SSACTPOL_Pos (2) /*!< SPI5_T::SSCTL: SSACTPOL Position */
kadonotakashi 0:8fdf9a60065b 455 #define SPI5_SSCTL_SSACTPOL_Msk (0x1ul << SPI5_SSCTL_SSACTPOL_Pos) /*!< SPI5_T::SSCTL: SSACTPOL Mask */
kadonotakashi 0:8fdf9a60065b 456
kadonotakashi 0:8fdf9a60065b 457 #define SPI5_SSCTL_AUTOSS_Pos (3) /*!< SPI5_T::SSCTL: AUTOSS Position */
kadonotakashi 0:8fdf9a60065b 458 #define SPI5_SSCTL_AUTOSS_Msk (0x1ul << SPI5_SSCTL_AUTOSS_Pos) /*!< SPI5_T::SSCTL: AUTOSS Mask */
kadonotakashi 0:8fdf9a60065b 459
kadonotakashi 0:8fdf9a60065b 460 #define SPI5_SSCTL_SSLTRIG_Pos (4) /*!< SPI5_T::SSCTL: SSLTRIG Position */
kadonotakashi 0:8fdf9a60065b 461 #define SPI5_SSCTL_SSLTRIG_Msk (0x1ul << SPI5_SSCTL_SSLTRIG_Pos) /*!< SPI5_T::SSCTL: SSLTRIG Mask */
kadonotakashi 0:8fdf9a60065b 462
kadonotakashi 0:8fdf9a60065b 463 #define SPI5_SSCTL_SLV3WIRE_Pos (5) /*!< SPI5_T::SSCTL: SLV3WIRE Position */
kadonotakashi 0:8fdf9a60065b 464 #define SPI5_SSCTL_SLV3WIRE_Msk (0x1ul << SPI5_SSCTL_SLV3WIRE_Pos) /*!< SPI5_T::SSCTL: SLV3WIRE Mask */
kadonotakashi 0:8fdf9a60065b 465
kadonotakashi 0:8fdf9a60065b 466 #define SPI5_SSCTL_SLVTOIEN_Pos (6) /*!< SPI5_T::SSCTL: SLVTOIEN Position */
kadonotakashi 0:8fdf9a60065b 467 #define SPI5_SSCTL_SLVTOIEN_Msk (0x1ul << SPI5_SSCTL_SLVTOIEN_Pos) /*!< SPI5_T::SSCTL: SLVTOIEN Mask */
kadonotakashi 0:8fdf9a60065b 468
kadonotakashi 0:8fdf9a60065b 469 #define SPI5_SSCTL_SLVABORT_Pos (8) /*!< SPI5_T::SSCTL: SLVABORT Position */
kadonotakashi 0:8fdf9a60065b 470 #define SPI5_SSCTL_SLVABORT_Msk (0x1ul << SPI5_SSCTL_SLVABORT_Pos) /*!< SPI5_T::SSCTL: SLVABORT Mask */
kadonotakashi 0:8fdf9a60065b 471
kadonotakashi 0:8fdf9a60065b 472 #define SPI5_SSCTL_SSTAIEN_Pos (9) /*!< SPI5_T::SSCTL: SSTAIEN Position */
kadonotakashi 0:8fdf9a60065b 473 #define SPI5_SSCTL_SSTAIEN_Msk (0x1ul << SPI5_SSCTL_SSTAIEN_Pos) /*!< SPI5_T::SSCTL: SSTAIEN Mask */
kadonotakashi 0:8fdf9a60065b 474
kadonotakashi 0:8fdf9a60065b 475 #define SPI5_SSCTL_SSINAIEN_Pos (16) /*!< SPI5_T::SSCTL: SSINAIEN Position */
kadonotakashi 0:8fdf9a60065b 476 #define SPI5_SSCTL_SSINAIEN_Msk (0x1ul << SPI5_SSCTL_SSINAIEN_Pos) /*!< SPI5_T::SSCTL: SSINAIEN Mask */
kadonotakashi 0:8fdf9a60065b 477
kadonotakashi 0:8fdf9a60065b 478 #define SPI5_SSCTL_SLVTOCNT_Pos (20) /*!< SPI5_T::SSCTL: SLVTOCNT Position */
kadonotakashi 0:8fdf9a60065b 479 #define SPI5_SSCTL_SLVTOCNT_Msk (0x3fful << SPI5_SSCTL_SLVTOCNT_Pos) /*!< SPI5_T::SSCTL: SLVTOCNT Mask */
kadonotakashi 0:8fdf9a60065b 480
kadonotakashi 0:8fdf9a60065b 481 #define SPI5_RX_RX_Pos (0) /*!< SPI5_T::RX: RX Position */
kadonotakashi 0:8fdf9a60065b 482 #define SPI5_RX_RX_Msk (0xfffffffful << SPI5_RX_RX_Pos) /*!< SPI5_T::RX: RX Mask */
kadonotakashi 0:8fdf9a60065b 483
kadonotakashi 0:8fdf9a60065b 484 #define SPI5_TX_TX_Pos (0) /*!< SPI5_T::TX: TX Position */
kadonotakashi 0:8fdf9a60065b 485 #define SPI5_TX_TX_Msk (0xfffffffful << SPI5_TX_TX_Pos) /*!< SPI5_T::TX: TX Mask */
kadonotakashi 0:8fdf9a60065b 486
kadonotakashi 0:8fdf9a60065b 487 #define SPI5_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI5_T::PDMACTL: TXPDMAEN Position */
kadonotakashi 0:8fdf9a60065b 488 #define SPI5_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI5_PDMACTL_TXPDMAEN_Pos) /*!< SPI5_T::PDMACTL: TXPDMAEN Mask */
kadonotakashi 0:8fdf9a60065b 489
kadonotakashi 0:8fdf9a60065b 490 #define SPI5_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI5_T::PDMACTL: RXPDMAEN Position */
kadonotakashi 0:8fdf9a60065b 491 #define SPI5_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI5_PDMACTL_RXPDMAEN_Pos) /*!< SPI5_T::PDMACTL: RXPDMAEN Mask */
kadonotakashi 0:8fdf9a60065b 492
kadonotakashi 0:8fdf9a60065b 493 #define SPI5_PDMACTL_PDMARST_Pos (2) /*!< SPI5_T::PDMACTL: PDMARST Position */
kadonotakashi 0:8fdf9a60065b 494 #define SPI5_PDMACTL_PDMARST_Msk (0x1ul << SPI5_PDMACTL_PDMARST_Pos) /*!< SPI5_T::PDMACTL: PDMARST Mask */
kadonotakashi 0:8fdf9a60065b 495
kadonotakashi 0:8fdf9a60065b 496 #define SPI5_FIFOCTL_RXFBCLR_Pos (0) /*!< SPI5_T::FIFOCTL: RXFBCLR Position */
kadonotakashi 0:8fdf9a60065b 497 #define SPI5_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI5_FIFOCTL_RXFBCLR_Pos) /*!< SPI5_T::FIFOCTL: RXFBCLR Mask */
kadonotakashi 0:8fdf9a60065b 498
kadonotakashi 0:8fdf9a60065b 499 #define SPI5_FIFOCTL_TXFBCLR_Pos (1) /*!< SPI5_T::FIFOCTL: TXFBCLR Position */
kadonotakashi 0:8fdf9a60065b 500 #define SPI5_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI5_FIFOCTL_TXFBCLR_Pos) /*!< SPI5_T::FIFOCTL: TXFBCLR Mask */
kadonotakashi 0:8fdf9a60065b 501
kadonotakashi 0:8fdf9a60065b 502 #define SPI5_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI5_T::FIFOCTL: RXTHIEN Position */
kadonotakashi 0:8fdf9a60065b 503 #define SPI5_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI5_FIFOCTL_RXTHIEN_Pos) /*!< SPI5_T::FIFOCTL: RXTHIEN Mask */
kadonotakashi 0:8fdf9a60065b 504
kadonotakashi 0:8fdf9a60065b 505 #define SPI5_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI5_T::FIFOCTL: TXTHIEN Position */
kadonotakashi 0:8fdf9a60065b 506 #define SPI5_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI5_FIFOCTL_TXTHIEN_Pos) /*!< SPI5_T::FIFOCTL: TXTHIEN Mask */
kadonotakashi 0:8fdf9a60065b 507
kadonotakashi 0:8fdf9a60065b 508 #define SPI5_FIFOCTL_RXOVIEN_Pos (4) /*!< SPI5_T::FIFOCTL: RXOVIEN Position */
kadonotakashi 0:8fdf9a60065b 509 #define SPI5_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI5_FIFOCTL_RXOVIEN_Pos) /*!< SPI5_T::FIFOCTL: RXOVIEN Mask */
kadonotakashi 0:8fdf9a60065b 510
kadonotakashi 0:8fdf9a60065b 511 #define SPI5_FIFOCTL_RXTOIEN_Pos (7) /*!< SPI5_T::FIFOCTL: RXTOIEN Position */
kadonotakashi 0:8fdf9a60065b 512 #define SPI5_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI5_FIFOCTL_RXTOIEN_Pos) /*!< SPI5_T::FIFOCTL: RXTOIEN Mask */
kadonotakashi 0:8fdf9a60065b 513
kadonotakashi 0:8fdf9a60065b 514 #define SPI5_FIFOCTL_RXTH_Pos (24) /*!< SPI5_T::FIFOCTL: RXTH Position */
kadonotakashi 0:8fdf9a60065b 515 #define SPI5_FIFOCTL_RXTH_Msk (0x7ul << SPI5_FIFOCTL_RXTH_Pos) /*!< SPI5_T::FIFOCTL: RXTH Mask */
kadonotakashi 0:8fdf9a60065b 516
kadonotakashi 0:8fdf9a60065b 517 #define SPI5_FIFOCTL_TXTH_Pos (28) /*!< SPI5_T::FIFOCTL: TXTH Position */
kadonotakashi 0:8fdf9a60065b 518 #define SPI5_FIFOCTL_TXTH_Msk (0x7ul << SPI5_FIFOCTL_TXTH_Pos) /*!< SPI5_T::FIFOCTL: TXTH Mask */
kadonotakashi 0:8fdf9a60065b 519
kadonotakashi 0:8fdf9a60065b 520 /**@}*/ /* SPI5_CONST */
kadonotakashi 0:8fdf9a60065b 521 /**@}*/ /* end of SPI5 register group */
kadonotakashi 0:8fdf9a60065b 522
kadonotakashi 0:8fdf9a60065b 523 #endif /* __SPI5_REG_H__ */