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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/rtc_reg.h@3:f3764f852aa8, 2018-10-11 (annotated)
- Committer:
- kadonotakashi
- Date:
- Thu Oct 11 02:27:46 2018 +0000
- Revision:
- 3:f3764f852aa8
- Parent:
- 0:8fdf9a60065b
Nucreo 446 + SSD1331 test version;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
kadonotakashi | 0:8fdf9a60065b | 2 | * @file rtc_reg.h |
kadonotakashi | 0:8fdf9a60065b | 3 | * @version V1.00 |
kadonotakashi | 0:8fdf9a60065b | 4 | * @brief RTC register definition header file |
kadonotakashi | 0:8fdf9a60065b | 5 | * |
kadonotakashi | 0:8fdf9a60065b | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 7 | *****************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 8 | #ifndef __RTC_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 9 | #define __RTC_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 10 | |
kadonotakashi | 0:8fdf9a60065b | 11 | /*---------------------- Real Time Clock Controller -------------------------*/ |
kadonotakashi | 0:8fdf9a60065b | 12 | /** |
kadonotakashi | 0:8fdf9a60065b | 13 | @addtogroup RTC Real Time Clock Controller(RTC) |
kadonotakashi | 0:8fdf9a60065b | 14 | Memory Mapped Structure for RTC Controller |
kadonotakashi | 0:8fdf9a60065b | 15 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 16 | |
kadonotakashi | 0:8fdf9a60065b | 17 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 18 | { |
kadonotakashi | 0:8fdf9a60065b | 19 | |
kadonotakashi | 0:8fdf9a60065b | 20 | |
kadonotakashi | 0:8fdf9a60065b | 21 | /** |
kadonotakashi | 0:8fdf9a60065b | 22 | * @var RTC_T::INIT |
kadonotakashi | 0:8fdf9a60065b | 23 | * Offset: 0x00 RTC Initiation Register |
kadonotakashi | 0:8fdf9a60065b | 24 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 25 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 26 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 27 | * |[0] |INIT_ACTIVE|RTC Active Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 28 | * | | |0 = RTC is at reset state. |
kadonotakashi | 0:8fdf9a60065b | 29 | * | | |1 = RTC is at normal active state. |
kadonotakashi | 0:8fdf9a60065b | 30 | * |[31:1] |INIT |RTC Initiation |
kadonotakashi | 0:8fdf9a60065b | 31 | * | | |When RTC block is powered on, RTC is at reset state |
kadonotakashi | 0:8fdf9a60065b | 32 | * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state |
kadonotakashi | 0:8fdf9a60065b | 33 | * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. |
kadonotakashi | 0:8fdf9a60065b | 34 | * | | |The INIT is a write-only field and read value will be always 0. |
kadonotakashi | 0:8fdf9a60065b | 35 | * @var RTC_T::RWEN |
kadonotakashi | 0:8fdf9a60065b | 36 | * Offset: 0x04 RTC Access Enable Register |
kadonotakashi | 0:8fdf9a60065b | 37 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 38 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 39 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 40 | * |[15:0] |RWEN |RTC Register Access Enable Password (Write Only) |
kadonotakashi | 0:8fdf9a60065b | 41 | * | | |Writing 0xA965 to this field will enable RTC accessible period keeps 1024 RTC clocks. |
kadonotakashi | 0:8fdf9a60065b | 42 | * | | |Note: Writing other value will clear RWENF and disable RTC register access function immediately. |
kadonotakashi | 0:8fdf9a60065b | 43 | * |[16] |RWENF |RTC Register Access Enable Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 44 | * | | |0 = RTC register read/write Disabled. |
kadonotakashi | 0:8fdf9a60065b | 45 | * | | |1 = RTC register read/write Enabled. |
kadonotakashi | 0:8fdf9a60065b | 46 | * | | |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clocks expired. |
kadonotakashi | 0:8fdf9a60065b | 47 | * | | |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also. |
kadonotakashi | 0:8fdf9a60065b | 48 | * |[24] |RTCBUSY |RTC Write Busy Flag |
kadonotakashi | 0:8fdf9a60065b | 49 | * | | |This bit indicates RTC registers are busy or not. RTC register R/W is invalid during RTCBUSY. |
kadonotakashi | 0:8fdf9a60065b | 50 | * | | |0: RTC registers are readable and writable. |
kadonotakashi | 0:8fdf9a60065b | 51 | * | | |1: RTC registers can't R/W, RTC under Busy Status. |
kadonotakashi | 0:8fdf9a60065b | 52 | * | | |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles or PCLKRTC switch on first few cycles. |
kadonotakashi | 0:8fdf9a60065b | 53 | * | | |Note: The bit reflect RWENF (RWENF = 0 when RTCBUSY). |
kadonotakashi | 0:8fdf9a60065b | 54 | * @var RTC_T::FREQADJ |
kadonotakashi | 0:8fdf9a60065b | 55 | * Offset: 0x08 RTC Frequency Compensation Register |
kadonotakashi | 0:8fdf9a60065b | 56 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 57 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 58 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 59 | * |[21:0] |FREQADJ |Frequency Compensation Register |
kadonotakashi | 0:8fdf9a60065b | 60 | * | | |User must to get actual LXT frequency for RTC application. |
kadonotakashi | 0:8fdf9a60065b | 61 | * | | |FCR = 0x200000 * (32768 / LXT frequency). |
kadonotakashi | 0:8fdf9a60065b | 62 | * | | |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0. |
kadonotakashi | 0:8fdf9a60065b | 63 | * | | |If set RTCSEL (CLK_CLKSEL3[8]) to 1, RTC clock source is from LIRC. |
kadonotakashi | 0:8fdf9a60065b | 64 | * | | |User can set FREQADJ to execute LIRC compensation for RTC counter more accurate and the formula as below, |
kadonotakashi | 0:8fdf9a60065b | 65 | * | | |FCR = 0x80000 * (32768 / LIRC frequency). |
kadonotakashi | 0:8fdf9a60065b | 66 | * @var RTC_T::TIME |
kadonotakashi | 0:8fdf9a60065b | 67 | * Offset: 0x0C RTC Time Loading Register |
kadonotakashi | 0:8fdf9a60065b | 68 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 69 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 70 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 71 | * |[3:0] |SEC |1-Sec Time Digit (0~9) |
kadonotakashi | 0:8fdf9a60065b | 72 | * |[6:4] |TENSEC |10-Sec Time Digit (0~5) |
kadonotakashi | 0:8fdf9a60065b | 73 | * |[11:8] |MIN |1-Min Time Digit (0~9) |
kadonotakashi | 0:8fdf9a60065b | 74 | * |[14:12] |TENMIN |10-Min Time Digit (0~5) |
kadonotakashi | 0:8fdf9a60065b | 75 | * |[19:16] |HR |1-Hour Time Digit (0~9) |
kadonotakashi | 0:8fdf9a60065b | 76 | * |[21:20] |TENHR |10-Hour Time Digit (0~2) |
kadonotakashi | 0:8fdf9a60065b | 77 | * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) |
kadonotakashi | 0:8fdf9a60065b | 78 | * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F) |
kadonotakashi | 0:8fdf9a60065b | 79 | * @var RTC_T::CAL |
kadonotakashi | 0:8fdf9a60065b | 80 | * Offset: 0x10 RTC Calendar Loading Register |
kadonotakashi | 0:8fdf9a60065b | 81 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 82 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 83 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 84 | * |[3:0] |DAY |1-Day Calendar Digit (0~9) |
kadonotakashi | 0:8fdf9a60065b | 85 | * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) |
kadonotakashi | 0:8fdf9a60065b | 86 | * |[11:8] |MON |1-Month Calendar Digit (0~9) |
kadonotakashi | 0:8fdf9a60065b | 87 | * |[12] |TENMON |10-Month Calendar Digit (0~1) |
kadonotakashi | 0:8fdf9a60065b | 88 | * |[19:16] |YEAR |1-Year Calendar Digit (0~9) |
kadonotakashi | 0:8fdf9a60065b | 89 | * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) |
kadonotakashi | 0:8fdf9a60065b | 90 | * @var RTC_T::CLKFMT |
kadonotakashi | 0:8fdf9a60065b | 91 | * Offset: 0x14 RTC Time Scale Selection Register |
kadonotakashi | 0:8fdf9a60065b | 92 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 93 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 94 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 95 | * |[0] |24HEN |24-hour / 12-hour Time Scale Selection |
kadonotakashi | 0:8fdf9a60065b | 96 | * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale |
kadonotakashi | 0:8fdf9a60065b | 97 | * | | |0 = 12-hour time scale with AM and PM indication selected. |
kadonotakashi | 0:8fdf9a60065b | 98 | * | | |1 = 24-hour time scale selected. |
kadonotakashi | 0:8fdf9a60065b | 99 | * |[8] |HZCNTEN |Sub-second Counter Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 100 | * | | |0 = HZCNT disabled in RTC_TIME and RTC_TALM. |
kadonotakashi | 0:8fdf9a60065b | 101 | * | | |1 = HZCNT enabled in RTC_TIME and RTC_TALM . |
kadonotakashi | 0:8fdf9a60065b | 102 | * @var RTC_T::WEEKDAY |
kadonotakashi | 0:8fdf9a60065b | 103 | * Offset: 0x18 RTC Day of the Week Register |
kadonotakashi | 0:8fdf9a60065b | 104 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 105 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 106 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 107 | * |[2:0] |WEEKDAY |Day of the Week Register |
kadonotakashi | 0:8fdf9a60065b | 108 | * | | |000 = Sunday. |
kadonotakashi | 0:8fdf9a60065b | 109 | * | | |001 = Monday. |
kadonotakashi | 0:8fdf9a60065b | 110 | * | | |010 = Tuesday. |
kadonotakashi | 0:8fdf9a60065b | 111 | * | | |011 = Wednesday. |
kadonotakashi | 0:8fdf9a60065b | 112 | * | | |100 = Thursday. |
kadonotakashi | 0:8fdf9a60065b | 113 | * | | |101 = Friday. |
kadonotakashi | 0:8fdf9a60065b | 114 | * | | |110 = Saturday. |
kadonotakashi | 0:8fdf9a60065b | 115 | * | | |111 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 116 | * @var RTC_T::TALM |
kadonotakashi | 0:8fdf9a60065b | 117 | * Offset: 0x1C RTC Time Alarm Register |
kadonotakashi | 0:8fdf9a60065b | 118 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 119 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 120 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 121 | * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 122 | * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) |
kadonotakashi | 0:8fdf9a60065b | 123 | * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 124 | * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) |
kadonotakashi | 0:8fdf9a60065b | 125 | * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 126 | * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) |
kadonotakashi | 0:8fdf9a60065b | 127 | * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) |
kadonotakashi | 0:8fdf9a60065b | 128 | * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F) |
kadonotakashi | 0:8fdf9a60065b | 129 | * @var RTC_T::CALM |
kadonotakashi | 0:8fdf9a60065b | 130 | * Offset: 0x20 RTC Calendar Alarm Register |
kadonotakashi | 0:8fdf9a60065b | 131 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 132 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 133 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 134 | * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 135 | * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) |
kadonotakashi | 0:8fdf9a60065b | 136 | * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 137 | * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) |
kadonotakashi | 0:8fdf9a60065b | 138 | * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 139 | * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 140 | * @var RTC_T::LEAPYEAR |
kadonotakashi | 0:8fdf9a60065b | 141 | * Offset: 0x24 RTC Leap Year Indicator Register |
kadonotakashi | 0:8fdf9a60065b | 142 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 143 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 144 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 145 | * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 146 | * | | |0 = This year is not a leap year. |
kadonotakashi | 0:8fdf9a60065b | 147 | * | | |1 = This year is leap year. |
kadonotakashi | 0:8fdf9a60065b | 148 | * @var RTC_T::INTEN |
kadonotakashi | 0:8fdf9a60065b | 149 | * Offset: 0x28 RTC Interrupt Enable Register |
kadonotakashi | 0:8fdf9a60065b | 150 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 151 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 152 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 153 | * |[0] |ALMIEN |Alarm Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 154 | * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. |
kadonotakashi | 0:8fdf9a60065b | 155 | * | | |0 = RTC Alarm interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 156 | * | | |1 = RTC Alarm interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 157 | * |[1] |TICKIEN |Time Tick Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 158 | * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. |
kadonotakashi | 0:8fdf9a60065b | 159 | * | | |0 = RTC Time Tick interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 160 | * | | |1 = RTC Time Tick interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 161 | * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 162 | * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. |
kadonotakashi | 0:8fdf9a60065b | 163 | * | | |0 = Tamper 0 interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 164 | * | | |1 = Tamper 0 interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 165 | * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 166 | * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. |
kadonotakashi | 0:8fdf9a60065b | 167 | * | | |0 = Tamper 1 or Pair 0 interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 168 | * | | |1 = Tamper 1 or Pair 0 interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 169 | * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 170 | * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. |
kadonotakashi | 0:8fdf9a60065b | 171 | * | | |0 = Tamper 2 interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 172 | * | | |1 = Tamper 2 interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 173 | * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 174 | * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. |
kadonotakashi | 0:8fdf9a60065b | 175 | * | | |0 = Tamper 3 or Pair 1 interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 176 | * | | |1 = Tamper 3 or Pair 1 interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 177 | * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 178 | * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. |
kadonotakashi | 0:8fdf9a60065b | 179 | * | | |0 = Tamper 4 interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 180 | * | | |1 = Tamper 4 interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 181 | * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 182 | * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. |
kadonotakashi | 0:8fdf9a60065b | 183 | * | | |0 = Tamper 5 or Pair 2 interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 184 | * | | |1 = Tamper 5 or Pair 2 interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 185 | * |[24] |CLKFIEN |LXT Clock Frequency Monitor Fail Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 186 | * | | |0 = LXT Frequency Fail interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 187 | * | | |1 = LXT Frequency Fail interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 188 | * |[25] |CLKSPIEN |LXT Clock Frequency Monitor Stop Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 189 | * | | |0 = LXT Frequency Stop interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 190 | * | | |1 = LXT Frequency Stop interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 191 | * @var RTC_T::INTSTS |
kadonotakashi | 0:8fdf9a60065b | 192 | * Offset: 0x2C RTC Interrupt Status Register |
kadonotakashi | 0:8fdf9a60065b | 193 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 194 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 195 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 196 | * |[0] |ALMIF |RTC Alarm Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 197 | * | | |0 = Alarm condition is not matched. |
kadonotakashi | 0:8fdf9a60065b | 198 | * | | |1 = Alarm condition is matched. |
kadonotakashi | 0:8fdf9a60065b | 199 | * | | |Note: Write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 200 | * |[1] |TICKIF |RTC Time Tick Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 201 | * | | |0 = Tick condition does not occur. |
kadonotakashi | 0:8fdf9a60065b | 202 | * | | |1 = Tick condition occur. |
kadonotakashi | 0:8fdf9a60065b | 203 | * | | |Note: Write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 204 | * |[8] |TAMP0IF |Tamper 0 Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 205 | * | | |0 = No Tamper 0 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 206 | * | | |1 = Tamper 0 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 207 | * | | |Note1: Write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 208 | * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. |
kadonotakashi | 0:8fdf9a60065b | 209 | * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 210 | * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 211 | * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 212 | * | | |Note1: Write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 213 | * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. |
kadonotakashi | 0:8fdf9a60065b | 214 | * |[10] |TAMP2IF |Tamper 2 Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 215 | * | | |0 = No Tamper 2 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 216 | * | | |1 = Tamper 2 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 217 | * | | |Note1: Write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 218 | * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. |
kadonotakashi | 0:8fdf9a60065b | 219 | * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 220 | * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 221 | * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 222 | * | | |Note1: Write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 223 | * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. |
kadonotakashi | 0:8fdf9a60065b | 224 | * |[12] |TAMP4IF |Tamper 4 Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 225 | * | | |0 = No Tamper 4 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 226 | * | | |1 = Tamper 4 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 227 | * | | |Note1: Write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 228 | * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. |
kadonotakashi | 0:8fdf9a60065b | 229 | * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 230 | * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 231 | * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated. |
kadonotakashi | 0:8fdf9a60065b | 232 | * | | |Note1: Write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 233 | * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. |
kadonotakashi | 0:8fdf9a60065b | 234 | * |[24] |CLKFIF |LXT Clock Frequency Monitor Fail Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 235 | * | | |0 = LXT frequency is normal. |
kadonotakashi | 0:8fdf9a60065b | 236 | * | | |1 = LXT frequency is abnormal. |
kadonotakashi | 0:8fdf9a60065b | 237 | * | | |Note1: Write 1 to clear the bit to 0. |
kadonotakashi | 0:8fdf9a60065b | 238 | * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. |
kadonotakashi | 0:8fdf9a60065b | 239 | * |[25] |CLKSPIF |LXT Clock Frequency Monitor Stop Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 240 | * | | |0 = LXT frequency is normal. |
kadonotakashi | 0:8fdf9a60065b | 241 | * | | |1 = LXT frequency is almost stop .. |
kadonotakashi | 0:8fdf9a60065b | 242 | * | | |Note1: Write 1 to clear the bit to 0. |
kadonotakashi | 0:8fdf9a60065b | 243 | * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. |
kadonotakashi | 0:8fdf9a60065b | 244 | * @var RTC_T::TICK |
kadonotakashi | 0:8fdf9a60065b | 245 | * Offset: 0x30 RTC Time Tick Register |
kadonotakashi | 0:8fdf9a60065b | 246 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 247 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 248 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 249 | * |[2:0] |TICK |Time Tick Register |
kadonotakashi | 0:8fdf9a60065b | 250 | * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. |
kadonotakashi | 0:8fdf9a60065b | 251 | * | | |000 = Time tick is 1 second. |
kadonotakashi | 0:8fdf9a60065b | 252 | * | | |001 = Time tick is 1/2 second. |
kadonotakashi | 0:8fdf9a60065b | 253 | * | | |010 = Time tick is 1/4 second. |
kadonotakashi | 0:8fdf9a60065b | 254 | * | | |011 = Time tick is 1/8 second. |
kadonotakashi | 0:8fdf9a60065b | 255 | * | | |100 = Time tick is 1/16 second. |
kadonotakashi | 0:8fdf9a60065b | 256 | * | | |101 = Time tick is 1/32 second. |
kadonotakashi | 0:8fdf9a60065b | 257 | * | | |110 = Time tick is 1/64 second. |
kadonotakashi | 0:8fdf9a60065b | 258 | * | | |111 = Time tick is 1/128 second. |
kadonotakashi | 0:8fdf9a60065b | 259 | * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. |
kadonotakashi | 0:8fdf9a60065b | 260 | * @var RTC_T::TAMSK |
kadonotakashi | 0:8fdf9a60065b | 261 | * Offset: 0x34 RTC Time Alarm Mask Register |
kadonotakashi | 0:8fdf9a60065b | 262 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 263 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 264 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 265 | * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 266 | * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) |
kadonotakashi | 0:8fdf9a60065b | 267 | * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 268 | * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) |
kadonotakashi | 0:8fdf9a60065b | 269 | * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 270 | * | | |Note: MHR function is only for 24-hour time scale mode. |
kadonotakashi | 0:8fdf9a60065b | 271 | * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) |
kadonotakashi | 0:8fdf9a60065b | 272 | * | | |Note: MTENHR function is only for 24-hour time scale mode. |
kadonotakashi | 0:8fdf9a60065b | 273 | * @var RTC_T::CAMSK |
kadonotakashi | 0:8fdf9a60065b | 274 | * Offset: 0x38 RTC Calendar Alarm Mask Register |
kadonotakashi | 0:8fdf9a60065b | 275 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 276 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 277 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 278 | * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 279 | * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) |
kadonotakashi | 0:8fdf9a60065b | 280 | * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 281 | * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) |
kadonotakashi | 0:8fdf9a60065b | 282 | * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 283 | * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) |
kadonotakashi | 0:8fdf9a60065b | 284 | * @var RTC_T::SPRCTL |
kadonotakashi | 0:8fdf9a60065b | 285 | * Offset: 0x3C RTC Spare Functional Control Register |
kadonotakashi | 0:8fdf9a60065b | 286 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 287 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 288 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 289 | * |[2] |SPRRWEN |Spare Register Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 290 | * | | |0 = Spare register is Disabled. |
kadonotakashi | 0:8fdf9a60065b | 291 | * | | |1 = Spare register is Enabled. |
kadonotakashi | 0:8fdf9a60065b | 292 | * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. |
kadonotakashi | 0:8fdf9a60065b | 293 | * |[5] |SPRCSTS |SPR Clear Flag |
kadonotakashi | 0:8fdf9a60065b | 294 | * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected. |
kadonotakashi | 0:8fdf9a60065b | 295 | * | | |0 = Spare register content is not cleared. |
kadonotakashi | 0:8fdf9a60065b | 296 | * | | |1 = Spare register content is cleared. |
kadonotakashi | 0:8fdf9a60065b | 297 | * | | |Writes 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 298 | * | | |Note: This bit keep 1 when RTC_INTSTS[13:8] or RTC_INTSTS[25:24] are not equal zero. |
kadonotakashi | 0:8fdf9a60065b | 299 | * |[16] |LXTFCLR |LXT Clock Monitor Fail/Stop to Clear Spare Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 300 | * | | |0 = LXT monitor Fail/Stop to clear Spare register content is Disabled.. |
kadonotakashi | 0:8fdf9a60065b | 301 | * | | |1 = LXT monitor Fail/Stop to clear Spare register content is Enabled. |
kadonotakashi | 0:8fdf9a60065b | 302 | * @var RTC_T::SPR[20] |
kadonotakashi | 0:8fdf9a60065b | 303 | * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 |
kadonotakashi | 0:8fdf9a60065b | 304 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 305 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 306 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 307 | * |[31:0] |SPARE |Spare Register |
kadonotakashi | 0:8fdf9a60065b | 308 | * | | |This field is used to store back-up information defined by user. |
kadonotakashi | 0:8fdf9a60065b | 309 | * | | |This field will be cleared by hardware automatically once a tamper pin event is detected. |
kadonotakashi | 0:8fdf9a60065b | 310 | * | | |Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled. |
kadonotakashi | 0:8fdf9a60065b | 311 | * @var RTC_T::LXTCTL |
kadonotakashi | 0:8fdf9a60065b | 312 | * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register |
kadonotakashi | 0:8fdf9a60065b | 313 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 314 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 315 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 316 | * |[0] |LIRC32KEN |LIRC 32K Source Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 317 | * | | |0 = LIRC32K Disabled. |
kadonotakashi | 0:8fdf9a60065b | 318 | * | | |1 = LIRC32K.Enabled. |
kadonotakashi | 0:8fdf9a60065b | 319 | * |[3:1] |GAIN |Oscillator Gain Option |
kadonotakashi | 0:8fdf9a60065b | 320 | * | | |User can select oscillator gain according to crystal external loading and operating temperature range |
kadonotakashi | 0:8fdf9a60065b | 321 | * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. |
kadonotakashi | 0:8fdf9a60065b | 322 | * | | |000 = L0 mode. |
kadonotakashi | 0:8fdf9a60065b | 323 | * | | |001 = L1 mode. |
kadonotakashi | 0:8fdf9a60065b | 324 | * | | |010 = L2 mode. |
kadonotakashi | 0:8fdf9a60065b | 325 | * | | |011 = L3 mode. |
kadonotakashi | 0:8fdf9a60065b | 326 | * | | |100 = L4 mode. |
kadonotakashi | 0:8fdf9a60065b | 327 | * | | |101 = L5 mode. |
kadonotakashi | 0:8fdf9a60065b | 328 | * | | |110 = L6 mode. |
kadonotakashi | 0:8fdf9a60065b | 329 | * | | |111 = L7 mode (Default). |
kadonotakashi | 0:8fdf9a60065b | 330 | * |[7] |C32KS |Clock 32K Source Selection: |
kadonotakashi | 0:8fdf9a60065b | 331 | * | | |0 = Internal 32K clock is from 32K crystal . |
kadonotakashi | 0:8fdf9a60065b | 332 | * | | |1 = Internal 32K clock is from LIRC32K. |
kadonotakashi | 0:8fdf9a60065b | 333 | * @var RTC_T::GPIOCTL0 |
kadonotakashi | 0:8fdf9a60065b | 334 | * Offset: 0x104 RTC GPIO Control 0 Register |
kadonotakashi | 0:8fdf9a60065b | 335 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 336 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 337 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 338 | * |[1:0] |OPMODE0 |IO Operation Mode |
kadonotakashi | 0:8fdf9a60065b | 339 | * | | |00 = PF.0 is input only mode, without pull-up resistor. |
kadonotakashi | 0:8fdf9a60065b | 340 | * | | |01 = PF.0 is output push pull mode. |
kadonotakashi | 0:8fdf9a60065b | 341 | * | | |10 = PF.0 is open drain mode. |
kadonotakashi | 0:8fdf9a60065b | 342 | * | | |11 = PF.0 is quasi-bidirectional mode with internal pull up. |
kadonotakashi | 0:8fdf9a60065b | 343 | * |[2] |DOUT0 |IO Output Data |
kadonotakashi | 0:8fdf9a60065b | 344 | * | | |0 = PF.0 output low. |
kadonotakashi | 0:8fdf9a60065b | 345 | * | | |1 = PF.0 output high. |
kadonotakashi | 0:8fdf9a60065b | 346 | * |[3] |CTLSEL0 |IO Pin State Backup Selection |
kadonotakashi | 0:8fdf9a60065b | 347 | * | | |When low speed 32 kHz oscillator is disabled, PF.0 pin (X32KO pin) can be used as GPIO function |
kadonotakashi | 0:8fdf9a60065b | 348 | * | | |User can program CTLSEL0 to decide PF.0 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. |
kadonotakashi | 0:8fdf9a60065b | 349 | * | | |0 = PF.0 pin I/O function is controlled by GPIO module. |
kadonotakashi | 0:8fdf9a60065b | 350 | * | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off. |
kadonotakashi | 0:8fdf9a60065b | 351 | * | | |1 = PF.0 pin I/O function is controlled by VBAT power domain. |
kadonotakashi | 0:8fdf9a60065b | 352 | * | | |PF.0 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1. |
kadonotakashi | 0:8fdf9a60065b | 353 | * | | |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. |
kadonotakashi | 0:8fdf9a60065b | 354 | * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 355 | * | | |Determine PF.0 I/O pull-up or pull-down. |
kadonotakashi | 0:8fdf9a60065b | 356 | * | | |00 = PF.0 pull-up and pull-up disable. |
kadonotakashi | 0:8fdf9a60065b | 357 | * | | |01 = PF.0 pull-down enable. |
kadonotakashi | 0:8fdf9a60065b | 358 | * | | |10 = PF.0 pull-up enable. |
kadonotakashi | 0:8fdf9a60065b | 359 | * | | |11 = PF.0 pull-up and pull-up disable. |
kadonotakashi | 0:8fdf9a60065b | 360 | * | | |Note: |
kadonotakashi | 0:8fdf9a60065b | 361 | * | | |Basically, the pull-up control and pull-down control has following behavior limitation. |
kadonotakashi | 0:8fdf9a60065b | 362 | * | | |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode. |
kadonotakashi | 0:8fdf9a60065b | 363 | * | | |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode. |
kadonotakashi | 0:8fdf9a60065b | 364 | * |[9:8] |OPMODE1 |IO Operation Mode |
kadonotakashi | 0:8fdf9a60065b | 365 | * | | |00 = PF.1 is input only mode, without pull-up resistor. |
kadonotakashi | 0:8fdf9a60065b | 366 | * | | |01 = PF.1 is output push pull mode. |
kadonotakashi | 0:8fdf9a60065b | 367 | * | | |10 = PF.1 is open drain mode. |
kadonotakashi | 0:8fdf9a60065b | 368 | * | | |11 = PF.1 is quasi-bidirectional mode with internal pull up. |
kadonotakashi | 0:8fdf9a60065b | 369 | * |[10] |DOUT1 |IO Output Data |
kadonotakashi | 0:8fdf9a60065b | 370 | * | | |0 = PF.1 output low. |
kadonotakashi | 0:8fdf9a60065b | 371 | * | | |1 = PF.1 output high. |
kadonotakashi | 0:8fdf9a60065b | 372 | * |[11] |CTLSEL1 |IO Pin State Backup Selection |
kadonotakashi | 0:8fdf9a60065b | 373 | * | | |When low speed 32 kHz oscillator is disabled, PF.1 pin (X32KI pin) can be used as GPIO function |
kadonotakashi | 0:8fdf9a60065b | 374 | * | | |User can program CTLSEL1 to decide PF.1 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. |
kadonotakashi | 0:8fdf9a60065b | 375 | * | | |0 = PF.1 pin I/O function is controlled by GPIO module. |
kadonotakashi | 0:8fdf9a60065b | 376 | * | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off. |
kadonotakashi | 0:8fdf9a60065b | 377 | * | | |1 = PF.1 pin I/O function is controlled by VBAT power domain. |
kadonotakashi | 0:8fdf9a60065b | 378 | * | | |PF.1 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1. |
kadonotakashi | 0:8fdf9a60065b | 379 | * | | |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. |
kadonotakashi | 0:8fdf9a60065b | 380 | * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 381 | * | | |Determine PF.1 I/O pull-up or pull-down. |
kadonotakashi | 0:8fdf9a60065b | 382 | * | | |00 = PF.1 pull-up and pull-up disable. |
kadonotakashi | 0:8fdf9a60065b | 383 | * | | |01 = PF.1 pull-down enable. |
kadonotakashi | 0:8fdf9a60065b | 384 | * | | |10 = PF.1 pull-up enable. |
kadonotakashi | 0:8fdf9a60065b | 385 | * | | |11 = PF.1 pull-up and pull-up disable. |
kadonotakashi | 0:8fdf9a60065b | 386 | * | | |Note: |
kadonotakashi | 0:8fdf9a60065b | 387 | * | | |Basically, the pull-up control and pull-down control has following behavior limitation. |
kadonotakashi | 0:8fdf9a60065b | 388 | * | | |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode. |
kadonotakashi | 0:8fdf9a60065b | 389 | * | | |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode. |
kadonotakashi | 0:8fdf9a60065b | 390 | * |[17:16] |OPMODE2 |IO Operation Mode |
kadonotakashi | 0:8fdf9a60065b | 391 | * | | |00 = PF.2 is input only mode, without pull-up resistor. |
kadonotakashi | 0:8fdf9a60065b | 392 | * | | |01 = PF.2 is output push pull mode. |
kadonotakashi | 0:8fdf9a60065b | 393 | * | | |10 = PF.2 is open drain mode. |
kadonotakashi | 0:8fdf9a60065b | 394 | * | | |11 = PF.2 is quasi-bidirectional mode with internal pull up. |
kadonotakashi | 0:8fdf9a60065b | 395 | * |[18] |DOUT2 |IO Output Data |
kadonotakashi | 0:8fdf9a60065b | 396 | * | | |0 = PF.2 output low. |
kadonotakashi | 0:8fdf9a60065b | 397 | * | | |1 = PF.2 output high. |
kadonotakashi | 0:8fdf9a60065b | 398 | * |[19] |CTLSEL2 |IO Pin State Backup Selection |
kadonotakashi | 0:8fdf9a60065b | 399 | * | | |When TAMP0EN is disabled, PF.2 pin (TAMPER0 pin) can be used as GPIO function |
kadonotakashi | 0:8fdf9a60065b | 400 | * | | |User can program CTLSEL2 to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. |
kadonotakashi | 0:8fdf9a60065b | 401 | * | | |0 = PF.2 pin I/O function is controlled by GPIO module. |
kadonotakashi | 0:8fdf9a60065b | 402 | * | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off. |
kadonotakashi | 0:8fdf9a60065b | 403 | * | | |1 = PF.2 pin I/O function is controlled by VBAT power domain. |
kadonotakashi | 0:8fdf9a60065b | 404 | * | | |PF.2 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1. |
kadonotakashi | 0:8fdf9a60065b | 405 | * | | |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. |
kadonotakashi | 0:8fdf9a60065b | 406 | * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 407 | * | | |Determine PF.2 I/O pull-up or pull-down. |
kadonotakashi | 0:8fdf9a60065b | 408 | * | | |00 = PF.2 pull-up and pull-up disable. |
kadonotakashi | 0:8fdf9a60065b | 409 | * | | |01 = PF.2 pull-down enable. |
kadonotakashi | 0:8fdf9a60065b | 410 | * | | |10 = PF.2 pull-up enable. |
kadonotakashi | 0:8fdf9a60065b | 411 | * | | |11 = PF.2 pull-up and pull-up disable. |
kadonotakashi | 0:8fdf9a60065b | 412 | * | | |Note1: |
kadonotakashi | 0:8fdf9a60065b | 413 | * | | |Basically, the pull-up control and pull-down control has following behavior limitation. |
kadonotakashi | 0:8fdf9a60065b | 414 | * | | |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode. |
kadonotakashi | 0:8fdf9a60065b | 415 | * | | |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode. |
kadonotakashi | 0:8fdf9a60065b | 416 | * |[25:24] |OPMODE3 |IO Operation Mode |
kadonotakashi | 0:8fdf9a60065b | 417 | * | | |00 = PF.7 is input only mode, without pull-up resistor. |
kadonotakashi | 0:8fdf9a60065b | 418 | * | | |01 = PF.7 is output push pull mode. |
kadonotakashi | 0:8fdf9a60065b | 419 | * | | |10 = PF.7 is open drain mode. |
kadonotakashi | 0:8fdf9a60065b | 420 | * | | |11 = PF.7 is quasi-bidirectional mode with with internal pull up. |
kadonotakashi | 0:8fdf9a60065b | 421 | * |[26] |DOUT3 |IO Output Data |
kadonotakashi | 0:8fdf9a60065b | 422 | * | | |0 = PF.7 output low. |
kadonotakashi | 0:8fdf9a60065b | 423 | * | | |1 = PF.7 output high. |
kadonotakashi | 0:8fdf9a60065b | 424 | * |[27] |CTLSEL3 |IO Pin State Backup Selection |
kadonotakashi | 0:8fdf9a60065b | 425 | * | | |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function |
kadonotakashi | 0:8fdf9a60065b | 426 | * | | |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. |
kadonotakashi | 0:8fdf9a60065b | 427 | * | | |0 = PF.7 pin I/O function is controlled by GPIO module. |
kadonotakashi | 0:8fdf9a60065b | 428 | * | | |Hardware auto becomes CTLSEL3 = 1 when system power is turned off. |
kadonotakashi | 0:8fdf9a60065b | 429 | * | | |1 = PF.7 pin I/O function is controlled by VBAT power domain. |
kadonotakashi | 0:8fdf9a60065b | 430 | * | | |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1. |
kadonotakashi | 0:8fdf9a60065b | 431 | * | | |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. |
kadonotakashi | 0:8fdf9a60065b | 432 | * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 433 | * | | |Determine PF.7 I/O pull-up or pull-down. |
kadonotakashi | 0:8fdf9a60065b | 434 | * | | |00 = PF.7 pull-up and pull-down disable. |
kadonotakashi | 0:8fdf9a60065b | 435 | * | | |01 = PF.7 pull-down enable. |
kadonotakashi | 0:8fdf9a60065b | 436 | * | | |10 = PF.7 pull-up enable. |
kadonotakashi | 0:8fdf9a60065b | 437 | * | | |11 = PF.7 pull-up and pull-down disable. |
kadonotakashi | 0:8fdf9a60065b | 438 | * | | |Note: |
kadonotakashi | 0:8fdf9a60065b | 439 | * | | |Basically, the pull-up control and pull-down control has following behavior limitation. |
kadonotakashi | 0:8fdf9a60065b | 440 | * | | |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode. |
kadonotakashi | 0:8fdf9a60065b | 441 | * | | |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode. |
kadonotakashi | 0:8fdf9a60065b | 442 | * @var RTC_T::GPIOCTL1 |
kadonotakashi | 0:8fdf9a60065b | 443 | * Offset: 0x108 RTC GPIO Control 1 Register |
kadonotakashi | 0:8fdf9a60065b | 444 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 445 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 446 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 447 | * |[1:0] |OPMODE4 |IO Operation Mode |
kadonotakashi | 0:8fdf9a60065b | 448 | * | | |00 = PF.8 is input only mode, without pull-up resistor. |
kadonotakashi | 0:8fdf9a60065b | 449 | * | | |01 = PF.8 is output push pull mode. |
kadonotakashi | 0:8fdf9a60065b | 450 | * | | |10 = PF.8 is open drain mode. |
kadonotakashi | 0:8fdf9a60065b | 451 | * | | |11 = PF.8 is quasi-bidirectional mode with with internal pull up. |
kadonotakashi | 0:8fdf9a60065b | 452 | * |[2] |DOUT4 |IO Output Data |
kadonotakashi | 0:8fdf9a60065b | 453 | * | | |0 = PF.8 output low. |
kadonotakashi | 0:8fdf9a60065b | 454 | * | | |1 = PF.8 output high. |
kadonotakashi | 0:8fdf9a60065b | 455 | * |[3] |CTLSEL4 |IO Pin State Backup Selection |
kadonotakashi | 0:8fdf9a60065b | 456 | * | | |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function |
kadonotakashi | 0:8fdf9a60065b | 457 | * | | |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. |
kadonotakashi | 0:8fdf9a60065b | 458 | * | | |0 = PF.8 pin I/O function is controlled by GPIO module. |
kadonotakashi | 0:8fdf9a60065b | 459 | * | | |Hardware auto becomes CTLSEL4 = 1 when system power is turned off. |
kadonotakashi | 0:8fdf9a60065b | 460 | * | | |1 = PF.8 pin I/O function is controlled by VBAT power domain. |
kadonotakashi | 0:8fdf9a60065b | 461 | * | | |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1. |
kadonotakashi | 0:8fdf9a60065b | 462 | * | | |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. |
kadonotakashi | 0:8fdf9a60065b | 463 | * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 464 | * | | |Determine PF.8 I/O pull-up or pull-down. |
kadonotakashi | 0:8fdf9a60065b | 465 | * | | |00 = PF.8 pull-up and pull-down disable. |
kadonotakashi | 0:8fdf9a60065b | 466 | * | | |01 = PF.8 pull-down enable. |
kadonotakashi | 0:8fdf9a60065b | 467 | * | | |10 = PF.8 pull-up enable. |
kadonotakashi | 0:8fdf9a60065b | 468 | * | | |11 = PF.8 pull-up and pull-down disable. |
kadonotakashi | 0:8fdf9a60065b | 469 | * | | |Note: |
kadonotakashi | 0:8fdf9a60065b | 470 | * | | |Basically, the pull-up control and pull-down control has following behavior limitation. |
kadonotakashi | 0:8fdf9a60065b | 471 | * | | |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode. |
kadonotakashi | 0:8fdf9a60065b | 472 | * | | |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode. |
kadonotakashi | 0:8fdf9a60065b | 473 | * |[9:8] |OPMODE5 |IO Operation Mode |
kadonotakashi | 0:8fdf9a60065b | 474 | * | | |00 = PF.9 is input only mode, without pull-up resistor. |
kadonotakashi | 0:8fdf9a60065b | 475 | * | | |01 = PF.9 is output push pull mode. |
kadonotakashi | 0:8fdf9a60065b | 476 | * | | |10 = PF.9 is open drain mode. |
kadonotakashi | 0:8fdf9a60065b | 477 | * | | |11 = PF.9 is quasi-bidirectional mode with with internal pull up. |
kadonotakashi | 0:8fdf9a60065b | 478 | * |[10] |DOUT5 |IO Output Data |
kadonotakashi | 0:8fdf9a60065b | 479 | * | | |0 = PF.9 output low. |
kadonotakashi | 0:8fdf9a60065b | 480 | * | | |1 = PF.9 output high. |
kadonotakashi | 0:8fdf9a60065b | 481 | * |[11] |CTLSEL5 |IO Pin State Backup Selection |
kadonotakashi | 0:8fdf9a60065b | 482 | * | | |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function |
kadonotakashi | 0:8fdf9a60065b | 483 | * | | |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. |
kadonotakashi | 0:8fdf9a60065b | 484 | * | | |0 = PF.9 pin I/O function is controlled by GPIO module. |
kadonotakashi | 0:8fdf9a60065b | 485 | * | | |Hardware auto becomes CTLSEL5 = 1 when system power is turned off. |
kadonotakashi | 0:8fdf9a60065b | 486 | * | | |1 = PF.9 pin I/O function is controlled by VBAT power domain. |
kadonotakashi | 0:8fdf9a60065b | 487 | * | | |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1. |
kadonotakashi | 0:8fdf9a60065b | 488 | * | | |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. |
kadonotakashi | 0:8fdf9a60065b | 489 | * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 490 | * | | |Determine PF.9 I/O pull-up or pull-down. |
kadonotakashi | 0:8fdf9a60065b | 491 | * | | |00 = PF.9 pull-up and pull-down disable. |
kadonotakashi | 0:8fdf9a60065b | 492 | * | | |01 = PF.9 pull-down enable. |
kadonotakashi | 0:8fdf9a60065b | 493 | * | | |10 = PF.9 pull-up enable. |
kadonotakashi | 0:8fdf9a60065b | 494 | * | | |11 = PF.9 pull-up and pull-down disable. |
kadonotakashi | 0:8fdf9a60065b | 495 | * | | |.Note: |
kadonotakashi | 0:8fdf9a60065b | 496 | * | | |Basically, the pull-up control and pull-down control has following behavior limitation. |
kadonotakashi | 0:8fdf9a60065b | 497 | * | | |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode. |
kadonotakashi | 0:8fdf9a60065b | 498 | * | | |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode. |
kadonotakashi | 0:8fdf9a60065b | 499 | * |[17:16] |OPMODE6 |IO Operation Mode |
kadonotakashi | 0:8fdf9a60065b | 500 | * | | |00 = PF.10 is input only mode, without pull-up resistor. |
kadonotakashi | 0:8fdf9a60065b | 501 | * | | |01 = PF.10 is output push pull mode. |
kadonotakashi | 0:8fdf9a60065b | 502 | * | | |10 = PF.10 is open drain mode. |
kadonotakashi | 0:8fdf9a60065b | 503 | * | | |11 = PF.10 is quasi-bidirectional mode with with internal pull up. |
kadonotakashi | 0:8fdf9a60065b | 504 | * |[18] |DOUT6 |IO Output Data |
kadonotakashi | 0:8fdf9a60065b | 505 | * | | |0 = PF.10 output low. |
kadonotakashi | 0:8fdf9a60065b | 506 | * | | |1 = PF.10 output high. |
kadonotakashi | 0:8fdf9a60065b | 507 | * |[19] |CTLSEL6 |IO Pin State Backup Selection |
kadonotakashi | 0:8fdf9a60065b | 508 | * | | |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function |
kadonotakashi | 0:8fdf9a60065b | 509 | * | | |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. |
kadonotakashi | 0:8fdf9a60065b | 510 | * | | |0 = PF.10 pin I/O function is controlled by GPIO module. |
kadonotakashi | 0:8fdf9a60065b | 511 | * | | |Hardware auto becomes CTLSEL6 = 1 when system power is turned off. |
kadonotakashi | 0:8fdf9a60065b | 512 | * | | |1 = PF.10 pin I/O function is controlled by VBAT power domain. |
kadonotakashi | 0:8fdf9a60065b | 513 | * | | |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1. |
kadonotakashi | 0:8fdf9a60065b | 514 | * | | |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. |
kadonotakashi | 0:8fdf9a60065b | 515 | * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 516 | * | | |Determine PF.10 I/O pull-up or pull-down. |
kadonotakashi | 0:8fdf9a60065b | 517 | * | | |00 = PF.10 pull-up and pull-down disable. |
kadonotakashi | 0:8fdf9a60065b | 518 | * | | |01 = PF.10 pull-down enable. |
kadonotakashi | 0:8fdf9a60065b | 519 | * | | |10 = PF.10 pull-up enable. |
kadonotakashi | 0:8fdf9a60065b | 520 | * | | |11 = PF.10 pull-up and pull-down disable. |
kadonotakashi | 0:8fdf9a60065b | 521 | * | | |Note: |
kadonotakashi | 0:8fdf9a60065b | 522 | * | | |Basically, the pull-up control and pull-down control has following behavior limitation. |
kadonotakashi | 0:8fdf9a60065b | 523 | * | | |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode. |
kadonotakashi | 0:8fdf9a60065b | 524 | * | | |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode. |
kadonotakashi | 0:8fdf9a60065b | 525 | * |[25:24] |OPMODE7 |IO Operation Mode |
kadonotakashi | 0:8fdf9a60065b | 526 | * | | |00 = PF.11 is input only mode, without pull-up resistor. |
kadonotakashi | 0:8fdf9a60065b | 527 | * | | |01 = PF.11 is output push pull mode. |
kadonotakashi | 0:8fdf9a60065b | 528 | * | | |10 = PF.11 is open drain mode. |
kadonotakashi | 0:8fdf9a60065b | 529 | * | | |11 = PF.11 is quasi-bidirectional mode with with internal pull up. |
kadonotakashi | 0:8fdf9a60065b | 530 | * |[26] |DOUT7 |IO Output Data |
kadonotakashi | 0:8fdf9a60065b | 531 | * | | |0 = PF.11 output low. |
kadonotakashi | 0:8fdf9a60065b | 532 | * | | |1 = PF.11 output high. |
kadonotakashi | 0:8fdf9a60065b | 533 | * |[27] |CTLSEL7 |IO Pin State Backup Selection |
kadonotakashi | 0:8fdf9a60065b | 534 | * | | |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function |
kadonotakashi | 0:8fdf9a60065b | 535 | * | | |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. |
kadonotakashi | 0:8fdf9a60065b | 536 | * | | |0 = PF.11 pin I/O function is controlled by GPIO module. |
kadonotakashi | 0:8fdf9a60065b | 537 | * | | |Hardware auto becomes CTLSEL7 = 1 when system power is turned off. |
kadonotakashi | 0:8fdf9a60065b | 538 | * | | |1 = PF.11 pin I/O function is controlled by VBAT power domain. |
kadonotakashi | 0:8fdf9a60065b | 539 | * | | |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1. |
kadonotakashi | 0:8fdf9a60065b | 540 | * | | |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. |
kadonotakashi | 0:8fdf9a60065b | 541 | * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 542 | * | | |Determine PF.11 I/O pull-up or pull-down. |
kadonotakashi | 0:8fdf9a60065b | 543 | * | | |00 = PF.11 pull-up and pull-down disable. |
kadonotakashi | 0:8fdf9a60065b | 544 | * | | |01 = PF.11 pull-down enable. |
kadonotakashi | 0:8fdf9a60065b | 545 | * | | |10 = PF.11 pull-up enable. |
kadonotakashi | 0:8fdf9a60065b | 546 | * | | |11 = PF.11 pull-up and pull-down disable. |
kadonotakashi | 0:8fdf9a60065b | 547 | * | | |Note: |
kadonotakashi | 0:8fdf9a60065b | 548 | * | | |Basically, the pull-up control and pull-down control has following behavior limitation. |
kadonotakashi | 0:8fdf9a60065b | 549 | * | | |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode. |
kadonotakashi | 0:8fdf9a60065b | 550 | * | | |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode. |
kadonotakashi | 0:8fdf9a60065b | 551 | * @var RTC_T::DSTCTL |
kadonotakashi | 0:8fdf9a60065b | 552 | * Offset: 0x110 RTC Daylight Saving Time Control Register |
kadonotakashi | 0:8fdf9a60065b | 553 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 554 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 555 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 556 | * |[0] |ADDHR |Add 1 Hour |
kadonotakashi | 0:8fdf9a60065b | 557 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 558 | * | | |1 = Indicates RTC hour digit has been added one hour for summer time change. |
kadonotakashi | 0:8fdf9a60065b | 559 | * |[1] |SUBHR |Subtract 1 Hour |
kadonotakashi | 0:8fdf9a60065b | 560 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 561 | * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change. |
kadonotakashi | 0:8fdf9a60065b | 562 | * |[2] |DSBAK |Daylight Saving Back |
kadonotakashi | 0:8fdf9a60065b | 563 | * | | |0= Daylight Saving Change is not performed. |
kadonotakashi | 0:8fdf9a60065b | 564 | * | | |1= Daylight Saving Change is performed. |
kadonotakashi | 0:8fdf9a60065b | 565 | * @var RTC_T::TAMPCTL |
kadonotakashi | 0:8fdf9a60065b | 566 | * Offset: 0x120 RTC Tamper Pin Control Register |
kadonotakashi | 0:8fdf9a60065b | 567 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 568 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 569 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 570 | * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select |
kadonotakashi | 0:8fdf9a60065b | 571 | * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. |
kadonotakashi | 0:8fdf9a60065b | 572 | * | | |0 = Tamper input is from Tamper 2. |
kadonotakashi | 0:8fdf9a60065b | 573 | * | | |1 = Tamper input is from Tamper 0. |
kadonotakashi | 0:8fdf9a60065b | 574 | * | | |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set |
kadonotakashi | 0:8fdf9a60065b | 575 | * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select |
kadonotakashi | 0:8fdf9a60065b | 576 | * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. |
kadonotakashi | 0:8fdf9a60065b | 577 | * | | |0 = Tamper input is from Tamper 4. |
kadonotakashi | 0:8fdf9a60065b | 578 | * | | |1 = Tamper input is from Tamper 0. |
kadonotakashi | 0:8fdf9a60065b | 579 | * | | |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set |
kadonotakashi | 0:8fdf9a60065b | 580 | * |[3:2] |DYNSRC |Dynamic Reference Pattern |
kadonotakashi | 0:8fdf9a60065b | 581 | * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode. |
kadonotakashi | 0:8fdf9a60065b | 582 | * | | |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out. |
kadonotakashi | 0:8fdf9a60065b | 583 | * | | |01 = The new reference pattern is repeated previous random value when the reference pattern run out. |
kadonotakashi | 0:8fdf9a60065b | 584 | * | | |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out. |
kadonotakashi | 0:8fdf9a60065b | 585 | * | | |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set. |
kadonotakashi | 0:8fdf9a60065b | 586 | * |[4] |SEEDRLD |Reload New Seed for PRNG Engine |
kadonotakashi | 0:8fdf9a60065b | 587 | * | | |Setting this bit, the tamper configuration will be reload. |
kadonotakashi | 0:8fdf9a60065b | 588 | * | | |0 = Generating key based on the current seed. |
kadonotakashi | 0:8fdf9a60065b | 589 | * | | |1 = Reload new seed. |
kadonotakashi | 0:8fdf9a60065b | 590 | * | | |Note: Before set this bit, the tamper configuration should be set to complete. |
kadonotakashi | 0:8fdf9a60065b | 591 | * |[7:5] |DYNRATE |Dynamic Change Rate |
kadonotakashi | 0:8fdf9a60065b | 592 | * | | |This item is choice the dynamic tamper output change rate. |
kadonotakashi | 0:8fdf9a60065b | 593 | * | | |000 = 2^10 * RTC_CLK. |
kadonotakashi | 0:8fdf9a60065b | 594 | * | | |001 = 2^11 * RTC_CLK. |
kadonotakashi | 0:8fdf9a60065b | 595 | * | | |010 = 2^12 * RTC_CLK. |
kadonotakashi | 0:8fdf9a60065b | 596 | * | | |011 = 2^13 * RTC_CLK. |
kadonotakashi | 0:8fdf9a60065b | 597 | * | | |100 = 2^14 * RTC_CLK. |
kadonotakashi | 0:8fdf9a60065b | 598 | * | | |101 = 2^15 * RTC_CLK. |
kadonotakashi | 0:8fdf9a60065b | 599 | * | | |110 = 2^16 * RTC_CLK. |
kadonotakashi | 0:8fdf9a60065b | 600 | * | | |111 = 2^17 * RTC_CLK. |
kadonotakashi | 0:8fdf9a60065b | 601 | * | | |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload chage rate immediately. |
kadonotakashi | 0:8fdf9a60065b | 602 | * |[8] |TAMP0EN |Tamper0 Detect Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 603 | * | | |0 = Tamper 0 detect Disabled. |
kadonotakashi | 0:8fdf9a60065b | 604 | * | | |1 = Tamper 0 detect Enabled. |
kadonotakashi | 0:8fdf9a60065b | 605 | * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. |
kadonotakashi | 0:8fdf9a60065b | 606 | * |[9] |TAMP0LV |Tamper 0 Level |
kadonotakashi | 0:8fdf9a60065b | 607 | * | | |This bit depend on level attribute of tamper pin for static tamper detection. |
kadonotakashi | 0:8fdf9a60065b | 608 | * | | |0 = Detect voltage level is low. |
kadonotakashi | 0:8fdf9a60065b | 609 | * | | |1 = Detect voltage level is high. |
kadonotakashi | 0:8fdf9a60065b | 610 | * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 611 | * | | |0 = Tamper 0 de-bounce Disabled. |
kadonotakashi | 0:8fdf9a60065b | 612 | * | | |1 = Tamper 0 de-bounce Enabled. |
kadonotakashi | 0:8fdf9a60065b | 613 | * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 614 | * | | |0 = Tamper 1 detect Disabled. |
kadonotakashi | 0:8fdf9a60065b | 615 | * | | |1 = Tamper 1 detect Enabled. |
kadonotakashi | 0:8fdf9a60065b | 616 | * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. |
kadonotakashi | 0:8fdf9a60065b | 617 | * |[13] |TAMP1LV |Tamper 1 Level |
kadonotakashi | 0:8fdf9a60065b | 618 | * | | |This bit depend on level attribute of tamper pin for static tamper detection. |
kadonotakashi | 0:8fdf9a60065b | 619 | * | | |0 = Detect voltage level is low. |
kadonotakashi | 0:8fdf9a60065b | 620 | * | | |1 = Detect voltage level is high. |
kadonotakashi | 0:8fdf9a60065b | 621 | * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 622 | * | | |0 = Tamper 1 de-bounce Disabled. |
kadonotakashi | 0:8fdf9a60065b | 623 | * | | |1 = Tamper 1 de-bounce Enabled. |
kadonotakashi | 0:8fdf9a60065b | 624 | * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 625 | * | | |0 = Static detect. |
kadonotakashi | 0:8fdf9a60065b | 626 | * | | |1 = Dynamic detect. |
kadonotakashi | 0:8fdf9a60065b | 627 | * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 628 | * | | |0 = Tamper 2 detect Disabled. |
kadonotakashi | 0:8fdf9a60065b | 629 | * | | |1 = Tamper 2 detect Enabled. |
kadonotakashi | 0:8fdf9a60065b | 630 | * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. |
kadonotakashi | 0:8fdf9a60065b | 631 | * |[17] |TAMP2LV |Tamper 2 Level |
kadonotakashi | 0:8fdf9a60065b | 632 | * | | |This bit depend on level attribute of tamper pin for static tamper detection. |
kadonotakashi | 0:8fdf9a60065b | 633 | * | | |0 = Detect voltage level is low. |
kadonotakashi | 0:8fdf9a60065b | 634 | * | | |1 = Detect voltage level is high. |
kadonotakashi | 0:8fdf9a60065b | 635 | * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 636 | * | | |0 = Tamper 2 de-bounce Disabled. |
kadonotakashi | 0:8fdf9a60065b | 637 | * | | |1 = Tamper 2 de-bounce Enabled. |
kadonotakashi | 0:8fdf9a60065b | 638 | * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 639 | * | | |0 = Tamper 3 detect Disabled. |
kadonotakashi | 0:8fdf9a60065b | 640 | * | | |1 = Tamper 3 detect Enabled. |
kadonotakashi | 0:8fdf9a60065b | 641 | * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. |
kadonotakashi | 0:8fdf9a60065b | 642 | * |[21] |TAMP3LV |Tamper 3 Level |
kadonotakashi | 0:8fdf9a60065b | 643 | * | | |This bit depend on level attribute of tamper pin for static tamper detection. |
kadonotakashi | 0:8fdf9a60065b | 644 | * | | |0 = Detect voltage level is low. |
kadonotakashi | 0:8fdf9a60065b | 645 | * | | |1 = Detect voltage level is high. |
kadonotakashi | 0:8fdf9a60065b | 646 | * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 647 | * | | |0 = Tamper 3 de-bounce Disabled. |
kadonotakashi | 0:8fdf9a60065b | 648 | * | | |1 = Tamper 3 de-bounce Enabled. |
kadonotakashi | 0:8fdf9a60065b | 649 | * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 650 | * | | |0 = Static detect. |
kadonotakashi | 0:8fdf9a60065b | 651 | * | | |1 = Dynamic detect. |
kadonotakashi | 0:8fdf9a60065b | 652 | * |[24] |TAMP4EN |Tamper4 Detect Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 653 | * | | |0 = Tamper 4 detect Disabled. |
kadonotakashi | 0:8fdf9a60065b | 654 | * | | |1 = Tamper 4 detect Enabled. |
kadonotakashi | 0:8fdf9a60065b | 655 | * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. |
kadonotakashi | 0:8fdf9a60065b | 656 | * |[25] |TAMP4LV |Tamper 4 Level |
kadonotakashi | 0:8fdf9a60065b | 657 | * | | |This bit depend on level attribute of tamper pin for static tamper detection. |
kadonotakashi | 0:8fdf9a60065b | 658 | * | | |0 = Detect voltage level is low. |
kadonotakashi | 0:8fdf9a60065b | 659 | * | | |1 = Detect voltage level is high. |
kadonotakashi | 0:8fdf9a60065b | 660 | * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 661 | * | | |0 = Tamper 4 de-bounce Disabled. |
kadonotakashi | 0:8fdf9a60065b | 662 | * | | |1 = Tamper 4 de-bounce Enabled. |
kadonotakashi | 0:8fdf9a60065b | 663 | * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 664 | * | | |0 = Tamper 5 detect Disabled. |
kadonotakashi | 0:8fdf9a60065b | 665 | * | | |1 = Tamper 5 detect Enabled. |
kadonotakashi | 0:8fdf9a60065b | 666 | * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. |
kadonotakashi | 0:8fdf9a60065b | 667 | * |[29] |TAMP5LV |Tamper 5 Level |
kadonotakashi | 0:8fdf9a60065b | 668 | * | | |This bit depend on level attribute of tamper pin for static tamper detection. |
kadonotakashi | 0:8fdf9a60065b | 669 | * | | |0 = Detect voltage level is low. |
kadonotakashi | 0:8fdf9a60065b | 670 | * | | |1 = Detect voltage level is high. |
kadonotakashi | 0:8fdf9a60065b | 671 | * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 672 | * | | |0 = Tamper 5 de-bounce Disabled. |
kadonotakashi | 0:8fdf9a60065b | 673 | * | | |1 = Tamper 5 de-bounce Enabled. |
kadonotakashi | 0:8fdf9a60065b | 674 | * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 675 | * | | |0 = Static detect. |
kadonotakashi | 0:8fdf9a60065b | 676 | * | | |1 = Dynamic detect. |
kadonotakashi | 0:8fdf9a60065b | 677 | * @var RTC_T::TAMPSEED |
kadonotakashi | 0:8fdf9a60065b | 678 | * Offset: 0x128 RTC Tamper Dynamic Seed Register |
kadonotakashi | 0:8fdf9a60065b | 679 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 680 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 681 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 682 | * |[31:0] |SEED |Seed Value |
kadonotakashi | 0:8fdf9a60065b | 683 | * @var RTC_T::TAMPTIME |
kadonotakashi | 0:8fdf9a60065b | 684 | * Offset: 0x130 RTC Tamper Time Register |
kadonotakashi | 0:8fdf9a60065b | 685 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 686 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 687 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 688 | * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) |
kadonotakashi | 0:8fdf9a60065b | 689 | * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) |
kadonotakashi | 0:8fdf9a60065b | 690 | * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) |
kadonotakashi | 0:8fdf9a60065b | 691 | * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) |
kadonotakashi | 0:8fdf9a60065b | 692 | * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) |
kadonotakashi | 0:8fdf9a60065b | 693 | * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) Note: 24-hour time scale only . |
kadonotakashi | 0:8fdf9a60065b | 694 | * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F) |
kadonotakashi | 0:8fdf9a60065b | 695 | * @var RTC_T::TAMPCAL |
kadonotakashi | 0:8fdf9a60065b | 696 | * Offset: 0x134 RTC Tamper Calendar Register |
kadonotakashi | 0:8fdf9a60065b | 697 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 698 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 699 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 700 | * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) |
kadonotakashi | 0:8fdf9a60065b | 701 | * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) |
kadonotakashi | 0:8fdf9a60065b | 702 | * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) |
kadonotakashi | 0:8fdf9a60065b | 703 | * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) |
kadonotakashi | 0:8fdf9a60065b | 704 | * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) |
kadonotakashi | 0:8fdf9a60065b | 705 | * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) |
kadonotakashi | 0:8fdf9a60065b | 706 | * @var RTC_T::CLKDCTL |
kadonotakashi | 0:8fdf9a60065b | 707 | * Offset: 0x140 Clock Fail Detector Control Register |
kadonotakashi | 0:8fdf9a60065b | 708 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 709 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 710 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 711 | * |[0] |LXTFDEN |LXT Clock Fail/Stop Detector Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 712 | * | | |0 = LXT clock fail/stop detector Disabled. |
kadonotakashi | 0:8fdf9a60065b | 713 | * | | |1 = LXT clock fail/stop detector Enabled. |
kadonotakashi | 0:8fdf9a60065b | 714 | * | | |Note: |
kadonotakashi | 0:8fdf9a60065b | 715 | * |[1] |LXTFSW |LXT Clock Fail Detector Switch LIRC32K Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 716 | * | | |0 = LXT Clock Fail Detector Switch LIRC32K Disabled. |
kadonotakashi | 0:8fdf9a60065b | 717 | * | | |1 = Enabled |
kadonotakashi | 0:8fdf9a60065b | 718 | * | | |If LXT clock fail detector flag CLKFIF (RTC_INTSTS[24]) is generated, RTC clock source will switch to LIRC32K automatically. |
kadonotakashi | 0:8fdf9a60065b | 719 | * |[2] |LXTSPSW |LXT Clock Stop Detector Switch LIRC32K Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 720 | * | | |0 = LXT Clock Stop Detector Switch LIRC32K Disabled. |
kadonotakashi | 0:8fdf9a60065b | 721 | * | | |1 = Enabled |
kadonotakashi | 0:8fdf9a60065b | 722 | * | | |If LXT clock stop detector flag CLKSPIF (RTC_INTSTS[25]) is generated, RTC clock source will switch to LIRC32K automatically |
kadonotakashi | 0:8fdf9a60065b | 723 | * |[16] |CLKSWLIRCF|LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 724 | * | | |0 = RTC clock source from LXT. |
kadonotakashi | 0:8fdf9a60065b | 725 | * | | |1 = RTC clock source from LIRC32K . |
kadonotakashi | 0:8fdf9a60065b | 726 | * |[17] |LXTFASTF |LXT Faster Than LIRX32K Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 727 | * | | |0 = LXT frequency is slowly. |
kadonotakashi | 0:8fdf9a60065b | 728 | * | | |1 = LXT frequency faster than LIRC32K. |
kadonotakashi | 0:8fdf9a60065b | 729 | * @var RTC_T::CDBR |
kadonotakashi | 0:8fdf9a60065b | 730 | * Offset: 0x144 Clock Frequency Detector Boundary Register |
kadonotakashi | 0:8fdf9a60065b | 731 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 732 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 733 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 734 | * |[7:0] |STOPBD |LXT Clock Frequency Detector Stop Boundary |
kadonotakashi | 0:8fdf9a60065b | 735 | * | | |The bits define the stop value of frequency monitor window. |
kadonotakashi | 0:8fdf9a60065b | 736 | * | | |When LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary , the LXT frequency detect Stop interrupt flag will set to 1. |
kadonotakashi | 0:8fdf9a60065b | 737 | * | | |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time. |
kadonotakashi | 0:8fdf9a60065b | 738 | * |[23:16] |FAILBD |LXT Clock Frequency Detector Fail Boundary |
kadonotakashi | 0:8fdf9a60065b | 739 | * | | |The bits define the fail value of frequency monitor window. |
kadonotakashi | 0:8fdf9a60065b | 740 | * | | |When LXT frequency monitor counter lower than Clock Frequency Detector fail Boundary , the LXT frequency detect fail interrupt flag will set to 1. |
kadonotakashi | 0:8fdf9a60065b | 741 | * | | |Note: The boundary is defined as the minimum value of LXT among 256 LIRC32K clock time. |
kadonotakashi | 0:8fdf9a60065b | 742 | */ |
kadonotakashi | 0:8fdf9a60065b | 743 | __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ |
kadonotakashi | 0:8fdf9a60065b | 744 | __IO uint32_t RWEN; /*!< [0x0004] RTC Access Enable Register */ |
kadonotakashi | 0:8fdf9a60065b | 745 | __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ |
kadonotakashi | 0:8fdf9a60065b | 746 | __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ |
kadonotakashi | 0:8fdf9a60065b | 747 | __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ |
kadonotakashi | 0:8fdf9a60065b | 748 | __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ |
kadonotakashi | 0:8fdf9a60065b | 749 | __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ |
kadonotakashi | 0:8fdf9a60065b | 750 | __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ |
kadonotakashi | 0:8fdf9a60065b | 751 | __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ |
kadonotakashi | 0:8fdf9a60065b | 752 | __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ |
kadonotakashi | 0:8fdf9a60065b | 753 | __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ |
kadonotakashi | 0:8fdf9a60065b | 754 | __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 755 | __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ |
kadonotakashi | 0:8fdf9a60065b | 756 | __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ |
kadonotakashi | 0:8fdf9a60065b | 757 | __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ |
kadonotakashi | 0:8fdf9a60065b | 758 | __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 759 | __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008C] RTC Spare Register 0 ~ 19 */ |
kadonotakashi | 0:8fdf9a60065b | 760 | __I uint32_t RESERVE0[28]; /* 0x90 ~ 0xFC */ |
kadonotakashi | 0:8fdf9a60065b | 761 | __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 762 | __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ |
kadonotakashi | 0:8fdf9a60065b | 763 | __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */ |
kadonotakashi | 0:8fdf9a60065b | 764 | __I uint32_t RESERVE1[1]; |
kadonotakashi | 0:8fdf9a60065b | 765 | __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 766 | __I uint32_t RESERVE2[3]; |
kadonotakashi | 0:8fdf9a60065b | 767 | __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 768 | __I uint32_t RESERVE3[1]; |
kadonotakashi | 0:8fdf9a60065b | 769 | __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */ |
kadonotakashi | 0:8fdf9a60065b | 770 | __I uint32_t RESERVE4[1]; |
kadonotakashi | 0:8fdf9a60065b | 771 | __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ |
kadonotakashi | 0:8fdf9a60065b | 772 | __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ |
kadonotakashi | 0:8fdf9a60065b | 773 | __I uint32_t RESERVE5[2]; |
kadonotakashi | 0:8fdf9a60065b | 774 | __IO uint32_t CLKDCTL; /*!< [0x0140] Clock Fail Detector Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 775 | __IO uint32_t CDBR; /*!< [0x0144] Clock Frequency Detector Boundary Register */ |
kadonotakashi | 0:8fdf9a60065b | 776 | |
kadonotakashi | 0:8fdf9a60065b | 777 | } RTC_T; |
kadonotakashi | 0:8fdf9a60065b | 778 | |
kadonotakashi | 0:8fdf9a60065b | 779 | /** |
kadonotakashi | 0:8fdf9a60065b | 780 | @addtogroup RTC_CONST RTC Bit Field Definition |
kadonotakashi | 0:8fdf9a60065b | 781 | Constant Definitions for RTC Controller |
kadonotakashi | 0:8fdf9a60065b | 782 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 783 | |
kadonotakashi | 0:8fdf9a60065b | 784 | #define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */ |
kadonotakashi | 0:8fdf9a60065b | 785 | #define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 786 | |
kadonotakashi | 0:8fdf9a60065b | 787 | #define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */ |
kadonotakashi | 0:8fdf9a60065b | 788 | #define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 789 | |
kadonotakashi | 0:8fdf9a60065b | 790 | #define RTC_RWEN_RWEN_Pos (0) /*!< RTC_T::RWEN: RWEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 791 | #define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /*!< RTC_T::RWEN: RWEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 792 | |
kadonotakashi | 0:8fdf9a60065b | 793 | #define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */ |
kadonotakashi | 0:8fdf9a60065b | 794 | #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 795 | |
kadonotakashi | 0:8fdf9a60065b | 796 | #define RTC_RWEN_RTCBUSY_Pos (24) /*!< RTC_T::RWEN: RTCBUSY Position */ |
kadonotakashi | 0:8fdf9a60065b | 797 | #define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) /*!< RTC_T::RWEN: RTCBUSY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 798 | |
kadonotakashi | 0:8fdf9a60065b | 799 | #define RTC_FREQADJ_FREQADJ_Pos (0) /*!< RTC_T::FREQADJ: FREQADJ Position */ |
kadonotakashi | 0:8fdf9a60065b | 800 | #define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) /*!< RTC_T::FREQADJ: FREQADJ Mask */ |
kadonotakashi | 0:8fdf9a60065b | 801 | |
kadonotakashi | 0:8fdf9a60065b | 802 | #define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ |
kadonotakashi | 0:8fdf9a60065b | 803 | #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 804 | |
kadonotakashi | 0:8fdf9a60065b | 805 | #define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ |
kadonotakashi | 0:8fdf9a60065b | 806 | #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 807 | |
kadonotakashi | 0:8fdf9a60065b | 808 | #define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ |
kadonotakashi | 0:8fdf9a60065b | 809 | #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 810 | |
kadonotakashi | 0:8fdf9a60065b | 811 | #define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ |
kadonotakashi | 0:8fdf9a60065b | 812 | #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 813 | |
kadonotakashi | 0:8fdf9a60065b | 814 | #define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ |
kadonotakashi | 0:8fdf9a60065b | 815 | #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 816 | |
kadonotakashi | 0:8fdf9a60065b | 817 | #define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ |
kadonotakashi | 0:8fdf9a60065b | 818 | #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 819 | |
kadonotakashi | 0:8fdf9a60065b | 820 | #define RTC_TIME_HZCNT_Pos (24) /*!< RTC_T::TIME: HZCNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 821 | #define RTC_TIME_HZCNT_Msk (0x7ful << RTC_TIME_HZCNT_Pos) /*!< RTC_T::TIME: HZCNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 822 | |
kadonotakashi | 0:8fdf9a60065b | 823 | #define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ |
kadonotakashi | 0:8fdf9a60065b | 824 | #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 825 | |
kadonotakashi | 0:8fdf9a60065b | 826 | #define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ |
kadonotakashi | 0:8fdf9a60065b | 827 | #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 828 | |
kadonotakashi | 0:8fdf9a60065b | 829 | #define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ |
kadonotakashi | 0:8fdf9a60065b | 830 | #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 831 | |
kadonotakashi | 0:8fdf9a60065b | 832 | #define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ |
kadonotakashi | 0:8fdf9a60065b | 833 | #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 834 | |
kadonotakashi | 0:8fdf9a60065b | 835 | #define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ |
kadonotakashi | 0:8fdf9a60065b | 836 | #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 837 | |
kadonotakashi | 0:8fdf9a60065b | 838 | #define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ |
kadonotakashi | 0:8fdf9a60065b | 839 | #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 840 | |
kadonotakashi | 0:8fdf9a60065b | 841 | #define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 842 | #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 843 | |
kadonotakashi | 0:8fdf9a60065b | 844 | #define RTC_CLKFMT_HZCNTEN_Pos (8) /*!< RTC_T::CLKFMT: HZCNTEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 845 | #define RTC_CLKFMT_HZCNTEN_Msk (0x1ul << RTC_CLKFMT_HZCNTEN_Pos) /*!< RTC_T::CLKFMT: HZCNTEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 846 | |
kadonotakashi | 0:8fdf9a60065b | 847 | #define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ |
kadonotakashi | 0:8fdf9a60065b | 848 | #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 849 | |
kadonotakashi | 0:8fdf9a60065b | 850 | #define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ |
kadonotakashi | 0:8fdf9a60065b | 851 | #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 852 | |
kadonotakashi | 0:8fdf9a60065b | 853 | #define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ |
kadonotakashi | 0:8fdf9a60065b | 854 | #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 855 | |
kadonotakashi | 0:8fdf9a60065b | 856 | #define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ |
kadonotakashi | 0:8fdf9a60065b | 857 | #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 858 | |
kadonotakashi | 0:8fdf9a60065b | 859 | #define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ |
kadonotakashi | 0:8fdf9a60065b | 860 | #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 861 | |
kadonotakashi | 0:8fdf9a60065b | 862 | #define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ |
kadonotakashi | 0:8fdf9a60065b | 863 | #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 864 | |
kadonotakashi | 0:8fdf9a60065b | 865 | #define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ |
kadonotakashi | 0:8fdf9a60065b | 866 | #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 867 | |
kadonotakashi | 0:8fdf9a60065b | 868 | #define RTC_TALM_HZCNT_Pos (24) /*!< RTC_T::TALM: HZCNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 869 | #define RTC_TALM_HZCNT_Msk (0x7ful << RTC_TALM_HZCNT_Pos) /*!< RTC_T::TALM: HZCNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 870 | |
kadonotakashi | 0:8fdf9a60065b | 871 | #define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ |
kadonotakashi | 0:8fdf9a60065b | 872 | #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 873 | |
kadonotakashi | 0:8fdf9a60065b | 874 | #define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ |
kadonotakashi | 0:8fdf9a60065b | 875 | #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 876 | |
kadonotakashi | 0:8fdf9a60065b | 877 | #define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ |
kadonotakashi | 0:8fdf9a60065b | 878 | #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 879 | |
kadonotakashi | 0:8fdf9a60065b | 880 | #define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ |
kadonotakashi | 0:8fdf9a60065b | 881 | #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 882 | |
kadonotakashi | 0:8fdf9a60065b | 883 | #define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ |
kadonotakashi | 0:8fdf9a60065b | 884 | #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 885 | |
kadonotakashi | 0:8fdf9a60065b | 886 | #define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ |
kadonotakashi | 0:8fdf9a60065b | 887 | #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 888 | |
kadonotakashi | 0:8fdf9a60065b | 889 | #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ |
kadonotakashi | 0:8fdf9a60065b | 890 | #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 891 | |
kadonotakashi | 0:8fdf9a60065b | 892 | #define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 893 | #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 894 | |
kadonotakashi | 0:8fdf9a60065b | 895 | #define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 896 | #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 897 | |
kadonotakashi | 0:8fdf9a60065b | 898 | #define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 899 | #define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 900 | |
kadonotakashi | 0:8fdf9a60065b | 901 | #define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 902 | #define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 903 | |
kadonotakashi | 0:8fdf9a60065b | 904 | #define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 905 | #define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 906 | |
kadonotakashi | 0:8fdf9a60065b | 907 | #define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 908 | #define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 909 | |
kadonotakashi | 0:8fdf9a60065b | 910 | #define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 911 | #define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 912 | |
kadonotakashi | 0:8fdf9a60065b | 913 | #define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 914 | #define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 915 | |
kadonotakashi | 0:8fdf9a60065b | 916 | #define RTC_INTEN_CLKFIEN_Pos (24) /*!< RTC_T::INTEN: CLKFIEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 917 | #define RTC_INTEN_CLKFIEN_Msk (0x1ul << RTC_INTEN_CLKFIEN_Pos) /*!< RTC_T::INTEN: CLKFIEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 918 | |
kadonotakashi | 0:8fdf9a60065b | 919 | #define RTC_INTEN_CLKSPIEN_Pos (25) /*!< RTC_T::INTEN: CLKSPIEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 920 | #define RTC_INTEN_CLKSPIEN_Msk (0x1ul << RTC_INTEN_CLKSPIEN_Pos) /*!< RTC_T::INTEN: CLKSPIEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 921 | |
kadonotakashi | 0:8fdf9a60065b | 922 | #define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ |
kadonotakashi | 0:8fdf9a60065b | 923 | #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 924 | |
kadonotakashi | 0:8fdf9a60065b | 925 | #define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ |
kadonotakashi | 0:8fdf9a60065b | 926 | #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 927 | |
kadonotakashi | 0:8fdf9a60065b | 928 | #define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ |
kadonotakashi | 0:8fdf9a60065b | 929 | #define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 930 | |
kadonotakashi | 0:8fdf9a60065b | 931 | #define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */ |
kadonotakashi | 0:8fdf9a60065b | 932 | #define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 933 | |
kadonotakashi | 0:8fdf9a60065b | 934 | #define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */ |
kadonotakashi | 0:8fdf9a60065b | 935 | #define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 936 | |
kadonotakashi | 0:8fdf9a60065b | 937 | #define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */ |
kadonotakashi | 0:8fdf9a60065b | 938 | #define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 939 | |
kadonotakashi | 0:8fdf9a60065b | 940 | #define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */ |
kadonotakashi | 0:8fdf9a60065b | 941 | #define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 942 | |
kadonotakashi | 0:8fdf9a60065b | 943 | #define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */ |
kadonotakashi | 0:8fdf9a60065b | 944 | #define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 945 | |
kadonotakashi | 0:8fdf9a60065b | 946 | #define RTC_INTSTS_CLKFIF_Pos (24) /*!< RTC_T::INTSTS: CLKFIF Position */ |
kadonotakashi | 0:8fdf9a60065b | 947 | #define RTC_INTSTS_CLKFIF_Msk (0x1ul << RTC_INTSTS_CLKFIF_Pos) /*!< RTC_T::INTSTS: CLKFIF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 948 | |
kadonotakashi | 0:8fdf9a60065b | 949 | #define RTC_INTSTS_CLKSPIF_Pos (25) /*!< RTC_T::INTSTS: CLKSPIF Position */ |
kadonotakashi | 0:8fdf9a60065b | 950 | #define RTC_INTSTS_CLKSPIF_Msk (0x1ul << RTC_INTSTS_CLKSPIF_Pos) /*!< RTC_T::INTSTS: CLKSPIF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 951 | |
kadonotakashi | 0:8fdf9a60065b | 952 | #define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ |
kadonotakashi | 0:8fdf9a60065b | 953 | #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 954 | |
kadonotakashi | 0:8fdf9a60065b | 955 | #define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ |
kadonotakashi | 0:8fdf9a60065b | 956 | #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 957 | |
kadonotakashi | 0:8fdf9a60065b | 958 | #define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ |
kadonotakashi | 0:8fdf9a60065b | 959 | #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 960 | |
kadonotakashi | 0:8fdf9a60065b | 961 | #define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ |
kadonotakashi | 0:8fdf9a60065b | 962 | #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 963 | |
kadonotakashi | 0:8fdf9a60065b | 964 | #define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ |
kadonotakashi | 0:8fdf9a60065b | 965 | #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 966 | |
kadonotakashi | 0:8fdf9a60065b | 967 | #define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ |
kadonotakashi | 0:8fdf9a60065b | 968 | #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 969 | |
kadonotakashi | 0:8fdf9a60065b | 970 | #define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ |
kadonotakashi | 0:8fdf9a60065b | 971 | #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 972 | |
kadonotakashi | 0:8fdf9a60065b | 973 | #define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ |
kadonotakashi | 0:8fdf9a60065b | 974 | #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 975 | |
kadonotakashi | 0:8fdf9a60065b | 976 | #define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ |
kadonotakashi | 0:8fdf9a60065b | 977 | #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 978 | |
kadonotakashi | 0:8fdf9a60065b | 979 | #define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ |
kadonotakashi | 0:8fdf9a60065b | 980 | #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 981 | |
kadonotakashi | 0:8fdf9a60065b | 982 | #define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ |
kadonotakashi | 0:8fdf9a60065b | 983 | #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 984 | |
kadonotakashi | 0:8fdf9a60065b | 985 | #define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ |
kadonotakashi | 0:8fdf9a60065b | 986 | #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 987 | |
kadonotakashi | 0:8fdf9a60065b | 988 | #define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ |
kadonotakashi | 0:8fdf9a60065b | 989 | #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 990 | |
kadonotakashi | 0:8fdf9a60065b | 991 | #define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 992 | #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 993 | |
kadonotakashi | 0:8fdf9a60065b | 994 | #define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ |
kadonotakashi | 0:8fdf9a60065b | 995 | #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 996 | |
kadonotakashi | 0:8fdf9a60065b | 997 | #define RTC_SPRCTL_LXTFCLR_Pos (16) /*!< RTC_T::SPRCTL: LXTFCLR Position */ |
kadonotakashi | 0:8fdf9a60065b | 998 | #define RTC_SPRCTL_LXTFCLR_Msk (0x1ul << RTC_SPRCTL_LXTFCLR_Pos) /*!< RTC_T::SPRCTL: LXTFCLR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 999 | |
kadonotakashi | 0:8fdf9a60065b | 1000 | #define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1001 | #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1002 | |
kadonotakashi | 0:8fdf9a60065b | 1003 | #define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1004 | #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1005 | |
kadonotakashi | 0:8fdf9a60065b | 1006 | #define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1007 | #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1008 | |
kadonotakashi | 0:8fdf9a60065b | 1009 | #define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1010 | #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1011 | |
kadonotakashi | 0:8fdf9a60065b | 1012 | #define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1013 | #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1014 | |
kadonotakashi | 0:8fdf9a60065b | 1015 | #define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1016 | #define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1017 | |
kadonotakashi | 0:8fdf9a60065b | 1018 | #define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1019 | #define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1020 | |
kadonotakashi | 0:8fdf9a60065b | 1021 | #define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1022 | #define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1023 | |
kadonotakashi | 0:8fdf9a60065b | 1024 | #define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1025 | #define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1026 | |
kadonotakashi | 0:8fdf9a60065b | 1027 | #define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1028 | #define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1029 | |
kadonotakashi | 0:8fdf9a60065b | 1030 | #define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1031 | #define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1032 | |
kadonotakashi | 0:8fdf9a60065b | 1033 | #define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1034 | #define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1035 | |
kadonotakashi | 0:8fdf9a60065b | 1036 | #define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1037 | #define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1038 | |
kadonotakashi | 0:8fdf9a60065b | 1039 | #define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1040 | #define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1041 | |
kadonotakashi | 0:8fdf9a60065b | 1042 | #define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1043 | #define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1044 | |
kadonotakashi | 0:8fdf9a60065b | 1045 | #define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1046 | #define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1047 | |
kadonotakashi | 0:8fdf9a60065b | 1048 | #define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1049 | #define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1050 | |
kadonotakashi | 0:8fdf9a60065b | 1051 | #define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1052 | #define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1053 | |
kadonotakashi | 0:8fdf9a60065b | 1054 | #define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1055 | #define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1056 | |
kadonotakashi | 0:8fdf9a60065b | 1057 | #define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1058 | #define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1059 | |
kadonotakashi | 0:8fdf9a60065b | 1060 | #define RTC_LXTCTL_LIRC32KEN_Pos (0) /*!< RTC_T::LXTCTL: LIRC32KEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1061 | #define RTC_LXTCTL_LIRC32KEN_Msk (0x1ul << RTC_LXTCTL_LIRC32KEN_Pos) /*!< RTC_T::LXTCTL: LIRC32KEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1062 | |
kadonotakashi | 0:8fdf9a60065b | 1063 | #define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1064 | #define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1065 | |
kadonotakashi | 0:8fdf9a60065b | 1066 | #define RTC_LXTCTL_C32KS_Pos (7) /*!< RTC_T::LXTCTL: C32KS Position */ |
kadonotakashi | 0:8fdf9a60065b | 1067 | #define RTC_LXTCTL_C32KS_Msk (0x1ul << RTC_LXTCTL_C32KS_Pos) /*!< RTC_T::LXTCTL: C32KS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1068 | |
kadonotakashi | 0:8fdf9a60065b | 1069 | #define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1070 | #define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1071 | |
kadonotakashi | 0:8fdf9a60065b | 1072 | #define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1073 | #define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1074 | |
kadonotakashi | 0:8fdf9a60065b | 1075 | #define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1076 | #define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1077 | |
kadonotakashi | 0:8fdf9a60065b | 1078 | #define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1079 | #define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1080 | |
kadonotakashi | 0:8fdf9a60065b | 1081 | #define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1082 | #define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1083 | |
kadonotakashi | 0:8fdf9a60065b | 1084 | #define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1085 | #define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1086 | |
kadonotakashi | 0:8fdf9a60065b | 1087 | #define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1088 | #define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1089 | |
kadonotakashi | 0:8fdf9a60065b | 1090 | #define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1091 | #define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1092 | |
kadonotakashi | 0:8fdf9a60065b | 1093 | #define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1094 | #define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1095 | |
kadonotakashi | 0:8fdf9a60065b | 1096 | #define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1097 | #define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1098 | |
kadonotakashi | 0:8fdf9a60065b | 1099 | #define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1100 | #define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1101 | |
kadonotakashi | 0:8fdf9a60065b | 1102 | #define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1103 | #define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1104 | |
kadonotakashi | 0:8fdf9a60065b | 1105 | #define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1106 | #define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1107 | |
kadonotakashi | 0:8fdf9a60065b | 1108 | #define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1109 | #define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1110 | |
kadonotakashi | 0:8fdf9a60065b | 1111 | #define RTC_GPIOCTL0_CTLSEL3_Pos (27) /*!< RTC_T::GPIOCTL0: CTLSEL3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1112 | #define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1113 | |
kadonotakashi | 0:8fdf9a60065b | 1114 | #define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1115 | #define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1116 | |
kadonotakashi | 0:8fdf9a60065b | 1117 | #define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1118 | #define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1119 | |
kadonotakashi | 0:8fdf9a60065b | 1120 | #define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1121 | #define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1122 | |
kadonotakashi | 0:8fdf9a60065b | 1123 | #define RTC_GPIOCTL1_CTLSEL4_Pos (3) /*!< RTC_T::GPIOCTL1: CTLSEL4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1124 | #define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1125 | |
kadonotakashi | 0:8fdf9a60065b | 1126 | #define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1127 | #define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1128 | |
kadonotakashi | 0:8fdf9a60065b | 1129 | #define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1130 | #define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1131 | |
kadonotakashi | 0:8fdf9a60065b | 1132 | #define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1133 | #define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1134 | |
kadonotakashi | 0:8fdf9a60065b | 1135 | #define RTC_GPIOCTL1_CTLSEL5_Pos (11) /*!< RTC_T::GPIOCTL1: CTLSEL5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1136 | #define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1137 | |
kadonotakashi | 0:8fdf9a60065b | 1138 | #define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1139 | #define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1140 | |
kadonotakashi | 0:8fdf9a60065b | 1141 | #define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1142 | #define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1143 | |
kadonotakashi | 0:8fdf9a60065b | 1144 | #define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1145 | #define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1146 | |
kadonotakashi | 0:8fdf9a60065b | 1147 | #define RTC_GPIOCTL1_CTLSEL6_Pos (19) /*!< RTC_T::GPIOCTL1: CTLSEL6 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1148 | #define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1149 | |
kadonotakashi | 0:8fdf9a60065b | 1150 | #define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1151 | #define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1152 | |
kadonotakashi | 0:8fdf9a60065b | 1153 | #define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1154 | #define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1155 | |
kadonotakashi | 0:8fdf9a60065b | 1156 | #define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1157 | #define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1158 | |
kadonotakashi | 0:8fdf9a60065b | 1159 | #define RTC_GPIOCTL1_CTLSEL7_Pos (27) /*!< RTC_T::GPIOCTL1: CTLSEL7 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1160 | #define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1161 | |
kadonotakashi | 0:8fdf9a60065b | 1162 | #define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */ |
kadonotakashi | 0:8fdf9a60065b | 1163 | #define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1164 | |
kadonotakashi | 0:8fdf9a60065b | 1165 | #define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ |
kadonotakashi | 0:8fdf9a60065b | 1166 | #define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1167 | |
kadonotakashi | 0:8fdf9a60065b | 1168 | #define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ |
kadonotakashi | 0:8fdf9a60065b | 1169 | #define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1170 | |
kadonotakashi | 0:8fdf9a60065b | 1171 | #define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1172 | #define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1173 | |
kadonotakashi | 0:8fdf9a60065b | 1174 | #define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */ |
kadonotakashi | 0:8fdf9a60065b | 1175 | #define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1176 | |
kadonotakashi | 0:8fdf9a60065b | 1177 | #define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */ |
kadonotakashi | 0:8fdf9a60065b | 1178 | #define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1179 | |
kadonotakashi | 0:8fdf9a60065b | 1180 | #define RTC_TAMPCTL_DYNSRC_Pos (2) /*!< RTC_T::TAMPCTL: DYNSRC Position */ |
kadonotakashi | 0:8fdf9a60065b | 1181 | #define RTC_TAMPCTL_DYNSRC_Msk (0x3ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1182 | |
kadonotakashi | 0:8fdf9a60065b | 1183 | #define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */ |
kadonotakashi | 0:8fdf9a60065b | 1184 | #define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1185 | |
kadonotakashi | 0:8fdf9a60065b | 1186 | #define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1187 | #define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1188 | |
kadonotakashi | 0:8fdf9a60065b | 1189 | #define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1190 | #define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1191 | |
kadonotakashi | 0:8fdf9a60065b | 1192 | #define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1193 | #define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1194 | |
kadonotakashi | 0:8fdf9a60065b | 1195 | #define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1196 | #define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1197 | |
kadonotakashi | 0:8fdf9a60065b | 1198 | #define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1199 | #define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1200 | |
kadonotakashi | 0:8fdf9a60065b | 1201 | #define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1202 | #define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1203 | |
kadonotakashi | 0:8fdf9a60065b | 1204 | #define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1205 | #define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1206 | |
kadonotakashi | 0:8fdf9a60065b | 1207 | #define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1208 | #define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1209 | |
kadonotakashi | 0:8fdf9a60065b | 1210 | #define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1211 | #define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1212 | |
kadonotakashi | 0:8fdf9a60065b | 1213 | #define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1214 | #define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1215 | |
kadonotakashi | 0:8fdf9a60065b | 1216 | #define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1217 | #define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1218 | |
kadonotakashi | 0:8fdf9a60065b | 1219 | #define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1220 | #define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1221 | |
kadonotakashi | 0:8fdf9a60065b | 1222 | #define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1223 | #define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1224 | |
kadonotakashi | 0:8fdf9a60065b | 1225 | #define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1226 | #define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1227 | |
kadonotakashi | 0:8fdf9a60065b | 1228 | #define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1229 | #define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1230 | |
kadonotakashi | 0:8fdf9a60065b | 1231 | #define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1232 | #define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1233 | |
kadonotakashi | 0:8fdf9a60065b | 1234 | #define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1235 | #define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1236 | |
kadonotakashi | 0:8fdf9a60065b | 1237 | #define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1238 | #define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1239 | |
kadonotakashi | 0:8fdf9a60065b | 1240 | #define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1241 | #define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1242 | |
kadonotakashi | 0:8fdf9a60065b | 1243 | #define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1244 | #define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1245 | |
kadonotakashi | 0:8fdf9a60065b | 1246 | #define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1247 | #define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1248 | |
kadonotakashi | 0:8fdf9a60065b | 1249 | #define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1250 | #define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1251 | |
kadonotakashi | 0:8fdf9a60065b | 1252 | #define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */ |
kadonotakashi | 0:8fdf9a60065b | 1253 | #define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1254 | |
kadonotakashi | 0:8fdf9a60065b | 1255 | #define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ |
kadonotakashi | 0:8fdf9a60065b | 1256 | #define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1257 | |
kadonotakashi | 0:8fdf9a60065b | 1258 | #define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ |
kadonotakashi | 0:8fdf9a60065b | 1259 | #define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1260 | |
kadonotakashi | 0:8fdf9a60065b | 1261 | #define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1262 | #define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1263 | |
kadonotakashi | 0:8fdf9a60065b | 1264 | #define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1265 | #define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1266 | |
kadonotakashi | 0:8fdf9a60065b | 1267 | #define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ |
kadonotakashi | 0:8fdf9a60065b | 1268 | #define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1269 | |
kadonotakashi | 0:8fdf9a60065b | 1270 | #define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ |
kadonotakashi | 0:8fdf9a60065b | 1271 | #define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1272 | |
kadonotakashi | 0:8fdf9a60065b | 1273 | #define RTC_TAMPTIME_HZCNT_Pos (24) /*!< RTC_T::TAMPTIME: HZCNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 1274 | #define RTC_TAMPTIME_HZCNT_Msk (0x7ful << RTC_TAMPTIME_HZCNT_Pos) /*!< RTC_T::TAMPTIME: HZCNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1275 | |
kadonotakashi | 0:8fdf9a60065b | 1276 | #define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ |
kadonotakashi | 0:8fdf9a60065b | 1277 | #define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1278 | |
kadonotakashi | 0:8fdf9a60065b | 1279 | #define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ |
kadonotakashi | 0:8fdf9a60065b | 1280 | #define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1281 | |
kadonotakashi | 0:8fdf9a60065b | 1282 | #define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ |
kadonotakashi | 0:8fdf9a60065b | 1283 | #define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1284 | |
kadonotakashi | 0:8fdf9a60065b | 1285 | #define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ |
kadonotakashi | 0:8fdf9a60065b | 1286 | #define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1287 | |
kadonotakashi | 0:8fdf9a60065b | 1288 | #define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ |
kadonotakashi | 0:8fdf9a60065b | 1289 | #define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1290 | |
kadonotakashi | 0:8fdf9a60065b | 1291 | #define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ |
kadonotakashi | 0:8fdf9a60065b | 1292 | #define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1293 | |
kadonotakashi | 0:8fdf9a60065b | 1294 | #define RTC_CLKDCTL_LXTFDEN_Pos (0) /*!< RTC_T::CLKDCTL: LXTFDEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1295 | #define RTC_CLKDCTL_LXTFDEN_Msk (0x1ul << RTC_CLKDCTL_LXTFDEN_Pos) /*!< RTC_T::CLKDCTL: LXTFDEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1296 | |
kadonotakashi | 0:8fdf9a60065b | 1297 | #define RTC_CLKDCTL_LXTFSW_Pos (1) /*!< RTC_T::CLKDCTL: LXTFSW Position */ |
kadonotakashi | 0:8fdf9a60065b | 1298 | #define RTC_CLKDCTL_LXTFSW_Msk (0x1ul << RTC_CLKDCTL_LXTFSW_Pos) /*!< RTC_T::CLKDCTL: LXTFSW Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1299 | |
kadonotakashi | 0:8fdf9a60065b | 1300 | #define RTC_CLKDCTL_LXTSPSW_Pos (2) /*!< RTC_T::CLKDCTL: LXTSPSW Position */ |
kadonotakashi | 0:8fdf9a60065b | 1301 | #define RTC_CLKDCTL_LXTSPSW_Msk (0x1ul << RTC_CLKDCTL_LXTSPSW_Pos) /*!< RTC_T::CLKDCTL: LXTSPSW Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1302 | |
kadonotakashi | 0:8fdf9a60065b | 1303 | #define RTC_CLKDCTL_CLKSWLIRCF_Pos (16) /*!< RTC_T::CLKDCTL: CLKSWLIRCF Position */ |
kadonotakashi | 0:8fdf9a60065b | 1304 | #define RTC_CLKDCTL_CLKSWLIRCF_Msk (0x1ul << RTC_CLKDCTL_CLKSWLIRCF_Pos) /*!< RTC_T::CLKDCTL: CLKSWLIRCF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1305 | |
kadonotakashi | 0:8fdf9a60065b | 1306 | #define RTC_CLKDCTL_LXTFASTF_Pos (17) /*!< RTC_T::CLKDCTL: LXTFASTF Position */ |
kadonotakashi | 0:8fdf9a60065b | 1307 | #define RTC_CLKDCTL_LXTFASTF_Msk (0x1ul << RTC_CLKDCTL_LXTFASTF_Pos) /*!< RTC_T::CLKDCTL: LXTFASTF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1308 | |
kadonotakashi | 0:8fdf9a60065b | 1309 | #define RTC_CDBR_STOPBD_Pos (0) /*!< RTC_T::CDBR: STOPBD Position */ |
kadonotakashi | 0:8fdf9a60065b | 1310 | #define RTC_CDBR_STOPBD_Msk (0xfful << RTC_CDBR_STOPBD_Pos) /*!< RTC_T::CDBR: STOPBD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1311 | |
kadonotakashi | 0:8fdf9a60065b | 1312 | #define RTC_CDBR_FAILBD_Pos (16) /*!< RTC_T::CDBR: FAILBD Position */ |
kadonotakashi | 0:8fdf9a60065b | 1313 | #define RTC_CDBR_FAILBD_Msk (0xfful << RTC_CDBR_FAILBD_Pos) /*!< RTC_T::CDBR: FAILBD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1314 | |
kadonotakashi | 0:8fdf9a60065b | 1315 | /**@}*/ /* RTC_CONST */ |
kadonotakashi | 0:8fdf9a60065b | 1316 | /**@}*/ /* end of RTC register group */ |
kadonotakashi | 0:8fdf9a60065b | 1317 | |
kadonotakashi | 0:8fdf9a60065b | 1318 | |
kadonotakashi | 0:8fdf9a60065b | 1319 | |
kadonotakashi | 0:8fdf9a60065b | 1320 | #endif /* __RTC_REG_H__ */ |