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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/ebi_reg.h@3:f3764f852aa8, 2018-10-11 (annotated)
- Committer:
- kadonotakashi
- Date:
- Thu Oct 11 02:27:46 2018 +0000
- Revision:
- 3:f3764f852aa8
- Parent:
- 0:8fdf9a60065b
Nucreo 446 + SSD1331 test version;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
kadonotakashi | 0:8fdf9a60065b | 2 | * @file ebi_reg.h |
kadonotakashi | 0:8fdf9a60065b | 3 | * @version V1.00 |
kadonotakashi | 0:8fdf9a60065b | 4 | * @brief EBI register definition header file |
kadonotakashi | 0:8fdf9a60065b | 5 | * |
kadonotakashi | 0:8fdf9a60065b | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 7 | *****************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 8 | #ifndef __EBI_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 9 | #define __EBI_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 10 | |
kadonotakashi | 0:8fdf9a60065b | 11 | |
kadonotakashi | 0:8fdf9a60065b | 12 | /*---------------------- External Bus Interface Controller -------------------------*/ |
kadonotakashi | 0:8fdf9a60065b | 13 | /** |
kadonotakashi | 0:8fdf9a60065b | 14 | @addtogroup EBI External Bus Interface Controller(EBI) |
kadonotakashi | 0:8fdf9a60065b | 15 | Memory Mapped Structure for EBI Controller |
kadonotakashi | 0:8fdf9a60065b | 16 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 17 | |
kadonotakashi | 0:8fdf9a60065b | 18 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 19 | { |
kadonotakashi | 0:8fdf9a60065b | 20 | |
kadonotakashi | 0:8fdf9a60065b | 21 | |
kadonotakashi | 0:8fdf9a60065b | 22 | /** |
kadonotakashi | 0:8fdf9a60065b | 23 | * @var EBI_T::CTL |
kadonotakashi | 0:8fdf9a60065b | 24 | * Offset: 0x00 External Bus Interface Control Register |
kadonotakashi | 0:8fdf9a60065b | 25 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 26 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 27 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 28 | * |[0] |EN |EBI Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 29 | * | | |This bit is the functional enable bit for EBI. |
kadonotakashi | 0:8fdf9a60065b | 30 | * | | |0 = EBI function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 31 | * | | |1 = EBI function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 32 | * |[1] |DW16 |EBI Data Width 16-bit Select |
kadonotakashi | 0:8fdf9a60065b | 33 | * | | |This bit defines if the EBI data width is 8-bit or 16-bit. |
kadonotakashi | 0:8fdf9a60065b | 34 | * | | |0 = EBI data width is 8-bit. |
kadonotakashi | 0:8fdf9a60065b | 35 | * | | |1 = EBI data width is 16-bit. |
kadonotakashi | 0:8fdf9a60065b | 36 | * |[2] |CSPOLINV |Chip Select Pin Polar Inverse |
kadonotakashi | 0:8fdf9a60065b | 37 | * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). |
kadonotakashi | 0:8fdf9a60065b | 38 | * | | |0 = Chip select pin (EBI_nCS) is active low. |
kadonotakashi | 0:8fdf9a60065b | 39 | * | | |1 = Chip select pin (EBI_nCS) is active high. |
kadonotakashi | 0:8fdf9a60065b | 40 | * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 41 | * | | |0 = Address/Data Bus Separating Mode Disabled. |
kadonotakashi | 0:8fdf9a60065b | 42 | * | | |1 = Address/Data Bus Separating Mode Enabled. |
kadonotakashi | 0:8fdf9a60065b | 43 | * |[4] |CACCESS |Continuous Data Access Mode |
kadonotakashi | 0:8fdf9a60065b | 44 | * | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. |
kadonotakashi | 0:8fdf9a60065b | 45 | * | | |0 = Continuous data access mode Disabled. |
kadonotakashi | 0:8fdf9a60065b | 46 | * | | |1 = Continuous data access mode Enabled. |
kadonotakashi | 0:8fdf9a60065b | 47 | * |[10:8] |MCLKDIV |External Output Clock Divider |
kadonotakashi | 0:8fdf9a60065b | 48 | * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: |
kadonotakashi | 0:8fdf9a60065b | 49 | * | | |000 = HCLK/1. |
kadonotakashi | 0:8fdf9a60065b | 50 | * | | |001 = HCLK/2. |
kadonotakashi | 0:8fdf9a60065b | 51 | * | | |010 = HCLK/4. |
kadonotakashi | 0:8fdf9a60065b | 52 | * | | |011 = HCLK/8. |
kadonotakashi | 0:8fdf9a60065b | 53 | * | | |100 = HCLK/16. |
kadonotakashi | 0:8fdf9a60065b | 54 | * | | |101 = HCLK/32. |
kadonotakashi | 0:8fdf9a60065b | 55 | * | | |110 = HCLK/64. |
kadonotakashi | 0:8fdf9a60065b | 56 | * | | |111 = HCLK/128. |
kadonotakashi | 0:8fdf9a60065b | 57 | * |[18:16] |TALE |Extend Time of ALE |
kadonotakashi | 0:8fdf9a60065b | 58 | * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. |
kadonotakashi | 0:8fdf9a60065b | 59 | * | | |tALE = (TALE+1)*EBI_MCLK. |
kadonotakashi | 0:8fdf9a60065b | 60 | * | | |Note: This field only available in EBI_CTL0 register |
kadonotakashi | 0:8fdf9a60065b | 61 | * @var EBI_T::TCTL |
kadonotakashi | 0:8fdf9a60065b | 62 | * Offset: 0x04 External Bus Interface Timing Control Register |
kadonotakashi | 0:8fdf9a60065b | 63 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 64 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 65 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 66 | * |[7:3] |TACC |EBI Data Access Time |
kadonotakashi | 0:8fdf9a60065b | 67 | * | | |TACC define data access time (tACC). |
kadonotakashi | 0:8fdf9a60065b | 68 | * | | |tACC = (TACC+1) * EBI_MCLK. |
kadonotakashi | 0:8fdf9a60065b | 69 | * |[10:8] |TAHD |EBI Data Access Hold Time |
kadonotakashi | 0:8fdf9a60065b | 70 | * | | |TAHD define data access hold time (tAHD). |
kadonotakashi | 0:8fdf9a60065b | 71 | * | | |tAHD = (TAHD+1) * EBI_MCLK. |
kadonotakashi | 0:8fdf9a60065b | 72 | * |[15:12] |W2X |Idle Cycle After Write |
kadonotakashi | 0:8fdf9a60065b | 73 | * | | |This field defines the number of W2X idle cycle. |
kadonotakashi | 0:8fdf9a60065b | 74 | * | | |W2X idle cycle = (W2X * EBI_MCLK). |
kadonotakashi | 0:8fdf9a60065b | 75 | * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. |
kadonotakashi | 0:8fdf9a60065b | 76 | * |[22] |RAHDOFF |Access Hold Time Disable Control When Read |
kadonotakashi | 0:8fdf9a60065b | 77 | * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. |
kadonotakashi | 0:8fdf9a60065b | 78 | * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. |
kadonotakashi | 0:8fdf9a60065b | 79 | * |[23] |WAHDOFF |Access Hold Time Disable Control When Write |
kadonotakashi | 0:8fdf9a60065b | 80 | * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. |
kadonotakashi | 0:8fdf9a60065b | 81 | * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. |
kadonotakashi | 0:8fdf9a60065b | 82 | * |[27:24] |R2R |Idle Cycle Between Read-to-read |
kadonotakashi | 0:8fdf9a60065b | 83 | * | | |This field defines the number of R2R idle cycle. |
kadonotakashi | 0:8fdf9a60065b | 84 | * | | |R2R idle cycle = (R2R * EBI_MCLK). |
kadonotakashi | 0:8fdf9a60065b | 85 | * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. |
kadonotakashi | 0:8fdf9a60065b | 86 | */ |
kadonotakashi | 0:8fdf9a60065b | 87 | __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 88 | __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 89 | __I uint32_t RESERVE0[2]; |
kadonotakashi | 0:8fdf9a60065b | 90 | __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 91 | __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 92 | __I uint32_t RESERVE1[2]; |
kadonotakashi | 0:8fdf9a60065b | 93 | __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 94 | __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 95 | |
kadonotakashi | 0:8fdf9a60065b | 96 | } EBI_T; |
kadonotakashi | 0:8fdf9a60065b | 97 | |
kadonotakashi | 0:8fdf9a60065b | 98 | /** |
kadonotakashi | 0:8fdf9a60065b | 99 | @addtogroup EBI_CONST EBI Bit Field Definition |
kadonotakashi | 0:8fdf9a60065b | 100 | Constant Definitions for EBI Controller |
kadonotakashi | 0:8fdf9a60065b | 101 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 102 | |
kadonotakashi | 0:8fdf9a60065b | 103 | #define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 104 | #define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 105 | |
kadonotakashi | 0:8fdf9a60065b | 106 | #define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */ |
kadonotakashi | 0:8fdf9a60065b | 107 | #define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 108 | |
kadonotakashi | 0:8fdf9a60065b | 109 | #define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */ |
kadonotakashi | 0:8fdf9a60065b | 110 | #define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 111 | |
kadonotakashi | 0:8fdf9a60065b | 112 | #define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 113 | #define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 114 | |
kadonotakashi | 0:8fdf9a60065b | 115 | #define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */ |
kadonotakashi | 0:8fdf9a60065b | 116 | #define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 117 | |
kadonotakashi | 0:8fdf9a60065b | 118 | #define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 119 | #define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 120 | |
kadonotakashi | 0:8fdf9a60065b | 121 | #define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */ |
kadonotakashi | 0:8fdf9a60065b | 122 | #define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 123 | |
kadonotakashi | 0:8fdf9a60065b | 124 | #define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */ |
kadonotakashi | 0:8fdf9a60065b | 125 | #define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 126 | |
kadonotakashi | 0:8fdf9a60065b | 127 | #define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */ |
kadonotakashi | 0:8fdf9a60065b | 128 | #define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 129 | |
kadonotakashi | 0:8fdf9a60065b | 130 | #define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */ |
kadonotakashi | 0:8fdf9a60065b | 131 | #define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */ |
kadonotakashi | 0:8fdf9a60065b | 132 | |
kadonotakashi | 0:8fdf9a60065b | 133 | #define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */ |
kadonotakashi | 0:8fdf9a60065b | 134 | #define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 135 | |
kadonotakashi | 0:8fdf9a60065b | 136 | #define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */ |
kadonotakashi | 0:8fdf9a60065b | 137 | #define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 138 | |
kadonotakashi | 0:8fdf9a60065b | 139 | #define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */ |
kadonotakashi | 0:8fdf9a60065b | 140 | #define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */ |
kadonotakashi | 0:8fdf9a60065b | 141 | |
kadonotakashi | 0:8fdf9a60065b | 142 | /**@}*/ /* EBI_CONST */ |
kadonotakashi | 0:8fdf9a60065b | 143 | /**@}*/ /* end of EBI register group */ |
kadonotakashi | 0:8fdf9a60065b | 144 | |
kadonotakashi | 0:8fdf9a60065b | 145 | |
kadonotakashi | 0:8fdf9a60065b | 146 | #endif /* __EBI_REG_H__ */ |