Nucleo446_SSD1331 - Color Oled(SSD1331) connect to STMicroelectronics…

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takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/eadc_reg.h@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:: kadonotakashi
Date:: Thu Oct 11 02:27:46 2018 +0000
Revision:: 3:f3764f852aa8
Parent:: 0:8fdf9a60065b

Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

User	Revision	Line number	New contents of line
kadonotakashi	0:8fdf9a60065b	1	/************************************************************************//
kadonotakashi	0:8fdf9a60065b	2	* @file eadc_reg.h
kadonotakashi	0:8fdf9a60065b	3	* @version V1.00
kadonotakashi	0:8fdf9a60065b	4	* @brief EADC register definition header file
kadonotakashi	0:8fdf9a60065b	5	*
kadonotakashi	0:8fdf9a60065b	6	* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
kadonotakashi	0:8fdf9a60065b	7	*****************************************************************************/
kadonotakashi	0:8fdf9a60065b	8	#ifndef __EADC_REG_H__
kadonotakashi	0:8fdf9a60065b	9	#define __EADC_REG_H__
kadonotakashi	0:8fdf9a60065b	10
kadonotakashi	0:8fdf9a60065b	11	/---------------------- Enhanced Analog to Digital Converter -------------------------/
kadonotakashi	0:8fdf9a60065b	12	/**
kadonotakashi	0:8fdf9a60065b	13	@addtogroup EADC Enhanced Analog to Digital Converter(EADC)
kadonotakashi	0:8fdf9a60065b	14	Memory Mapped Structure for EADC Controller
kadonotakashi	0:8fdf9a60065b	15	@{ */
kadonotakashi	0:8fdf9a60065b	16
kadonotakashi	0:8fdf9a60065b	17
kadonotakashi	0:8fdf9a60065b	18	typedef struct
kadonotakashi	0:8fdf9a60065b	19	{
kadonotakashi	0:8fdf9a60065b	20
kadonotakashi	0:8fdf9a60065b	21
kadonotakashi	0:8fdf9a60065b	22	/**
kadonotakashi	0:8fdf9a60065b	23	* @var EADC_T::DAT[19]
kadonotakashi	0:8fdf9a60065b	24	* Offset: 0x00 ADC Data Register 0~18 for Sample Module 0~18
kadonotakashi	0:8fdf9a60065b	25	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	26	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	27	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	28	* \|[15:0] \|RESULT \|ADC Conversion Result
kadonotakashi	0:8fdf9a60065b	29	* \| \| \|This field contains 12 bits conversion result.
kadonotakashi	0:8fdf9a60065b	30	* \| \| \|When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
kadonotakashi	0:8fdf9a60065b	31	* \| \| \|When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
kadonotakashi	0:8fdf9a60065b	32	* \|[16] \|OV \|Overrun Flag
kadonotakashi	0:8fdf9a60065b	33	* \| \| \|If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
kadonotakashi	0:8fdf9a60065b	34	* \| \| \|0 = Data in RESULT[11:0] is recent conversion result.
kadonotakashi	0:8fdf9a60065b	35	* \| \| \|1 = Data in RESULT[11:0] is overwrite.
kadonotakashi	0:8fdf9a60065b	36	* \| \| \|Note: It is cleared by hardware after EADC_DAT register is read.
kadonotakashi	0:8fdf9a60065b	37	* \|[17] \|VALID \|Valid Flag
kadonotakashi	0:8fdf9a60065b	38	* \| \| \|This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
kadonotakashi	0:8fdf9a60065b	39	* \| \| \|0 = Data in RESULT[11:0] bits is not valid.
kadonotakashi	0:8fdf9a60065b	40	* \| \| \|1 = Data in RESULT[11:0] bits is valid.
kadonotakashi	0:8fdf9a60065b	41	* @var EADC_T::CURDAT
kadonotakashi	0:8fdf9a60065b	42	* Offset: 0x4C ADC PDMA Current Transfer Data Register
kadonotakashi	0:8fdf9a60065b	43	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	44	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	45	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	46	* \|[17:0] \|CURDAT \|ADC PDMA Current Transfer Data Register
kadonotakashi	0:8fdf9a60065b	47	* \| \| \|This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
kadonotakashi	0:8fdf9a60065b	48	* \| \| \|This is a read only register.
kadonotakashi	0:8fdf9a60065b	49	* @var EADC_T::CTL
kadonotakashi	0:8fdf9a60065b	50	* Offset: 0x50 ADC Control Register
kadonotakashi	0:8fdf9a60065b	51	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	52	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	53	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	54	* \|[0] \|ADCEN \|ADC Converter Enable Bit
kadonotakashi	0:8fdf9a60065b	55	* \| \| \|0 = Disabled EADC.
kadonotakashi	0:8fdf9a60065b	56	* \| \| \|1 = Enabled EADC.
kadonotakashi	0:8fdf9a60065b	57	* \| \| \|Note: Before starting ADC conversion function, this bit should be set to 1
kadonotakashi	0:8fdf9a60065b	58	* \| \| \|Clear it to 0 to disable ADC converter analog circuit power consumption.
kadonotakashi	0:8fdf9a60065b	59	* \|[1] \|ADCRST \|ADC Converter Control Circuits Reset
kadonotakashi	0:8fdf9a60065b	60	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	61	* \| \| \|1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
kadonotakashi	0:8fdf9a60065b	62	* \| \| \|Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
kadonotakashi	0:8fdf9a60065b	63	* \|[2] \|ADCIEN0 \|Specific Sample Module ADC ADINT0 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	64	* \| \| \|The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion
kadonotakashi	0:8fdf9a60065b	65	* \| \| \|If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
kadonotakashi	0:8fdf9a60065b	66	* \| \| \|0 = Specific sample module ADC ADINT0 interrupt function Disabled.
kadonotakashi	0:8fdf9a60065b	67	* \| \| \|1 = Specific sample module ADC ADINT0 interrupt function Enabled.
kadonotakashi	0:8fdf9a60065b	68	* \|[3] \|ADCIEN1 \|Specific Sample Module ADC ADINT1 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	69	* \| \| \|The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion
kadonotakashi	0:8fdf9a60065b	70	* \| \| \|If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
kadonotakashi	0:8fdf9a60065b	71	* \| \| \|0 = Specific sample module ADC ADINT1 interrupt function Disabled.
kadonotakashi	0:8fdf9a60065b	72	* \| \| \|1 = Specific sample module ADC ADINT1 interrupt function Enabled.
kadonotakashi	0:8fdf9a60065b	73	* \|[4] \|ADCIEN2 \|Specific Sample Module ADC ADINT2 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	74	* \| \| \|The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion
kadonotakashi	0:8fdf9a60065b	75	* \| \| \|If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
kadonotakashi	0:8fdf9a60065b	76	* \| \| \|0 = Specific sample module ADC ADINT2 interrupt function Disabled.
kadonotakashi	0:8fdf9a60065b	77	* \| \| \|1 = Specific sample module ADC ADINT2 interrupt function Enabled.
kadonotakashi	0:8fdf9a60065b	78	* \|[5] \|ADCIEN3 \|Specific Sample Module ADC ADINT3 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	79	* \| \| \|The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion
kadonotakashi	0:8fdf9a60065b	80	* \| \| \|If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
kadonotakashi	0:8fdf9a60065b	81	* \| \| \|0 = Specific sample module ADC ADINT3 interrupt function Disabled.
kadonotakashi	0:8fdf9a60065b	82	* \| \| \|1 = Specific sample module ADC ADINT3 interrupt function Enabled.
kadonotakashi	0:8fdf9a60065b	83	* \|[7:6] \|RESSEL \|Resolution Selection
kadonotakashi	0:8fdf9a60065b	84	* \| \| \|00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]).
kadonotakashi	0:8fdf9a60065b	85	* \| \| \|01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]).
kadonotakashi	0:8fdf9a60065b	86	* \| \| \|10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]).
kadonotakashi	0:8fdf9a60065b	87	* \| \| \|11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]).
kadonotakashi	0:8fdf9a60065b	88	* \|[8] \|DIFFEN \|Differential Analog Input Mode Enable Bit
kadonotakashi	0:8fdf9a60065b	89	* \| \| \|0 = Single-end analog input mode.
kadonotakashi	0:8fdf9a60065b	90	* \| \| \|1 = Differential analog input mode.
kadonotakashi	0:8fdf9a60065b	91	* \|[9] \|DMOF \|ADC Differential Input Mode Output Format
kadonotakashi	0:8fdf9a60065b	92	* \| \| \|0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
kadonotakashi	0:8fdf9a60065b	93	* \| \| \|1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
kadonotakashi	0:8fdf9a60065b	94	* \|[11] \|PDMAEN \|PDMA Transfer Enable Bit
kadonotakashi	0:8fdf9a60065b	95	* \| \| \|When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
kadonotakashi	0:8fdf9a60065b	96	* \| \| \|0 = PDMA data transfer Disabled.
kadonotakashi	0:8fdf9a60065b	97	* \| \| \|1 = PDMA data transfer Enabled.
kadonotakashi	0:8fdf9a60065b	98	* \| \| \|Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
kadonotakashi	0:8fdf9a60065b	99	* @var EADC_T::SWTRG
kadonotakashi	0:8fdf9a60065b	100	* Offset: 0x54 ADC Sample Module Software Start Register
kadonotakashi	0:8fdf9a60065b	101	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	102	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	103	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	104	* \|[18:0] \|SWTRG \|ADC Sample Module 0~18 Software Force to Start ADC Conversion
kadonotakashi	0:8fdf9a60065b	105	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	106	* \| \| \|1 = Cause an ADC conversion when the priority is given to sample module.
kadonotakashi	0:8fdf9a60065b	107	* \| \| \|Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion
kadonotakashi	0:8fdf9a60065b	108	* \| \| \|If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
kadonotakashi	0:8fdf9a60065b	109	* @var EADC_T::PENDSTS
kadonotakashi	0:8fdf9a60065b	110	* Offset: 0x58 ADC Start of Conversion Pending Flag Register
kadonotakashi	0:8fdf9a60065b	111	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	112	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	113	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	114	* \|[18:0] \|STPF \|ADC Sample Module 0~18 Start of Conversion Pending Flag
kadonotakashi	0:8fdf9a60065b	115	* \| \| \|Read:
kadonotakashi	0:8fdf9a60065b	116	* \| \| \|0 = There is no pending conversion for sample module.
kadonotakashi	0:8fdf9a60065b	117	* \| \| \|1 = Sample module ADC start of conversion is pending.
kadonotakashi	0:8fdf9a60065b	118	* \| \| \|Write:
kadonotakashi	0:8fdf9a60065b	119	* \| \| \|1 = clear pending flag and cancel the conversion for sample module.
kadonotakashi	0:8fdf9a60065b	120	* \| \| \|Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0
kadonotakashi	0:8fdf9a60065b	121	* @var EADC_T::OVSTS
kadonotakashi	0:8fdf9a60065b	122	* Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register
kadonotakashi	0:8fdf9a60065b	123	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	124	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	125	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	126	* \|[18:0] \|SPOVF \|ADC SAMPLE0~18 Overrun Flag
kadonotakashi	0:8fdf9a60065b	127	* \| \| \|0 = No sample module event overrun.
kadonotakashi	0:8fdf9a60065b	128	* \| \| \|1 = Indicates a new sample module event is generated while an old one event is pending.
kadonotakashi	0:8fdf9a60065b	129	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	130	* @var EADC_T::SCTL[19]
kadonotakashi	0:8fdf9a60065b	131	* Offset: 0x80 ADC Sample Module 0~18 Control Register
kadonotakashi	0:8fdf9a60065b	132	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	133	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	134	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	135	* \|[3:0] \|CHSEL \|ADC Sample Module Channel Selection
kadonotakashi	0:8fdf9a60065b	136	* \| \| \|00H = EADC_CH0 (slow channel).
kadonotakashi	0:8fdf9a60065b	137	* \| \| \|01H = EADC_CH1 (slow channel).
kadonotakashi	0:8fdf9a60065b	138	* \| \| \|02H = EADC_CH2 (slow channel).
kadonotakashi	0:8fdf9a60065b	139	* \| \| \|03H = EADC_CH3 (slow channel).
kadonotakashi	0:8fdf9a60065b	140	* \| \| \|04H = EADC_CH4 (slow channel).
kadonotakashi	0:8fdf9a60065b	141	* \| \| \|05H = EADC_CH5 (slow channel).
kadonotakashi	0:8fdf9a60065b	142	* \| \| \|06H = EADC_CH6 (slow channel).
kadonotakashi	0:8fdf9a60065b	143	* \| \| \|07H = EADC_CH7 (slow channel).
kadonotakashi	0:8fdf9a60065b	144	* \| \| \|08H = EADC_CH8 (slow channel).
kadonotakashi	0:8fdf9a60065b	145	* \| \| \|09H = EADC_CH9 (slow channel).
kadonotakashi	0:8fdf9a60065b	146	* \| \| \|0AH = EADC_CH10 (fast channel).
kadonotakashi	0:8fdf9a60065b	147	* \| \| \|0BH = EADC_CH11 (fast channel).
kadonotakashi	0:8fdf9a60065b	148	* \| \| \|0CH = EADC_CH12 (fast channel).
kadonotakashi	0:8fdf9a60065b	149	* \| \| \|0DH = EADC_CH13 (fast channel).
kadonotakashi	0:8fdf9a60065b	150	* \| \| \|0EH = EADC_CH14 (fast channel).
kadonotakashi	0:8fdf9a60065b	151	* \| \| \|0FH = EADC_CH15 (fast channel).
kadonotakashi	0:8fdf9a60065b	152	* \|[4] \|EXTREN \|ADC External Trigger Rising Edge Enable Bit
kadonotakashi	0:8fdf9a60065b	153	* \| \| \|0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source.
kadonotakashi	0:8fdf9a60065b	154	* \| \| \|1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source.
kadonotakashi	0:8fdf9a60065b	155	* \|[5] \|EXTFEN \|ADC External Trigger Falling Edge Enable Bit
kadonotakashi	0:8fdf9a60065b	156	* \| \| \|0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source.
kadonotakashi	0:8fdf9a60065b	157	* \| \| \|1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source.
kadonotakashi	0:8fdf9a60065b	158	* \|[7:6] \|TRGDLYDIV \|ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection
kadonotakashi	0:8fdf9a60065b	159	* \| \| \|Trigger delay clock frequency:
kadonotakashi	0:8fdf9a60065b	160	* \| \| \|00 = ADC_CLK/1.
kadonotakashi	0:8fdf9a60065b	161	* \| \| \|01 = ADC_CLK/2.
kadonotakashi	0:8fdf9a60065b	162	* \| \| \|10 = ADC_CLK/4.
kadonotakashi	0:8fdf9a60065b	163	* \| \| \|11 = ADC_CLK/16.
kadonotakashi	0:8fdf9a60065b	164	* \|[15:8] \|TRGDLYCNT \|ADC Sample Module Start of Conversion Trigger Delay Time
kadonotakashi	0:8fdf9a60065b	165	* \| \| \|Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
kadonotakashi	0:8fdf9a60065b	166	* \|[20:16] \|TRGSEL \|ADC Sample Module Start of Conversion Trigger Source Selection
kadonotakashi	0:8fdf9a60065b	167	* \| \| \|0H = Disable trigger.
kadonotakashi	0:8fdf9a60065b	168	* \| \| \|1H = External trigger from EADC0_ST pin input.
kadonotakashi	0:8fdf9a60065b	169	* \| \| \|2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
kadonotakashi	0:8fdf9a60065b	170	* \| \| \|3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
kadonotakashi	0:8fdf9a60065b	171	* \| \| \|4H = Timer0 overflow pulse trigger.
kadonotakashi	0:8fdf9a60065b	172	* \| \| \|5H = Timer1 overflow pulse trigger.
kadonotakashi	0:8fdf9a60065b	173	* \| \| \|6H = Timer2 overflow pulse trigger.
kadonotakashi	0:8fdf9a60065b	174	* \| \| \|7H = Timer3 overflow pulse trigger.
kadonotakashi	0:8fdf9a60065b	175	* \| \| \|8H = EPWM0TG0.
kadonotakashi	0:8fdf9a60065b	176	* \| \| \|9H = EPWM0TG1.
kadonotakashi	0:8fdf9a60065b	177	* \| \| \|AH = EPWM0TG2.
kadonotakashi	0:8fdf9a60065b	178	* \| \| \|BH = EPWM0TG3.
kadonotakashi	0:8fdf9a60065b	179	* \| \| \|CH = EPWM0TG4.
kadonotakashi	0:8fdf9a60065b	180	* \| \| \|DH = EPWM0TG5.
kadonotakashi	0:8fdf9a60065b	181	* \| \| \|EH = EPWM1TG0.
kadonotakashi	0:8fdf9a60065b	182	* \| \| \|FH = EPWM1TG1.
kadonotakashi	0:8fdf9a60065b	183	* \| \| \|10H = EPWM1TG2.
kadonotakashi	0:8fdf9a60065b	184	* \| \| \|11H = EPWM1TG3.
kadonotakashi	0:8fdf9a60065b	185	* \| \| \|12H = EPWM1TG4.
kadonotakashi	0:8fdf9a60065b	186	* \| \| \|13H = EPWM1TG5.
kadonotakashi	0:8fdf9a60065b	187	* \| \| \|14H = BPWM0TG.
kadonotakashi	0:8fdf9a60065b	188	* \| \| \|15H = BPWM1TG.
kadonotakashi	0:8fdf9a60065b	189	* \| \| \|other = Reserved.
kadonotakashi	0:8fdf9a60065b	190	* \|[22] \|INTPOS \|Interrupt Flag Position Select
kadonotakashi	0:8fdf9a60065b	191	* \| \| \|0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion.
kadonotakashi	0:8fdf9a60065b	192	* \| \| \|1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion.
kadonotakashi	0:8fdf9a60065b	193	* \|[23] \|DBMEN \|Double Buffer Mode Enable Bit
kadonotakashi	0:8fdf9a60065b	194	* \| \| \|0 = Sample has one sample result register. (default).
kadonotakashi	0:8fdf9a60065b	195	* \| \| \|1 = Sample has two sample result registers.
kadonotakashi	0:8fdf9a60065b	196	* \|[31:24] \|EXTSMPT \|ADC Sampling Time Extend
kadonotakashi	0:8fdf9a60065b	197	* \| \| \|When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.
kadonotakashi	0:8fdf9a60065b	198	* \| \| \|The range of start delay time is from 0~255 ADC clock.
kadonotakashi	0:8fdf9a60065b	199	* @var EADC_T::INTSRC[4]
kadonotakashi	0:8fdf9a60065b	200	* Offset: 0xD0 ADC interrupt 0~3 Source Enable Control Register.
kadonotakashi	0:8fdf9a60065b	201	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	202	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	203	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	204	* \|[0] \|SPLIE0 \|Sample Module 0 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	205	* \| \| \|0 = Sample Module 0 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	206	* \| \| \|1 = Sample Module 0 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	207	* \|[1] \|SPLIE1 \|Sample Module 1 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	208	* \| \| \|0 = Sample Module 1 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	209	* \| \| \|1 = Sample Module 1 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	210	* \|[2] \|SPLIE2 \|Sample Module 2 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	211	* \| \| \|0 = Sample Module 2 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	212	* \| \| \|1 = Sample Module 2 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	213	* \|[3] \|SPLIE3 \|Sample Module 3 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	214	* \| \| \|0 = Sample Module 3 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	215	* \| \| \|1 = Sample Module 3 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	216	* \|[4] \|SPLIE4 \|Sample Module 4 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	217	* \| \| \|0 = Sample Module 4 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	218	* \| \| \|1 = Sample Module 4 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	219	* \|[5] \|SPLIE5 \|Sample Module 5 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	220	* \| \| \|0 = Sample Module 5 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	221	* \| \| \|1 = Sample Module 5 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	222	* \|[6] \|SPLIE6 \|Sample Module 6 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	223	* \| \| \|0 = Sample Module 6 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	224	* \| \| \|1 = Sample Module 6 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	225	* \|[7] \|SPLIE7 \|Sample Module 7 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	226	* \| \| \|0 = Sample Module 7 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	227	* \| \| \|1 = Sample Module 7 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	228	* \|[8] \|SPLIE8 \|Sample Module 8 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	229	* \| \| \|0 = Sample Module 8 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	230	* \| \| \|1 = Sample Module 8 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	231	* \|[9] \|SPLIE9 \|Sample Module 9 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	232	* \| \| \|0 = Sample Module 9 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	233	* \| \| \|1 = Sample Module 9 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	234	* \|[10] \|SPLIE10 \|Sample Module 10 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	235	* \| \| \|0 = Sample Module 10 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	236	* \| \| \|1 = Sample Module 10 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	237	* \|[11] \|SPLIE11 \|Sample Module 11 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	238	* \| \| \|0 = Sample Module 11 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	239	* \| \| \|1 = Sample Module 11 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	240	* \|[12] \|SPLIE12 \|Sample Module 12 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	241	* \| \| \|0 = Sample Module 12 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	242	* \| \| \|1 = Sample Module 12 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	243	* \|[13] \|SPLIE13 \|Sample Module 13 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	244	* \| \| \|0 = Sample Module 13 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	245	* \| \| \|1 = Sample Module 13 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	246	* \|[14] \|SPLIE14 \|Sample Module 14 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	247	* \| \| \|0 = Sample Module 14 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	248	* \| \| \|1 = Sample Module 14 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	249	* \|[15] \|SPLIE15 \|Sample Module 15 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	250	* \| \| \|0 = Sample Module 15 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	251	* \| \| \|1 = Sample Module 15 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	252	* \|[16] \|SPLIE16 \|Sample Module 16 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	253	* \| \| \|0 = Sample Module 16 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	254	* \| \| \|1 = Sample Module 16 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	255	* \|[17] \|SPLIE17 \|Sample Module 17 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	256	* \| \| \|0 = Sample Module 17 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	257	* \| \| \|1 = Sample Module 17 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	258	* \|[18] \|SPLIE18 \|Sample Module 18 Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	259	* \| \| \|0 = Sample Module 18 interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	260	* \| \| \|1 = Sample Module 18 interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	261	* @var EADC_T::CMP[4]
kadonotakashi	0:8fdf9a60065b	262	* Offset: 0xE0 ADC Result Compare Register 0~3
kadonotakashi	0:8fdf9a60065b	263	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	264	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	265	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	266	* \|[0] \|ADCMPEN \|ADC Result Compare Enable Bit
kadonotakashi	0:8fdf9a60065b	267	* \| \| \|0 = Compare Disabled.
kadonotakashi	0:8fdf9a60065b	268	* \| \| \|1 = Compare Enabled.
kadonotakashi	0:8fdf9a60065b	269	* \| \| \|Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
kadonotakashi	0:8fdf9a60065b	270	* \|[1] \|ADCMPIE \|ADC Result Compare Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	271	* \| \| \|0 = Compare function interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	272	* \| \| \|1 = Compare function interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	273	* \| \| \|If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
kadonotakashi	0:8fdf9a60065b	274	* \|[2] \|CMPCOND \|Compare Condition
kadonotakashi	0:8fdf9a60065b	275	* \| \| \|0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
kadonotakashi	0:8fdf9a60065b	276	* \| \| \|1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
kadonotakashi	0:8fdf9a60065b	277	* \| \| \|Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
kadonotakashi	0:8fdf9a60065b	278	* \|[7:3] \|CMPSPL \|Compare Sample Module Selection
kadonotakashi	0:8fdf9a60065b	279	* \| \| \|00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	280	* \| \| \|00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	281	* \| \| \|00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	282	* \| \| \|00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	283	* \| \| \|00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	284	* \| \| \|00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	285	* \| \| \|00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	286	* \| \| \|00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	287	* \| \| \|01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	288	* \| \| \|01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	289	* \| \| \|01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	290	* \| \| \|01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	291	* \| \| \|01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	292	* \| \| \|01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	293	* \| \| \|01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	294	* \| \| \|01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	295	* \| \| \|10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	296	* \| \| \|10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	297	* \| \| \|10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
kadonotakashi	0:8fdf9a60065b	298	* \|[11:8] \|CMPMCNT \|Compare Match Count
kadonotakashi	0:8fdf9a60065b	299	* \| \| \|When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1
kadonotakashi	0:8fdf9a60065b	300	* \| \| \|If the compare result does not meet the compare condition, the internal compare match counter will reset to 0
kadonotakashi	0:8fdf9a60065b	301	* \| \| \|When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
kadonotakashi	0:8fdf9a60065b	302	* \|[15] \|CMPWEN \|Compare Window Mode Enable Bit
kadonotakashi	0:8fdf9a60065b	303	* \| \| \|0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched
kadonotakashi	0:8fdf9a60065b	304	* \| \| \|ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched
kadonotakashi	0:8fdf9a60065b	305	* \| \| \|1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched
kadonotakashi	0:8fdf9a60065b	306	* \| \| \|ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
kadonotakashi	0:8fdf9a60065b	307	* \| \| \|Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
kadonotakashi	0:8fdf9a60065b	308	* \|[27:16] \|CMPDAT \|Comparison Data
kadonotakashi	0:8fdf9a60065b	309	* \| \| \|The 12 bits data is used to compare with conversion result of specified sample module
kadonotakashi	0:8fdf9a60065b	310	* \| \| \|User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
kadonotakashi	0:8fdf9a60065b	311	* @var EADC_T::STATUS0
kadonotakashi	0:8fdf9a60065b	312	* Offset: 0xF0 ADC Status Register 0
kadonotakashi	0:8fdf9a60065b	313	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	314	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	315	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	316	* \|[15:0] \|VALID \|EADC_DAT0~15 Data Valid Flag
kadonotakashi	0:8fdf9a60065b	317	* \| \| \|It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).
kadonotakashi	0:8fdf9a60065b	318	* \|[31:16] \|OV \|EADC_DAT0~15 Overrun Flag
kadonotakashi	0:8fdf9a60065b	319	* \| \| \|It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).
kadonotakashi	0:8fdf9a60065b	320	* @var EADC_T::STATUS1
kadonotakashi	0:8fdf9a60065b	321	* Offset: 0xF4 ADC Status Register 1
kadonotakashi	0:8fdf9a60065b	322	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	323	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	324	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	325	* \|[2:0] \|VALID \|EADC_DAT16~18 Data Valid Flag
kadonotakashi	0:8fdf9a60065b	326	* \| \| \|It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).
kadonotakashi	0:8fdf9a60065b	327	* \|[18:16] \|OV \|EADC_DAT16~18 Overrun Flag
kadonotakashi	0:8fdf9a60065b	328	* \| \| \|It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).
kadonotakashi	0:8fdf9a60065b	329	* @var EADC_T::STATUS2
kadonotakashi	0:8fdf9a60065b	330	* Offset: 0xF8 ADC Status Register 2
kadonotakashi	0:8fdf9a60065b	331	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	332	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	333	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	334	* \|[0] \|ADIF0 \|ADC ADINT0 Interrupt Flag
kadonotakashi	0:8fdf9a60065b	335	* \| \| \|0 = No ADINT0 interrupt pulse received.
kadonotakashi	0:8fdf9a60065b	336	* \| \| \|1 = ADINT0 interrupt pulse has been received.
kadonotakashi	0:8fdf9a60065b	337	* \| \| \|Note1: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	338	* \| \| \|Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
kadonotakashi	0:8fdf9a60065b	339	* \|[1] \|ADIF1 \|ADC ADINT1 Interrupt Flag
kadonotakashi	0:8fdf9a60065b	340	* \| \| \|0 = No ADINT1 interrupt pulse received.
kadonotakashi	0:8fdf9a60065b	341	* \| \| \|1 = ADINT1 interrupt pulse has been received.
kadonotakashi	0:8fdf9a60065b	342	* \| \| \|Note1: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	343	* \| \| \|Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
kadonotakashi	0:8fdf9a60065b	344	* \|[2] \|ADIF2 \|ADC ADINT2 Interrupt Flag
kadonotakashi	0:8fdf9a60065b	345	* \| \| \|0 = No ADINT2 interrupt pulse received.
kadonotakashi	0:8fdf9a60065b	346	* \| \| \|1 = ADINT2 interrupt pulse has been received.
kadonotakashi	0:8fdf9a60065b	347	* \| \| \|Note1: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	348	* \| \| \|Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
kadonotakashi	0:8fdf9a60065b	349	* \|[3] \|ADIF3 \|ADC ADINT3 Interrupt Flag
kadonotakashi	0:8fdf9a60065b	350	* \| \| \|0 = No ADINT3 interrupt pulse received.
kadonotakashi	0:8fdf9a60065b	351	* \| \| \|1 = ADINT3 interrupt pulse has been received.
kadonotakashi	0:8fdf9a60065b	352	* \| \| \|Note1: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	353	* \| \| \|Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
kadonotakashi	0:8fdf9a60065b	354	* \|[4] \|ADCMPF0 \|ADC Compare 0 Flag
kadonotakashi	0:8fdf9a60065b	355	* \| \| \|When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
kadonotakashi	0:8fdf9a60065b	356	* \| \| \|0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
kadonotakashi	0:8fdf9a60065b	357	* \| \| \|1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
kadonotakashi	0:8fdf9a60065b	358	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	359	* \|[5] \|ADCMPF1 \|ADC Compare 1 Flag
kadonotakashi	0:8fdf9a60065b	360	* \| \| \|When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
kadonotakashi	0:8fdf9a60065b	361	* \| \| \|0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
kadonotakashi	0:8fdf9a60065b	362	* \| \| \|1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
kadonotakashi	0:8fdf9a60065b	363	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	364	* \|[6] \|ADCMPF2 \|ADC Compare 2 Flag
kadonotakashi	0:8fdf9a60065b	365	* \| \| \|When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
kadonotakashi	0:8fdf9a60065b	366	* \| \| \|0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
kadonotakashi	0:8fdf9a60065b	367	* \| \| \|1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
kadonotakashi	0:8fdf9a60065b	368	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	369	* \|[7] \|ADCMPF3 \|ADC Compare 3 Flag
kadonotakashi	0:8fdf9a60065b	370	* \| \| \|When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
kadonotakashi	0:8fdf9a60065b	371	* \| \| \|0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
kadonotakashi	0:8fdf9a60065b	372	* \| \| \|1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
kadonotakashi	0:8fdf9a60065b	373	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	374	* \|[8] \|ADOVIF0 \|ADC ADINT0 Interrupt Flag Overrun
kadonotakashi	0:8fdf9a60065b	375	* \| \| \|0 = ADINT0 interrupt flag is not overwritten to 1.
kadonotakashi	0:8fdf9a60065b	376	* \| \| \|1 = ADINT0 interrupt flag is overwritten to 1.
kadonotakashi	0:8fdf9a60065b	377	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	378	* \|[9] \|ADOVIF1 \|ADC ADINT1 Interrupt Flag Overrun
kadonotakashi	0:8fdf9a60065b	379	* \| \| \|0 = ADINT1 interrupt flag is not overwritten to 1.
kadonotakashi	0:8fdf9a60065b	380	* \| \| \|1 = ADINT1 interrupt flag is overwritten to 1.
kadonotakashi	0:8fdf9a60065b	381	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	382	* \|[10] \|ADOVIF2 \|ADC ADINT2 Interrupt Flag Overrun
kadonotakashi	0:8fdf9a60065b	383	* \| \| \|0 = ADINT2 interrupt flag is not overwritten to 1.
kadonotakashi	0:8fdf9a60065b	384	* \| \| \|1 = ADINT2 interrupt flag is s overwritten to 1.
kadonotakashi	0:8fdf9a60065b	385	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	386	* \|[11] \|ADOVIF3 \|ADC ADINT3 Interrupt Flag Overrun
kadonotakashi	0:8fdf9a60065b	387	* \| \| \|0 = ADINT3 interrupt flag is not overwritten to 1.
kadonotakashi	0:8fdf9a60065b	388	* \| \| \|1 = ADINT3 interrupt flag is overwritten to 1.
kadonotakashi	0:8fdf9a60065b	389	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	390	* \|[12] \|ADCMPO0 \|ADC Compare 0 Output Status (Read Only)
kadonotakashi	0:8fdf9a60065b	391	* \| \| \|The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module.
kadonotakashi	0:8fdf9a60065b	392	* \| \| \|User can use it to monitor the external analog input pin voltage status.
kadonotakashi	0:8fdf9a60065b	393	* \| \| \|0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
kadonotakashi	0:8fdf9a60065b	394	* \| \| \|1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting.
kadonotakashi	0:8fdf9a60065b	395	* \|[13] \|ADCMPO1 \|ADC Compare 1 Output Status (Read Only)
kadonotakashi	0:8fdf9a60065b	396	* \| \| \|The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module.
kadonotakashi	0:8fdf9a60065b	397	* \| \| \|User can use it to monitor the external analog input pin voltage status.
kadonotakashi	0:8fdf9a60065b	398	* \| \| \|0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
kadonotakashi	0:8fdf9a60065b	399	* \| \| \|1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting.
kadonotakashi	0:8fdf9a60065b	400	* \|[14] \|ADCMPO2 \|ADC Compare 2 Output Status (Read Only)
kadonotakashi	0:8fdf9a60065b	401	* \| \| \|The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module.
kadonotakashi	0:8fdf9a60065b	402	* \| \| \|User can use it to monitor the external analog input pin voltage status.
kadonotakashi	0:8fdf9a60065b	403	* \| \| \|0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
kadonotakashi	0:8fdf9a60065b	404	* \| \| \|1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting.
kadonotakashi	0:8fdf9a60065b	405	* \|[15] \|ADCMPO3 \|ADC Compare 3 Output Status (Read Only)
kadonotakashi	0:8fdf9a60065b	406	* \| \| \|The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module.
kadonotakashi	0:8fdf9a60065b	407	* \| \| \|User can use it to monitor the external analog input pin voltage status.
kadonotakashi	0:8fdf9a60065b	408	* \| \| \|0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
kadonotakashi	0:8fdf9a60065b	409	* \| \| \|1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting.
kadonotakashi	0:8fdf9a60065b	410	* \|[20:16] \|CHANNEL \|Current Conversion Channel (Read Only)
kadonotakashi	0:8fdf9a60065b	411	* \| \| \|This filed reflects ADC current conversion channel when BUSY=1.
kadonotakashi	0:8fdf9a60065b	412	* \| \| \|It is read only.
kadonotakashi	0:8fdf9a60065b	413	* \| \| \|00H = EADC_CH0.
kadonotakashi	0:8fdf9a60065b	414	* \| \| \|01H = EADC_CH1.
kadonotakashi	0:8fdf9a60065b	415	* \| \| \|02H = EADC_CH2.
kadonotakashi	0:8fdf9a60065b	416	* \| \| \|03H = EADC_CH3.
kadonotakashi	0:8fdf9a60065b	417	* \| \| \|04H = EADC_CH4.
kadonotakashi	0:8fdf9a60065b	418	* \| \| \|05H = EADC_CH5.
kadonotakashi	0:8fdf9a60065b	419	* \| \| \|06H = EADC_CH6.
kadonotakashi	0:8fdf9a60065b	420	* \| \| \|07H = EADC_CH7.
kadonotakashi	0:8fdf9a60065b	421	* \| \| \|08H = EADC_CH8.
kadonotakashi	0:8fdf9a60065b	422	* \| \| \|09H = EADC_CH9.
kadonotakashi	0:8fdf9a60065b	423	* \| \| \|0AH = EADC_CH10.
kadonotakashi	0:8fdf9a60065b	424	* \| \| \|0BH = EADC_CH11.
kadonotakashi	0:8fdf9a60065b	425	* \| \| \|0CH = EADC_CH12.
kadonotakashi	0:8fdf9a60065b	426	* \| \| \|0DH = EADC_CH13.
kadonotakashi	0:8fdf9a60065b	427	* \| \| \|0EH = EADC_CH14.
kadonotakashi	0:8fdf9a60065b	428	* \| \| \|0FH = EADC_CH15.
kadonotakashi	0:8fdf9a60065b	429	* \| \| \|10H = VBG.
kadonotakashi	0:8fdf9a60065b	430	* \| \| \|11H = VTEMP.
kadonotakashi	0:8fdf9a60065b	431	* \| \| \|12H = VBAT/4.
kadonotakashi	0:8fdf9a60065b	432	* \|[23] \|BUSY \|Busy/Idle (Read Only)
kadonotakashi	0:8fdf9a60065b	433	* \| \| \|0 = EADC is in idle state.
kadonotakashi	0:8fdf9a60065b	434	* \| \| \|1 = EADC is busy at conversion.
kadonotakashi	0:8fdf9a60065b	435	* \|[24] \|ADOVIF \|All ADC Interrupt Flag Overrun Bits Check (Read Only)
kadonotakashi	0:8fdf9a60065b	436	* \| \| \|n=0~3.
kadonotakashi	0:8fdf9a60065b	437	* \| \| \|0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
kadonotakashi	0:8fdf9a60065b	438	* \| \| \|1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
kadonotakashi	0:8fdf9a60065b	439	* \| \| \|Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
kadonotakashi	0:8fdf9a60065b	440	* \|[25] \|STOVF \|for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only)
kadonotakashi	0:8fdf9a60065b	441	* \| \| \|n=0~18.
kadonotakashi	0:8fdf9a60065b	442	* \| \| \|0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
kadonotakashi	0:8fdf9a60065b	443	* \| \| \|1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
kadonotakashi	0:8fdf9a60065b	444	* \| \| \|Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
kadonotakashi	0:8fdf9a60065b	445	* \|[26] \|AVALID \|for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)
kadonotakashi	0:8fdf9a60065b	446	* \| \| \|n=0~18.
kadonotakashi	0:8fdf9a60065b	447	* \| \| \|0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
kadonotakashi	0:8fdf9a60065b	448	* \| \| \|1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
kadonotakashi	0:8fdf9a60065b	449	* \| \| \|Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
kadonotakashi	0:8fdf9a60065b	450	* \|[27] \|AOV \|for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only)
kadonotakashi	0:8fdf9a60065b	451	* \| \| \|n=0~18.
kadonotakashi	0:8fdf9a60065b	452	* \| \| \|0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
kadonotakashi	0:8fdf9a60065b	453	* \| \| \|1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
kadonotakashi	0:8fdf9a60065b	454	* \| \| \|Note: This bit will keep 1 when any OVn Flag is equal to 1.
kadonotakashi	0:8fdf9a60065b	455	* @var EADC_T::STATUS3
kadonotakashi	0:8fdf9a60065b	456	* Offset: 0xFC ADC Status Register 3
kadonotakashi	0:8fdf9a60065b	457	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	458	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	459	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	460	* \|[4:0] \|CURSPL \|ADC Current Sample Module
kadonotakashi	0:8fdf9a60065b	461	* \| \| \|This register show the current ADC is controlled by which sample module control logic modules.
kadonotakashi	0:8fdf9a60065b	462	* \| \| \|If the ADC is Idle, this bit filed will set to 0x1F.
kadonotakashi	0:8fdf9a60065b	463	* \| \| \|This is a read only register.
kadonotakashi	0:8fdf9a60065b	464	* @var EADC_T::DDAT
kadonotakashi	0:8fdf9a60065b	465	* Offset: 0x100-0x10C ADC Double Data Register n for Sample Module n, n=0~3
kadonotakashi	0:8fdf9a60065b	466	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	467	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	468	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	469	* \|[15:0] \|RESULT \|ADC Conversion Results
kadonotakashi	0:8fdf9a60065b	470	* \| \| \|This field contains 12 bits conversion results.
kadonotakashi	0:8fdf9a60065b	471	* \| \| \|When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
kadonotakashi	0:8fdf9a60065b	472	* \| \| \|When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
kadonotakashi	0:8fdf9a60065b	473	* \|[16] \|OV \|Overrun Flag
kadonotakashi	0:8fdf9a60065b	474	* \| \| \|0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
kadonotakashi	0:8fdf9a60065b	475	* \| \| \|1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
kadonotakashi	0:8fdf9a60065b	476	* \| \| \|If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
kadonotakashi	0:8fdf9a60065b	477	* \| \| \|It is cleared by hardware after EADC_DDAT register is read.
kadonotakashi	0:8fdf9a60065b	478	* \|[17] \|VALID \|Valid Flag
kadonotakashi	0:8fdf9a60065b	479	* \| \| \|0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
kadonotakashi	0:8fdf9a60065b	480	* \| \| \|1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
kadonotakashi	0:8fdf9a60065b	481	* \| \| \|This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read.
kadonotakashi	0:8fdf9a60065b	482	* \| \| \|(n=0~3).
kadonotakashi	0:8fdf9a60065b	483	* @var EADC_T::PWRM
kadonotakashi	0:8fdf9a60065b	484	* Offset: 0x110 ADC Power Management Register
kadonotakashi	0:8fdf9a60065b	485	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	486	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	487	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	488	* \|[0] \|PWUPRDY \|ADC Power-up Sequence Completed and Ready for Conversion (Read Only)
kadonotakashi	0:8fdf9a60065b	489	* \| \| \|0 = ADC is not ready for conversion may be in power down state or in the progress of power up.
kadonotakashi	0:8fdf9a60065b	490	* \| \| \|1 = ADC is ready for conversion.
kadonotakashi	0:8fdf9a60065b	491	* \|[1] \|PWUCALEN \|Power Up Calibration Function Enable Control
kadonotakashi	0:8fdf9a60065b	492	* \| \| \|0 = Disable the function of calibration at power up.
kadonotakashi	0:8fdf9a60065b	493	* \| \| \|1 = Enable the function of calibration at power up.
kadonotakashi	0:8fdf9a60065b	494	* \| \| \|Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following
kadonotakashi	0:8fdf9a60065b	495	* \| \| \|{PWUCALEN, CALSEL } Description:
kadonotakashi	0:8fdf9a60065b	496	* \| \| \|PWUCALEN is 0 and CALSEL is 0: No need to calibrate.
kadonotakashi	0:8fdf9a60065b	497	* \| \| \|PWUCALEN is 0 and CALSEL is 1: No need to calibrate.
kadonotakashi	0:8fdf9a60065b	498	* \| \| \|PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up.
kadonotakashi	0:8fdf9a60065b	499	* \| \| \|PWUCALEN is 1 and CALSEL is 1: Calibrate when power up.
kadonotakashi	0:8fdf9a60065b	500	* \|[3:2] \|PWDMOD \|ADC Power-down Mode
kadonotakashi	0:8fdf9a60065b	501	* \| \| \|Set this bit fields to select ADC power down mode when system power-down.
kadonotakashi	0:8fdf9a60065b	502	* \| \| \|00 = ADC Deep power down mode.
kadonotakashi	0:8fdf9a60065b	503	* \| \| \|01 = ADC Power down.
kadonotakashi	0:8fdf9a60065b	504	* \| \| \|10 = ADC Standby mode.
kadonotakashi	0:8fdf9a60065b	505	* \| \| \|11 = ADC Deep power down mode.
kadonotakashi	0:8fdf9a60065b	506	* \| \| \|Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up
kadonotakashi	0:8fdf9a60065b	507	* \|[19:8] \|LDOSUT \|ADC Internal LDO Start-up Time
kadonotakashi	0:8fdf9a60065b	508	* \| \| \|Set this bit fields to control LDO start-up time
kadonotakashi	0:8fdf9a60065b	509	* \| \| \|The minimum required LDO start-up time is 20us
kadonotakashi	0:8fdf9a60065b	510	* \| \| \|LDO start-up time = (1/ADC_CLK) x LDOSUT.
kadonotakashi	0:8fdf9a60065b	511	* @var EADC_T::CALCTL
kadonotakashi	0:8fdf9a60065b	512	* Offset: 0x114 ADC Calibration Control Register
kadonotakashi	0:8fdf9a60065b	513	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	514	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	515	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	516	* \|[1] \|CALSTART \|Calibration Functional Block Start
kadonotakashi	0:8fdf9a60065b	517	* \| \| \|0 = Stops calibration functional block.
kadonotakashi	0:8fdf9a60065b	518	* \| \| \|1 = Starts calibration functional block.
kadonotakashi	0:8fdf9a60065b	519	* \| \| \|Note: This bit is set by SW and clear by HW after re-calibration finish
kadonotakashi	0:8fdf9a60065b	520	* \|[2] \|CALDONE \|Calibration Functional Block Complete (Read Only)
kadonotakashi	0:8fdf9a60065b	521	* \| \| \|0 = During a calibration.
kadonotakashi	0:8fdf9a60065b	522	* \| \| \|1 = Calibration is completed.
kadonotakashi	0:8fdf9a60065b	523	* \|[3] \|CALSEL \|Select Calibration Functional Block
kadonotakashi	0:8fdf9a60065b	524	* \| \| \|0 = Load calibration word when calibration functional block is active.
kadonotakashi	0:8fdf9a60065b	525	* \| \| \|1 = Execute calibration when calibration functional block is active.
kadonotakashi	0:8fdf9a60065b	526	* @var EADC_T::CALDWRD
kadonotakashi	0:8fdf9a60065b	527	* Offset: 0x118 ADC Calibration Load Word Register
kadonotakashi	0:8fdf9a60065b	528	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	529	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	530	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	531	* \|[6:0] \|CALWORD \|Calibration Word Bits
kadonotakashi	0:8fdf9a60065b	532	* \| \| \|Write to this register with the previous calibration word before load calibration action.
kadonotakashi	0:8fdf9a60065b	533	* \| \| \|Read this register after calibration done.
kadonotakashi	0:8fdf9a60065b	534	* \| \| \|Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.
kadonotakashi	0:8fdf9a60065b	535	*/
kadonotakashi	0:8fdf9a60065b	536
kadonotakashi	0:8fdf9a60065b	537	__I uint32_t DAT[19]; /!< [0x0000~0x0048] ADC Data Register n for Sample Module n, n=0~18 /
kadonotakashi	0:8fdf9a60065b	538	__I uint32_t CURDAT; /!< [0x004c] ADC PDMA Current Transfer Data Register /
kadonotakashi	0:8fdf9a60065b	539	__IO uint32_t CTL; /!< [0x0050] ADC Control Register /
kadonotakashi	0:8fdf9a60065b	540	__O uint32_t SWTRG; /!< [0x0054] ADC Sample Module Software Start Register /
kadonotakashi	0:8fdf9a60065b	541	__IO uint32_t PENDSTS; /!< [0x0058] ADC Start of Conversion Pending Flag Register /
kadonotakashi	0:8fdf9a60065b	542	__IO uint32_t OVSTS; /!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register /
kadonotakashi	0:8fdf9a60065b	543	__I uint32_t RESERVE0[8];
kadonotakashi	0:8fdf9a60065b	544	__IO uint32_t SCTL[19]; /!< [0x0080~0x00c8] ADC Sample Module n Control Register, n=0~18 /
kadonotakashi	0:8fdf9a60065b	545	__I uint32_t RESERVE1[1];
kadonotakashi	0:8fdf9a60065b	546	__IO uint32_t INTSRC[4]; /!< [0x00d0~0x00dc] ADC interrupt n Source Enable Control Register, n=0~3 /
kadonotakashi	0:8fdf9a60065b	547	__IO uint32_t CMP[4]; /!< [0x00e0~0x00ec] ADC Result Compare Register n, n=0~3 /
kadonotakashi	0:8fdf9a60065b	548	__I uint32_t STATUS0; /!< [0x00f0] ADC Status Register 0 /
kadonotakashi	0:8fdf9a60065b	549	__I uint32_t STATUS1; /!< [0x00f4] ADC Status Register 1 /
kadonotakashi	0:8fdf9a60065b	550	__IO uint32_t STATUS2; /!< [0x00f8] ADC Status Register 2 /
kadonotakashi	0:8fdf9a60065b	551	__I uint32_t STATUS3; /!< [0x00fc] ADC Status Register 3 /
kadonotakashi	0:8fdf9a60065b	552	__I uint32_t DDAT[4]; /!< [0x0100~0x010c] ADC Double Data Register n for Sample Module n, n=0~3 /
kadonotakashi	0:8fdf9a60065b	553	__IO uint32_t PWRM; /!< [0x0110] ADC Power Management Register /
kadonotakashi	0:8fdf9a60065b	554	__IO uint32_t CALCTL; /!< [0x0114] ADC Calibration Control Register /
kadonotakashi	0:8fdf9a60065b	555	__IO uint32_t CALDWRD; /!< [0x0118] ADC Calibration Load Word Register /
kadonotakashi	0:8fdf9a60065b	556
kadonotakashi	0:8fdf9a60065b	557	} EADC_T;
kadonotakashi	0:8fdf9a60065b	558
kadonotakashi	0:8fdf9a60065b	559	/**
kadonotakashi	0:8fdf9a60065b	560	@addtogroup EADC_CONST EADC Bit Field Definition
kadonotakashi	0:8fdf9a60065b	561	Constant Definitions for EADC Controller
kadonotakashi	0:8fdf9a60065b	562	@{ */
kadonotakashi	0:8fdf9a60065b	563
kadonotakashi	0:8fdf9a60065b	564	#define EADC_DAT_RESULT_Pos (0) /!< EADC_T::DAT: RESULT Position /
kadonotakashi	0:8fdf9a60065b	565	#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /!< EADC_T::DAT: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	566
kadonotakashi	0:8fdf9a60065b	567	#define EADC_DAT_OV_Pos (16) /!< EADC_T::DAT: OV Position /
kadonotakashi	0:8fdf9a60065b	568	#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /!< EADC_T::DAT: OV Mask /
kadonotakashi	0:8fdf9a60065b	569
kadonotakashi	0:8fdf9a60065b	570	#define EADC_DAT_VALID_Pos (17) /!< EADC_T::DAT: VALID Position /
kadonotakashi	0:8fdf9a60065b	571	#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /!< EADC_T::DAT: VALID Mask /
kadonotakashi	0:8fdf9a60065b	572
kadonotakashi	0:8fdf9a60065b	573	#define EADC_DAT0_RESULT_Pos (0) /!< EADC_T::DAT0: RESULT Position /
kadonotakashi	0:8fdf9a60065b	574	#define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /!< EADC_T::DAT0: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	575
kadonotakashi	0:8fdf9a60065b	576	#define EADC_DAT0_OV_Pos (16) /!< EADC_T::DAT0: OV Position /
kadonotakashi	0:8fdf9a60065b	577	#define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /!< EADC_T::DAT0: OV Mask /
kadonotakashi	0:8fdf9a60065b	578
kadonotakashi	0:8fdf9a60065b	579	#define EADC_DAT0_VALID_Pos (17) /!< EADC_T::DAT0: VALID Position /
kadonotakashi	0:8fdf9a60065b	580	#define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /!< EADC_T::DAT0: VALID Mask /
kadonotakashi	0:8fdf9a60065b	581
kadonotakashi	0:8fdf9a60065b	582	#define EADC_DAT1_RESULT_Pos (0) /!< EADC_T::DAT1: RESULT Position /
kadonotakashi	0:8fdf9a60065b	583	#define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /!< EADC_T::DAT1: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	584
kadonotakashi	0:8fdf9a60065b	585	#define EADC_DAT1_OV_Pos (16) /!< EADC_T::DAT1: OV Position /
kadonotakashi	0:8fdf9a60065b	586	#define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /!< EADC_T::DAT1: OV Mask /
kadonotakashi	0:8fdf9a60065b	587
kadonotakashi	0:8fdf9a60065b	588	#define EADC_DAT1_VALID_Pos (17) /!< EADC_T::DAT1: VALID Position /
kadonotakashi	0:8fdf9a60065b	589	#define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /!< EADC_T::DAT1: VALID Mask /
kadonotakashi	0:8fdf9a60065b	590
kadonotakashi	0:8fdf9a60065b	591	#define EADC_DAT2_RESULT_Pos (0) /!< EADC_T::DAT2: RESULT Position /
kadonotakashi	0:8fdf9a60065b	592	#define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /!< EADC_T::DAT2: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	593
kadonotakashi	0:8fdf9a60065b	594	#define EADC_DAT2_OV_Pos (16) /!< EADC_T::DAT2: OV Position /
kadonotakashi	0:8fdf9a60065b	595	#define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /!< EADC_T::DAT2: OV Mask /
kadonotakashi	0:8fdf9a60065b	596
kadonotakashi	0:8fdf9a60065b	597	#define EADC_DAT2_VALID_Pos (17) /!< EADC_T::DAT2: VALID Position /
kadonotakashi	0:8fdf9a60065b	598	#define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /!< EADC_T::DAT2: VALID Mask /
kadonotakashi	0:8fdf9a60065b	599
kadonotakashi	0:8fdf9a60065b	600	#define EADC_DAT3_RESULT_Pos (0) /!< EADC_T::DAT3: RESULT Position /
kadonotakashi	0:8fdf9a60065b	601	#define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /!< EADC_T::DAT3: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	602
kadonotakashi	0:8fdf9a60065b	603	#define EADC_DAT3_OV_Pos (16) /!< EADC_T::DAT3: OV Position /
kadonotakashi	0:8fdf9a60065b	604	#define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /!< EADC_T::DAT3: OV Mask /
kadonotakashi	0:8fdf9a60065b	605
kadonotakashi	0:8fdf9a60065b	606	#define EADC_DAT3_VALID_Pos (17) /!< EADC_T::DAT3: VALID Position /
kadonotakashi	0:8fdf9a60065b	607	#define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /!< EADC_T::DAT3: VALID Mask /
kadonotakashi	0:8fdf9a60065b	608
kadonotakashi	0:8fdf9a60065b	609	#define EADC_DAT4_RESULT_Pos (0) /!< EADC_T::DAT4: RESULT Position /
kadonotakashi	0:8fdf9a60065b	610	#define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /!< EADC_T::DAT4: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	611
kadonotakashi	0:8fdf9a60065b	612	#define EADC_DAT4_OV_Pos (16) /!< EADC_T::DAT4: OV Position /
kadonotakashi	0:8fdf9a60065b	613	#define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /!< EADC_T::DAT4: OV Mask /
kadonotakashi	0:8fdf9a60065b	614
kadonotakashi	0:8fdf9a60065b	615	#define EADC_DAT4_VALID_Pos (17) /!< EADC_T::DAT4: VALID Position /
kadonotakashi	0:8fdf9a60065b	616	#define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /!< EADC_T::DAT4: VALID Mask /
kadonotakashi	0:8fdf9a60065b	617
kadonotakashi	0:8fdf9a60065b	618	#define EADC_DAT5_RESULT_Pos (0) /!< EADC_T::DAT5: RESULT Position /
kadonotakashi	0:8fdf9a60065b	619	#define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /!< EADC_T::DAT5: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	620
kadonotakashi	0:8fdf9a60065b	621	#define EADC_DAT5_OV_Pos (16) /!< EADC_T::DAT5: OV Position /
kadonotakashi	0:8fdf9a60065b	622	#define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /!< EADC_T::DAT5: OV Mask /
kadonotakashi	0:8fdf9a60065b	623
kadonotakashi	0:8fdf9a60065b	624	#define EADC_DAT5_VALID_Pos (17) /!< EADC_T::DAT5: VALID Position /
kadonotakashi	0:8fdf9a60065b	625	#define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /!< EADC_T::DAT5: VALID Mask /
kadonotakashi	0:8fdf9a60065b	626
kadonotakashi	0:8fdf9a60065b	627	#define EADC_DAT6_RESULT_Pos (0) /!< EADC_T::DAT6: RESULT Position /
kadonotakashi	0:8fdf9a60065b	628	#define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /!< EADC_T::DAT6: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	629
kadonotakashi	0:8fdf9a60065b	630	#define EADC_DAT6_OV_Pos (16) /!< EADC_T::DAT6: OV Position /
kadonotakashi	0:8fdf9a60065b	631	#define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /!< EADC_T::DAT6: OV Mask /
kadonotakashi	0:8fdf9a60065b	632
kadonotakashi	0:8fdf9a60065b	633	#define EADC_DAT6_VALID_Pos (17) /!< EADC_T::DAT6: VALID Position /
kadonotakashi	0:8fdf9a60065b	634	#define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /!< EADC_T::DAT6: VALID Mask /
kadonotakashi	0:8fdf9a60065b	635
kadonotakashi	0:8fdf9a60065b	636	#define EADC_DAT7_RESULT_Pos (0) /!< EADC_T::DAT7: RESULT Position /
kadonotakashi	0:8fdf9a60065b	637	#define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /!< EADC_T::DAT7: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	638
kadonotakashi	0:8fdf9a60065b	639	#define EADC_DAT7_OV_Pos (16) /!< EADC_T::DAT7: OV Position /
kadonotakashi	0:8fdf9a60065b	640	#define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /!< EADC_T::DAT7: OV Mask /
kadonotakashi	0:8fdf9a60065b	641
kadonotakashi	0:8fdf9a60065b	642	#define EADC_DAT7_VALID_Pos (17) /!< EADC_T::DAT7: VALID Position /
kadonotakashi	0:8fdf9a60065b	643	#define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /!< EADC_T::DAT7: VALID Mask /
kadonotakashi	0:8fdf9a60065b	644
kadonotakashi	0:8fdf9a60065b	645	#define EADC_DAT8_RESULT_Pos (0) /!< EADC_T::DAT8: RESULT Position /
kadonotakashi	0:8fdf9a60065b	646	#define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /!< EADC_T::DAT8: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	647
kadonotakashi	0:8fdf9a60065b	648	#define EADC_DAT8_OV_Pos (16) /!< EADC_T::DAT8: OV Position /
kadonotakashi	0:8fdf9a60065b	649	#define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /!< EADC_T::DAT8: OV Mask /
kadonotakashi	0:8fdf9a60065b	650
kadonotakashi	0:8fdf9a60065b	651	#define EADC_DAT8_VALID_Pos (17) /!< EADC_T::DAT8: VALID Position /
kadonotakashi	0:8fdf9a60065b	652	#define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /!< EADC_T::DAT8: VALID Mask /
kadonotakashi	0:8fdf9a60065b	653
kadonotakashi	0:8fdf9a60065b	654	#define EADC_DAT9_RESULT_Pos (0) /!< EADC_T::DAT9: RESULT Position /
kadonotakashi	0:8fdf9a60065b	655	#define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /!< EADC_T::DAT9: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	656
kadonotakashi	0:8fdf9a60065b	657	#define EADC_DAT9_OV_Pos (16) /!< EADC_T::DAT9: OV Position /
kadonotakashi	0:8fdf9a60065b	658	#define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /!< EADC_T::DAT9: OV Mask /
kadonotakashi	0:8fdf9a60065b	659
kadonotakashi	0:8fdf9a60065b	660	#define EADC_DAT9_VALID_Pos (17) /!< EADC_T::DAT9: VALID Position /
kadonotakashi	0:8fdf9a60065b	661	#define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /!< EADC_T::DAT9: VALID Mask /
kadonotakashi	0:8fdf9a60065b	662
kadonotakashi	0:8fdf9a60065b	663	#define EADC_DAT10_RESULT_Pos (0) /!< EADC_T::DAT10: RESULT Position /
kadonotakashi	0:8fdf9a60065b	664	#define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /!< EADC_T::DAT10: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	665
kadonotakashi	0:8fdf9a60065b	666	#define EADC_DAT10_OV_Pos (16) /!< EADC_T::DAT10: OV Position /
kadonotakashi	0:8fdf9a60065b	667	#define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /!< EADC_T::DAT10: OV Mask /
kadonotakashi	0:8fdf9a60065b	668
kadonotakashi	0:8fdf9a60065b	669	#define EADC_DAT10_VALID_Pos (17) /!< EADC_T::DAT10: VALID Position /
kadonotakashi	0:8fdf9a60065b	670	#define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /!< EADC_T::DAT10: VALID Mask /
kadonotakashi	0:8fdf9a60065b	671
kadonotakashi	0:8fdf9a60065b	672	#define EADC_DAT11_RESULT_Pos (0) /!< EADC_T::DAT11: RESULT Position /
kadonotakashi	0:8fdf9a60065b	673	#define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /!< EADC_T::DAT11: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	674
kadonotakashi	0:8fdf9a60065b	675	#define EADC_DAT11_OV_Pos (16) /!< EADC_T::DAT11: OV Position /
kadonotakashi	0:8fdf9a60065b	676	#define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /!< EADC_T::DAT11: OV Mask /
kadonotakashi	0:8fdf9a60065b	677
kadonotakashi	0:8fdf9a60065b	678	#define EADC_DAT11_VALID_Pos (17) /!< EADC_T::DAT11: VALID Position /
kadonotakashi	0:8fdf9a60065b	679	#define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /!< EADC_T::DAT11: VALID Mask /
kadonotakashi	0:8fdf9a60065b	680
kadonotakashi	0:8fdf9a60065b	681	#define EADC_DAT12_RESULT_Pos (0) /!< EADC_T::DAT12: RESULT Position /
kadonotakashi	0:8fdf9a60065b	682	#define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /!< EADC_T::DAT12: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	683
kadonotakashi	0:8fdf9a60065b	684	#define EADC_DAT12_OV_Pos (16) /!< EADC_T::DAT12: OV Position /
kadonotakashi	0:8fdf9a60065b	685	#define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /!< EADC_T::DAT12: OV Mask /
kadonotakashi	0:8fdf9a60065b	686
kadonotakashi	0:8fdf9a60065b	687	#define EADC_DAT12_VALID_Pos (17) /!< EADC_T::DAT12: VALID Position /
kadonotakashi	0:8fdf9a60065b	688	#define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /!< EADC_T::DAT12: VALID Mask /
kadonotakashi	0:8fdf9a60065b	689
kadonotakashi	0:8fdf9a60065b	690	#define EADC_DAT13_RESULT_Pos (0) /!< EADC_T::DAT13: RESULT Position /
kadonotakashi	0:8fdf9a60065b	691	#define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /!< EADC_T::DAT13: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	692
kadonotakashi	0:8fdf9a60065b	693	#define EADC_DAT13_OV_Pos (16) /!< EADC_T::DAT13: OV Position /
kadonotakashi	0:8fdf9a60065b	694	#define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /!< EADC_T::DAT13: OV Mask /
kadonotakashi	0:8fdf9a60065b	695
kadonotakashi	0:8fdf9a60065b	696	#define EADC_DAT13_VALID_Pos (17) /!< EADC_T::DAT13: VALID Position /
kadonotakashi	0:8fdf9a60065b	697	#define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /!< EADC_T::DAT13: VALID Mask /
kadonotakashi	0:8fdf9a60065b	698
kadonotakashi	0:8fdf9a60065b	699	#define EADC_DAT14_RESULT_Pos (0) /!< EADC_T::DAT14: RESULT Position /
kadonotakashi	0:8fdf9a60065b	700	#define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /!< EADC_T::DAT14: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	701
kadonotakashi	0:8fdf9a60065b	702	#define EADC_DAT14_OV_Pos (16) /!< EADC_T::DAT14: OV Position /
kadonotakashi	0:8fdf9a60065b	703	#define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /!< EADC_T::DAT14: OV Mask /
kadonotakashi	0:8fdf9a60065b	704
kadonotakashi	0:8fdf9a60065b	705	#define EADC_DAT14_VALID_Pos (17) /!< EADC_T::DAT14: VALID Position /
kadonotakashi	0:8fdf9a60065b	706	#define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /!< EADC_T::DAT14: VALID Mask /
kadonotakashi	0:8fdf9a60065b	707
kadonotakashi	0:8fdf9a60065b	708	#define EADC_DAT15_RESULT_Pos (0) /!< EADC_T::DAT15: RESULT Position /
kadonotakashi	0:8fdf9a60065b	709	#define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /!< EADC_T::DAT15: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	710
kadonotakashi	0:8fdf9a60065b	711	#define EADC_DAT15_OV_Pos (16) /!< EADC_T::DAT15: OV Position /
kadonotakashi	0:8fdf9a60065b	712	#define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /!< EADC_T::DAT15: OV Mask /
kadonotakashi	0:8fdf9a60065b	713
kadonotakashi	0:8fdf9a60065b	714	#define EADC_DAT15_VALID_Pos (17) /!< EADC_T::DAT15: VALID Position /
kadonotakashi	0:8fdf9a60065b	715	#define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /!< EADC_T::DAT15: VALID Mask /
kadonotakashi	0:8fdf9a60065b	716
kadonotakashi	0:8fdf9a60065b	717	#define EADC_DAT16_RESULT_Pos (0) /!< EADC_T::DAT16: RESULT Position /
kadonotakashi	0:8fdf9a60065b	718	#define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /!< EADC_T::DAT16: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	719
kadonotakashi	0:8fdf9a60065b	720	#define EADC_DAT16_OV_Pos (16) /!< EADC_T::DAT16: OV Position /
kadonotakashi	0:8fdf9a60065b	721	#define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /!< EADC_T::DAT16: OV Mask /
kadonotakashi	0:8fdf9a60065b	722
kadonotakashi	0:8fdf9a60065b	723	#define EADC_DAT16_VALID_Pos (17) /!< EADC_T::DAT16: VALID Position /
kadonotakashi	0:8fdf9a60065b	724	#define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /!< EADC_T::DAT16: VALID Mask /
kadonotakashi	0:8fdf9a60065b	725
kadonotakashi	0:8fdf9a60065b	726	#define EADC_DAT17_RESULT_Pos (0) /!< EADC_T::DAT17: RESULT Position /
kadonotakashi	0:8fdf9a60065b	727	#define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /!< EADC_T::DAT17: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	728
kadonotakashi	0:8fdf9a60065b	729	#define EADC_DAT17_OV_Pos (16) /!< EADC_T::DAT17: OV Position /
kadonotakashi	0:8fdf9a60065b	730	#define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /!< EADC_T::DAT17: OV Mask /
kadonotakashi	0:8fdf9a60065b	731
kadonotakashi	0:8fdf9a60065b	732	#define EADC_DAT17_VALID_Pos (17) /!< EADC_T::DAT17: VALID Position /
kadonotakashi	0:8fdf9a60065b	733	#define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /!< EADC_T::DAT17: VALID Mask /
kadonotakashi	0:8fdf9a60065b	734
kadonotakashi	0:8fdf9a60065b	735	#define EADC_DAT18_RESULT_Pos (0) /!< EADC_T::DAT18: RESULT Position /
kadonotakashi	0:8fdf9a60065b	736	#define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /!< EADC_T::DAT18: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	737
kadonotakashi	0:8fdf9a60065b	738	#define EADC_DAT18_OV_Pos (16) /!< EADC_T::DAT18: OV Position /
kadonotakashi	0:8fdf9a60065b	739	#define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /!< EADC_T::DAT18: OV Mask /
kadonotakashi	0:8fdf9a60065b	740
kadonotakashi	0:8fdf9a60065b	741	#define EADC_DAT18_VALID_Pos (17) /!< EADC_T::DAT18: VALID Position /
kadonotakashi	0:8fdf9a60065b	742	#define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /!< EADC_T::DAT18: VALID Mask /
kadonotakashi	0:8fdf9a60065b	743
kadonotakashi	0:8fdf9a60065b	744	#define EADC_CURDAT_CURDAT_Pos (0) /!< EADC_T::CURDAT: CURDAT Position /
kadonotakashi	0:8fdf9a60065b	745	#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /!< EADC_T::CURDAT: CURDAT Mask /
kadonotakashi	0:8fdf9a60065b	746
kadonotakashi	0:8fdf9a60065b	747	#define EADC_CTL_ADCEN_Pos (0) /!< EADC_T::CTL: ADCEN Position /
kadonotakashi	0:8fdf9a60065b	748	#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /!< EADC_T::CTL: ADCEN Mask /
kadonotakashi	0:8fdf9a60065b	749
kadonotakashi	0:8fdf9a60065b	750	#define EADC_CTL_ADCRST_Pos (1) /!< EADC_T::CTL: ADCRST Position /
kadonotakashi	0:8fdf9a60065b	751	#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /!< EADC_T::CTL: ADCRST Mask /
kadonotakashi	0:8fdf9a60065b	752
kadonotakashi	0:8fdf9a60065b	753	#define EADC_CTL_ADCIEN0_Pos (2) /!< EADC_T::CTL: ADCIEN0 Position /
kadonotakashi	0:8fdf9a60065b	754	#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /!< EADC_T::CTL: ADCIEN0 Mask /
kadonotakashi	0:8fdf9a60065b	755
kadonotakashi	0:8fdf9a60065b	756	#define EADC_CTL_ADCIEN1_Pos (3) /!< EADC_T::CTL: ADCIEN1 Position /
kadonotakashi	0:8fdf9a60065b	757	#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /!< EADC_T::CTL: ADCIEN1 Mask /
kadonotakashi	0:8fdf9a60065b	758
kadonotakashi	0:8fdf9a60065b	759	#define EADC_CTL_ADCIEN2_Pos (4) /!< EADC_T::CTL: ADCIEN2 Position /
kadonotakashi	0:8fdf9a60065b	760	#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /!< EADC_T::CTL: ADCIEN2 Mask /
kadonotakashi	0:8fdf9a60065b	761
kadonotakashi	0:8fdf9a60065b	762	#define EADC_CTL_ADCIEN3_Pos (5) /!< EADC_T::CTL: ADCIEN3 Position /
kadonotakashi	0:8fdf9a60065b	763	#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /!< EADC_T::CTL: ADCIEN3 Mask /
kadonotakashi	0:8fdf9a60065b	764
kadonotakashi	0:8fdf9a60065b	765	#define EADC_CTL_RESSEL_Pos (6) /!< EADC_T::CTL: RESSEL Position /
kadonotakashi	0:8fdf9a60065b	766	#define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) /!< EADC_T::CTL: RESSEL Mask /
kadonotakashi	0:8fdf9a60065b	767
kadonotakashi	0:8fdf9a60065b	768	#define EADC_CTL_DIFFEN_Pos (8) /!< EADC_T::CTL: DIFFEN Position /
kadonotakashi	0:8fdf9a60065b	769	#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /!< EADC_T::CTL: DIFFEN Mask /
kadonotakashi	0:8fdf9a60065b	770
kadonotakashi	0:8fdf9a60065b	771	#define EADC_CTL_DMOF_Pos (9) /!< EADC_T::CTL: DMOF Position /
kadonotakashi	0:8fdf9a60065b	772	#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /!< EADC_T::CTL: DMOF Mask /
kadonotakashi	0:8fdf9a60065b	773
kadonotakashi	0:8fdf9a60065b	774	#define EADC_CTL_PDMAEN_Pos (11) /!< EADC_T::CTL: PDMAEN Position /
kadonotakashi	0:8fdf9a60065b	775	#define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /!< EADC_T::CTL: PDMAEN Mask /
kadonotakashi	0:8fdf9a60065b	776
kadonotakashi	0:8fdf9a60065b	777	#define EADC_SWTRG_SWTRG_Pos (0) /!< EADC_T::SWTRG: SWTRG Position /
kadonotakashi	0:8fdf9a60065b	778	#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /!< EADC_T::SWTRG: SWTRG Mask /
kadonotakashi	0:8fdf9a60065b	779
kadonotakashi	0:8fdf9a60065b	780	#define EADC_PENDSTS_STPF_Pos (0) /!< EADC_T::PENDSTS: STPF Position /
kadonotakashi	0:8fdf9a60065b	781	#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /!< EADC_T::PENDSTS: STPF Mask /
kadonotakashi	0:8fdf9a60065b	782
kadonotakashi	0:8fdf9a60065b	783	#define EADC_OVSTS_SPOVF_Pos (0) /!< EADC_T::OVSTS: SPOVF Position /
kadonotakashi	0:8fdf9a60065b	784	#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /!< EADC_T::OVSTS: SPOVF Mask /
kadonotakashi	0:8fdf9a60065b	785
kadonotakashi	0:8fdf9a60065b	786	#define EADC_SCTL_CHSEL_Pos (0) /!< EADC_T::SCTL: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	787	#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /!< EADC_T::SCTL: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	788
kadonotakashi	0:8fdf9a60065b	789	#define EADC_SCTL_EXTREN_Pos (4) /!< EADC_T::SCTL: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	790	#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /!< EADC_T::SCTL: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	791
kadonotakashi	0:8fdf9a60065b	792	#define EADC_SCTL_EXTFEN_Pos (5) /!< EADC_T::SCTL: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	793	#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /!< EADC_T::SCTL: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	794
kadonotakashi	0:8fdf9a60065b	795	#define EADC_SCTL_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	796	#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /!< EADC_T::SCTL: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	797
kadonotakashi	0:8fdf9a60065b	798	#define EADC_SCTL_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	799	#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /!< EADC_T::SCTL: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	800
kadonotakashi	0:8fdf9a60065b	801	#define EADC_SCTL_TRGSEL_Pos (16) /!< EADC_T::SCTL: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	802	#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /!< EADC_T::SCTL: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	803
kadonotakashi	0:8fdf9a60065b	804	#define EADC_SCTL_INTPOS_Pos (22) /!< EADC_T::SCTL: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	805	#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /!< EADC_T::SCTL: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	806
kadonotakashi	0:8fdf9a60065b	807	#define EADC_SCTL_DBMEN_Pos (23) /!< EADC_T::SCTL: DBMEN Position /
kadonotakashi	0:8fdf9a60065b	808	#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /!< EADC_T::SCTL: DBMEN Mask /
kadonotakashi	0:8fdf9a60065b	809
kadonotakashi	0:8fdf9a60065b	810	#define EADC_SCTL_EXTSMPT_Pos (24) /!< EADC_T::SCTL: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	811	#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /!< EADC_T::SCTL: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	812
kadonotakashi	0:8fdf9a60065b	813	#define EADC_SCTL0_CHSEL_Pos (0) /!< EADC_T::SCTL0: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	814	#define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /!< EADC_T::SCTL0: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	815
kadonotakashi	0:8fdf9a60065b	816	#define EADC_SCTL0_EXTREN_Pos (4) /!< EADC_T::SCTL0: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	817	#define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /!< EADC_T::SCTL0: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	818
kadonotakashi	0:8fdf9a60065b	819	#define EADC_SCTL0_EXTFEN_Pos (5) /!< EADC_T::SCTL0: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	820	#define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /!< EADC_T::SCTL0: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	821
kadonotakashi	0:8fdf9a60065b	822	#define EADC_SCTL0_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL0: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	823	#define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /!< EADC_T::SCTL0: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	824
kadonotakashi	0:8fdf9a60065b	825	#define EADC_SCTL0_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL0: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	826	#define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /!< EADC_T::SCTL0: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	827
kadonotakashi	0:8fdf9a60065b	828	#define EADC_SCTL0_TRGSEL_Pos (16) /!< EADC_T::SCTL0: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	829	#define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /!< EADC_T::SCTL0: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	830
kadonotakashi	0:8fdf9a60065b	831	#define EADC_SCTL0_INTPOS_Pos (22) /!< EADC_T::SCTL0: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	832	#define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /!< EADC_T::SCTL0: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	833
kadonotakashi	0:8fdf9a60065b	834	#define EADC_SCTL0_DBMEN_Pos (23) /!< EADC_T::SCTL0: DBMEN Position /
kadonotakashi	0:8fdf9a60065b	835	#define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /!< EADC_T::SCTL0: DBMEN Mask /
kadonotakashi	0:8fdf9a60065b	836
kadonotakashi	0:8fdf9a60065b	837	#define EADC_SCTL0_EXTSMPT_Pos (24) /!< EADC_T::SCTL0: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	838	#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /!< EADC_T::SCTL0: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	839
kadonotakashi	0:8fdf9a60065b	840	#define EADC_SCTL1_CHSEL_Pos (0) /!< EADC_T::SCTL1: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	841	#define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /!< EADC_T::SCTL1: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	842
kadonotakashi	0:8fdf9a60065b	843	#define EADC_SCTL1_EXTREN_Pos (4) /!< EADC_T::SCTL1: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	844	#define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /!< EADC_T::SCTL1: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	845
kadonotakashi	0:8fdf9a60065b	846	#define EADC_SCTL1_EXTFEN_Pos (5) /!< EADC_T::SCTL1: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	847	#define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /!< EADC_T::SCTL1: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	848
kadonotakashi	0:8fdf9a60065b	849	#define EADC_SCTL1_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL1: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	850	#define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /!< EADC_T::SCTL1: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	851
kadonotakashi	0:8fdf9a60065b	852	#define EADC_SCTL1_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL1: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	853	#define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /!< EADC_T::SCTL1: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	854
kadonotakashi	0:8fdf9a60065b	855	#define EADC_SCTL1_TRGSEL_Pos (16) /!< EADC_T::SCTL1: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	856	#define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /!< EADC_T::SCTL1: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	857
kadonotakashi	0:8fdf9a60065b	858	#define EADC_SCTL1_INTPOS_Pos (22) /!< EADC_T::SCTL1: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	859	#define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /!< EADC_T::SCTL1: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	860
kadonotakashi	0:8fdf9a60065b	861	#define EADC_SCTL1_DBMEN_Pos (23) /!< EADC_T::SCTL1: DBMEN Position /
kadonotakashi	0:8fdf9a60065b	862	#define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /!< EADC_T::SCTL1: DBMEN Mask /
kadonotakashi	0:8fdf9a60065b	863
kadonotakashi	0:8fdf9a60065b	864	#define EADC_SCTL1_EXTSMPT_Pos (24) /!< EADC_T::SCTL1: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	865	#define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /!< EADC_T::SCTL1: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	866
kadonotakashi	0:8fdf9a60065b	867	#define EADC_SCTL2_CHSEL_Pos (0) /!< EADC_T::SCTL2: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	868	#define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /!< EADC_T::SCTL2: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	869
kadonotakashi	0:8fdf9a60065b	870	#define EADC_SCTL2_EXTREN_Pos (4) /!< EADC_T::SCTL2: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	871	#define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /!< EADC_T::SCTL2: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	872
kadonotakashi	0:8fdf9a60065b	873	#define EADC_SCTL2_EXTFEN_Pos (5) /!< EADC_T::SCTL2: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	874	#define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /!< EADC_T::SCTL2: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	875
kadonotakashi	0:8fdf9a60065b	876	#define EADC_SCTL2_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL2: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	877	#define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /!< EADC_T::SCTL2: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	878
kadonotakashi	0:8fdf9a60065b	879	#define EADC_SCTL2_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL2: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	880	#define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /!< EADC_T::SCTL2: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	881
kadonotakashi	0:8fdf9a60065b	882	#define EADC_SCTL2_TRGSEL_Pos (16) /!< EADC_T::SCTL2: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	883	#define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /!< EADC_T::SCTL2: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	884
kadonotakashi	0:8fdf9a60065b	885	#define EADC_SCTL2_INTPOS_Pos (22) /!< EADC_T::SCTL2: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	886	#define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /!< EADC_T::SCTL2: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	887
kadonotakashi	0:8fdf9a60065b	888	#define EADC_SCTL2_DBMEN_Pos (23) /!< EADC_T::SCTL2: DBMEN Position /
kadonotakashi	0:8fdf9a60065b	889	#define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /!< EADC_T::SCTL2: DBMEN Mask /
kadonotakashi	0:8fdf9a60065b	890
kadonotakashi	0:8fdf9a60065b	891	#define EADC_SCTL2_EXTSMPT_Pos (24) /!< EADC_T::SCTL2: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	892	#define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /!< EADC_T::SCTL2: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	893
kadonotakashi	0:8fdf9a60065b	894	#define EADC_SCTL3_CHSEL_Pos (0) /!< EADC_T::SCTL3: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	895	#define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /!< EADC_T::SCTL3: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	896
kadonotakashi	0:8fdf9a60065b	897	#define EADC_SCTL3_EXTREN_Pos (4) /!< EADC_T::SCTL3: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	898	#define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /!< EADC_T::SCTL3: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	899
kadonotakashi	0:8fdf9a60065b	900	#define EADC_SCTL3_EXTFEN_Pos (5) /!< EADC_T::SCTL3: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	901	#define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /!< EADC_T::SCTL3: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	902
kadonotakashi	0:8fdf9a60065b	903	#define EADC_SCTL3_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL3: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	904	#define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /!< EADC_T::SCTL3: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	905
kadonotakashi	0:8fdf9a60065b	906	#define EADC_SCTL3_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL3: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	907	#define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /!< EADC_T::SCTL3: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	908
kadonotakashi	0:8fdf9a60065b	909	#define EADC_SCTL3_TRGSEL_Pos (16) /!< EADC_T::SCTL3: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	910	#define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /!< EADC_T::SCTL3: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	911
kadonotakashi	0:8fdf9a60065b	912	#define EADC_SCTL3_INTPOS_Pos (22) /!< EADC_T::SCTL3: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	913	#define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /!< EADC_T::SCTL3: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	914
kadonotakashi	0:8fdf9a60065b	915	#define EADC_SCTL3_DBMEN_Pos (23) /!< EADC_T::SCTL3: DBMEN Position /
kadonotakashi	0:8fdf9a60065b	916	#define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /!< EADC_T::SCTL3: DBMEN Mask /
kadonotakashi	0:8fdf9a60065b	917
kadonotakashi	0:8fdf9a60065b	918	#define EADC_SCTL3_EXTSMPT_Pos (24) /!< EADC_T::SCTL3: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	919	#define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /!< EADC_T::SCTL3: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	920
kadonotakashi	0:8fdf9a60065b	921	#define EADC_SCTL4_CHSEL_Pos (0) /!< EADC_T::SCTL4: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	922	#define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /!< EADC_T::SCTL4: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	923
kadonotakashi	0:8fdf9a60065b	924	#define EADC_SCTL4_EXTREN_Pos (4) /!< EADC_T::SCTL4: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	925	#define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /!< EADC_T::SCTL4: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	926
kadonotakashi	0:8fdf9a60065b	927	#define EADC_SCTL4_EXTFEN_Pos (5) /!< EADC_T::SCTL4: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	928	#define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /!< EADC_T::SCTL4: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	929
kadonotakashi	0:8fdf9a60065b	930	#define EADC_SCTL4_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL4: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	931	#define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /!< EADC_T::SCTL4: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	932
kadonotakashi	0:8fdf9a60065b	933	#define EADC_SCTL4_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL4: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	934	#define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /!< EADC_T::SCTL4: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	935
kadonotakashi	0:8fdf9a60065b	936	#define EADC_SCTL4_TRGSEL_Pos (16) /!< EADC_T::SCTL4: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	937	#define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /!< EADC_T::SCTL4: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	938
kadonotakashi	0:8fdf9a60065b	939	#define EADC_SCTL4_INTPOS_Pos (22) /!< EADC_T::SCTL4: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	940	#define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /!< EADC_T::SCTL4: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	941
kadonotakashi	0:8fdf9a60065b	942	#define EADC_SCTL4_EXTSMPT_Pos (24) /!< EADC_T::SCTL4: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	943	#define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /!< EADC_T::SCTL4: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	944
kadonotakashi	0:8fdf9a60065b	945	#define EADC_SCTL5_CHSEL_Pos (0) /!< EADC_T::SCTL5: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	946	#define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /!< EADC_T::SCTL5: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	947
kadonotakashi	0:8fdf9a60065b	948	#define EADC_SCTL5_EXTREN_Pos (4) /!< EADC_T::SCTL5: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	949	#define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /!< EADC_T::SCTL5: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	950
kadonotakashi	0:8fdf9a60065b	951	#define EADC_SCTL5_EXTFEN_Pos (5) /!< EADC_T::SCTL5: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	952	#define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /!< EADC_T::SCTL5: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	953
kadonotakashi	0:8fdf9a60065b	954	#define EADC_SCTL5_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL5: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	955	#define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /!< EADC_T::SCTL5: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	956
kadonotakashi	0:8fdf9a60065b	957	#define EADC_SCTL5_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL5: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	958	#define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /!< EADC_T::SCTL5: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	959
kadonotakashi	0:8fdf9a60065b	960	#define EADC_SCTL5_TRGSEL_Pos (16) /!< EADC_T::SCTL5: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	961	#define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /!< EADC_T::SCTL5: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	962
kadonotakashi	0:8fdf9a60065b	963	#define EADC_SCTL5_INTPOS_Pos (22) /!< EADC_T::SCTL5: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	964	#define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /!< EADC_T::SCTL5: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	965
kadonotakashi	0:8fdf9a60065b	966	#define EADC_SCTL5_EXTSMPT_Pos (24) /!< EADC_T::SCTL5: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	967	#define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /!< EADC_T::SCTL5: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	968
kadonotakashi	0:8fdf9a60065b	969	#define EADC_SCTL6_CHSEL_Pos (0) /!< EADC_T::SCTL6: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	970	#define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /!< EADC_T::SCTL6: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	971
kadonotakashi	0:8fdf9a60065b	972	#define EADC_SCTL6_EXTREN_Pos (4) /!< EADC_T::SCTL6: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	973	#define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /!< EADC_T::SCTL6: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	974
kadonotakashi	0:8fdf9a60065b	975	#define EADC_SCTL6_EXTFEN_Pos (5) /!< EADC_T::SCTL6: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	976	#define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /!< EADC_T::SCTL6: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	977
kadonotakashi	0:8fdf9a60065b	978	#define EADC_SCTL6_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL6: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	979	#define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /!< EADC_T::SCTL6: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	980
kadonotakashi	0:8fdf9a60065b	981	#define EADC_SCTL6_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL6: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	982	#define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /!< EADC_T::SCTL6: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	983
kadonotakashi	0:8fdf9a60065b	984	#define EADC_SCTL6_TRGSEL_Pos (16) /!< EADC_T::SCTL6: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	985	#define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /!< EADC_T::SCTL6: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	986
kadonotakashi	0:8fdf9a60065b	987	#define EADC_SCTL6_INTPOS_Pos (22) /!< EADC_T::SCTL6: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	988	#define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /!< EADC_T::SCTL6: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	989
kadonotakashi	0:8fdf9a60065b	990	#define EADC_SCTL6_EXTSMPT_Pos (24) /!< EADC_T::SCTL6: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	991	#define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /!< EADC_T::SCTL6: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	992
kadonotakashi	0:8fdf9a60065b	993	#define EADC_SCTL7_CHSEL_Pos (0) /!< EADC_T::SCTL7: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	994	#define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /!< EADC_T::SCTL7: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	995
kadonotakashi	0:8fdf9a60065b	996	#define EADC_SCTL7_EXTREN_Pos (4) /!< EADC_T::SCTL7: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	997	#define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /!< EADC_T::SCTL7: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	998
kadonotakashi	0:8fdf9a60065b	999	#define EADC_SCTL7_EXTFEN_Pos (5) /!< EADC_T::SCTL7: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	1000	#define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /!< EADC_T::SCTL7: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	1001
kadonotakashi	0:8fdf9a60065b	1002	#define EADC_SCTL7_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL7: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	1003	#define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /!< EADC_T::SCTL7: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	1004
kadonotakashi	0:8fdf9a60065b	1005	#define EADC_SCTL7_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL7: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	1006	#define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /!< EADC_T::SCTL7: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	1007
kadonotakashi	0:8fdf9a60065b	1008	#define EADC_SCTL7_TRGSEL_Pos (16) /!< EADC_T::SCTL7: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	1009	#define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /!< EADC_T::SCTL7: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1010
kadonotakashi	0:8fdf9a60065b	1011	#define EADC_SCTL7_INTPOS_Pos (22) /!< EADC_T::SCTL7: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	1012	#define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /!< EADC_T::SCTL7: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	1013
kadonotakashi	0:8fdf9a60065b	1014	#define EADC_SCTL7_EXTSMPT_Pos (24) /!< EADC_T::SCTL7: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1015	#define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /!< EADC_T::SCTL7: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1016
kadonotakashi	0:8fdf9a60065b	1017	#define EADC_SCTL8_CHSEL_Pos (0) /!< EADC_T::SCTL8: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	1018	#define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) /!< EADC_T::SCTL8: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	1019
kadonotakashi	0:8fdf9a60065b	1020	#define EADC_SCTL8_EXTREN_Pos (4) /!< EADC_T::SCTL8: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	1021	#define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /!< EADC_T::SCTL8: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	1022
kadonotakashi	0:8fdf9a60065b	1023	#define EADC_SCTL8_EXTFEN_Pos (5) /!< EADC_T::SCTL8: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	1024	#define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /!< EADC_T::SCTL8: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	1025
kadonotakashi	0:8fdf9a60065b	1026	#define EADC_SCTL8_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL8: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	1027	#define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /!< EADC_T::SCTL8: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	1028
kadonotakashi	0:8fdf9a60065b	1029	#define EADC_SCTL8_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL8: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	1030	#define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /!< EADC_T::SCTL8: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	1031
kadonotakashi	0:8fdf9a60065b	1032	#define EADC_SCTL8_TRGSEL_Pos (16) /!< EADC_T::SCTL8: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	1033	#define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /!< EADC_T::SCTL8: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1034
kadonotakashi	0:8fdf9a60065b	1035	#define EADC_SCTL8_INTPOS_Pos (22) /!< EADC_T::SCTL8: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	1036	#define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /!< EADC_T::SCTL8: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	1037
kadonotakashi	0:8fdf9a60065b	1038	#define EADC_SCTL8_EXTSMPT_Pos (24) /!< EADC_T::SCTL8: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1039	#define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /!< EADC_T::SCTL8: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1040
kadonotakashi	0:8fdf9a60065b	1041	#define EADC_SCTL9_CHSEL_Pos (0) /!< EADC_T::SCTL9: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	1042	#define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) /!< EADC_T::SCTL9: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	1043
kadonotakashi	0:8fdf9a60065b	1044	#define EADC_SCTL9_EXTREN_Pos (4) /!< EADC_T::SCTL9: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	1045	#define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /!< EADC_T::SCTL9: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	1046
kadonotakashi	0:8fdf9a60065b	1047	#define EADC_SCTL9_EXTFEN_Pos (5) /!< EADC_T::SCTL9: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	1048	#define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /!< EADC_T::SCTL9: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	1049
kadonotakashi	0:8fdf9a60065b	1050	#define EADC_SCTL9_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL9: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	1051	#define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /!< EADC_T::SCTL9: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	1052
kadonotakashi	0:8fdf9a60065b	1053	#define EADC_SCTL9_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL9: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	1054	#define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /!< EADC_T::SCTL9: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	1055
kadonotakashi	0:8fdf9a60065b	1056	#define EADC_SCTL9_TRGSEL_Pos (16) /!< EADC_T::SCTL9: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	1057	#define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /!< EADC_T::SCTL9: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1058
kadonotakashi	0:8fdf9a60065b	1059	#define EADC_SCTL9_INTPOS_Pos (22) /!< EADC_T::SCTL9: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	1060	#define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /!< EADC_T::SCTL9: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	1061
kadonotakashi	0:8fdf9a60065b	1062	#define EADC_SCTL9_EXTSMPT_Pos (24) /!< EADC_T::SCTL9: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1063	#define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /!< EADC_T::SCTL9: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1064
kadonotakashi	0:8fdf9a60065b	1065	#define EADC_SCTL10_CHSEL_Pos (0) /!< EADC_T::SCTL10: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	1066	#define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) /!< EADC_T::SCTL10: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	1067
kadonotakashi	0:8fdf9a60065b	1068	#define EADC_SCTL10_EXTREN_Pos (4) /!< EADC_T::SCTL10: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	1069	#define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /!< EADC_T::SCTL10: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	1070
kadonotakashi	0:8fdf9a60065b	1071	#define EADC_SCTL10_EXTFEN_Pos (5) /!< EADC_T::SCTL10: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	1072	#define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /!< EADC_T::SCTL10: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	1073
kadonotakashi	0:8fdf9a60065b	1074	#define EADC_SCTL10_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL10: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	1075	#define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /!< EADC_T::SCTL10: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	1076
kadonotakashi	0:8fdf9a60065b	1077	#define EADC_SCTL10_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL10: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	1078	#define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /!< EADC_T::SCTL10: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	1079
kadonotakashi	0:8fdf9a60065b	1080	#define EADC_SCTL10_TRGSEL_Pos (16) /!< EADC_T::SCTL10: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	1081	#define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /!< EADC_T::SCTL10: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1082
kadonotakashi	0:8fdf9a60065b	1083	#define EADC_SCTL10_INTPOS_Pos (22) /!< EADC_T::SCTL10: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	1084	#define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /!< EADC_T::SCTL10: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	1085
kadonotakashi	0:8fdf9a60065b	1086	#define EADC_SCTL10_EXTSMPT_Pos (24) /!< EADC_T::SCTL10: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1087	#define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /!< EADC_T::SCTL10: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1088
kadonotakashi	0:8fdf9a60065b	1089	#define EADC_SCTL11_CHSEL_Pos (0) /!< EADC_T::SCTL11: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	1090	#define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) /!< EADC_T::SCTL11: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	1091
kadonotakashi	0:8fdf9a60065b	1092	#define EADC_SCTL11_EXTREN_Pos (4) /!< EADC_T::SCTL11: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	1093	#define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /!< EADC_T::SCTL11: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	1094
kadonotakashi	0:8fdf9a60065b	1095	#define EADC_SCTL11_EXTFEN_Pos (5) /!< EADC_T::SCTL11: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	1096	#define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /!< EADC_T::SCTL11: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	1097
kadonotakashi	0:8fdf9a60065b	1098	#define EADC_SCTL11_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL11: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	1099	#define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /!< EADC_T::SCTL11: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	1100
kadonotakashi	0:8fdf9a60065b	1101	#define EADC_SCTL11_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL11: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	1102	#define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /!< EADC_T::SCTL11: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	1103
kadonotakashi	0:8fdf9a60065b	1104	#define EADC_SCTL11_TRGSEL_Pos (16) /!< EADC_T::SCTL11: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	1105	#define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /!< EADC_T::SCTL11: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1106
kadonotakashi	0:8fdf9a60065b	1107	#define EADC_SCTL11_INTPOS_Pos (22) /!< EADC_T::SCTL11: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	1108	#define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /!< EADC_T::SCTL11: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	1109
kadonotakashi	0:8fdf9a60065b	1110	#define EADC_SCTL11_EXTSMPT_Pos (24) /!< EADC_T::SCTL11: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1111	#define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /!< EADC_T::SCTL11: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1112
kadonotakashi	0:8fdf9a60065b	1113	#define EADC_SCTL12_CHSEL_Pos (0) /!< EADC_T::SCTL12: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	1114	#define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) /!< EADC_T::SCTL12: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	1115
kadonotakashi	0:8fdf9a60065b	1116	#define EADC_SCTL12_EXTREN_Pos (4) /!< EADC_T::SCTL12: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	1117	#define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /!< EADC_T::SCTL12: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	1118
kadonotakashi	0:8fdf9a60065b	1119	#define EADC_SCTL12_EXTFEN_Pos (5) /!< EADC_T::SCTL12: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	1120	#define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /!< EADC_T::SCTL12: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	1121
kadonotakashi	0:8fdf9a60065b	1122	#define EADC_SCTL12_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL12: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	1123	#define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /!< EADC_T::SCTL12: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	1124
kadonotakashi	0:8fdf9a60065b	1125	#define EADC_SCTL12_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL12: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	1126	#define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /!< EADC_T::SCTL12: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	1127
kadonotakashi	0:8fdf9a60065b	1128	#define EADC_SCTL12_TRGSEL_Pos (16) /!< EADC_T::SCTL12: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	1129	#define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /!< EADC_T::SCTL12: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1130
kadonotakashi	0:8fdf9a60065b	1131	#define EADC_SCTL12_INTPOS_Pos (22) /!< EADC_T::SCTL12: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	1132	#define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /!< EADC_T::SCTL12: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	1133
kadonotakashi	0:8fdf9a60065b	1134	#define EADC_SCTL12_EXTSMPT_Pos (24) /!< EADC_T::SCTL12: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1135	#define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /!< EADC_T::SCTL12: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1136
kadonotakashi	0:8fdf9a60065b	1137	#define EADC_SCTL13_CHSEL_Pos (0) /!< EADC_T::SCTL13: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	1138	#define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) /!< EADC_T::SCTL13: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	1139
kadonotakashi	0:8fdf9a60065b	1140	#define EADC_SCTL13_EXTREN_Pos (4) /!< EADC_T::SCTL13: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	1141	#define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /!< EADC_T::SCTL13: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	1142
kadonotakashi	0:8fdf9a60065b	1143	#define EADC_SCTL13_EXTFEN_Pos (5) /!< EADC_T::SCTL13: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	1144	#define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /!< EADC_T::SCTL13: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	1145
kadonotakashi	0:8fdf9a60065b	1146	#define EADC_SCTL13_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL13: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	1147	#define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /!< EADC_T::SCTL13: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	1148
kadonotakashi	0:8fdf9a60065b	1149	#define EADC_SCTL13_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL13: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	1150	#define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /!< EADC_T::SCTL13: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	1151
kadonotakashi	0:8fdf9a60065b	1152	#define EADC_SCTL13_TRGSEL_Pos (16) /!< EADC_T::SCTL13: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	1153	#define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /!< EADC_T::SCTL13: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1154
kadonotakashi	0:8fdf9a60065b	1155	#define EADC_SCTL13_INTPOS_Pos (22) /!< EADC_T::SCTL13: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	1156	#define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /!< EADC_T::SCTL13: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	1157
kadonotakashi	0:8fdf9a60065b	1158	#define EADC_SCTL13_EXTSMPT_Pos (24) /!< EADC_T::SCTL13: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1159	#define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /!< EADC_T::SCTL13: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1160
kadonotakashi	0:8fdf9a60065b	1161	#define EADC_SCTL14_CHSEL_Pos (0) /!< EADC_T::SCTL14: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	1162	#define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) /!< EADC_T::SCTL14: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	1163
kadonotakashi	0:8fdf9a60065b	1164	#define EADC_SCTL14_EXTREN_Pos (4) /!< EADC_T::SCTL14: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	1165	#define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /!< EADC_T::SCTL14: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	1166
kadonotakashi	0:8fdf9a60065b	1167	#define EADC_SCTL14_EXTFEN_Pos (5) /!< EADC_T::SCTL14: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	1168	#define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /!< EADC_T::SCTL14: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	1169
kadonotakashi	0:8fdf9a60065b	1170	#define EADC_SCTL14_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL14: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	1171	#define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /!< EADC_T::SCTL14: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	1172
kadonotakashi	0:8fdf9a60065b	1173	#define EADC_SCTL14_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL14: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	1174	#define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /!< EADC_T::SCTL14: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	1175
kadonotakashi	0:8fdf9a60065b	1176	#define EADC_SCTL14_TRGSEL_Pos (16) /!< EADC_T::SCTL14: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	1177	#define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /!< EADC_T::SCTL14: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1178
kadonotakashi	0:8fdf9a60065b	1179	#define EADC_SCTL14_INTPOS_Pos (22) /!< EADC_T::SCTL14: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	1180	#define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /!< EADC_T::SCTL14: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	1181
kadonotakashi	0:8fdf9a60065b	1182	#define EADC_SCTL14_EXTSMPT_Pos (24) /!< EADC_T::SCTL14: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1183	#define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /!< EADC_T::SCTL14: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1184
kadonotakashi	0:8fdf9a60065b	1185	#define EADC_SCTL15_CHSEL_Pos (0) /!< EADC_T::SCTL15: CHSEL Position /
kadonotakashi	0:8fdf9a60065b	1186	#define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) /!< EADC_T::SCTL15: CHSEL Mask /
kadonotakashi	0:8fdf9a60065b	1187
kadonotakashi	0:8fdf9a60065b	1188	#define EADC_SCTL15_EXTREN_Pos (4) /!< EADC_T::SCTL15: EXTREN Position /
kadonotakashi	0:8fdf9a60065b	1189	#define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /!< EADC_T::SCTL15: EXTREN Mask /
kadonotakashi	0:8fdf9a60065b	1190
kadonotakashi	0:8fdf9a60065b	1191	#define EADC_SCTL15_EXTFEN_Pos (5) /!< EADC_T::SCTL15: EXTFEN Position /
kadonotakashi	0:8fdf9a60065b	1192	#define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /!< EADC_T::SCTL15: EXTFEN Mask /
kadonotakashi	0:8fdf9a60065b	1193
kadonotakashi	0:8fdf9a60065b	1194	#define EADC_SCTL15_TRGDLYDIV_Pos (6) /!< EADC_T::SCTL15: TRGDLYDIV Position /
kadonotakashi	0:8fdf9a60065b	1195	#define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /!< EADC_T::SCTL15: TRGDLYDIV Mask /
kadonotakashi	0:8fdf9a60065b	1196
kadonotakashi	0:8fdf9a60065b	1197	#define EADC_SCTL15_TRGDLYCNT_Pos (8) /!< EADC_T::SCTL15: TRGDLYCNT Position /
kadonotakashi	0:8fdf9a60065b	1198	#define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /!< EADC_T::SCTL15: TRGDLYCNT Mask /
kadonotakashi	0:8fdf9a60065b	1199
kadonotakashi	0:8fdf9a60065b	1200	#define EADC_SCTL15_TRGSEL_Pos (16) /!< EADC_T::SCTL15: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	1201	#define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /!< EADC_T::SCTL15: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1202
kadonotakashi	0:8fdf9a60065b	1203	#define EADC_SCTL15_INTPOS_Pos (22) /!< EADC_T::SCTL15: INTPOS Position /
kadonotakashi	0:8fdf9a60065b	1204	#define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /!< EADC_T::SCTL15: INTPOS Mask /
kadonotakashi	0:8fdf9a60065b	1205
kadonotakashi	0:8fdf9a60065b	1206	#define EADC_SCTL15_EXTSMPT_Pos (24) /!< EADC_T::SCTL15: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1207	#define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /!< EADC_T::SCTL15: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1208
kadonotakashi	0:8fdf9a60065b	1209	#define EADC_SCTL16_EXTSMPT_Pos (24) /!< EADC_T::SCTL16: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1210	#define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /!< EADC_T::SCTL16: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1211
kadonotakashi	0:8fdf9a60065b	1212	#define EADC_SCTL17_EXTSMPT_Pos (24) /!< EADC_T::SCTL17: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1213	#define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /!< EADC_T::SCTL17: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1214
kadonotakashi	0:8fdf9a60065b	1215	#define EADC_SCTL18_EXTSMPT_Pos (24) /!< EADC_T::SCTL18: EXTSMPT Position /
kadonotakashi	0:8fdf9a60065b	1216	#define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /!< EADC_T::SCTL18: EXTSMPT Mask /
kadonotakashi	0:8fdf9a60065b	1217
kadonotakashi	0:8fdf9a60065b	1218	#define EADC_INTSRC0_SPLIE0_Pos (0) /!< EADC_T::INTSRC0: SPLIE0 Position /
kadonotakashi	0:8fdf9a60065b	1219	#define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /!< EADC_T::INTSRC0: SPLIE0 Mask /
kadonotakashi	0:8fdf9a60065b	1220
kadonotakashi	0:8fdf9a60065b	1221	#define EADC_INTSRC0_SPLIE1_Pos (1) /!< EADC_T::INTSRC0: SPLIE1 Position /
kadonotakashi	0:8fdf9a60065b	1222	#define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /!< EADC_T::INTSRC0: SPLIE1 Mask /
kadonotakashi	0:8fdf9a60065b	1223
kadonotakashi	0:8fdf9a60065b	1224	#define EADC_INTSRC0_SPLIE2_Pos (2) /!< EADC_T::INTSRC0: SPLIE2 Position /
kadonotakashi	0:8fdf9a60065b	1225	#define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /!< EADC_T::INTSRC0: SPLIE2 Mask /
kadonotakashi	0:8fdf9a60065b	1226
kadonotakashi	0:8fdf9a60065b	1227	#define EADC_INTSRC0_SPLIE3_Pos (3) /!< EADC_T::INTSRC0: SPLIE3 Position /
kadonotakashi	0:8fdf9a60065b	1228	#define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /!< EADC_T::INTSRC0: SPLIE3 Mask /
kadonotakashi	0:8fdf9a60065b	1229
kadonotakashi	0:8fdf9a60065b	1230	#define EADC_INTSRC0_SPLIE4_Pos (4) /!< EADC_T::INTSRC0: SPLIE4 Position /
kadonotakashi	0:8fdf9a60065b	1231	#define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /!< EADC_T::INTSRC0: SPLIE4 Mask /
kadonotakashi	0:8fdf9a60065b	1232
kadonotakashi	0:8fdf9a60065b	1233	#define EADC_INTSRC0_SPLIE5_Pos (5) /!< EADC_T::INTSRC0: SPLIE5 Position /
kadonotakashi	0:8fdf9a60065b	1234	#define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /!< EADC_T::INTSRC0: SPLIE5 Mask /
kadonotakashi	0:8fdf9a60065b	1235
kadonotakashi	0:8fdf9a60065b	1236	#define EADC_INTSRC0_SPLIE6_Pos (6) /!< EADC_T::INTSRC0: SPLIE6 Position /
kadonotakashi	0:8fdf9a60065b	1237	#define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /!< EADC_T::INTSRC0: SPLIE6 Mask /
kadonotakashi	0:8fdf9a60065b	1238
kadonotakashi	0:8fdf9a60065b	1239	#define EADC_INTSRC0_SPLIE7_Pos (7) /!< EADC_T::INTSRC0: SPLIE7 Position /
kadonotakashi	0:8fdf9a60065b	1240	#define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /!< EADC_T::INTSRC0: SPLIE7 Mask /
kadonotakashi	0:8fdf9a60065b	1241
kadonotakashi	0:8fdf9a60065b	1242	#define EADC_INTSRC0_SPLIE8_Pos (8) /!< EADC_T::INTSRC0: SPLIE8 Position /
kadonotakashi	0:8fdf9a60065b	1243	#define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /!< EADC_T::INTSRC0: SPLIE8 Mask /
kadonotakashi	0:8fdf9a60065b	1244
kadonotakashi	0:8fdf9a60065b	1245	#define EADC_INTSRC0_SPLIE9_Pos (9) /!< EADC_T::INTSRC0: SPLIE9 Position /
kadonotakashi	0:8fdf9a60065b	1246	#define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /!< EADC_T::INTSRC0: SPLIE9 Mask /
kadonotakashi	0:8fdf9a60065b	1247
kadonotakashi	0:8fdf9a60065b	1248	#define EADC_INTSRC0_SPLIE10_Pos (10) /!< EADC_T::INTSRC0: SPLIE10 Position /
kadonotakashi	0:8fdf9a60065b	1249	#define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /!< EADC_T::INTSRC0: SPLIE10 Mask /
kadonotakashi	0:8fdf9a60065b	1250
kadonotakashi	0:8fdf9a60065b	1251	#define EADC_INTSRC0_SPLIE11_Pos (11) /!< EADC_T::INTSRC0: SPLIE11 Position /
kadonotakashi	0:8fdf9a60065b	1252	#define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /!< EADC_T::INTSRC0: SPLIE11 Mask /
kadonotakashi	0:8fdf9a60065b	1253
kadonotakashi	0:8fdf9a60065b	1254	#define EADC_INTSRC0_SPLIE12_Pos (12) /!< EADC_T::INTSRC0: SPLIE12 Position /
kadonotakashi	0:8fdf9a60065b	1255	#define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /!< EADC_T::INTSRC0: SPLIE12 Mask /
kadonotakashi	0:8fdf9a60065b	1256
kadonotakashi	0:8fdf9a60065b	1257	#define EADC_INTSRC0_SPLIE13_Pos (13) /!< EADC_T::INTSRC0: SPLIE13 Position /
kadonotakashi	0:8fdf9a60065b	1258	#define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /!< EADC_T::INTSRC0: SPLIE13 Mask /
kadonotakashi	0:8fdf9a60065b	1259
kadonotakashi	0:8fdf9a60065b	1260	#define EADC_INTSRC0_SPLIE14_Pos (14) /!< EADC_T::INTSRC0: SPLIE14 Position /
kadonotakashi	0:8fdf9a60065b	1261	#define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /!< EADC_T::INTSRC0: SPLIE14 Mask /
kadonotakashi	0:8fdf9a60065b	1262
kadonotakashi	0:8fdf9a60065b	1263	#define EADC_INTSRC0_SPLIE15_Pos (15) /!< EADC_T::INTSRC0: SPLIE15 Position /
kadonotakashi	0:8fdf9a60065b	1264	#define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /!< EADC_T::INTSRC0: SPLIE15 Mask /
kadonotakashi	0:8fdf9a60065b	1265
kadonotakashi	0:8fdf9a60065b	1266	#define EADC_INTSRC0_SPLIE16_Pos (16) /!< EADC_T::INTSRC0: SPLIE16 Position /
kadonotakashi	0:8fdf9a60065b	1267	#define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /!< EADC_T::INTSRC0: SPLIE16 Mask /
kadonotakashi	0:8fdf9a60065b	1268
kadonotakashi	0:8fdf9a60065b	1269	#define EADC_INTSRC0_SPLIE17_Pos (17) /!< EADC_T::INTSRC0: SPLIE17 Position /
kadonotakashi	0:8fdf9a60065b	1270	#define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /!< EADC_T::INTSRC0: SPLIE17 Mask /
kadonotakashi	0:8fdf9a60065b	1271
kadonotakashi	0:8fdf9a60065b	1272	#define EADC_INTSRC0_SPLIE18_Pos (18) /!< EADC_T::INTSRC0: SPLIE18 Position /
kadonotakashi	0:8fdf9a60065b	1273	#define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /!< EADC_T::INTSRC0: SPLIE18 Mask /
kadonotakashi	0:8fdf9a60065b	1274
kadonotakashi	0:8fdf9a60065b	1275	#define EADC_INTSRC1_SPLIE0_Pos (0) /!< EADC_T::INTSRC1: SPLIE0 Position /
kadonotakashi	0:8fdf9a60065b	1276	#define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /!< EADC_T::INTSRC1: SPLIE0 Mask /
kadonotakashi	0:8fdf9a60065b	1277
kadonotakashi	0:8fdf9a60065b	1278	#define EADC_INTSRC1_SPLIE1_Pos (1) /!< EADC_T::INTSRC1: SPLIE1 Position /
kadonotakashi	0:8fdf9a60065b	1279	#define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /!< EADC_T::INTSRC1: SPLIE1 Mask /
kadonotakashi	0:8fdf9a60065b	1280
kadonotakashi	0:8fdf9a60065b	1281	#define EADC_INTSRC1_SPLIE2_Pos (2) /!< EADC_T::INTSRC1: SPLIE2 Position /
kadonotakashi	0:8fdf9a60065b	1282	#define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /!< EADC_T::INTSRC1: SPLIE2 Mask /
kadonotakashi	0:8fdf9a60065b	1283
kadonotakashi	0:8fdf9a60065b	1284	#define EADC_INTSRC1_SPLIE3_Pos (3) /!< EADC_T::INTSRC1: SPLIE3 Position /
kadonotakashi	0:8fdf9a60065b	1285	#define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /!< EADC_T::INTSRC1: SPLIE3 Mask /
kadonotakashi	0:8fdf9a60065b	1286
kadonotakashi	0:8fdf9a60065b	1287	#define EADC_INTSRC1_SPLIE4_Pos (4) /!< EADC_T::INTSRC1: SPLIE4 Position /
kadonotakashi	0:8fdf9a60065b	1288	#define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /!< EADC_T::INTSRC1: SPLIE4 Mask /
kadonotakashi	0:8fdf9a60065b	1289
kadonotakashi	0:8fdf9a60065b	1290	#define EADC_INTSRC1_SPLIE5_Pos (5) /!< EADC_T::INTSRC1: SPLIE5 Position /
kadonotakashi	0:8fdf9a60065b	1291	#define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /!< EADC_T::INTSRC1: SPLIE5 Mask /
kadonotakashi	0:8fdf9a60065b	1292
kadonotakashi	0:8fdf9a60065b	1293	#define EADC_INTSRC1_SPLIE6_Pos (6) /!< EADC_T::INTSRC1: SPLIE6 Position /
kadonotakashi	0:8fdf9a60065b	1294	#define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /!< EADC_T::INTSRC1: SPLIE6 Mask /
kadonotakashi	0:8fdf9a60065b	1295
kadonotakashi	0:8fdf9a60065b	1296	#define EADC_INTSRC1_SPLIE7_Pos (7) /!< EADC_T::INTSRC1: SPLIE7 Position /
kadonotakashi	0:8fdf9a60065b	1297	#define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /!< EADC_T::INTSRC1: SPLIE7 Mask /
kadonotakashi	0:8fdf9a60065b	1298
kadonotakashi	0:8fdf9a60065b	1299	#define EADC_INTSRC1_SPLIE8_Pos (8) /!< EADC_T::INTSRC1: SPLIE8 Position /
kadonotakashi	0:8fdf9a60065b	1300	#define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /!< EADC_T::INTSRC1: SPLIE8 Mask /
kadonotakashi	0:8fdf9a60065b	1301
kadonotakashi	0:8fdf9a60065b	1302	#define EADC_INTSRC1_SPLIE9_Pos (9) /!< EADC_T::INTSRC1: SPLIE9 Position /
kadonotakashi	0:8fdf9a60065b	1303	#define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /!< EADC_T::INTSRC1: SPLIE9 Mask /
kadonotakashi	0:8fdf9a60065b	1304
kadonotakashi	0:8fdf9a60065b	1305	#define EADC_INTSRC1_SPLIE10_Pos (10) /!< EADC_T::INTSRC1: SPLIE10 Position /
kadonotakashi	0:8fdf9a60065b	1306	#define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /!< EADC_T::INTSRC1: SPLIE10 Mask /
kadonotakashi	0:8fdf9a60065b	1307
kadonotakashi	0:8fdf9a60065b	1308	#define EADC_INTSRC1_SPLIE11_Pos (11) /!< EADC_T::INTSRC1: SPLIE11 Position /
kadonotakashi	0:8fdf9a60065b	1309	#define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /!< EADC_T::INTSRC1: SPLIE11 Mask /
kadonotakashi	0:8fdf9a60065b	1310
kadonotakashi	0:8fdf9a60065b	1311	#define EADC_INTSRC1_SPLIE12_Pos (12) /!< EADC_T::INTSRC1: SPLIE12 Position /
kadonotakashi	0:8fdf9a60065b	1312	#define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /!< EADC_T::INTSRC1: SPLIE12 Mask /
kadonotakashi	0:8fdf9a60065b	1313
kadonotakashi	0:8fdf9a60065b	1314	#define EADC_INTSRC1_SPLIE13_Pos (13) /!< EADC_T::INTSRC1: SPLIE13 Position /
kadonotakashi	0:8fdf9a60065b	1315	#define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /!< EADC_T::INTSRC1: SPLIE13 Mask /
kadonotakashi	0:8fdf9a60065b	1316
kadonotakashi	0:8fdf9a60065b	1317	#define EADC_INTSRC1_SPLIE14_Pos (14) /!< EADC_T::INTSRC1: SPLIE14 Position /
kadonotakashi	0:8fdf9a60065b	1318	#define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /!< EADC_T::INTSRC1: SPLIE14 Mask /
kadonotakashi	0:8fdf9a60065b	1319
kadonotakashi	0:8fdf9a60065b	1320	#define EADC_INTSRC1_SPLIE15_Pos (15) /!< EADC_T::INTSRC1: SPLIE15 Position /
kadonotakashi	0:8fdf9a60065b	1321	#define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /!< EADC_T::INTSRC1: SPLIE15 Mask /
kadonotakashi	0:8fdf9a60065b	1322
kadonotakashi	0:8fdf9a60065b	1323	#define EADC_INTSRC1_SPLIE16_Pos (16) /!< EADC_T::INTSRC1: SPLIE16 Position /
kadonotakashi	0:8fdf9a60065b	1324	#define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /!< EADC_T::INTSRC1: SPLIE16 Mask /
kadonotakashi	0:8fdf9a60065b	1325
kadonotakashi	0:8fdf9a60065b	1326	#define EADC_INTSRC1_SPLIE17_Pos (17) /!< EADC_T::INTSRC1: SPLIE17 Position /
kadonotakashi	0:8fdf9a60065b	1327	#define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /!< EADC_T::INTSRC1: SPLIE17 Mask /
kadonotakashi	0:8fdf9a60065b	1328
kadonotakashi	0:8fdf9a60065b	1329	#define EADC_INTSRC1_SPLIE18_Pos (18) /!< EADC_T::INTSRC1: SPLIE18 Position /
kadonotakashi	0:8fdf9a60065b	1330	#define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /!< EADC_T::INTSRC1: SPLIE18 Mask /
kadonotakashi	0:8fdf9a60065b	1331
kadonotakashi	0:8fdf9a60065b	1332	#define EADC_INTSRC2_SPLIE0_Pos (0) /!< EADC_T::INTSRC2: SPLIE0 Position /
kadonotakashi	0:8fdf9a60065b	1333	#define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /!< EADC_T::INTSRC2: SPLIE0 Mask /
kadonotakashi	0:8fdf9a60065b	1334
kadonotakashi	0:8fdf9a60065b	1335	#define EADC_INTSRC2_SPLIE1_Pos (1) /!< EADC_T::INTSRC2: SPLIE1 Position /
kadonotakashi	0:8fdf9a60065b	1336	#define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /!< EADC_T::INTSRC2: SPLIE1 Mask /
kadonotakashi	0:8fdf9a60065b	1337
kadonotakashi	0:8fdf9a60065b	1338	#define EADC_INTSRC2_SPLIE2_Pos (2) /!< EADC_T::INTSRC2: SPLIE2 Position /
kadonotakashi	0:8fdf9a60065b	1339	#define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /!< EADC_T::INTSRC2: SPLIE2 Mask /
kadonotakashi	0:8fdf9a60065b	1340
kadonotakashi	0:8fdf9a60065b	1341	#define EADC_INTSRC2_SPLIE3_Pos (3) /!< EADC_T::INTSRC2: SPLIE3 Position /
kadonotakashi	0:8fdf9a60065b	1342	#define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /!< EADC_T::INTSRC2: SPLIE3 Mask /
kadonotakashi	0:8fdf9a60065b	1343
kadonotakashi	0:8fdf9a60065b	1344	#define EADC_INTSRC2_SPLIE4_Pos (4) /!< EADC_T::INTSRC2: SPLIE4 Position /
kadonotakashi	0:8fdf9a60065b	1345	#define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /!< EADC_T::INTSRC2: SPLIE4 Mask /
kadonotakashi	0:8fdf9a60065b	1346
kadonotakashi	0:8fdf9a60065b	1347	#define EADC_INTSRC2_SPLIE5_Pos (5) /!< EADC_T::INTSRC2: SPLIE5 Position /
kadonotakashi	0:8fdf9a60065b	1348	#define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /!< EADC_T::INTSRC2: SPLIE5 Mask /
kadonotakashi	0:8fdf9a60065b	1349
kadonotakashi	0:8fdf9a60065b	1350	#define EADC_INTSRC2_SPLIE6_Pos (6) /!< EADC_T::INTSRC2: SPLIE6 Position /
kadonotakashi	0:8fdf9a60065b	1351	#define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /!< EADC_T::INTSRC2: SPLIE6 Mask /
kadonotakashi	0:8fdf9a60065b	1352
kadonotakashi	0:8fdf9a60065b	1353	#define EADC_INTSRC2_SPLIE7_Pos (7) /!< EADC_T::INTSRC2: SPLIE7 Position /
kadonotakashi	0:8fdf9a60065b	1354	#define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /!< EADC_T::INTSRC2: SPLIE7 Mask /
kadonotakashi	0:8fdf9a60065b	1355
kadonotakashi	0:8fdf9a60065b	1356	#define EADC_INTSRC2_SPLIE8_Pos (8) /!< EADC_T::INTSRC2: SPLIE8 Position /
kadonotakashi	0:8fdf9a60065b	1357	#define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /!< EADC_T::INTSRC2: SPLIE8 Mask /
kadonotakashi	0:8fdf9a60065b	1358
kadonotakashi	0:8fdf9a60065b	1359	#define EADC_INTSRC2_SPLIE9_Pos (9) /!< EADC_T::INTSRC2: SPLIE9 Position /
kadonotakashi	0:8fdf9a60065b	1360	#define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /!< EADC_T::INTSRC2: SPLIE9 Mask /
kadonotakashi	0:8fdf9a60065b	1361
kadonotakashi	0:8fdf9a60065b	1362	#define EADC_INTSRC2_SPLIE10_Pos (10) /!< EADC_T::INTSRC2: SPLIE10 Position /
kadonotakashi	0:8fdf9a60065b	1363	#define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /!< EADC_T::INTSRC2: SPLIE10 Mask /
kadonotakashi	0:8fdf9a60065b	1364
kadonotakashi	0:8fdf9a60065b	1365	#define EADC_INTSRC2_SPLIE11_Pos (11) /!< EADC_T::INTSRC2: SPLIE11 Position /
kadonotakashi	0:8fdf9a60065b	1366	#define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /!< EADC_T::INTSRC2: SPLIE11 Mask /
kadonotakashi	0:8fdf9a60065b	1367
kadonotakashi	0:8fdf9a60065b	1368	#define EADC_INTSRC2_SPLIE12_Pos (12) /!< EADC_T::INTSRC2: SPLIE12 Position /
kadonotakashi	0:8fdf9a60065b	1369	#define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /!< EADC_T::INTSRC2: SPLIE12 Mask /
kadonotakashi	0:8fdf9a60065b	1370
kadonotakashi	0:8fdf9a60065b	1371	#define EADC_INTSRC2_SPLIE13_Pos (13) /!< EADC_T::INTSRC2: SPLIE13 Position /
kadonotakashi	0:8fdf9a60065b	1372	#define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /!< EADC_T::INTSRC2: SPLIE13 Mask /
kadonotakashi	0:8fdf9a60065b	1373
kadonotakashi	0:8fdf9a60065b	1374	#define EADC_INTSRC2_SPLIE14_Pos (14) /!< EADC_T::INTSRC2: SPLIE14 Position /
kadonotakashi	0:8fdf9a60065b	1375	#define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /!< EADC_T::INTSRC2: SPLIE14 Mask /
kadonotakashi	0:8fdf9a60065b	1376
kadonotakashi	0:8fdf9a60065b	1377	#define EADC_INTSRC2_SPLIE15_Pos (15) /!< EADC_T::INTSRC2: SPLIE15 Position /
kadonotakashi	0:8fdf9a60065b	1378	#define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /!< EADC_T::INTSRC2: SPLIE15 Mask /
kadonotakashi	0:8fdf9a60065b	1379
kadonotakashi	0:8fdf9a60065b	1380	#define EADC_INTSRC2_SPLIE16_Pos (16) /!< EADC_T::INTSRC2: SPLIE16 Position /
kadonotakashi	0:8fdf9a60065b	1381	#define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /!< EADC_T::INTSRC2: SPLIE16 Mask /
kadonotakashi	0:8fdf9a60065b	1382
kadonotakashi	0:8fdf9a60065b	1383	#define EADC_INTSRC2_SPLIE17_Pos (17) /!< EADC_T::INTSRC2: SPLIE17 Position /
kadonotakashi	0:8fdf9a60065b	1384	#define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /!< EADC_T::INTSRC2: SPLIE17 Mask /
kadonotakashi	0:8fdf9a60065b	1385
kadonotakashi	0:8fdf9a60065b	1386	#define EADC_INTSRC2_SPLIE18_Pos (18) /!< EADC_T::INTSRC2: SPLIE18 Position /
kadonotakashi	0:8fdf9a60065b	1387	#define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /!< EADC_T::INTSRC2: SPLIE18 Mask /
kadonotakashi	0:8fdf9a60065b	1388
kadonotakashi	0:8fdf9a60065b	1389	#define EADC_INTSRC3_SPLIE0_Pos (0) /!< EADC_T::INTSRC3: SPLIE0 Position /
kadonotakashi	0:8fdf9a60065b	1390	#define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /!< EADC_T::INTSRC3: SPLIE0 Mask /
kadonotakashi	0:8fdf9a60065b	1391
kadonotakashi	0:8fdf9a60065b	1392	#define EADC_INTSRC3_SPLIE1_Pos (1) /!< EADC_T::INTSRC3: SPLIE1 Position /
kadonotakashi	0:8fdf9a60065b	1393	#define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /!< EADC_T::INTSRC3: SPLIE1 Mask /
kadonotakashi	0:8fdf9a60065b	1394
kadonotakashi	0:8fdf9a60065b	1395	#define EADC_INTSRC3_SPLIE2_Pos (2) /!< EADC_T::INTSRC3: SPLIE2 Position /
kadonotakashi	0:8fdf9a60065b	1396	#define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /!< EADC_T::INTSRC3: SPLIE2 Mask /
kadonotakashi	0:8fdf9a60065b	1397
kadonotakashi	0:8fdf9a60065b	1398	#define EADC_INTSRC3_SPLIE3_Pos (3) /!< EADC_T::INTSRC3: SPLIE3 Position /
kadonotakashi	0:8fdf9a60065b	1399	#define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /!< EADC_T::INTSRC3: SPLIE3 Mask /
kadonotakashi	0:8fdf9a60065b	1400
kadonotakashi	0:8fdf9a60065b	1401	#define EADC_INTSRC3_SPLIE4_Pos (4) /!< EADC_T::INTSRC3: SPLIE4 Position /
kadonotakashi	0:8fdf9a60065b	1402	#define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /!< EADC_T::INTSRC3: SPLIE4 Mask /
kadonotakashi	0:8fdf9a60065b	1403
kadonotakashi	0:8fdf9a60065b	1404	#define EADC_INTSRC3_SPLIE5_Pos (5) /!< EADC_T::INTSRC3: SPLIE5 Position /
kadonotakashi	0:8fdf9a60065b	1405	#define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /!< EADC_T::INTSRC3: SPLIE5 Mask /
kadonotakashi	0:8fdf9a60065b	1406
kadonotakashi	0:8fdf9a60065b	1407	#define EADC_INTSRC3_SPLIE6_Pos (6) /!< EADC_T::INTSRC3: SPLIE6 Position /
kadonotakashi	0:8fdf9a60065b	1408	#define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /!< EADC_T::INTSRC3: SPLIE6 Mask /
kadonotakashi	0:8fdf9a60065b	1409
kadonotakashi	0:8fdf9a60065b	1410	#define EADC_INTSRC3_SPLIE7_Pos (7) /!< EADC_T::INTSRC3: SPLIE7 Position /
kadonotakashi	0:8fdf9a60065b	1411	#define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /!< EADC_T::INTSRC3: SPLIE7 Mask /
kadonotakashi	0:8fdf9a60065b	1412
kadonotakashi	0:8fdf9a60065b	1413	#define EADC_INTSRC3_SPLIE8_Pos (8) /!< EADC_T::INTSRC3: SPLIE8 Position /
kadonotakashi	0:8fdf9a60065b	1414	#define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /!< EADC_T::INTSRC3: SPLIE8 Mask /
kadonotakashi	0:8fdf9a60065b	1415
kadonotakashi	0:8fdf9a60065b	1416	#define EADC_INTSRC3_SPLIE9_Pos (9) /!< EADC_T::INTSRC3: SPLIE9 Position /
kadonotakashi	0:8fdf9a60065b	1417	#define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /!< EADC_T::INTSRC3: SPLIE9 Mask /
kadonotakashi	0:8fdf9a60065b	1418
kadonotakashi	0:8fdf9a60065b	1419	#define EADC_INTSRC3_SPLIE10_Pos (10) /!< EADC_T::INTSRC3: SPLIE10 Position /
kadonotakashi	0:8fdf9a60065b	1420	#define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /!< EADC_T::INTSRC3: SPLIE10 Mask /
kadonotakashi	0:8fdf9a60065b	1421
kadonotakashi	0:8fdf9a60065b	1422	#define EADC_INTSRC3_SPLIE11_Pos (11) /!< EADC_T::INTSRC3: SPLIE11 Position /
kadonotakashi	0:8fdf9a60065b	1423	#define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /!< EADC_T::INTSRC3: SPLIE11 Mask /
kadonotakashi	0:8fdf9a60065b	1424
kadonotakashi	0:8fdf9a60065b	1425	#define EADC_INTSRC3_SPLIE12_Pos (12) /!< EADC_T::INTSRC3: SPLIE12 Position /
kadonotakashi	0:8fdf9a60065b	1426	#define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /!< EADC_T::INTSRC3: SPLIE12 Mask /
kadonotakashi	0:8fdf9a60065b	1427
kadonotakashi	0:8fdf9a60065b	1428	#define EADC_INTSRC3_SPLIE13_Pos (13) /!< EADC_T::INTSRC3: SPLIE13 Position /
kadonotakashi	0:8fdf9a60065b	1429	#define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /!< EADC_T::INTSRC3: SPLIE13 Mask /
kadonotakashi	0:8fdf9a60065b	1430
kadonotakashi	0:8fdf9a60065b	1431	#define EADC_INTSRC3_SPLIE14_Pos (14) /!< EADC_T::INTSRC3: SPLIE14 Position /
kadonotakashi	0:8fdf9a60065b	1432	#define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /!< EADC_T::INTSRC3: SPLIE14 Mask /
kadonotakashi	0:8fdf9a60065b	1433
kadonotakashi	0:8fdf9a60065b	1434	#define EADC_INTSRC3_SPLIE15_Pos (15) /!< EADC_T::INTSRC3: SPLIE15 Position /
kadonotakashi	0:8fdf9a60065b	1435	#define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /!< EADC_T::INTSRC3: SPLIE15 Mask /
kadonotakashi	0:8fdf9a60065b	1436
kadonotakashi	0:8fdf9a60065b	1437	#define EADC_INTSRC3_SPLIE16_Pos (16) /!< EADC_T::INTSRC3: SPLIE16 Position /
kadonotakashi	0:8fdf9a60065b	1438	#define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /!< EADC_T::INTSRC3: SPLIE16 Mask /
kadonotakashi	0:8fdf9a60065b	1439
kadonotakashi	0:8fdf9a60065b	1440	#define EADC_INTSRC3_SPLIE17_Pos (17) /!< EADC_T::INTSRC3: SPLIE17 Position /
kadonotakashi	0:8fdf9a60065b	1441	#define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /!< EADC_T::INTSRC3: SPLIE17 Mask /
kadonotakashi	0:8fdf9a60065b	1442
kadonotakashi	0:8fdf9a60065b	1443	#define EADC_INTSRC3_SPLIE18_Pos (18) /!< EADC_T::INTSRC3: SPLIE18 Position /
kadonotakashi	0:8fdf9a60065b	1444	#define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /!< EADC_T::INTSRC3: SPLIE18 Mask /
kadonotakashi	0:8fdf9a60065b	1445
kadonotakashi	0:8fdf9a60065b	1446	#define EADC_CMP_ADCMPEN_Pos (0) /!< EADC_T::CMP: ADCMPEN Position /
kadonotakashi	0:8fdf9a60065b	1447	#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /!< EADC_T::CMP: ADCMPEN Mask /
kadonotakashi	0:8fdf9a60065b	1448
kadonotakashi	0:8fdf9a60065b	1449	#define EADC_CMP_ADCMPIE_Pos (1) /!< EADC_T::CMP: ADCMPIE Position /
kadonotakashi	0:8fdf9a60065b	1450	#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /!< EADC_T::CMP: ADCMPIE Mask /
kadonotakashi	0:8fdf9a60065b	1451
kadonotakashi	0:8fdf9a60065b	1452	#define EADC_CMP_CMPCOND_Pos (2) /!< EADC_T::CMP: CMPCOND Position /
kadonotakashi	0:8fdf9a60065b	1453	#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /!< EADC_T::CMP: CMPCOND Mask /
kadonotakashi	0:8fdf9a60065b	1454
kadonotakashi	0:8fdf9a60065b	1455	#define EADC_CMP_CMPSPL_Pos (3) /!< EADC_T::CMP: CMPSPL Position /
kadonotakashi	0:8fdf9a60065b	1456	#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /!< EADC_T::CMP: CMPSPL Mask /
kadonotakashi	0:8fdf9a60065b	1457
kadonotakashi	0:8fdf9a60065b	1458	#define EADC_CMP_CMPMCNT_Pos (8) /!< EADC_T::CMP: CMPMCNT Position /
kadonotakashi	0:8fdf9a60065b	1459	#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /!< EADC_T::CMP: CMPMCNT Mask /
kadonotakashi	0:8fdf9a60065b	1460
kadonotakashi	0:8fdf9a60065b	1461	#define EADC_CMP_CMPWEN_Pos (15) /!< EADC_T::CMP: CMPWEN Position /
kadonotakashi	0:8fdf9a60065b	1462	#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /!< EADC_T::CMP: CMPWEN Mask /
kadonotakashi	0:8fdf9a60065b	1463
kadonotakashi	0:8fdf9a60065b	1464	#define EADC_CMP_CMPDAT_Pos (16) /!< EADC_T::CMP: CMPDAT Position /
kadonotakashi	0:8fdf9a60065b	1465	#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /!< EADC_T::CMP: CMPDAT Mask /
kadonotakashi	0:8fdf9a60065b	1466
kadonotakashi	0:8fdf9a60065b	1467	#define EADC_CMP0_ADCMPEN_Pos (0) /!< EADC_T::CMP0: ADCMPEN Position /
kadonotakashi	0:8fdf9a60065b	1468	#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /!< EADC_T::CMP0: ADCMPEN Mask /
kadonotakashi	0:8fdf9a60065b	1469
kadonotakashi	0:8fdf9a60065b	1470	#define EADC_CMP0_ADCMPIE_Pos (1) /!< EADC_T::CMP0: ADCMPIE Position /
kadonotakashi	0:8fdf9a60065b	1471	#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /!< EADC_T::CMP0: ADCMPIE Mask /
kadonotakashi	0:8fdf9a60065b	1472
kadonotakashi	0:8fdf9a60065b	1473	#define EADC_CMP0_CMPCOND_Pos (2) /!< EADC_T::CMP0: CMPCOND Position /
kadonotakashi	0:8fdf9a60065b	1474	#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /!< EADC_T::CMP0: CMPCOND Mask /
kadonotakashi	0:8fdf9a60065b	1475
kadonotakashi	0:8fdf9a60065b	1476	#define EADC_CMP0_CMPSPL_Pos (3) /!< EADC_T::CMP0: CMPSPL Position /
kadonotakashi	0:8fdf9a60065b	1477	#define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /!< EADC_T::CMP0: CMPSPL Mask /
kadonotakashi	0:8fdf9a60065b	1478
kadonotakashi	0:8fdf9a60065b	1479	#define EADC_CMP0_CMPMCNT_Pos (8) /!< EADC_T::CMP0: CMPMCNT Position /
kadonotakashi	0:8fdf9a60065b	1480	#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /!< EADC_T::CMP0: CMPMCNT Mask /
kadonotakashi	0:8fdf9a60065b	1481
kadonotakashi	0:8fdf9a60065b	1482	#define EADC_CMP0_CMPWEN_Pos (15) /!< EADC_T::CMP0: CMPWEN Position /
kadonotakashi	0:8fdf9a60065b	1483	#define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /!< EADC_T::CMP0: CMPWEN Mask /
kadonotakashi	0:8fdf9a60065b	1484
kadonotakashi	0:8fdf9a60065b	1485	#define EADC_CMP0_CMPDAT_Pos (16) /!< EADC_T::CMP0: CMPDAT Position /
kadonotakashi	0:8fdf9a60065b	1486	#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /!< EADC_T::CMP0: CMPDAT Mask /
kadonotakashi	0:8fdf9a60065b	1487
kadonotakashi	0:8fdf9a60065b	1488	#define EADC_CMP1_ADCMPEN_Pos (0) /!< EADC_T::CMP1: ADCMPEN Position /
kadonotakashi	0:8fdf9a60065b	1489	#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /!< EADC_T::CMP1: ADCMPEN Mask /
kadonotakashi	0:8fdf9a60065b	1490
kadonotakashi	0:8fdf9a60065b	1491	#define EADC_CMP1_ADCMPIE_Pos (1) /!< EADC_T::CMP1: ADCMPIE Position /
kadonotakashi	0:8fdf9a60065b	1492	#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /!< EADC_T::CMP1: ADCMPIE Mask /
kadonotakashi	0:8fdf9a60065b	1493
kadonotakashi	0:8fdf9a60065b	1494	#define EADC_CMP1_CMPCOND_Pos (2) /!< EADC_T::CMP1: CMPCOND Position /
kadonotakashi	0:8fdf9a60065b	1495	#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /!< EADC_T::CMP1: CMPCOND Mask /
kadonotakashi	0:8fdf9a60065b	1496
kadonotakashi	0:8fdf9a60065b	1497	#define EADC_CMP1_CMPSPL_Pos (3) /!< EADC_T::CMP1: CMPSPL Position /
kadonotakashi	0:8fdf9a60065b	1498	#define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /!< EADC_T::CMP1: CMPSPL Mask /
kadonotakashi	0:8fdf9a60065b	1499
kadonotakashi	0:8fdf9a60065b	1500	#define EADC_CMP1_CMPMCNT_Pos (8) /!< EADC_T::CMP1: CMPMCNT Position /
kadonotakashi	0:8fdf9a60065b	1501	#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /!< EADC_T::CMP1: CMPMCNT Mask /
kadonotakashi	0:8fdf9a60065b	1502
kadonotakashi	0:8fdf9a60065b	1503	#define EADC_CMP1_CMPWEN_Pos (15) /!< EADC_T::CMP1: CMPWEN Position /
kadonotakashi	0:8fdf9a60065b	1504	#define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /!< EADC_T::CMP1: CMPWEN Mask /
kadonotakashi	0:8fdf9a60065b	1505
kadonotakashi	0:8fdf9a60065b	1506	#define EADC_CMP1_CMPDAT_Pos (16) /!< EADC_T::CMP1: CMPDAT Position /
kadonotakashi	0:8fdf9a60065b	1507	#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /!< EADC_T::CMP1: CMPDAT Mask /
kadonotakashi	0:8fdf9a60065b	1508
kadonotakashi	0:8fdf9a60065b	1509	#define EADC_CMP2_ADCMPEN_Pos (0) /!< EADC_T::CMP2: ADCMPEN Position /
kadonotakashi	0:8fdf9a60065b	1510	#define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /!< EADC_T::CMP2: ADCMPEN Mask /
kadonotakashi	0:8fdf9a60065b	1511
kadonotakashi	0:8fdf9a60065b	1512	#define EADC_CMP2_ADCMPIE_Pos (1) /!< EADC_T::CMP2: ADCMPIE Position /
kadonotakashi	0:8fdf9a60065b	1513	#define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /!< EADC_T::CMP2: ADCMPIE Mask /
kadonotakashi	0:8fdf9a60065b	1514
kadonotakashi	0:8fdf9a60065b	1515	#define EADC_CMP2_CMPCOND_Pos (2) /!< EADC_T::CMP2: CMPCOND Position /
kadonotakashi	0:8fdf9a60065b	1516	#define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /!< EADC_T::CMP2: CMPCOND Mask /
kadonotakashi	0:8fdf9a60065b	1517
kadonotakashi	0:8fdf9a60065b	1518	#define EADC_CMP2_CMPSPL_Pos (3) /!< EADC_T::CMP2: CMPSPL Position /
kadonotakashi	0:8fdf9a60065b	1519	#define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /!< EADC_T::CMP2: CMPSPL Mask /
kadonotakashi	0:8fdf9a60065b	1520
kadonotakashi	0:8fdf9a60065b	1521	#define EADC_CMP2_CMPMCNT_Pos (8) /!< EADC_T::CMP2: CMPMCNT Position /
kadonotakashi	0:8fdf9a60065b	1522	#define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /!< EADC_T::CMP2: CMPMCNT Mask /
kadonotakashi	0:8fdf9a60065b	1523
kadonotakashi	0:8fdf9a60065b	1524	#define EADC_CMP2_CMPWEN_Pos (15) /!< EADC_T::CMP2: CMPWEN Position /
kadonotakashi	0:8fdf9a60065b	1525	#define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /!< EADC_T::CMP2: CMPWEN Mask /
kadonotakashi	0:8fdf9a60065b	1526
kadonotakashi	0:8fdf9a60065b	1527	#define EADC_CMP2_CMPDAT_Pos (16) /!< EADC_T::CMP2: CMPDAT Position /
kadonotakashi	0:8fdf9a60065b	1528	#define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /!< EADC_T::CMP2: CMPDAT Mask /
kadonotakashi	0:8fdf9a60065b	1529
kadonotakashi	0:8fdf9a60065b	1530	#define EADC_CMP3_ADCMPEN_Pos (0) /!< EADC_T::CMP3: ADCMPEN Position /
kadonotakashi	0:8fdf9a60065b	1531	#define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /!< EADC_T::CMP3: ADCMPEN Mask /
kadonotakashi	0:8fdf9a60065b	1532
kadonotakashi	0:8fdf9a60065b	1533	#define EADC_CMP3_ADCMPIE_Pos (1) /!< EADC_T::CMP3: ADCMPIE Position /
kadonotakashi	0:8fdf9a60065b	1534	#define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /!< EADC_T::CMP3: ADCMPIE Mask /
kadonotakashi	0:8fdf9a60065b	1535
kadonotakashi	0:8fdf9a60065b	1536	#define EADC_CMP3_CMPCOND_Pos (2) /!< EADC_T::CMP3: CMPCOND Position /
kadonotakashi	0:8fdf9a60065b	1537	#define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /!< EADC_T::CMP3: CMPCOND Mask /
kadonotakashi	0:8fdf9a60065b	1538
kadonotakashi	0:8fdf9a60065b	1539	#define EADC_CMP3_CMPSPL_Pos (3) /!< EADC_T::CMP3: CMPSPL Position /
kadonotakashi	0:8fdf9a60065b	1540	#define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /!< EADC_T::CMP3: CMPSPL Mask /
kadonotakashi	0:8fdf9a60065b	1541
kadonotakashi	0:8fdf9a60065b	1542	#define EADC_CMP3_CMPMCNT_Pos (8) /!< EADC_T::CMP3: CMPMCNT Position /
kadonotakashi	0:8fdf9a60065b	1543	#define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /!< EADC_T::CMP3: CMPMCNT Mask /
kadonotakashi	0:8fdf9a60065b	1544
kadonotakashi	0:8fdf9a60065b	1545	#define EADC_CMP3_CMPWEN_Pos (15) /!< EADC_T::CMP3: CMPWEN Position /
kadonotakashi	0:8fdf9a60065b	1546	#define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /!< EADC_T::CMP3: CMPWEN Mask /
kadonotakashi	0:8fdf9a60065b	1547
kadonotakashi	0:8fdf9a60065b	1548	#define EADC_CMP3_CMPDAT_Pos (16) /!< EADC_T::CMP3: CMPDAT Position /
kadonotakashi	0:8fdf9a60065b	1549	#define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /!< EADC_T::CMP3: CMPDAT Mask /
kadonotakashi	0:8fdf9a60065b	1550
kadonotakashi	0:8fdf9a60065b	1551	#define EADC_STATUS0_VALID_Pos (0) /!< EADC_T::STATUS0: VALID Position /
kadonotakashi	0:8fdf9a60065b	1552	#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /!< EADC_T::STATUS0: VALID Mask /
kadonotakashi	0:8fdf9a60065b	1553
kadonotakashi	0:8fdf9a60065b	1554	#define EADC_STATUS0_OV_Pos (16) /!< EADC_T::STATUS0: OV Position /
kadonotakashi	0:8fdf9a60065b	1555	#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /!< EADC_T::STATUS0: OV Mask /
kadonotakashi	0:8fdf9a60065b	1556
kadonotakashi	0:8fdf9a60065b	1557	#define EADC_STATUS1_VALID_Pos (0) /!< EADC_T::STATUS1: VALID Position /
kadonotakashi	0:8fdf9a60065b	1558	#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /!< EADC_T::STATUS1: VALID Mask /
kadonotakashi	0:8fdf9a60065b	1559
kadonotakashi	0:8fdf9a60065b	1560	#define EADC_STATUS1_OV_Pos (16) /!< EADC_T::STATUS1: OV Position /
kadonotakashi	0:8fdf9a60065b	1561	#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /!< EADC_T::STATUS1: OV Mask /
kadonotakashi	0:8fdf9a60065b	1562
kadonotakashi	0:8fdf9a60065b	1563	#define EADC_STATUS2_ADIF0_Pos (0) /!< EADC_T::STATUS2: ADIF0 Position /
kadonotakashi	0:8fdf9a60065b	1564	#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /!< EADC_T::STATUS2: ADIF0 Mask /
kadonotakashi	0:8fdf9a60065b	1565
kadonotakashi	0:8fdf9a60065b	1566	#define EADC_STATUS2_ADIF1_Pos (1) /!< EADC_T::STATUS2: ADIF1 Position /
kadonotakashi	0:8fdf9a60065b	1567	#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /!< EADC_T::STATUS2: ADIF1 Mask /
kadonotakashi	0:8fdf9a60065b	1568
kadonotakashi	0:8fdf9a60065b	1569	#define EADC_STATUS2_ADIF2_Pos (2) /!< EADC_T::STATUS2: ADIF2 Position /
kadonotakashi	0:8fdf9a60065b	1570	#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /!< EADC_T::STATUS2: ADIF2 Mask /
kadonotakashi	0:8fdf9a60065b	1571
kadonotakashi	0:8fdf9a60065b	1572	#define EADC_STATUS2_ADIF3_Pos (3) /!< EADC_T::STATUS2: ADIF3 Position /
kadonotakashi	0:8fdf9a60065b	1573	#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /!< EADC_T::STATUS2: ADIF3 Mask /
kadonotakashi	0:8fdf9a60065b	1574
kadonotakashi	0:8fdf9a60065b	1575	#define EADC_STATUS2_ADCMPF0_Pos (4) /!< EADC_T::STATUS2: ADCMPF0 Position /
kadonotakashi	0:8fdf9a60065b	1576	#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /!< EADC_T::STATUS2: ADCMPF0 Mask /
kadonotakashi	0:8fdf9a60065b	1577
kadonotakashi	0:8fdf9a60065b	1578	#define EADC_STATUS2_ADCMPF1_Pos (5) /!< EADC_T::STATUS2: ADCMPF1 Position /
kadonotakashi	0:8fdf9a60065b	1579	#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /!< EADC_T::STATUS2: ADCMPF1 Mask /
kadonotakashi	0:8fdf9a60065b	1580
kadonotakashi	0:8fdf9a60065b	1581	#define EADC_STATUS2_ADCMPF2_Pos (6) /!< EADC_T::STATUS2: ADCMPF2 Position /
kadonotakashi	0:8fdf9a60065b	1582	#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /!< EADC_T::STATUS2: ADCMPF2 Mask /
kadonotakashi	0:8fdf9a60065b	1583
kadonotakashi	0:8fdf9a60065b	1584	#define EADC_STATUS2_ADCMPF3_Pos (7) /!< EADC_T::STATUS2: ADCMPF3 Position /
kadonotakashi	0:8fdf9a60065b	1585	#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /!< EADC_T::STATUS2: ADCMPF3 Mask /
kadonotakashi	0:8fdf9a60065b	1586
kadonotakashi	0:8fdf9a60065b	1587	#define EADC_STATUS2_ADOVIF0_Pos (8) /!< EADC_T::STATUS2: ADOVIF0 Position /
kadonotakashi	0:8fdf9a60065b	1588	#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /!< EADC_T::STATUS2: ADOVIF0 Mask /
kadonotakashi	0:8fdf9a60065b	1589
kadonotakashi	0:8fdf9a60065b	1590	#define EADC_STATUS2_ADOVIF1_Pos (9) /!< EADC_T::STATUS2: ADOVIF1 Position /
kadonotakashi	0:8fdf9a60065b	1591	#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /!< EADC_T::STATUS2: ADOVIF1 Mask /
kadonotakashi	0:8fdf9a60065b	1592
kadonotakashi	0:8fdf9a60065b	1593	#define EADC_STATUS2_ADOVIF2_Pos (10) /!< EADC_T::STATUS2: ADOVIF2 Position /
kadonotakashi	0:8fdf9a60065b	1594	#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /!< EADC_T::STATUS2: ADOVIF2 Mask /
kadonotakashi	0:8fdf9a60065b	1595
kadonotakashi	0:8fdf9a60065b	1596	#define EADC_STATUS2_ADOVIF3_Pos (11) /!< EADC_T::STATUS2: ADOVIF3 Position /
kadonotakashi	0:8fdf9a60065b	1597	#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /!< EADC_T::STATUS2: ADOVIF3 Mask /
kadonotakashi	0:8fdf9a60065b	1598
kadonotakashi	0:8fdf9a60065b	1599	#define EADC_STATUS2_ADCMPO0_Pos (12) /!< EADC_T::STATUS2: ADCMPO0 Position /
kadonotakashi	0:8fdf9a60065b	1600	#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /!< EADC_T::STATUS2: ADCMPO0 Mask /
kadonotakashi	0:8fdf9a60065b	1601
kadonotakashi	0:8fdf9a60065b	1602	#define EADC_STATUS2_ADCMPO1_Pos (13) /!< EADC_T::STATUS2: ADCMPO1 Position /
kadonotakashi	0:8fdf9a60065b	1603	#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /!< EADC_T::STATUS2: ADCMPO1 Mask /
kadonotakashi	0:8fdf9a60065b	1604
kadonotakashi	0:8fdf9a60065b	1605	#define EADC_STATUS2_ADCMPO2_Pos (14) /!< EADC_T::STATUS2: ADCMPO2 Position /
kadonotakashi	0:8fdf9a60065b	1606	#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /!< EADC_T::STATUS2: ADCMPO2 Mask /
kadonotakashi	0:8fdf9a60065b	1607
kadonotakashi	0:8fdf9a60065b	1608	#define EADC_STATUS2_ADCMPO3_Pos (15) /!< EADC_T::STATUS2: ADCMPO3 Position /
kadonotakashi	0:8fdf9a60065b	1609	#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /!< EADC_T::STATUS2: ADCMPO3 Mask /
kadonotakashi	0:8fdf9a60065b	1610
kadonotakashi	0:8fdf9a60065b	1611	#define EADC_STATUS2_CHANNEL_Pos (16) /!< EADC_T::STATUS2: CHANNEL Position /
kadonotakashi	0:8fdf9a60065b	1612	#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /!< EADC_T::STATUS2: CHANNEL Mask /
kadonotakashi	0:8fdf9a60065b	1613
kadonotakashi	0:8fdf9a60065b	1614	#define EADC_STATUS2_BUSY_Pos (23) /!< EADC_T::STATUS2: BUSY Position /
kadonotakashi	0:8fdf9a60065b	1615	#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /!< EADC_T::STATUS2: BUSY Mask /
kadonotakashi	0:8fdf9a60065b	1616
kadonotakashi	0:8fdf9a60065b	1617	#define EADC_STATUS2_ADOVIF_Pos (24) /!< EADC_T::STATUS2: ADOVIF Position /
kadonotakashi	0:8fdf9a60065b	1618	#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /!< EADC_T::STATUS2: ADOVIF Mask /
kadonotakashi	0:8fdf9a60065b	1619
kadonotakashi	0:8fdf9a60065b	1620	#define EADC_STATUS2_STOVF_Pos (25) /!< EADC_T::STATUS2: STOVF Position /
kadonotakashi	0:8fdf9a60065b	1621	#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /!< EADC_T::STATUS2: STOVF Mask /
kadonotakashi	0:8fdf9a60065b	1622
kadonotakashi	0:8fdf9a60065b	1623	#define EADC_STATUS2_AVALID_Pos (26) /!< EADC_T::STATUS2: AVALID Position /
kadonotakashi	0:8fdf9a60065b	1624	#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /!< EADC_T::STATUS2: AVALID Mask /
kadonotakashi	0:8fdf9a60065b	1625
kadonotakashi	0:8fdf9a60065b	1626	#define EADC_STATUS2_AOV_Pos (27) /!< EADC_T::STATUS2: AOV Position /
kadonotakashi	0:8fdf9a60065b	1627	#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /!< EADC_T::STATUS2: AOV Mask /
kadonotakashi	0:8fdf9a60065b	1628
kadonotakashi	0:8fdf9a60065b	1629	#define EADC_STATUS3_CURSPL_Pos (0) /!< EADC_T::STATUS3: CURSPL Position /
kadonotakashi	0:8fdf9a60065b	1630	#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /!< EADC_T::STATUS3: CURSPL Mask /
kadonotakashi	0:8fdf9a60065b	1631
kadonotakashi	0:8fdf9a60065b	1632	#define EADC_DDAT0_RESULT_Pos (0) /!< EADC_T::DDAT0: RESULT Position /
kadonotakashi	0:8fdf9a60065b	1633	#define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /!< EADC_T::DDAT0: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	1634
kadonotakashi	0:8fdf9a60065b	1635	#define EADC_DDAT0_OV_Pos (16) /!< EADC_T::DDAT0: OV Position /
kadonotakashi	0:8fdf9a60065b	1636	#define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /!< EADC_T::DDAT0: OV Mask /
kadonotakashi	0:8fdf9a60065b	1637
kadonotakashi	0:8fdf9a60065b	1638	#define EADC_DDAT0_VALID_Pos (17) /!< EADC_T::DDAT0: VALID Position /
kadonotakashi	0:8fdf9a60065b	1639	#define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /!< EADC_T::DDAT0: VALID Mask /
kadonotakashi	0:8fdf9a60065b	1640
kadonotakashi	0:8fdf9a60065b	1641	#define EADC_DDAT1_RESULT_Pos (0) /!< EADC_T::DDAT1: RESULT Position /
kadonotakashi	0:8fdf9a60065b	1642	#define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /!< EADC_T::DDAT1: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	1643
kadonotakashi	0:8fdf9a60065b	1644	#define EADC_DDAT1_OV_Pos (16) /!< EADC_T::DDAT1: OV Position /
kadonotakashi	0:8fdf9a60065b	1645	#define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /!< EADC_T::DDAT1: OV Mask /
kadonotakashi	0:8fdf9a60065b	1646
kadonotakashi	0:8fdf9a60065b	1647	#define EADC_DDAT1_VALID_Pos (17) /!< EADC_T::DDAT1: VALID Position /
kadonotakashi	0:8fdf9a60065b	1648	#define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /!< EADC_T::DDAT1: VALID Mask /
kadonotakashi	0:8fdf9a60065b	1649
kadonotakashi	0:8fdf9a60065b	1650	#define EADC_DDAT2_RESULT_Pos (0) /!< EADC_T::DDAT2: RESULT Position /
kadonotakashi	0:8fdf9a60065b	1651	#define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /!< EADC_T::DDAT2: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	1652
kadonotakashi	0:8fdf9a60065b	1653	#define EADC_DDAT2_OV_Pos (16) /!< EADC_T::DDAT2: OV Position /
kadonotakashi	0:8fdf9a60065b	1654	#define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /!< EADC_T::DDAT2: OV Mask /
kadonotakashi	0:8fdf9a60065b	1655
kadonotakashi	0:8fdf9a60065b	1656	#define EADC_DDAT2_VALID_Pos (17) /!< EADC_T::DDAT2: VALID Position /
kadonotakashi	0:8fdf9a60065b	1657	#define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /!< EADC_T::DDAT2: VALID Mask /
kadonotakashi	0:8fdf9a60065b	1658
kadonotakashi	0:8fdf9a60065b	1659	#define EADC_DDAT3_RESULT_Pos (0) /!< EADC_T::DDAT3: RESULT Position /
kadonotakashi	0:8fdf9a60065b	1660	#define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /!< EADC_T::DDAT3: RESULT Mask /
kadonotakashi	0:8fdf9a60065b	1661
kadonotakashi	0:8fdf9a60065b	1662	#define EADC_DDAT3_OV_Pos (16) /!< EADC_T::DDAT3: OV Position /
kadonotakashi	0:8fdf9a60065b	1663	#define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /!< EADC_T::DDAT3: OV Mask /
kadonotakashi	0:8fdf9a60065b	1664
kadonotakashi	0:8fdf9a60065b	1665	#define EADC_DDAT3_VALID_Pos (17) /!< EADC_T::DDAT3: VALID Position /
kadonotakashi	0:8fdf9a60065b	1666	#define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /!< EADC_T::DDAT3: VALID Mask /
kadonotakashi	0:8fdf9a60065b	1667
kadonotakashi	0:8fdf9a60065b	1668	#define EADC_PWRM_PWUPRDY_Pos (0) /!< EADC_T::PWRM: PWUPRDY Position /
kadonotakashi	0:8fdf9a60065b	1669	#define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /!< EADC_T::PWRM: PWUPRDY Mask /
kadonotakashi	0:8fdf9a60065b	1670
kadonotakashi	0:8fdf9a60065b	1671	#define EADC_PWRM_PWUCALEN_Pos (1) /!< EADC_T::PWRM: PWUCALEN Position /
kadonotakashi	0:8fdf9a60065b	1672	#define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /!< EADC_T::PWRM: PWUCALEN Mask /
kadonotakashi	0:8fdf9a60065b	1673
kadonotakashi	0:8fdf9a60065b	1674	#define EADC_PWRM_PWDMOD_Pos (2) /!< EADC_T::PWRM: PWDMOD Position /
kadonotakashi	0:8fdf9a60065b	1675	#define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /!< EADC_T::PWRM: PWDMOD Mask /
kadonotakashi	0:8fdf9a60065b	1676
kadonotakashi	0:8fdf9a60065b	1677	#define EADC_PWRM_LDOSUT_Pos (8) /!< EADC_T::PWRM: LDOSUT Position /
kadonotakashi	0:8fdf9a60065b	1678	#define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) /!< EADC_T::PWRM: LDOSUT Mask /
kadonotakashi	0:8fdf9a60065b	1679
kadonotakashi	0:8fdf9a60065b	1680	#define EADC_CALCTL_CALSTART_Pos (1) /!< EADC_T::CALCTL: CALSTART Position /
kadonotakashi	0:8fdf9a60065b	1681	#define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /!< EADC_T::CALCTL: CALSTART Mask /
kadonotakashi	0:8fdf9a60065b	1682
kadonotakashi	0:8fdf9a60065b	1683	#define EADC_CALCTL_CALDONE_Pos (2) /!< EADC_T::CALCTL: CALDONE Position /
kadonotakashi	0:8fdf9a60065b	1684	#define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /!< EADC_T::CALCTL: CALDONE Mask /
kadonotakashi	0:8fdf9a60065b	1685
kadonotakashi	0:8fdf9a60065b	1686	#define EADC_CALCTL_CALSEL_Pos (3) /!< EADC_T::CALCTL: CALSEL Position /
kadonotakashi	0:8fdf9a60065b	1687	#define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /!< EADC_T::CALCTL: CALSEL Mask /
kadonotakashi	0:8fdf9a60065b	1688
kadonotakashi	0:8fdf9a60065b	1689	#define EADC_CALDWRD_CALWORD_Pos (0) /!< EADC_T::CALDWRD: CALWORD Position /
kadonotakashi	0:8fdf9a60065b	1690	#define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) /!< EADC_T::CALDWRD: CALWORD Mask /
kadonotakashi	0:8fdf9a60065b	1691
kadonotakashi	0:8fdf9a60065b	1692	/*@}/ /* EADC_CONST */
kadonotakashi	0:8fdf9a60065b	1693	/*@}/ /* end of EADC register group */
kadonotakashi	0:8fdf9a60065b	1694
kadonotakashi	0:8fdf9a60065b	1695
kadonotakashi	0:8fdf9a60065b	1696
kadonotakashi	0:8fdf9a60065b	1697	#endif /* __EADC_REG_H__ */

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Type:	Program
Mbed OS support:	Mbed OS
Created:	11 Oct 2018
Imports:	15
Forks:	0
Commits:	4
Dependents:	0
Dependencies:	1
Followers:	1

mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/eadc_reg.h@3:f3764f852aa8, 2018-10-11 (annotated)

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