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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/clk_reg.h@3:f3764f852aa8, 2018-10-11 (annotated)
- Committer:
- kadonotakashi
- Date:
- Thu Oct 11 02:27:46 2018 +0000
- Revision:
- 3:f3764f852aa8
- Parent:
- 0:8fdf9a60065b
Nucreo 446 + SSD1331 test version;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
kadonotakashi | 0:8fdf9a60065b | 2 | * @file clk_reg.h |
kadonotakashi | 0:8fdf9a60065b | 3 | * @version V1.00 |
kadonotakashi | 0:8fdf9a60065b | 4 | * @brief CLK register definition header file |
kadonotakashi | 0:8fdf9a60065b | 5 | * |
kadonotakashi | 0:8fdf9a60065b | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 7 | *****************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 8 | #ifndef __CLK_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 9 | #define __CLK_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 10 | |
kadonotakashi | 0:8fdf9a60065b | 11 | /*---------------------- System Clock Controller -------------------------*/ |
kadonotakashi | 0:8fdf9a60065b | 12 | /** |
kadonotakashi | 0:8fdf9a60065b | 13 | @addtogroup CLK System Clock Controller(CLK) |
kadonotakashi | 0:8fdf9a60065b | 14 | Memory Mapped Structure for CLK Controller |
kadonotakashi | 0:8fdf9a60065b | 15 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 16 | |
kadonotakashi | 0:8fdf9a60065b | 17 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 18 | { |
kadonotakashi | 0:8fdf9a60065b | 19 | |
kadonotakashi | 0:8fdf9a60065b | 20 | /** |
kadonotakashi | 0:8fdf9a60065b | 21 | * @var CLK_T::PWRCTL |
kadonotakashi | 0:8fdf9a60065b | 22 | * Offset: 0x00 System Power-down Control Register |
kadonotakashi | 0:8fdf9a60065b | 23 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 24 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 25 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 26 | * |[0] |HXTEN |HXT Enable Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 27 | * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. |
kadonotakashi | 0:8fdf9a60065b | 28 | * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. |
kadonotakashi | 0:8fdf9a60065b | 29 | * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 30 | * | | |Note2: HXT cannot be disabled and HXTEN will always read as 1 if HCLK clock source is selected from HXT or PLL (clock source from HXT). |
kadonotakashi | 0:8fdf9a60065b | 31 | * |[1] |LXTEN |LXT Enable Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 32 | * | | |0 = 32.768 kHz external low speed crystal (extLXT) Disabled. |
kadonotakashi | 0:8fdf9a60065b | 33 | * | | |1 = 32.768 kHz external low speed crystal (extLXT) Enabled. |
kadonotakashi | 0:8fdf9a60065b | 34 | * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 35 | * | | |Note2: LXT cannot be disabled and LXTEN will always read as 1 if HCLK clock source is selected from LXT when the LXT clock source is selected as extLXT by setting C32KS(RTC_LXTCTL[7]) to 1. |
kadonotakashi | 0:8fdf9a60065b | 36 | * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 37 | * | | |The HCLK default clock source is from HIRC and this bit default value is 1. |
kadonotakashi | 0:8fdf9a60065b | 38 | * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. |
kadonotakashi | 0:8fdf9a60065b | 39 | * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. |
kadonotakashi | 0:8fdf9a60065b | 40 | * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 41 | * | | |Note2: HIRC cannot be disabled and HIRCEN will always read as 1 if Flash access cycle auto-tuning function is enabled or HCLK clock source is selected from HIRC or PLL (clock source from HIRC). |
kadonotakashi | 0:8fdf9a60065b | 42 | * | | |Flash access cycle auto-tuning function can be disabled by setting FADIS (FMC_CYCCTL[8]). |
kadonotakashi | 0:8fdf9a60065b | 43 | * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 44 | * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. |
kadonotakashi | 0:8fdf9a60065b | 45 | * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. |
kadonotakashi | 0:8fdf9a60065b | 46 | * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 47 | * | | |Note2: LIRC cannot be disabled and LIRCEN will always read as 1 if HCLK clock source is selected from LIRC. |
kadonotakashi | 0:8fdf9a60065b | 48 | * | | |Note3: If CWDTEN(CONFIG[31,4:3]) is set to 111, LIRC clock can be enabled or disabled by setting LIRCEN(CLK_PWRCTL[3]). |
kadonotakashi | 0:8fdf9a60065b | 49 | * | | |If CWDTEN([31,4:3]) is not set to 111, LIRC cannot be disabled in normal mode and LIRCEN will always read as 1 |
kadonotakashi | 0:8fdf9a60065b | 50 | * | | |In Power-down mode, LIRC clock is control by LIRCEN(CLK_PWRCTL[3]) and CWDTPDEN (CONFIG[30]) setting. |
kadonotakashi | 0:8fdf9a60065b | 51 | * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 52 | * | | |0 = Power-down mode wake-up interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 53 | * | | |1 = Power-down mode wake-up interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 54 | * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high, after resume from power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 55 | * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 56 | * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status |
kadonotakashi | 0:8fdf9a60065b | 57 | * | | |Set by Power-down wake-up event, it indicates that resume from Power-down mode |
kadonotakashi | 0:8fdf9a60065b | 58 | * | | |The flag is set if the EINT7~0, GPIO, UART0~5, USBH, USBD, OTG, CAN0, BOD, ACMP, WDT, SDH0, TMR0~3, I2C0~2, USCI0~1, SPI5, DSRC, RTC wake-up occurred. |
kadonotakashi | 0:8fdf9a60065b | 59 | * | | |Note1: Write 1 to clear the bit to 0. |
kadonotakashi | 0:8fdf9a60065b | 60 | * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. |
kadonotakashi | 0:8fdf9a60065b | 61 | * |[7] |PDEN |System Power-down Enable (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 62 | * | | |When this bit is set to 1, Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 63 | * | | |When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. |
kadonotakashi | 0:8fdf9a60065b | 64 | * | | |In Power-down mode, HXT, HIRC, HIRC48, PLL and system clock will be disabled and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. |
kadonotakashi | 0:8fdf9a60065b | 65 | * | | |0 = Chip operating normally or chip in idle mode because of WFI command. |
kadonotakashi | 0:8fdf9a60065b | 66 | * | | |1 = Chip waits CPU sleep command WFI and then enters Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 67 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 68 | * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 69 | * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally. |
kadonotakashi | 0:8fdf9a60065b | 70 | * | | |If gain control is enabled, crystal will consume more power than gain control off. |
kadonotakashi | 0:8fdf9a60065b | 71 | * | | |00 = HXT frequency is lower than from 8 MHz. |
kadonotakashi | 0:8fdf9a60065b | 72 | * | | |01 = HXT frequency is from 8 MHz to 12 MHz. |
kadonotakashi | 0:8fdf9a60065b | 73 | * | | |10 = HXT frequency is from 12 MHz to 16 MHz. |
kadonotakashi | 0:8fdf9a60065b | 74 | * | | |11 = HXT frequency is higher than 16 MHz. |
kadonotakashi | 0:8fdf9a60065b | 75 | * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 76 | * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 77 | * | | |0 = Select INV type. |
kadonotakashi | 0:8fdf9a60065b | 78 | * | | |1 = Select GM type. |
kadonotakashi | 0:8fdf9a60065b | 79 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 80 | * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 81 | * | | |0 = HXT Crystal TURBO mode disabled. |
kadonotakashi | 0:8fdf9a60065b | 82 | * | | |1 = HXT Crystal TURBO mode enabled. |
kadonotakashi | 0:8fdf9a60065b | 83 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 84 | * |[18] |HIRC48EN |HIRC48 Enable Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 85 | * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48) Disabled. |
kadonotakashi | 0:8fdf9a60065b | 86 | * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48) Enabled. |
kadonotakashi | 0:8fdf9a60065b | 87 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 88 | * @var CLK_T::AHBCLK |
kadonotakashi | 0:8fdf9a60065b | 89 | * Offset: 0x04 AHB Devices Clock Enable Control Register |
kadonotakashi | 0:8fdf9a60065b | 90 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 91 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 92 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 93 | * |[0] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit (Secure) |
kadonotakashi | 0:8fdf9a60065b | 94 | * | | |0 = PDMA peripheral clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 95 | * | | |1 = PDMA peripheral clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 96 | * |[1] |PDMA1CKEN |PDMA1 Controller Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 97 | * | | |0 = PDMA peripheral clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 98 | * | | |1 = PDMA peripheral clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 99 | * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 100 | * | | |0 = Flash ISP peripheral clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 101 | * | | |1 = Flash ISP peripheral clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 102 | * |[3] |EBICKEN |EBI Controller Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 103 | * | | |0 = EBI peripheral clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 104 | * | | |1 = EBI peripheral clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 105 | * |[6] |SDH0CKEN |SDHOST0 Controller Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 106 | * | | |0 = SDHOST0 peripheral clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 107 | * | | |1 = SDHOST0 peripheral clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 108 | * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 109 | * | | |0 = CRC peripheral clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 110 | * | | |1 = CRC peripheral clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 111 | * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 112 | * | | |0 = Cryptographic Accelerator clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 113 | * | | |1 = Cryptographic Accelerator clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 114 | * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode |
kadonotakashi | 0:8fdf9a60065b | 115 | * | | |0 = FMC clock Disabled when chip is under IDLE mode. |
kadonotakashi | 0:8fdf9a60065b | 116 | * | | |1 = FMC clock Enabled when chip is under IDLE mode. |
kadonotakashi | 0:8fdf9a60065b | 117 | * |[16] |USBHCKEN |USB HOST 1.1 Controller Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 118 | * | | |0 = USB HOST 1.1 peripheral clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 119 | * | | |1 = USB HOST 1.1 peripheral clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 120 | * @var CLK_T::APBCLK0 |
kadonotakashi | 0:8fdf9a60065b | 121 | * Offset: 0x08 APB Devices Clock Enable Control Register 0 |
kadonotakashi | 0:8fdf9a60065b | 122 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 123 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 124 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 125 | * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 126 | * | | |0 = Watchdog timer clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 127 | * | | |1 = Watchdog timer clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 128 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 129 | * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 130 | * | | |This bit is used to control the RTC APB clock only |
kadonotakashi | 0:8fdf9a60065b | 131 | * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]) |
kadonotakashi | 0:8fdf9a60065b | 132 | * | | |It can be selected to 32.768 kHz external low speed crystal (LXT) or 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 133 | * | | |0 = RTC clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 134 | * | | |1 = RTC clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 135 | * |[2] |TMR0CKEN |Timer0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 136 | * | | |0 = Timer0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 137 | * | | |1 = Timer0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 138 | * |[3] |TMR1CKEN |Timer1 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 139 | * | | |0 = Timer1 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 140 | * | | |1 = Timer1 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 141 | * |[4] |TMR2CKEN |Timer2 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 142 | * | | |0 = Timer2 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 143 | * | | |1 = Timer2 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 144 | * |[5] |TMR3CKEN |Timer3 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 145 | * | | |0 = Timer3 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 146 | * | | |1 = Timer3 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 147 | * |[6] |CLKOCKEN |CLKO Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 148 | * | | |0 = CLKO clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 149 | * | | |1 = CLKO clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 150 | * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 151 | * | | |0 = Analog comparator 0/1 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 152 | * | | |1 = Analog comparator 0/1 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 153 | * |[8] |I2C0CKEN |I2C0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 154 | * | | |0 = I2C0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 155 | * | | |1 = I2C0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 156 | * |[9] |I2C1CKEN |I2C1 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 157 | * | | |0 = I2C1 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 158 | * | | |1 = I2C1 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 159 | * |[10] |I2C2CKEN |I2C2 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 160 | * | | |0 = I2C2 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 161 | * | | |1 = I2C2 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 162 | * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 163 | * | | |0 = QSPI0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 164 | * | | |1 = QSPI0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 165 | * |[13] |SPI0CKEN |SPI0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 166 | * | | |0 = SPI0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 167 | * | | |1 = SPI0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 168 | * |[14] |SPI1CKEN |SPI1 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 169 | * | | |0 = SPI1 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 170 | * | | |1 = SPI1 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 171 | * |[15] |SPI2CKEN |SPI2 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 172 | * | | |0 = SPI2 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 173 | * | | |1 = SPI2 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 174 | * |[16] |UART0CKEN |UART0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 175 | * | | |0 = UART0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 176 | * | | |1 = UART0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 177 | * |[17] |UART1CKEN |UART1 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 178 | * | | |0 = UART1 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 179 | * | | |1 = UART1 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 180 | * |[18] |UART2CKEN |UART2 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 181 | * | | |0 = UART2 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 182 | * | | |1 = UART2 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 183 | * |[19] |UART3CKEN |UART3 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 184 | * | | |0 = UART3 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 185 | * | | |1 = UART3 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 186 | * |[20] |UART4CKEN |UART4 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 187 | * | | |0 = UART4 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 188 | * | | |1 = UART4 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 189 | * |[21] |UART5CKEN |UART5 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 190 | * | | |0 = UART5 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 191 | * | | |1 = UART5 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 192 | * |[23] |DSRCCKEN |DSRC Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 193 | * | | |0 = DSRC clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 194 | * | | |1 = DSRC clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 195 | * |[24] |CAN0CKEN |CAN0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 196 | * | | |0 = CAN0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 197 | * | | |1 = CAN0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 198 | * |[26] |OTGCKEN |USB OTG Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 199 | * | | |0 = USB OTG clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 200 | * | | |1 = USB OTG clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 201 | * |[27] |USBDCKEN |USB Device Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 202 | * | | |0 = USB Device clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 203 | * | | |1 = USB Device clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 204 | * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 205 | * | | |0 = EADC clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 206 | * | | |1 = EADC clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 207 | * |[29] |I2S0CKEN |I2S0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 208 | * | | |0 = I2S0 Clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 209 | * | | |1 = I2S0 Clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 210 | * @var CLK_T::APBCLK1 |
kadonotakashi | 0:8fdf9a60065b | 211 | * Offset: 0x0C APB Devices Clock Enable Control Register 1 |
kadonotakashi | 0:8fdf9a60065b | 212 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 213 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 214 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 215 | * |[0] |SC0CKEN |Smart Card 0 (SC0) Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 216 | * | | |0 = SC0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 217 | * | | |1 = SC0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 218 | * |[1] |SC1CKEN |Smart Card 1 (SC1) Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 219 | * | | |0 = SC1 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 220 | * | | |1 = SC1 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 221 | * |[2] |SC2CKEN |Smart Card 2 (SC2) Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 222 | * | | |0 = SC2 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 223 | * | | |1 = SC2 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 224 | * |[6] |SPI3CKEN |SPI3 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 225 | * | | |0 = SPI3 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 226 | * | | |1 = SPI3 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 227 | * |[7] |SPI5CKEN |SPI5 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 228 | * | | |0 = SPI5 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 229 | * | | |1 = SPI5 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 230 | * |[8] |USCI0CKEN |USCI0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 231 | * | | |0 = USCI0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 232 | * | | |1 = USCI0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 233 | * |[9] |USCI1CKEN |USCI1 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 234 | * | | |0 = USCI1 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 235 | * | | |1 = USCI1 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 236 | * |[12] |DACCKEN |DAC Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 237 | * | | |0 = DAC clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 238 | * | | |1 = DAC clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 239 | * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 240 | * | | |0 = PWM0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 241 | * | | |1 = PWM0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 242 | * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 243 | * | | |0 = PWM1 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 244 | * | | |1 = PWM1 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 245 | * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 246 | * | | |0 = BPWM0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 247 | * | | |1 = BPWM0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 248 | * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 249 | * | | |0 = BPWM1 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 250 | * | | |1 = BPWM1 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 251 | * |[22] |QEI0CKEN |QEI0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 252 | * | | |0 = QEI0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 253 | * | | |1 = QEI0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 254 | * |[23] |QEI1CKEN |QEI1 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 255 | * | | |0 = QEI1 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 256 | * | | |1 = QEI1 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 257 | * |[25] |TRNGCKEN |TRNG Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 258 | * | | |0 = TRNG clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 259 | * | | |1 = TRNG clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 260 | * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 261 | * | | |0 = ECAP0 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 262 | * | | |1 = ECAP0 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 263 | * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 264 | * | | |0 = ECAP1 clock Disabled. |
kadonotakashi | 0:8fdf9a60065b | 265 | * | | |1 = ECAP1 clock Enabled. |
kadonotakashi | 0:8fdf9a60065b | 266 | * @var CLK_T::CLKSEL0 |
kadonotakashi | 0:8fdf9a60065b | 267 | * Offset: 0x10 Clock Source Select Control Register 0 |
kadonotakashi | 0:8fdf9a60065b | 268 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 269 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 270 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 271 | * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 272 | * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. |
kadonotakashi | 0:8fdf9a60065b | 273 | * | | |000 = Clock source from HXT. |
kadonotakashi | 0:8fdf9a60065b | 274 | * | | |001 = Clock source from LXT. |
kadonotakashi | 0:8fdf9a60065b | 275 | * | | |010 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 276 | * | | |011 = Clock source from LIRC. |
kadonotakashi | 0:8fdf9a60065b | 277 | * | | |100 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 278 | * | | |101 = Clock source from HIRC48. |
kadonotakashi | 0:8fdf9a60065b | 279 | * | | |111 = Clock source from HIRC. |
kadonotakashi | 0:8fdf9a60065b | 280 | * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 281 | * |[5:3] |STCLKSEL |SysTick Clock Source Selection (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 282 | * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. |
kadonotakashi | 0:8fdf9a60065b | 283 | * | | |000 = Clock source from HXT. |
kadonotakashi | 0:8fdf9a60065b | 284 | * | | |001 = Clock source from LXT. |
kadonotakashi | 0:8fdf9a60065b | 285 | * | | |010 = Clock source from HXT/2. |
kadonotakashi | 0:8fdf9a60065b | 286 | * | | |011 = Clock source from HCLK/2. |
kadonotakashi | 0:8fdf9a60065b | 287 | * | | |111 = Clock source from HIRC/2. |
kadonotakashi | 0:8fdf9a60065b | 288 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 289 | * | | |Note1: if SysTick clock source is not from HCLK (i.e |
kadonotakashi | 0:8fdf9a60065b | 290 | * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2. |
kadonotakashi | 0:8fdf9a60065b | 291 | * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 292 | * |[8] |USBSEL |USB Clock Source Selection (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 293 | * | | |0 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 294 | * | | |1 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 295 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 296 | * |[21:20] |SDH0SEL |SDHOST0 Peripheral Clock Source Selection (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 297 | * | | |00 = Clock source from HXT clock. |
kadonotakashi | 0:8fdf9a60065b | 298 | * | | |01 = Clock source from PLL clock. |
kadonotakashi | 0:8fdf9a60065b | 299 | * | | |10 = Clock source from HCLK. |
kadonotakashi | 0:8fdf9a60065b | 300 | * | | |11 = Clock source from HIRC clock. |
kadonotakashi | 0:8fdf9a60065b | 301 | * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 302 | * @var CLK_T::CLKSEL1 |
kadonotakashi | 0:8fdf9a60065b | 303 | * Offset: 0x14 Clock Source Select Control Register 1 |
kadonotakashi | 0:8fdf9a60065b | 304 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 305 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 306 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 307 | * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 308 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 309 | * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 310 | * | | |10 = Clock source from HCLK/2048. |
kadonotakashi | 0:8fdf9a60065b | 311 | * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 312 | * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 313 | * |[3] |DSRCSEL |DSRC Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 314 | * | | |0 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 315 | * | | |1 = Clock source from HIRC. |
kadonotakashi | 0:8fdf9a60065b | 316 | * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 317 | * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 318 | * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 319 | * | | |010 = Clock source from PCLK0. |
kadonotakashi | 0:8fdf9a60065b | 320 | * | | |011 = Clock source from external clock TM0 pin. |
kadonotakashi | 0:8fdf9a60065b | 321 | * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 322 | * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 323 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 324 | * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 325 | * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 326 | * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 327 | * | | |010 = Clock source from PCLK0. |
kadonotakashi | 0:8fdf9a60065b | 328 | * | | |011 = Clock source from external clock TM1 pin. |
kadonotakashi | 0:8fdf9a60065b | 329 | * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 330 | * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 331 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 332 | * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 333 | * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 334 | * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 335 | * | | |010 = Clock source from PCLK1. |
kadonotakashi | 0:8fdf9a60065b | 336 | * | | |011 = Clock source from external clock TM2 pin. |
kadonotakashi | 0:8fdf9a60065b | 337 | * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 338 | * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 339 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 340 | * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 341 | * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 342 | * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 343 | * | | |010 = Clock source from PCLK1. |
kadonotakashi | 0:8fdf9a60065b | 344 | * | | |011 = Clock source from external clock TM3 pin. |
kadonotakashi | 0:8fdf9a60065b | 345 | * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 346 | * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 347 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 348 | * |[25:24] |UART0SEL |UART0 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 349 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 350 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 351 | * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 352 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 353 | * |[27:26] |UART1SEL |UART1 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 354 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 355 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 356 | * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 357 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 358 | * |[29:28] |CLKOSEL |Clock Output Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 359 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 360 | * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 361 | * | | |10 = Clock source from HCLK. |
kadonotakashi | 0:8fdf9a60065b | 362 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 363 | * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 364 | * | | |10 = Clock source from HCLK/2048. |
kadonotakashi | 0:8fdf9a60065b | 365 | * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 366 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 367 | * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 368 | * @var CLK_T::CLKSEL2 |
kadonotakashi | 0:8fdf9a60065b | 369 | * Offset: 0x18 Clock Source Select Control Register 2 |
kadonotakashi | 0:8fdf9a60065b | 370 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 371 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 372 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 373 | * |[0] |EPWM0SEL |EPWM0 Clock Source Selection (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 374 | * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. |
kadonotakashi | 0:8fdf9a60065b | 375 | * | | |1 = Clock source from PCLK0. |
kadonotakashi | 0:8fdf9a60065b | 376 | * |[1] |EPWM1SEL |EPWM1 Clock Source Selection (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 377 | * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. |
kadonotakashi | 0:8fdf9a60065b | 378 | * | | |1 = Clock source from PCLK1. |
kadonotakashi | 0:8fdf9a60065b | 379 | * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 380 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 381 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 382 | * | | |10 = Clock source from PCLK0. |
kadonotakashi | 0:8fdf9a60065b | 383 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 384 | * |[5:4] |SPI0SEL |SPI0 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 385 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 386 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 387 | * | | |10 = Clock source from PCLK1. |
kadonotakashi | 0:8fdf9a60065b | 388 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 389 | * |[7:6] |SPI1SEL |SPI1 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 390 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 391 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 392 | * | | |10 = Clock source from PCLK0. |
kadonotakashi | 0:8fdf9a60065b | 393 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 394 | * |[8] |BPWM0SEL |BPWM0 Clock Source Selection (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 395 | * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. |
kadonotakashi | 0:8fdf9a60065b | 396 | * | | |1 = Clock source from PCLK0. |
kadonotakashi | 0:8fdf9a60065b | 397 | * |[9] |BPWM1SEL |BPWM1 Clock Source Selection (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 398 | * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. |
kadonotakashi | 0:8fdf9a60065b | 399 | * | | |1 = Clock source from PCLK1. |
kadonotakashi | 0:8fdf9a60065b | 400 | * |[11:10] |SPI2SEL |SPI2 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 401 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 402 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 403 | * | | |10 = Clock source from PCLK1. |
kadonotakashi | 0:8fdf9a60065b | 404 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 405 | * |[13:12] |SPI3SEL |SPI3 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 406 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 407 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 408 | * | | |10 = Clock source from PCLK0. |
kadonotakashi | 0:8fdf9a60065b | 409 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 410 | * |[15:14] |SPI5SEL |SPI5 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 411 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 412 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 413 | * | | |10 = Clock source from PCLK1. |
kadonotakashi | 0:8fdf9a60065b | 414 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 415 | * @var CLK_T::CLKSEL3 |
kadonotakashi | 0:8fdf9a60065b | 416 | * Offset: 0x1C Clock Source Select Control Register 3 |
kadonotakashi | 0:8fdf9a60065b | 417 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 418 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 419 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 420 | * |[1:0] |SC0SEL |Smart Card 0 (SC0) Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 421 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 422 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 423 | * | | |10 = Clock source from PCLK0. |
kadonotakashi | 0:8fdf9a60065b | 424 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 425 | * |[3:2] |SC1SEL |Smart Card 1 (SC1) Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 426 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 427 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 428 | * | | |10 = Clock source from PCLK1. |
kadonotakashi | 0:8fdf9a60065b | 429 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 430 | * |[5:4] |SC2SEL |Smart Card 2 (SC2) Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 431 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 432 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 433 | * | | |10 = Clock source from PCLK0. |
kadonotakashi | 0:8fdf9a60065b | 434 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 435 | * |[8] |RTCSEL |RTC Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 436 | * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 437 | * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 438 | * |[17:16] |I2S0SEL |I2S0 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 439 | * | | |00 = Clock source from HXT clock. |
kadonotakashi | 0:8fdf9a60065b | 440 | * | | |01 = Clock source from PLL clock. |
kadonotakashi | 0:8fdf9a60065b | 441 | * | | |10 = Clock source from PCLK0. |
kadonotakashi | 0:8fdf9a60065b | 442 | * | | |11 = Clock source from HIRC clock. |
kadonotakashi | 0:8fdf9a60065b | 443 | * |[25:24] |UART2SEL |UART2 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 444 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 445 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 446 | * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 447 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 448 | * |[27:26] |UART3SEL |UART3 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 449 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 450 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 451 | * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 452 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 453 | * |[29:28] |UART4SEL |UART4 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 454 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 455 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 456 | * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 457 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 458 | * |[31:30] |UART5SEL |UART5 Clock Source Selection |
kadonotakashi | 0:8fdf9a60065b | 459 | * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 460 | * | | |01 = Clock source from PLL. |
kadonotakashi | 0:8fdf9a60065b | 461 | * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). |
kadonotakashi | 0:8fdf9a60065b | 462 | * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 463 | * @var CLK_T::CLKDIV0 |
kadonotakashi | 0:8fdf9a60065b | 464 | * Offset: 0x20 Clock Divider Number Register 0 |
kadonotakashi | 0:8fdf9a60065b | 465 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 466 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 467 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 468 | * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source |
kadonotakashi | 0:8fdf9a60065b | 469 | * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 470 | * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock |
kadonotakashi | 0:8fdf9a60065b | 471 | * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 472 | * |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source |
kadonotakashi | 0:8fdf9a60065b | 473 | * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 474 | * |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source |
kadonotakashi | 0:8fdf9a60065b | 475 | * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 476 | * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source |
kadonotakashi | 0:8fdf9a60065b | 477 | * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 478 | * |[31:24] |SDH0DIV |SDHOST0 Clock Divide Number From SDHOST0 Clock Source |
kadonotakashi | 0:8fdf9a60065b | 479 | * | | |SDHOST0 clock frequency = (SDHOST0 clock source frequency) / (SDH0DIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 480 | * @var CLK_T::CLKDIV1 |
kadonotakashi | 0:8fdf9a60065b | 481 | * Offset: 0x24 Clock Divider Number Register 1 |
kadonotakashi | 0:8fdf9a60065b | 482 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 483 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 484 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 485 | * |[7:0] |SC0DIV |Smart Card 0 (SC0) Clock Divide Number From SC0 Clock Source |
kadonotakashi | 0:8fdf9a60065b | 486 | * | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 487 | * |[15:8] |SC1DIV |Smart Card 1 (SC1) Clock Divide Number From SC1 Clock Source |
kadonotakashi | 0:8fdf9a60065b | 488 | * | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 489 | * |[23:16] |SC2DIV |Smart Card 2 (SC2) Clock Divide Number From SC2 Clock Source |
kadonotakashi | 0:8fdf9a60065b | 490 | * | | |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 491 | * |[28:24] |DSRCDIV |DSRC Clock Divide Number From DSRC Clock Source |
kadonotakashi | 0:8fdf9a60065b | 492 | * | | |DSRC clock frequency = (DSRC clock source frequency) / (DSRCDIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 493 | * @var CLK_T::CLKDIV4 |
kadonotakashi | 0:8fdf9a60065b | 494 | * Offset: 0x30 Clock Divider Number Register 4 |
kadonotakashi | 0:8fdf9a60065b | 495 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 496 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 497 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 498 | * |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source |
kadonotakashi | 0:8fdf9a60065b | 499 | * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 500 | * |[7:4] |UART3DIV |UART3 Clock Divide Number From UART3 Clock Source |
kadonotakashi | 0:8fdf9a60065b | 501 | * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 502 | * |[11:8] |UART4DIV |UART4 Clock Divide Number From UART4 Clock Source |
kadonotakashi | 0:8fdf9a60065b | 503 | * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 504 | * |[15:12] |UART5DIV |UART5 Clock Divide Number From UART5 Clock Source |
kadonotakashi | 0:8fdf9a60065b | 505 | * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). |
kadonotakashi | 0:8fdf9a60065b | 506 | * @var CLK_T::PCLKDIV |
kadonotakashi | 0:8fdf9a60065b | 507 | * Offset: 0x34 APB Clock Divider Register |
kadonotakashi | 0:8fdf9a60065b | 508 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 509 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 510 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 511 | * |[2:0] |APB0DIV |APB0 Clock Divider |
kadonotakashi | 0:8fdf9a60065b | 512 | * | | |APB0 clock can be divided from HCLK. |
kadonotakashi | 0:8fdf9a60065b | 513 | * | | |000 = PCLK0 frequency is HCLK. |
kadonotakashi | 0:8fdf9a60065b | 514 | * | | |001 = PCLK0 frequency is 1/2 HCLK. |
kadonotakashi | 0:8fdf9a60065b | 515 | * | | |010 = PCLK0 frequency is 1/4 HCLK. |
kadonotakashi | 0:8fdf9a60065b | 516 | * | | |011 = PCLK0 frequency is 1/8 HCLK. |
kadonotakashi | 0:8fdf9a60065b | 517 | * | | |100 = PCLK0 frequency is 1/16 HCLK. |
kadonotakashi | 0:8fdf9a60065b | 518 | * | | |101 = PCLK0 frequency is 1/32 HCLK. |
kadonotakashi | 0:8fdf9a60065b | 519 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 520 | * |[6:4] |APB1DIV |APB1 Clock Divider |
kadonotakashi | 0:8fdf9a60065b | 521 | * | | |APB1 clock can be divided from HCLK. |
kadonotakashi | 0:8fdf9a60065b | 522 | * | | |000 = PCLK1 frequency is HCLK. |
kadonotakashi | 0:8fdf9a60065b | 523 | * | | |001 = PCLK1 frequency is 1/2 HCLK. |
kadonotakashi | 0:8fdf9a60065b | 524 | * | | |010 = PCLK1 frequency is 1/4 HCLK. |
kadonotakashi | 0:8fdf9a60065b | 525 | * | | |011 = PCLK1 frequency is 1/8 HCLK. |
kadonotakashi | 0:8fdf9a60065b | 526 | * | | |100 = PCLK1 frequency is 1/16 HCLK. |
kadonotakashi | 0:8fdf9a60065b | 527 | * | | |101 = PCLK1 frequency is 1/32 HCLK. |
kadonotakashi | 0:8fdf9a60065b | 528 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 529 | * @var CLK_T::PLLCTL |
kadonotakashi | 0:8fdf9a60065b | 530 | * Offset: 0x40 PLL Control Register |
kadonotakashi | 0:8fdf9a60065b | 531 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 532 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 533 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 534 | * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 535 | * | | |Refer to the PLL formulas. |
kadonotakashi | 0:8fdf9a60065b | 536 | * | | |Note1: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 537 | * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 538 | * | | |Refer to the PLL formulas. |
kadonotakashi | 0:8fdf9a60065b | 539 | * | | |Note1: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 540 | * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 541 | * | | |Refer to the PLL formulas. |
kadonotakashi | 0:8fdf9a60065b | 542 | * | | |Note1: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 543 | * |[16] |PD |Power-down Mode (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 544 | * | | |0 = PLL is enable (in normal mode). |
kadonotakashi | 0:8fdf9a60065b | 545 | * | | |1 = PLL is disable (in Power-down mode) (default). |
kadonotakashi | 0:8fdf9a60065b | 546 | * | | |Note1: If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. |
kadonotakashi | 0:8fdf9a60065b | 547 | * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 548 | * |[17] |BP |PLL Bypass Control (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 549 | * | | |0 = PLL is in normal mode (default). |
kadonotakashi | 0:8fdf9a60065b | 550 | * | | |1 = PLL clock output is same as PLL input clock FIN. |
kadonotakashi | 0:8fdf9a60065b | 551 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 552 | * |[18] |OE |PLL OE (FOUT Enable) Control (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 553 | * | | |0 = PLL FOUT Enabled. |
kadonotakashi | 0:8fdf9a60065b | 554 | * | | |1 = PLL FOUT is fixed low. |
kadonotakashi | 0:8fdf9a60065b | 555 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 556 | * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 557 | * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). |
kadonotakashi | 0:8fdf9a60065b | 558 | * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). |
kadonotakashi | 0:8fdf9a60065b | 559 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 560 | * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 561 | * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz). |
kadonotakashi | 0:8fdf9a60065b | 562 | * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz). |
kadonotakashi | 0:8fdf9a60065b | 563 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 564 | * @var CLK_T::STATUS |
kadonotakashi | 0:8fdf9a60065b | 565 | * Offset: 0x50 Clock Status Monitor Register |
kadonotakashi | 0:8fdf9a60065b | 566 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 567 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 568 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 569 | * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 570 | * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. |
kadonotakashi | 0:8fdf9a60065b | 571 | * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. |
kadonotakashi | 0:8fdf9a60065b | 572 | * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 573 | * | | |LXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7]). If C32KS is set to 0 the LXT stable flag is set when extLXT clock source is stable. If C32KS is set to 1 the LXT stable flag is set when LIRC32 clock source is stable. |
kadonotakashi | 0:8fdf9a60065b | 574 | * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. |
kadonotakashi | 0:8fdf9a60065b | 575 | * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. |
kadonotakashi | 0:8fdf9a60065b | 576 | * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 577 | * | | |0 = Internal PLL clock is not stable or disabled. |
kadonotakashi | 0:8fdf9a60065b | 578 | * | | |1 = Internal PLL clock is stable and enabled. |
kadonotakashi | 0:8fdf9a60065b | 579 | * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 580 | * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. |
kadonotakashi | 0:8fdf9a60065b | 581 | * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. |
kadonotakashi | 0:8fdf9a60065b | 582 | * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 583 | * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. |
kadonotakashi | 0:8fdf9a60065b | 584 | * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. |
kadonotakashi | 0:8fdf9a60065b | 585 | * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 586 | * | | |This bit is updated when software switches system clock source. |
kadonotakashi | 0:8fdf9a60065b | 587 | * | | |If switch target clock is stable, this bit will be set to 0. |
kadonotakashi | 0:8fdf9a60065b | 588 | * | | |If switch target clock is not stable, this bit will be set to 1. |
kadonotakashi | 0:8fdf9a60065b | 589 | * | | |0 = Clock switching success. |
kadonotakashi | 0:8fdf9a60065b | 590 | * | | |1 = Clock switching failure. |
kadonotakashi | 0:8fdf9a60065b | 591 | * | | |Note: This bit is read only. |
kadonotakashi | 0:8fdf9a60065b | 592 | * | | |After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. |
kadonotakashi | 0:8fdf9a60065b | 593 | * |[8] |EXTLXTSTB |EXTLXT Clock Source Stable Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 594 | * | | |0 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is not stable or disabled. |
kadonotakashi | 0:8fdf9a60065b | 595 | * | | |1 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is stable and enabled. |
kadonotakashi | 0:8fdf9a60065b | 596 | * |[9] |LIRC32STB |LIRC32 Clock Source Stable Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 597 | * | | |0 = 32 kHz internal low speed RC oscillator (LIRC32) clock is not stable or disabled. |
kadonotakashi | 0:8fdf9a60065b | 598 | * | | |1 = 32 kHz internal low speed RC oscillator (LIRC32) clock is stable and enabled. |
kadonotakashi | 0:8fdf9a60065b | 599 | * @var CLK_T::CLKOCTL |
kadonotakashi | 0:8fdf9a60065b | 600 | * Offset: 0x60 Clock Output Control Register |
kadonotakashi | 0:8fdf9a60065b | 601 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 602 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 603 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 604 | * |[3:0] |FREQSEL |Clock Output Frequency Selection |
kadonotakashi | 0:8fdf9a60065b | 605 | * | | |The formula of output frequency is Fout = Fin/2(N+1). |
kadonotakashi | 0:8fdf9a60065b | 606 | * | | |Fin is the input clock frequency. |
kadonotakashi | 0:8fdf9a60065b | 607 | * | | |Fout is the frequency of divider output clock. |
kadonotakashi | 0:8fdf9a60065b | 608 | * | | |N is the 4-bit value of FREQSEL[3:0]. |
kadonotakashi | 0:8fdf9a60065b | 609 | * |[4] |CLKOEN |Clock Output Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 610 | * | | |0 = Clock Output function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 611 | * | | |1 = Clock Output function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 612 | * |[5] |DIV1EN |Clock Output Divide One Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 613 | * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. |
kadonotakashi | 0:8fdf9a60065b | 614 | * | | |1 = Clock Output will output clock with source frequency. |
kadonotakashi | 0:8fdf9a60065b | 615 | * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 616 | * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. |
kadonotakashi | 0:8fdf9a60065b | 617 | * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. |
kadonotakashi | 0:8fdf9a60065b | 618 | * @var CLK_T::CLKDCTL |
kadonotakashi | 0:8fdf9a60065b | 619 | * Offset: 0x70 Clock Fail Detector Control Register |
kadonotakashi | 0:8fdf9a60065b | 620 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 621 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 622 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 623 | * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 624 | * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. |
kadonotakashi | 0:8fdf9a60065b | 625 | * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. |
kadonotakashi | 0:8fdf9a60065b | 626 | * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 627 | * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 628 | * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 629 | * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 630 | * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. |
kadonotakashi | 0:8fdf9a60065b | 631 | * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. |
kadonotakashi | 0:8fdf9a60065b | 632 | * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 633 | * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 634 | * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 635 | * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 636 | * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled. |
kadonotakashi | 0:8fdf9a60065b | 637 | * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled. |
kadonotakashi | 0:8fdf9a60065b | 638 | * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 639 | * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 640 | * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 641 | * @var CLK_T::CLKDSTS |
kadonotakashi | 0:8fdf9a60065b | 642 | * Offset: 0x74 Clock Fail Detector Status Register |
kadonotakashi | 0:8fdf9a60065b | 643 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 644 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 645 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 646 | * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 647 | * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. |
kadonotakashi | 0:8fdf9a60065b | 648 | * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. |
kadonotakashi | 0:8fdf9a60065b | 649 | * | | |Note1: Write 1 to clear the bit to 0. |
kadonotakashi | 0:8fdf9a60065b | 650 | * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 651 | * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 652 | * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. |
kadonotakashi | 0:8fdf9a60065b | 653 | * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. |
kadonotakashi | 0:8fdf9a60065b | 654 | * | | |Note1: Write 1 to clear the bit to 0. |
kadonotakashi | 0:8fdf9a60065b | 655 | * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 656 | * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 657 | * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. |
kadonotakashi | 0:8fdf9a60065b | 658 | * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. |
kadonotakashi | 0:8fdf9a60065b | 659 | * | | |Note1: Write 1 to clear the bit to 0. |
kadonotakashi | 0:8fdf9a60065b | 660 | * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 661 | * @var CLK_T::CDUPB |
kadonotakashi | 0:8fdf9a60065b | 662 | * Offset: 0x78 Clock Frequency Detector Upper Boundary Register |
kadonotakashi | 0:8fdf9a60065b | 663 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 664 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 665 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 666 | * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary |
kadonotakashi | 0:8fdf9a60065b | 667 | * | | |The bits define the high value of frequency monitor window. |
kadonotakashi | 0:8fdf9a60065b | 668 | * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. |
kadonotakashi | 0:8fdf9a60065b | 669 | * @var CLK_T::CDLOWB |
kadonotakashi | 0:8fdf9a60065b | 670 | * Offset: 0x7C Clock Frequency Detector Lower Boundary Register |
kadonotakashi | 0:8fdf9a60065b | 671 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 672 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 673 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 674 | * |[9:0] |LOWERBD |HXT Clock Frequency Detector Lower Boundary |
kadonotakashi | 0:8fdf9a60065b | 675 | * | | |The bits define the low value of frequency monitor window. |
kadonotakashi | 0:8fdf9a60065b | 676 | * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. |
kadonotakashi | 0:8fdf9a60065b | 677 | * @var CLK_T::PMUCTL |
kadonotakashi | 0:8fdf9a60065b | 678 | * Offset: 0x90 Power Manager Control Register |
kadonotakashi | 0:8fdf9a60065b | 679 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 680 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 681 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 682 | * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 683 | * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. |
kadonotakashi | 0:8fdf9a60065b | 684 | * | | |000 = Power-down mode is selected (PD). |
kadonotakashi | 0:8fdf9a60065b | 685 | * | | |001 = Low leakage Power-down mode is selected (LLPD). |
kadonotakashi | 0:8fdf9a60065b | 686 | * | | |010 = Fast wake-up Power-down (FWPD). |
kadonotakashi | 0:8fdf9a60065b | 687 | * | | |011 = Ultra low leakage Power-down mode is selected (ULLPD). |
kadonotakashi | 0:8fdf9a60065b | 688 | * | | |100 = Standby Power-down mode is selected (SPD). |
kadonotakashi | 0:8fdf9a60065b | 689 | * | | |101 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 690 | * | | |110 = Deep Power-down mode is selected (DPD). |
kadonotakashi | 0:8fdf9a60065b | 691 | * | | |111 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 692 | * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 693 | * |[8] |WKTMREN |Wake-up Timer Enable (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 694 | * | | |0 = Wake-up timer disable at Deep Power-down mode or Standby Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 695 | * | | |1 = Wake-up timer enabled at Deep Power-down mode or Standby Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 696 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 697 | * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 698 | * | | |These bits control wake-up timer time-out interval when chip under Deep Power-down mode or Standby Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 699 | * | | |000 = Time-out interval is 128 OSC10K clocks (12.8ms). |
kadonotakashi | 0:8fdf9a60065b | 700 | * | | |001 = Time-out interval is 256 OSC10K clocks (25.6ms). |
kadonotakashi | 0:8fdf9a60065b | 701 | * | | |010 = Time-out interval is 512 OSC10K clocks (51.2ms). |
kadonotakashi | 0:8fdf9a60065b | 702 | * | | |011 = Time-out interval is 1024 OSC10K clocks (102.4ms). |
kadonotakashi | 0:8fdf9a60065b | 703 | * | | |100 = Time-out interval is 4096 OSC10K clocks (409.6ms). |
kadonotakashi | 0:8fdf9a60065b | 704 | * | | |101 = Time-out interval is 8192 OSC10K clocks (819.2ms). |
kadonotakashi | 0:8fdf9a60065b | 705 | * | | |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms). |
kadonotakashi | 0:8fdf9a60065b | 706 | * | | |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms). |
kadonotakashi | 0:8fdf9a60065b | 707 | * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 708 | * |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 709 | * | | |00 = Wake-up pin disable at Deep Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 710 | * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 711 | * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 712 | * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 713 | * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 714 | * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 715 | * | | |0 = ACMP wake-up disable at Standby Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 716 | * | | |1 = ACMP wake-up enabled at Standby Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 717 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 718 | * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 719 | * | | |This is a protected register. Please refer to open lock sequence to program it. |
kadonotakashi | 0:8fdf9a60065b | 720 | * | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 721 | * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 722 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 723 | * @var CLK_T::PMUSTS |
kadonotakashi | 0:8fdf9a60065b | 724 | * @var CLK_T::PMUSTS |
kadonotakashi | 0:8fdf9a60065b | 725 | * Offset: 0x94 Power Manager Status Register |
kadonotakashi | 0:8fdf9a60065b | 726 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 727 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 728 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 729 | * |[0] |PINWK |Pin Wake-up Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 730 | * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the WAKEUP pin (GPC.0). |
kadonotakashi | 0:8fdf9a60065b | 731 | * | | |This flag is cleared when DPD mode is entered. |
kadonotakashi | 0:8fdf9a60065b | 732 | * |[1] |TMRWK |Timer Wake-up Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 733 | * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. |
kadonotakashi | 0:8fdf9a60065b | 734 | * | | |This flag is cleared when DPD or SPD mode is entered. |
kadonotakashi | 0:8fdf9a60065b | 735 | * |[2] |RTCWK |RTC Wake-up Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 736 | * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened. |
kadonotakashi | 0:8fdf9a60065b | 737 | * | | |This flag is cleared when DPD or SPD mode is entered. |
kadonotakashi | 0:8fdf9a60065b | 738 | * |[8] |GPAWK |GPA Wake-up Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 739 | * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPA group pins. |
kadonotakashi | 0:8fdf9a60065b | 740 | * | | |This flag is cleared when SPD mode is entered. |
kadonotakashi | 0:8fdf9a60065b | 741 | * |[9] |GPBWK |GPB Wake-up Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 742 | * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPB group pins. |
kadonotakashi | 0:8fdf9a60065b | 743 | * | | |This flag is cleared when SPD mode is entered. |
kadonotakashi | 0:8fdf9a60065b | 744 | * |[10] |GPCWK |GPC Wake-up Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 745 | * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPC group pins. |
kadonotakashi | 0:8fdf9a60065b | 746 | * | | |This flag is cleared when SPD mode is entered. |
kadonotakashi | 0:8fdf9a60065b | 747 | * |[11] |GPDWK |GPD Wake-up Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 748 | * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins. |
kadonotakashi | 0:8fdf9a60065b | 749 | * | | |This flag is cleared when SPD mode is entered. |
kadonotakashi | 0:8fdf9a60065b | 750 | * |[12] |LVRWK |LVR Wake-up Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 751 | * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a LVR happened. |
kadonotakashi | 0:8fdf9a60065b | 752 | * | | |This flag is cleared when SPD mode is entered. |
kadonotakashi | 0:8fdf9a60065b | 753 | * |[13] |BODWK |BOD Wake-up Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 754 | * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened. |
kadonotakashi | 0:8fdf9a60065b | 755 | * | | |This flag is cleared when SPD mode is entered. |
kadonotakashi | 0:8fdf9a60065b | 756 | * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 757 | * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition. |
kadonotakashi | 0:8fdf9a60065b | 758 | * | | |This flag is cleared when SPD mode is entered. |
kadonotakashi | 0:8fdf9a60065b | 759 | * |[31] |CLRWK |Clear Wake-up Flag |
kadonotakashi | 0:8fdf9a60065b | 760 | * | | |0 = No clear. |
kadonotakashi | 0:8fdf9a60065b | 761 | * | | |1 = Clear all wake-up flag. |
kadonotakashi | 0:8fdf9a60065b | 762 | * | | |Note: This bit is auto cleared by hardware. |
kadonotakashi | 0:8fdf9a60065b | 763 | * @var CLK_T::SWKDBCTL |
kadonotakashi | 0:8fdf9a60065b | 764 | * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register |
kadonotakashi | 0:8fdf9a60065b | 765 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 766 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 767 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 768 | * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection |
kadonotakashi | 0:8fdf9a60065b | 769 | * | | |0000 = Sample wake-up input once per 1 clocks. |
kadonotakashi | 0:8fdf9a60065b | 770 | * | | |0001 = Sample wake-up input once per 2 clocks. |
kadonotakashi | 0:8fdf9a60065b | 771 | * | | |0010 = Sample wake-up input once per 4 clocks. |
kadonotakashi | 0:8fdf9a60065b | 772 | * | | |0011 = Sample wake-up input once per 8 clocks. |
kadonotakashi | 0:8fdf9a60065b | 773 | * | | |0100 = Sample wake-up input once per 16 clocks. |
kadonotakashi | 0:8fdf9a60065b | 774 | * | | |0101 = Sample wake-up input once per 32 clocks. |
kadonotakashi | 0:8fdf9a60065b | 775 | * | | |0110 = Sample wake-up input once per 64 clocks. |
kadonotakashi | 0:8fdf9a60065b | 776 | * | | |0111 = Sample wake-up input once per 128 clocks. |
kadonotakashi | 0:8fdf9a60065b | 777 | * | | |1000 = Sample wake-up input once per 256 clocks. |
kadonotakashi | 0:8fdf9a60065b | 778 | * | | |1001 = Sample wake-up input once per 2*256 clocks. |
kadonotakashi | 0:8fdf9a60065b | 779 | * | | |1010 = Sample wake-up input once per 4*256 clocks. |
kadonotakashi | 0:8fdf9a60065b | 780 | * | | |1011 = Sample wake-up input once per 8*256 clocks. |
kadonotakashi | 0:8fdf9a60065b | 781 | * | | |1100 = Sample wake-up input once per 16*256 clocks. |
kadonotakashi | 0:8fdf9a60065b | 782 | * | | |1101 = Sample wake-up input once per 32*256 clocks. |
kadonotakashi | 0:8fdf9a60065b | 783 | * | | |1110 = Sample wake-up input once per 64*256 clocks. |
kadonotakashi | 0:8fdf9a60065b | 784 | * | | |1111 = Sample wake-up input once per 128*256 clocks. |
kadonotakashi | 0:8fdf9a60065b | 785 | * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 786 | * @var CLK_T::PASWKCTL |
kadonotakashi | 0:8fdf9a60065b | 787 | * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register |
kadonotakashi | 0:8fdf9a60065b | 788 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 789 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 790 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 791 | * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 792 | * | | |0 = GPA group pin wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 793 | * | | |1 = GPA group pin wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 794 | * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 795 | * | | |0 = GPA group pin rising edge wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 796 | * | | |1 = GPA group pin rising edge wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 797 | * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 798 | * | | |0 = GPA group pin falling edge wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 799 | * | | |1 = GPA group pin falling edge wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 800 | * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select |
kadonotakashi | 0:8fdf9a60065b | 801 | * | | |0000 = GPA.0 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 802 | * | | |0001 = GPA.1 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 803 | * | | |0010 = GPA.2 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 804 | * | | |0011 = GPA.3 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 805 | * | | |0100 = GPA.4 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 806 | * | | |0101 = GPA.5 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 807 | * | | |0110 = GPA.6 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 808 | * | | |0111 = GPA.7 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 809 | * | | |1000 = GPA.8 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 810 | * | | |1001 = GPA.9 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 811 | * | | |1010 = GPA.10 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 812 | * | | |1011 = GPA.11 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 813 | * | | |1100 = GPA.12 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 814 | * | | |1101 = GPA.13 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 815 | * | | |1110 = GPA.14 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 816 | * | | |1111 = GPA.15 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 817 | * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 818 | * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. |
kadonotakashi | 0:8fdf9a60065b | 819 | * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 820 | * | | |0 = Standby power-down wake-up pin De-bounce function disable. |
kadonotakashi | 0:8fdf9a60065b | 821 | * | | |1 = Standby power-down wake-up pin De-bounce function enable. |
kadonotakashi | 0:8fdf9a60065b | 822 | * | | |The de-bounce function is valid only for edge triggered. |
kadonotakashi | 0:8fdf9a60065b | 823 | * @var CLK_T::PBSWKCTL |
kadonotakashi | 0:8fdf9a60065b | 824 | * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register |
kadonotakashi | 0:8fdf9a60065b | 825 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 826 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 827 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 828 | * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 829 | * | | |0 = GPB group pin wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 830 | * | | |1 = GPB group pin wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 831 | * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 832 | * | | |0 = GPB group pin rising edge wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 833 | * | | |1 = GPB group pin rising edge wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 834 | * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 835 | * | | |0 = GPB group pin falling edge wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 836 | * | | |1 = GPB group pin falling edge wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 837 | * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select |
kadonotakashi | 0:8fdf9a60065b | 838 | * | | |0000 = GPB.0 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 839 | * | | |0001 = GPB.1 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 840 | * | | |0010 = GPB.2 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 841 | * | | |0011 = GPB.3 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 842 | * | | |0100 = GPB.4 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 843 | * | | |0101 = GPB.5 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 844 | * | | |0110 = GPB.6 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 845 | * | | |0111 = GPB.7 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 846 | * | | |1000 = GPB.8 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 847 | * | | |1001 = GPB.9 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 848 | * | | |1010 = GPB.10 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 849 | * | | |1011 = GPB.11 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 850 | * | | |1100 = GPB.12 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 851 | * | | |1101 = GPB.13 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 852 | * | | |1110 = GPB.14 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 853 | * | | |1111 = GPB.15 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 854 | * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 855 | * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. |
kadonotakashi | 0:8fdf9a60065b | 856 | * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup |
kadonotakashi | 0:8fdf9a60065b | 857 | * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 858 | * | | |0 = Standby power-down wake-up pin De-bounce function disable. |
kadonotakashi | 0:8fdf9a60065b | 859 | * | | |1 = Standby power-down wake-up pin De-bounce function enable. |
kadonotakashi | 0:8fdf9a60065b | 860 | * | | |The de-bounce function is valid only for edge triggered. |
kadonotakashi | 0:8fdf9a60065b | 861 | * @var CLK_T::PCSWKCTL |
kadonotakashi | 0:8fdf9a60065b | 862 | * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register |
kadonotakashi | 0:8fdf9a60065b | 863 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 864 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 865 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 866 | * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 867 | * | | |0 = GPC group pin wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 868 | * | | |1 = GPC group pin wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 869 | * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 870 | * | | |0 = GPC group pin rising edge wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 871 | * | | |1 = GPC group pin rising edge wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 872 | * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 873 | * | | |0 = GPC group pin falling edge wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 874 | * | | |1 = GPC group pin falling edge wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 875 | * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select |
kadonotakashi | 0:8fdf9a60065b | 876 | * | | |0000 = GPC.0 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 877 | * | | |0001 = GPC.1 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 878 | * | | |0010 = GPC.2 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 879 | * | | |0011 = GPC.3 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 880 | * | | |0100 = GPC.4 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 881 | * | | |0101 = GPC.5 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 882 | * | | |0110 = GPC.6 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 883 | * | | |0111 = GPC.7 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 884 | * | | |1000 = GPC.8 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 885 | * | | |1001 = GPC.9 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 886 | * | | |1010 = GPC.10 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 887 | * | | |1011 = GPC.11 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 888 | * | | |1100 = GPC.12 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 889 | * | | |1101 = GPC.13 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 890 | * | | |1110 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 891 | * | | |1111 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 892 | * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 893 | * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. |
kadonotakashi | 0:8fdf9a60065b | 894 | * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 895 | * | | |0 = Standby power-down wake-up pin De-bounce function disable. |
kadonotakashi | 0:8fdf9a60065b | 896 | * | | |1 = Standby power-down wake-up pin De-bounce function enable. |
kadonotakashi | 0:8fdf9a60065b | 897 | * | | |The de-bounce function is valid only for edge triggered. |
kadonotakashi | 0:8fdf9a60065b | 898 | * @var CLK_T::PDSWKCTL |
kadonotakashi | 0:8fdf9a60065b | 899 | * Offset: 0xAC GPD Standby Power-down Wake-up Control Register |
kadonotakashi | 0:8fdf9a60065b | 900 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 901 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 902 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 903 | * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 904 | * | | |0 = GPD group pin wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 905 | * | | |1 = GPD group pin wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 906 | * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 907 | * | | |0 = GPD group pin rising edge wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 908 | * | | |1 = GPD group pin rising edge wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 909 | * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 910 | * | | |0 = GPD group pin falling edge wake-up function disabled. |
kadonotakashi | 0:8fdf9a60065b | 911 | * | | |1 = GPD group pin falling edge wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 912 | * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select |
kadonotakashi | 0:8fdf9a60065b | 913 | * | | |0000 = GPD.0 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 914 | * | | |0001 = GPD.1 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 915 | * | | |0010 = GPD.2 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 916 | * | | |0011 = GPD.3 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 917 | * | | |0100 = GPD.4 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 918 | * | | |0101 = GPD.5 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 919 | * | | |0110 = GPD.6 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 920 | * | | |0111 = GPD.7 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 921 | * | | |1000 = GPD.8 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 922 | * | | |1001 = GPD.9 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 923 | * | | |1010 = GPD.10 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 924 | * | | |1011 = GPD.11 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 925 | * | | |1100 = GPD.12 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 926 | * | | |1101 = GPD.13 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 927 | * | | |1110 = GPD.14 wake-up function enabled. |
kadonotakashi | 0:8fdf9a60065b | 928 | * | | |1111 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 929 | * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 930 | * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. |
kadonotakashi | 0:8fdf9a60065b | 931 | * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). |
kadonotakashi | 0:8fdf9a60065b | 932 | * | | |0 = Standby power-down wake-up pin De-bounce function disable. |
kadonotakashi | 0:8fdf9a60065b | 933 | * | | |1 = Standby power-down wake-up pin De-bounce function enable. |
kadonotakashi | 0:8fdf9a60065b | 934 | * | | |The de-bounce function is valid only for edge triggered. |
kadonotakashi | 0:8fdf9a60065b | 935 | * @var CLK_T::IOPDCTL |
kadonotakashi | 0:8fdf9a60065b | 936 | * Offset: 0xB0 GPIO Standby Power-down Control Register |
kadonotakashi | 0:8fdf9a60065b | 937 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 938 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 939 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 940 | * |[0] |IOHR |GPIO Hold Release |
kadonotakashi | 0:8fdf9a60065b | 941 | * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status |
kadonotakashi | 0:8fdf9a60065b | 942 | * | | |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status. |
kadonotakashi | 0:8fdf9a60065b | 943 | * | | |Note: This bit is auto cleared by hardware. |
kadonotakashi | 0:8fdf9a60065b | 944 | * @var CLK_T::HXTFSEL |
kadonotakashi | 0:8fdf9a60065b | 945 | * Offset: 0xB4 HXT Filter Select Control Register |
kadonotakashi | 0:8fdf9a60065b | 946 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 947 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 948 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 949 | * |[0] |HXTFSEL |HXT Filter Select |
kadonotakashi | 0:8fdf9a60065b | 950 | * | | |0 = HXT frequency is > 12MHz. |
kadonotakashi | 0:8fdf9a60065b | 951 | * | | |1 = HXT frequency is <= 12MHz. |
kadonotakashi | 0:8fdf9a60065b | 952 | * | | |Note: This bit is auto cleared by hardware. |
kadonotakashi | 0:8fdf9a60065b | 953 | */ |
kadonotakashi | 0:8fdf9a60065b | 954 | |
kadonotakashi | 0:8fdf9a60065b | 955 | |
kadonotakashi | 0:8fdf9a60065b | 956 | __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 957 | __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 958 | __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ |
kadonotakashi | 0:8fdf9a60065b | 959 | __IO uint32_t APBCLK1; /*!< [0x000C] APB Devices Clock Enable Control Register 1 */ |
kadonotakashi | 0:8fdf9a60065b | 960 | __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ |
kadonotakashi | 0:8fdf9a60065b | 961 | __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ |
kadonotakashi | 0:8fdf9a60065b | 962 | __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ |
kadonotakashi | 0:8fdf9a60065b | 963 | __IO uint32_t CLKSEL3; /*!< [0x001C] Clock Source Select Control Register 3 */ |
kadonotakashi | 0:8fdf9a60065b | 964 | __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ |
kadonotakashi | 0:8fdf9a60065b | 965 | __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ |
kadonotakashi | 0:8fdf9a60065b | 966 | __I uint32_t RESERVE0[2]; |
kadonotakashi | 0:8fdf9a60065b | 967 | __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ |
kadonotakashi | 0:8fdf9a60065b | 968 | __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ |
kadonotakashi | 0:8fdf9a60065b | 969 | __I uint32_t RESERVE1[2]; |
kadonotakashi | 0:8fdf9a60065b | 970 | __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 971 | __I uint32_t RESERVE2[3]; |
kadonotakashi | 0:8fdf9a60065b | 972 | __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ |
kadonotakashi | 0:8fdf9a60065b | 973 | __I uint32_t RESERVE3[3]; |
kadonotakashi | 0:8fdf9a60065b | 974 | __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 975 | __I uint32_t RESERVE4[3]; |
kadonotakashi | 0:8fdf9a60065b | 976 | __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 977 | __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 978 | __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Detector Upper Boundary Register */ |
kadonotakashi | 0:8fdf9a60065b | 979 | __IO uint32_t CDLOWB; /*!< [0x007C] Clock Frequency Detector Low Boundary Register */ |
kadonotakashi | 0:8fdf9a60065b | 980 | __I uint32_t RESERVE5[4]; |
kadonotakashi | 0:8fdf9a60065b | 981 | __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 982 | __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 983 | __I uint32_t RESERVE6[1]; |
kadonotakashi | 0:8fdf9a60065b | 984 | __IO uint32_t SWKDBCTL; /*!< [0x009C] Standby Power-down Wake-up De-bounce Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 985 | __IO uint32_t PASWKCTL; /*!< [0x00A0] GPA Standby Power-down Wake-up Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 986 | __IO uint32_t PBSWKCTL; /*!< [0x00A4] GPB Standby Power-down Wake-up Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 987 | __IO uint32_t PCSWKCTL; /*!< [0x00A8] GPC Standby Power-down Wake-up Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 988 | __IO uint32_t PDSWKCTL; /*!< [0x00AC] GPD Standby Power-down Wake-up Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 989 | __IO uint32_t IOPDCTL; /*!< [0x00B0] GPIO Standby Power-down Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 990 | __IO uint32_t HXTFSEL; /*!< [0x00B4] HXT Filter Select Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 991 | |
kadonotakashi | 0:8fdf9a60065b | 992 | } CLK_T; |
kadonotakashi | 0:8fdf9a60065b | 993 | |
kadonotakashi | 0:8fdf9a60065b | 994 | /** |
kadonotakashi | 0:8fdf9a60065b | 995 | @addtogroup CLK_CONST CLK Bit Field Definition |
kadonotakashi | 0:8fdf9a60065b | 996 | Constant Definitions for CLK Controller |
kadonotakashi | 0:8fdf9a60065b | 997 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 998 | |
kadonotakashi | 0:8fdf9a60065b | 999 | #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1000 | #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1001 | |
kadonotakashi | 0:8fdf9a60065b | 1002 | #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1003 | #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1004 | |
kadonotakashi | 0:8fdf9a60065b | 1005 | #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1006 | #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1007 | |
kadonotakashi | 0:8fdf9a60065b | 1008 | #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1009 | #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1010 | |
kadonotakashi | 0:8fdf9a60065b | 1011 | #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1012 | #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1013 | |
kadonotakashi | 0:8fdf9a60065b | 1014 | #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ |
kadonotakashi | 0:8fdf9a60065b | 1015 | #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1016 | |
kadonotakashi | 0:8fdf9a60065b | 1017 | #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1018 | #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1019 | |
kadonotakashi | 0:8fdf9a60065b | 1020 | #define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1021 | #define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1022 | |
kadonotakashi | 0:8fdf9a60065b | 1023 | #define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ |
kadonotakashi | 0:8fdf9a60065b | 1024 | #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1025 | |
kadonotakashi | 0:8fdf9a60065b | 1026 | #define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1027 | #define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1028 | |
kadonotakashi | 0:8fdf9a60065b | 1029 | #define CLK_PWRCTL_HIRC48EN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1030 | #define CLK_PWRCTL_HIRC48EN_Msk (0x1ul << CLK_PWRCTL_HIRC48EN_Pos) /*!< CLK_T::PWRCTL: HIRC48EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1031 | |
kadonotakashi | 0:8fdf9a60065b | 1032 | #define CLK_AHBCLK_PDMA0CKEN_Pos (0) /*!< CLK_T::AHBCLK: PDMA0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1033 | #define CLK_AHBCLK_PDMA0CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA0CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1034 | |
kadonotakashi | 0:8fdf9a60065b | 1035 | #define CLK_AHBCLK_PDMA1CKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMA1CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1036 | #define CLK_AHBCLK_PDMA1CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA1CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA1CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1037 | |
kadonotakashi | 0:8fdf9a60065b | 1038 | #define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1039 | #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1040 | |
kadonotakashi | 0:8fdf9a60065b | 1041 | #define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1042 | #define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1043 | |
kadonotakashi | 0:8fdf9a60065b | 1044 | #define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1045 | #define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1046 | |
kadonotakashi | 0:8fdf9a60065b | 1047 | #define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1048 | #define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1049 | |
kadonotakashi | 0:8fdf9a60065b | 1050 | #define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1051 | #define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1052 | |
kadonotakashi | 0:8fdf9a60065b | 1053 | #define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1054 | #define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1055 | |
kadonotakashi | 0:8fdf9a60065b | 1056 | #define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1057 | #define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1058 | |
kadonotakashi | 0:8fdf9a60065b | 1059 | #define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1060 | #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1061 | |
kadonotakashi | 0:8fdf9a60065b | 1062 | #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1063 | #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1064 | |
kadonotakashi | 0:8fdf9a60065b | 1065 | #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1066 | #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1067 | |
kadonotakashi | 0:8fdf9a60065b | 1068 | #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1069 | #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1070 | |
kadonotakashi | 0:8fdf9a60065b | 1071 | #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1072 | #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1073 | |
kadonotakashi | 0:8fdf9a60065b | 1074 | #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1075 | #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1076 | |
kadonotakashi | 0:8fdf9a60065b | 1077 | #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1078 | #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1079 | |
kadonotakashi | 0:8fdf9a60065b | 1080 | #define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1081 | #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1082 | |
kadonotakashi | 0:8fdf9a60065b | 1083 | #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1084 | #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1085 | |
kadonotakashi | 0:8fdf9a60065b | 1086 | #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1087 | #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1088 | |
kadonotakashi | 0:8fdf9a60065b | 1089 | #define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1090 | #define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1091 | |
kadonotakashi | 0:8fdf9a60065b | 1092 | #define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1093 | #define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1094 | |
kadonotakashi | 0:8fdf9a60065b | 1095 | #define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1096 | #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1097 | |
kadonotakashi | 0:8fdf9a60065b | 1098 | #define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1099 | #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1100 | |
kadonotakashi | 0:8fdf9a60065b | 1101 | #define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1102 | #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1103 | |
kadonotakashi | 0:8fdf9a60065b | 1104 | #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1105 | #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1106 | |
kadonotakashi | 0:8fdf9a60065b | 1107 | #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1108 | #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1109 | |
kadonotakashi | 0:8fdf9a60065b | 1110 | #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1111 | #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1112 | |
kadonotakashi | 0:8fdf9a60065b | 1113 | #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1114 | #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1115 | |
kadonotakashi | 0:8fdf9a60065b | 1116 | #define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1117 | #define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1118 | |
kadonotakashi | 0:8fdf9a60065b | 1119 | #define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1120 | #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1121 | |
kadonotakashi | 0:8fdf9a60065b | 1122 | #define CLK_APBCLK0_DSRCCKEN_Pos (23) /*!< CLK_T::APBCLK0: DSRCCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1123 | #define CLK_APBCLK0_DSRCCKEN_Msk (0x1ul << CLK_APBCLK0_DSRCCKEN_Pos) /*!< CLK_T::APBCLK0: DSRCCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1124 | |
kadonotakashi | 0:8fdf9a60065b | 1125 | #define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1126 | #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1127 | |
kadonotakashi | 0:8fdf9a60065b | 1128 | #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1129 | #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1130 | |
kadonotakashi | 0:8fdf9a60065b | 1131 | #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1132 | #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1133 | |
kadonotakashi | 0:8fdf9a60065b | 1134 | #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1135 | #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1136 | |
kadonotakashi | 0:8fdf9a60065b | 1137 | #define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1138 | #define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1139 | |
kadonotakashi | 0:8fdf9a60065b | 1140 | #define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1141 | #define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1142 | |
kadonotakashi | 0:8fdf9a60065b | 1143 | #define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1144 | #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1145 | |
kadonotakashi | 0:8fdf9a60065b | 1146 | #define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1147 | #define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1148 | |
kadonotakashi | 0:8fdf9a60065b | 1149 | #define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1150 | #define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1151 | |
kadonotakashi | 0:8fdf9a60065b | 1152 | #define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1153 | #define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1154 | |
kadonotakashi | 0:8fdf9a60065b | 1155 | #define CLK_APBCLK1_SPI5CKEN_Pos (7) /*!< CLK_T::APBCLK1: SPI5CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1156 | #define CLK_APBCLK1_SPI5CKEN_Msk (0x1ul << CLK_APBCLK1_SPI5CKEN_Pos) /*!< CLK_T::APBCLK1: SPI5CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1157 | |
kadonotakashi | 0:8fdf9a60065b | 1158 | #define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1159 | #define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1160 | |
kadonotakashi | 0:8fdf9a60065b | 1161 | #define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1162 | #define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1163 | |
kadonotakashi | 0:8fdf9a60065b | 1164 | #define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1165 | #define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1166 | |
kadonotakashi | 0:8fdf9a60065b | 1167 | #define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1168 | #define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1169 | |
kadonotakashi | 0:8fdf9a60065b | 1170 | #define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1171 | #define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1172 | |
kadonotakashi | 0:8fdf9a60065b | 1173 | #define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1174 | #define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1175 | |
kadonotakashi | 0:8fdf9a60065b | 1176 | #define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1177 | #define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1178 | |
kadonotakashi | 0:8fdf9a60065b | 1179 | #define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1180 | #define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1181 | |
kadonotakashi | 0:8fdf9a60065b | 1182 | #define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1183 | #define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1184 | |
kadonotakashi | 0:8fdf9a60065b | 1185 | #define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1186 | #define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1187 | |
kadonotakashi | 0:8fdf9a60065b | 1188 | #define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1189 | #define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1190 | |
kadonotakashi | 0:8fdf9a60065b | 1191 | #define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1192 | #define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1193 | |
kadonotakashi | 0:8fdf9a60065b | 1194 | #define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1195 | #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1196 | |
kadonotakashi | 0:8fdf9a60065b | 1197 | #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1198 | #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1199 | |
kadonotakashi | 0:8fdf9a60065b | 1200 | #define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1201 | #define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: USBSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1202 | |
kadonotakashi | 0:8fdf9a60065b | 1203 | #define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1204 | #define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1205 | |
kadonotakashi | 0:8fdf9a60065b | 1206 | #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1207 | #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1208 | |
kadonotakashi | 0:8fdf9a60065b | 1209 | #define CLK_CLKSEL1_DSRCSEL_Pos (3) /*!< CLK_T::CLKSEL1: DSRCSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1210 | #define CLK_CLKSEL1_DSRCSEL_Msk (0x1ul << CLK_CLKSEL1_DSRCSEL_Pos) /*!< CLK_T::CLKSEL1: DSRCSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1211 | |
kadonotakashi | 0:8fdf9a60065b | 1212 | #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1213 | #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1214 | |
kadonotakashi | 0:8fdf9a60065b | 1215 | #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1216 | #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1217 | |
kadonotakashi | 0:8fdf9a60065b | 1218 | #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1219 | #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1220 | |
kadonotakashi | 0:8fdf9a60065b | 1221 | #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1222 | #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1223 | |
kadonotakashi | 0:8fdf9a60065b | 1224 | #define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1225 | #define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1226 | |
kadonotakashi | 0:8fdf9a60065b | 1227 | #define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1228 | #define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1229 | |
kadonotakashi | 0:8fdf9a60065b | 1230 | #define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1231 | #define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1232 | |
kadonotakashi | 0:8fdf9a60065b | 1233 | #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1234 | #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1235 | |
kadonotakashi | 0:8fdf9a60065b | 1236 | #define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1237 | #define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1238 | |
kadonotakashi | 0:8fdf9a60065b | 1239 | #define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1240 | #define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1241 | |
kadonotakashi | 0:8fdf9a60065b | 1242 | #define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1243 | #define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1244 | |
kadonotakashi | 0:8fdf9a60065b | 1245 | #define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1246 | #define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1247 | |
kadonotakashi | 0:8fdf9a60065b | 1248 | #define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1249 | #define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1250 | |
kadonotakashi | 0:8fdf9a60065b | 1251 | #define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1252 | #define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1253 | |
kadonotakashi | 0:8fdf9a60065b | 1254 | #define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1255 | #define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1256 | |
kadonotakashi | 0:8fdf9a60065b | 1257 | #define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1258 | #define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1259 | |
kadonotakashi | 0:8fdf9a60065b | 1260 | #define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1261 | #define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1262 | |
kadonotakashi | 0:8fdf9a60065b | 1263 | #define CLK_CLKSEL2_SPI5SEL_Pos (14) /*!< CLK_T::CLKSEL2: SPI5SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1264 | #define CLK_CLKSEL2_SPI5SEL_Msk (0x3ul << CLK_CLKSEL2_SPI5SEL_Pos) /*!< CLK_T::CLKSEL2: SPI5SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1265 | |
kadonotakashi | 0:8fdf9a60065b | 1266 | #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1267 | #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1268 | |
kadonotakashi | 0:8fdf9a60065b | 1269 | #define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1270 | #define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1271 | |
kadonotakashi | 0:8fdf9a60065b | 1272 | #define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1273 | #define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1274 | |
kadonotakashi | 0:8fdf9a60065b | 1275 | #define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1276 | #define CLK_CLKSEL3_RTCSEL_Msk (0x3ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1277 | |
kadonotakashi | 0:8fdf9a60065b | 1278 | #define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1279 | #define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1280 | |
kadonotakashi | 0:8fdf9a60065b | 1281 | #define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1282 | #define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1283 | |
kadonotakashi | 0:8fdf9a60065b | 1284 | #define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1285 | #define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1286 | |
kadonotakashi | 0:8fdf9a60065b | 1287 | #define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1288 | #define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1289 | |
kadonotakashi | 0:8fdf9a60065b | 1290 | #define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1291 | #define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1292 | |
kadonotakashi | 0:8fdf9a60065b | 1293 | #define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1294 | #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1295 | |
kadonotakashi | 0:8fdf9a60065b | 1296 | #define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1297 | #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1298 | |
kadonotakashi | 0:8fdf9a60065b | 1299 | #define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1300 | #define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1301 | |
kadonotakashi | 0:8fdf9a60065b | 1302 | #define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1303 | #define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1304 | |
kadonotakashi | 0:8fdf9a60065b | 1305 | #define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1306 | #define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1307 | |
kadonotakashi | 0:8fdf9a60065b | 1308 | #define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1309 | #define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1310 | |
kadonotakashi | 0:8fdf9a60065b | 1311 | #define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1312 | #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1313 | |
kadonotakashi | 0:8fdf9a60065b | 1314 | #define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1315 | #define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1316 | |
kadonotakashi | 0:8fdf9a60065b | 1317 | #define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1318 | #define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1319 | |
kadonotakashi | 0:8fdf9a60065b | 1320 | #define CLK_CLKDIV1_DSRCDIV_Pos (24) /*!< CLK_T::CLKDIV1: DSRCDIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1321 | #define CLK_CLKDIV1_DSRCDIV_Msk (0xfful << CLK_CLKDIV1_DSRCDIV_Pos) /*!< CLK_T::CLKDIV1: DSRCDIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1322 | |
kadonotakashi | 0:8fdf9a60065b | 1323 | #define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1324 | #define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1325 | |
kadonotakashi | 0:8fdf9a60065b | 1326 | #define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1327 | #define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1328 | |
kadonotakashi | 0:8fdf9a60065b | 1329 | #define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1330 | #define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1331 | |
kadonotakashi | 0:8fdf9a60065b | 1332 | #define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1333 | #define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1334 | |
kadonotakashi | 0:8fdf9a60065b | 1335 | #define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1336 | #define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1337 | |
kadonotakashi | 0:8fdf9a60065b | 1338 | #define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1339 | #define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1340 | |
kadonotakashi | 0:8fdf9a60065b | 1341 | #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1342 | #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1343 | |
kadonotakashi | 0:8fdf9a60065b | 1344 | #define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1345 | #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1346 | |
kadonotakashi | 0:8fdf9a60065b | 1347 | #define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ |
kadonotakashi | 0:8fdf9a60065b | 1348 | #define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1349 | |
kadonotakashi | 0:8fdf9a60065b | 1350 | #define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ |
kadonotakashi | 0:8fdf9a60065b | 1351 | #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1352 | |
kadonotakashi | 0:8fdf9a60065b | 1353 | #define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ |
kadonotakashi | 0:8fdf9a60065b | 1354 | #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1355 | |
kadonotakashi | 0:8fdf9a60065b | 1356 | #define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ |
kadonotakashi | 0:8fdf9a60065b | 1357 | #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1358 | |
kadonotakashi | 0:8fdf9a60065b | 1359 | #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ |
kadonotakashi | 0:8fdf9a60065b | 1360 | #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1361 | |
kadonotakashi | 0:8fdf9a60065b | 1362 | #define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1363 | #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1364 | |
kadonotakashi | 0:8fdf9a60065b | 1365 | #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ |
kadonotakashi | 0:8fdf9a60065b | 1366 | #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1367 | |
kadonotakashi | 0:8fdf9a60065b | 1368 | #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ |
kadonotakashi | 0:8fdf9a60065b | 1369 | #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1370 | |
kadonotakashi | 0:8fdf9a60065b | 1371 | #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ |
kadonotakashi | 0:8fdf9a60065b | 1372 | #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1373 | |
kadonotakashi | 0:8fdf9a60065b | 1374 | #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ |
kadonotakashi | 0:8fdf9a60065b | 1375 | #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1376 | |
kadonotakashi | 0:8fdf9a60065b | 1377 | #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ |
kadonotakashi | 0:8fdf9a60065b | 1378 | #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1379 | |
kadonotakashi | 0:8fdf9a60065b | 1380 | #define CLK_STATUS_HIRC48STB_Pos (6) /*!< CLK_T::STATUS: HIRC48STB Position */ |
kadonotakashi | 0:8fdf9a60065b | 1381 | #define CLK_STATUS_HIRC48STB_Msk (0x1ul << CLK_STATUS_HIRC48STB_Pos) /*!< CLK_T::STATUS: HIRC48STB Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1382 | |
kadonotakashi | 0:8fdf9a60065b | 1383 | #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1384 | #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1385 | |
kadonotakashi | 0:8fdf9a60065b | 1386 | #define CLK_STATUS_EXTLXTSTB_Pos (8) /*!< CLK_T::STATUS: EXTLXTSTB Position */ |
kadonotakashi | 0:8fdf9a60065b | 1387 | #define CLK_STATUS_EXTLXTSTB_Msk (0x1ul << CLK_STATUS_EXTLXTSTB_Pos) /*!< CLK_T::STATUS: EXTLXTSTB Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1388 | |
kadonotakashi | 0:8fdf9a60065b | 1389 | #define CLK_STATUS_LIRC32STB_Pos (9) /*!< CLK_T::STATUS: LIRC32STB Position */ |
kadonotakashi | 0:8fdf9a60065b | 1390 | #define CLK_STATUS_LIRC32STB_Msk (0x1ul << CLK_STATUS_LIRC32STB_Pos) /*!< CLK_T::STATUS: LIRC32STB Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1391 | |
kadonotakashi | 0:8fdf9a60065b | 1392 | #define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1393 | #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1394 | |
kadonotakashi | 0:8fdf9a60065b | 1395 | #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1396 | #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1397 | |
kadonotakashi | 0:8fdf9a60065b | 1398 | #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1399 | #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1400 | |
kadonotakashi | 0:8fdf9a60065b | 1401 | #define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1402 | #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1403 | |
kadonotakashi | 0:8fdf9a60065b | 1404 | #define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1405 | #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1406 | |
kadonotakashi | 0:8fdf9a60065b | 1407 | #define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1408 | #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1409 | |
kadonotakashi | 0:8fdf9a60065b | 1410 | #define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1411 | #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1412 | |
kadonotakashi | 0:8fdf9a60065b | 1413 | #define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1414 | #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1415 | |
kadonotakashi | 0:8fdf9a60065b | 1416 | #define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1417 | #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1418 | |
kadonotakashi | 0:8fdf9a60065b | 1419 | #define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1420 | #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1421 | |
kadonotakashi | 0:8fdf9a60065b | 1422 | #define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ |
kadonotakashi | 0:8fdf9a60065b | 1423 | #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1424 | |
kadonotakashi | 0:8fdf9a60065b | 1425 | #define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ |
kadonotakashi | 0:8fdf9a60065b | 1426 | #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1427 | |
kadonotakashi | 0:8fdf9a60065b | 1428 | #define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ |
kadonotakashi | 0:8fdf9a60065b | 1429 | #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1430 | |
kadonotakashi | 0:8fdf9a60065b | 1431 | #define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ |
kadonotakashi | 0:8fdf9a60065b | 1432 | #define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1433 | |
kadonotakashi | 0:8fdf9a60065b | 1434 | #define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ |
kadonotakashi | 0:8fdf9a60065b | 1435 | #define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1436 | |
kadonotakashi | 0:8fdf9a60065b | 1437 | #define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1438 | #define CLK_PMUCTL_PDMSEL_Msk (0x7ul<< CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1439 | |
kadonotakashi | 0:8fdf9a60065b | 1440 | #define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1441 | #define CLK_PMUCTL_WKTMREN_Msk (0x1ul<< CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1442 | |
kadonotakashi | 0:8fdf9a60065b | 1443 | #define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ |
kadonotakashi | 0:8fdf9a60065b | 1444 | #define CLK_PMUCTL_WKTMRIS_Msk (0x7ul<< CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1445 | |
kadonotakashi | 0:8fdf9a60065b | 1446 | #define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1447 | #define CLK_PMUCTL_WKPINEN_Msk (0x3ul<< CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1448 | |
kadonotakashi | 0:8fdf9a60065b | 1449 | #define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1450 | #define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul<< CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1451 | |
kadonotakashi | 0:8fdf9a60065b | 1452 | #define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1453 | #define CLK_PMUCTL_RTCWKEN_Msk (0x1ul<< CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1454 | |
kadonotakashi | 0:8fdf9a60065b | 1455 | #define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1456 | #define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1457 | |
kadonotakashi | 0:8fdf9a60065b | 1458 | #define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1459 | #define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1460 | |
kadonotakashi | 0:8fdf9a60065b | 1461 | #define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1462 | #define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1463 | |
kadonotakashi | 0:8fdf9a60065b | 1464 | #define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1465 | #define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1466 | |
kadonotakashi | 0:8fdf9a60065b | 1467 | #define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1468 | #define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1469 | |
kadonotakashi | 0:8fdf9a60065b | 1470 | #define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1471 | #define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1472 | |
kadonotakashi | 0:8fdf9a60065b | 1473 | #define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1474 | #define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1475 | |
kadonotakashi | 0:8fdf9a60065b | 1476 | #define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1477 | #define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1478 | |
kadonotakashi | 0:8fdf9a60065b | 1479 | #define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1480 | #define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1481 | |
kadonotakashi | 0:8fdf9a60065b | 1482 | #define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1483 | #define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1484 | |
kadonotakashi | 0:8fdf9a60065b | 1485 | #define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ |
kadonotakashi | 0:8fdf9a60065b | 1486 | #define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1487 | |
kadonotakashi | 0:8fdf9a60065b | 1488 | #define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1489 | #define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xFul<< CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1490 | |
kadonotakashi | 0:8fdf9a60065b | 1491 | #define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1492 | #define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1493 | |
kadonotakashi | 0:8fdf9a60065b | 1494 | #define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1495 | #define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1496 | |
kadonotakashi | 0:8fdf9a60065b | 1497 | #define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1498 | #define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1499 | |
kadonotakashi | 0:8fdf9a60065b | 1500 | #define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1501 | #define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1502 | |
kadonotakashi | 0:8fdf9a60065b | 1503 | #define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1504 | #define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1505 | |
kadonotakashi | 0:8fdf9a60065b | 1506 | #define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1507 | #define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1508 | |
kadonotakashi | 0:8fdf9a60065b | 1509 | #define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1510 | #define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1511 | |
kadonotakashi | 0:8fdf9a60065b | 1512 | #define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1513 | #define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1514 | |
kadonotakashi | 0:8fdf9a60065b | 1515 | #define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1516 | #define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1517 | |
kadonotakashi | 0:8fdf9a60065b | 1518 | #define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1519 | #define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1520 | |
kadonotakashi | 0:8fdf9a60065b | 1521 | #define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1522 | #define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1523 | |
kadonotakashi | 0:8fdf9a60065b | 1524 | #define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1525 | #define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1526 | |
kadonotakashi | 0:8fdf9a60065b | 1527 | #define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1528 | #define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1529 | |
kadonotakashi | 0:8fdf9a60065b | 1530 | #define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1531 | #define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1532 | |
kadonotakashi | 0:8fdf9a60065b | 1533 | #define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1534 | #define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1535 | |
kadonotakashi | 0:8fdf9a60065b | 1536 | #define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1537 | #define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1538 | |
kadonotakashi | 0:8fdf9a60065b | 1539 | #define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1540 | #define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1541 | |
kadonotakashi | 0:8fdf9a60065b | 1542 | #define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1543 | #define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1544 | |
kadonotakashi | 0:8fdf9a60065b | 1545 | #define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1546 | #define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1547 | |
kadonotakashi | 0:8fdf9a60065b | 1548 | #define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 1549 | #define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1550 | |
kadonotakashi | 0:8fdf9a60065b | 1551 | #define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ |
kadonotakashi | 0:8fdf9a60065b | 1552 | #define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1553 | |
kadonotakashi | 0:8fdf9a60065b | 1554 | #define CLK_HXTFSEL_HXTFSEL_Pos (0) /*!< CLK_T::HXTFSEL: HXTFSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 1555 | #define CLK_HXTFSEL_HXTFSEL_Msk (0x1ul << CLK_HXTFSEL_HXTFSEL_Pos) /*!< CLK_T::HXTFSEL: HXTFSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 1556 | |
kadonotakashi | 0:8fdf9a60065b | 1557 | |
kadonotakashi | 0:8fdf9a60065b | 1558 | /**@}*/ /* CLK_CONST */ |
kadonotakashi | 0:8fdf9a60065b | 1559 | /**@}*/ /* end of CLK register group */ |
kadonotakashi | 0:8fdf9a60065b | 1560 | |
kadonotakashi | 0:8fdf9a60065b | 1561 | #endif /* __CLK_REG_H__ */ |