takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_HEXIWEAR/fsl_clock_config.c@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /*
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
kadonotakashi 0:8fdf9a60065b 3 * All rights reserved.
kadonotakashi 0:8fdf9a60065b 4 *
kadonotakashi 0:8fdf9a60065b 5 * Redistribution and use in source and binary forms, with or without modification,
kadonotakashi 0:8fdf9a60065b 6 * are permitted provided that the following conditions are met:
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * o Redistributions of source code must retain the above copyright notice, this list
kadonotakashi 0:8fdf9a60065b 9 * of conditions and the following disclaimer.
kadonotakashi 0:8fdf9a60065b 10 *
kadonotakashi 0:8fdf9a60065b 11 * o Redistributions in binary form must reproduce the above copyright notice, this
kadonotakashi 0:8fdf9a60065b 12 * list of conditions and the following disclaimer in the documentation and/or
kadonotakashi 0:8fdf9a60065b 13 * other materials provided with the distribution.
kadonotakashi 0:8fdf9a60065b 14 *
kadonotakashi 0:8fdf9a60065b 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kadonotakashi 0:8fdf9a60065b 16 * contributors may be used to endorse or promote products derived from this
kadonotakashi 0:8fdf9a60065b 17 * software without specific prior written permission.
kadonotakashi 0:8fdf9a60065b 18 *
kadonotakashi 0:8fdf9a60065b 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kadonotakashi 0:8fdf9a60065b 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kadonotakashi 0:8fdf9a60065b 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kadonotakashi 0:8fdf9a60065b 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kadonotakashi 0:8fdf9a60065b 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kadonotakashi 0:8fdf9a60065b 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kadonotakashi 0:8fdf9a60065b 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kadonotakashi 0:8fdf9a60065b 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kadonotakashi 0:8fdf9a60065b 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kadonotakashi 0:8fdf9a60065b 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kadonotakashi 0:8fdf9a60065b 29 */
kadonotakashi 0:8fdf9a60065b 30
kadonotakashi 0:8fdf9a60065b 31 #include "fsl_common.h"
kadonotakashi 0:8fdf9a60065b 32 #include "fsl_smc.h"
kadonotakashi 0:8fdf9a60065b 33 #include "fsl_clock_config.h"
kadonotakashi 0:8fdf9a60065b 34
kadonotakashi 0:8fdf9a60065b 35 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 36 * Definitions
kadonotakashi 0:8fdf9a60065b 37 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 38 /*! @brief Clock configuration structure. */
kadonotakashi 0:8fdf9a60065b 39 typedef struct _clock_config
kadonotakashi 0:8fdf9a60065b 40 {
kadonotakashi 0:8fdf9a60065b 41 mcg_config_t mcgConfig; /*!< MCG configuration. */
kadonotakashi 0:8fdf9a60065b 42 sim_clock_config_t simConfig; /*!< SIM configuration. */
kadonotakashi 0:8fdf9a60065b 43 osc_config_t oscConfig; /*!< OSC configuration. */
kadonotakashi 0:8fdf9a60065b 44 uint32_t coreClock; /*!< core clock frequency. */
kadonotakashi 0:8fdf9a60065b 45 } clock_config_t;
kadonotakashi 0:8fdf9a60065b 46
kadonotakashi 0:8fdf9a60065b 47 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 48 * Variables
kadonotakashi 0:8fdf9a60065b 49 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 50 /* System clock frequency. */
kadonotakashi 0:8fdf9a60065b 51 extern uint32_t SystemCoreClock;
kadonotakashi 0:8fdf9a60065b 52
kadonotakashi 0:8fdf9a60065b 53 /* Configuration for enter VLPR mode. Core clock = 4MHz. */
kadonotakashi 0:8fdf9a60065b 54 const clock_config_t g_defaultClockConfigVlpr = {
kadonotakashi 0:8fdf9a60065b 55 .mcgConfig =
kadonotakashi 0:8fdf9a60065b 56 {
kadonotakashi 0:8fdf9a60065b 57 .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */
kadonotakashi 0:8fdf9a60065b 58 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
kadonotakashi 0:8fdf9a60065b 59 .ircs = kMCG_IrcFast, /* Select IRC4M. */
kadonotakashi 0:8fdf9a60065b 60 .fcrdiv = 0U, /* FCRDIV is 0. */
kadonotakashi 0:8fdf9a60065b 61
kadonotakashi 0:8fdf9a60065b 62 .frdiv = 0U,
kadonotakashi 0:8fdf9a60065b 63 .drs = kMCG_DrsLow, /* Low frequency range. */
kadonotakashi 0:8fdf9a60065b 64 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
kadonotakashi 0:8fdf9a60065b 65 .oscsel = kMCG_OscselOsc, /* Select OSC. */
kadonotakashi 0:8fdf9a60065b 66
kadonotakashi 0:8fdf9a60065b 67 .pll0Config =
kadonotakashi 0:8fdf9a60065b 68 {
kadonotakashi 0:8fdf9a60065b 69 .enableMode = 0U, /* Don't eanble PLL. */
kadonotakashi 0:8fdf9a60065b 70 .prdiv = 0U,
kadonotakashi 0:8fdf9a60065b 71 .vdiv = 0U,
kadonotakashi 0:8fdf9a60065b 72 },
kadonotakashi 0:8fdf9a60065b 73 },
kadonotakashi 0:8fdf9a60065b 74 .simConfig =
kadonotakashi 0:8fdf9a60065b 75 {
kadonotakashi 0:8fdf9a60065b 76 .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
kadonotakashi 0:8fdf9a60065b 77 .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
kadonotakashi 0:8fdf9a60065b 78 .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
kadonotakashi 0:8fdf9a60065b 79 },
kadonotakashi 0:8fdf9a60065b 80 .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
kadonotakashi 0:8fdf9a60065b 81 .capLoad = 0,
kadonotakashi 0:8fdf9a60065b 82 .workMode = kOSC_ModeOscLowPower,
kadonotakashi 0:8fdf9a60065b 83 .oscerConfig =
kadonotakashi 0:8fdf9a60065b 84 {
kadonotakashi 0:8fdf9a60065b 85 .enableMode = kOSC_ErClkEnable,
kadonotakashi 0:8fdf9a60065b 86 #if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
kadonotakashi 0:8fdf9a60065b 87 .erclkDiv = 0U,
kadonotakashi 0:8fdf9a60065b 88 #endif
kadonotakashi 0:8fdf9a60065b 89 }},
kadonotakashi 0:8fdf9a60065b 90 .coreClock = 4000000U, /* Core clock frequency */
kadonotakashi 0:8fdf9a60065b 91 };
kadonotakashi 0:8fdf9a60065b 92
kadonotakashi 0:8fdf9a60065b 93 /* Configuration for enter RUN mode. Core clock = 120MHz. */
kadonotakashi 0:8fdf9a60065b 94 const clock_config_t g_defaultClockConfigRun = {
kadonotakashi 0:8fdf9a60065b 95 .mcgConfig =
kadonotakashi 0:8fdf9a60065b 96 {
kadonotakashi 0:8fdf9a60065b 97 .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
kadonotakashi 0:8fdf9a60065b 98 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
kadonotakashi 0:8fdf9a60065b 99 .ircs = kMCG_IrcSlow, /* Select IRC32k. */
kadonotakashi 0:8fdf9a60065b 100 .fcrdiv = 0U, /* FCRDIV is 0. */
kadonotakashi 0:8fdf9a60065b 101
kadonotakashi 0:8fdf9a60065b 102 .frdiv = 7U,
kadonotakashi 0:8fdf9a60065b 103 .drs = kMCG_DrsLow, /* Low frequency range. */
kadonotakashi 0:8fdf9a60065b 104 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
kadonotakashi 0:8fdf9a60065b 105 .oscsel = kMCG_OscselOsc, /* Select OSC. */
kadonotakashi 0:8fdf9a60065b 106
kadonotakashi 0:8fdf9a60065b 107 .pll0Config =
kadonotakashi 0:8fdf9a60065b 108 {
kadonotakashi 0:8fdf9a60065b 109 .enableMode = 0U, .prdiv = 0x3U, .vdiv = 0x10U,
kadonotakashi 0:8fdf9a60065b 110 },
kadonotakashi 0:8fdf9a60065b 111 },
kadonotakashi 0:8fdf9a60065b 112 .simConfig =
kadonotakashi 0:8fdf9a60065b 113 {
kadonotakashi 0:8fdf9a60065b 114 .pllFllSel = 1U, /* PLLFLLSEL select PLL. */
kadonotakashi 0:8fdf9a60065b 115 .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
kadonotakashi 0:8fdf9a60065b 116 .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
kadonotakashi 0:8fdf9a60065b 117 },
kadonotakashi 0:8fdf9a60065b 118 .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
kadonotakashi 0:8fdf9a60065b 119 .capLoad = 0,
kadonotakashi 0:8fdf9a60065b 120 .workMode = kOSC_ModeOscLowPower,
kadonotakashi 0:8fdf9a60065b 121 .oscerConfig =
kadonotakashi 0:8fdf9a60065b 122 {
kadonotakashi 0:8fdf9a60065b 123 .enableMode = kOSC_ErClkEnable,
kadonotakashi 0:8fdf9a60065b 124 #if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
kadonotakashi 0:8fdf9a60065b 125 .erclkDiv = 0U,
kadonotakashi 0:8fdf9a60065b 126 #endif
kadonotakashi 0:8fdf9a60065b 127 }},
kadonotakashi 0:8fdf9a60065b 128 .coreClock = 120000000U, /* Core clock frequency */
kadonotakashi 0:8fdf9a60065b 129 };
kadonotakashi 0:8fdf9a60065b 130
kadonotakashi 0:8fdf9a60065b 131 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 132 * Code
kadonotakashi 0:8fdf9a60065b 133 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 134 /*
kadonotakashi 0:8fdf9a60065b 135 * How to setup clock using clock driver functions:
kadonotakashi 0:8fdf9a60065b 136 *
kadonotakashi 0:8fdf9a60065b 137 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
kadonotakashi 0:8fdf9a60065b 138 * and flash clock are in allowed range during clock mode switch.
kadonotakashi 0:8fdf9a60065b 139 *
kadonotakashi 0:8fdf9a60065b 140 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
kadonotakashi 0:8fdf9a60065b 141 *
kadonotakashi 0:8fdf9a60065b 142 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
kadonotakashi 0:8fdf9a60065b 143 * internal reference clock(MCGIRCLK). Follow the steps to setup:
kadonotakashi 0:8fdf9a60065b 144 *
kadonotakashi 0:8fdf9a60065b 145 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
kadonotakashi 0:8fdf9a60065b 146 *
kadonotakashi 0:8fdf9a60065b 147 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
kadonotakashi 0:8fdf9a60065b 148 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
kadonotakashi 0:8fdf9a60065b 149 * explicitly to setup MCGIRCLK.
kadonotakashi 0:8fdf9a60065b 150 *
kadonotakashi 0:8fdf9a60065b 151 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
kadonotakashi 0:8fdf9a60065b 152 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
kadonotakashi 0:8fdf9a60065b 153 * if the target mode is not FLL mode, the FLL is disabled.
kadonotakashi 0:8fdf9a60065b 154 *
kadonotakashi 0:8fdf9a60065b 155 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
kadonotakashi 0:8fdf9a60065b 156 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
kadonotakashi 0:8fdf9a60065b 157 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
kadonotakashi 0:8fdf9a60065b 158 *
kadonotakashi 0:8fdf9a60065b 159 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
kadonotakashi 0:8fdf9a60065b 160 */
kadonotakashi 0:8fdf9a60065b 161
kadonotakashi 0:8fdf9a60065b 162 void BOARD_BootClockVLPR(void)
kadonotakashi 0:8fdf9a60065b 163 {
kadonotakashi 0:8fdf9a60065b 164 CLOCK_SetSimSafeDivs();
kadonotakashi 0:8fdf9a60065b 165
kadonotakashi 0:8fdf9a60065b 166 CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
kadonotakashi 0:8fdf9a60065b 167 g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
kadonotakashi 0:8fdf9a60065b 168
kadonotakashi 0:8fdf9a60065b 169 CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
kadonotakashi 0:8fdf9a60065b 170
kadonotakashi 0:8fdf9a60065b 171 SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
kadonotakashi 0:8fdf9a60065b 172
kadonotakashi 0:8fdf9a60065b 173 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
kadonotakashi 0:8fdf9a60065b 174 SMC_SetPowerModeVlpr(SMC, false);
kadonotakashi 0:8fdf9a60065b 175 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
kadonotakashi 0:8fdf9a60065b 176 {
kadonotakashi 0:8fdf9a60065b 177 }
kadonotakashi 0:8fdf9a60065b 178 }
kadonotakashi 0:8fdf9a60065b 179
kadonotakashi 0:8fdf9a60065b 180 void BOARD_BootClockRUN(void)
kadonotakashi 0:8fdf9a60065b 181 {
kadonotakashi 0:8fdf9a60065b 182 CLOCK_SetSimSafeDivs();
kadonotakashi 0:8fdf9a60065b 183
kadonotakashi 0:8fdf9a60065b 184 CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
kadonotakashi 0:8fdf9a60065b 185 CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
kadonotakashi 0:8fdf9a60065b 186
kadonotakashi 0:8fdf9a60065b 187 CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
kadonotakashi 0:8fdf9a60065b 188 &g_defaultClockConfigRun.mcgConfig.pll0Config);
kadonotakashi 0:8fdf9a60065b 189
kadonotakashi 0:8fdf9a60065b 190 CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
kadonotakashi 0:8fdf9a60065b 191 g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
kadonotakashi 0:8fdf9a60065b 192
kadonotakashi 0:8fdf9a60065b 193 CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
kadonotakashi 0:8fdf9a60065b 194
kadonotakashi 0:8fdf9a60065b 195 SystemCoreClock = g_defaultClockConfigRun.coreClock;
kadonotakashi 0:8fdf9a60065b 196 }