![](/media/cache/img/default_profile.jpg.50x50_q85.jpg)
Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_FRDM/fsl_phy.c@3:f3764f852aa8, 2018-10-11 (annotated)
- Committer:
- kadonotakashi
- Date:
- Thu Oct 11 02:27:46 2018 +0000
- Revision:
- 3:f3764f852aa8
- Parent:
- 0:8fdf9a60065b
Nucreo 446 + SSD1331 test version;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /* |
kadonotakashi | 0:8fdf9a60065b | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
kadonotakashi | 0:8fdf9a60065b | 3 | * Copyright 2016-2017 NXP |
kadonotakashi | 0:8fdf9a60065b | 4 | * |
kadonotakashi | 0:8fdf9a60065b | 5 | * Redistribution and use in source and binary forms, with or without modification, |
kadonotakashi | 0:8fdf9a60065b | 6 | * are permitted provided that the following conditions are met: |
kadonotakashi | 0:8fdf9a60065b | 7 | * |
kadonotakashi | 0:8fdf9a60065b | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
kadonotakashi | 0:8fdf9a60065b | 9 | * of conditions and the following disclaimer. |
kadonotakashi | 0:8fdf9a60065b | 10 | * |
kadonotakashi | 0:8fdf9a60065b | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
kadonotakashi | 0:8fdf9a60065b | 12 | * list of conditions and the following disclaimer in the documentation and/or |
kadonotakashi | 0:8fdf9a60065b | 13 | * other materials provided with the distribution. |
kadonotakashi | 0:8fdf9a60065b | 14 | * |
kadonotakashi | 0:8fdf9a60065b | 15 | * o Neither the name of the copyright holder nor the names of its |
kadonotakashi | 0:8fdf9a60065b | 16 | * contributors may be used to endorse or promote products derived from this |
kadonotakashi | 0:8fdf9a60065b | 17 | * software without specific prior written permission. |
kadonotakashi | 0:8fdf9a60065b | 18 | * |
kadonotakashi | 0:8fdf9a60065b | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
kadonotakashi | 0:8fdf9a60065b | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
kadonotakashi | 0:8fdf9a60065b | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
kadonotakashi | 0:8fdf9a60065b | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
kadonotakashi | 0:8fdf9a60065b | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
kadonotakashi | 0:8fdf9a60065b | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
kadonotakashi | 0:8fdf9a60065b | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
kadonotakashi | 0:8fdf9a60065b | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
kadonotakashi | 0:8fdf9a60065b | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
kadonotakashi | 0:8fdf9a60065b | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
kadonotakashi | 0:8fdf9a60065b | 29 | */ |
kadonotakashi | 0:8fdf9a60065b | 30 | |
kadonotakashi | 0:8fdf9a60065b | 31 | #include "fsl_phy.h" |
kadonotakashi | 0:8fdf9a60065b | 32 | |
kadonotakashi | 0:8fdf9a60065b | 33 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 34 | * Definitions |
kadonotakashi | 0:8fdf9a60065b | 35 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 36 | |
kadonotakashi | 0:8fdf9a60065b | 37 | /*! @brief Defines the timeout macro. */ |
kadonotakashi | 0:8fdf9a60065b | 38 | #define PHY_TIMEOUT_COUNT 0xFFFFFU |
kadonotakashi | 0:8fdf9a60065b | 39 | |
kadonotakashi | 0:8fdf9a60065b | 40 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 41 | * Prototypes |
kadonotakashi | 0:8fdf9a60065b | 42 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 43 | |
kadonotakashi | 0:8fdf9a60065b | 44 | /*! |
kadonotakashi | 0:8fdf9a60065b | 45 | * @brief Get the ENET instance from peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 46 | * |
kadonotakashi | 0:8fdf9a60065b | 47 | * @param base ENET peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 48 | * @return ENET instance. |
kadonotakashi | 0:8fdf9a60065b | 49 | */ |
kadonotakashi | 0:8fdf9a60065b | 50 | extern uint32_t ENET_GetInstance(ENET_Type *base); |
kadonotakashi | 0:8fdf9a60065b | 51 | |
kadonotakashi | 0:8fdf9a60065b | 52 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 53 | * Variables |
kadonotakashi | 0:8fdf9a60065b | 54 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 55 | |
kadonotakashi | 0:8fdf9a60065b | 56 | #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) |
kadonotakashi | 0:8fdf9a60065b | 57 | /*! @brief Pointers to enet clocks for each instance. */ |
kadonotakashi | 0:8fdf9a60065b | 58 | extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; |
kadonotakashi | 0:8fdf9a60065b | 59 | #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ |
kadonotakashi | 0:8fdf9a60065b | 60 | |
kadonotakashi | 0:8fdf9a60065b | 61 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 62 | * Code |
kadonotakashi | 0:8fdf9a60065b | 63 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 64 | |
kadonotakashi | 0:8fdf9a60065b | 65 | status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) |
kadonotakashi | 0:8fdf9a60065b | 66 | { |
kadonotakashi | 0:8fdf9a60065b | 67 | uint32_t counter = PHY_TIMEOUT_COUNT; |
kadonotakashi | 0:8fdf9a60065b | 68 | uint32_t idReg = 0; |
kadonotakashi | 0:8fdf9a60065b | 69 | status_t result = kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 70 | uint32_t instance = ENET_GetInstance(base); |
kadonotakashi | 0:8fdf9a60065b | 71 | |
kadonotakashi | 0:8fdf9a60065b | 72 | #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) |
kadonotakashi | 0:8fdf9a60065b | 73 | /* Set SMI first. */ |
kadonotakashi | 0:8fdf9a60065b | 74 | CLOCK_EnableClock(s_enetClock[instance]); |
kadonotakashi | 0:8fdf9a60065b | 75 | #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ |
kadonotakashi | 0:8fdf9a60065b | 76 | ENET_SetSMI(base, srcClock_Hz, false); |
kadonotakashi | 0:8fdf9a60065b | 77 | |
kadonotakashi | 0:8fdf9a60065b | 78 | /* Initialization after PHY stars to work. */ |
kadonotakashi | 0:8fdf9a60065b | 79 | while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) |
kadonotakashi | 0:8fdf9a60065b | 80 | { |
kadonotakashi | 0:8fdf9a60065b | 81 | PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); |
kadonotakashi | 0:8fdf9a60065b | 82 | counter --; |
kadonotakashi | 0:8fdf9a60065b | 83 | } |
kadonotakashi | 0:8fdf9a60065b | 84 | |
kadonotakashi | 0:8fdf9a60065b | 85 | if (!counter) |
kadonotakashi | 0:8fdf9a60065b | 86 | { |
kadonotakashi | 0:8fdf9a60065b | 87 | return kStatus_Fail; |
kadonotakashi | 0:8fdf9a60065b | 88 | } |
kadonotakashi | 0:8fdf9a60065b | 89 | |
kadonotakashi | 0:8fdf9a60065b | 90 | /* Reset PHY. */ |
kadonotakashi | 0:8fdf9a60065b | 91 | result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); |
kadonotakashi | 0:8fdf9a60065b | 92 | |
kadonotakashi | 0:8fdf9a60065b | 93 | return result; |
kadonotakashi | 0:8fdf9a60065b | 94 | } |
kadonotakashi | 0:8fdf9a60065b | 95 | |
kadonotakashi | 0:8fdf9a60065b | 96 | status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr) |
kadonotakashi | 0:8fdf9a60065b | 97 | { |
kadonotakashi | 0:8fdf9a60065b | 98 | status_t result = kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 99 | uint32_t bssReg; |
kadonotakashi | 0:8fdf9a60065b | 100 | uint32_t counter = PHY_TIMEOUT_COUNT; |
kadonotakashi | 0:8fdf9a60065b | 101 | |
kadonotakashi | 0:8fdf9a60065b | 102 | /* Set the negotiation. */ |
kadonotakashi | 0:8fdf9a60065b | 103 | result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, |
kadonotakashi | 0:8fdf9a60065b | 104 | (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | |
kadonotakashi | 0:8fdf9a60065b | 105 | PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); |
kadonotakashi | 0:8fdf9a60065b | 106 | if (result == kStatus_Success) |
kadonotakashi | 0:8fdf9a60065b | 107 | { |
kadonotakashi | 0:8fdf9a60065b | 108 | result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, |
kadonotakashi | 0:8fdf9a60065b | 109 | (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); |
kadonotakashi | 0:8fdf9a60065b | 110 | if (result == kStatus_Success) |
kadonotakashi | 0:8fdf9a60065b | 111 | { |
kadonotakashi | 0:8fdf9a60065b | 112 | /* Check auto negotiation complete. */ |
kadonotakashi | 0:8fdf9a60065b | 113 | while (counter --) |
kadonotakashi | 0:8fdf9a60065b | 114 | { |
kadonotakashi | 0:8fdf9a60065b | 115 | result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); |
kadonotakashi | 0:8fdf9a60065b | 116 | if ( result == kStatus_Success) |
kadonotakashi | 0:8fdf9a60065b | 117 | { |
kadonotakashi | 0:8fdf9a60065b | 118 | if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) |
kadonotakashi | 0:8fdf9a60065b | 119 | { |
kadonotakashi | 0:8fdf9a60065b | 120 | break; |
kadonotakashi | 0:8fdf9a60065b | 121 | } |
kadonotakashi | 0:8fdf9a60065b | 122 | } |
kadonotakashi | 0:8fdf9a60065b | 123 | |
kadonotakashi | 0:8fdf9a60065b | 124 | if (!counter) |
kadonotakashi | 0:8fdf9a60065b | 125 | { |
kadonotakashi | 0:8fdf9a60065b | 126 | return kStatus_PHY_AutoNegotiateFail; |
kadonotakashi | 0:8fdf9a60065b | 127 | } |
kadonotakashi | 0:8fdf9a60065b | 128 | } |
kadonotakashi | 0:8fdf9a60065b | 129 | } |
kadonotakashi | 0:8fdf9a60065b | 130 | } |
kadonotakashi | 0:8fdf9a60065b | 131 | |
kadonotakashi | 0:8fdf9a60065b | 132 | return result; |
kadonotakashi | 0:8fdf9a60065b | 133 | } |
kadonotakashi | 0:8fdf9a60065b | 134 | |
kadonotakashi | 0:8fdf9a60065b | 135 | status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) |
kadonotakashi | 0:8fdf9a60065b | 136 | { |
kadonotakashi | 0:8fdf9a60065b | 137 | uint32_t counter; |
kadonotakashi | 0:8fdf9a60065b | 138 | |
kadonotakashi | 0:8fdf9a60065b | 139 | /* Clear the SMI interrupt event. */ |
kadonotakashi | 0:8fdf9a60065b | 140 | ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); |
kadonotakashi | 0:8fdf9a60065b | 141 | |
kadonotakashi | 0:8fdf9a60065b | 142 | /* Starts a SMI write command. */ |
kadonotakashi | 0:8fdf9a60065b | 143 | ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data); |
kadonotakashi | 0:8fdf9a60065b | 144 | |
kadonotakashi | 0:8fdf9a60065b | 145 | /* Wait for SMI complete. */ |
kadonotakashi | 0:8fdf9a60065b | 146 | for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) |
kadonotakashi | 0:8fdf9a60065b | 147 | { |
kadonotakashi | 0:8fdf9a60065b | 148 | if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) |
kadonotakashi | 0:8fdf9a60065b | 149 | { |
kadonotakashi | 0:8fdf9a60065b | 150 | break; |
kadonotakashi | 0:8fdf9a60065b | 151 | } |
kadonotakashi | 0:8fdf9a60065b | 152 | } |
kadonotakashi | 0:8fdf9a60065b | 153 | |
kadonotakashi | 0:8fdf9a60065b | 154 | /* Check for timeout. */ |
kadonotakashi | 0:8fdf9a60065b | 155 | if (!counter) |
kadonotakashi | 0:8fdf9a60065b | 156 | { |
kadonotakashi | 0:8fdf9a60065b | 157 | return kStatus_PHY_SMIVisitTimeout; |
kadonotakashi | 0:8fdf9a60065b | 158 | } |
kadonotakashi | 0:8fdf9a60065b | 159 | |
kadonotakashi | 0:8fdf9a60065b | 160 | /* Clear MII interrupt event. */ |
kadonotakashi | 0:8fdf9a60065b | 161 | ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); |
kadonotakashi | 0:8fdf9a60065b | 162 | |
kadonotakashi | 0:8fdf9a60065b | 163 | return kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 164 | } |
kadonotakashi | 0:8fdf9a60065b | 165 | |
kadonotakashi | 0:8fdf9a60065b | 166 | status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) |
kadonotakashi | 0:8fdf9a60065b | 167 | { |
kadonotakashi | 0:8fdf9a60065b | 168 | assert(dataPtr); |
kadonotakashi | 0:8fdf9a60065b | 169 | |
kadonotakashi | 0:8fdf9a60065b | 170 | uint32_t counter; |
kadonotakashi | 0:8fdf9a60065b | 171 | |
kadonotakashi | 0:8fdf9a60065b | 172 | /* Clear the MII interrupt event. */ |
kadonotakashi | 0:8fdf9a60065b | 173 | ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); |
kadonotakashi | 0:8fdf9a60065b | 174 | |
kadonotakashi | 0:8fdf9a60065b | 175 | /* Starts a SMI read command operation. */ |
kadonotakashi | 0:8fdf9a60065b | 176 | ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame); |
kadonotakashi | 0:8fdf9a60065b | 177 | |
kadonotakashi | 0:8fdf9a60065b | 178 | /* Wait for MII complete. */ |
kadonotakashi | 0:8fdf9a60065b | 179 | for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) |
kadonotakashi | 0:8fdf9a60065b | 180 | { |
kadonotakashi | 0:8fdf9a60065b | 181 | if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) |
kadonotakashi | 0:8fdf9a60065b | 182 | { |
kadonotakashi | 0:8fdf9a60065b | 183 | break; |
kadonotakashi | 0:8fdf9a60065b | 184 | } |
kadonotakashi | 0:8fdf9a60065b | 185 | } |
kadonotakashi | 0:8fdf9a60065b | 186 | |
kadonotakashi | 0:8fdf9a60065b | 187 | /* Check for timeout. */ |
kadonotakashi | 0:8fdf9a60065b | 188 | if (!counter) |
kadonotakashi | 0:8fdf9a60065b | 189 | { |
kadonotakashi | 0:8fdf9a60065b | 190 | return kStatus_PHY_SMIVisitTimeout; |
kadonotakashi | 0:8fdf9a60065b | 191 | } |
kadonotakashi | 0:8fdf9a60065b | 192 | |
kadonotakashi | 0:8fdf9a60065b | 193 | /* Get data from MII register. */ |
kadonotakashi | 0:8fdf9a60065b | 194 | *dataPtr = ENET_ReadSMIData(base); |
kadonotakashi | 0:8fdf9a60065b | 195 | |
kadonotakashi | 0:8fdf9a60065b | 196 | /* Clear MII interrupt event. */ |
kadonotakashi | 0:8fdf9a60065b | 197 | ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); |
kadonotakashi | 0:8fdf9a60065b | 198 | |
kadonotakashi | 0:8fdf9a60065b | 199 | return kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 200 | } |
kadonotakashi | 0:8fdf9a60065b | 201 | |
kadonotakashi | 0:8fdf9a60065b | 202 | status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable) |
kadonotakashi | 0:8fdf9a60065b | 203 | { |
kadonotakashi | 0:8fdf9a60065b | 204 | status_t result; |
kadonotakashi | 0:8fdf9a60065b | 205 | uint32_t data = 0; |
kadonotakashi | 0:8fdf9a60065b | 206 | |
kadonotakashi | 0:8fdf9a60065b | 207 | /* Set the loop mode. */ |
kadonotakashi | 0:8fdf9a60065b | 208 | if (enable) |
kadonotakashi | 0:8fdf9a60065b | 209 | { |
kadonotakashi | 0:8fdf9a60065b | 210 | if (mode == kPHY_LocalLoop) |
kadonotakashi | 0:8fdf9a60065b | 211 | { |
kadonotakashi | 0:8fdf9a60065b | 212 | /* First read the current status in control register. */ |
kadonotakashi | 0:8fdf9a60065b | 213 | result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); |
kadonotakashi | 0:8fdf9a60065b | 214 | if (result == kStatus_Success) |
kadonotakashi | 0:8fdf9a60065b | 215 | { |
kadonotakashi | 0:8fdf9a60065b | 216 | return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_LOOP_MASK)); |
kadonotakashi | 0:8fdf9a60065b | 217 | } |
kadonotakashi | 0:8fdf9a60065b | 218 | } |
kadonotakashi | 0:8fdf9a60065b | 219 | else |
kadonotakashi | 0:8fdf9a60065b | 220 | { |
kadonotakashi | 0:8fdf9a60065b | 221 | /* First read the current status in control register. */ |
kadonotakashi | 0:8fdf9a60065b | 222 | result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); |
kadonotakashi | 0:8fdf9a60065b | 223 | if (result == kStatus_Success) |
kadonotakashi | 0:8fdf9a60065b | 224 | { |
kadonotakashi | 0:8fdf9a60065b | 225 | return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); |
kadonotakashi | 0:8fdf9a60065b | 226 | } |
kadonotakashi | 0:8fdf9a60065b | 227 | } |
kadonotakashi | 0:8fdf9a60065b | 228 | } |
kadonotakashi | 0:8fdf9a60065b | 229 | else |
kadonotakashi | 0:8fdf9a60065b | 230 | { |
kadonotakashi | 0:8fdf9a60065b | 231 | /* Disable the loop mode. */ |
kadonotakashi | 0:8fdf9a60065b | 232 | if (mode == kPHY_LocalLoop) |
kadonotakashi | 0:8fdf9a60065b | 233 | { |
kadonotakashi | 0:8fdf9a60065b | 234 | /* First read the current status in the basic control register. */ |
kadonotakashi | 0:8fdf9a60065b | 235 | result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); |
kadonotakashi | 0:8fdf9a60065b | 236 | if (result == kStatus_Success) |
kadonotakashi | 0:8fdf9a60065b | 237 | { |
kadonotakashi | 0:8fdf9a60065b | 238 | return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data & ~PHY_BCTL_LOOP_MASK)); |
kadonotakashi | 0:8fdf9a60065b | 239 | } |
kadonotakashi | 0:8fdf9a60065b | 240 | } |
kadonotakashi | 0:8fdf9a60065b | 241 | else |
kadonotakashi | 0:8fdf9a60065b | 242 | { |
kadonotakashi | 0:8fdf9a60065b | 243 | /* First read the current status in control one register. */ |
kadonotakashi | 0:8fdf9a60065b | 244 | result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); |
kadonotakashi | 0:8fdf9a60065b | 245 | if (result == kStatus_Success) |
kadonotakashi | 0:8fdf9a60065b | 246 | { |
kadonotakashi | 0:8fdf9a60065b | 247 | return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); |
kadonotakashi | 0:8fdf9a60065b | 248 | } |
kadonotakashi | 0:8fdf9a60065b | 249 | } |
kadonotakashi | 0:8fdf9a60065b | 250 | } |
kadonotakashi | 0:8fdf9a60065b | 251 | return result; |
kadonotakashi | 0:8fdf9a60065b | 252 | } |
kadonotakashi | 0:8fdf9a60065b | 253 | |
kadonotakashi | 0:8fdf9a60065b | 254 | status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) |
kadonotakashi | 0:8fdf9a60065b | 255 | { |
kadonotakashi | 0:8fdf9a60065b | 256 | assert(status); |
kadonotakashi | 0:8fdf9a60065b | 257 | |
kadonotakashi | 0:8fdf9a60065b | 258 | status_t result = kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 259 | uint32_t data; |
kadonotakashi | 0:8fdf9a60065b | 260 | |
kadonotakashi | 0:8fdf9a60065b | 261 | /* Read the basic status register. */ |
kadonotakashi | 0:8fdf9a60065b | 262 | result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); |
kadonotakashi | 0:8fdf9a60065b | 263 | if (result == kStatus_Success) |
kadonotakashi | 0:8fdf9a60065b | 264 | { |
kadonotakashi | 0:8fdf9a60065b | 265 | if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) |
kadonotakashi | 0:8fdf9a60065b | 266 | { |
kadonotakashi | 0:8fdf9a60065b | 267 | /* link down. */ |
kadonotakashi | 0:8fdf9a60065b | 268 | *status = false; |
kadonotakashi | 0:8fdf9a60065b | 269 | } |
kadonotakashi | 0:8fdf9a60065b | 270 | else |
kadonotakashi | 0:8fdf9a60065b | 271 | { |
kadonotakashi | 0:8fdf9a60065b | 272 | /* link up. */ |
kadonotakashi | 0:8fdf9a60065b | 273 | *status = true; |
kadonotakashi | 0:8fdf9a60065b | 274 | } |
kadonotakashi | 0:8fdf9a60065b | 275 | } |
kadonotakashi | 0:8fdf9a60065b | 276 | return result; |
kadonotakashi | 0:8fdf9a60065b | 277 | } |
kadonotakashi | 0:8fdf9a60065b | 278 | |
kadonotakashi | 0:8fdf9a60065b | 279 | status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) |
kadonotakashi | 0:8fdf9a60065b | 280 | { |
kadonotakashi | 0:8fdf9a60065b | 281 | assert(duplex); |
kadonotakashi | 0:8fdf9a60065b | 282 | |
kadonotakashi | 0:8fdf9a60065b | 283 | status_t result = kStatus_Success; |
kadonotakashi | 0:8fdf9a60065b | 284 | uint32_t data, ctlReg; |
kadonotakashi | 0:8fdf9a60065b | 285 | |
kadonotakashi | 0:8fdf9a60065b | 286 | /* Read the control two register. */ |
kadonotakashi | 0:8fdf9a60065b | 287 | result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); |
kadonotakashi | 0:8fdf9a60065b | 288 | if (result == kStatus_Success) |
kadonotakashi | 0:8fdf9a60065b | 289 | { |
kadonotakashi | 0:8fdf9a60065b | 290 | data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; |
kadonotakashi | 0:8fdf9a60065b | 291 | if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) |
kadonotakashi | 0:8fdf9a60065b | 292 | { |
kadonotakashi | 0:8fdf9a60065b | 293 | /* Full duplex. */ |
kadonotakashi | 0:8fdf9a60065b | 294 | *duplex = kPHY_FullDuplex; |
kadonotakashi | 0:8fdf9a60065b | 295 | } |
kadonotakashi | 0:8fdf9a60065b | 296 | else |
kadonotakashi | 0:8fdf9a60065b | 297 | { |
kadonotakashi | 0:8fdf9a60065b | 298 | /* Half duplex. */ |
kadonotakashi | 0:8fdf9a60065b | 299 | *duplex = kPHY_HalfDuplex; |
kadonotakashi | 0:8fdf9a60065b | 300 | } |
kadonotakashi | 0:8fdf9a60065b | 301 | |
kadonotakashi | 0:8fdf9a60065b | 302 | data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; |
kadonotakashi | 0:8fdf9a60065b | 303 | if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) |
kadonotakashi | 0:8fdf9a60065b | 304 | { |
kadonotakashi | 0:8fdf9a60065b | 305 | /* 100M speed. */ |
kadonotakashi | 0:8fdf9a60065b | 306 | *speed = kPHY_Speed100M; |
kadonotakashi | 0:8fdf9a60065b | 307 | } |
kadonotakashi | 0:8fdf9a60065b | 308 | else |
kadonotakashi | 0:8fdf9a60065b | 309 | { /* 10M speed. */ |
kadonotakashi | 0:8fdf9a60065b | 310 | *speed = kPHY_Speed10M; |
kadonotakashi | 0:8fdf9a60065b | 311 | } |
kadonotakashi | 0:8fdf9a60065b | 312 | } |
kadonotakashi | 0:8fdf9a60065b | 313 | |
kadonotakashi | 0:8fdf9a60065b | 314 | return result; |
kadonotakashi | 0:8fdf9a60065b | 315 | } |