takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_spi.h@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /*
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
kadonotakashi 0:8fdf9a60065b 3 * All rights reserved.
kadonotakashi 0:8fdf9a60065b 4 *
kadonotakashi 0:8fdf9a60065b 5 * Redistribution and use in source and binary forms, with or without modification,
kadonotakashi 0:8fdf9a60065b 6 * are permitted provided that the following conditions are met:
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * o Redistributions of source code must retain the above copyright notice, this list
kadonotakashi 0:8fdf9a60065b 9 * of conditions and the following disclaimer.
kadonotakashi 0:8fdf9a60065b 10 *
kadonotakashi 0:8fdf9a60065b 11 * o Redistributions in binary form must reproduce the above copyright notice, this
kadonotakashi 0:8fdf9a60065b 12 * list of conditions and the following disclaimer in the documentation and/or
kadonotakashi 0:8fdf9a60065b 13 * other materials provided with the distribution.
kadonotakashi 0:8fdf9a60065b 14 *
kadonotakashi 0:8fdf9a60065b 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kadonotakashi 0:8fdf9a60065b 16 * contributors may be used tom endorse or promote products derived from this
kadonotakashi 0:8fdf9a60065b 17 * software without specific prior written permission.
kadonotakashi 0:8fdf9a60065b 18 *
kadonotakashi 0:8fdf9a60065b 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kadonotakashi 0:8fdf9a60065b 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kadonotakashi 0:8fdf9a60065b 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kadonotakashi 0:8fdf9a60065b 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kadonotakashi 0:8fdf9a60065b 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kadonotakashi 0:8fdf9a60065b 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kadonotakashi 0:8fdf9a60065b 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kadonotakashi 0:8fdf9a60065b 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kadonotakashi 0:8fdf9a60065b 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kadonotakashi 0:8fdf9a60065b 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kadonotakashi 0:8fdf9a60065b 29 */
kadonotakashi 0:8fdf9a60065b 30 #ifndef _FSL_SPI_H_
kadonotakashi 0:8fdf9a60065b 31 #define _FSL_SPI_H_
kadonotakashi 0:8fdf9a60065b 32
kadonotakashi 0:8fdf9a60065b 33 #include "fsl_common.h"
kadonotakashi 0:8fdf9a60065b 34
kadonotakashi 0:8fdf9a60065b 35 /*!
kadonotakashi 0:8fdf9a60065b 36 * @addtogroup spi_driver
kadonotakashi 0:8fdf9a60065b 37 * @{
kadonotakashi 0:8fdf9a60065b 38 */
kadonotakashi 0:8fdf9a60065b 39
kadonotakashi 0:8fdf9a60065b 40
kadonotakashi 0:8fdf9a60065b 41 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 42 * Definitions
kadonotakashi 0:8fdf9a60065b 43 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 44
kadonotakashi 0:8fdf9a60065b 45 /*! @name Driver version */
kadonotakashi 0:8fdf9a60065b 46 /*@{*/
kadonotakashi 0:8fdf9a60065b 47 /*! @brief SPI driver version 2.0.1. */
kadonotakashi 0:8fdf9a60065b 48 #define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
kadonotakashi 0:8fdf9a60065b 49 /*@}*/
kadonotakashi 0:8fdf9a60065b 50
kadonotakashi 0:8fdf9a60065b 51 #ifndef SPI_DUMMYDATA
kadonotakashi 0:8fdf9a60065b 52 /*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */
kadonotakashi 0:8fdf9a60065b 53 #define SPI_DUMMYDATA (0xFFU)
kadonotakashi 0:8fdf9a60065b 54 #endif
kadonotakashi 0:8fdf9a60065b 55
kadonotakashi 0:8fdf9a60065b 56 /*! @brief Return status for the SPI driver.*/
kadonotakashi 0:8fdf9a60065b 57 enum _spi_status
kadonotakashi 0:8fdf9a60065b 58 {
kadonotakashi 0:8fdf9a60065b 59 kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_SPI, 0), /*!< SPI bus is busy */
kadonotakashi 0:8fdf9a60065b 60 kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_SPI, 1), /*!< SPI is idle */
kadonotakashi 0:8fdf9a60065b 61 kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_SPI, 2) /*!< SPI error */
kadonotakashi 0:8fdf9a60065b 62 };
kadonotakashi 0:8fdf9a60065b 63
kadonotakashi 0:8fdf9a60065b 64 /*! @brief SPI clock polarity configuration.*/
kadonotakashi 0:8fdf9a60065b 65 typedef enum _spi_clock_polarity
kadonotakashi 0:8fdf9a60065b 66 {
kadonotakashi 0:8fdf9a60065b 67 kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
kadonotakashi 0:8fdf9a60065b 68 kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */
kadonotakashi 0:8fdf9a60065b 69 } spi_clock_polarity_t;
kadonotakashi 0:8fdf9a60065b 70
kadonotakashi 0:8fdf9a60065b 71 /*! @brief SPI clock phase configuration.*/
kadonotakashi 0:8fdf9a60065b 72 typedef enum _spi_clock_phase
kadonotakashi 0:8fdf9a60065b 73 {
kadonotakashi 0:8fdf9a60065b 74 kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first
kadonotakashi 0:8fdf9a60065b 75 * cycle of a data transfer. */
kadonotakashi 0:8fdf9a60065b 76 kSPI_ClockPhaseSecondEdge /*!< First edge on SPSCK occurs at the start of the
kadonotakashi 0:8fdf9a60065b 77 * first cycle of a data transfer. */
kadonotakashi 0:8fdf9a60065b 78 } spi_clock_phase_t;
kadonotakashi 0:8fdf9a60065b 79
kadonotakashi 0:8fdf9a60065b 80 /*! @brief SPI data shifter direction options.*/
kadonotakashi 0:8fdf9a60065b 81 typedef enum _spi_shift_direction
kadonotakashi 0:8fdf9a60065b 82 {
kadonotakashi 0:8fdf9a60065b 83 kSPI_MsbFirst = 0x0U, /*!< Data transfers start with most significant bit. */
kadonotakashi 0:8fdf9a60065b 84 kSPI_LsbFirst /*!< Data transfers start with least significant bit. */
kadonotakashi 0:8fdf9a60065b 85 } spi_shift_direction_t;
kadonotakashi 0:8fdf9a60065b 86
kadonotakashi 0:8fdf9a60065b 87 /*! @brief SPI slave select output mode options.*/
kadonotakashi 0:8fdf9a60065b 88 typedef enum _spi_ss_output_mode
kadonotakashi 0:8fdf9a60065b 89 {
kadonotakashi 0:8fdf9a60065b 90 kSPI_SlaveSelectAsGpio = 0x0U, /*!< Slave select pin configured as GPIO. */
kadonotakashi 0:8fdf9a60065b 91 kSPI_SlaveSelectFaultInput = 0x2U, /*!< Slave select pin configured for fault detection. */
kadonotakashi 0:8fdf9a60065b 92 kSPI_SlaveSelectAutomaticOutput = 0x3U /*!< Slave select pin configured for automatic SPI output. */
kadonotakashi 0:8fdf9a60065b 93 } spi_ss_output_mode_t;
kadonotakashi 0:8fdf9a60065b 94
kadonotakashi 0:8fdf9a60065b 95 /*! @brief SPI pin mode options.*/
kadonotakashi 0:8fdf9a60065b 96 typedef enum _spi_pin_mode
kadonotakashi 0:8fdf9a60065b 97 {
kadonotakashi 0:8fdf9a60065b 98 kSPI_PinModeNormal = 0x0U, /*!< Pins operate in normal, single-direction mode.*/
kadonotakashi 0:8fdf9a60065b 99 kSPI_PinModeInput = 0x1U, /*!< Bidirectional mode. Master: MOSI pin is input;
kadonotakashi 0:8fdf9a60065b 100 * Slave: MISO pin is input. */
kadonotakashi 0:8fdf9a60065b 101 kSPI_PinModeOutput = 0x3U /*!< Bidirectional mode. Master: MOSI pin is output;
kadonotakashi 0:8fdf9a60065b 102 * Slave: MISO pin is output. */
kadonotakashi 0:8fdf9a60065b 103 } spi_pin_mode_t;
kadonotakashi 0:8fdf9a60065b 104
kadonotakashi 0:8fdf9a60065b 105 /*! @brief SPI data length mode options.*/
kadonotakashi 0:8fdf9a60065b 106 typedef enum _spi_data_bitcount_mode
kadonotakashi 0:8fdf9a60065b 107 {
kadonotakashi 0:8fdf9a60065b 108 kSPI_8BitMode = 0x0U, /*!< 8-bit data transmission mode*/
kadonotakashi 0:8fdf9a60065b 109 kSPI_16BitMode /*!< 16-bit data transmission mode*/
kadonotakashi 0:8fdf9a60065b 110 } spi_data_bitcount_mode_t;
kadonotakashi 0:8fdf9a60065b 111
kadonotakashi 0:8fdf9a60065b 112 /*! @brief SPI interrupt sources.*/
kadonotakashi 0:8fdf9a60065b 113 enum _spi_interrupt_enable
kadonotakashi 0:8fdf9a60065b 114 {
kadonotakashi 0:8fdf9a60065b 115 kSPI_RxFullAndModfInterruptEnable = 0x1U, /*!< Receive buffer full (SPRF) and mode fault (MODF) interrupt */
kadonotakashi 0:8fdf9a60065b 116 kSPI_TxEmptyInterruptEnable = 0x2U, /*!< Transmit buffer empty interrupt */
kadonotakashi 0:8fdf9a60065b 117 kSPI_MatchInterruptEnable = 0x4U, /*!< Match interrupt */
kadonotakashi 0:8fdf9a60065b 118 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
kadonotakashi 0:8fdf9a60065b 119 kSPI_RxFifoNearFullInterruptEnable = 0x8U, /*!< Receive FIFO nearly full interrupt */
kadonotakashi 0:8fdf9a60065b 120 kSPI_TxFifoNearEmptyInterruptEnable = 0x10U, /*!< Transmit FIFO nearly empty interrupt */
kadonotakashi 0:8fdf9a60065b 121 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
kadonotakashi 0:8fdf9a60065b 122 };
kadonotakashi 0:8fdf9a60065b 123
kadonotakashi 0:8fdf9a60065b 124 /*! @brief SPI status flags.*/
kadonotakashi 0:8fdf9a60065b 125 enum _spi_flags
kadonotakashi 0:8fdf9a60065b 126 {
kadonotakashi 0:8fdf9a60065b 127 kSPI_RxBufferFullFlag = SPI_S_SPRF_MASK, /*!< Read buffer full flag */
kadonotakashi 0:8fdf9a60065b 128 kSPI_MatchFlag = SPI_S_SPMF_MASK, /*!< Match flag */
kadonotakashi 0:8fdf9a60065b 129 kSPI_TxBufferEmptyFlag = SPI_S_SPTEF_MASK, /*!< Transmit buffer empty flag */
kadonotakashi 0:8fdf9a60065b 130 kSPI_ModeFaultFlag = SPI_S_MODF_MASK, /*!< Mode fault flag */
kadonotakashi 0:8fdf9a60065b 131 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
kadonotakashi 0:8fdf9a60065b 132 kSPI_RxFifoNearFullFlag = SPI_S_RNFULLF_MASK, /*!< Rx FIFO near full */
kadonotakashi 0:8fdf9a60065b 133 kSPI_TxFifoNearEmptyFlag = SPI_S_TNEAREF_MASK, /*!< Tx FIFO near empty */
kadonotakashi 0:8fdf9a60065b 134 kSPI_TxFifoFullFlag = SPI_S_TXFULLF_MASK, /*!< Tx FIFO full */
kadonotakashi 0:8fdf9a60065b 135 kSPI_RxFifoEmptyFlag = SPI_S_RFIFOEF_MASK, /*!< Rx FIFO empty */
kadonotakashi 0:8fdf9a60065b 136 kSPI_TxFifoError = SPI_CI_TXFERR_MASK << 8U, /*!< Tx FIFO error */
kadonotakashi 0:8fdf9a60065b 137 kSPI_RxFifoError = SPI_CI_RXFERR_MASK << 8U, /*!< Rx FIFO error */
kadonotakashi 0:8fdf9a60065b 138 kSPI_TxOverflow = SPI_CI_TXFOF_MASK << 8U, /*!< Tx FIFO Overflow */
kadonotakashi 0:8fdf9a60065b 139 kSPI_RxOverflow = SPI_CI_RXFOF_MASK << 8U /*!< Rx FIFO Overflow */
kadonotakashi 0:8fdf9a60065b 140 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
kadonotakashi 0:8fdf9a60065b 141 };
kadonotakashi 0:8fdf9a60065b 142
kadonotakashi 0:8fdf9a60065b 143 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
kadonotakashi 0:8fdf9a60065b 144 /*! @brief SPI FIFO write-1-to-clear interrupt flags.*/
kadonotakashi 0:8fdf9a60065b 145 typedef enum _spi_w1c_interrupt
kadonotakashi 0:8fdf9a60065b 146 {
kadonotakashi 0:8fdf9a60065b 147 kSPI_RxFifoFullClearInterrupt = SPI_CI_SPRFCI_MASK, /*!< Receive FIFO full interrupt */
kadonotakashi 0:8fdf9a60065b 148 kSPI_TxFifoEmptyClearInterrupt = SPI_CI_SPTEFCI_MASK, /*!< Transmit FIFO empty interrupt */
kadonotakashi 0:8fdf9a60065b 149 kSPI_RxNearFullClearInterrupt = SPI_CI_RNFULLFCI_MASK, /*!< Receive FIFO nearly full interrupt */
kadonotakashi 0:8fdf9a60065b 150 kSPI_TxNearEmptyClearInterrupt = SPI_CI_TNEAREFCI_MASK /*!< Transmit FIFO nearly empty interrupt */
kadonotakashi 0:8fdf9a60065b 151 } spi_w1c_interrupt_t;
kadonotakashi 0:8fdf9a60065b 152
kadonotakashi 0:8fdf9a60065b 153 /*! @brief SPI TX FIFO watermark settings.*/
kadonotakashi 0:8fdf9a60065b 154 typedef enum _spi_txfifo_watermark
kadonotakashi 0:8fdf9a60065b 155 {
kadonotakashi 0:8fdf9a60065b 156 kSPI_TxFifoOneFourthEmpty = 0, /*!< SPI tx watermark at 1/4 FIFO size */
kadonotakashi 0:8fdf9a60065b 157 kSPI_TxFifoOneHalfEmpty = 1 /*!< SPI tx watermark at 1/2 FIFO size */
kadonotakashi 0:8fdf9a60065b 158 } spi_txfifo_watermark_t;
kadonotakashi 0:8fdf9a60065b 159
kadonotakashi 0:8fdf9a60065b 160 /*! @brief SPI RX FIFO watermark settings.*/
kadonotakashi 0:8fdf9a60065b 161 typedef enum _spi_rxfifo_watermark
kadonotakashi 0:8fdf9a60065b 162 {
kadonotakashi 0:8fdf9a60065b 163 kSPI_RxFifoThreeFourthsFull = 0, /*!< SPI rx watermark at 3/4 FIFO size */
kadonotakashi 0:8fdf9a60065b 164 kSPI_RxFifoOneHalfFull = 1 /*!< SPI rx watermark at 1/2 FIFO size */
kadonotakashi 0:8fdf9a60065b 165 } spi_rxfifo_watermark_t;
kadonotakashi 0:8fdf9a60065b 166 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
kadonotakashi 0:8fdf9a60065b 167
kadonotakashi 0:8fdf9a60065b 168 #if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT
kadonotakashi 0:8fdf9a60065b 169 /*! @brief SPI DMA source*/
kadonotakashi 0:8fdf9a60065b 170 enum _spi_dma_enable_t
kadonotakashi 0:8fdf9a60065b 171 {
kadonotakashi 0:8fdf9a60065b 172 kSPI_TxDmaEnable = SPI_C2_TXDMAE_MASK, /*!< Tx DMA request source */
kadonotakashi 0:8fdf9a60065b 173 kSPI_RxDmaEnable = SPI_C2_RXDMAE_MASK, /*!< Rx DMA request source */
kadonotakashi 0:8fdf9a60065b 174 kSPI_DmaAllEnable = (SPI_C2_TXDMAE_MASK | SPI_C2_RXDMAE_MASK) /*!< All DMA request source*/
kadonotakashi 0:8fdf9a60065b 175 };
kadonotakashi 0:8fdf9a60065b 176 #endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */
kadonotakashi 0:8fdf9a60065b 177
kadonotakashi 0:8fdf9a60065b 178 /*! @brief SPI master user configure structure.*/
kadonotakashi 0:8fdf9a60065b 179 typedef struct _spi_master_config
kadonotakashi 0:8fdf9a60065b 180 {
kadonotakashi 0:8fdf9a60065b 181 bool enableMaster; /*!< Enable SPI at initialization time */
kadonotakashi 0:8fdf9a60065b 182 bool enableStopInWaitMode; /*!< SPI stop in wait mode */
kadonotakashi 0:8fdf9a60065b 183 spi_clock_polarity_t polarity; /*!< Clock polarity */
kadonotakashi 0:8fdf9a60065b 184 spi_clock_phase_t phase; /*!< Clock phase */
kadonotakashi 0:8fdf9a60065b 185 spi_shift_direction_t direction; /*!< MSB or LSB */
kadonotakashi 0:8fdf9a60065b 186 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
kadonotakashi 0:8fdf9a60065b 187 spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode */
kadonotakashi 0:8fdf9a60065b 188 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
kadonotakashi 0:8fdf9a60065b 189 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
kadonotakashi 0:8fdf9a60065b 190 spi_txfifo_watermark_t txWatermark; /*!< Tx watermark settings */
kadonotakashi 0:8fdf9a60065b 191 spi_rxfifo_watermark_t rxWatermark; /*!< Rx watermark settings */
kadonotakashi 0:8fdf9a60065b 192 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
kadonotakashi 0:8fdf9a60065b 193 spi_ss_output_mode_t outputMode; /*!< SS pin setting */
kadonotakashi 0:8fdf9a60065b 194 spi_pin_mode_t pinMode; /*!< SPI pin mode select */
kadonotakashi 0:8fdf9a60065b 195 uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */
kadonotakashi 0:8fdf9a60065b 196 } spi_master_config_t;
kadonotakashi 0:8fdf9a60065b 197
kadonotakashi 0:8fdf9a60065b 198 /*! @brief SPI slave user configure structure.*/
kadonotakashi 0:8fdf9a60065b 199 typedef struct _spi_slave_config
kadonotakashi 0:8fdf9a60065b 200 {
kadonotakashi 0:8fdf9a60065b 201 bool enableSlave; /*!< Enable SPI at initialization time */
kadonotakashi 0:8fdf9a60065b 202 bool enableStopInWaitMode; /*!< SPI stop in wait mode */
kadonotakashi 0:8fdf9a60065b 203 spi_clock_polarity_t polarity; /*!< Clock polarity */
kadonotakashi 0:8fdf9a60065b 204 spi_clock_phase_t phase; /*!< Clock phase */
kadonotakashi 0:8fdf9a60065b 205 spi_shift_direction_t direction; /*!< MSB or LSB */
kadonotakashi 0:8fdf9a60065b 206 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
kadonotakashi 0:8fdf9a60065b 207 spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode */
kadonotakashi 0:8fdf9a60065b 208 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
kadonotakashi 0:8fdf9a60065b 209 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
kadonotakashi 0:8fdf9a60065b 210 spi_txfifo_watermark_t txWatermark; /*!< Tx watermark settings */
kadonotakashi 0:8fdf9a60065b 211 spi_rxfifo_watermark_t rxWatermark; /*!< Rx watermark settings */
kadonotakashi 0:8fdf9a60065b 212 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
kadonotakashi 0:8fdf9a60065b 213 } spi_slave_config_t;
kadonotakashi 0:8fdf9a60065b 214
kadonotakashi 0:8fdf9a60065b 215 /*! @brief SPI transfer structure */
kadonotakashi 0:8fdf9a60065b 216 typedef struct _spi_transfer
kadonotakashi 0:8fdf9a60065b 217 {
kadonotakashi 0:8fdf9a60065b 218 uint8_t *txData; /*!< Send buffer */
kadonotakashi 0:8fdf9a60065b 219 uint8_t *rxData; /*!< Receive buffer */
kadonotakashi 0:8fdf9a60065b 220 size_t dataSize; /*!< Transfer bytes */
kadonotakashi 0:8fdf9a60065b 221 uint32_t flags; /*!< SPI control flag, useless to SPI.*/
kadonotakashi 0:8fdf9a60065b 222 } spi_transfer_t;
kadonotakashi 0:8fdf9a60065b 223
kadonotakashi 0:8fdf9a60065b 224 typedef struct _spi_master_handle spi_master_handle_t;
kadonotakashi 0:8fdf9a60065b 225
kadonotakashi 0:8fdf9a60065b 226 /*! @brief Slave handle is the same with master handle */
kadonotakashi 0:8fdf9a60065b 227 typedef spi_master_handle_t spi_slave_handle_t;
kadonotakashi 0:8fdf9a60065b 228
kadonotakashi 0:8fdf9a60065b 229 /*! @brief SPI master callback for finished transmit */
kadonotakashi 0:8fdf9a60065b 230 typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
kadonotakashi 0:8fdf9a60065b 231
kadonotakashi 0:8fdf9a60065b 232 /*! @brief SPI master callback for finished transmit */
kadonotakashi 0:8fdf9a60065b 233 typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
kadonotakashi 0:8fdf9a60065b 234
kadonotakashi 0:8fdf9a60065b 235 /*! @brief SPI transfer handle structure */
kadonotakashi 0:8fdf9a60065b 236 struct _spi_master_handle
kadonotakashi 0:8fdf9a60065b 237 {
kadonotakashi 0:8fdf9a60065b 238 uint8_t *volatile txData; /*!< Transfer buffer */
kadonotakashi 0:8fdf9a60065b 239 uint8_t *volatile rxData; /*!< Receive buffer */
kadonotakashi 0:8fdf9a60065b 240 volatile size_t txRemainingBytes; /*!< Send data remaining in bytes */
kadonotakashi 0:8fdf9a60065b 241 volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes */
kadonotakashi 0:8fdf9a60065b 242 volatile uint32_t state; /*!< SPI internal state */
kadonotakashi 0:8fdf9a60065b 243 size_t transferSize; /*!< Bytes to be transferred */
kadonotakashi 0:8fdf9a60065b 244 uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */
kadonotakashi 0:8fdf9a60065b 245 uint8_t watermark; /*!< Watermark value for SPI transfer */
kadonotakashi 0:8fdf9a60065b 246 spi_master_callback_t callback; /*!< SPI callback */
kadonotakashi 0:8fdf9a60065b 247 void *userData; /*!< Callback parameter */
kadonotakashi 0:8fdf9a60065b 248 };
kadonotakashi 0:8fdf9a60065b 249
kadonotakashi 0:8fdf9a60065b 250 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 251 extern "C" {
kadonotakashi 0:8fdf9a60065b 252 #endif
kadonotakashi 0:8fdf9a60065b 253 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 254 * APIs
kadonotakashi 0:8fdf9a60065b 255 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 256 /*!
kadonotakashi 0:8fdf9a60065b 257 * @name Initialization and deinitialization
kadonotakashi 0:8fdf9a60065b 258 * @{
kadonotakashi 0:8fdf9a60065b 259 */
kadonotakashi 0:8fdf9a60065b 260
kadonotakashi 0:8fdf9a60065b 261 /*!
kadonotakashi 0:8fdf9a60065b 262 * @brief Sets the SPI master configuration structure to default values.
kadonotakashi 0:8fdf9a60065b 263 *
kadonotakashi 0:8fdf9a60065b 264 * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
kadonotakashi 0:8fdf9a60065b 265 * User may use the initialized structure unchanged in SPI_MasterInit(), or modify
kadonotakashi 0:8fdf9a60065b 266 * some fields of the structure before calling SPI_MasterInit(). After calling this API,
kadonotakashi 0:8fdf9a60065b 267 * the master is ready to transfer.
kadonotakashi 0:8fdf9a60065b 268 * Example:
kadonotakashi 0:8fdf9a60065b 269 @code
kadonotakashi 0:8fdf9a60065b 270 spi_master_config_t config;
kadonotakashi 0:8fdf9a60065b 271 SPI_MasterGetDefaultConfig(&config);
kadonotakashi 0:8fdf9a60065b 272 @endcode
kadonotakashi 0:8fdf9a60065b 273 *
kadonotakashi 0:8fdf9a60065b 274 * @param config pointer to master config structure
kadonotakashi 0:8fdf9a60065b 275 */
kadonotakashi 0:8fdf9a60065b 276 void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
kadonotakashi 0:8fdf9a60065b 277
kadonotakashi 0:8fdf9a60065b 278 /*!
kadonotakashi 0:8fdf9a60065b 279 * @brief Initializes the SPI with master configuration.
kadonotakashi 0:8fdf9a60065b 280 *
kadonotakashi 0:8fdf9a60065b 281 * The configuration structure can be filled by user from scratch, or be set with default
kadonotakashi 0:8fdf9a60065b 282 * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
kadonotakashi 0:8fdf9a60065b 283 * Example
kadonotakashi 0:8fdf9a60065b 284 @code
kadonotakashi 0:8fdf9a60065b 285 spi_master_config_t config = {
kadonotakashi 0:8fdf9a60065b 286 .baudRate_Bps = 400000,
kadonotakashi 0:8fdf9a60065b 287 ...
kadonotakashi 0:8fdf9a60065b 288 };
kadonotakashi 0:8fdf9a60065b 289 SPI_MasterInit(SPI0, &config);
kadonotakashi 0:8fdf9a60065b 290 @endcode
kadonotakashi 0:8fdf9a60065b 291 *
kadonotakashi 0:8fdf9a60065b 292 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 293 * @param config pointer to master configuration structure
kadonotakashi 0:8fdf9a60065b 294 * @param srcClock_Hz Source clock frequency.
kadonotakashi 0:8fdf9a60065b 295 */
kadonotakashi 0:8fdf9a60065b 296 void SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
kadonotakashi 0:8fdf9a60065b 297
kadonotakashi 0:8fdf9a60065b 298 /*!
kadonotakashi 0:8fdf9a60065b 299 * @brief Sets the SPI slave configuration structure to default values.
kadonotakashi 0:8fdf9a60065b 300 *
kadonotakashi 0:8fdf9a60065b 301 * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
kadonotakashi 0:8fdf9a60065b 302 * Modify some fields of the structure before calling SPI_SlaveInit().
kadonotakashi 0:8fdf9a60065b 303 * Example:
kadonotakashi 0:8fdf9a60065b 304 @code
kadonotakashi 0:8fdf9a60065b 305 spi_slave_config_t config;
kadonotakashi 0:8fdf9a60065b 306 SPI_SlaveGetDefaultConfig(&config);
kadonotakashi 0:8fdf9a60065b 307 @endcode
kadonotakashi 0:8fdf9a60065b 308 *
kadonotakashi 0:8fdf9a60065b 309 * @param config pointer to slave configuration structure
kadonotakashi 0:8fdf9a60065b 310 */
kadonotakashi 0:8fdf9a60065b 311 void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
kadonotakashi 0:8fdf9a60065b 312
kadonotakashi 0:8fdf9a60065b 313 /*!
kadonotakashi 0:8fdf9a60065b 314 * @brief Initializes the SPI with slave configuration.
kadonotakashi 0:8fdf9a60065b 315 *
kadonotakashi 0:8fdf9a60065b 316 * The configuration structure can be filled by user from scratch or be set with
kadonotakashi 0:8fdf9a60065b 317 * default values by SPI_SlaveGetDefaultConfig().
kadonotakashi 0:8fdf9a60065b 318 * After calling this API, the slave is ready to transfer.
kadonotakashi 0:8fdf9a60065b 319 * Example
kadonotakashi 0:8fdf9a60065b 320 @code
kadonotakashi 0:8fdf9a60065b 321 spi_slave_config_t config = {
kadonotakashi 0:8fdf9a60065b 322 .polarity = kSPIClockPolarity_ActiveHigh;
kadonotakashi 0:8fdf9a60065b 323 .phase = kSPIClockPhase_FirstEdge;
kadonotakashi 0:8fdf9a60065b 324 .direction = kSPIMsbFirst;
kadonotakashi 0:8fdf9a60065b 325 ...
kadonotakashi 0:8fdf9a60065b 326 };
kadonotakashi 0:8fdf9a60065b 327 SPI_MasterInit(SPI0, &config);
kadonotakashi 0:8fdf9a60065b 328 @endcode
kadonotakashi 0:8fdf9a60065b 329 *
kadonotakashi 0:8fdf9a60065b 330 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 331 * @param config pointer to master configuration structure
kadonotakashi 0:8fdf9a60065b 332 */
kadonotakashi 0:8fdf9a60065b 333 void SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
kadonotakashi 0:8fdf9a60065b 334
kadonotakashi 0:8fdf9a60065b 335 /*!
kadonotakashi 0:8fdf9a60065b 336 * @brief De-initializes the SPI.
kadonotakashi 0:8fdf9a60065b 337 *
kadonotakashi 0:8fdf9a60065b 338 * Calling this API resets the SPI module, gates the SPI clock.
kadonotakashi 0:8fdf9a60065b 339 * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
kadonotakashi 0:8fdf9a60065b 340 *
kadonotakashi 0:8fdf9a60065b 341 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 342 */
kadonotakashi 0:8fdf9a60065b 343 void SPI_Deinit(SPI_Type *base);
kadonotakashi 0:8fdf9a60065b 344
kadonotakashi 0:8fdf9a60065b 345 /*!
kadonotakashi 0:8fdf9a60065b 346 * @brief Enables or disables the SPI.
kadonotakashi 0:8fdf9a60065b 347 *
kadonotakashi 0:8fdf9a60065b 348 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 349 * @param enable pass true to enable module, false to disable module
kadonotakashi 0:8fdf9a60065b 350 */
kadonotakashi 0:8fdf9a60065b 351 static inline void SPI_Enable(SPI_Type *base, bool enable)
kadonotakashi 0:8fdf9a60065b 352 {
kadonotakashi 0:8fdf9a60065b 353 if (enable)
kadonotakashi 0:8fdf9a60065b 354 {
kadonotakashi 0:8fdf9a60065b 355 base->C1 |= SPI_C1_SPE_MASK;
kadonotakashi 0:8fdf9a60065b 356 }
kadonotakashi 0:8fdf9a60065b 357 else
kadonotakashi 0:8fdf9a60065b 358 {
kadonotakashi 0:8fdf9a60065b 359 base->C1 &= ~SPI_C1_SPE_MASK;
kadonotakashi 0:8fdf9a60065b 360 }
kadonotakashi 0:8fdf9a60065b 361 }
kadonotakashi 0:8fdf9a60065b 362
kadonotakashi 0:8fdf9a60065b 363 /*! @} */
kadonotakashi 0:8fdf9a60065b 364
kadonotakashi 0:8fdf9a60065b 365 /*!
kadonotakashi 0:8fdf9a60065b 366 * @name Status
kadonotakashi 0:8fdf9a60065b 367 * @{
kadonotakashi 0:8fdf9a60065b 368 */
kadonotakashi 0:8fdf9a60065b 369
kadonotakashi 0:8fdf9a60065b 370 /*!
kadonotakashi 0:8fdf9a60065b 371 * @brief Gets the status flag.
kadonotakashi 0:8fdf9a60065b 372 *
kadonotakashi 0:8fdf9a60065b 373 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 374 * @return SPI Status, use status flag to AND #_spi_flags could get the related status.
kadonotakashi 0:8fdf9a60065b 375 */
kadonotakashi 0:8fdf9a60065b 376 uint32_t SPI_GetStatusFlags(SPI_Type *base);
kadonotakashi 0:8fdf9a60065b 377
kadonotakashi 0:8fdf9a60065b 378 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
kadonotakashi 0:8fdf9a60065b 379 /*!
kadonotakashi 0:8fdf9a60065b 380 * @brief Clear the interrupt if enable INCTLR.
kadonotakashi 0:8fdf9a60065b 381 *
kadonotakashi 0:8fdf9a60065b 382 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 383 * @param interrupt Interrupt need to be cleared
kadonotakashi 0:8fdf9a60065b 384 * The parameter could be any combination of the following values:
kadonotakashi 0:8fdf9a60065b 385 * @arg kSPIRxFifoFullClearInt
kadonotakashi 0:8fdf9a60065b 386 * @arg kSPITxFifoEmptyClearInt
kadonotakashi 0:8fdf9a60065b 387 * @arg kSPIRxNearFullClearInt
kadonotakashi 0:8fdf9a60065b 388 * @arg kSPITxNearEmptyClearInt
kadonotakashi 0:8fdf9a60065b 389 */
kadonotakashi 0:8fdf9a60065b 390 static inline void SPI_ClearInterrupt(SPI_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 391 {
kadonotakashi 0:8fdf9a60065b 392 base->CI |= mask;
kadonotakashi 0:8fdf9a60065b 393 }
kadonotakashi 0:8fdf9a60065b 394 #endif /* FSL_FEATURE_SPI_HAS_FIFO */
kadonotakashi 0:8fdf9a60065b 395
kadonotakashi 0:8fdf9a60065b 396 /*! @} */
kadonotakashi 0:8fdf9a60065b 397
kadonotakashi 0:8fdf9a60065b 398 /*!
kadonotakashi 0:8fdf9a60065b 399 * @name Interrupts
kadonotakashi 0:8fdf9a60065b 400 * @{
kadonotakashi 0:8fdf9a60065b 401 */
kadonotakashi 0:8fdf9a60065b 402
kadonotakashi 0:8fdf9a60065b 403 /*!
kadonotakashi 0:8fdf9a60065b 404 * @brief Enables the interrupt for the SPI.
kadonotakashi 0:8fdf9a60065b 405 *
kadonotakashi 0:8fdf9a60065b 406 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 407 * @param mask SPI interrupt source. The parameter can be any combination of the following values:
kadonotakashi 0:8fdf9a60065b 408 * @arg kSPI_RxFullAndModfInterruptEnable
kadonotakashi 0:8fdf9a60065b 409 * @arg kSPI_TxEmptyInterruptEnable
kadonotakashi 0:8fdf9a60065b 410 * @arg kSPI_MatchInterruptEnable
kadonotakashi 0:8fdf9a60065b 411 * @arg kSPI_RxFifoNearFullInterruptEnable
kadonotakashi 0:8fdf9a60065b 412 * @arg kSPI_TxFifoNearEmptyInterruptEnable
kadonotakashi 0:8fdf9a60065b 413 */
kadonotakashi 0:8fdf9a60065b 414 void SPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
kadonotakashi 0:8fdf9a60065b 415
kadonotakashi 0:8fdf9a60065b 416 /*!
kadonotakashi 0:8fdf9a60065b 417 * @brief Disables the interrupt for the SPI.
kadonotakashi 0:8fdf9a60065b 418 *
kadonotakashi 0:8fdf9a60065b 419 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 420 * @param mask SPI interrupt source. The parameter can be any combination of the following values:
kadonotakashi 0:8fdf9a60065b 421 * @arg kSPI_RxFullAndModfInterruptEnable
kadonotakashi 0:8fdf9a60065b 422 * @arg kSPI_TxEmptyInterruptEnable
kadonotakashi 0:8fdf9a60065b 423 * @arg kSPI_MatchInterruptEnable
kadonotakashi 0:8fdf9a60065b 424 * @arg kSPI_RxFifoNearFullInterruptEnable
kadonotakashi 0:8fdf9a60065b 425 * @arg kSPI_TxFifoNearEmptyInterruptEnable
kadonotakashi 0:8fdf9a60065b 426 */
kadonotakashi 0:8fdf9a60065b 427 void SPI_DisableInterrupts(SPI_Type *base, uint32_t mask);
kadonotakashi 0:8fdf9a60065b 428
kadonotakashi 0:8fdf9a60065b 429 /*! @} */
kadonotakashi 0:8fdf9a60065b 430
kadonotakashi 0:8fdf9a60065b 431 /*!
kadonotakashi 0:8fdf9a60065b 432 * @name DMA Control
kadonotakashi 0:8fdf9a60065b 433 * @{
kadonotakashi 0:8fdf9a60065b 434 */
kadonotakashi 0:8fdf9a60065b 435
kadonotakashi 0:8fdf9a60065b 436 #if defined(FSL_FEATURE_SPI_HAS_DMA_SUPPORT) && FSL_FEATURE_SPI_HAS_DMA_SUPPORT
kadonotakashi 0:8fdf9a60065b 437 /*!
kadonotakashi 0:8fdf9a60065b 438 * @brief Enables the DMA source for SPI.
kadonotakashi 0:8fdf9a60065b 439 *
kadonotakashi 0:8fdf9a60065b 440 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 441 * @param source SPI DMA source.
kadonotakashi 0:8fdf9a60065b 442 * @param enable True means enable DMA, false means disable DMA
kadonotakashi 0:8fdf9a60065b 443 */
kadonotakashi 0:8fdf9a60065b 444 static inline void SPI_EnableDMA(SPI_Type *base, uint32_t mask, bool enable)
kadonotakashi 0:8fdf9a60065b 445 {
kadonotakashi 0:8fdf9a60065b 446 if (enable)
kadonotakashi 0:8fdf9a60065b 447 {
kadonotakashi 0:8fdf9a60065b 448 base->C2 |= mask;
kadonotakashi 0:8fdf9a60065b 449 }
kadonotakashi 0:8fdf9a60065b 450 else
kadonotakashi 0:8fdf9a60065b 451 {
kadonotakashi 0:8fdf9a60065b 452 base->C2 &= ~mask;
kadonotakashi 0:8fdf9a60065b 453 }
kadonotakashi 0:8fdf9a60065b 454 }
kadonotakashi 0:8fdf9a60065b 455 #endif /* FSL_FEATURE_SPI_HAS_DMA_SUPPORT */
kadonotakashi 0:8fdf9a60065b 456
kadonotakashi 0:8fdf9a60065b 457 /*!
kadonotakashi 0:8fdf9a60065b 458 * @brief Gets the SPI tx/rx data register address.
kadonotakashi 0:8fdf9a60065b 459 *
kadonotakashi 0:8fdf9a60065b 460 * This API is used to provide a transfer address for the SPI DMA transfer configuration.
kadonotakashi 0:8fdf9a60065b 461 *
kadonotakashi 0:8fdf9a60065b 462 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 463 * @return data register address
kadonotakashi 0:8fdf9a60065b 464 */
kadonotakashi 0:8fdf9a60065b 465 static inline uint32_t SPI_GetDataRegisterAddress(SPI_Type *base)
kadonotakashi 0:8fdf9a60065b 466 {
kadonotakashi 0:8fdf9a60065b 467 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
kadonotakashi 0:8fdf9a60065b 468 return (uint32_t)(&(base->DL));
kadonotakashi 0:8fdf9a60065b 469 #else
kadonotakashi 0:8fdf9a60065b 470 return (uint32_t)(&(base->D));
kadonotakashi 0:8fdf9a60065b 471 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
kadonotakashi 0:8fdf9a60065b 472 }
kadonotakashi 0:8fdf9a60065b 473
kadonotakashi 0:8fdf9a60065b 474 /*! @} */
kadonotakashi 0:8fdf9a60065b 475
kadonotakashi 0:8fdf9a60065b 476 /*!
kadonotakashi 0:8fdf9a60065b 477 * @name Bus Operations
kadonotakashi 0:8fdf9a60065b 478 * @{
kadonotakashi 0:8fdf9a60065b 479 */
kadonotakashi 0:8fdf9a60065b 480
kadonotakashi 0:8fdf9a60065b 481 /*!
kadonotakashi 0:8fdf9a60065b 482 * @brief Sets the baud rate for SPI transfer. This is only used in master.
kadonotakashi 0:8fdf9a60065b 483 *
kadonotakashi 0:8fdf9a60065b 484 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 485 * @param baudRate_Bps baud rate needed in Hz.
kadonotakashi 0:8fdf9a60065b 486 * @param srcClock_Hz SPI source clock frequency in Hz.
kadonotakashi 0:8fdf9a60065b 487 */
kadonotakashi 0:8fdf9a60065b 488 void SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
kadonotakashi 0:8fdf9a60065b 489
kadonotakashi 0:8fdf9a60065b 490 /*!
kadonotakashi 0:8fdf9a60065b 491 * @brief Sets the match data for SPI.
kadonotakashi 0:8fdf9a60065b 492 *
kadonotakashi 0:8fdf9a60065b 493 * The match data is a hardware comparison value. When the value received in the SPI receive data
kadonotakashi 0:8fdf9a60065b 494 * buffer equals the hardware comparison value, the SPI Match Flag in the S register (S[SPMF]) sets.
kadonotakashi 0:8fdf9a60065b 495 * This can also generate an interrupt if the enable bit sets.
kadonotakashi 0:8fdf9a60065b 496 *
kadonotakashi 0:8fdf9a60065b 497 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 498 * @param matchData Match data.
kadonotakashi 0:8fdf9a60065b 499 */
kadonotakashi 0:8fdf9a60065b 500 static inline void SPI_SetMatchData(SPI_Type *base, uint32_t matchData)
kadonotakashi 0:8fdf9a60065b 501 {
kadonotakashi 0:8fdf9a60065b 502 #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS
kadonotakashi 0:8fdf9a60065b 503 base->ML = matchData & 0xFFU;
kadonotakashi 0:8fdf9a60065b 504 base->MH = (matchData >> 8U) & 0xFFU;
kadonotakashi 0:8fdf9a60065b 505 #else
kadonotakashi 0:8fdf9a60065b 506 base->M = matchData;
kadonotakashi 0:8fdf9a60065b 507 #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
kadonotakashi 0:8fdf9a60065b 508 }
kadonotakashi 0:8fdf9a60065b 509
kadonotakashi 0:8fdf9a60065b 510 #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO
kadonotakashi 0:8fdf9a60065b 511 /*!
kadonotakashi 0:8fdf9a60065b 512 * @brief Enables or disables the FIFO if there is a FIFO.
kadonotakashi 0:8fdf9a60065b 513 *
kadonotakashi 0:8fdf9a60065b 514 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 515 * @param enable True means enable FIFO, false means disable FIFO.
kadonotakashi 0:8fdf9a60065b 516 */
kadonotakashi 0:8fdf9a60065b 517 void SPI_EnableFIFO(SPI_Type *base, bool enable);
kadonotakashi 0:8fdf9a60065b 518 #endif
kadonotakashi 0:8fdf9a60065b 519
kadonotakashi 0:8fdf9a60065b 520 /*!
kadonotakashi 0:8fdf9a60065b 521 * @brief Sends a buffer of data bytes using a blocking method.
kadonotakashi 0:8fdf9a60065b 522 *
kadonotakashi 0:8fdf9a60065b 523 * @note This function blocks via polling until all bytes have been sent.
kadonotakashi 0:8fdf9a60065b 524 *
kadonotakashi 0:8fdf9a60065b 525 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 526 * @param buffer The data bytes to send
kadonotakashi 0:8fdf9a60065b 527 * @param size The number of data bytes to send
kadonotakashi 0:8fdf9a60065b 528 */
kadonotakashi 0:8fdf9a60065b 529 void SPI_WriteBlocking(SPI_Type *base, uint8_t *buffer, size_t size);
kadonotakashi 0:8fdf9a60065b 530
kadonotakashi 0:8fdf9a60065b 531 /*!
kadonotakashi 0:8fdf9a60065b 532 * @brief Writes a data into the SPI data register.
kadonotakashi 0:8fdf9a60065b 533 *
kadonotakashi 0:8fdf9a60065b 534 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 535 * @param data needs to be write.
kadonotakashi 0:8fdf9a60065b 536 */
kadonotakashi 0:8fdf9a60065b 537 void SPI_WriteData(SPI_Type *base, uint16_t data);
kadonotakashi 0:8fdf9a60065b 538
kadonotakashi 0:8fdf9a60065b 539 /*!
kadonotakashi 0:8fdf9a60065b 540 * @brief Gets a data from the SPI data register.
kadonotakashi 0:8fdf9a60065b 541 *
kadonotakashi 0:8fdf9a60065b 542 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 543 * @return Data in the register.
kadonotakashi 0:8fdf9a60065b 544 */
kadonotakashi 0:8fdf9a60065b 545 uint16_t SPI_ReadData(SPI_Type *base);
kadonotakashi 0:8fdf9a60065b 546
kadonotakashi 0:8fdf9a60065b 547 /*! @} */
kadonotakashi 0:8fdf9a60065b 548
kadonotakashi 0:8fdf9a60065b 549 /*!
kadonotakashi 0:8fdf9a60065b 550 * @name Transactional
kadonotakashi 0:8fdf9a60065b 551 * @{
kadonotakashi 0:8fdf9a60065b 552 */
kadonotakashi 0:8fdf9a60065b 553
kadonotakashi 0:8fdf9a60065b 554 /*!
kadonotakashi 0:8fdf9a60065b 555 * @brief Initializes the SPI master handle.
kadonotakashi 0:8fdf9a60065b 556 *
kadonotakashi 0:8fdf9a60065b 557 * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
kadonotakashi 0:8fdf9a60065b 558 * for a specified SPI instance, call this API once to get the initialized handle.
kadonotakashi 0:8fdf9a60065b 559 *
kadonotakashi 0:8fdf9a60065b 560 * @param base SPI peripheral base address.
kadonotakashi 0:8fdf9a60065b 561 * @param handle SPI handle pointer.
kadonotakashi 0:8fdf9a60065b 562 * @param callback Callback function.
kadonotakashi 0:8fdf9a60065b 563 * @param userData User data.
kadonotakashi 0:8fdf9a60065b 564 */
kadonotakashi 0:8fdf9a60065b 565 void SPI_MasterTransferCreateHandle(SPI_Type *base,
kadonotakashi 0:8fdf9a60065b 566 spi_master_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 567 spi_master_callback_t callback,
kadonotakashi 0:8fdf9a60065b 568 void *userData);
kadonotakashi 0:8fdf9a60065b 569
kadonotakashi 0:8fdf9a60065b 570 /*!
kadonotakashi 0:8fdf9a60065b 571 * @brief Transfers a block of data using a polling method.
kadonotakashi 0:8fdf9a60065b 572 *
kadonotakashi 0:8fdf9a60065b 573 * @param base SPI base pointer
kadonotakashi 0:8fdf9a60065b 574 * @param xfer pointer to spi_xfer_config_t structure
kadonotakashi 0:8fdf9a60065b 575 * @retval kStatus_Success Successfully start a transfer.
kadonotakashi 0:8fdf9a60065b 576 * @retval kStatus_InvalidArgument Input argument is invalid.
kadonotakashi 0:8fdf9a60065b 577 */
kadonotakashi 0:8fdf9a60065b 578 status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
kadonotakashi 0:8fdf9a60065b 579
kadonotakashi 0:8fdf9a60065b 580 /*!
kadonotakashi 0:8fdf9a60065b 581 * @brief Performs a non-blocking SPI interrupt transfer.
kadonotakashi 0:8fdf9a60065b 582 *
kadonotakashi 0:8fdf9a60065b 583 * @note The API immediately returns after transfer initialization is finished.
kadonotakashi 0:8fdf9a60065b 584 * Call SPI_GetStatusIRQ() to get the transfer status.
kadonotakashi 0:8fdf9a60065b 585 * @note If using the SPI with FIFO for the interrupt transfer, the transfer size is the integer times of the watermark.
kadonotakashi 0:8fdf9a60065b 586 * Otherwise,
kadonotakashi 0:8fdf9a60065b 587 * the last data may be lost because it cannot generate an interrupt request. Users can also call the functional API to
kadonotakashi 0:8fdf9a60065b 588 * get the last
kadonotakashi 0:8fdf9a60065b 589 * received data.
kadonotakashi 0:8fdf9a60065b 590 *
kadonotakashi 0:8fdf9a60065b 591 * @param base SPI peripheral base address.
kadonotakashi 0:8fdf9a60065b 592 * @param handle pointer to spi_master_handle_t structure which stores the transfer state
kadonotakashi 0:8fdf9a60065b 593 * @param xfer pointer to spi_xfer_config_t structure
kadonotakashi 0:8fdf9a60065b 594 * @retval kStatus_Success Successfully start a transfer.
kadonotakashi 0:8fdf9a60065b 595 * @retval kStatus_InvalidArgument Input argument is invalid.
kadonotakashi 0:8fdf9a60065b 596 * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
kadonotakashi 0:8fdf9a60065b 597 */
kadonotakashi 0:8fdf9a60065b 598 status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
kadonotakashi 0:8fdf9a60065b 599
kadonotakashi 0:8fdf9a60065b 600 /*!
kadonotakashi 0:8fdf9a60065b 601 * @brief Gets the bytes of the SPI interrupt transferred.
kadonotakashi 0:8fdf9a60065b 602 *
kadonotakashi 0:8fdf9a60065b 603 * @param base SPI peripheral base address.
kadonotakashi 0:8fdf9a60065b 604 * @param handle Pointer to SPI transfer handle, this should be a static variable.
kadonotakashi 0:8fdf9a60065b 605 * @param count Transferred bytes of SPI master.
kadonotakashi 0:8fdf9a60065b 606 * @retval kStatus_SPI_Success Succeed get the transfer count.
kadonotakashi 0:8fdf9a60065b 607 * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
kadonotakashi 0:8fdf9a60065b 608 */
kadonotakashi 0:8fdf9a60065b 609 status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
kadonotakashi 0:8fdf9a60065b 610
kadonotakashi 0:8fdf9a60065b 611 /*!
kadonotakashi 0:8fdf9a60065b 612 * @brief Aborts an SPI transfer using interrupt.
kadonotakashi 0:8fdf9a60065b 613 *
kadonotakashi 0:8fdf9a60065b 614 * @param base SPI peripheral base address.
kadonotakashi 0:8fdf9a60065b 615 * @param handle Pointer to SPI transfer handle, this should be a static variable.
kadonotakashi 0:8fdf9a60065b 616 */
kadonotakashi 0:8fdf9a60065b 617 void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
kadonotakashi 0:8fdf9a60065b 618
kadonotakashi 0:8fdf9a60065b 619 /*!
kadonotakashi 0:8fdf9a60065b 620 * @brief Interrupts the handler for the SPI.
kadonotakashi 0:8fdf9a60065b 621 *
kadonotakashi 0:8fdf9a60065b 622 * @param base SPI peripheral base address.
kadonotakashi 0:8fdf9a60065b 623 * @param handle pointer to spi_master_handle_t structure which stores the transfer state.
kadonotakashi 0:8fdf9a60065b 624 */
kadonotakashi 0:8fdf9a60065b 625 void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
kadonotakashi 0:8fdf9a60065b 626
kadonotakashi 0:8fdf9a60065b 627 /*!
kadonotakashi 0:8fdf9a60065b 628 * @brief Initializes the SPI slave handle.
kadonotakashi 0:8fdf9a60065b 629 *
kadonotakashi 0:8fdf9a60065b 630 * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
kadonotakashi 0:8fdf9a60065b 631 * for a specified SPI instance, call this API once to get the initialized handle.
kadonotakashi 0:8fdf9a60065b 632 *
kadonotakashi 0:8fdf9a60065b 633 * @param base SPI peripheral base address.
kadonotakashi 0:8fdf9a60065b 634 * @param handle SPI handle pointer.
kadonotakashi 0:8fdf9a60065b 635 * @param callback Callback function.
kadonotakashi 0:8fdf9a60065b 636 * @param userData User data.
kadonotakashi 0:8fdf9a60065b 637 */
kadonotakashi 0:8fdf9a60065b 638 void SPI_SlaveTransferCreateHandle(SPI_Type *base,
kadonotakashi 0:8fdf9a60065b 639 spi_slave_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 640 spi_slave_callback_t callback,
kadonotakashi 0:8fdf9a60065b 641 void *userData);
kadonotakashi 0:8fdf9a60065b 642
kadonotakashi 0:8fdf9a60065b 643 /*!
kadonotakashi 0:8fdf9a60065b 644 * @brief Performs a non-blocking SPI slave interrupt transfer.
kadonotakashi 0:8fdf9a60065b 645 *
kadonotakashi 0:8fdf9a60065b 646 * @note The API returns immediately after the transfer initialization is finished.
kadonotakashi 0:8fdf9a60065b 647 * Call SPI_GetStatusIRQ() to get the transfer status.
kadonotakashi 0:8fdf9a60065b 648 * @note If using the SPI with FIFO for the interrupt transfer, the transfer size is the integer times the watermark.
kadonotakashi 0:8fdf9a60065b 649 * Otherwise,
kadonotakashi 0:8fdf9a60065b 650 * the last data may be lost because it cannot generate an interrupt request. Call the functional API to get the last
kadonotakashi 0:8fdf9a60065b 651 * several
kadonotakashi 0:8fdf9a60065b 652 * receive data.
kadonotakashi 0:8fdf9a60065b 653 *
kadonotakashi 0:8fdf9a60065b 654 * @param base SPI peripheral base address.
kadonotakashi 0:8fdf9a60065b 655 * @param handle pointer to spi_master_handle_t structure which stores the transfer state
kadonotakashi 0:8fdf9a60065b 656 * @param xfer pointer to spi_xfer_config_t structure
kadonotakashi 0:8fdf9a60065b 657 * @retval kStatus_Success Successfully start a transfer.
kadonotakashi 0:8fdf9a60065b 658 * @retval kStatus_InvalidArgument Input argument is invalid.
kadonotakashi 0:8fdf9a60065b 659 * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
kadonotakashi 0:8fdf9a60065b 660 */
kadonotakashi 0:8fdf9a60065b 661 static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer)
kadonotakashi 0:8fdf9a60065b 662 {
kadonotakashi 0:8fdf9a60065b 663 return SPI_MasterTransferNonBlocking(base, handle, xfer);
kadonotakashi 0:8fdf9a60065b 664 }
kadonotakashi 0:8fdf9a60065b 665
kadonotakashi 0:8fdf9a60065b 666 /*!
kadonotakashi 0:8fdf9a60065b 667 * @brief Gets the bytes of the SPI interrupt transferred.
kadonotakashi 0:8fdf9a60065b 668 *
kadonotakashi 0:8fdf9a60065b 669 * @param base SPI peripheral base address.
kadonotakashi 0:8fdf9a60065b 670 * @param handle Pointer to SPI transfer handle, this should be a static variable.
kadonotakashi 0:8fdf9a60065b 671 * @param count Transferred bytes of SPI slave.
kadonotakashi 0:8fdf9a60065b 672 * @retval kStatus_SPI_Success Succeed get the transfer count.
kadonotakashi 0:8fdf9a60065b 673 * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
kadonotakashi 0:8fdf9a60065b 674 */
kadonotakashi 0:8fdf9a60065b 675 static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
kadonotakashi 0:8fdf9a60065b 676 {
kadonotakashi 0:8fdf9a60065b 677 return SPI_MasterTransferGetCount(base, handle, count);
kadonotakashi 0:8fdf9a60065b 678 }
kadonotakashi 0:8fdf9a60065b 679
kadonotakashi 0:8fdf9a60065b 680 /*!
kadonotakashi 0:8fdf9a60065b 681 * @brief Aborts an SPI slave transfer using interrupt.
kadonotakashi 0:8fdf9a60065b 682 *
kadonotakashi 0:8fdf9a60065b 683 * @param base SPI peripheral base address.
kadonotakashi 0:8fdf9a60065b 684 * @param handle Pointer to SPI transfer handle, this should be a static variable.
kadonotakashi 0:8fdf9a60065b 685 */
kadonotakashi 0:8fdf9a60065b 686 static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
kadonotakashi 0:8fdf9a60065b 687 {
kadonotakashi 0:8fdf9a60065b 688 SPI_MasterTransferAbort(base, handle);
kadonotakashi 0:8fdf9a60065b 689 }
kadonotakashi 0:8fdf9a60065b 690
kadonotakashi 0:8fdf9a60065b 691 /*!
kadonotakashi 0:8fdf9a60065b 692 * @brief Interrupts a handler for the SPI slave.
kadonotakashi 0:8fdf9a60065b 693 *
kadonotakashi 0:8fdf9a60065b 694 * @param base SPI peripheral base address.
kadonotakashi 0:8fdf9a60065b 695 * @param handle pointer to spi_slave_handle_t structure which stores the transfer state
kadonotakashi 0:8fdf9a60065b 696 */
kadonotakashi 0:8fdf9a60065b 697 void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle);
kadonotakashi 0:8fdf9a60065b 698
kadonotakashi 0:8fdf9a60065b 699 /*! @} */
kadonotakashi 0:8fdf9a60065b 700
kadonotakashi 0:8fdf9a60065b 701 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 702 }
kadonotakashi 0:8fdf9a60065b 703 #endif
kadonotakashi 0:8fdf9a60065b 704
kadonotakashi 0:8fdf9a60065b 705 /*! @} */
kadonotakashi 0:8fdf9a60065b 706
kadonotakashi 0:8fdf9a60065b 707 #endif /* _FSL_SPI_H_*/