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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_cmp.c@3:f3764f852aa8, 2018-10-11 (annotated)
- Committer:
- kadonotakashi
- Date:
- Thu Oct 11 02:27:46 2018 +0000
- Revision:
- 3:f3764f852aa8
- Parent:
- 0:8fdf9a60065b
Nucreo 446 + SSD1331 test version;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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kadonotakashi | 0:8fdf9a60065b | 1 | /* |
kadonotakashi | 0:8fdf9a60065b | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
kadonotakashi | 0:8fdf9a60065b | 3 | * All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 4 | * |
kadonotakashi | 0:8fdf9a60065b | 5 | * Redistribution and use in source and binary forms, with or without modification, |
kadonotakashi | 0:8fdf9a60065b | 6 | * are permitted provided that the following conditions are met: |
kadonotakashi | 0:8fdf9a60065b | 7 | * |
kadonotakashi | 0:8fdf9a60065b | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
kadonotakashi | 0:8fdf9a60065b | 9 | * of conditions and the following disclaimer. |
kadonotakashi | 0:8fdf9a60065b | 10 | * |
kadonotakashi | 0:8fdf9a60065b | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
kadonotakashi | 0:8fdf9a60065b | 12 | * list of conditions and the following disclaimer in the documentation and/or |
kadonotakashi | 0:8fdf9a60065b | 13 | * other materials provided with the distribution. |
kadonotakashi | 0:8fdf9a60065b | 14 | * |
kadonotakashi | 0:8fdf9a60065b | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
kadonotakashi | 0:8fdf9a60065b | 16 | * contributors may be used to endorse or promote products derived from this |
kadonotakashi | 0:8fdf9a60065b | 17 | * software without specific prior written permission. |
kadonotakashi | 0:8fdf9a60065b | 18 | * |
kadonotakashi | 0:8fdf9a60065b | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
kadonotakashi | 0:8fdf9a60065b | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
kadonotakashi | 0:8fdf9a60065b | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
kadonotakashi | 0:8fdf9a60065b | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
kadonotakashi | 0:8fdf9a60065b | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
kadonotakashi | 0:8fdf9a60065b | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
kadonotakashi | 0:8fdf9a60065b | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
kadonotakashi | 0:8fdf9a60065b | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
kadonotakashi | 0:8fdf9a60065b | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
kadonotakashi | 0:8fdf9a60065b | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
kadonotakashi | 0:8fdf9a60065b | 29 | */ |
kadonotakashi | 0:8fdf9a60065b | 30 | |
kadonotakashi | 0:8fdf9a60065b | 31 | #include "fsl_cmp.h" |
kadonotakashi | 0:8fdf9a60065b | 32 | |
kadonotakashi | 0:8fdf9a60065b | 33 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 34 | * Prototypes |
kadonotakashi | 0:8fdf9a60065b | 35 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 36 | /*! |
kadonotakashi | 0:8fdf9a60065b | 37 | * @brief Get instance number for CMP module. |
kadonotakashi | 0:8fdf9a60065b | 38 | * |
kadonotakashi | 0:8fdf9a60065b | 39 | * @param base CMP peripheral base address |
kadonotakashi | 0:8fdf9a60065b | 40 | */ |
kadonotakashi | 0:8fdf9a60065b | 41 | static uint32_t CMP_GetInstance(CMP_Type *base); |
kadonotakashi | 0:8fdf9a60065b | 42 | |
kadonotakashi | 0:8fdf9a60065b | 43 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 44 | * Variables |
kadonotakashi | 0:8fdf9a60065b | 45 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 46 | /*! @brief Pointers to CMP bases for each instance. */ |
kadonotakashi | 0:8fdf9a60065b | 47 | static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS; |
kadonotakashi | 0:8fdf9a60065b | 48 | /*! @brief Pointers to CMP clocks for each instance. */ |
kadonotakashi | 0:8fdf9a60065b | 49 | const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS; |
kadonotakashi | 0:8fdf9a60065b | 50 | |
kadonotakashi | 0:8fdf9a60065b | 51 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 52 | * Codes |
kadonotakashi | 0:8fdf9a60065b | 53 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 54 | static uint32_t CMP_GetInstance(CMP_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 55 | { |
kadonotakashi | 0:8fdf9a60065b | 56 | uint32_t instance; |
kadonotakashi | 0:8fdf9a60065b | 57 | |
kadonotakashi | 0:8fdf9a60065b | 58 | /* Find the instance index from base address mappings. */ |
kadonotakashi | 0:8fdf9a60065b | 59 | for (instance = 0; instance < FSL_FEATURE_SOC_CMP_COUNT; instance++) |
kadonotakashi | 0:8fdf9a60065b | 60 | { |
kadonotakashi | 0:8fdf9a60065b | 61 | if (s_cmpBases[instance] == base) |
kadonotakashi | 0:8fdf9a60065b | 62 | { |
kadonotakashi | 0:8fdf9a60065b | 63 | break; |
kadonotakashi | 0:8fdf9a60065b | 64 | } |
kadonotakashi | 0:8fdf9a60065b | 65 | } |
kadonotakashi | 0:8fdf9a60065b | 66 | |
kadonotakashi | 0:8fdf9a60065b | 67 | assert(instance < FSL_FEATURE_SOC_CMP_COUNT); |
kadonotakashi | 0:8fdf9a60065b | 68 | |
kadonotakashi | 0:8fdf9a60065b | 69 | return instance; |
kadonotakashi | 0:8fdf9a60065b | 70 | } |
kadonotakashi | 0:8fdf9a60065b | 71 | |
kadonotakashi | 0:8fdf9a60065b | 72 | void CMP_Init(CMP_Type *base, const cmp_config_t *config) |
kadonotakashi | 0:8fdf9a60065b | 73 | { |
kadonotakashi | 0:8fdf9a60065b | 74 | assert(NULL != config); |
kadonotakashi | 0:8fdf9a60065b | 75 | |
kadonotakashi | 0:8fdf9a60065b | 76 | uint8_t tmp8; |
kadonotakashi | 0:8fdf9a60065b | 77 | |
kadonotakashi | 0:8fdf9a60065b | 78 | /* Enable the clock. */ |
kadonotakashi | 0:8fdf9a60065b | 79 | CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]); |
kadonotakashi | 0:8fdf9a60065b | 80 | |
kadonotakashi | 0:8fdf9a60065b | 81 | /* Configure. */ |
kadonotakashi | 0:8fdf9a60065b | 82 | CMP_Enable(base, false); /* Disable the CMP module during configuring. */ |
kadonotakashi | 0:8fdf9a60065b | 83 | /* CMPx_CR1. */ |
kadonotakashi | 0:8fdf9a60065b | 84 | tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK); |
kadonotakashi | 0:8fdf9a60065b | 85 | if (config->enableHighSpeed) |
kadonotakashi | 0:8fdf9a60065b | 86 | { |
kadonotakashi | 0:8fdf9a60065b | 87 | tmp8 |= CMP_CR1_PMODE_MASK; |
kadonotakashi | 0:8fdf9a60065b | 88 | } |
kadonotakashi | 0:8fdf9a60065b | 89 | if (config->enableInvertOutput) |
kadonotakashi | 0:8fdf9a60065b | 90 | { |
kadonotakashi | 0:8fdf9a60065b | 91 | tmp8 |= CMP_CR1_INV_MASK; |
kadonotakashi | 0:8fdf9a60065b | 92 | } |
kadonotakashi | 0:8fdf9a60065b | 93 | if (config->useUnfilteredOutput) |
kadonotakashi | 0:8fdf9a60065b | 94 | { |
kadonotakashi | 0:8fdf9a60065b | 95 | tmp8 |= CMP_CR1_COS_MASK; |
kadonotakashi | 0:8fdf9a60065b | 96 | } |
kadonotakashi | 0:8fdf9a60065b | 97 | if (config->enablePinOut) |
kadonotakashi | 0:8fdf9a60065b | 98 | { |
kadonotakashi | 0:8fdf9a60065b | 99 | tmp8 |= CMP_CR1_OPE_MASK; |
kadonotakashi | 0:8fdf9a60065b | 100 | } |
kadonotakashi | 0:8fdf9a60065b | 101 | #if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE |
kadonotakashi | 0:8fdf9a60065b | 102 | if (config->enableTriggerMode) |
kadonotakashi | 0:8fdf9a60065b | 103 | { |
kadonotakashi | 0:8fdf9a60065b | 104 | tmp8 |= CMP_CR1_TRIGM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 105 | } |
kadonotakashi | 0:8fdf9a60065b | 106 | else |
kadonotakashi | 0:8fdf9a60065b | 107 | { |
kadonotakashi | 0:8fdf9a60065b | 108 | tmp8 &= ~CMP_CR1_TRIGM_MASK; |
kadonotakashi | 0:8fdf9a60065b | 109 | } |
kadonotakashi | 0:8fdf9a60065b | 110 | #endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ |
kadonotakashi | 0:8fdf9a60065b | 111 | base->CR1 = tmp8; |
kadonotakashi | 0:8fdf9a60065b | 112 | |
kadonotakashi | 0:8fdf9a60065b | 113 | /* CMPx_CR0. */ |
kadonotakashi | 0:8fdf9a60065b | 114 | tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK; |
kadonotakashi | 0:8fdf9a60065b | 115 | tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode); |
kadonotakashi | 0:8fdf9a60065b | 116 | base->CR0 = tmp8; |
kadonotakashi | 0:8fdf9a60065b | 117 | |
kadonotakashi | 0:8fdf9a60065b | 118 | CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ |
kadonotakashi | 0:8fdf9a60065b | 119 | } |
kadonotakashi | 0:8fdf9a60065b | 120 | |
kadonotakashi | 0:8fdf9a60065b | 121 | void CMP_Deinit(CMP_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 122 | { |
kadonotakashi | 0:8fdf9a60065b | 123 | /* Disable the CMP module. */ |
kadonotakashi | 0:8fdf9a60065b | 124 | CMP_Enable(base, false); |
kadonotakashi | 0:8fdf9a60065b | 125 | |
kadonotakashi | 0:8fdf9a60065b | 126 | /* Disable the clock. */ |
kadonotakashi | 0:8fdf9a60065b | 127 | CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); |
kadonotakashi | 0:8fdf9a60065b | 128 | } |
kadonotakashi | 0:8fdf9a60065b | 129 | |
kadonotakashi | 0:8fdf9a60065b | 130 | void CMP_GetDefaultConfig(cmp_config_t *config) |
kadonotakashi | 0:8fdf9a60065b | 131 | { |
kadonotakashi | 0:8fdf9a60065b | 132 | assert(NULL != config); |
kadonotakashi | 0:8fdf9a60065b | 133 | |
kadonotakashi | 0:8fdf9a60065b | 134 | config->enableCmp = true; /* Enable the CMP module after initialization. */ |
kadonotakashi | 0:8fdf9a60065b | 135 | config->hysteresisMode = kCMP_HysteresisLevel0; |
kadonotakashi | 0:8fdf9a60065b | 136 | config->enableHighSpeed = false; |
kadonotakashi | 0:8fdf9a60065b | 137 | config->enableInvertOutput = false; |
kadonotakashi | 0:8fdf9a60065b | 138 | config->useUnfilteredOutput = false; |
kadonotakashi | 0:8fdf9a60065b | 139 | config->enablePinOut = false; |
kadonotakashi | 0:8fdf9a60065b | 140 | #if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE |
kadonotakashi | 0:8fdf9a60065b | 141 | config->enableTriggerMode = false; |
kadonotakashi | 0:8fdf9a60065b | 142 | #endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ |
kadonotakashi | 0:8fdf9a60065b | 143 | } |
kadonotakashi | 0:8fdf9a60065b | 144 | |
kadonotakashi | 0:8fdf9a60065b | 145 | void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) |
kadonotakashi | 0:8fdf9a60065b | 146 | { |
kadonotakashi | 0:8fdf9a60065b | 147 | uint8_t tmp8 = base->MUXCR; |
kadonotakashi | 0:8fdf9a60065b | 148 | |
kadonotakashi | 0:8fdf9a60065b | 149 | tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); |
kadonotakashi | 0:8fdf9a60065b | 150 | tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel); |
kadonotakashi | 0:8fdf9a60065b | 151 | base->MUXCR = tmp8; |
kadonotakashi | 0:8fdf9a60065b | 152 | } |
kadonotakashi | 0:8fdf9a60065b | 153 | |
kadonotakashi | 0:8fdf9a60065b | 154 | #if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA |
kadonotakashi | 0:8fdf9a60065b | 155 | void CMP_EnableDMA(CMP_Type *base, bool enable) |
kadonotakashi | 0:8fdf9a60065b | 156 | { |
kadonotakashi | 0:8fdf9a60065b | 157 | uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ |
kadonotakashi | 0:8fdf9a60065b | 158 | |
kadonotakashi | 0:8fdf9a60065b | 159 | if (enable) |
kadonotakashi | 0:8fdf9a60065b | 160 | { |
kadonotakashi | 0:8fdf9a60065b | 161 | tmp8 |= CMP_SCR_DMAEN_MASK; |
kadonotakashi | 0:8fdf9a60065b | 162 | } |
kadonotakashi | 0:8fdf9a60065b | 163 | else |
kadonotakashi | 0:8fdf9a60065b | 164 | { |
kadonotakashi | 0:8fdf9a60065b | 165 | tmp8 &= ~CMP_SCR_DMAEN_MASK; |
kadonotakashi | 0:8fdf9a60065b | 166 | } |
kadonotakashi | 0:8fdf9a60065b | 167 | base->SCR = tmp8; |
kadonotakashi | 0:8fdf9a60065b | 168 | } |
kadonotakashi | 0:8fdf9a60065b | 169 | #endif /* FSL_FEATURE_CMP_HAS_DMA */ |
kadonotakashi | 0:8fdf9a60065b | 170 | |
kadonotakashi | 0:8fdf9a60065b | 171 | void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) |
kadonotakashi | 0:8fdf9a60065b | 172 | { |
kadonotakashi | 0:8fdf9a60065b | 173 | assert(NULL != config); |
kadonotakashi | 0:8fdf9a60065b | 174 | |
kadonotakashi | 0:8fdf9a60065b | 175 | uint8_t tmp8; |
kadonotakashi | 0:8fdf9a60065b | 176 | |
kadonotakashi | 0:8fdf9a60065b | 177 | #if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT |
kadonotakashi | 0:8fdf9a60065b | 178 | /* Choose the clock source for sampling. */ |
kadonotakashi | 0:8fdf9a60065b | 179 | if (config->enableSample) |
kadonotakashi | 0:8fdf9a60065b | 180 | { |
kadonotakashi | 0:8fdf9a60065b | 181 | base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ |
kadonotakashi | 0:8fdf9a60065b | 182 | } |
kadonotakashi | 0:8fdf9a60065b | 183 | else |
kadonotakashi | 0:8fdf9a60065b | 184 | { |
kadonotakashi | 0:8fdf9a60065b | 185 | base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */ |
kadonotakashi | 0:8fdf9a60065b | 186 | } |
kadonotakashi | 0:8fdf9a60065b | 187 | #endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ |
kadonotakashi | 0:8fdf9a60065b | 188 | /* Set the filter count. */ |
kadonotakashi | 0:8fdf9a60065b | 189 | tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK; |
kadonotakashi | 0:8fdf9a60065b | 190 | tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount); |
kadonotakashi | 0:8fdf9a60065b | 191 | base->CR0 = tmp8; |
kadonotakashi | 0:8fdf9a60065b | 192 | /* Set the filter period. It is used as the divider to bus clock. */ |
kadonotakashi | 0:8fdf9a60065b | 193 | base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); |
kadonotakashi | 0:8fdf9a60065b | 194 | } |
kadonotakashi | 0:8fdf9a60065b | 195 | |
kadonotakashi | 0:8fdf9a60065b | 196 | void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) |
kadonotakashi | 0:8fdf9a60065b | 197 | { |
kadonotakashi | 0:8fdf9a60065b | 198 | uint8_t tmp8 = 0U; |
kadonotakashi | 0:8fdf9a60065b | 199 | |
kadonotakashi | 0:8fdf9a60065b | 200 | if (NULL == config) |
kadonotakashi | 0:8fdf9a60065b | 201 | { |
kadonotakashi | 0:8fdf9a60065b | 202 | /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/ |
kadonotakashi | 0:8fdf9a60065b | 203 | base->DACCR = 0U; |
kadonotakashi | 0:8fdf9a60065b | 204 | return; |
kadonotakashi | 0:8fdf9a60065b | 205 | } |
kadonotakashi | 0:8fdf9a60065b | 206 | /* CMPx_DACCR. */ |
kadonotakashi | 0:8fdf9a60065b | 207 | tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ |
kadonotakashi | 0:8fdf9a60065b | 208 | if (kCMP_VrefSourceVin2 == config->referenceVoltageSource) |
kadonotakashi | 0:8fdf9a60065b | 209 | { |
kadonotakashi | 0:8fdf9a60065b | 210 | tmp8 |= CMP_DACCR_VRSEL_MASK; |
kadonotakashi | 0:8fdf9a60065b | 211 | } |
kadonotakashi | 0:8fdf9a60065b | 212 | tmp8 |= CMP_DACCR_VOSEL(config->DACValue); |
kadonotakashi | 0:8fdf9a60065b | 213 | |
kadonotakashi | 0:8fdf9a60065b | 214 | base->DACCR = tmp8; |
kadonotakashi | 0:8fdf9a60065b | 215 | } |
kadonotakashi | 0:8fdf9a60065b | 216 | |
kadonotakashi | 0:8fdf9a60065b | 217 | void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) |
kadonotakashi | 0:8fdf9a60065b | 218 | { |
kadonotakashi | 0:8fdf9a60065b | 219 | uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ |
kadonotakashi | 0:8fdf9a60065b | 220 | |
kadonotakashi | 0:8fdf9a60065b | 221 | if (0U != (kCMP_OutputRisingInterruptEnable & mask)) |
kadonotakashi | 0:8fdf9a60065b | 222 | { |
kadonotakashi | 0:8fdf9a60065b | 223 | tmp8 |= CMP_SCR_IER_MASK; |
kadonotakashi | 0:8fdf9a60065b | 224 | } |
kadonotakashi | 0:8fdf9a60065b | 225 | if (0U != (kCMP_OutputFallingInterruptEnable & mask)) |
kadonotakashi | 0:8fdf9a60065b | 226 | { |
kadonotakashi | 0:8fdf9a60065b | 227 | tmp8 |= CMP_SCR_IEF_MASK; |
kadonotakashi | 0:8fdf9a60065b | 228 | } |
kadonotakashi | 0:8fdf9a60065b | 229 | base->SCR = tmp8; |
kadonotakashi | 0:8fdf9a60065b | 230 | } |
kadonotakashi | 0:8fdf9a60065b | 231 | |
kadonotakashi | 0:8fdf9a60065b | 232 | void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) |
kadonotakashi | 0:8fdf9a60065b | 233 | { |
kadonotakashi | 0:8fdf9a60065b | 234 | uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ |
kadonotakashi | 0:8fdf9a60065b | 235 | |
kadonotakashi | 0:8fdf9a60065b | 236 | if (0U != (kCMP_OutputRisingInterruptEnable & mask)) |
kadonotakashi | 0:8fdf9a60065b | 237 | { |
kadonotakashi | 0:8fdf9a60065b | 238 | tmp8 &= ~CMP_SCR_IER_MASK; |
kadonotakashi | 0:8fdf9a60065b | 239 | } |
kadonotakashi | 0:8fdf9a60065b | 240 | if (0U != (kCMP_OutputFallingInterruptEnable & mask)) |
kadonotakashi | 0:8fdf9a60065b | 241 | { |
kadonotakashi | 0:8fdf9a60065b | 242 | tmp8 &= ~CMP_SCR_IEF_MASK; |
kadonotakashi | 0:8fdf9a60065b | 243 | } |
kadonotakashi | 0:8fdf9a60065b | 244 | base->SCR = tmp8; |
kadonotakashi | 0:8fdf9a60065b | 245 | } |
kadonotakashi | 0:8fdf9a60065b | 246 | |
kadonotakashi | 0:8fdf9a60065b | 247 | uint32_t CMP_GetStatusFlags(CMP_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 248 | { |
kadonotakashi | 0:8fdf9a60065b | 249 | uint32_t ret32 = 0U; |
kadonotakashi | 0:8fdf9a60065b | 250 | |
kadonotakashi | 0:8fdf9a60065b | 251 | if (0U != (CMP_SCR_CFR_MASK & base->SCR)) |
kadonotakashi | 0:8fdf9a60065b | 252 | { |
kadonotakashi | 0:8fdf9a60065b | 253 | ret32 |= kCMP_OutputRisingEventFlag; |
kadonotakashi | 0:8fdf9a60065b | 254 | } |
kadonotakashi | 0:8fdf9a60065b | 255 | if (0U != (CMP_SCR_CFF_MASK & base->SCR)) |
kadonotakashi | 0:8fdf9a60065b | 256 | { |
kadonotakashi | 0:8fdf9a60065b | 257 | ret32 |= kCMP_OutputFallingEventFlag; |
kadonotakashi | 0:8fdf9a60065b | 258 | } |
kadonotakashi | 0:8fdf9a60065b | 259 | if (0U != (CMP_SCR_COUT_MASK & base->SCR)) |
kadonotakashi | 0:8fdf9a60065b | 260 | { |
kadonotakashi | 0:8fdf9a60065b | 261 | ret32 |= kCMP_OutputAssertEventFlag; |
kadonotakashi | 0:8fdf9a60065b | 262 | } |
kadonotakashi | 0:8fdf9a60065b | 263 | return ret32; |
kadonotakashi | 0:8fdf9a60065b | 264 | } |
kadonotakashi | 0:8fdf9a60065b | 265 | |
kadonotakashi | 0:8fdf9a60065b | 266 | void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) |
kadonotakashi | 0:8fdf9a60065b | 267 | { |
kadonotakashi | 0:8fdf9a60065b | 268 | uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ |
kadonotakashi | 0:8fdf9a60065b | 269 | |
kadonotakashi | 0:8fdf9a60065b | 270 | if (0U != (kCMP_OutputRisingEventFlag & mask)) |
kadonotakashi | 0:8fdf9a60065b | 271 | { |
kadonotakashi | 0:8fdf9a60065b | 272 | tmp8 |= CMP_SCR_CFR_MASK; |
kadonotakashi | 0:8fdf9a60065b | 273 | } |
kadonotakashi | 0:8fdf9a60065b | 274 | if (0U != (kCMP_OutputFallingEventFlag & mask)) |
kadonotakashi | 0:8fdf9a60065b | 275 | { |
kadonotakashi | 0:8fdf9a60065b | 276 | tmp8 |= CMP_SCR_CFF_MASK; |
kadonotakashi | 0:8fdf9a60065b | 277 | } |
kadonotakashi | 0:8fdf9a60065b | 278 | base->SCR = tmp8; |
kadonotakashi | 0:8fdf9a60065b | 279 | } |