takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_clock.h@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /*
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
kadonotakashi 0:8fdf9a60065b 3 * All rights reserved.
kadonotakashi 0:8fdf9a60065b 4 *
kadonotakashi 0:8fdf9a60065b 5 * Redistribution and use in source and binary forms, with or without modification,
kadonotakashi 0:8fdf9a60065b 6 * are permitted provided that the following conditions are met:
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * o Redistributions of source code must retain the above copyright notice, this list
kadonotakashi 0:8fdf9a60065b 9 * of conditions and the following disclaimer.
kadonotakashi 0:8fdf9a60065b 10 *
kadonotakashi 0:8fdf9a60065b 11 * o Redistributions in binary form must reproduce the above copyright notice, this
kadonotakashi 0:8fdf9a60065b 12 * list of conditions and the following disclaimer in the documentation and/or
kadonotakashi 0:8fdf9a60065b 13 * other materials provided with the distribution.
kadonotakashi 0:8fdf9a60065b 14 *
kadonotakashi 0:8fdf9a60065b 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kadonotakashi 0:8fdf9a60065b 16 * contributors may be used to endorse or promote products derived from this
kadonotakashi 0:8fdf9a60065b 17 * software without specific prior written permission.
kadonotakashi 0:8fdf9a60065b 18 *
kadonotakashi 0:8fdf9a60065b 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kadonotakashi 0:8fdf9a60065b 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kadonotakashi 0:8fdf9a60065b 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kadonotakashi 0:8fdf9a60065b 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kadonotakashi 0:8fdf9a60065b 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kadonotakashi 0:8fdf9a60065b 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kadonotakashi 0:8fdf9a60065b 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kadonotakashi 0:8fdf9a60065b 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kadonotakashi 0:8fdf9a60065b 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kadonotakashi 0:8fdf9a60065b 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kadonotakashi 0:8fdf9a60065b 29 */
kadonotakashi 0:8fdf9a60065b 30
kadonotakashi 0:8fdf9a60065b 31 #ifndef _FSL_CLOCK_H_
kadonotakashi 0:8fdf9a60065b 32 #define _FSL_CLOCK_H_
kadonotakashi 0:8fdf9a60065b 33
kadonotakashi 0:8fdf9a60065b 34 #include "fsl_device_registers.h"
kadonotakashi 0:8fdf9a60065b 35 #include <stdint.h>
kadonotakashi 0:8fdf9a60065b 36 #include <stdbool.h>
kadonotakashi 0:8fdf9a60065b 37 #include <assert.h>
kadonotakashi 0:8fdf9a60065b 38
kadonotakashi 0:8fdf9a60065b 39 /*! @addtogroup mcglite */
kadonotakashi 0:8fdf9a60065b 40 /*! @{ */
kadonotakashi 0:8fdf9a60065b 41
kadonotakashi 0:8fdf9a60065b 42 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 43 * Definitions
kadonotakashi 0:8fdf9a60065b 44 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 45
kadonotakashi 0:8fdf9a60065b 46 /*! @brief Clock driver version. */
kadonotakashi 0:8fdf9a60065b 47 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
kadonotakashi 0:8fdf9a60065b 48
kadonotakashi 0:8fdf9a60065b 49 /*! @brief External XTAL0 (OSC0) clock frequency.
kadonotakashi 0:8fdf9a60065b 50 *
kadonotakashi 0:8fdf9a60065b 51 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz, when the clock is setup, use the
kadonotakashi 0:8fdf9a60065b 52 * function CLOCK_SetXtal0Freq to set the value in to clock driver. For example,
kadonotakashi 0:8fdf9a60065b 53 * if XTAL0 is 8MHz,
kadonotakashi 0:8fdf9a60065b 54 * @code
kadonotakashi 0:8fdf9a60065b 55 * CLOCK_InitOsc0(...); // Setup the OSC0
kadonotakashi 0:8fdf9a60065b 56 * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to clock driver.
kadonotakashi 0:8fdf9a60065b 57 * @endcode
kadonotakashi 0:8fdf9a60065b 58 *
kadonotakashi 0:8fdf9a60065b 59 * This is important for the multicore platforms, only one core needs to setup
kadonotakashi 0:8fdf9a60065b 60 * OSC0 using CLOCK_InitOsc0, all other cores need to call CLOCK_SetXtal0Freq
kadonotakashi 0:8fdf9a60065b 61 * to get valid clock frequency.
kadonotakashi 0:8fdf9a60065b 62 */
kadonotakashi 0:8fdf9a60065b 63 extern uint32_t g_xtal0Freq;
kadonotakashi 0:8fdf9a60065b 64
kadonotakashi 0:8fdf9a60065b 65 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
kadonotakashi 0:8fdf9a60065b 66 *
kadonotakashi 0:8fdf9a60065b 67 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz, when the clock is setup, use the
kadonotakashi 0:8fdf9a60065b 68 * function CLOCK_SetXtal32Freq to set the value in to clock driver.
kadonotakashi 0:8fdf9a60065b 69 *
kadonotakashi 0:8fdf9a60065b 70 * This is important for the multicore platforms, only one core needs to setup
kadonotakashi 0:8fdf9a60065b 71 * the clock, all other cores need to call CLOCK_SetXtal32Freq
kadonotakashi 0:8fdf9a60065b 72 * to get valid clock frequency.
kadonotakashi 0:8fdf9a60065b 73 */
kadonotakashi 0:8fdf9a60065b 74 extern uint32_t g_xtal32Freq;
kadonotakashi 0:8fdf9a60065b 75
kadonotakashi 0:8fdf9a60065b 76 /*! @brief Clock ip name array for DMAMUX. */
kadonotakashi 0:8fdf9a60065b 77 #define DMAMUX_CLOCKS \
kadonotakashi 0:8fdf9a60065b 78 { \
kadonotakashi 0:8fdf9a60065b 79 kCLOCK_Dmamux0 \
kadonotakashi 0:8fdf9a60065b 80 }
kadonotakashi 0:8fdf9a60065b 81
kadonotakashi 0:8fdf9a60065b 82 /*! @brief Clock ip name array for RTC. */
kadonotakashi 0:8fdf9a60065b 83 #define RTC_CLOCKS \
kadonotakashi 0:8fdf9a60065b 84 { \
kadonotakashi 0:8fdf9a60065b 85 kCLOCK_Rtc0 \
kadonotakashi 0:8fdf9a60065b 86 }
kadonotakashi 0:8fdf9a60065b 87
kadonotakashi 0:8fdf9a60065b 88 /*! @brief Clock ip name array for SAI. */
kadonotakashi 0:8fdf9a60065b 89 #define SAI_CLOCKS \
kadonotakashi 0:8fdf9a60065b 90 { \
kadonotakashi 0:8fdf9a60065b 91 kCLOCK_Sai0 \
kadonotakashi 0:8fdf9a60065b 92 }
kadonotakashi 0:8fdf9a60065b 93
kadonotakashi 0:8fdf9a60065b 94 /*! @brief Clock ip name array for SPI. */
kadonotakashi 0:8fdf9a60065b 95 #define SPI_CLOCKS \
kadonotakashi 0:8fdf9a60065b 96 { \
kadonotakashi 0:8fdf9a60065b 97 kCLOCK_Spi0, kCLOCK_Spi1 \
kadonotakashi 0:8fdf9a60065b 98 }
kadonotakashi 0:8fdf9a60065b 99
kadonotakashi 0:8fdf9a60065b 100 /*! @brief Clock ip name array for SLCD. */
kadonotakashi 0:8fdf9a60065b 101 #define SLCD_CLOCKS \
kadonotakashi 0:8fdf9a60065b 102 { \
kadonotakashi 0:8fdf9a60065b 103 kCLOCK_Slcd0 \
kadonotakashi 0:8fdf9a60065b 104 }
kadonotakashi 0:8fdf9a60065b 105
kadonotakashi 0:8fdf9a60065b 106 /*! @brief Clock ip name array for PIT. */
kadonotakashi 0:8fdf9a60065b 107 #define PIT_CLOCKS \
kadonotakashi 0:8fdf9a60065b 108 { \
kadonotakashi 0:8fdf9a60065b 109 kCLOCK_Pit0 \
kadonotakashi 0:8fdf9a60065b 110 }
kadonotakashi 0:8fdf9a60065b 111
kadonotakashi 0:8fdf9a60065b 112 /*! @brief Clock ip name array for PORT. */
kadonotakashi 0:8fdf9a60065b 113 #define PORT_CLOCKS \
kadonotakashi 0:8fdf9a60065b 114 { \
kadonotakashi 0:8fdf9a60065b 115 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
kadonotakashi 0:8fdf9a60065b 116 }
kadonotakashi 0:8fdf9a60065b 117
kadonotakashi 0:8fdf9a60065b 118 /*! @brief Clock ip name array for LPUART. */
kadonotakashi 0:8fdf9a60065b 119 #define LPUART_CLOCKS \
kadonotakashi 0:8fdf9a60065b 120 { \
kadonotakashi 0:8fdf9a60065b 121 kCLOCK_Lpuart0, kCLOCK_Lpuart1 \
kadonotakashi 0:8fdf9a60065b 122 }
kadonotakashi 0:8fdf9a60065b 123
kadonotakashi 0:8fdf9a60065b 124 /*! @brief Clock ip name array for DAC. */
kadonotakashi 0:8fdf9a60065b 125 #define DAC_CLOCKS \
kadonotakashi 0:8fdf9a60065b 126 { \
kadonotakashi 0:8fdf9a60065b 127 kCLOCK_Dac0 \
kadonotakashi 0:8fdf9a60065b 128 }
kadonotakashi 0:8fdf9a60065b 129
kadonotakashi 0:8fdf9a60065b 130 /*! @brief Clock ip name array for LPTMR. */
kadonotakashi 0:8fdf9a60065b 131 #define LPTMR_CLOCKS \
kadonotakashi 0:8fdf9a60065b 132 { \
kadonotakashi 0:8fdf9a60065b 133 kCLOCK_Lptmr0 \
kadonotakashi 0:8fdf9a60065b 134 }
kadonotakashi 0:8fdf9a60065b 135
kadonotakashi 0:8fdf9a60065b 136 /*! @brief Clock ip name array for ADC16. */
kadonotakashi 0:8fdf9a60065b 137 #define ADC16_CLOCKS \
kadonotakashi 0:8fdf9a60065b 138 { \
kadonotakashi 0:8fdf9a60065b 139 kCLOCK_Adc0 \
kadonotakashi 0:8fdf9a60065b 140 }
kadonotakashi 0:8fdf9a60065b 141
kadonotakashi 0:8fdf9a60065b 142 /*! @brief Clock ip name array for FLEXIO. */
kadonotakashi 0:8fdf9a60065b 143 #define FLEXIO_CLOCKS \
kadonotakashi 0:8fdf9a60065b 144 { \
kadonotakashi 0:8fdf9a60065b 145 kCLOCK_Flexio0 \
kadonotakashi 0:8fdf9a60065b 146 }
kadonotakashi 0:8fdf9a60065b 147
kadonotakashi 0:8fdf9a60065b 148 /*! @brief Clock ip name array for VREF. */
kadonotakashi 0:8fdf9a60065b 149 #define VREF_CLOCKS \
kadonotakashi 0:8fdf9a60065b 150 { \
kadonotakashi 0:8fdf9a60065b 151 kCLOCK_Vref0 \
kadonotakashi 0:8fdf9a60065b 152 }
kadonotakashi 0:8fdf9a60065b 153
kadonotakashi 0:8fdf9a60065b 154 /*! @brief Clock ip name array for DMA. */
kadonotakashi 0:8fdf9a60065b 155 #define DMA_CLOCKS \
kadonotakashi 0:8fdf9a60065b 156 { \
kadonotakashi 0:8fdf9a60065b 157 kCLOCK_Dma0 \
kadonotakashi 0:8fdf9a60065b 158 }
kadonotakashi 0:8fdf9a60065b 159
kadonotakashi 0:8fdf9a60065b 160 /*! @brief Clock ip name array for UART. */
kadonotakashi 0:8fdf9a60065b 161 #define UART_CLOCKS \
kadonotakashi 0:8fdf9a60065b 162 { \
kadonotakashi 0:8fdf9a60065b 163 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Uart2 \
kadonotakashi 0:8fdf9a60065b 164 }
kadonotakashi 0:8fdf9a60065b 165
kadonotakashi 0:8fdf9a60065b 166 /*! @brief Clock ip name array for TPM. */
kadonotakashi 0:8fdf9a60065b 167 #define TPM_CLOCKS \
kadonotakashi 0:8fdf9a60065b 168 { \
kadonotakashi 0:8fdf9a60065b 169 kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2 \
kadonotakashi 0:8fdf9a60065b 170 }
kadonotakashi 0:8fdf9a60065b 171
kadonotakashi 0:8fdf9a60065b 172 /*! @brief Clock ip name array for I2C. */
kadonotakashi 0:8fdf9a60065b 173 #define I2C_CLOCKS \
kadonotakashi 0:8fdf9a60065b 174 { \
kadonotakashi 0:8fdf9a60065b 175 kCLOCK_I2c0, kCLOCK_I2c1 \
kadonotakashi 0:8fdf9a60065b 176 }
kadonotakashi 0:8fdf9a60065b 177
kadonotakashi 0:8fdf9a60065b 178 /*! @brief Clock ip name array for FTF. */
kadonotakashi 0:8fdf9a60065b 179 #define FTF_CLOCKS \
kadonotakashi 0:8fdf9a60065b 180 { \
kadonotakashi 0:8fdf9a60065b 181 kCLOCK_Ftf0 \
kadonotakashi 0:8fdf9a60065b 182 }
kadonotakashi 0:8fdf9a60065b 183
kadonotakashi 0:8fdf9a60065b 184 /*! @brief Clock ip name array for CMP. */
kadonotakashi 0:8fdf9a60065b 185 #define CMP_CLOCKS \
kadonotakashi 0:8fdf9a60065b 186 { \
kadonotakashi 0:8fdf9a60065b 187 kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \
kadonotakashi 0:8fdf9a60065b 188 }
kadonotakashi 0:8fdf9a60065b 189
kadonotakashi 0:8fdf9a60065b 190 /*!
kadonotakashi 0:8fdf9a60065b 191 * @brief LPO clock frequency.
kadonotakashi 0:8fdf9a60065b 192 */
kadonotakashi 0:8fdf9a60065b 193 #define LPO_CLK_FREQ 1000U
kadonotakashi 0:8fdf9a60065b 194
kadonotakashi 0:8fdf9a60065b 195 /*! @brief Peripherals clock source definition. */
kadonotakashi 0:8fdf9a60065b 196 #define SYS_CLK kCLOCK_CoreSysClk
kadonotakashi 0:8fdf9a60065b 197 #define BUS_CLK kCLOCK_BusClk
kadonotakashi 0:8fdf9a60065b 198
kadonotakashi 0:8fdf9a60065b 199 #define I2C0_CLK_SRC SYS_CLK
kadonotakashi 0:8fdf9a60065b 200 #define I2C1_CLK_SRC SYS_CLK
kadonotakashi 0:8fdf9a60065b 201 #define SPI0_CLK_SRC BUS_CLK
kadonotakashi 0:8fdf9a60065b 202 #define SPI1_CLK_SRC SYS_CLK
kadonotakashi 0:8fdf9a60065b 203 #define UART2_CLK_SRC BUS_CLK
kadonotakashi 0:8fdf9a60065b 204
kadonotakashi 0:8fdf9a60065b 205 /*! @brief Clock name used to get clock frequency. */
kadonotakashi 0:8fdf9a60065b 206 typedef enum _clock_name
kadonotakashi 0:8fdf9a60065b 207 {
kadonotakashi 0:8fdf9a60065b 208
kadonotakashi 0:8fdf9a60065b 209 /* ----------------------------- System layer clock -------------------------------*/
kadonotakashi 0:8fdf9a60065b 210 kCLOCK_CoreSysClk, /*!< Core/system clock */
kadonotakashi 0:8fdf9a60065b 211 kCLOCK_PlatClk, /*!< Platform clock */
kadonotakashi 0:8fdf9a60065b 212 kCLOCK_BusClk, /*!< Bus clock */
kadonotakashi 0:8fdf9a60065b 213 kCLOCK_FlexBusClk, /*!< FlexBus clock */
kadonotakashi 0:8fdf9a60065b 214 kCLOCK_FlashClk, /*!< Flash clock */
kadonotakashi 0:8fdf9a60065b 215 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
kadonotakashi 0:8fdf9a60065b 216 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
kadonotakashi 0:8fdf9a60065b 217
kadonotakashi 0:8fdf9a60065b 218 /* ---------------------------------- OSC clock -----------------------------------*/
kadonotakashi 0:8fdf9a60065b 219 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
kadonotakashi 0:8fdf9a60065b 220 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
kadonotakashi 0:8fdf9a60065b 221 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
kadonotakashi 0:8fdf9a60065b 222 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
kadonotakashi 0:8fdf9a60065b 223
kadonotakashi 0:8fdf9a60065b 224 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
kadonotakashi 0:8fdf9a60065b 225 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
kadonotakashi 0:8fdf9a60065b 226 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
kadonotakashi 0:8fdf9a60065b 227 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
kadonotakashi 0:8fdf9a60065b 228 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
kadonotakashi 0:8fdf9a60065b 229 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
kadonotakashi 0:8fdf9a60065b 230 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
kadonotakashi 0:8fdf9a60065b 231 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
kadonotakashi 0:8fdf9a60065b 232 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
kadonotakashi 0:8fdf9a60065b 233
kadonotakashi 0:8fdf9a60065b 234 /* --------------------------------- Other clock ----------------------------------*/
kadonotakashi 0:8fdf9a60065b 235 kCLOCK_LpoClk, /*!< LPO clock */
kadonotakashi 0:8fdf9a60065b 236
kadonotakashi 0:8fdf9a60065b 237 } clock_name_t;
kadonotakashi 0:8fdf9a60065b 238
kadonotakashi 0:8fdf9a60065b 239 /*! @brief USB clock source definition. */
kadonotakashi 0:8fdf9a60065b 240 typedef enum _clock_usb_src
kadonotakashi 0:8fdf9a60065b 241 {
kadonotakashi 0:8fdf9a60065b 242 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U), /*!< Use IRC48M. */
kadonotakashi 0:8fdf9a60065b 243 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */
kadonotakashi 0:8fdf9a60065b 244 } clock_usb_src_t;
kadonotakashi 0:8fdf9a60065b 245 /*------------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 246
kadonotakashi 0:8fdf9a60065b 247 clock_gate_t definition:
kadonotakashi 0:8fdf9a60065b 248
kadonotakashi 0:8fdf9a60065b 249 31 16 0
kadonotakashi 0:8fdf9a60065b 250 -----------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 251 | SIM_SCGC register offset | control bit offset in SCGC |
kadonotakashi 0:8fdf9a60065b 252 -----------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 253
kadonotakashi 0:8fdf9a60065b 254 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
kadonotakashi 0:8fdf9a60065b 255 SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
kadonotakashi 0:8fdf9a60065b 256
kadonotakashi 0:8fdf9a60065b 257 kCLOCK_GateSdhc0 = (0x1030 << 16) | 17;
kadonotakashi 0:8fdf9a60065b 258
kadonotakashi 0:8fdf9a60065b 259 ------------------------------------------------------------------------------*/
kadonotakashi 0:8fdf9a60065b 260
kadonotakashi 0:8fdf9a60065b 261 #define CLK_GATE_REG_OFFSET_SHIFT 16U
kadonotakashi 0:8fdf9a60065b 262 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
kadonotakashi 0:8fdf9a60065b 263 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
kadonotakashi 0:8fdf9a60065b 264 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
kadonotakashi 0:8fdf9a60065b 265
kadonotakashi 0:8fdf9a60065b 266 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
kadonotakashi 0:8fdf9a60065b 267 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
kadonotakashi 0:8fdf9a60065b 268 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
kadonotakashi 0:8fdf9a60065b 269
kadonotakashi 0:8fdf9a60065b 270 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
kadonotakashi 0:8fdf9a60065b 271 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
kadonotakashi 0:8fdf9a60065b 272
kadonotakashi 0:8fdf9a60065b 273 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
kadonotakashi 0:8fdf9a60065b 274 typedef enum _clock_ip_name
kadonotakashi 0:8fdf9a60065b 275 {
kadonotakashi 0:8fdf9a60065b 276 kCLOCK_IpInvalid = 0U,
kadonotakashi 0:8fdf9a60065b 277 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
kadonotakashi 0:8fdf9a60065b 278 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
kadonotakashi 0:8fdf9a60065b 279 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
kadonotakashi 0:8fdf9a60065b 280 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
kadonotakashi 0:8fdf9a60065b 281 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
kadonotakashi 0:8fdf9a60065b 282 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
kadonotakashi 0:8fdf9a60065b 283 kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
kadonotakashi 0:8fdf9a60065b 284 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
kadonotakashi 0:8fdf9a60065b 285 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x1034U, 22U),
kadonotakashi 0:8fdf9a60065b 286 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x1034U, 23U),
kadonotakashi 0:8fdf9a60065b 287
kadonotakashi 0:8fdf9a60065b 288 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
kadonotakashi 0:8fdf9a60065b 289 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
kadonotakashi 0:8fdf9a60065b 290 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
kadonotakashi 0:8fdf9a60065b 291 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
kadonotakashi 0:8fdf9a60065b 292 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
kadonotakashi 0:8fdf9a60065b 293 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
kadonotakashi 0:8fdf9a60065b 294 kCLOCK_Slcd0 = CLK_GATE_DEFINE(0x1038U, 19U),
kadonotakashi 0:8fdf9a60065b 295 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x1038U, 20U),
kadonotakashi 0:8fdf9a60065b 296 kCLOCK_Lpuart1 = CLK_GATE_DEFINE(0x1038U, 21U),
kadonotakashi 0:8fdf9a60065b 297 kCLOCK_Flexio0 = CLK_GATE_DEFINE(0x1038U, 31U),
kadonotakashi 0:8fdf9a60065b 298
kadonotakashi 0:8fdf9a60065b 299 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
kadonotakashi 0:8fdf9a60065b 300 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
kadonotakashi 0:8fdf9a60065b 301 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
kadonotakashi 0:8fdf9a60065b 302 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
kadonotakashi 0:8fdf9a60065b 303 kCLOCK_Tpm0 = CLK_GATE_DEFINE(0x103CU, 24U),
kadonotakashi 0:8fdf9a60065b 304 kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x103CU, 25U),
kadonotakashi 0:8fdf9a60065b 305 kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x103CU, 26U),
kadonotakashi 0:8fdf9a60065b 306 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
kadonotakashi 0:8fdf9a60065b 307 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
kadonotakashi 0:8fdf9a60065b 308 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
kadonotakashi 0:8fdf9a60065b 309
kadonotakashi 0:8fdf9a60065b 310 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U),
kadonotakashi 0:8fdf9a60065b 311 } clock_ip_name_t;
kadonotakashi 0:8fdf9a60065b 312
kadonotakashi 0:8fdf9a60065b 313 /*!@brief SIM configuration structure for clock setting. */
kadonotakashi 0:8fdf9a60065b 314 typedef struct _sim_clock_config
kadonotakashi 0:8fdf9a60065b 315 {
kadonotakashi 0:8fdf9a60065b 316 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
kadonotakashi 0:8fdf9a60065b 317 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
kadonotakashi 0:8fdf9a60065b 318 } sim_clock_config_t;
kadonotakashi 0:8fdf9a60065b 319
kadonotakashi 0:8fdf9a60065b 320 /*! @brief Oscillator capacitor load setting.*/
kadonotakashi 0:8fdf9a60065b 321 enum _osc_cap_load
kadonotakashi 0:8fdf9a60065b 322 {
kadonotakashi 0:8fdf9a60065b 323 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
kadonotakashi 0:8fdf9a60065b 324 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
kadonotakashi 0:8fdf9a60065b 325 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
kadonotakashi 0:8fdf9a60065b 326 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
kadonotakashi 0:8fdf9a60065b 327 };
kadonotakashi 0:8fdf9a60065b 328
kadonotakashi 0:8fdf9a60065b 329 /*! @brief OSCERCLK enable mode. */
kadonotakashi 0:8fdf9a60065b 330 enum _oscer_enable_mode
kadonotakashi 0:8fdf9a60065b 331 {
kadonotakashi 0:8fdf9a60065b 332 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
kadonotakashi 0:8fdf9a60065b 333 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
kadonotakashi 0:8fdf9a60065b 334 };
kadonotakashi 0:8fdf9a60065b 335
kadonotakashi 0:8fdf9a60065b 336 /*! @brief OSC configuration for OSCERCLK. */
kadonotakashi 0:8fdf9a60065b 337 typedef struct _oscer_config
kadonotakashi 0:8fdf9a60065b 338 {
kadonotakashi 0:8fdf9a60065b 339 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of \ref _oscer_enable_mode. */
kadonotakashi 0:8fdf9a60065b 340
kadonotakashi 0:8fdf9a60065b 341 } oscer_config_t;
kadonotakashi 0:8fdf9a60065b 342
kadonotakashi 0:8fdf9a60065b 343 /*! @brief OSC work mode. */
kadonotakashi 0:8fdf9a60065b 344 typedef enum _osc_mode
kadonotakashi 0:8fdf9a60065b 345 {
kadonotakashi 0:8fdf9a60065b 346 kOSC_ModeExt = 0U, /*!< Use external clock. */
kadonotakashi 0:8fdf9a60065b 347 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
kadonotakashi 0:8fdf9a60065b 348 kOSC_ModeOscHighGain = MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
kadonotakashi 0:8fdf9a60065b 349 } osc_mode_t;
kadonotakashi 0:8fdf9a60065b 350
kadonotakashi 0:8fdf9a60065b 351 /*!
kadonotakashi 0:8fdf9a60065b 352 * @brief OSC Initialization Configuration Structure
kadonotakashi 0:8fdf9a60065b 353 *
kadonotakashi 0:8fdf9a60065b 354 * Defines the configuration data structure to initialize the OSC.
kadonotakashi 0:8fdf9a60065b 355 * When porting to a new board, set the following members
kadonotakashi 0:8fdf9a60065b 356 * according to board settings:
kadonotakashi 0:8fdf9a60065b 357 * 1. freq: The external frequency.
kadonotakashi 0:8fdf9a60065b 358 * 2. workMode: The OSC module mode.
kadonotakashi 0:8fdf9a60065b 359 */
kadonotakashi 0:8fdf9a60065b 360 typedef struct _osc_config
kadonotakashi 0:8fdf9a60065b 361 {
kadonotakashi 0:8fdf9a60065b 362 uint32_t freq; /*!< External clock frequency. */
kadonotakashi 0:8fdf9a60065b 363 uint8_t capLoad; /*!< Capacitor load setting. */
kadonotakashi 0:8fdf9a60065b 364 osc_mode_t workMode; /*!< OSC work mode setting. */
kadonotakashi 0:8fdf9a60065b 365 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
kadonotakashi 0:8fdf9a60065b 366 } osc_config_t;
kadonotakashi 0:8fdf9a60065b 367
kadonotakashi 0:8fdf9a60065b 368 /*! @brief MCG_Lite clock source selection. */
kadonotakashi 0:8fdf9a60065b 369 typedef enum _mcglite_clkout_src
kadonotakashi 0:8fdf9a60065b 370 {
kadonotakashi 0:8fdf9a60065b 371 kMCGLITE_ClkSrcHirc, /*!< MCGOUTCLK source is HIRC */
kadonotakashi 0:8fdf9a60065b 372 kMCGLITE_ClkSrcLirc, /*!< MCGOUTCLK source is LIRC */
kadonotakashi 0:8fdf9a60065b 373 kMCGLITE_ClkSrcExt, /*!< MCGOUTCLK source is external clock source */
kadonotakashi 0:8fdf9a60065b 374 kMCGLITE_ClkSrcReserved
kadonotakashi 0:8fdf9a60065b 375 } mcglite_clkout_src_t;
kadonotakashi 0:8fdf9a60065b 376
kadonotakashi 0:8fdf9a60065b 377 /*! @brief MCG_Lite LIRC select. */
kadonotakashi 0:8fdf9a60065b 378 typedef enum _mcglite_lirc_mode
kadonotakashi 0:8fdf9a60065b 379 {
kadonotakashi 0:8fdf9a60065b 380 kMCGLITE_Lirc2M, /*!< Slow internal reference(LIRC) 2MHz clock selected */
kadonotakashi 0:8fdf9a60065b 381 kMCGLITE_Lirc8M, /*!< Slow internal reference(LIRC) 8MHz clock selected */
kadonotakashi 0:8fdf9a60065b 382 } mcglite_lirc_mode_t;
kadonotakashi 0:8fdf9a60065b 383
kadonotakashi 0:8fdf9a60065b 384 /*! @brief MCG_Lite divider factor selection for clock source*/
kadonotakashi 0:8fdf9a60065b 385 typedef enum _mcglite_lirc_div
kadonotakashi 0:8fdf9a60065b 386 {
kadonotakashi 0:8fdf9a60065b 387 kMCGLITE_LircDivBy1 = 0U, /*!< Divider is 1 */
kadonotakashi 0:8fdf9a60065b 388 kMCGLITE_LircDivBy2, /*!< Divider is 2 */
kadonotakashi 0:8fdf9a60065b 389 kMCGLITE_LircDivBy4, /*!< Divider is 4 */
kadonotakashi 0:8fdf9a60065b 390 kMCGLITE_LircDivBy8, /*!< Divider is 8 */
kadonotakashi 0:8fdf9a60065b 391 kMCGLITE_LircDivBy16, /*!< Divider is 16 */
kadonotakashi 0:8fdf9a60065b 392 kMCGLITE_LircDivBy32, /*!< Divider is 32 */
kadonotakashi 0:8fdf9a60065b 393 kMCGLITE_LircDivBy64, /*!< Divider is 64 */
kadonotakashi 0:8fdf9a60065b 394 kMCGLITE_LircDivBy128 /*!< Divider is 128 */
kadonotakashi 0:8fdf9a60065b 395 } mcglite_lirc_div_t;
kadonotakashi 0:8fdf9a60065b 396
kadonotakashi 0:8fdf9a60065b 397 /*! @brief MCG_Lite clock mode definitions */
kadonotakashi 0:8fdf9a60065b 398 typedef enum _mcglite_mode
kadonotakashi 0:8fdf9a60065b 399 {
kadonotakashi 0:8fdf9a60065b 400 kMCGLITE_ModeHirc48M, /*!< Clock mode is HIRC 48 M */
kadonotakashi 0:8fdf9a60065b 401 kMCGLITE_ModeLirc8M, /*!< Clock mode is LIRC 8 M */
kadonotakashi 0:8fdf9a60065b 402 kMCGLITE_ModeLirc2M, /*!< Clock mode is LIRC 2 M */
kadonotakashi 0:8fdf9a60065b 403 kMCGLITE_ModeExt, /*!< Clock mode is EXT */
kadonotakashi 0:8fdf9a60065b 404 kMCGLITE_ModeError /*!< Unknown mode */
kadonotakashi 0:8fdf9a60065b 405 } mcglite_mode_t;
kadonotakashi 0:8fdf9a60065b 406
kadonotakashi 0:8fdf9a60065b 407 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
kadonotakashi 0:8fdf9a60065b 408 enum _mcglite_irclk_enable_mode
kadonotakashi 0:8fdf9a60065b 409 {
kadonotakashi 0:8fdf9a60065b 410 kMCGLITE_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
kadonotakashi 0:8fdf9a60065b 411 kMCGLITE_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
kadonotakashi 0:8fdf9a60065b 412 };
kadonotakashi 0:8fdf9a60065b 413
kadonotakashi 0:8fdf9a60065b 414 /*! @brief MCG_Lite configure structure for mode change. */
kadonotakashi 0:8fdf9a60065b 415 typedef struct _mcglite_config
kadonotakashi 0:8fdf9a60065b 416 {
kadonotakashi 0:8fdf9a60065b 417 mcglite_clkout_src_t outSrc; /*!< MCGOUT clock select. */
kadonotakashi 0:8fdf9a60065b 418 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode, OR'ed value of _mcglite_irclk_enable_mode. */
kadonotakashi 0:8fdf9a60065b 419 mcglite_lirc_mode_t ircs; /*!< MCG_C2[IRCS]. */
kadonotakashi 0:8fdf9a60065b 420 mcglite_lirc_div_t fcrdiv; /*!< MCG_SC[FCRDIV]. */
kadonotakashi 0:8fdf9a60065b 421 mcglite_lirc_div_t lircDiv2; /*!< MCG_MC[LIRC_DIV2]. */
kadonotakashi 0:8fdf9a60065b 422 bool hircEnableInNotHircMode; /*!< HIRC enable when not in HIRC mode. */
kadonotakashi 0:8fdf9a60065b 423 } mcglite_config_t;
kadonotakashi 0:8fdf9a60065b 424
kadonotakashi 0:8fdf9a60065b 425 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 426 * API
kadonotakashi 0:8fdf9a60065b 427 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 428
kadonotakashi 0:8fdf9a60065b 429 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 430 extern "C" {
kadonotakashi 0:8fdf9a60065b 431 #endif /* __cplusplus */
kadonotakashi 0:8fdf9a60065b 432
kadonotakashi 0:8fdf9a60065b 433 /*!
kadonotakashi 0:8fdf9a60065b 434 * @brief Set the XTAL0 frequency based on board setting.
kadonotakashi 0:8fdf9a60065b 435 *
kadonotakashi 0:8fdf9a60065b 436 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
kadonotakashi 0:8fdf9a60065b 437 */
kadonotakashi 0:8fdf9a60065b 438 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
kadonotakashi 0:8fdf9a60065b 439 {
kadonotakashi 0:8fdf9a60065b 440 g_xtal0Freq = freq;
kadonotakashi 0:8fdf9a60065b 441 }
kadonotakashi 0:8fdf9a60065b 442
kadonotakashi 0:8fdf9a60065b 443 /*!
kadonotakashi 0:8fdf9a60065b 444 * @brief Set the XTAL32/RTC_CLKIN frequency based on board setting.
kadonotakashi 0:8fdf9a60065b 445 *
kadonotakashi 0:8fdf9a60065b 446 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
kadonotakashi 0:8fdf9a60065b 447 */
kadonotakashi 0:8fdf9a60065b 448 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
kadonotakashi 0:8fdf9a60065b 449 {
kadonotakashi 0:8fdf9a60065b 450 g_xtal32Freq = freq;
kadonotakashi 0:8fdf9a60065b 451 }
kadonotakashi 0:8fdf9a60065b 452
kadonotakashi 0:8fdf9a60065b 453 /*!
kadonotakashi 0:8fdf9a60065b 454 * @brief Enable the clock for specific IP.
kadonotakashi 0:8fdf9a60065b 455 *
kadonotakashi 0:8fdf9a60065b 456 * @param name Which clock to enable, see \ref clock_ip_name_t.
kadonotakashi 0:8fdf9a60065b 457 */
kadonotakashi 0:8fdf9a60065b 458 static inline void CLOCK_EnableClock(clock_ip_name_t name)
kadonotakashi 0:8fdf9a60065b 459 {
kadonotakashi 0:8fdf9a60065b 460 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
kadonotakashi 0:8fdf9a60065b 461 (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
kadonotakashi 0:8fdf9a60065b 462 }
kadonotakashi 0:8fdf9a60065b 463
kadonotakashi 0:8fdf9a60065b 464 /*!
kadonotakashi 0:8fdf9a60065b 465 * @brief Disable the clock for specific IP.
kadonotakashi 0:8fdf9a60065b 466 *
kadonotakashi 0:8fdf9a60065b 467 * @param name Which clock to disable, see \ref clock_ip_name_t.
kadonotakashi 0:8fdf9a60065b 468 */
kadonotakashi 0:8fdf9a60065b 469 static inline void CLOCK_DisableClock(clock_ip_name_t name)
kadonotakashi 0:8fdf9a60065b 470 {
kadonotakashi 0:8fdf9a60065b 471 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
kadonotakashi 0:8fdf9a60065b 472 (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
kadonotakashi 0:8fdf9a60065b 473 }
kadonotakashi 0:8fdf9a60065b 474
kadonotakashi 0:8fdf9a60065b 475 /*!
kadonotakashi 0:8fdf9a60065b 476 * @brief Set ERCLK32K source.
kadonotakashi 0:8fdf9a60065b 477 *
kadonotakashi 0:8fdf9a60065b 478 * @param src The value to set ERCLK32K clock source.
kadonotakashi 0:8fdf9a60065b 479 */
kadonotakashi 0:8fdf9a60065b 480 static inline void CLOCK_SetEr32kClock(uint32_t src)
kadonotakashi 0:8fdf9a60065b 481 {
kadonotakashi 0:8fdf9a60065b 482 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
kadonotakashi 0:8fdf9a60065b 483 }
kadonotakashi 0:8fdf9a60065b 484
kadonotakashi 0:8fdf9a60065b 485 /*!
kadonotakashi 0:8fdf9a60065b 486 * @brief Set LPUART0 clock source.
kadonotakashi 0:8fdf9a60065b 487 *
kadonotakashi 0:8fdf9a60065b 488 * @param src The value to set LPUART0 clock source.
kadonotakashi 0:8fdf9a60065b 489 */
kadonotakashi 0:8fdf9a60065b 490 static inline void CLOCK_SetLpuart0Clock(uint32_t src)
kadonotakashi 0:8fdf9a60065b 491 {
kadonotakashi 0:8fdf9a60065b 492 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) | SIM_SOPT2_LPUART0SRC(src));
kadonotakashi 0:8fdf9a60065b 493 }
kadonotakashi 0:8fdf9a60065b 494
kadonotakashi 0:8fdf9a60065b 495 /*!
kadonotakashi 0:8fdf9a60065b 496 * @brief Set LPUART1 clock source.
kadonotakashi 0:8fdf9a60065b 497 *
kadonotakashi 0:8fdf9a60065b 498 * @param src The value to set LPUART1 clock source.
kadonotakashi 0:8fdf9a60065b 499 */
kadonotakashi 0:8fdf9a60065b 500 static inline void CLOCK_SetLpuart1Clock(uint32_t src)
kadonotakashi 0:8fdf9a60065b 501 {
kadonotakashi 0:8fdf9a60065b 502 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART1SRC_MASK) | SIM_SOPT2_LPUART1SRC(src));
kadonotakashi 0:8fdf9a60065b 503 }
kadonotakashi 0:8fdf9a60065b 504
kadonotakashi 0:8fdf9a60065b 505 /*!
kadonotakashi 0:8fdf9a60065b 506 * @brief Set TPM clock source.
kadonotakashi 0:8fdf9a60065b 507 *
kadonotakashi 0:8fdf9a60065b 508 * @param src The value to set TPM clock source.
kadonotakashi 0:8fdf9a60065b 509 */
kadonotakashi 0:8fdf9a60065b 510 static inline void CLOCK_SetTpmClock(uint32_t src)
kadonotakashi 0:8fdf9a60065b 511 {
kadonotakashi 0:8fdf9a60065b 512 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
kadonotakashi 0:8fdf9a60065b 513 }
kadonotakashi 0:8fdf9a60065b 514
kadonotakashi 0:8fdf9a60065b 515 /*!
kadonotakashi 0:8fdf9a60065b 516 * @brief Set FLEXIO clock source.
kadonotakashi 0:8fdf9a60065b 517 *
kadonotakashi 0:8fdf9a60065b 518 * @param src The value to set FLEXIO clock source.
kadonotakashi 0:8fdf9a60065b 519 */
kadonotakashi 0:8fdf9a60065b 520 static inline void CLOCK_SetFlexio0Clock(uint32_t src)
kadonotakashi 0:8fdf9a60065b 521 {
kadonotakashi 0:8fdf9a60065b 522 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_FLEXIOSRC_MASK) | SIM_SOPT2_FLEXIOSRC(src));
kadonotakashi 0:8fdf9a60065b 523 }
kadonotakashi 0:8fdf9a60065b 524
kadonotakashi 0:8fdf9a60065b 525 /*! @brief Enable USB FS clock.
kadonotakashi 0:8fdf9a60065b 526 *
kadonotakashi 0:8fdf9a60065b 527 * @param src USB FS clock source.
kadonotakashi 0:8fdf9a60065b 528 * @param freq The frequency specified by src.
kadonotakashi 0:8fdf9a60065b 529 * @retval true The clock is set successfully.
kadonotakashi 0:8fdf9a60065b 530 * @retval false The clock source is invalid to get proper USB FS clock.
kadonotakashi 0:8fdf9a60065b 531 */
kadonotakashi 0:8fdf9a60065b 532 bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
kadonotakashi 0:8fdf9a60065b 533
kadonotakashi 0:8fdf9a60065b 534 /*! @brief Disable USB FS clock.
kadonotakashi 0:8fdf9a60065b 535 *
kadonotakashi 0:8fdf9a60065b 536 * Disable USB FS clock.
kadonotakashi 0:8fdf9a60065b 537 */
kadonotakashi 0:8fdf9a60065b 538 static inline void CLOCK_DisableUsbfs0Clock(void)
kadonotakashi 0:8fdf9a60065b 539 {
kadonotakashi 0:8fdf9a60065b 540 CLOCK_DisableClock(kCLOCK_Usbfs0);
kadonotakashi 0:8fdf9a60065b 541 }
kadonotakashi 0:8fdf9a60065b 542
kadonotakashi 0:8fdf9a60065b 543 /*!
kadonotakashi 0:8fdf9a60065b 544 * @brief Set CLKOUT source.
kadonotakashi 0:8fdf9a60065b 545 *
kadonotakashi 0:8fdf9a60065b 546 * @param src The value to set CLKOUT source.
kadonotakashi 0:8fdf9a60065b 547 */
kadonotakashi 0:8fdf9a60065b 548 static inline void CLOCK_SetClkOutClock(uint32_t src)
kadonotakashi 0:8fdf9a60065b 549 {
kadonotakashi 0:8fdf9a60065b 550 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
kadonotakashi 0:8fdf9a60065b 551 }
kadonotakashi 0:8fdf9a60065b 552
kadonotakashi 0:8fdf9a60065b 553 /*!
kadonotakashi 0:8fdf9a60065b 554 * @brief Set RTC_CLKOUT source.
kadonotakashi 0:8fdf9a60065b 555 *
kadonotakashi 0:8fdf9a60065b 556 * @param src The value to set RTC_CLKOUT source.
kadonotakashi 0:8fdf9a60065b 557 */
kadonotakashi 0:8fdf9a60065b 558 static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
kadonotakashi 0:8fdf9a60065b 559 {
kadonotakashi 0:8fdf9a60065b 560 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
kadonotakashi 0:8fdf9a60065b 561 }
kadonotakashi 0:8fdf9a60065b 562
kadonotakashi 0:8fdf9a60065b 563 /*!
kadonotakashi 0:8fdf9a60065b 564 * @brief System clock divider
kadonotakashi 0:8fdf9a60065b 565 *
kadonotakashi 0:8fdf9a60065b 566 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV4].
kadonotakashi 0:8fdf9a60065b 567 *
kadonotakashi 0:8fdf9a60065b 568 * @param outdiv1 Clock 1 output divider value.
kadonotakashi 0:8fdf9a60065b 569 *
kadonotakashi 0:8fdf9a60065b 570 * @param outdiv4 Clock 4 output divider value.
kadonotakashi 0:8fdf9a60065b 571 */
kadonotakashi 0:8fdf9a60065b 572 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv4)
kadonotakashi 0:8fdf9a60065b 573 {
kadonotakashi 0:8fdf9a60065b 574 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4);
kadonotakashi 0:8fdf9a60065b 575 }
kadonotakashi 0:8fdf9a60065b 576
kadonotakashi 0:8fdf9a60065b 577 /*!
kadonotakashi 0:8fdf9a60065b 578 * @brief Gets the clock frequency for a specific clock name.
kadonotakashi 0:8fdf9a60065b 579 *
kadonotakashi 0:8fdf9a60065b 580 * This function checks the current clock configurations and then calculates
kadonotakashi 0:8fdf9a60065b 581 * the clock frequency for a specific clock name defined in clock_name_t.
kadonotakashi 0:8fdf9a60065b 582 * The MCG must be properly configured before using this function.
kadonotakashi 0:8fdf9a60065b 583 *
kadonotakashi 0:8fdf9a60065b 584 * @param clockName Clock names defined in clock_name_t
kadonotakashi 0:8fdf9a60065b 585 * @return Clock frequency value in Hertz
kadonotakashi 0:8fdf9a60065b 586 */
kadonotakashi 0:8fdf9a60065b 587 uint32_t CLOCK_GetFreq(clock_name_t clockName);
kadonotakashi 0:8fdf9a60065b 588
kadonotakashi 0:8fdf9a60065b 589 /*!
kadonotakashi 0:8fdf9a60065b 590 * @brief Get the core clock or system clock frequency.
kadonotakashi 0:8fdf9a60065b 591 *
kadonotakashi 0:8fdf9a60065b 592 * @return Clock frequency in Hz.
kadonotakashi 0:8fdf9a60065b 593 */
kadonotakashi 0:8fdf9a60065b 594 uint32_t CLOCK_GetCoreSysClkFreq(void);
kadonotakashi 0:8fdf9a60065b 595
kadonotakashi 0:8fdf9a60065b 596 /*!
kadonotakashi 0:8fdf9a60065b 597 * @brief Get the platform clock frequency.
kadonotakashi 0:8fdf9a60065b 598 *
kadonotakashi 0:8fdf9a60065b 599 * @return Clock frequency in Hz.
kadonotakashi 0:8fdf9a60065b 600 */
kadonotakashi 0:8fdf9a60065b 601 uint32_t CLOCK_GetPlatClkFreq(void);
kadonotakashi 0:8fdf9a60065b 602
kadonotakashi 0:8fdf9a60065b 603 /*!
kadonotakashi 0:8fdf9a60065b 604 * @brief Get the bus clock frequency.
kadonotakashi 0:8fdf9a60065b 605 *
kadonotakashi 0:8fdf9a60065b 606 * @return Clock frequency in Hz.
kadonotakashi 0:8fdf9a60065b 607 */
kadonotakashi 0:8fdf9a60065b 608 uint32_t CLOCK_GetBusClkFreq(void);
kadonotakashi 0:8fdf9a60065b 609
kadonotakashi 0:8fdf9a60065b 610 /*!
kadonotakashi 0:8fdf9a60065b 611 * @brief Get the flash clock frequency.
kadonotakashi 0:8fdf9a60065b 612 *
kadonotakashi 0:8fdf9a60065b 613 * @return Clock frequency in Hz.
kadonotakashi 0:8fdf9a60065b 614 */
kadonotakashi 0:8fdf9a60065b 615 uint32_t CLOCK_GetFlashClkFreq(void);
kadonotakashi 0:8fdf9a60065b 616
kadonotakashi 0:8fdf9a60065b 617 /*!
kadonotakashi 0:8fdf9a60065b 618 * @brief Get the external reference 32K clock frequency (ERCLK32K).
kadonotakashi 0:8fdf9a60065b 619 *
kadonotakashi 0:8fdf9a60065b 620 * @return Clock frequency in Hz.
kadonotakashi 0:8fdf9a60065b 621 */
kadonotakashi 0:8fdf9a60065b 622 uint32_t CLOCK_GetEr32kClkFreq(void);
kadonotakashi 0:8fdf9a60065b 623
kadonotakashi 0:8fdf9a60065b 624 /*!
kadonotakashi 0:8fdf9a60065b 625 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
kadonotakashi 0:8fdf9a60065b 626 *
kadonotakashi 0:8fdf9a60065b 627 * @return Clock frequency in Hz.
kadonotakashi 0:8fdf9a60065b 628 */
kadonotakashi 0:8fdf9a60065b 629 uint32_t CLOCK_GetOsc0ErClkFreq(void);
kadonotakashi 0:8fdf9a60065b 630
kadonotakashi 0:8fdf9a60065b 631 /*!
kadonotakashi 0:8fdf9a60065b 632 * @brief Set the clock configure in SIM module.
kadonotakashi 0:8fdf9a60065b 633 *
kadonotakashi 0:8fdf9a60065b 634 * This function sets system layer clock settings in SIM module.
kadonotakashi 0:8fdf9a60065b 635 *
kadonotakashi 0:8fdf9a60065b 636 * @param config Pointer to the configure structure.
kadonotakashi 0:8fdf9a60065b 637 */
kadonotakashi 0:8fdf9a60065b 638 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
kadonotakashi 0:8fdf9a60065b 639
kadonotakashi 0:8fdf9a60065b 640 /*!
kadonotakashi 0:8fdf9a60065b 641 * @brief Set the system clock dividers in SIM to safe value.
kadonotakashi 0:8fdf9a60065b 642 *
kadonotakashi 0:8fdf9a60065b 643 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
kadonotakashi 0:8fdf9a60065b 644 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
kadonotakashi 0:8fdf9a60065b 645 * changes then the system level clocks may be out of range. This function could
kadonotakashi 0:8fdf9a60065b 646 * be used before MCG mode change, to make sure system level clocks are in allowed
kadonotakashi 0:8fdf9a60065b 647 * range.
kadonotakashi 0:8fdf9a60065b 648 *
kadonotakashi 0:8fdf9a60065b 649 * @param config Pointer to the configure structure.
kadonotakashi 0:8fdf9a60065b 650 */
kadonotakashi 0:8fdf9a60065b 651 static inline void CLOCK_SetSimSafeDivs(void)
kadonotakashi 0:8fdf9a60065b 652 {
kadonotakashi 0:8fdf9a60065b 653 SIM->CLKDIV1 = 0x10030000U;
kadonotakashi 0:8fdf9a60065b 654 }
kadonotakashi 0:8fdf9a60065b 655
kadonotakashi 0:8fdf9a60065b 656 /*!
kadonotakashi 0:8fdf9a60065b 657 * @name MCG_Lite clock frequency
kadonotakashi 0:8fdf9a60065b 658 * @{
kadonotakashi 0:8fdf9a60065b 659 */
kadonotakashi 0:8fdf9a60065b 660
kadonotakashi 0:8fdf9a60065b 661 /*!
kadonotakashi 0:8fdf9a60065b 662 * @brief Gets the MCG_Lite output clock (MCGOUTCLK) frequency.
kadonotakashi 0:8fdf9a60065b 663 *
kadonotakashi 0:8fdf9a60065b 664 * This function gets the MCG_Lite output clock frequency (Hz) based on the current
kadonotakashi 0:8fdf9a60065b 665 * MCG_Lite register value.
kadonotakashi 0:8fdf9a60065b 666 *
kadonotakashi 0:8fdf9a60065b 667 * @return The frequency of MCGOUTCLK.
kadonotakashi 0:8fdf9a60065b 668 */
kadonotakashi 0:8fdf9a60065b 669 uint32_t CLOCK_GetOutClkFreq(void);
kadonotakashi 0:8fdf9a60065b 670
kadonotakashi 0:8fdf9a60065b 671 /*!
kadonotakashi 0:8fdf9a60065b 672 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
kadonotakashi 0:8fdf9a60065b 673 *
kadonotakashi 0:8fdf9a60065b 674 * This function gets the MCG_Lite internal reference clock frequency (Hz) based
kadonotakashi 0:8fdf9a60065b 675 * on the current MCG register value.
kadonotakashi 0:8fdf9a60065b 676 *
kadonotakashi 0:8fdf9a60065b 677 * @return The frequency of MCGIRCLK.
kadonotakashi 0:8fdf9a60065b 678 */
kadonotakashi 0:8fdf9a60065b 679 uint32_t CLOCK_GetInternalRefClkFreq(void);
kadonotakashi 0:8fdf9a60065b 680
kadonotakashi 0:8fdf9a60065b 681 /*!
kadonotakashi 0:8fdf9a60065b 682 * @brief Gets the current MCGPCLK frequency.
kadonotakashi 0:8fdf9a60065b 683 *
kadonotakashi 0:8fdf9a60065b 684 * This function gets the MCGPCLK frequency (Hertz) based on the current MCG_Lite
kadonotakashi 0:8fdf9a60065b 685 * register settings.
kadonotakashi 0:8fdf9a60065b 686 *
kadonotakashi 0:8fdf9a60065b 687 * @return The frequency of MCGPCLK.
kadonotakashi 0:8fdf9a60065b 688 */
kadonotakashi 0:8fdf9a60065b 689 uint32_t CLOCK_GetPeriphClkFreq(void);
kadonotakashi 0:8fdf9a60065b 690
kadonotakashi 0:8fdf9a60065b 691 /*! @}*/
kadonotakashi 0:8fdf9a60065b 692
kadonotakashi 0:8fdf9a60065b 693 /*!
kadonotakashi 0:8fdf9a60065b 694 * @name MCG_Lite mode.
kadonotakashi 0:8fdf9a60065b 695 * @{
kadonotakashi 0:8fdf9a60065b 696 */
kadonotakashi 0:8fdf9a60065b 697
kadonotakashi 0:8fdf9a60065b 698 /*!
kadonotakashi 0:8fdf9a60065b 699 * @brief Gets the current MCG_Lite mode.
kadonotakashi 0:8fdf9a60065b 700 *
kadonotakashi 0:8fdf9a60065b 701 * This function checks the MCG_Lite registers and determines the current MCG_Lite mode.
kadonotakashi 0:8fdf9a60065b 702 *
kadonotakashi 0:8fdf9a60065b 703 * @return Current MCG_Lite mode or error code.
kadonotakashi 0:8fdf9a60065b 704 */
kadonotakashi 0:8fdf9a60065b 705 mcglite_mode_t CLOCK_GetMode(void);
kadonotakashi 0:8fdf9a60065b 706
kadonotakashi 0:8fdf9a60065b 707 /*!
kadonotakashi 0:8fdf9a60065b 708 * @brief Sets the MCG_Lite configuration.
kadonotakashi 0:8fdf9a60065b 709 *
kadonotakashi 0:8fdf9a60065b 710 * This function configures the MCG_Lite, include output clock source, MCGIRCLK
kadonotakashi 0:8fdf9a60065b 711 * setting, HIRC setting and so on, see @ref mcglite_config_t for details.
kadonotakashi 0:8fdf9a60065b 712 *
kadonotakashi 0:8fdf9a60065b 713 * @param targetConfig Pointer to the target MCG_Lite mode configuration structure.
kadonotakashi 0:8fdf9a60065b 714 * @return Error code.
kadonotakashi 0:8fdf9a60065b 715 */
kadonotakashi 0:8fdf9a60065b 716 status_t CLOCK_SetMcgliteConfig(mcglite_config_t const *targetConfig);
kadonotakashi 0:8fdf9a60065b 717
kadonotakashi 0:8fdf9a60065b 718 /*! @}*/
kadonotakashi 0:8fdf9a60065b 719
kadonotakashi 0:8fdf9a60065b 720 /*!
kadonotakashi 0:8fdf9a60065b 721 * @name OSC configuration
kadonotakashi 0:8fdf9a60065b 722 * @{
kadonotakashi 0:8fdf9a60065b 723 */
kadonotakashi 0:8fdf9a60065b 724
kadonotakashi 0:8fdf9a60065b 725 /*!
kadonotakashi 0:8fdf9a60065b 726 * @brief Configures the OSC external reference clock (OSCERCLK).
kadonotakashi 0:8fdf9a60065b 727 *
kadonotakashi 0:8fdf9a60065b 728 * This function configures the OSC external reference clock (OSCERCLK).
kadonotakashi 0:8fdf9a60065b 729 * For example, to enable the OSCERCLK in normal mode and stop mode, and also set
kadonotakashi 0:8fdf9a60065b 730 * the output divider to 1, as follows:
kadonotakashi 0:8fdf9a60065b 731 *
kadonotakashi 0:8fdf9a60065b 732 @code
kadonotakashi 0:8fdf9a60065b 733 oscer_config_t config =
kadonotakashi 0:8fdf9a60065b 734 {
kadonotakashi 0:8fdf9a60065b 735 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
kadonotakashi 0:8fdf9a60065b 736 .erclkDiv = 1U,
kadonotakashi 0:8fdf9a60065b 737 };
kadonotakashi 0:8fdf9a60065b 738
kadonotakashi 0:8fdf9a60065b 739 OSC_SetExtRefClkConfig(OSC, &config);
kadonotakashi 0:8fdf9a60065b 740 @endcode
kadonotakashi 0:8fdf9a60065b 741 *
kadonotakashi 0:8fdf9a60065b 742 * @param base OSC peripheral address.
kadonotakashi 0:8fdf9a60065b 743 * @param config Pointer to the configuration structure.
kadonotakashi 0:8fdf9a60065b 744 */
kadonotakashi 0:8fdf9a60065b 745 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
kadonotakashi 0:8fdf9a60065b 746 {
kadonotakashi 0:8fdf9a60065b 747 uint8_t reg = base->CR;
kadonotakashi 0:8fdf9a60065b 748
kadonotakashi 0:8fdf9a60065b 749 reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK);
kadonotakashi 0:8fdf9a60065b 750 reg |= config->enableMode;
kadonotakashi 0:8fdf9a60065b 751
kadonotakashi 0:8fdf9a60065b 752 base->CR = reg;
kadonotakashi 0:8fdf9a60065b 753 }
kadonotakashi 0:8fdf9a60065b 754
kadonotakashi 0:8fdf9a60065b 755 /*!
kadonotakashi 0:8fdf9a60065b 756 * @brief Sets the capacitor load configuration for the oscillator.
kadonotakashi 0:8fdf9a60065b 757 *
kadonotakashi 0:8fdf9a60065b 758 * This function sets the specified capacitors configuration for the oscillator.
kadonotakashi 0:8fdf9a60065b 759 * This should be done in the early system level initialization function call
kadonotakashi 0:8fdf9a60065b 760 * based on the system configuration.
kadonotakashi 0:8fdf9a60065b 761 *
kadonotakashi 0:8fdf9a60065b 762 * @param base OSC peripheral address.
kadonotakashi 0:8fdf9a60065b 763 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
kadonotakashi 0:8fdf9a60065b 764 *
kadonotakashi 0:8fdf9a60065b 765 * Example:
kadonotakashi 0:8fdf9a60065b 766 @code
kadonotakashi 0:8fdf9a60065b 767 // To enable only 2 pF and 8 pF capacitor load, please use like this.
kadonotakashi 0:8fdf9a60065b 768 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
kadonotakashi 0:8fdf9a60065b 769 @endcode
kadonotakashi 0:8fdf9a60065b 770 */
kadonotakashi 0:8fdf9a60065b 771
kadonotakashi 0:8fdf9a60065b 772 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
kadonotakashi 0:8fdf9a60065b 773 {
kadonotakashi 0:8fdf9a60065b 774 uint8_t reg = base->CR;
kadonotakashi 0:8fdf9a60065b 775
kadonotakashi 0:8fdf9a60065b 776 reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK);
kadonotakashi 0:8fdf9a60065b 777 reg |= capLoad;
kadonotakashi 0:8fdf9a60065b 778
kadonotakashi 0:8fdf9a60065b 779 base->CR = reg;
kadonotakashi 0:8fdf9a60065b 780 }
kadonotakashi 0:8fdf9a60065b 781
kadonotakashi 0:8fdf9a60065b 782 /*!
kadonotakashi 0:8fdf9a60065b 783 * @brief Initialize OSC0.
kadonotakashi 0:8fdf9a60065b 784 *
kadonotakashi 0:8fdf9a60065b 785 * This function initializes the OSC0 according to the board configuration.
kadonotakashi 0:8fdf9a60065b 786 *
kadonotakashi 0:8fdf9a60065b 787 * @param config Pointer to the OSC0 configuration structure.
kadonotakashi 0:8fdf9a60065b 788 */
kadonotakashi 0:8fdf9a60065b 789 void CLOCK_InitOsc0(osc_config_t const *config);
kadonotakashi 0:8fdf9a60065b 790
kadonotakashi 0:8fdf9a60065b 791 /*!
kadonotakashi 0:8fdf9a60065b 792 * @brief Deinitializes the OSC0.
kadonotakashi 0:8fdf9a60065b 793 *
kadonotakashi 0:8fdf9a60065b 794 * This function deinitializes the OSC0.
kadonotakashi 0:8fdf9a60065b 795 */
kadonotakashi 0:8fdf9a60065b 796 void CLOCK_DeinitOsc0(void);
kadonotakashi 0:8fdf9a60065b 797
kadonotakashi 0:8fdf9a60065b 798 /*! @}*/
kadonotakashi 0:8fdf9a60065b 799
kadonotakashi 0:8fdf9a60065b 800 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 801 }
kadonotakashi 0:8fdf9a60065b 802 #endif /* __cplusplus */
kadonotakashi 0:8fdf9a60065b 803
kadonotakashi 0:8fdf9a60065b 804 /*! @} */
kadonotakashi 0:8fdf9a60065b 805
kadonotakashi 0:8fdf9a60065b 806 #endif /* _FSL_CLOCK_H_ */