Nucleo446_SSD1331 - Color Oled(SSD1331) connect to STMicroelectronics…

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takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_trng.c@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:: kadonotakashi
Date:: Thu Oct 11 02:27:46 2018 +0000
Revision:: 3:f3764f852aa8
Parent:: 0:8fdf9a60065b

Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

User	Revision	Line number	New contents of line
kadonotakashi	0:8fdf9a60065b	1	/*
kadonotakashi	0:8fdf9a60065b	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
kadonotakashi	0:8fdf9a60065b	3	* All rights reserved.
kadonotakashi	0:8fdf9a60065b	4	*
kadonotakashi	0:8fdf9a60065b	5	* Redistribution and use in source and binary forms, with or without modification,
kadonotakashi	0:8fdf9a60065b	6	* are permitted provided that the following conditions are met:
kadonotakashi	0:8fdf9a60065b	7	*
kadonotakashi	0:8fdf9a60065b	8	* o Redistributions of source code must retain the above copyright notice, this list
kadonotakashi	0:8fdf9a60065b	9	* of conditions and the following disclaimer.
kadonotakashi	0:8fdf9a60065b	10	*
kadonotakashi	0:8fdf9a60065b	11	* o Redistributions in binary form must reproduce the above copyright notice, this
kadonotakashi	0:8fdf9a60065b	12	* list of conditions and the following disclaimer in the documentation and/or
kadonotakashi	0:8fdf9a60065b	13	* other materials provided with the distribution.
kadonotakashi	0:8fdf9a60065b	14	*
kadonotakashi	0:8fdf9a60065b	15	* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kadonotakashi	0:8fdf9a60065b	16	* contributors may be used to endorse or promote products derived from this
kadonotakashi	0:8fdf9a60065b	17	* software without specific prior written permission.
kadonotakashi	0:8fdf9a60065b	18	*
kadonotakashi	0:8fdf9a60065b	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kadonotakashi	0:8fdf9a60065b	20	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kadonotakashi	0:8fdf9a60065b	21	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kadonotakashi	0:8fdf9a60065b	22	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kadonotakashi	0:8fdf9a60065b	23	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kadonotakashi	0:8fdf9a60065b	24	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kadonotakashi	0:8fdf9a60065b	25	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kadonotakashi	0:8fdf9a60065b	26	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kadonotakashi	0:8fdf9a60065b	27	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kadonotakashi	0:8fdf9a60065b	28	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kadonotakashi	0:8fdf9a60065b	29	*/
kadonotakashi	0:8fdf9a60065b	30	#include "fsl_trng.h"
kadonotakashi	0:8fdf9a60065b	31
kadonotakashi	0:8fdf9a60065b	32	#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT
kadonotakashi	0:8fdf9a60065b	33
kadonotakashi	0:8fdf9a60065b	34	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	35	* Definitions
kadonotakashi	0:8fdf9a60065b	36	*******************************************************************************/
kadonotakashi	0:8fdf9a60065b	37	/* Default values for user configuration structure.*/
kadonotakashi	0:8fdf9a60065b	38	#if (defined(KW40Z4_SERIES) \|\| defined(KW41Z4_SERIES) \|\| defined(KW31Z4_SERIES) \|\| defined(KW21Z4_SERIES))
kadonotakashi	0:8fdf9a60065b	39	#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8
kadonotakashi	0:8fdf9a60065b	40	#elif(defined(KV56F24_SERIES) \|\| defined(KV58F24_SERIES) \|\| defined(KL28Z7_SERIES) \|\| defined(KL81Z7_SERIES) \|\| \
kadonotakashi	0:8fdf9a60065b	41	defined(KL82Z7_SERIES))
kadonotakashi	0:8fdf9a60065b	42	#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4
kadonotakashi	0:8fdf9a60065b	43	#elif defined(K81F25615_SERIES)
kadonotakashi	0:8fdf9a60065b	44	#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2
kadonotakashi	0:8fdf9a60065b	45	#else
kadonotakashi	0:8fdf9a60065b	46	#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv0
kadonotakashi	0:8fdf9a60065b	47	#endif
kadonotakashi	0:8fdf9a60065b	48
kadonotakashi	0:8fdf9a60065b	49	#define TRNG_USER_CONFIG_DEFAULT_LOCK 0
kadonotakashi	0:8fdf9a60065b	50	#define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200
kadonotakashi	0:8fdf9a60065b	51	#define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 2500
kadonotakashi	0:8fdf9a60065b	52	#define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63
kadonotakashi	0:8fdf9a60065b	53	#define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1
kadonotakashi	0:8fdf9a60065b	54	#define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 34
kadonotakashi	0:8fdf9a60065b	55
kadonotakashi	0:8fdf9a60065b	56	#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 1384
kadonotakashi	0:8fdf9a60065b	57	#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 268)
kadonotakashi	0:8fdf9a60065b	58	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 405
kadonotakashi	0:8fdf9a60065b	59	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 178)
kadonotakashi	0:8fdf9a60065b	60	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 220
kadonotakashi	0:8fdf9a60065b	61	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 122)
kadonotakashi	0:8fdf9a60065b	62	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 125
kadonotakashi	0:8fdf9a60065b	63	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 88)
kadonotakashi	0:8fdf9a60065b	64	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 75
kadonotakashi	0:8fdf9a60065b	65	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 64)
kadonotakashi	0:8fdf9a60065b	66	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 47
kadonotakashi	0:8fdf9a60065b	67	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 46)
kadonotakashi	0:8fdf9a60065b	68	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 47
kadonotakashi	0:8fdf9a60065b	69	#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 46)
kadonotakashi	0:8fdf9a60065b	70	#define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 26912
kadonotakashi	0:8fdf9a60065b	71	#define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 2467)
kadonotakashi	0:8fdf9a60065b	72	#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 25600
kadonotakashi	0:8fdf9a60065b	73	#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1600
kadonotakashi	0:8fdf9a60065b	74
kadonotakashi	0:8fdf9a60065b	75	/! @brief TRNG work mode /
kadonotakashi	0:8fdf9a60065b	76	typedef enum _trng_work_mode
kadonotakashi	0:8fdf9a60065b	77	{
kadonotakashi	0:8fdf9a60065b	78	kTRNG_WorkModeRun = 0U, /!< Run Mode. /
kadonotakashi	0:8fdf9a60065b	79	kTRNG_WorkModeProgram = 1U /!< Program Mode. /
kadonotakashi	0:8fdf9a60065b	80	} trng_work_mode_t;
kadonotakashi	0:8fdf9a60065b	81
kadonotakashi	0:8fdf9a60065b	82	/! @brief TRNG statistical check type/
kadonotakashi	0:8fdf9a60065b	83	typedef enum _trng_statistical_check
kadonotakashi	0:8fdf9a60065b	84	{
kadonotakashi	0:8fdf9a60065b	85	kTRNG_StatisticalCheckMonobit =
kadonotakashi	0:8fdf9a60065b	86	1U, /!< Statistical check of number of ones/zero detected during entropy generation. /
kadonotakashi	0:8fdf9a60065b	87	kTRNG_StatisticalCheckRunBit1, /*!< Statistical check of number of runs of length 1 detected during entropy
kadonotakashi	0:8fdf9a60065b	88	generation. */
kadonotakashi	0:8fdf9a60065b	89	kTRNG_StatisticalCheckRunBit2, /*!< Statistical check of number of runs of length 2 detected during entropy
kadonotakashi	0:8fdf9a60065b	90	generation. */
kadonotakashi	0:8fdf9a60065b	91	kTRNG_StatisticalCheckRunBit3, /*!< Statistical check of number of runs of length 3 detected during entropy
kadonotakashi	0:8fdf9a60065b	92	generation. */
kadonotakashi	0:8fdf9a60065b	93	kTRNG_StatisticalCheckRunBit4, /*!< Statistical check of number of runs of length 4 detected during entropy
kadonotakashi	0:8fdf9a60065b	94	generation. */
kadonotakashi	0:8fdf9a60065b	95	kTRNG_StatisticalCheckRunBit5, /*!< Statistical check of number of runs of length 5 detected during entropy
kadonotakashi	0:8fdf9a60065b	96	generation. */
kadonotakashi	0:8fdf9a60065b	97	kTRNG_StatisticalCheckRunBit6Plus, /*!< Statistical check of number of runs of length 6 or more detected during
kadonotakashi	0:8fdf9a60065b	98	entropy generation. */
kadonotakashi	0:8fdf9a60065b	99	kTRNG_StatisticalCheckPoker, /!< Statistical check of "Poker Test". /
kadonotakashi	0:8fdf9a60065b	100	kTRNG_StatisticalCheckFrequencyCount /!< Statistical check of entropy sample frequency count. /
kadonotakashi	0:8fdf9a60065b	101	} trng_statistical_check_t;
kadonotakashi	0:8fdf9a60065b	102
kadonotakashi	0:8fdf9a60065b	103	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	104	* TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
kadonotakashi	0:8fdf9a60065b	105	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	106	/*!
kadonotakashi	0:8fdf9a60065b	107	* @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW)
kadonotakashi	0:8fdf9a60065b	108	*
kadonotakashi	0:8fdf9a60065b	109	* RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation,
kadonotakashi	0:8fdf9a60065b	110	* the RTY_CT value indicates the number of times a retry should occur before
kadonotakashi	0:8fdf9a60065b	111	* generating an error. This field is writable only if MCTL[PRGM] bit is 1. This
kadonotakashi	0:8fdf9a60065b	112	* field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing
kadonotakashi	0:8fdf9a60065b	113	* the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	114	*/
kadonotakashi	0:8fdf9a60065b	115	/@{/
kadonotakashi	0:8fdf9a60065b	116	/! @brief Read current value of the TRNG_SCMISC_RTY_CT field. /
kadonotakashi	0:8fdf9a60065b	117	#define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT)
kadonotakashi	0:8fdf9a60065b	118
kadonotakashi	0:8fdf9a60065b	119	/! @brief Set the RTY_CT field to a new value. /
kadonotakashi	0:8fdf9a60065b	120	#define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value)))
kadonotakashi	0:8fdf9a60065b	121	/@}/
kadonotakashi	0:8fdf9a60065b	122
kadonotakashi	0:8fdf9a60065b	123	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	124	* TRNG_SCML - RNG Statistical Check Monobit Limit Register
kadonotakashi	0:8fdf9a60065b	125	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	126	/*!
kadonotakashi	0:8fdf9a60065b	127	* @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW)
kadonotakashi	0:8fdf9a60065b	128	*
kadonotakashi	0:8fdf9a60065b	129	* Reset value: 0x010C0568U
kadonotakashi	0:8fdf9a60065b	130	*
kadonotakashi	0:8fdf9a60065b	131	* The RNG Statistical Check Monobit Limit Register defines the allowable
kadonotakashi	0:8fdf9a60065b	132	* maximum and minimum number of ones/zero detected during entropy generation. To pass
kadonotakashi	0:8fdf9a60065b	133	* the test, the number of ones/zeroes generated must be less than the programmed
kadonotakashi	0:8fdf9a60065b	134	* maximum value, and the number of ones/zeroes generated must be greater than
kadonotakashi	0:8fdf9a60065b	135	* (maximum - range). If this test fails, the Retry Counter in SCMISC will be
kadonotakashi	0:8fdf9a60065b	136	* decremented, and a retry will occur if the Retry Count has not reached zero. If
kadonotakashi	0:8fdf9a60065b	137	* the Retry Count has reached zero, an error will be generated. Note that this
kadonotakashi	0:8fdf9a60065b	138	* offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0,
kadonotakashi	0:8fdf9a60065b	139	* this offset is used as SCMC readback register.
kadonotakashi	0:8fdf9a60065b	140	*/
kadonotakashi	0:8fdf9a60065b	141	/*!
kadonotakashi	0:8fdf9a60065b	142	* @name Constants and macros for entire TRNG_SCML register
kadonotakashi	0:8fdf9a60065b	143	*/
kadonotakashi	0:8fdf9a60065b	144	/@{/
kadonotakashi	0:8fdf9a60065b	145	#define TRNG_SCML_REG(base) ((base)->SCML)
kadonotakashi	0:8fdf9a60065b	146	#define TRNG_RD_SCML(base) (TRNG_SCML_REG(base))
kadonotakashi	0:8fdf9a60065b	147	#define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	148	#define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	149	/@}/
kadonotakashi	0:8fdf9a60065b	150	/*!
kadonotakashi	0:8fdf9a60065b	151	* @name Register TRNG_SCML, field MONO_MAX[15:0] (RW)
kadonotakashi	0:8fdf9a60065b	152	*
kadonotakashi	0:8fdf9a60065b	153	* Monobit Maximum Limit. Defines the maximum allowable count taken during
kadonotakashi	0:8fdf9a60065b	154	* entropy generation. The number of ones/zeroes detected during entropy generation
kadonotakashi	0:8fdf9a60065b	155	* must be less than MONO_MAX, else a retry or error will occur. This register is
kadonotakashi	0:8fdf9a60065b	156	* cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	157	*/
kadonotakashi	0:8fdf9a60065b	158	/@{/
kadonotakashi	0:8fdf9a60065b	159	/! @brief Read current value of the TRNG_SCML_MONO_MAX field. /
kadonotakashi	0:8fdf9a60065b	160	#define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT)
kadonotakashi	0:8fdf9a60065b	161
kadonotakashi	0:8fdf9a60065b	162	/! @brief Set the MONO_MAX field to a new value. /
kadonotakashi	0:8fdf9a60065b	163	#define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value)))
kadonotakashi	0:8fdf9a60065b	164	/@}/
kadonotakashi	0:8fdf9a60065b	165	/*!
kadonotakashi	0:8fdf9a60065b	166	* @name Register TRNG_SCML, field MONO_RNG[31:16] (RW)
kadonotakashi	0:8fdf9a60065b	167	*
kadonotakashi	0:8fdf9a60065b	168	* Monobit Range. The number of ones/zeroes detected during entropy generation
kadonotakashi	0:8fdf9a60065b	169	* must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur.
kadonotakashi	0:8fdf9a60065b	170	* This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF]
kadonotakashi	0:8fdf9a60065b	171	* bit to 1.
kadonotakashi	0:8fdf9a60065b	172	*/
kadonotakashi	0:8fdf9a60065b	173	/@{/
kadonotakashi	0:8fdf9a60065b	174	/! @brief Read current value of the TRNG_SCML_MONO_RNG field. /
kadonotakashi	0:8fdf9a60065b	175	#define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT)
kadonotakashi	0:8fdf9a60065b	176
kadonotakashi	0:8fdf9a60065b	177	/! @brief Set the MONO_RNG field to a new value. /
kadonotakashi	0:8fdf9a60065b	178	#define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value)))
kadonotakashi	0:8fdf9a60065b	179	/@}/
kadonotakashi	0:8fdf9a60065b	180
kadonotakashi	0:8fdf9a60065b	181	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	182	* TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register
kadonotakashi	0:8fdf9a60065b	183	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	184
kadonotakashi	0:8fdf9a60065b	185	/*!
kadonotakashi	0:8fdf9a60065b	186	* @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW)
kadonotakashi	0:8fdf9a60065b	187	*
kadonotakashi	0:8fdf9a60065b	188	* Reset value: 0x00B20195U
kadonotakashi	0:8fdf9a60065b	189	*
kadonotakashi	0:8fdf9a60065b	190	* The RNG Statistical Check Run Length 1 Limit Register defines the allowable
kadonotakashi	0:8fdf9a60065b	191	* maximum and minimum number of runs of length 1 detected during entropy
kadonotakashi	0:8fdf9a60065b	192	* generation. To pass the test, the number of runs of length 1 (for samples of both 0
kadonotakashi	0:8fdf9a60065b	193	* and 1) must be less than the programmed maximum value, and the number of runs of
kadonotakashi	0:8fdf9a60065b	194	* length 1 must be greater than (maximum - range). If this test fails, the
kadonotakashi	0:8fdf9a60065b	195	* Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
kadonotakashi	0:8fdf9a60065b	196	* Count has not reached zero. If the Retry Count has reached zero, an error will
kadonotakashi	0:8fdf9a60065b	197	* be generated. Note that this address (0xBASE_0624) is used as SCR1L only if
kadonotakashi	0:8fdf9a60065b	198	* MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback
kadonotakashi	0:8fdf9a60065b	199	* register.
kadonotakashi	0:8fdf9a60065b	200	*/
kadonotakashi	0:8fdf9a60065b	201	/*!
kadonotakashi	0:8fdf9a60065b	202	* @name Constants and macros for entire TRNG_SCR1L register
kadonotakashi	0:8fdf9a60065b	203	*/
kadonotakashi	0:8fdf9a60065b	204	/@{/
kadonotakashi	0:8fdf9a60065b	205	#define TRNG_SCR1L_REG(base) ((base)->SCR1L)
kadonotakashi	0:8fdf9a60065b	206	#define TRNG_RD_SCR1L(base) (TRNG_SCR1L_REG(base))
kadonotakashi	0:8fdf9a60065b	207	#define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	208	#define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	209	/@}/
kadonotakashi	0:8fdf9a60065b	210
kadonotakashi	0:8fdf9a60065b	211	/*!
kadonotakashi	0:8fdf9a60065b	212	* @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW)
kadonotakashi	0:8fdf9a60065b	213	*
kadonotakashi	0:8fdf9a60065b	214	* Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1
kadonotakashi	0:8fdf9a60065b	215	* (for both 0 and 1) detected during entropy generation. The number of runs of
kadonotakashi	0:8fdf9a60065b	216	* length 1 detected during entropy generation must be less than RUN1_MAX, else a
kadonotakashi	0:8fdf9a60065b	217	* retry or error will occur. This register is cleared to 01E5h (decimal 485) by
kadonotakashi	0:8fdf9a60065b	218	* writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	219	*/
kadonotakashi	0:8fdf9a60065b	220	/@{/
kadonotakashi	0:8fdf9a60065b	221	/! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. /
kadonotakashi	0:8fdf9a60065b	222	#define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT)
kadonotakashi	0:8fdf9a60065b	223
kadonotakashi	0:8fdf9a60065b	224	/! @brief Set the RUN1_MAX field to a new value. /
kadonotakashi	0:8fdf9a60065b	225	#define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value)))
kadonotakashi	0:8fdf9a60065b	226	/@}/
kadonotakashi	0:8fdf9a60065b	227
kadonotakashi	0:8fdf9a60065b	228	/*!
kadonotakashi	0:8fdf9a60065b	229	* @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW)
kadonotakashi	0:8fdf9a60065b	230	*
kadonotakashi	0:8fdf9a60065b	231	* Run Length 1 Range. The number of runs of length 1 (for both 0 and 1)
kadonotakashi	0:8fdf9a60065b	232	* detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a
kadonotakashi	0:8fdf9a60065b	233	* retry or error will occur. This register is cleared to 0102h (decimal 258) by
kadonotakashi	0:8fdf9a60065b	234	* writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	235	*/
kadonotakashi	0:8fdf9a60065b	236	/@{/
kadonotakashi	0:8fdf9a60065b	237	/! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. /
kadonotakashi	0:8fdf9a60065b	238	#define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT)
kadonotakashi	0:8fdf9a60065b	239
kadonotakashi	0:8fdf9a60065b	240	/! @brief Set the RUN1_RNG field to a new value. /
kadonotakashi	0:8fdf9a60065b	241	#define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value)))
kadonotakashi	0:8fdf9a60065b	242	/@}/
kadonotakashi	0:8fdf9a60065b	243
kadonotakashi	0:8fdf9a60065b	244	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	245	* TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register
kadonotakashi	0:8fdf9a60065b	246	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	247
kadonotakashi	0:8fdf9a60065b	248	/*!
kadonotakashi	0:8fdf9a60065b	249	* @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW)
kadonotakashi	0:8fdf9a60065b	250	*
kadonotakashi	0:8fdf9a60065b	251	* Reset value: 0x007A00DCU
kadonotakashi	0:8fdf9a60065b	252	*
kadonotakashi	0:8fdf9a60065b	253	* The RNG Statistical Check Run Length 2 Limit Register defines the allowable
kadonotakashi	0:8fdf9a60065b	254	* maximum and minimum number of runs of length 2 detected during entropy
kadonotakashi	0:8fdf9a60065b	255	* generation. To pass the test, the number of runs of length 2 (for samples of both 0
kadonotakashi	0:8fdf9a60065b	256	* and 1) must be less than the programmed maximum value, and the number of runs of
kadonotakashi	0:8fdf9a60065b	257	* length 2 must be greater than (maximum - range). If this test fails, the
kadonotakashi	0:8fdf9a60065b	258	* Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
kadonotakashi	0:8fdf9a60065b	259	* Count has not reached zero. If the Retry Count has reached zero, an error will
kadonotakashi	0:8fdf9a60065b	260	* be generated. Note that this address (0xBASE_0628) is used as SCR2L only if
kadonotakashi	0:8fdf9a60065b	261	* MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback
kadonotakashi	0:8fdf9a60065b	262	* register.
kadonotakashi	0:8fdf9a60065b	263	*/
kadonotakashi	0:8fdf9a60065b	264	/*!
kadonotakashi	0:8fdf9a60065b	265	* @name Constants and macros for entire TRNG_SCR2L register
kadonotakashi	0:8fdf9a60065b	266	*/
kadonotakashi	0:8fdf9a60065b	267	/@{/
kadonotakashi	0:8fdf9a60065b	268	#define TRNG_SCR2L_REG(base) ((base)->SCR2L)
kadonotakashi	0:8fdf9a60065b	269	#define TRNG_RD_SCR2L(base) (TRNG_SCR2L_REG(base))
kadonotakashi	0:8fdf9a60065b	270	#define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	271	#define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	272	/@}/
kadonotakashi	0:8fdf9a60065b	273
kadonotakashi	0:8fdf9a60065b	274	/*
kadonotakashi	0:8fdf9a60065b	275	* Constants & macros for individual TRNG_SCR2L bitfields
kadonotakashi	0:8fdf9a60065b	276	*/
kadonotakashi	0:8fdf9a60065b	277
kadonotakashi	0:8fdf9a60065b	278	/*!
kadonotakashi	0:8fdf9a60065b	279	* @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW)
kadonotakashi	0:8fdf9a60065b	280	*
kadonotakashi	0:8fdf9a60065b	281	* Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2
kadonotakashi	0:8fdf9a60065b	282	* (for both 0 and 1) detected during entropy generation. The number of runs of
kadonotakashi	0:8fdf9a60065b	283	* length 2 detected during entropy generation must be less than RUN2_MAX, else a
kadonotakashi	0:8fdf9a60065b	284	* retry or error will occur. This register is cleared to 00DCh (decimal 220) by
kadonotakashi	0:8fdf9a60065b	285	* writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	286	*/
kadonotakashi	0:8fdf9a60065b	287	/@{/
kadonotakashi	0:8fdf9a60065b	288	/! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. /
kadonotakashi	0:8fdf9a60065b	289	#define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT)
kadonotakashi	0:8fdf9a60065b	290
kadonotakashi	0:8fdf9a60065b	291	/! @brief Set the RUN2_MAX field to a new value. /
kadonotakashi	0:8fdf9a60065b	292	#define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value)))
kadonotakashi	0:8fdf9a60065b	293	/@}/
kadonotakashi	0:8fdf9a60065b	294
kadonotakashi	0:8fdf9a60065b	295	/*!
kadonotakashi	0:8fdf9a60065b	296	* @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW)
kadonotakashi	0:8fdf9a60065b	297	*
kadonotakashi	0:8fdf9a60065b	298	* Run Length 2 Range. The number of runs of length 2 (for both 0 and 1)
kadonotakashi	0:8fdf9a60065b	299	* detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a
kadonotakashi	0:8fdf9a60065b	300	* retry or error will occur. This register is cleared to 007Ah (decimal 122) by
kadonotakashi	0:8fdf9a60065b	301	* writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	302	*/
kadonotakashi	0:8fdf9a60065b	303	/@{/
kadonotakashi	0:8fdf9a60065b	304	/! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. /
kadonotakashi	0:8fdf9a60065b	305	#define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT)
kadonotakashi	0:8fdf9a60065b	306
kadonotakashi	0:8fdf9a60065b	307	/! @brief Set the RUN2_RNG field to a new value. /
kadonotakashi	0:8fdf9a60065b	308	#define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value)))
kadonotakashi	0:8fdf9a60065b	309	/@}/
kadonotakashi	0:8fdf9a60065b	310
kadonotakashi	0:8fdf9a60065b	311	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	312	* TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register
kadonotakashi	0:8fdf9a60065b	313	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	314
kadonotakashi	0:8fdf9a60065b	315	/*!
kadonotakashi	0:8fdf9a60065b	316	* @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW)
kadonotakashi	0:8fdf9a60065b	317	*
kadonotakashi	0:8fdf9a60065b	318	* Reset value: 0x0058007DU
kadonotakashi	0:8fdf9a60065b	319	*
kadonotakashi	0:8fdf9a60065b	320	* The RNG Statistical Check Run Length 3 Limit Register defines the allowable
kadonotakashi	0:8fdf9a60065b	321	* maximum and minimum number of runs of length 3 detected during entropy
kadonotakashi	0:8fdf9a60065b	322	* generation. To pass the test, the number of runs of length 3 (for samples of both 0
kadonotakashi	0:8fdf9a60065b	323	* and 1) must be less than the programmed maximum value, and the number of runs of
kadonotakashi	0:8fdf9a60065b	324	* length 3 must be greater than (maximum - range). If this test fails, the
kadonotakashi	0:8fdf9a60065b	325	* Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
kadonotakashi	0:8fdf9a60065b	326	* Count has not reached zero. If the Retry Count has reached zero, an error will
kadonotakashi	0:8fdf9a60065b	327	* be generated. Note that this address (0xBASE_062C) is used as SCR3L only if
kadonotakashi	0:8fdf9a60065b	328	* MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback
kadonotakashi	0:8fdf9a60065b	329	* register.
kadonotakashi	0:8fdf9a60065b	330	*/
kadonotakashi	0:8fdf9a60065b	331	/*!
kadonotakashi	0:8fdf9a60065b	332	* @name Constants and macros for entire TRNG_SCR3L register
kadonotakashi	0:8fdf9a60065b	333	*/
kadonotakashi	0:8fdf9a60065b	334	/@{/
kadonotakashi	0:8fdf9a60065b	335	#define TRNG_SCR3L_REG(base) ((base)->SCR3L)
kadonotakashi	0:8fdf9a60065b	336	#define TRNG_RD_SCR3L(base) (TRNG_SCR3L_REG(base))
kadonotakashi	0:8fdf9a60065b	337	#define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	338	#define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	339	/@}/
kadonotakashi	0:8fdf9a60065b	340
kadonotakashi	0:8fdf9a60065b	341	/*
kadonotakashi	0:8fdf9a60065b	342	* Constants & macros for individual TRNG_SCR3L bitfields
kadonotakashi	0:8fdf9a60065b	343	*/
kadonotakashi	0:8fdf9a60065b	344
kadonotakashi	0:8fdf9a60065b	345	/*!
kadonotakashi	0:8fdf9a60065b	346	* @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW)
kadonotakashi	0:8fdf9a60065b	347	*
kadonotakashi	0:8fdf9a60065b	348	* Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3
kadonotakashi	0:8fdf9a60065b	349	* (for both 0 and 1) detected during entropy generation. The number of runs of
kadonotakashi	0:8fdf9a60065b	350	* length 3 detected during entropy generation must be less than RUN3_MAX, else a
kadonotakashi	0:8fdf9a60065b	351	* retry or error will occur. This register is cleared to 007Dh (decimal 125) by
kadonotakashi	0:8fdf9a60065b	352	* writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	353	*/
kadonotakashi	0:8fdf9a60065b	354	/@{/
kadonotakashi	0:8fdf9a60065b	355	/! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. /
kadonotakashi	0:8fdf9a60065b	356	#define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT)
kadonotakashi	0:8fdf9a60065b	357
kadonotakashi	0:8fdf9a60065b	358	/! @brief Set the RUN3_MAX field to a new value. /
kadonotakashi	0:8fdf9a60065b	359	#define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value)))
kadonotakashi	0:8fdf9a60065b	360	/@}/
kadonotakashi	0:8fdf9a60065b	361
kadonotakashi	0:8fdf9a60065b	362	/*!
kadonotakashi	0:8fdf9a60065b	363	* @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW)
kadonotakashi	0:8fdf9a60065b	364	*
kadonotakashi	0:8fdf9a60065b	365	* Run Length 3 Range. The number of runs of length 3 (for both 0 and 1)
kadonotakashi	0:8fdf9a60065b	366	* detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a
kadonotakashi	0:8fdf9a60065b	367	* retry or error will occur. This register is cleared to 0058h (decimal 88) by
kadonotakashi	0:8fdf9a60065b	368	* writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	369	*/
kadonotakashi	0:8fdf9a60065b	370	/@{/
kadonotakashi	0:8fdf9a60065b	371	/! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. /
kadonotakashi	0:8fdf9a60065b	372	#define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT)
kadonotakashi	0:8fdf9a60065b	373
kadonotakashi	0:8fdf9a60065b	374	/! @brief Set the RUN3_RNG field to a new value. /
kadonotakashi	0:8fdf9a60065b	375	#define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value)))
kadonotakashi	0:8fdf9a60065b	376	/@}/
kadonotakashi	0:8fdf9a60065b	377
kadonotakashi	0:8fdf9a60065b	378	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	379	* TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register
kadonotakashi	0:8fdf9a60065b	380	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	381
kadonotakashi	0:8fdf9a60065b	382	/*!
kadonotakashi	0:8fdf9a60065b	383	* @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW)
kadonotakashi	0:8fdf9a60065b	384	*
kadonotakashi	0:8fdf9a60065b	385	* Reset value: 0x0040004BU
kadonotakashi	0:8fdf9a60065b	386	*
kadonotakashi	0:8fdf9a60065b	387	* The RNG Statistical Check Run Length 4 Limit Register defines the allowable
kadonotakashi	0:8fdf9a60065b	388	* maximum and minimum number of runs of length 4 detected during entropy
kadonotakashi	0:8fdf9a60065b	389	* generation. To pass the test, the number of runs of length 4 (for samples of both 0
kadonotakashi	0:8fdf9a60065b	390	* and 1) must be less than the programmed maximum value, and the number of runs of
kadonotakashi	0:8fdf9a60065b	391	* length 4 must be greater than (maximum - range). If this test fails, the
kadonotakashi	0:8fdf9a60065b	392	* Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
kadonotakashi	0:8fdf9a60065b	393	* Count has not reached zero. If the Retry Count has reached zero, an error will
kadonotakashi	0:8fdf9a60065b	394	* be generated. Note that this address (0xBASE_0630) is used as SCR4L only if
kadonotakashi	0:8fdf9a60065b	395	* MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback
kadonotakashi	0:8fdf9a60065b	396	* register.
kadonotakashi	0:8fdf9a60065b	397	*/
kadonotakashi	0:8fdf9a60065b	398	/*!
kadonotakashi	0:8fdf9a60065b	399	* @name Constants and macros for entire TRNG_SCR4L register
kadonotakashi	0:8fdf9a60065b	400	*/
kadonotakashi	0:8fdf9a60065b	401	/@{/
kadonotakashi	0:8fdf9a60065b	402	#define TRNG_SCR4L_REG(base) ((base)->SCR4L)
kadonotakashi	0:8fdf9a60065b	403	#define TRNG_RD_SCR4L(base) (TRNG_SCR4L_REG(base))
kadonotakashi	0:8fdf9a60065b	404	#define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	405	#define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	406	/@}/
kadonotakashi	0:8fdf9a60065b	407
kadonotakashi	0:8fdf9a60065b	408	/*
kadonotakashi	0:8fdf9a60065b	409	* Constants & macros for individual TRNG_SCR4L bitfields
kadonotakashi	0:8fdf9a60065b	410	*/
kadonotakashi	0:8fdf9a60065b	411
kadonotakashi	0:8fdf9a60065b	412	/*!
kadonotakashi	0:8fdf9a60065b	413	* @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW)
kadonotakashi	0:8fdf9a60065b	414	*
kadonotakashi	0:8fdf9a60065b	415	* Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4
kadonotakashi	0:8fdf9a60065b	416	* (for both 0 and 1) detected during entropy generation. The number of runs of
kadonotakashi	0:8fdf9a60065b	417	* length 4 detected during entropy generation must be less than RUN4_MAX, else a
kadonotakashi	0:8fdf9a60065b	418	* retry or error will occur. This register is cleared to 004Bh (decimal 75) by
kadonotakashi	0:8fdf9a60065b	419	* writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	420	*/
kadonotakashi	0:8fdf9a60065b	421	/@{/
kadonotakashi	0:8fdf9a60065b	422	/! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. /
kadonotakashi	0:8fdf9a60065b	423	#define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT)
kadonotakashi	0:8fdf9a60065b	424
kadonotakashi	0:8fdf9a60065b	425	/! @brief Set the RUN4_MAX field to a new value. /
kadonotakashi	0:8fdf9a60065b	426	#define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value)))
kadonotakashi	0:8fdf9a60065b	427	/@}/
kadonotakashi	0:8fdf9a60065b	428
kadonotakashi	0:8fdf9a60065b	429	/*!
kadonotakashi	0:8fdf9a60065b	430	* @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW)
kadonotakashi	0:8fdf9a60065b	431	*
kadonotakashi	0:8fdf9a60065b	432	* Run Length 4 Range. The number of runs of length 4 (for both 0 and 1)
kadonotakashi	0:8fdf9a60065b	433	* detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a
kadonotakashi	0:8fdf9a60065b	434	* retry or error will occur. This register is cleared to 0040h (decimal 64) by
kadonotakashi	0:8fdf9a60065b	435	* writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	436	*/
kadonotakashi	0:8fdf9a60065b	437	/@{/
kadonotakashi	0:8fdf9a60065b	438	/! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. /
kadonotakashi	0:8fdf9a60065b	439	#define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT)
kadonotakashi	0:8fdf9a60065b	440
kadonotakashi	0:8fdf9a60065b	441	/! @brief Set the RUN4_RNG field to a new value. /
kadonotakashi	0:8fdf9a60065b	442	#define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value)))
kadonotakashi	0:8fdf9a60065b	443	/@}/
kadonotakashi	0:8fdf9a60065b	444
kadonotakashi	0:8fdf9a60065b	445	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	446	* TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register
kadonotakashi	0:8fdf9a60065b	447	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	448
kadonotakashi	0:8fdf9a60065b	449	/*!
kadonotakashi	0:8fdf9a60065b	450	* @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW)
kadonotakashi	0:8fdf9a60065b	451	*
kadonotakashi	0:8fdf9a60065b	452	* Reset value: 0x002E002FU
kadonotakashi	0:8fdf9a60065b	453	*
kadonotakashi	0:8fdf9a60065b	454	* The RNG Statistical Check Run Length 5 Limit Register defines the allowable
kadonotakashi	0:8fdf9a60065b	455	* maximum and minimum number of runs of length 5 detected during entropy
kadonotakashi	0:8fdf9a60065b	456	* generation. To pass the test, the number of runs of length 5 (for samples of both 0
kadonotakashi	0:8fdf9a60065b	457	* and 1) must be less than the programmed maximum value, and the number of runs of
kadonotakashi	0:8fdf9a60065b	458	* length 5 must be greater than (maximum - range). If this test fails, the
kadonotakashi	0:8fdf9a60065b	459	* Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
kadonotakashi	0:8fdf9a60065b	460	* Count has not reached zero. If the Retry Count has reached zero, an error will
kadonotakashi	0:8fdf9a60065b	461	* be generated. Note that this address (0xBASE_0634) is used as SCR5L only if
kadonotakashi	0:8fdf9a60065b	462	* MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback
kadonotakashi	0:8fdf9a60065b	463	* register.
kadonotakashi	0:8fdf9a60065b	464	*/
kadonotakashi	0:8fdf9a60065b	465	/*!
kadonotakashi	0:8fdf9a60065b	466	* @name Constants and macros for entire TRNG_SCR5L register
kadonotakashi	0:8fdf9a60065b	467	*/
kadonotakashi	0:8fdf9a60065b	468	/@{/
kadonotakashi	0:8fdf9a60065b	469	#define TRNG_SCR5L_REG(base) ((base)->SCR5L)
kadonotakashi	0:8fdf9a60065b	470	#define TRNG_RD_SCR5L(base) (TRNG_SCR5L_REG(base))
kadonotakashi	0:8fdf9a60065b	471	#define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	472	#define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	473	/@}/
kadonotakashi	0:8fdf9a60065b	474
kadonotakashi	0:8fdf9a60065b	475	/*
kadonotakashi	0:8fdf9a60065b	476	* Constants & macros for individual TRNG_SCR5L bitfields
kadonotakashi	0:8fdf9a60065b	477	*/
kadonotakashi	0:8fdf9a60065b	478
kadonotakashi	0:8fdf9a60065b	479	/*!
kadonotakashi	0:8fdf9a60065b	480	* @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW)
kadonotakashi	0:8fdf9a60065b	481	*
kadonotakashi	0:8fdf9a60065b	482	* Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5
kadonotakashi	0:8fdf9a60065b	483	* (for both 0 and 1) detected during entropy generation. The number of runs of
kadonotakashi	0:8fdf9a60065b	484	* length 5 detected during entropy generation must be less than RUN5_MAX, else a
kadonotakashi	0:8fdf9a60065b	485	* retry or error will occur. This register is cleared to 002Fh (decimal 47) by
kadonotakashi	0:8fdf9a60065b	486	* writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	487	*/
kadonotakashi	0:8fdf9a60065b	488	/@{/
kadonotakashi	0:8fdf9a60065b	489	/! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. /
kadonotakashi	0:8fdf9a60065b	490	#define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT)
kadonotakashi	0:8fdf9a60065b	491
kadonotakashi	0:8fdf9a60065b	492	/! @brief Set the RUN5_MAX field to a new value. /
kadonotakashi	0:8fdf9a60065b	493	#define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value)))
kadonotakashi	0:8fdf9a60065b	494	/@}/
kadonotakashi	0:8fdf9a60065b	495
kadonotakashi	0:8fdf9a60065b	496	/*!
kadonotakashi	0:8fdf9a60065b	497	* @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW)
kadonotakashi	0:8fdf9a60065b	498	*
kadonotakashi	0:8fdf9a60065b	499	* Run Length 5 Range. The number of runs of length 5 (for both 0 and 1)
kadonotakashi	0:8fdf9a60065b	500	* detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a
kadonotakashi	0:8fdf9a60065b	501	* retry or error will occur. This register is cleared to 002Eh (decimal 46) by
kadonotakashi	0:8fdf9a60065b	502	* writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	503	*/
kadonotakashi	0:8fdf9a60065b	504	/@{/
kadonotakashi	0:8fdf9a60065b	505	/! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. /
kadonotakashi	0:8fdf9a60065b	506	#define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT)
kadonotakashi	0:8fdf9a60065b	507
kadonotakashi	0:8fdf9a60065b	508	/! @brief Set the RUN5_RNG field to a new value. /
kadonotakashi	0:8fdf9a60065b	509	#define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value)))
kadonotakashi	0:8fdf9a60065b	510	/@}/
kadonotakashi	0:8fdf9a60065b	511
kadonotakashi	0:8fdf9a60065b	512	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	513	* TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register
kadonotakashi	0:8fdf9a60065b	514	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	515
kadonotakashi	0:8fdf9a60065b	516	/*!
kadonotakashi	0:8fdf9a60065b	517	* @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW)
kadonotakashi	0:8fdf9a60065b	518	*
kadonotakashi	0:8fdf9a60065b	519	* Reset value: 0x002E002FU
kadonotakashi	0:8fdf9a60065b	520	*
kadonotakashi	0:8fdf9a60065b	521	* The RNG Statistical Check Run Length 6+ Limit Register defines the allowable
kadonotakashi	0:8fdf9a60065b	522	* maximum and minimum number of runs of length 6 or more detected during entropy
kadonotakashi	0:8fdf9a60065b	523	* generation. To pass the test, the number of runs of length 6 or more (for
kadonotakashi	0:8fdf9a60065b	524	* samples of both 0 and 1) must be less than the programmed maximum value, and the
kadonotakashi	0:8fdf9a60065b	525	* number of runs of length 6 or more must be greater than (maximum - range). If
kadonotakashi	0:8fdf9a60065b	526	* this test fails, the Retry Counter in SCMISC will be decremented, and a retry
kadonotakashi	0:8fdf9a60065b	527	* will occur if the Retry Count has not reached zero. If the Retry Count has
kadonotakashi	0:8fdf9a60065b	528	* reached zero, an error will be generated. Note that this offset (0xBASE_0638) is
kadonotakashi	0:8fdf9a60065b	529	* used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is
kadonotakashi	0:8fdf9a60065b	530	* used as SCR6PC readback register.
kadonotakashi	0:8fdf9a60065b	531	*/
kadonotakashi	0:8fdf9a60065b	532	/*!
kadonotakashi	0:8fdf9a60065b	533	* @name Constants and macros for entire TRNG_SCR6PL register
kadonotakashi	0:8fdf9a60065b	534	*/
kadonotakashi	0:8fdf9a60065b	535	/@{/
kadonotakashi	0:8fdf9a60065b	536	#define TRNG_SCR6PL_REG(base) ((base)->SCR6PL)
kadonotakashi	0:8fdf9a60065b	537	#define TRNG_RD_SCR6PL(base) (TRNG_SCR6PL_REG(base))
kadonotakashi	0:8fdf9a60065b	538	#define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	539	#define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	540	/@}/
kadonotakashi	0:8fdf9a60065b	541
kadonotakashi	0:8fdf9a60065b	542	/*
kadonotakashi	0:8fdf9a60065b	543	* Constants & macros for individual TRNG_SCR6PL bitfields
kadonotakashi	0:8fdf9a60065b	544	*/
kadonotakashi	0:8fdf9a60065b	545
kadonotakashi	0:8fdf9a60065b	546	/*!
kadonotakashi	0:8fdf9a60065b	547	* @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW)
kadonotakashi	0:8fdf9a60065b	548	*
kadonotakashi	0:8fdf9a60065b	549	* Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6
kadonotakashi	0:8fdf9a60065b	550	* or more (for both 0 and 1) detected during entropy generation. The number of
kadonotakashi	0:8fdf9a60065b	551	* runs of length 6 or more detected during entropy generation must be less than
kadonotakashi	0:8fdf9a60065b	552	* RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh
kadonotakashi	0:8fdf9a60065b	553	* (decimal 47) by writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	554	*/
kadonotakashi	0:8fdf9a60065b	555	/@{/
kadonotakashi	0:8fdf9a60065b	556	/! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. /
kadonotakashi	0:8fdf9a60065b	557	#define TRNG_RD_SCR6PL_RUN6P_MAX(base) \
kadonotakashi	0:8fdf9a60065b	558	((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT)
kadonotakashi	0:8fdf9a60065b	559
kadonotakashi	0:8fdf9a60065b	560	/! @brief Set the RUN6P_MAX field to a new value. /
kadonotakashi	0:8fdf9a60065b	561	#define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) \
kadonotakashi	0:8fdf9a60065b	562	(TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value)))
kadonotakashi	0:8fdf9a60065b	563	/@}/
kadonotakashi	0:8fdf9a60065b	564
kadonotakashi	0:8fdf9a60065b	565	/*!
kadonotakashi	0:8fdf9a60065b	566	* @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW)
kadonotakashi	0:8fdf9a60065b	567	*
kadonotakashi	0:8fdf9a60065b	568	* Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and
kadonotakashi	0:8fdf9a60065b	569	* 1) detected during entropy generation must be greater than RUN6P_MAX -
kadonotakashi	0:8fdf9a60065b	570	* RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh
kadonotakashi	0:8fdf9a60065b	571	* (decimal 46) by writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	572	*/
kadonotakashi	0:8fdf9a60065b	573	/@{/
kadonotakashi	0:8fdf9a60065b	574	/! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. /
kadonotakashi	0:8fdf9a60065b	575	#define TRNG_RD_SCR6PL_RUN6P_RNG(base) \
kadonotakashi	0:8fdf9a60065b	576	((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT)
kadonotakashi	0:8fdf9a60065b	577
kadonotakashi	0:8fdf9a60065b	578	/! @brief Set the RUN6P_RNG field to a new value. /
kadonotakashi	0:8fdf9a60065b	579	#define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) \
kadonotakashi	0:8fdf9a60065b	580	(TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value)))
kadonotakashi	0:8fdf9a60065b	581	/@}/
kadonotakashi	0:8fdf9a60065b	582
kadonotakashi	0:8fdf9a60065b	583	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	584	* TRNG_PKRMAX - RNG Poker Maximum Limit Register
kadonotakashi	0:8fdf9a60065b	585	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	586
kadonotakashi	0:8fdf9a60065b	587	/*!
kadonotakashi	0:8fdf9a60065b	588	* @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW)
kadonotakashi	0:8fdf9a60065b	589	*
kadonotakashi	0:8fdf9a60065b	590	* Reset value: 0x00006920U
kadonotakashi	0:8fdf9a60065b	591	*
kadonotakashi	0:8fdf9a60065b	592	* The RNG Poker Maximum Limit Register defines Maximum Limit allowable during
kadonotakashi	0:8fdf9a60065b	593	* the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is
kadonotakashi	0:8fdf9a60065b	594	* used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used
kadonotakashi	0:8fdf9a60065b	595	* as the PKRSQ readback register.
kadonotakashi	0:8fdf9a60065b	596	*/
kadonotakashi	0:8fdf9a60065b	597	/*!
kadonotakashi	0:8fdf9a60065b	598	* @name Constants and macros for entire TRNG_PKRMAX register
kadonotakashi	0:8fdf9a60065b	599	*/
kadonotakashi	0:8fdf9a60065b	600	/@{/
kadonotakashi	0:8fdf9a60065b	601	#define TRNG_PKRMAX_REG(base) ((base)->PKRMAX)
kadonotakashi	0:8fdf9a60065b	602	#define TRNG_RD_PKRMAX(base) (TRNG_PKRMAX_REG(base))
kadonotakashi	0:8fdf9a60065b	603	#define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	604	#define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	605	/@}/
kadonotakashi	0:8fdf9a60065b	606
kadonotakashi	0:8fdf9a60065b	607	/*
kadonotakashi	0:8fdf9a60065b	608	* Constants & macros for individual TRNG_PKRMAX bitfields
kadonotakashi	0:8fdf9a60065b	609	*/
kadonotakashi	0:8fdf9a60065b	610
kadonotakashi	0:8fdf9a60065b	611	/*!
kadonotakashi	0:8fdf9a60065b	612	* @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW)
kadonotakashi	0:8fdf9a60065b	613	*
kadonotakashi	0:8fdf9a60065b	614	* Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is
kadonotakashi	0:8fdf9a60065b	615	* run which requires a maximum and minimum limit. The maximum allowable result is
kadonotakashi	0:8fdf9a60065b	616	* programmed in the PKRMAX[PKR_MAX] register. This field is writable only if
kadonotakashi	0:8fdf9a60065b	617	* MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by
kadonotakashi	0:8fdf9a60065b	618	* writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers
kadonotakashi	0:8fdf9a60065b	619	* combined are used to define the minimum allowable Poker result, which is PKR_MAX -
kadonotakashi	0:8fdf9a60065b	620	* PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used
kadonotakashi	0:8fdf9a60065b	621	* to read the Poker Test Square Calculation result in register PKRSQ, as defined
kadonotakashi	0:8fdf9a60065b	622	* in the following section.
kadonotakashi	0:8fdf9a60065b	623	*/
kadonotakashi	0:8fdf9a60065b	624	/@{/
kadonotakashi	0:8fdf9a60065b	625	/! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. /
kadonotakashi	0:8fdf9a60065b	626	#define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT)
kadonotakashi	0:8fdf9a60065b	627
kadonotakashi	0:8fdf9a60065b	628	/! @brief Set the PKR_MAX field to a new value. /
kadonotakashi	0:8fdf9a60065b	629	#define TRNG_WR_PKRMAX_PKR_MAX(base, value) \
kadonotakashi	0:8fdf9a60065b	630	(TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value)))
kadonotakashi	0:8fdf9a60065b	631	/@}/
kadonotakashi	0:8fdf9a60065b	632
kadonotakashi	0:8fdf9a60065b	633	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	634	* TRNG_PKRRNG - RNG Poker Range Register
kadonotakashi	0:8fdf9a60065b	635	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	636
kadonotakashi	0:8fdf9a60065b	637	/*!
kadonotakashi	0:8fdf9a60065b	638	* @brief TRNG_PKRRNG - RNG Poker Range Register (RW)
kadonotakashi	0:8fdf9a60065b	639	*
kadonotakashi	0:8fdf9a60065b	640	* Reset value: 0x000009A3U
kadonotakashi	0:8fdf9a60065b	641	*
kadonotakashi	0:8fdf9a60065b	642	* The RNG Poker Range Register defines the difference between the TRNG Poker
kadonotakashi	0:8fdf9a60065b	643	* Maximum Limit and the minimum limit. These limits are used during the TRNG
kadonotakashi	0:8fdf9a60065b	644	* Statistical Check Poker Test.
kadonotakashi	0:8fdf9a60065b	645	*/
kadonotakashi	0:8fdf9a60065b	646	/*!
kadonotakashi	0:8fdf9a60065b	647	* @name Constants and macros for entire TRNG_PKRRNG register
kadonotakashi	0:8fdf9a60065b	648	*/
kadonotakashi	0:8fdf9a60065b	649	/@{/
kadonotakashi	0:8fdf9a60065b	650	#define TRNG_PKRRNG_REG(base) ((base)->PKRRNG)
kadonotakashi	0:8fdf9a60065b	651	#define TRNG_RD_PKRRNG(base) (TRNG_PKRRNG_REG(base))
kadonotakashi	0:8fdf9a60065b	652	#define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	653	#define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	654	/@}/
kadonotakashi	0:8fdf9a60065b	655
kadonotakashi	0:8fdf9a60065b	656	/*
kadonotakashi	0:8fdf9a60065b	657	* Constants & macros for individual TRNG_PKRRNG bitfields
kadonotakashi	0:8fdf9a60065b	658	*/
kadonotakashi	0:8fdf9a60065b	659
kadonotakashi	0:8fdf9a60065b	660	/*!
kadonotakashi	0:8fdf9a60065b	661	* @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW)
kadonotakashi	0:8fdf9a60065b	662	*
kadonotakashi	0:8fdf9a60065b	663	* Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which
kadonotakashi	0:8fdf9a60065b	664	* requires a maximum and minimum limit. The maximum is programmed in the
kadonotakashi	0:8fdf9a60065b	665	* RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG
kadonotakashi	0:8fdf9a60065b	666	* value from the programmed maximum value. This field is writable only if
kadonotakashi	0:8fdf9a60065b	667	* MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is
kadonotakashi	0:8fdf9a60065b	668	* cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that
kadonotakashi	0:8fdf9a60065b	669	* the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1.
kadonotakashi	0:8fdf9a60065b	670	*/
kadonotakashi	0:8fdf9a60065b	671	/@{/
kadonotakashi	0:8fdf9a60065b	672	/! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. /
kadonotakashi	0:8fdf9a60065b	673	#define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT)
kadonotakashi	0:8fdf9a60065b	674
kadonotakashi	0:8fdf9a60065b	675	/! @brief Set the PKR_RNG field to a new value. /
kadonotakashi	0:8fdf9a60065b	676	#define TRNG_WR_PKRRNG_PKR_RNG(base, value) \
kadonotakashi	0:8fdf9a60065b	677	(TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value)))
kadonotakashi	0:8fdf9a60065b	678	/@}/
kadonotakashi	0:8fdf9a60065b	679
kadonotakashi	0:8fdf9a60065b	680	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	681	* TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register
kadonotakashi	0:8fdf9a60065b	682	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	683
kadonotakashi	0:8fdf9a60065b	684	/*!
kadonotakashi	0:8fdf9a60065b	685	* @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW)
kadonotakashi	0:8fdf9a60065b	686	*
kadonotakashi	0:8fdf9a60065b	687	* Reset value: 0x00006400U
kadonotakashi	0:8fdf9a60065b	688	*
kadonotakashi	0:8fdf9a60065b	689	* The RNG Frequency Count Maximum Limit Register defines the maximum allowable
kadonotakashi	0:8fdf9a60065b	690	* count taken by the Entropy sample counter during each Entropy sample. During
kadonotakashi	0:8fdf9a60065b	691	* any sample period, if the count is greater than this programmed maximum, a
kadonotakashi	0:8fdf9a60065b	692	* Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note
kadonotakashi	0:8fdf9a60065b	693	* that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If
kadonotakashi	0:8fdf9a60065b	694	* MCTL[PRGM] is 0, this address is used as FRQCNT readback register.
kadonotakashi	0:8fdf9a60065b	695	*/
kadonotakashi	0:8fdf9a60065b	696	/*!
kadonotakashi	0:8fdf9a60065b	697	* @name Constants and macros for entire TRNG_FRQMAX register
kadonotakashi	0:8fdf9a60065b	698	*/
kadonotakashi	0:8fdf9a60065b	699	/@{/
kadonotakashi	0:8fdf9a60065b	700	#define TRNG_FRQMAX_REG(base) ((base)->FRQMAX)
kadonotakashi	0:8fdf9a60065b	701	#define TRNG_RD_FRQMAX(base) (TRNG_FRQMAX_REG(base))
kadonotakashi	0:8fdf9a60065b	702	#define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	703	#define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	704	/@}/
kadonotakashi	0:8fdf9a60065b	705
kadonotakashi	0:8fdf9a60065b	706	/*
kadonotakashi	0:8fdf9a60065b	707	* Constants & macros for individual TRNG_FRQMAX bitfields
kadonotakashi	0:8fdf9a60065b	708	*/
kadonotakashi	0:8fdf9a60065b	709
kadonotakashi	0:8fdf9a60065b	710	/*!
kadonotakashi	0:8fdf9a60065b	711	* @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW)
kadonotakashi	0:8fdf9a60065b	712	*
kadonotakashi	0:8fdf9a60065b	713	* Frequency Counter Maximum Limit. Defines the maximum allowable count taken
kadonotakashi	0:8fdf9a60065b	714	* during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
kadonotakashi	0:8fdf9a60065b	715	* This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	716	* Note that if MCTL[PRGM] bit is 0, this register address is used to read the
kadonotakashi	0:8fdf9a60065b	717	* Frequency Count result in register FRQCNT, as defined in the following section.
kadonotakashi	0:8fdf9a60065b	718	*/
kadonotakashi	0:8fdf9a60065b	719	/@{/
kadonotakashi	0:8fdf9a60065b	720	/! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. /
kadonotakashi	0:8fdf9a60065b	721	#define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT)
kadonotakashi	0:8fdf9a60065b	722
kadonotakashi	0:8fdf9a60065b	723	/! @brief Set the FRQ_MAX field to a new value. /
kadonotakashi	0:8fdf9a60065b	724	#define TRNG_WR_FRQMAX_FRQ_MAX(base, value) \
kadonotakashi	0:8fdf9a60065b	725	(TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value)))
kadonotakashi	0:8fdf9a60065b	726	/@}/
kadonotakashi	0:8fdf9a60065b	727
kadonotakashi	0:8fdf9a60065b	728	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	729	* TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register
kadonotakashi	0:8fdf9a60065b	730	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	731
kadonotakashi	0:8fdf9a60065b	732	/*!
kadonotakashi	0:8fdf9a60065b	733	* @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW)
kadonotakashi	0:8fdf9a60065b	734	*
kadonotakashi	0:8fdf9a60065b	735	* Reset value: 0x00000640U
kadonotakashi	0:8fdf9a60065b	736	*
kadonotakashi	0:8fdf9a60065b	737	* The RNG Frequency Count Minimum Limit Register defines the minimum allowable
kadonotakashi	0:8fdf9a60065b	738	* count taken by the Entropy sample counter during each Entropy sample. During
kadonotakashi	0:8fdf9a60065b	739	* any sample period, if the count is less than this programmed minimum, a
kadonotakashi	0:8fdf9a60065b	740	* Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated.
kadonotakashi	0:8fdf9a60065b	741	*/
kadonotakashi	0:8fdf9a60065b	742	/*!
kadonotakashi	0:8fdf9a60065b	743	* @name Constants and macros for entire TRNG_FRQMIN register
kadonotakashi	0:8fdf9a60065b	744	*/
kadonotakashi	0:8fdf9a60065b	745	/@{/
kadonotakashi	0:8fdf9a60065b	746	#define TRNG_FRQMIN_REG(base) ((base)->FRQMIN)
kadonotakashi	0:8fdf9a60065b	747	#define TRNG_RD_FRQMIN(base) (TRNG_FRQMIN_REG(base))
kadonotakashi	0:8fdf9a60065b	748	#define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	749	#define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	750	/@}/
kadonotakashi	0:8fdf9a60065b	751
kadonotakashi	0:8fdf9a60065b	752	/*
kadonotakashi	0:8fdf9a60065b	753	* Constants & macros for individual TRNG_FRQMIN bitfields
kadonotakashi	0:8fdf9a60065b	754	*/
kadonotakashi	0:8fdf9a60065b	755
kadonotakashi	0:8fdf9a60065b	756	/*!
kadonotakashi	0:8fdf9a60065b	757	* @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW)
kadonotakashi	0:8fdf9a60065b	758	*
kadonotakashi	0:8fdf9a60065b	759	* Frequency Count Minimum Limit. Defines the minimum allowable count taken
kadonotakashi	0:8fdf9a60065b	760	* during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
kadonotakashi	0:8fdf9a60065b	761	* This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64
kadonotakashi	0:8fdf9a60065b	762	* by writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	763	*/
kadonotakashi	0:8fdf9a60065b	764	/@{/
kadonotakashi	0:8fdf9a60065b	765	/! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. /
kadonotakashi	0:8fdf9a60065b	766	#define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT)
kadonotakashi	0:8fdf9a60065b	767
kadonotakashi	0:8fdf9a60065b	768	/! @brief Set the FRQ_MIN field to a new value. /
kadonotakashi	0:8fdf9a60065b	769	#define TRNG_WR_FRQMIN_FRQ_MIN(base, value) \
kadonotakashi	0:8fdf9a60065b	770	(TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value)))
kadonotakashi	0:8fdf9a60065b	771	/@}/
kadonotakashi	0:8fdf9a60065b	772
kadonotakashi	0:8fdf9a60065b	773	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	774	* TRNG_MCTL - RNG Miscellaneous Control Register
kadonotakashi	0:8fdf9a60065b	775	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	776
kadonotakashi	0:8fdf9a60065b	777	/*!
kadonotakashi	0:8fdf9a60065b	778	* @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW)
kadonotakashi	0:8fdf9a60065b	779	*
kadonotakashi	0:8fdf9a60065b	780	* Reset value: 0x00012001U
kadonotakashi	0:8fdf9a60065b	781	*
kadonotakashi	0:8fdf9a60065b	782	* This register is intended to be used for programming, configuring and testing
kadonotakashi	0:8fdf9a60065b	783	* the RNG. It is the main register to read/write, in order to enable Entropy
kadonotakashi	0:8fdf9a60065b	784	* generation, to stop entropy generation and to block access to entropy registers.
kadonotakashi	0:8fdf9a60065b	785	* This is done via the special TRNG_ACC and PRGM bits below. The RNG
kadonotakashi	0:8fdf9a60065b	786	* Miscellaneous Control Register is a read/write register used to control the RNG's True
kadonotakashi	0:8fdf9a60065b	787	* Random Number Generator (TRNG) access, operation and test. Note that in many
kadonotakashi	0:8fdf9a60065b	788	* cases two RNG registers share the same address, and a particular register at the
kadonotakashi	0:8fdf9a60065b	789	* shared address is selected based upon the value in the PRGM field of the MCTL
kadonotakashi	0:8fdf9a60065b	790	* register.
kadonotakashi	0:8fdf9a60065b	791	*/
kadonotakashi	0:8fdf9a60065b	792	/*!
kadonotakashi	0:8fdf9a60065b	793	* @name Constants and macros for entire TRNG_MCTL register
kadonotakashi	0:8fdf9a60065b	794	*/
kadonotakashi	0:8fdf9a60065b	795	/@{/
kadonotakashi	0:8fdf9a60065b	796	#define TRNG_MCTL_REG(base) ((base)->MCTL)
kadonotakashi	0:8fdf9a60065b	797	#define TRNG_RD_MCTL(base) (TRNG_MCTL_REG(base))
kadonotakashi	0:8fdf9a60065b	798	#define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	799	#define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	800	/@}/
kadonotakashi	0:8fdf9a60065b	801
kadonotakashi	0:8fdf9a60065b	802	/*!
kadonotakashi	0:8fdf9a60065b	803	* @name Register TRNG_MCTL, field FOR_SCLK[7] (RW)
kadonotakashi	0:8fdf9a60065b	804	*
kadonotakashi	0:8fdf9a60065b	805	* Force System Clock. If set, the system clock is used to operate the TRNG,
kadonotakashi	0:8fdf9a60065b	806	* instead of the ring oscillator. This is for test use only, and indeterminate
kadonotakashi	0:8fdf9a60065b	807	* results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is
kadonotakashi	0:8fdf9a60065b	808	* being written to 1 simultaneously to writing this bit. This bit is cleared by
kadonotakashi	0:8fdf9a60065b	809	* writing the RST_DEF bit to 1.
kadonotakashi	0:8fdf9a60065b	810	*/
kadonotakashi	0:8fdf9a60065b	811	/@{/
kadonotakashi	0:8fdf9a60065b	812	/! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. /
kadonotakashi	0:8fdf9a60065b	813	#define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT)
kadonotakashi	0:8fdf9a60065b	814
kadonotakashi	0:8fdf9a60065b	815	/! @brief Set the FOR_SCLK field to a new value. /
kadonotakashi	0:8fdf9a60065b	816	#define TRNG_WR_MCTL_FOR_SCLK(base, value) \
kadonotakashi	0:8fdf9a60065b	817	(TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK \| TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value)))
kadonotakashi	0:8fdf9a60065b	818	/@}/
kadonotakashi	0:8fdf9a60065b	819
kadonotakashi	0:8fdf9a60065b	820	/*!
kadonotakashi	0:8fdf9a60065b	821	* @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW)
kadonotakashi	0:8fdf9a60065b	822	*
kadonotakashi	0:8fdf9a60065b	823	* Oscillator Divide. Determines the amount of dividing done to the ring
kadonotakashi	0:8fdf9a60065b	824	* oscillator before it is used by the TRNG.This field is writable only if PRGM bit is
kadonotakashi	0:8fdf9a60065b	825	* 1, or PRGM bit is being written to 1 simultaneously to writing this field. This
kadonotakashi	0:8fdf9a60065b	826	* field is cleared to 00 by writing the RST_DEF bit to 1.
kadonotakashi	0:8fdf9a60065b	827	*
kadonotakashi	0:8fdf9a60065b	828	* Values:
kadonotakashi	0:8fdf9a60065b	829	* - 0b00 - use ring oscillator with no divide
kadonotakashi	0:8fdf9a60065b	830	* - 0b01 - use ring oscillator divided-by-2
kadonotakashi	0:8fdf9a60065b	831	* - 0b10 - use ring oscillator divided-by-4
kadonotakashi	0:8fdf9a60065b	832	* - 0b11 - use ring oscillator divided-by-8
kadonotakashi	0:8fdf9a60065b	833	*/
kadonotakashi	0:8fdf9a60065b	834	/@{/
kadonotakashi	0:8fdf9a60065b	835	/! @brief Read current value of the TRNG_MCTL_OSC_DIV field. /
kadonotakashi	0:8fdf9a60065b	836	#define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT)
kadonotakashi	0:8fdf9a60065b	837
kadonotakashi	0:8fdf9a60065b	838	/! @brief Set the OSC_DIV field to a new value. /
kadonotakashi	0:8fdf9a60065b	839	#define TRNG_WR_MCTL_OSC_DIV(base, value) \
kadonotakashi	0:8fdf9a60065b	840	(TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK \| TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value)))
kadonotakashi	0:8fdf9a60065b	841	/@}/
kadonotakashi	0:8fdf9a60065b	842
kadonotakashi	0:8fdf9a60065b	843	/*!
kadonotakashi	0:8fdf9a60065b	844	* @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW)
kadonotakashi	0:8fdf9a60065b	845	*
kadonotakashi	0:8fdf9a60065b	846	* Sample Mode. Determines the method of sampling the ring oscillator while
kadonotakashi	0:8fdf9a60065b	847	* generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM
kadonotakashi	0:8fdf9a60065b	848	* bit is being written to 1 simultaneously with writing this field. This field
kadonotakashi	0:8fdf9a60065b	849	* is cleared to 01 by writing the RST_DEF bit to 1.
kadonotakashi	0:8fdf9a60065b	850	*
kadonotakashi	0:8fdf9a60065b	851	* Values:
kadonotakashi	0:8fdf9a60065b	852	* - 0b00 - use Von Neumann data into both Entropy shifter and Statistical
kadonotakashi	0:8fdf9a60065b	853	* Checker
kadonotakashi	0:8fdf9a60065b	854	* - 0b01 - use raw data into both Entropy shifter and Statistical Checker
kadonotakashi	0:8fdf9a60065b	855	* - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into
kadonotakashi	0:8fdf9a60065b	856	* Statistical Checker
kadonotakashi	0:8fdf9a60065b	857	* - 0b11 - reserved.
kadonotakashi	0:8fdf9a60065b	858	*/
kadonotakashi	0:8fdf9a60065b	859	/@{/
kadonotakashi	0:8fdf9a60065b	860	/! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. /
kadonotakashi	0:8fdf9a60065b	861	#define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT)
kadonotakashi	0:8fdf9a60065b	862
kadonotakashi	0:8fdf9a60065b	863	/! @brief Set the SAMP_MODE field to a new value. /
kadonotakashi	0:8fdf9a60065b	864	#define TRNG_WR_MCTL_SAMP_MODE(base, value) \
kadonotakashi	0:8fdf9a60065b	865	(TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK \| TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value)))
kadonotakashi	0:8fdf9a60065b	866	/@}/
kadonotakashi	0:8fdf9a60065b	867
kadonotakashi	0:8fdf9a60065b	868	/*!
kadonotakashi	0:8fdf9a60065b	869	* @name Register TRNG_MCTL, field PRGM[16] (RW)
kadonotakashi	0:8fdf9a60065b	870	*
kadonotakashi	0:8fdf9a60065b	871	* Programming Mode Select. When this bit is 1, the TRNG is in Program Mode,
kadonotakashi	0:8fdf9a60065b	872	* otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is
kadonotakashi	0:8fdf9a60065b	873	* in Program Mode. Note that different RNG registers are accessible at the same
kadonotakashi	0:8fdf9a60065b	874	* address depending on whether PRGM is set to 1 or 0. This is noted in the RNG
kadonotakashi	0:8fdf9a60065b	875	* register descriptions.
kadonotakashi	0:8fdf9a60065b	876	*/
kadonotakashi	0:8fdf9a60065b	877	/@{/
kadonotakashi	0:8fdf9a60065b	878	/! @brief Read current value of the TRNG_MCTL_PRGM field. /
kadonotakashi	0:8fdf9a60065b	879	#define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT)
kadonotakashi	0:8fdf9a60065b	880
kadonotakashi	0:8fdf9a60065b	881	/! @brief Set the PRGM field to a new value. /
kadonotakashi	0:8fdf9a60065b	882	#define TRNG_WR_MCTL_PRGM(base, value) \
kadonotakashi	0:8fdf9a60065b	883	(TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK \| TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value)))
kadonotakashi	0:8fdf9a60065b	884	/@}/
kadonotakashi	0:8fdf9a60065b	885
kadonotakashi	0:8fdf9a60065b	886	/*!
kadonotakashi	0:8fdf9a60065b	887	* @name Register TRNG_MCTL, field RST_DEF[6] (WO)
kadonotakashi	0:8fdf9a60065b	888	*
kadonotakashi	0:8fdf9a60065b	889	* Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and
kadonotakashi	0:8fdf9a60065b	890	* bits within registers, to their default state. This bit is writable only if PRGM
kadonotakashi	0:8fdf9a60065b	891	* bit is 1, or PRGM bit is being written to 1 simultaneously to writing this
kadonotakashi	0:8fdf9a60065b	892	* bit. Reading this bit always produces a 0.
kadonotakashi	0:8fdf9a60065b	893	*/
kadonotakashi	0:8fdf9a60065b	894	/@{/
kadonotakashi	0:8fdf9a60065b	895	/! @brief Set the RST_DEF field to a new value. /
kadonotakashi	0:8fdf9a60065b	896	#define TRNG_WR_MCTL_RST_DEF(base, value) \
kadonotakashi	0:8fdf9a60065b	897	(TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK \| TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value)))
kadonotakashi	0:8fdf9a60065b	898	/@}/
kadonotakashi	0:8fdf9a60065b	899
kadonotakashi	0:8fdf9a60065b	900	/*!
kadonotakashi	0:8fdf9a60065b	901	* @name Register TRNG_MCTL, field TRNG_ACC[5] (RW)
kadonotakashi	0:8fdf9a60065b	902	*
kadonotakashi	0:8fdf9a60065b	903	* TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy
kadonotakashi	0:8fdf9a60065b	904	* value that can be read via the ENT0-ENT15 registers. The Entropy value may be
kadonotakashi	0:8fdf9a60065b	905	* read once the ENT VAL bit is asserted. Also see ENTa register descriptions
kadonotakashi	0:8fdf9a60065b	906	* (For a = 0 to 15).
kadonotakashi	0:8fdf9a60065b	907	*/
kadonotakashi	0:8fdf9a60065b	908	/@{/
kadonotakashi	0:8fdf9a60065b	909	/! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. /
kadonotakashi	0:8fdf9a60065b	910	#define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT)
kadonotakashi	0:8fdf9a60065b	911
kadonotakashi	0:8fdf9a60065b	912	/! @brief Set the TRNG_ACC field to a new value. /
kadonotakashi	0:8fdf9a60065b	913	#define TRNG_WR_MCTL_TRNG_ACC(base, value) \
kadonotakashi	0:8fdf9a60065b	914	(TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK \| TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value)))
kadonotakashi	0:8fdf9a60065b	915	/@}/
kadonotakashi	0:8fdf9a60065b	916
kadonotakashi	0:8fdf9a60065b	917	/*!
kadonotakashi	0:8fdf9a60065b	918	* @name Register TRNG_MCTL, field TSTOP_OK[13] (RO)
kadonotakashi	0:8fdf9a60065b	919	*
kadonotakashi	0:8fdf9a60065b	920	* TRNG_OK_TO_STOP. Software should check that this bit is a 1 before
kadonotakashi	0:8fdf9a60065b	921	* transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG
kadonotakashi	0:8fdf9a60065b	922	* free-running ring oscillator whenever new entropy is being generated and turns off the
kadonotakashi	0:8fdf9a60065b	923	* ring oscillator when entropy generation is complete. If the RNG clock is
kadonotakashi	0:8fdf9a60065b	924	* stopped while the TRNG ring oscillator is running, the oscillator will continue
kadonotakashi	0:8fdf9a60065b	925	* running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG
kadonotakashi	0:8fdf9a60065b	926	* ring oscillator is not running. and therefore it is ok to stop the RNG clock.
kadonotakashi	0:8fdf9a60065b	927	*/
kadonotakashi	0:8fdf9a60065b	928	/@{/
kadonotakashi	0:8fdf9a60065b	929	/! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. /
kadonotakashi	0:8fdf9a60065b	930	#define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT)
kadonotakashi	0:8fdf9a60065b	931	/@}/
kadonotakashi	0:8fdf9a60065b	932
kadonotakashi	0:8fdf9a60065b	933	/*!
kadonotakashi	0:8fdf9a60065b	934	* @name Register TRNG_MCTL, field ENT_VAL[10] (RO)
kadonotakashi	0:8fdf9a60065b	935	*
kadonotakashi	0:8fdf9a60065b	936	* Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then
kadonotakashi	0:8fdf9a60065b	937	* after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0
kadonotakashi	0:8fdf9a60065b	938	* through ENT14 should be read before reading ENT15).
kadonotakashi	0:8fdf9a60065b	939	*/
kadonotakashi	0:8fdf9a60065b	940	/@{/
kadonotakashi	0:8fdf9a60065b	941	/! @brief Read current value of the TRNG_MCTL_ENT_VAL field. /
kadonotakashi	0:8fdf9a60065b	942	#define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT)
kadonotakashi	0:8fdf9a60065b	943	/@}/
kadonotakashi	0:8fdf9a60065b	944
kadonotakashi	0:8fdf9a60065b	945	/*!
kadonotakashi	0:8fdf9a60065b	946	* @name Register TRNG_MCTL, field ERR[12] (W1C)
kadonotakashi	0:8fdf9a60065b	947	*
kadonotakashi	0:8fdf9a60065b	948	* Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear
kadonotakashi	0:8fdf9a60065b	949	* errors. Writing 0 has no effect.
kadonotakashi	0:8fdf9a60065b	950	*/
kadonotakashi	0:8fdf9a60065b	951	/@{/
kadonotakashi	0:8fdf9a60065b	952	/! @brief Read current value of the TRNG_MCTL_ERR field. /
kadonotakashi	0:8fdf9a60065b	953	#define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT)
kadonotakashi	0:8fdf9a60065b	954
kadonotakashi	0:8fdf9a60065b	955	/! @brief Set the ERR field to a new value. /
kadonotakashi	0:8fdf9a60065b	956	#define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value)))
kadonotakashi	0:8fdf9a60065b	957	/@}/
kadonotakashi	0:8fdf9a60065b	958
kadonotakashi	0:8fdf9a60065b	959	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	960	* TRNG_SDCTL - RNG Seed Control Register
kadonotakashi	0:8fdf9a60065b	961	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	962
kadonotakashi	0:8fdf9a60065b	963	/*!
kadonotakashi	0:8fdf9a60065b	964	* @brief TRNG_SDCTL - RNG Seed Control Register (RW)
kadonotakashi	0:8fdf9a60065b	965	*
kadonotakashi	0:8fdf9a60065b	966	* Reset value: 0x0C8009C4U
kadonotakashi	0:8fdf9a60065b	967	*
kadonotakashi	0:8fdf9a60065b	968	* The RNG Seed Control Register contains two fields. One field defines the
kadonotakashi	0:8fdf9a60065b	969	* length (in system clocks) of each Entropy sample (ENT_DLY), and the other field
kadonotakashi	0:8fdf9a60065b	970	* indicates the number of samples that will taken during each TRNG Entropy
kadonotakashi	0:8fdf9a60065b	971	* generation (SAMP_SIZE).
kadonotakashi	0:8fdf9a60065b	972	*/
kadonotakashi	0:8fdf9a60065b	973	/*!
kadonotakashi	0:8fdf9a60065b	974	* @name Constants and macros for entire TRNG_SDCTL register
kadonotakashi	0:8fdf9a60065b	975	*/
kadonotakashi	0:8fdf9a60065b	976	/@{/
kadonotakashi	0:8fdf9a60065b	977	#define TRNG_SDCTL_REG(base) ((base)->SDCTL)
kadonotakashi	0:8fdf9a60065b	978	#define TRNG_RD_SDCTL(base) (TRNG_SDCTL_REG(base))
kadonotakashi	0:8fdf9a60065b	979	#define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	980	#define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	981	/@}/
kadonotakashi	0:8fdf9a60065b	982
kadonotakashi	0:8fdf9a60065b	983	/*
kadonotakashi	0:8fdf9a60065b	984	* Constants & macros for individual TRNG_SDCTL bitfields
kadonotakashi	0:8fdf9a60065b	985	*/
kadonotakashi	0:8fdf9a60065b	986
kadonotakashi	0:8fdf9a60065b	987	/*!
kadonotakashi	0:8fdf9a60065b	988	* @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW)
kadonotakashi	0:8fdf9a60065b	989	*
kadonotakashi	0:8fdf9a60065b	990	* Sample Size. Defines the total number of Entropy samples that will be taken
kadonotakashi	0:8fdf9a60065b	991	* during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1.
kadonotakashi	0:8fdf9a60065b	992	* This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h
kadonotakashi	0:8fdf9a60065b	993	* (decimal 2500) by writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	994	*/
kadonotakashi	0:8fdf9a60065b	995	/@{/
kadonotakashi	0:8fdf9a60065b	996	/! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. /
kadonotakashi	0:8fdf9a60065b	997	#define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT)
kadonotakashi	0:8fdf9a60065b	998
kadonotakashi	0:8fdf9a60065b	999	/! @brief Set the SAMP_SIZE field to a new value. /
kadonotakashi	0:8fdf9a60065b	1000	#define TRNG_WR_SDCTL_SAMP_SIZE(base, value) \
kadonotakashi	0:8fdf9a60065b	1001	(TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value)))
kadonotakashi	0:8fdf9a60065b	1002	/@}/
kadonotakashi	0:8fdf9a60065b	1003
kadonotakashi	0:8fdf9a60065b	1004	/*!
kadonotakashi	0:8fdf9a60065b	1005	* @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW)
kadonotakashi	0:8fdf9a60065b	1006	*
kadonotakashi	0:8fdf9a60065b	1007	* Entropy Delay. Defines the length (in system clocks) of each Entropy sample
kadonotakashi	0:8fdf9a60065b	1008	* taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read
kadonotakashi	0:8fdf9a60065b	1009	* zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by
kadonotakashi	0:8fdf9a60065b	1010	* writing the MCTL[RST_DEF] bit to 1.
kadonotakashi	0:8fdf9a60065b	1011	*/
kadonotakashi	0:8fdf9a60065b	1012	/@{/
kadonotakashi	0:8fdf9a60065b	1013	/! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. /
kadonotakashi	0:8fdf9a60065b	1014	#define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT)
kadonotakashi	0:8fdf9a60065b	1015
kadonotakashi	0:8fdf9a60065b	1016	/! @brief Set the ENT_DLY field to a new value. /
kadonotakashi	0:8fdf9a60065b	1017	#define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value)))
kadonotakashi	0:8fdf9a60065b	1018	/@}/
kadonotakashi	0:8fdf9a60065b	1019
kadonotakashi	0:8fdf9a60065b	1020	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	1021	* TRNG_SBLIM - RNG Sparse Bit Limit Register
kadonotakashi	0:8fdf9a60065b	1022	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	1023
kadonotakashi	0:8fdf9a60065b	1024	/*!
kadonotakashi	0:8fdf9a60065b	1025	* @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW)
kadonotakashi	0:8fdf9a60065b	1026	*
kadonotakashi	0:8fdf9a60065b	1027	* Reset value: 0x0000003FU
kadonotakashi	0:8fdf9a60065b	1028	*
kadonotakashi	0:8fdf9a60065b	1029	* The RNG Sparse Bit Limit Register is used when Von Neumann sampling is
kadonotakashi	0:8fdf9a60065b	1030	* selected during Entropy Generation. It defines the maximum number of consecutive Von
kadonotakashi	0:8fdf9a60065b	1031	* Neumann samples which may be discarded before an error is generated. Note
kadonotakashi	0:8fdf9a60065b	1032	* that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If
kadonotakashi	0:8fdf9a60065b	1033	* MCTL[PRGM] is 0, this address is used as TOTSAM readback register.
kadonotakashi	0:8fdf9a60065b	1034	*/
kadonotakashi	0:8fdf9a60065b	1035	/*!
kadonotakashi	0:8fdf9a60065b	1036	* @name Constants and macros for entire TRNG_SBLIM register
kadonotakashi	0:8fdf9a60065b	1037	*/
kadonotakashi	0:8fdf9a60065b	1038	/@{/
kadonotakashi	0:8fdf9a60065b	1039	#define TRNG_SBLIM_REG(base) ((base)->SBLIM)
kadonotakashi	0:8fdf9a60065b	1040	#define TRNG_RD_SBLIM(base) (TRNG_SBLIM_REG(base))
kadonotakashi	0:8fdf9a60065b	1041	#define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	1042	#define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	1043	/@}/
kadonotakashi	0:8fdf9a60065b	1044
kadonotakashi	0:8fdf9a60065b	1045	/*
kadonotakashi	0:8fdf9a60065b	1046	* Constants & macros for individual TRNG_SBLIM bitfields
kadonotakashi	0:8fdf9a60065b	1047	*/
kadonotakashi	0:8fdf9a60065b	1048
kadonotakashi	0:8fdf9a60065b	1049	/*!
kadonotakashi	0:8fdf9a60065b	1050	* @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW)
kadonotakashi	0:8fdf9a60065b	1051	*
kadonotakashi	0:8fdf9a60065b	1052	* Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE],
kadonotakashi	0:8fdf9a60065b	1053	* samples are discarded if two consecutive raw samples are both 0 or both 1. If
kadonotakashi	0:8fdf9a60065b	1054	* this discarding occurs for a long period of time, it indicates that there is
kadonotakashi	0:8fdf9a60065b	1055	* insufficient Entropy. The Sparse Bit Limit defines the maximum number of
kadonotakashi	0:8fdf9a60065b	1056	* consecutive samples that may be discarded before an error is generated. This field
kadonotakashi	0:8fdf9a60065b	1057	* is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by
kadonotakashi	0:8fdf9a60065b	1058	* writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this
kadonotakashi	0:8fdf9a60065b	1059	* register address is used to read the Total Samples count in register TOTSAM, as
kadonotakashi	0:8fdf9a60065b	1060	* defined in the following section.
kadonotakashi	0:8fdf9a60065b	1061	*/
kadonotakashi	0:8fdf9a60065b	1062	/@{/
kadonotakashi	0:8fdf9a60065b	1063	/! @brief Read current value of the TRNG_SBLIM_SB_LIM field. /
kadonotakashi	0:8fdf9a60065b	1064	#define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT)
kadonotakashi	0:8fdf9a60065b	1065
kadonotakashi	0:8fdf9a60065b	1066	/! @brief Set the SB_LIM field to a new value. /
kadonotakashi	0:8fdf9a60065b	1067	#define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value)))
kadonotakashi	0:8fdf9a60065b	1068	/@}/
kadonotakashi	0:8fdf9a60065b	1069
kadonotakashi	0:8fdf9a60065b	1070	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	1071	* TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
kadonotakashi	0:8fdf9a60065b	1072	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	1073
kadonotakashi	0:8fdf9a60065b	1074	/*!
kadonotakashi	0:8fdf9a60065b	1075	* @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW)
kadonotakashi	0:8fdf9a60065b	1076	*
kadonotakashi	0:8fdf9a60065b	1077	* Reset value: 0x0001001FU
kadonotakashi	0:8fdf9a60065b	1078	*
kadonotakashi	0:8fdf9a60065b	1079	* The RNG Statistical Check Miscellaneous Register contains the Long Run
kadonotakashi	0:8fdf9a60065b	1080	* Maximum Limit value and the Retry Count value. This register is accessible only when
kadonotakashi	0:8fdf9a60065b	1081	* the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot
kadonotakashi	0:8fdf9a60065b	1082	* be written.
kadonotakashi	0:8fdf9a60065b	1083	*/
kadonotakashi	0:8fdf9a60065b	1084	/*!
kadonotakashi	0:8fdf9a60065b	1085	* @name Constants and macros for entire TRNG_SCMISC register
kadonotakashi	0:8fdf9a60065b	1086	*/
kadonotakashi	0:8fdf9a60065b	1087	/@{/
kadonotakashi	0:8fdf9a60065b	1088	#define TRNG_SCMISC_REG(base) ((base)->SCMISC)
kadonotakashi	0:8fdf9a60065b	1089	#define TRNG_RD_SCMISC(base) (TRNG_SCMISC_REG(base))
kadonotakashi	0:8fdf9a60065b	1090	#define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	1091	#define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	1092	/@}/
kadonotakashi	0:8fdf9a60065b	1093
kadonotakashi	0:8fdf9a60065b	1094	/*
kadonotakashi	0:8fdf9a60065b	1095	* Constants & macros for individual TRNG_SCMISC bitfields
kadonotakashi	0:8fdf9a60065b	1096	*/
kadonotakashi	0:8fdf9a60065b	1097
kadonotakashi	0:8fdf9a60065b	1098	/*!
kadonotakashi	0:8fdf9a60065b	1099	* @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW)
kadonotakashi	0:8fdf9a60065b	1100	*
kadonotakashi	0:8fdf9a60065b	1101	* LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive
kadonotakashi	0:8fdf9a60065b	1102	* samples of all 1, or all 0, that is allowed during the Entropy generation.
kadonotakashi	0:8fdf9a60065b	1103	* This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes
kadonotakashi	0:8fdf9a60065b	1104	* if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF]
kadonotakashi	0:8fdf9a60065b	1105	* bit to 1.
kadonotakashi	0:8fdf9a60065b	1106	*/
kadonotakashi	0:8fdf9a60065b	1107	/@{/
kadonotakashi	0:8fdf9a60065b	1108	/! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. /
kadonotakashi	0:8fdf9a60065b	1109	#define TRNG_RD_SCMISC_LRUN_MAX(base) \
kadonotakashi	0:8fdf9a60065b	1110	((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT)
kadonotakashi	0:8fdf9a60065b	1111
kadonotakashi	0:8fdf9a60065b	1112	/! @brief Set the LRUN_MAX field to a new value. /
kadonotakashi	0:8fdf9a60065b	1113	#define TRNG_WR_SCMISC_LRUN_MAX(base, value) \
kadonotakashi	0:8fdf9a60065b	1114	(TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value)))
kadonotakashi	0:8fdf9a60065b	1115	/@}/
kadonotakashi	0:8fdf9a60065b	1116
kadonotakashi	0:8fdf9a60065b	1117	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	1118	* TRNG_ENT - RNG TRNG Entropy Read Register
kadonotakashi	0:8fdf9a60065b	1119	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	1120
kadonotakashi	0:8fdf9a60065b	1121	/*!
kadonotakashi	0:8fdf9a60065b	1122	* @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO)
kadonotakashi	0:8fdf9a60065b	1123	*
kadonotakashi	0:8fdf9a60065b	1124	* Reset value: 0x00000000U
kadonotakashi	0:8fdf9a60065b	1125	*
kadonotakashi	0:8fdf9a60065b	1126	* The RNG TRNG can be programmed to generate an entropy value that is readable
kadonotakashi	0:8fdf9a60065b	1127	* via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the
kadonotakashi	0:8fdf9a60065b	1128	* entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this
kadonotakashi	0:8fdf9a60065b	1129	* point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value.
kadonotakashi	0:8fdf9a60065b	1130	* Note that once ENT15 is read, the entropy value will be cleared and a new
kadonotakashi	0:8fdf9a60065b	1131	* value will begin generation, so it is important that ENT15 be read last. These
kadonotakashi	0:8fdf9a60065b	1132	* registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1
kadonotakashi	0:8fdf9a60065b	1133	* (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read.
kadonotakashi	0:8fdf9a60065b	1134	*/
kadonotakashi	0:8fdf9a60065b	1135	/*!
kadonotakashi	0:8fdf9a60065b	1136	* @name Constants and macros for entire TRNG_ENT register
kadonotakashi	0:8fdf9a60065b	1137	*/
kadonotakashi	0:8fdf9a60065b	1138	/@{/
kadonotakashi	0:8fdf9a60065b	1139	#define TRNG_ENT_REG(base, index) ((base)->ENT[index])
kadonotakashi	0:8fdf9a60065b	1140	#define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index))
kadonotakashi	0:8fdf9a60065b	1141	/@}/
kadonotakashi	0:8fdf9a60065b	1142
kadonotakashi	0:8fdf9a60065b	1143	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	1144	* TRNG_SEC_CFG - RNG Security Configuration Register
kadonotakashi	0:8fdf9a60065b	1145	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	1146
kadonotakashi	0:8fdf9a60065b	1147	/*!
kadonotakashi	0:8fdf9a60065b	1148	* @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW)
kadonotakashi	0:8fdf9a60065b	1149	*
kadonotakashi	0:8fdf9a60065b	1150	* Reset value: 0x00000000U
kadonotakashi	0:8fdf9a60065b	1151	*
kadonotakashi	0:8fdf9a60065b	1152	* The RNG Security Configuration Register is a read/write register used to
kadonotakashi	0:8fdf9a60065b	1153	* control the test mode, programmability and state modes of the RNG. Many bits are
kadonotakashi	0:8fdf9a60065b	1154	* place holders for this version. More configurability will be added here. Clears
kadonotakashi	0:8fdf9a60065b	1155	* on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0
kadonotakashi	0:8fdf9a60065b	1156	* to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use
kadonotakashi	0:8fdf9a60065b	1157	* these registers, if hard coded.
kadonotakashi	0:8fdf9a60065b	1158	*/
kadonotakashi	0:8fdf9a60065b	1159	/*!
kadonotakashi	0:8fdf9a60065b	1160	* @name Constants and macros for entire TRNG_SEC_CFG register
kadonotakashi	0:8fdf9a60065b	1161	*/
kadonotakashi	0:8fdf9a60065b	1162	/@{/
kadonotakashi	0:8fdf9a60065b	1163	#define TRNG_SEC_CFG_REG(base) ((base)->SEC_CFG)
kadonotakashi	0:8fdf9a60065b	1164	#define TRNG_RD_SEC_CFG(base) (TRNG_SEC_CFG_REG(base))
kadonotakashi	0:8fdf9a60065b	1165	#define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value))
kadonotakashi	0:8fdf9a60065b	1166	#define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) \| (value)))
kadonotakashi	0:8fdf9a60065b	1167	/@}/
kadonotakashi	0:8fdf9a60065b	1168
kadonotakashi	0:8fdf9a60065b	1169	/*!
kadonotakashi	0:8fdf9a60065b	1170	* @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW)
kadonotakashi	0:8fdf9a60065b	1171	*
kadonotakashi	0:8fdf9a60065b	1172	* If set the TRNG registers cannot be programmed. That is, regardless of the
kadonotakashi	0:8fdf9a60065b	1173	* TRNG access mode in the SA-TRNG Miscellaneous Control Register.
kadonotakashi	0:8fdf9a60065b	1174	*
kadonotakashi	0:8fdf9a60065b	1175	* Values:
kadonotakashi	0:8fdf9a60065b	1176	* - 0b0 - Programability of registers controlled only by the RNG Miscellaneous
kadonotakashi	0:8fdf9a60065b	1177	* Control Register's access mode bit.
kadonotakashi	0:8fdf9a60065b	1178	* - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents
kadonotakashi	0:8fdf9a60065b	1179	* TRNG register programming.
kadonotakashi	0:8fdf9a60065b	1180	*/
kadonotakashi	0:8fdf9a60065b	1181	/@{/
kadonotakashi	0:8fdf9a60065b	1182	/! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. /
kadonotakashi	0:8fdf9a60065b	1183	#define TRNG_RD_SEC_CFG_NO_PRGM(base) \
kadonotakashi	0:8fdf9a60065b	1184	((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT)
kadonotakashi	0:8fdf9a60065b	1185
kadonotakashi	0:8fdf9a60065b	1186	/! @brief Set the NO_PRGM field to a new value. /
kadonotakashi	0:8fdf9a60065b	1187	#define TRNG_WR_SEC_CFG_NO_PRGM(base, value) \
kadonotakashi	0:8fdf9a60065b	1188	(TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value)))
kadonotakashi	0:8fdf9a60065b	1189	/@}/
kadonotakashi	0:8fdf9a60065b	1190
kadonotakashi	0:8fdf9a60065b	1191	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	1192	* Prototypes
kadonotakashi	0:8fdf9a60065b	1193	*******************************************************************************/
kadonotakashi	0:8fdf9a60065b	1194	static status_t trng_ApplyUserConfig(TRNG_Type base, const trng_config_t userConfig);
kadonotakashi	0:8fdf9a60065b	1195	static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count);
kadonotakashi	0:8fdf9a60065b	1196	static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base,
kadonotakashi	0:8fdf9a60065b	1197	trng_statistical_check_t statistical_check,
kadonotakashi	0:8fdf9a60065b	1198	const trng_statistical_check_limit_t *limit);
kadonotakashi	0:8fdf9a60065b	1199	static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index);
kadonotakashi	0:8fdf9a60065b	1200
kadonotakashi	0:8fdf9a60065b	1201	/*******************************************************************************
kadonotakashi	0:8fdf9a60065b	1202	* Code
kadonotakashi	0:8fdf9a60065b	1203	******************************************************************************/
kadonotakashi	0:8fdf9a60065b	1204
kadonotakashi	0:8fdf9a60065b	1205	/FUNCTION********************************************************************
kadonotakashi	0:8fdf9a60065b	1206	*
kadonotakashi	0:8fdf9a60065b	1207	* Function Name : TRNG_InitUserConfigDefault
kadonotakashi	0:8fdf9a60065b	1208	* Description : Initializes user configuration structure to default settings.
kadonotakashi	0:8fdf9a60065b	1209	*
kadonotakashi	0:8fdf9a60065b	1210	END************************************************************************/
kadonotakashi	0:8fdf9a60065b	1211	status_t TRNG_GetDefaultConfig(trng_config_t *userConfig)
kadonotakashi	0:8fdf9a60065b	1212	{
kadonotakashi	0:8fdf9a60065b	1213	status_t result;
kadonotakashi	0:8fdf9a60065b	1214
kadonotakashi	0:8fdf9a60065b	1215	if (userConfig != 0)
kadonotakashi	0:8fdf9a60065b	1216	{
kadonotakashi	0:8fdf9a60065b	1217	userConfig->lock = TRNG_USER_CONFIG_DEFAULT_LOCK;
kadonotakashi	0:8fdf9a60065b	1218	userConfig->clockMode = kTRNG_ClockModeRingOscillator;
kadonotakashi	0:8fdf9a60065b	1219	userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV;
kadonotakashi	0:8fdf9a60065b	1220	userConfig->sampleMode = kTRNG_SampleModeRaw;
kadonotakashi	0:8fdf9a60065b	1221	userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY;
kadonotakashi	0:8fdf9a60065b	1222	userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE;
kadonotakashi	0:8fdf9a60065b	1223	userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT;
kadonotakashi	0:8fdf9a60065b	1224
kadonotakashi	0:8fdf9a60065b	1225	/* Statistical Check Parameters.*/
kadonotakashi	0:8fdf9a60065b	1226	userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT;
kadonotakashi	0:8fdf9a60065b	1227	userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT;
kadonotakashi	0:8fdf9a60065b	1228
kadonotakashi	0:8fdf9a60065b	1229	userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM;
kadonotakashi	0:8fdf9a60065b	1230	userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM;
kadonotakashi	0:8fdf9a60065b	1231	userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM;
kadonotakashi	0:8fdf9a60065b	1232	userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM;
kadonotakashi	0:8fdf9a60065b	1233	userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM;
kadonotakashi	0:8fdf9a60065b	1234	userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM;
kadonotakashi	0:8fdf9a60065b	1235	userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM;
kadonotakashi	0:8fdf9a60065b	1236	userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM;
kadonotakashi	0:8fdf9a60065b	1237	userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM;
kadonotakashi	0:8fdf9a60065b	1238	userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM;
kadonotakashi	0:8fdf9a60065b	1239	userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM;
kadonotakashi	0:8fdf9a60065b	1240	userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM;
kadonotakashi	0:8fdf9a60065b	1241	userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM;
kadonotakashi	0:8fdf9a60065b	1242	userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM;
kadonotakashi	0:8fdf9a60065b	1243	userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM;
kadonotakashi	0:8fdf9a60065b	1244	userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM;
kadonotakashi	0:8fdf9a60065b	1245	userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM;
kadonotakashi	0:8fdf9a60065b	1246	userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM;
kadonotakashi	0:8fdf9a60065b	1247
kadonotakashi	0:8fdf9a60065b	1248	result = kStatus_Success;
kadonotakashi	0:8fdf9a60065b	1249	}
kadonotakashi	0:8fdf9a60065b	1250	else
kadonotakashi	0:8fdf9a60065b	1251	{
kadonotakashi	0:8fdf9a60065b	1252	result = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1253	}
kadonotakashi	0:8fdf9a60065b	1254
kadonotakashi	0:8fdf9a60065b	1255	return result;
kadonotakashi	0:8fdf9a60065b	1256	}
kadonotakashi	0:8fdf9a60065b	1257
kadonotakashi	0:8fdf9a60065b	1258	/*!
kadonotakashi	0:8fdf9a60065b	1259	* @brief Sets the TRNG retry count.
kadonotakashi	0:8fdf9a60065b	1260	*
kadonotakashi	0:8fdf9a60065b	1261	* This function sets the retry counter which defines the number of times a
kadonotakashi	0:8fdf9a60065b	1262	* statistical check may fails during the TRNG Entropy Generation before
kadonotakashi	0:8fdf9a60065b	1263	* generating an error.
kadonotakashi	0:8fdf9a60065b	1264	*/
kadonotakashi	0:8fdf9a60065b	1265	static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count)
kadonotakashi	0:8fdf9a60065b	1266	{
kadonotakashi	0:8fdf9a60065b	1267	status_t status;
kadonotakashi	0:8fdf9a60065b	1268
kadonotakashi	0:8fdf9a60065b	1269	if ((retry_count >= 1u) && (retry_count <= 15u))
kadonotakashi	0:8fdf9a60065b	1270	{
kadonotakashi	0:8fdf9a60065b	1271	/* Set retry count.*/
kadonotakashi	0:8fdf9a60065b	1272	TRNG_WR_SCMISC_RTY_CT(base, retry_count);
kadonotakashi	0:8fdf9a60065b	1273	status = kStatus_Success;
kadonotakashi	0:8fdf9a60065b	1274	}
kadonotakashi	0:8fdf9a60065b	1275	else
kadonotakashi	0:8fdf9a60065b	1276	{
kadonotakashi	0:8fdf9a60065b	1277	status = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1278	}
kadonotakashi	0:8fdf9a60065b	1279	return status;
kadonotakashi	0:8fdf9a60065b	1280	}
kadonotakashi	0:8fdf9a60065b	1281
kadonotakashi	0:8fdf9a60065b	1282	/*!
kadonotakashi	0:8fdf9a60065b	1283	* @brief Sets statistical check limits.
kadonotakashi	0:8fdf9a60065b	1284	*
kadonotakashi	0:8fdf9a60065b	1285	* This function is used to set minimum and maximum limits of statistical checks.
kadonotakashi	0:8fdf9a60065b	1286	*
kadonotakashi	0:8fdf9a60065b	1287	*/
kadonotakashi	0:8fdf9a60065b	1288	static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base,
kadonotakashi	0:8fdf9a60065b	1289	trng_statistical_check_t statistical_check,
kadonotakashi	0:8fdf9a60065b	1290	const trng_statistical_check_limit_t *limit)
kadonotakashi	0:8fdf9a60065b	1291	{
kadonotakashi	0:8fdf9a60065b	1292	uint32_t range;
kadonotakashi	0:8fdf9a60065b	1293	status_t status = kStatus_Success;
kadonotakashi	0:8fdf9a60065b	1294
kadonotakashi	0:8fdf9a60065b	1295	if (limit && (limit->maximum > limit->minimum))
kadonotakashi	0:8fdf9a60065b	1296	{
kadonotakashi	0:8fdf9a60065b	1297	range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/
kadonotakashi	0:8fdf9a60065b	1298
kadonotakashi	0:8fdf9a60065b	1299	switch (statistical_check)
kadonotakashi	0:8fdf9a60065b	1300	{
kadonotakashi	0:8fdf9a60065b	1301	case kTRNG_StatisticalCheckMonobit: /* Allowable maximum and minimum number of ones/zero detected during
kadonotakashi	0:8fdf9a60065b	1302	entropy generation. */
kadonotakashi	0:8fdf9a60065b	1303	if ((range <= 0xffffu) && (limit->maximum <= 0xffffu))
kadonotakashi	0:8fdf9a60065b	1304	{
kadonotakashi	0:8fdf9a60065b	1305	TRNG_WR_SCML_MONO_MAX(base, limit->maximum);
kadonotakashi	0:8fdf9a60065b	1306	TRNG_WR_SCML_MONO_RNG(base, range);
kadonotakashi	0:8fdf9a60065b	1307	}
kadonotakashi	0:8fdf9a60065b	1308	else
kadonotakashi	0:8fdf9a60065b	1309	{
kadonotakashi	0:8fdf9a60065b	1310	status = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1311	}
kadonotakashi	0:8fdf9a60065b	1312	break;
kadonotakashi	0:8fdf9a60065b	1313	case kTRNG_StatisticalCheckRunBit1: /* Allowable maximum and minimum number of runs of length 1 detected
kadonotakashi	0:8fdf9a60065b	1314	during entropy generation. */
kadonotakashi	0:8fdf9a60065b	1315	if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu))
kadonotakashi	0:8fdf9a60065b	1316	{
kadonotakashi	0:8fdf9a60065b	1317	TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum);
kadonotakashi	0:8fdf9a60065b	1318	TRNG_WR_SCR1L_RUN1_RNG(base, range);
kadonotakashi	0:8fdf9a60065b	1319	}
kadonotakashi	0:8fdf9a60065b	1320	else
kadonotakashi	0:8fdf9a60065b	1321	{
kadonotakashi	0:8fdf9a60065b	1322	status = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1323	}
kadonotakashi	0:8fdf9a60065b	1324	break;
kadonotakashi	0:8fdf9a60065b	1325	case kTRNG_StatisticalCheckRunBit2: /* Allowable maximum and minimum number of runs of length 2 detected
kadonotakashi	0:8fdf9a60065b	1326	during entropy generation. */
kadonotakashi	0:8fdf9a60065b	1327	if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu))
kadonotakashi	0:8fdf9a60065b	1328	{
kadonotakashi	0:8fdf9a60065b	1329	TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum);
kadonotakashi	0:8fdf9a60065b	1330	TRNG_WR_SCR2L_RUN2_RNG(base, range);
kadonotakashi	0:8fdf9a60065b	1331	}
kadonotakashi	0:8fdf9a60065b	1332	else
kadonotakashi	0:8fdf9a60065b	1333	{
kadonotakashi	0:8fdf9a60065b	1334	status = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1335	}
kadonotakashi	0:8fdf9a60065b	1336	break;
kadonotakashi	0:8fdf9a60065b	1337	case kTRNG_StatisticalCheckRunBit3: /* Allowable maximum and minimum number of runs of length 3 detected
kadonotakashi	0:8fdf9a60065b	1338	during entropy generation. */
kadonotakashi	0:8fdf9a60065b	1339	if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu))
kadonotakashi	0:8fdf9a60065b	1340	{
kadonotakashi	0:8fdf9a60065b	1341	TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum);
kadonotakashi	0:8fdf9a60065b	1342	TRNG_WR_SCR3L_RUN3_RNG(base, range);
kadonotakashi	0:8fdf9a60065b	1343	}
kadonotakashi	0:8fdf9a60065b	1344	else
kadonotakashi	0:8fdf9a60065b	1345	{
kadonotakashi	0:8fdf9a60065b	1346	status = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1347	}
kadonotakashi	0:8fdf9a60065b	1348	break;
kadonotakashi	0:8fdf9a60065b	1349	case kTRNG_StatisticalCheckRunBit4: /* Allowable maximum and minimum number of runs of length 4 detected
kadonotakashi	0:8fdf9a60065b	1350	during entropy generation. */
kadonotakashi	0:8fdf9a60065b	1351	if ((range <= 0xfffu) && (limit->maximum <= 0xfffu))
kadonotakashi	0:8fdf9a60065b	1352	{
kadonotakashi	0:8fdf9a60065b	1353	TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum);
kadonotakashi	0:8fdf9a60065b	1354	TRNG_WR_SCR4L_RUN4_RNG(base, range);
kadonotakashi	0:8fdf9a60065b	1355	}
kadonotakashi	0:8fdf9a60065b	1356	else
kadonotakashi	0:8fdf9a60065b	1357	{
kadonotakashi	0:8fdf9a60065b	1358	status = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1359	}
kadonotakashi	0:8fdf9a60065b	1360	break;
kadonotakashi	0:8fdf9a60065b	1361	case kTRNG_StatisticalCheckRunBit5: /* Allowable maximum and minimum number of runs of length 5 detected
kadonotakashi	0:8fdf9a60065b	1362	during entropy generation. */
kadonotakashi	0:8fdf9a60065b	1363	if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu))
kadonotakashi	0:8fdf9a60065b	1364	{
kadonotakashi	0:8fdf9a60065b	1365	TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum);
kadonotakashi	0:8fdf9a60065b	1366	TRNG_WR_SCR5L_RUN5_RNG(base, range);
kadonotakashi	0:8fdf9a60065b	1367	}
kadonotakashi	0:8fdf9a60065b	1368	else
kadonotakashi	0:8fdf9a60065b	1369	{
kadonotakashi	0:8fdf9a60065b	1370	status = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1371	}
kadonotakashi	0:8fdf9a60065b	1372	break;
kadonotakashi	0:8fdf9a60065b	1373	case kTRNG_StatisticalCheckRunBit6Plus: /* Allowable maximum and minimum number of length 6 or more detected
kadonotakashi	0:8fdf9a60065b	1374	during entropy generation */
kadonotakashi	0:8fdf9a60065b	1375	if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu))
kadonotakashi	0:8fdf9a60065b	1376	{
kadonotakashi	0:8fdf9a60065b	1377	TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum);
kadonotakashi	0:8fdf9a60065b	1378	TRNG_WR_SCR6PL_RUN6P_RNG(base, range);
kadonotakashi	0:8fdf9a60065b	1379	}
kadonotakashi	0:8fdf9a60065b	1380	else
kadonotakashi	0:8fdf9a60065b	1381	{
kadonotakashi	0:8fdf9a60065b	1382	status = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1383	}
kadonotakashi	0:8fdf9a60065b	1384	break;
kadonotakashi	0:8fdf9a60065b	1385	case kTRNG_StatisticalCheckPoker: /* Allowable maximum and minimum limit of "Poker Test" detected during
kadonotakashi	0:8fdf9a60065b	1386	entropy generation . */
kadonotakashi	0:8fdf9a60065b	1387	if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu))
kadonotakashi	0:8fdf9a60065b	1388	{
kadonotakashi	0:8fdf9a60065b	1389	TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum);
kadonotakashi	0:8fdf9a60065b	1390	TRNG_WR_PKRRNG_PKR_RNG(base, range);
kadonotakashi	0:8fdf9a60065b	1391	}
kadonotakashi	0:8fdf9a60065b	1392	else
kadonotakashi	0:8fdf9a60065b	1393	{
kadonotakashi	0:8fdf9a60065b	1394	status = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1395	}
kadonotakashi	0:8fdf9a60065b	1396	break;
kadonotakashi	0:8fdf9a60065b	1397	case kTRNG_StatisticalCheckFrequencyCount: /* Allowable maximum and minimum limit of entropy sample frquency
kadonotakashi	0:8fdf9a60065b	1398	count during entropy generation . */
kadonotakashi	0:8fdf9a60065b	1399	if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu))
kadonotakashi	0:8fdf9a60065b	1400	{
kadonotakashi	0:8fdf9a60065b	1401	TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum);
kadonotakashi	0:8fdf9a60065b	1402	TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum);
kadonotakashi	0:8fdf9a60065b	1403	}
kadonotakashi	0:8fdf9a60065b	1404	else
kadonotakashi	0:8fdf9a60065b	1405	{
kadonotakashi	0:8fdf9a60065b	1406	status = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1407	}
kadonotakashi	0:8fdf9a60065b	1408	break;
kadonotakashi	0:8fdf9a60065b	1409	default:
kadonotakashi	0:8fdf9a60065b	1410	status = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1411	break;
kadonotakashi	0:8fdf9a60065b	1412	}
kadonotakashi	0:8fdf9a60065b	1413	}
kadonotakashi	0:8fdf9a60065b	1414
kadonotakashi	0:8fdf9a60065b	1415	return status;
kadonotakashi	0:8fdf9a60065b	1416	}
kadonotakashi	0:8fdf9a60065b	1417
kadonotakashi	0:8fdf9a60065b	1418	/FUNCTION********************************************************************
kadonotakashi	0:8fdf9a60065b	1419	*
kadonotakashi	0:8fdf9a60065b	1420	* Function Name : trng_ApplyUserConfig
kadonotakashi	0:8fdf9a60065b	1421	* Description : Apply user configuration settings to TRNG module.
kadonotakashi	0:8fdf9a60065b	1422	*
kadonotakashi	0:8fdf9a60065b	1423	END************************************************************************/
kadonotakashi	0:8fdf9a60065b	1424	static status_t trng_ApplyUserConfig(TRNG_Type base, const trng_config_t userConfig)
kadonotakashi	0:8fdf9a60065b	1425	{
kadonotakashi	0:8fdf9a60065b	1426	status_t status;
kadonotakashi	0:8fdf9a60065b	1427
kadonotakashi	0:8fdf9a60065b	1428	if (((status = trng_SetRetryCount(base, userConfig->retryCount)) == kStatus_Success) &&
kadonotakashi	0:8fdf9a60065b	1429	((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit)) ==
kadonotakashi	0:8fdf9a60065b	1430	kStatus_Success) &&
kadonotakashi	0:8fdf9a60065b	1431	((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit)) ==
kadonotakashi	0:8fdf9a60065b	1432	kStatus_Success) &&
kadonotakashi	0:8fdf9a60065b	1433	((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit)) ==
kadonotakashi	0:8fdf9a60065b	1434	kStatus_Success) &&
kadonotakashi	0:8fdf9a60065b	1435	((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit)) ==
kadonotakashi	0:8fdf9a60065b	1436	kStatus_Success) &&
kadonotakashi	0:8fdf9a60065b	1437	((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit)) ==
kadonotakashi	0:8fdf9a60065b	1438	kStatus_Success) &&
kadonotakashi	0:8fdf9a60065b	1439	((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit)) ==
kadonotakashi	0:8fdf9a60065b	1440	kStatus_Success) &&
kadonotakashi	0:8fdf9a60065b	1441	((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus,
kadonotakashi	0:8fdf9a60065b	1442	&userConfig->runBit6PlusLimit)) == kStatus_Success) &&
kadonotakashi	0:8fdf9a60065b	1443	((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit)) ==
kadonotakashi	0:8fdf9a60065b	1444	kStatus_Success) &&
kadonotakashi	0:8fdf9a60065b	1445	((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount,
kadonotakashi	0:8fdf9a60065b	1446	&userConfig->frequencyCountLimit)) == kStatus_Success))
kadonotakashi	0:8fdf9a60065b	1447	{
kadonotakashi	0:8fdf9a60065b	1448	TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode);
kadonotakashi	0:8fdf9a60065b	1449	TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv);
kadonotakashi	0:8fdf9a60065b	1450	TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode);
kadonotakashi	0:8fdf9a60065b	1451	TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay);
kadonotakashi	0:8fdf9a60065b	1452	TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize);
kadonotakashi	0:8fdf9a60065b	1453	TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit);
kadonotakashi	0:8fdf9a60065b	1454	TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit);
kadonotakashi	0:8fdf9a60065b	1455	}
kadonotakashi	0:8fdf9a60065b	1456
kadonotakashi	0:8fdf9a60065b	1457	return status;
kadonotakashi	0:8fdf9a60065b	1458	}
kadonotakashi	0:8fdf9a60065b	1459
kadonotakashi	0:8fdf9a60065b	1460	/*!
kadonotakashi	0:8fdf9a60065b	1461	* @brief Gets a entry data from the TRNG.
kadonotakashi	0:8fdf9a60065b	1462	*
kadonotakashi	0:8fdf9a60065b	1463	* This function gets an entropy data from TRNG.
kadonotakashi	0:8fdf9a60065b	1464	* Entropy data is spread over TRNG_ENT_COUNT registers.
kadonotakashi	0:8fdf9a60065b	1465	* Read register number is defined by index parameter.
kadonotakashi	0:8fdf9a60065b	1466	*/
kadonotakashi	0:8fdf9a60065b	1467	static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index)
kadonotakashi	0:8fdf9a60065b	1468	{
kadonotakashi	0:8fdf9a60065b	1469	uint32_t data;
kadonotakashi	0:8fdf9a60065b	1470
kadonotakashi	0:8fdf9a60065b	1471	index = index % TRNG_ENT_COUNT; /* This way we can use incremental index without limit control from application.*/
kadonotakashi	0:8fdf9a60065b	1472
kadonotakashi	0:8fdf9a60065b	1473	data = TRNG_RD_ENT(base, index);
kadonotakashi	0:8fdf9a60065b	1474
kadonotakashi	0:8fdf9a60065b	1475	if (index == (TRNG_ENT_COUNT - 1))
kadonotakashi	0:8fdf9a60065b	1476	{
kadonotakashi	0:8fdf9a60065b	1477	/* Dummy read. Defect workaround.
kadonotakashi	0:8fdf9a60065b	1478	* TRNG could not clear ENT_VAL flag automatically, application
kadonotakashi	0:8fdf9a60065b	1479	* had to do a dummy reading operation for anyone TRNG register
kadonotakashi	0:8fdf9a60065b	1480	* to clear it firstly, then to read the RTENT0 to RTENT15 again */
kadonotakashi	0:8fdf9a60065b	1481	index = TRNG_RD_ENT(base, 0);
kadonotakashi	0:8fdf9a60065b	1482	}
kadonotakashi	0:8fdf9a60065b	1483
kadonotakashi	0:8fdf9a60065b	1484	return data;
kadonotakashi	0:8fdf9a60065b	1485	}
kadonotakashi	0:8fdf9a60065b	1486
kadonotakashi	0:8fdf9a60065b	1487	status_t TRNG_Init(TRNG_Type base, const trng_config_t userConfig)
kadonotakashi	0:8fdf9a60065b	1488	{
kadonotakashi	0:8fdf9a60065b	1489	status_t result;
kadonotakashi	0:8fdf9a60065b	1490
kadonotakashi	0:8fdf9a60065b	1491	/* Check input parameters.*/
kadonotakashi	0:8fdf9a60065b	1492	if ((base != 0) && (userConfig != 0))
kadonotakashi	0:8fdf9a60065b	1493	{
kadonotakashi	0:8fdf9a60065b	1494	#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
kadonotakashi	0:8fdf9a60065b	1495	/* Enable the clock gate. */
kadonotakashi	0:8fdf9a60065b	1496	CLOCK_EnableClock(kCLOCK_Trng0);
kadonotakashi	0:8fdf9a60065b	1497	#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
kadonotakashi	0:8fdf9a60065b	1498
kadonotakashi	0:8fdf9a60065b	1499	/* Reset the registers of TRNG module to reset state. */
kadonotakashi	0:8fdf9a60065b	1500	/* Must be in program mode.*/
kadonotakashi	0:8fdf9a60065b	1501	TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram);
kadonotakashi	0:8fdf9a60065b	1502	/* Reset Defaults.*/
kadonotakashi	0:8fdf9a60065b	1503	TRNG_WR_MCTL_RST_DEF(base, 1);
kadonotakashi	0:8fdf9a60065b	1504
kadonotakashi	0:8fdf9a60065b	1505	/* Set configuration.*/
kadonotakashi	0:8fdf9a60065b	1506	if ((result = trng_ApplyUserConfig(base, userConfig)) == kStatus_Success)
kadonotakashi	0:8fdf9a60065b	1507	{
kadonotakashi	0:8fdf9a60065b	1508	/* Start entropy generation.*/
kadonotakashi	0:8fdf9a60065b	1509	/* Set to Run mode.*/
kadonotakashi	0:8fdf9a60065b	1510	TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun);
kadonotakashi	0:8fdf9a60065b	1511	/* Enable TRNG Access Mode. To generate an Entropy
kadonotakashi	0:8fdf9a60065b	1512	* value that can be read via the true0-true15 registers.*/
kadonotakashi	0:8fdf9a60065b	1513	TRNG_WR_MCTL_TRNG_ACC(base, 1);
kadonotakashi	0:8fdf9a60065b	1514
kadonotakashi	0:8fdf9a60065b	1515	if (userConfig->lock == 1) /* Disable programmability of TRNG registers. */
kadonotakashi	0:8fdf9a60065b	1516	{
kadonotakashi	0:8fdf9a60065b	1517	TRNG_WR_SEC_CFG_NO_PRGM(base, 1);
kadonotakashi	0:8fdf9a60065b	1518	}
kadonotakashi	0:8fdf9a60065b	1519
kadonotakashi	0:8fdf9a60065b	1520	result = kStatus_Success;
kadonotakashi	0:8fdf9a60065b	1521	}
kadonotakashi	0:8fdf9a60065b	1522	}
kadonotakashi	0:8fdf9a60065b	1523	else
kadonotakashi	0:8fdf9a60065b	1524	{
kadonotakashi	0:8fdf9a60065b	1525	result = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1526	}
kadonotakashi	0:8fdf9a60065b	1527
kadonotakashi	0:8fdf9a60065b	1528	return result;
kadonotakashi	0:8fdf9a60065b	1529	}
kadonotakashi	0:8fdf9a60065b	1530
kadonotakashi	0:8fdf9a60065b	1531	void TRNG_Deinit(TRNG_Type *base)
kadonotakashi	0:8fdf9a60065b	1532	{
kadonotakashi	0:8fdf9a60065b	1533	/* Check input parameters.*/
kadonotakashi	0:8fdf9a60065b	1534	if (base)
kadonotakashi	0:8fdf9a60065b	1535	{
kadonotakashi	0:8fdf9a60065b	1536	/* Move to program mode. Stop entropy generation.*/
kadonotakashi	0:8fdf9a60065b	1537	TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram);
kadonotakashi	0:8fdf9a60065b	1538
kadonotakashi	0:8fdf9a60065b	1539	/* Check before clock stop.
kadonotakashi	0:8fdf9a60065b	1540	TRNG turns on the TRNG free-running ring oscillator whenever new entropy
kadonotakashi	0:8fdf9a60065b	1541	is being generated and turns off the ring oscillator when entropy generation
kadonotakashi	0:8fdf9a60065b	1542	is complete. If the TRNG clock is stopped while the TRNG ring oscillator
kadonotakashi	0:8fdf9a60065b	1543	is running, the oscillator continues running though the RNG clock.
kadonotakashi	0:8fdf9a60065b	1544	is stopped. */
kadonotakashi	0:8fdf9a60065b	1545	while (TRNG_RD_MCTL_TSTOP_OK(base) == 0)
kadonotakashi	0:8fdf9a60065b	1546	{
kadonotakashi	0:8fdf9a60065b	1547	}
kadonotakashi	0:8fdf9a60065b	1548
kadonotakashi	0:8fdf9a60065b	1549	#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
kadonotakashi	0:8fdf9a60065b	1550	/* Disable Clock*/
kadonotakashi	0:8fdf9a60065b	1551	CLOCK_DisableClock(kCLOCK_Trng0);
kadonotakashi	0:8fdf9a60065b	1552	#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
kadonotakashi	0:8fdf9a60065b	1553	}
kadonotakashi	0:8fdf9a60065b	1554	}
kadonotakashi	0:8fdf9a60065b	1555
kadonotakashi	0:8fdf9a60065b	1556	status_t TRNG_GetRandomData(TRNG_Type base, void data, size_t dataSize)
kadonotakashi	0:8fdf9a60065b	1557	{
kadonotakashi	0:8fdf9a60065b	1558	status_t result = kStatus_Success;
kadonotakashi	0:8fdf9a60065b	1559	uint32_t random_32;
kadonotakashi	0:8fdf9a60065b	1560	uint8_t *random_p;
kadonotakashi	0:8fdf9a60065b	1561	uint32_t random_size;
kadonotakashi	0:8fdf9a60065b	1562	uint8_t data_p = (uint8_t )data;
kadonotakashi	0:8fdf9a60065b	1563	uint32_t i;
kadonotakashi	0:8fdf9a60065b	1564	int index = 0;
kadonotakashi	0:8fdf9a60065b	1565
kadonotakashi	0:8fdf9a60065b	1566	/* Check input parameters.*/
kadonotakashi	0:8fdf9a60065b	1567	if (base && data && dataSize)
kadonotakashi	0:8fdf9a60065b	1568	{
kadonotakashi	0:8fdf9a60065b	1569	do
kadonotakashi	0:8fdf9a60065b	1570	{
kadonotakashi	0:8fdf9a60065b	1571	/* Wait for Valid or Error flag*/
kadonotakashi	0:8fdf9a60065b	1572	while ((TRNG_RD_MCTL_ENT_VAL(base) == 0) && (TRNG_RD_MCTL_ERR(base) == 0))
kadonotakashi	0:8fdf9a60065b	1573	{
kadonotakashi	0:8fdf9a60065b	1574	}
kadonotakashi	0:8fdf9a60065b	1575
kadonotakashi	0:8fdf9a60065b	1576	/* Check HW error.*/
kadonotakashi	0:8fdf9a60065b	1577	if (TRNG_RD_MCTL_ERR(base))
kadonotakashi	0:8fdf9a60065b	1578	{
kadonotakashi	0:8fdf9a60065b	1579	result = kStatus_Fail; /* TRNG module error occurred */
kadonotakashi	0:8fdf9a60065b	1580	/* Clear error.*/
kadonotakashi	0:8fdf9a60065b	1581	TRNG_WR_MCTL_ERR(base, 1);
kadonotakashi	0:8fdf9a60065b	1582	break; /* No sense stay here.*/
kadonotakashi	0:8fdf9a60065b	1583	}
kadonotakashi	0:8fdf9a60065b	1584
kadonotakashi	0:8fdf9a60065b	1585	/* Read Entropy.*/
kadonotakashi	0:8fdf9a60065b	1586	random_32 = trng_ReadEntropy(base, index++);
kadonotakashi	0:8fdf9a60065b	1587
kadonotakashi	0:8fdf9a60065b	1588	random_p = (uint8_t *)&random_32;
kadonotakashi	0:8fdf9a60065b	1589
kadonotakashi	0:8fdf9a60065b	1590	if (dataSize < sizeof(random_32))
kadonotakashi	0:8fdf9a60065b	1591	{
kadonotakashi	0:8fdf9a60065b	1592	random_size = dataSize;
kadonotakashi	0:8fdf9a60065b	1593	}
kadonotakashi	0:8fdf9a60065b	1594	else
kadonotakashi	0:8fdf9a60065b	1595	{
kadonotakashi	0:8fdf9a60065b	1596	random_size = sizeof(random_32);
kadonotakashi	0:8fdf9a60065b	1597	}
kadonotakashi	0:8fdf9a60065b	1598
kadonotakashi	0:8fdf9a60065b	1599	for (i = 0U; i < random_size; i++)
kadonotakashi	0:8fdf9a60065b	1600	{
kadonotakashi	0:8fdf9a60065b	1601	data_p++ = random_p++;
kadonotakashi	0:8fdf9a60065b	1602	}
kadonotakashi	0:8fdf9a60065b	1603
kadonotakashi	0:8fdf9a60065b	1604	dataSize -= random_size;
kadonotakashi	0:8fdf9a60065b	1605	} while (dataSize > 0);
kadonotakashi	0:8fdf9a60065b	1606
kadonotakashi	0:8fdf9a60065b	1607	/* Start a new entropy generation.
kadonotakashi	0:8fdf9a60065b	1608	It is done by reading of the last entropy register.*/
kadonotakashi	0:8fdf9a60065b	1609	if ((index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1))
kadonotakashi	0:8fdf9a60065b	1610	{
kadonotakashi	0:8fdf9a60065b	1611	trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1));
kadonotakashi	0:8fdf9a60065b	1612	}
kadonotakashi	0:8fdf9a60065b	1613	}
kadonotakashi	0:8fdf9a60065b	1614	else
kadonotakashi	0:8fdf9a60065b	1615	{
kadonotakashi	0:8fdf9a60065b	1616	result = kStatus_InvalidArgument;
kadonotakashi	0:8fdf9a60065b	1617	}
kadonotakashi	0:8fdf9a60065b	1618
kadonotakashi	0:8fdf9a60065b	1619	return result;
kadonotakashi	0:8fdf9a60065b	1620	}
kadonotakashi	0:8fdf9a60065b	1621
kadonotakashi	0:8fdf9a60065b	1622	#endif /* FSL_FEATURE_SOC_TRNG_COUNT */

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Type:	Program
Mbed OS support:	Mbed OS
Created:	11 Oct 2018
Imports:	15
Forks:	0
Commits:	4
Dependents:	0
Dependencies:	1
Followers:	1

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_trng.c@3:f3764f852aa8, 2018-10-11 (annotated)

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