takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_llwu.c@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /*
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
kadonotakashi 0:8fdf9a60065b 3 * All rights reserved.
kadonotakashi 0:8fdf9a60065b 4 *
kadonotakashi 0:8fdf9a60065b 5 * Redistribution and use in source and binary forms, with or without modification,
kadonotakashi 0:8fdf9a60065b 6 * are permitted provided that the following conditions are met:
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * o Redistributions of source code must retain the above copyright notice, this list
kadonotakashi 0:8fdf9a60065b 9 * of conditions and the following disclaimer.
kadonotakashi 0:8fdf9a60065b 10 *
kadonotakashi 0:8fdf9a60065b 11 * o Redistributions in binary form must reproduce the above copyright notice, this
kadonotakashi 0:8fdf9a60065b 12 * list of conditions and the following disclaimer in the documentation and/or
kadonotakashi 0:8fdf9a60065b 13 * other materials provided with the distribution.
kadonotakashi 0:8fdf9a60065b 14 *
kadonotakashi 0:8fdf9a60065b 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kadonotakashi 0:8fdf9a60065b 16 * contributors may be used to endorse or promote products derived from this
kadonotakashi 0:8fdf9a60065b 17 * software without specific prior written permission.
kadonotakashi 0:8fdf9a60065b 18 *
kadonotakashi 0:8fdf9a60065b 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kadonotakashi 0:8fdf9a60065b 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kadonotakashi 0:8fdf9a60065b 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kadonotakashi 0:8fdf9a60065b 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kadonotakashi 0:8fdf9a60065b 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kadonotakashi 0:8fdf9a60065b 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kadonotakashi 0:8fdf9a60065b 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kadonotakashi 0:8fdf9a60065b 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kadonotakashi 0:8fdf9a60065b 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kadonotakashi 0:8fdf9a60065b 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kadonotakashi 0:8fdf9a60065b 29 */
kadonotakashi 0:8fdf9a60065b 30
kadonotakashi 0:8fdf9a60065b 31 #include "fsl_llwu.h"
kadonotakashi 0:8fdf9a60065b 32
kadonotakashi 0:8fdf9a60065b 33 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN)
kadonotakashi 0:8fdf9a60065b 34 void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode)
kadonotakashi 0:8fdf9a60065b 35 {
kadonotakashi 0:8fdf9a60065b 36 #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
kadonotakashi 0:8fdf9a60065b 37 volatile uint32_t *regBase;
kadonotakashi 0:8fdf9a60065b 38 uint32_t regOffset;
kadonotakashi 0:8fdf9a60065b 39 uint32_t reg;
kadonotakashi 0:8fdf9a60065b 40
kadonotakashi 0:8fdf9a60065b 41 switch (pinIndex >> 4U)
kadonotakashi 0:8fdf9a60065b 42 {
kadonotakashi 0:8fdf9a60065b 43 case 0U:
kadonotakashi 0:8fdf9a60065b 44 regBase = &base->PE1;
kadonotakashi 0:8fdf9a60065b 45 break;
kadonotakashi 0:8fdf9a60065b 46 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
kadonotakashi 0:8fdf9a60065b 47 case 1U:
kadonotakashi 0:8fdf9a60065b 48 regBase = &base->PE2;
kadonotakashi 0:8fdf9a60065b 49 break;
kadonotakashi 0:8fdf9a60065b 50 #endif
kadonotakashi 0:8fdf9a60065b 51 default:
kadonotakashi 0:8fdf9a60065b 52 regBase = NULL;
kadonotakashi 0:8fdf9a60065b 53 break;
kadonotakashi 0:8fdf9a60065b 54 }
kadonotakashi 0:8fdf9a60065b 55 #else
kadonotakashi 0:8fdf9a60065b 56 volatile uint8_t *regBase;
kadonotakashi 0:8fdf9a60065b 57 uint8_t regOffset;
kadonotakashi 0:8fdf9a60065b 58 uint8_t reg;
kadonotakashi 0:8fdf9a60065b 59 switch (pinIndex >> 2U)
kadonotakashi 0:8fdf9a60065b 60 {
kadonotakashi 0:8fdf9a60065b 61 case 0U:
kadonotakashi 0:8fdf9a60065b 62 regBase = &base->PE1;
kadonotakashi 0:8fdf9a60065b 63 break;
kadonotakashi 0:8fdf9a60065b 64 case 1U:
kadonotakashi 0:8fdf9a60065b 65 regBase = &base->PE2;
kadonotakashi 0:8fdf9a60065b 66 break;
kadonotakashi 0:8fdf9a60065b 67 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
kadonotakashi 0:8fdf9a60065b 68 case 2U:
kadonotakashi 0:8fdf9a60065b 69 regBase = &base->PE3;
kadonotakashi 0:8fdf9a60065b 70 break;
kadonotakashi 0:8fdf9a60065b 71 #endif
kadonotakashi 0:8fdf9a60065b 72 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 12))
kadonotakashi 0:8fdf9a60065b 73 case 3U:
kadonotakashi 0:8fdf9a60065b 74 regBase = &base->PE4;
kadonotakashi 0:8fdf9a60065b 75 break;
kadonotakashi 0:8fdf9a60065b 76 #endif
kadonotakashi 0:8fdf9a60065b 77 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
kadonotakashi 0:8fdf9a60065b 78 case 4U:
kadonotakashi 0:8fdf9a60065b 79 regBase = &base->PE5;
kadonotakashi 0:8fdf9a60065b 80 break;
kadonotakashi 0:8fdf9a60065b 81 #endif
kadonotakashi 0:8fdf9a60065b 82 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 20))
kadonotakashi 0:8fdf9a60065b 83 case 5U:
kadonotakashi 0:8fdf9a60065b 84 regBase = &base->PE6;
kadonotakashi 0:8fdf9a60065b 85 break;
kadonotakashi 0:8fdf9a60065b 86 #endif
kadonotakashi 0:8fdf9a60065b 87 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
kadonotakashi 0:8fdf9a60065b 88 case 6U:
kadonotakashi 0:8fdf9a60065b 89 regBase = &base->PE7;
kadonotakashi 0:8fdf9a60065b 90 break;
kadonotakashi 0:8fdf9a60065b 91 #endif
kadonotakashi 0:8fdf9a60065b 92 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 28))
kadonotakashi 0:8fdf9a60065b 93 case 7U:
kadonotakashi 0:8fdf9a60065b 94 regBase = &base->PE8;
kadonotakashi 0:8fdf9a60065b 95 break;
kadonotakashi 0:8fdf9a60065b 96 #endif
kadonotakashi 0:8fdf9a60065b 97 default:
kadonotakashi 0:8fdf9a60065b 98 regBase = NULL;
kadonotakashi 0:8fdf9a60065b 99 break;
kadonotakashi 0:8fdf9a60065b 100 }
kadonotakashi 0:8fdf9a60065b 101 #endif /* FSL_FEATURE_LLWU_REG_BITWIDTH == 32 */
kadonotakashi 0:8fdf9a60065b 102
kadonotakashi 0:8fdf9a60065b 103 if (regBase)
kadonotakashi 0:8fdf9a60065b 104 {
kadonotakashi 0:8fdf9a60065b 105 reg = *regBase;
kadonotakashi 0:8fdf9a60065b 106 #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
kadonotakashi 0:8fdf9a60065b 107 regOffset = ((pinIndex & 0x0FU) << 1U);
kadonotakashi 0:8fdf9a60065b 108 #else
kadonotakashi 0:8fdf9a60065b 109 regOffset = ((pinIndex & 0x03U) << 1U);
kadonotakashi 0:8fdf9a60065b 110 #endif
kadonotakashi 0:8fdf9a60065b 111 reg &= ~(0x3U << regOffset);
kadonotakashi 0:8fdf9a60065b 112 reg |= ((uint32_t)pinMode << regOffset);
kadonotakashi 0:8fdf9a60065b 113 *regBase = reg;
kadonotakashi 0:8fdf9a60065b 114 }
kadonotakashi 0:8fdf9a60065b 115 }
kadonotakashi 0:8fdf9a60065b 116
kadonotakashi 0:8fdf9a60065b 117 bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex)
kadonotakashi 0:8fdf9a60065b 118 {
kadonotakashi 0:8fdf9a60065b 119 #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
kadonotakashi 0:8fdf9a60065b 120 return (bool)(base->PF & (1U << pinIndex));
kadonotakashi 0:8fdf9a60065b 121 #else
kadonotakashi 0:8fdf9a60065b 122 volatile uint8_t *regBase;
kadonotakashi 0:8fdf9a60065b 123
kadonotakashi 0:8fdf9a60065b 124 switch (pinIndex >> 3U)
kadonotakashi 0:8fdf9a60065b 125 {
kadonotakashi 0:8fdf9a60065b 126 #if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
kadonotakashi 0:8fdf9a60065b 127 case 0U:
kadonotakashi 0:8fdf9a60065b 128 regBase = &base->PF1;
kadonotakashi 0:8fdf9a60065b 129 break;
kadonotakashi 0:8fdf9a60065b 130 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
kadonotakashi 0:8fdf9a60065b 131 case 1U:
kadonotakashi 0:8fdf9a60065b 132 regBase = &base->PF2;
kadonotakashi 0:8fdf9a60065b 133 break;
kadonotakashi 0:8fdf9a60065b 134 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 135 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
kadonotakashi 0:8fdf9a60065b 136 case 2U:
kadonotakashi 0:8fdf9a60065b 137 regBase = &base->PF3;
kadonotakashi 0:8fdf9a60065b 138 break;
kadonotakashi 0:8fdf9a60065b 139 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 140 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
kadonotakashi 0:8fdf9a60065b 141 case 3U:
kadonotakashi 0:8fdf9a60065b 142 regBase = &base->PF4;
kadonotakashi 0:8fdf9a60065b 143 break;
kadonotakashi 0:8fdf9a60065b 144 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 145 #else
kadonotakashi 0:8fdf9a60065b 146 case 0U:
kadonotakashi 0:8fdf9a60065b 147 regBase = &base->F1;
kadonotakashi 0:8fdf9a60065b 148 break;
kadonotakashi 0:8fdf9a60065b 149 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
kadonotakashi 0:8fdf9a60065b 150 case 1U:
kadonotakashi 0:8fdf9a60065b 151 regBase = &base->F2;
kadonotakashi 0:8fdf9a60065b 152 break;
kadonotakashi 0:8fdf9a60065b 153 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 154 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
kadonotakashi 0:8fdf9a60065b 155 case 2U:
kadonotakashi 0:8fdf9a60065b 156 regBase = &base->F3;
kadonotakashi 0:8fdf9a60065b 157 break;
kadonotakashi 0:8fdf9a60065b 158 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 159 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
kadonotakashi 0:8fdf9a60065b 160 case 3U:
kadonotakashi 0:8fdf9a60065b 161 regBase = &base->F4;
kadonotakashi 0:8fdf9a60065b 162 break;
kadonotakashi 0:8fdf9a60065b 163 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 164 #endif /* FSL_FEATURE_LLWU_HAS_PF */
kadonotakashi 0:8fdf9a60065b 165 default:
kadonotakashi 0:8fdf9a60065b 166 regBase = NULL;
kadonotakashi 0:8fdf9a60065b 167 break;
kadonotakashi 0:8fdf9a60065b 168 }
kadonotakashi 0:8fdf9a60065b 169
kadonotakashi 0:8fdf9a60065b 170 if (regBase)
kadonotakashi 0:8fdf9a60065b 171 {
kadonotakashi 0:8fdf9a60065b 172 return (bool)(*regBase & (1U << pinIndex % 8));
kadonotakashi 0:8fdf9a60065b 173 }
kadonotakashi 0:8fdf9a60065b 174 else
kadonotakashi 0:8fdf9a60065b 175 {
kadonotakashi 0:8fdf9a60065b 176 return false;
kadonotakashi 0:8fdf9a60065b 177 }
kadonotakashi 0:8fdf9a60065b 178 #endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
kadonotakashi 0:8fdf9a60065b 179 }
kadonotakashi 0:8fdf9a60065b 180
kadonotakashi 0:8fdf9a60065b 181 void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex)
kadonotakashi 0:8fdf9a60065b 182 {
kadonotakashi 0:8fdf9a60065b 183 #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
kadonotakashi 0:8fdf9a60065b 184 base->PF = (1U << pinIndex);
kadonotakashi 0:8fdf9a60065b 185 #else
kadonotakashi 0:8fdf9a60065b 186 volatile uint8_t *regBase;
kadonotakashi 0:8fdf9a60065b 187 switch (pinIndex >> 3U)
kadonotakashi 0:8fdf9a60065b 188 {
kadonotakashi 0:8fdf9a60065b 189 #if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
kadonotakashi 0:8fdf9a60065b 190 case 0U:
kadonotakashi 0:8fdf9a60065b 191 regBase = &base->PF1;
kadonotakashi 0:8fdf9a60065b 192 break;
kadonotakashi 0:8fdf9a60065b 193 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
kadonotakashi 0:8fdf9a60065b 194 case 1U:
kadonotakashi 0:8fdf9a60065b 195 regBase = &base->PF2;
kadonotakashi 0:8fdf9a60065b 196 break;
kadonotakashi 0:8fdf9a60065b 197 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 198 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
kadonotakashi 0:8fdf9a60065b 199 case 2U:
kadonotakashi 0:8fdf9a60065b 200 regBase = &base->PF3;
kadonotakashi 0:8fdf9a60065b 201 break;
kadonotakashi 0:8fdf9a60065b 202 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 203 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
kadonotakashi 0:8fdf9a60065b 204 case 3U:
kadonotakashi 0:8fdf9a60065b 205 regBase = &base->PF4;
kadonotakashi 0:8fdf9a60065b 206 break;
kadonotakashi 0:8fdf9a60065b 207 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 208 #else
kadonotakashi 0:8fdf9a60065b 209 case 0U:
kadonotakashi 0:8fdf9a60065b 210 regBase = &base->F1;
kadonotakashi 0:8fdf9a60065b 211 break;
kadonotakashi 0:8fdf9a60065b 212 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8))
kadonotakashi 0:8fdf9a60065b 213 case 1U:
kadonotakashi 0:8fdf9a60065b 214 regBase = &base->F2;
kadonotakashi 0:8fdf9a60065b 215 break;
kadonotakashi 0:8fdf9a60065b 216 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 217 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
kadonotakashi 0:8fdf9a60065b 218 case 2U:
kadonotakashi 0:8fdf9a60065b 219 regBase = &base->F3;
kadonotakashi 0:8fdf9a60065b 220 break;
kadonotakashi 0:8fdf9a60065b 221 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 222 #if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24))
kadonotakashi 0:8fdf9a60065b 223 case 3U:
kadonotakashi 0:8fdf9a60065b 224 regBase = &base->F4;
kadonotakashi 0:8fdf9a60065b 225 break;
kadonotakashi 0:8fdf9a60065b 226 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 227 #endif /* FSL_FEATURE_LLWU_HAS_PF */
kadonotakashi 0:8fdf9a60065b 228 default:
kadonotakashi 0:8fdf9a60065b 229 regBase = NULL;
kadonotakashi 0:8fdf9a60065b 230 break;
kadonotakashi 0:8fdf9a60065b 231 }
kadonotakashi 0:8fdf9a60065b 232 if (regBase)
kadonotakashi 0:8fdf9a60065b 233 {
kadonotakashi 0:8fdf9a60065b 234 *regBase = (1U << pinIndex % 8U);
kadonotakashi 0:8fdf9a60065b 235 }
kadonotakashi 0:8fdf9a60065b 236 #endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
kadonotakashi 0:8fdf9a60065b 237 }
kadonotakashi 0:8fdf9a60065b 238 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
kadonotakashi 0:8fdf9a60065b 239
kadonotakashi 0:8fdf9a60065b 240 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER)
kadonotakashi 0:8fdf9a60065b 241 void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode)
kadonotakashi 0:8fdf9a60065b 242 {
kadonotakashi 0:8fdf9a60065b 243 #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
kadonotakashi 0:8fdf9a60065b 244 uint32_t reg;
kadonotakashi 0:8fdf9a60065b 245
kadonotakashi 0:8fdf9a60065b 246 reg = base->FILT;
kadonotakashi 0:8fdf9a60065b 247 reg &= ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << (filterIndex * 8U - 1U));
kadonotakashi 0:8fdf9a60065b 248 reg |= (((filterMode.pinIndex << LLWU_FILT_FILTSEL1_SHIFT) | (filterMode.filterMode << LLWU_FILT_FILTE1_SHIFT)
kadonotakashi 0:8fdf9a60065b 249 /* Clear the Filter Detect Flag */
kadonotakashi 0:8fdf9a60065b 250 | LLWU_FILT_FILTF1_MASK)
kadonotakashi 0:8fdf9a60065b 251 << (filterIndex * 8U - 1U));
kadonotakashi 0:8fdf9a60065b 252 base->FILT = reg;
kadonotakashi 0:8fdf9a60065b 253 #else
kadonotakashi 0:8fdf9a60065b 254 volatile uint8_t *regBase;
kadonotakashi 0:8fdf9a60065b 255 uint8_t reg;
kadonotakashi 0:8fdf9a60065b 256
kadonotakashi 0:8fdf9a60065b 257 switch (filterIndex)
kadonotakashi 0:8fdf9a60065b 258 {
kadonotakashi 0:8fdf9a60065b 259 case 1:
kadonotakashi 0:8fdf9a60065b 260 regBase = &base->FILT1;
kadonotakashi 0:8fdf9a60065b 261 break;
kadonotakashi 0:8fdf9a60065b 262 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1))
kadonotakashi 0:8fdf9a60065b 263 case 2:
kadonotakashi 0:8fdf9a60065b 264 regBase = &base->FILT2;
kadonotakashi 0:8fdf9a60065b 265 break;
kadonotakashi 0:8fdf9a60065b 266 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
kadonotakashi 0:8fdf9a60065b 267 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2))
kadonotakashi 0:8fdf9a60065b 268 case 3:
kadonotakashi 0:8fdf9a60065b 269 regBase = &base->FILT3;
kadonotakashi 0:8fdf9a60065b 270 break;
kadonotakashi 0:8fdf9a60065b 271 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
kadonotakashi 0:8fdf9a60065b 272 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3))
kadonotakashi 0:8fdf9a60065b 273 case 4:
kadonotakashi 0:8fdf9a60065b 274 regBase = &base->FILT4;
kadonotakashi 0:8fdf9a60065b 275 break;
kadonotakashi 0:8fdf9a60065b 276 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
kadonotakashi 0:8fdf9a60065b 277 default:
kadonotakashi 0:8fdf9a60065b 278 regBase = NULL;
kadonotakashi 0:8fdf9a60065b 279 break;
kadonotakashi 0:8fdf9a60065b 280 }
kadonotakashi 0:8fdf9a60065b 281
kadonotakashi 0:8fdf9a60065b 282 if (regBase)
kadonotakashi 0:8fdf9a60065b 283 {
kadonotakashi 0:8fdf9a60065b 284 reg = *regBase;
kadonotakashi 0:8fdf9a60065b 285 reg &= ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK);
kadonotakashi 0:8fdf9a60065b 286 reg |= ((uint32_t)filterMode.pinIndex << LLWU_FILT1_FILTSEL_SHIFT);
kadonotakashi 0:8fdf9a60065b 287 reg |= ((uint32_t)filterMode.filterMode << LLWU_FILT1_FILTE_SHIFT);
kadonotakashi 0:8fdf9a60065b 288 /* Clear the Filter Detect Flag */
kadonotakashi 0:8fdf9a60065b 289 reg |= LLWU_FILT1_FILTF_MASK;
kadonotakashi 0:8fdf9a60065b 290 *regBase = reg;
kadonotakashi 0:8fdf9a60065b 291 }
kadonotakashi 0:8fdf9a60065b 292 #endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
kadonotakashi 0:8fdf9a60065b 293 }
kadonotakashi 0:8fdf9a60065b 294
kadonotakashi 0:8fdf9a60065b 295 bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex)
kadonotakashi 0:8fdf9a60065b 296 {
kadonotakashi 0:8fdf9a60065b 297 #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
kadonotakashi 0:8fdf9a60065b 298 return (bool)(base->FILT & (1U << (filterIndex * 8U - 1)));
kadonotakashi 0:8fdf9a60065b 299 #else
kadonotakashi 0:8fdf9a60065b 300 bool status = false;
kadonotakashi 0:8fdf9a60065b 301
kadonotakashi 0:8fdf9a60065b 302 switch (filterIndex)
kadonotakashi 0:8fdf9a60065b 303 {
kadonotakashi 0:8fdf9a60065b 304 case 1:
kadonotakashi 0:8fdf9a60065b 305 status = (base->FILT1 & LLWU_FILT1_FILTF_MASK);
kadonotakashi 0:8fdf9a60065b 306 break;
kadonotakashi 0:8fdf9a60065b 307 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1))
kadonotakashi 0:8fdf9a60065b 308 case 2:
kadonotakashi 0:8fdf9a60065b 309 status = (base->FILT2 & LLWU_FILT2_FILTF_MASK);
kadonotakashi 0:8fdf9a60065b 310 break;
kadonotakashi 0:8fdf9a60065b 311 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
kadonotakashi 0:8fdf9a60065b 312 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2))
kadonotakashi 0:8fdf9a60065b 313 case 3:
kadonotakashi 0:8fdf9a60065b 314 status = (base->FILT3 & LLWU_FILT3_FILTF_MASK);
kadonotakashi 0:8fdf9a60065b 315 break;
kadonotakashi 0:8fdf9a60065b 316 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
kadonotakashi 0:8fdf9a60065b 317 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3))
kadonotakashi 0:8fdf9a60065b 318 case 4:
kadonotakashi 0:8fdf9a60065b 319 status = (base->FILT4 & LLWU_FILT4_FILTF_MASK);
kadonotakashi 0:8fdf9a60065b 320 break;
kadonotakashi 0:8fdf9a60065b 321 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
kadonotakashi 0:8fdf9a60065b 322 default:
kadonotakashi 0:8fdf9a60065b 323 break;
kadonotakashi 0:8fdf9a60065b 324 }
kadonotakashi 0:8fdf9a60065b 325
kadonotakashi 0:8fdf9a60065b 326 return status;
kadonotakashi 0:8fdf9a60065b 327 #endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
kadonotakashi 0:8fdf9a60065b 328 }
kadonotakashi 0:8fdf9a60065b 329
kadonotakashi 0:8fdf9a60065b 330 void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex)
kadonotakashi 0:8fdf9a60065b 331 {
kadonotakashi 0:8fdf9a60065b 332 #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
kadonotakashi 0:8fdf9a60065b 333 uint32_t reg;
kadonotakashi 0:8fdf9a60065b 334
kadonotakashi 0:8fdf9a60065b 335 reg = base->FILT;
kadonotakashi 0:8fdf9a60065b 336 switch (filterIndex)
kadonotakashi 0:8fdf9a60065b 337 {
kadonotakashi 0:8fdf9a60065b 338 case 1:
kadonotakashi 0:8fdf9a60065b 339 reg |= LLWU_FILT_FILTF1_MASK;
kadonotakashi 0:8fdf9a60065b 340 break;
kadonotakashi 0:8fdf9a60065b 341 case 2:
kadonotakashi 0:8fdf9a60065b 342 reg |= LLWU_FILT_FILTF2_MASK;
kadonotakashi 0:8fdf9a60065b 343 break;
kadonotakashi 0:8fdf9a60065b 344 case 3:
kadonotakashi 0:8fdf9a60065b 345 reg |= LLWU_FILT_FILTF3_MASK;
kadonotakashi 0:8fdf9a60065b 346 break;
kadonotakashi 0:8fdf9a60065b 347 case 4:
kadonotakashi 0:8fdf9a60065b 348 reg |= LLWU_FILT_FILTF4_MASK;
kadonotakashi 0:8fdf9a60065b 349 break;
kadonotakashi 0:8fdf9a60065b 350 default:
kadonotakashi 0:8fdf9a60065b 351 break;
kadonotakashi 0:8fdf9a60065b 352 }
kadonotakashi 0:8fdf9a60065b 353 base->FILT = reg;
kadonotakashi 0:8fdf9a60065b 354 #else
kadonotakashi 0:8fdf9a60065b 355 volatile uint8_t *regBase;
kadonotakashi 0:8fdf9a60065b 356 uint8_t reg;
kadonotakashi 0:8fdf9a60065b 357
kadonotakashi 0:8fdf9a60065b 358 switch (filterIndex)
kadonotakashi 0:8fdf9a60065b 359 {
kadonotakashi 0:8fdf9a60065b 360 case 1:
kadonotakashi 0:8fdf9a60065b 361 regBase = &base->FILT1;
kadonotakashi 0:8fdf9a60065b 362 break;
kadonotakashi 0:8fdf9a60065b 363 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1))
kadonotakashi 0:8fdf9a60065b 364 case 2:
kadonotakashi 0:8fdf9a60065b 365 regBase = &base->FILT2;
kadonotakashi 0:8fdf9a60065b 366 break;
kadonotakashi 0:8fdf9a60065b 367 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
kadonotakashi 0:8fdf9a60065b 368 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2))
kadonotakashi 0:8fdf9a60065b 369 case 3:
kadonotakashi 0:8fdf9a60065b 370 regBase = &base->FILT3;
kadonotakashi 0:8fdf9a60065b 371 break;
kadonotakashi 0:8fdf9a60065b 372 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
kadonotakashi 0:8fdf9a60065b 373 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3))
kadonotakashi 0:8fdf9a60065b 374 case 4:
kadonotakashi 0:8fdf9a60065b 375 regBase = &base->FILT4;
kadonotakashi 0:8fdf9a60065b 376 break;
kadonotakashi 0:8fdf9a60065b 377 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
kadonotakashi 0:8fdf9a60065b 378 default:
kadonotakashi 0:8fdf9a60065b 379 regBase = NULL;
kadonotakashi 0:8fdf9a60065b 380 break;
kadonotakashi 0:8fdf9a60065b 381 }
kadonotakashi 0:8fdf9a60065b 382
kadonotakashi 0:8fdf9a60065b 383 if (regBase)
kadonotakashi 0:8fdf9a60065b 384 {
kadonotakashi 0:8fdf9a60065b 385 reg = *regBase;
kadonotakashi 0:8fdf9a60065b 386 reg |= LLWU_FILT1_FILTF_MASK;
kadonotakashi 0:8fdf9a60065b 387 *regBase = reg;
kadonotakashi 0:8fdf9a60065b 388 }
kadonotakashi 0:8fdf9a60065b 389 #endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
kadonotakashi 0:8fdf9a60065b 390 }
kadonotakashi 0:8fdf9a60065b 391 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
kadonotakashi 0:8fdf9a60065b 392
kadonotakashi 0:8fdf9a60065b 393 #if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE)
kadonotakashi 0:8fdf9a60065b 394 void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode)
kadonotakashi 0:8fdf9a60065b 395 {
kadonotakashi 0:8fdf9a60065b 396 uint8_t reg;
kadonotakashi 0:8fdf9a60065b 397
kadonotakashi 0:8fdf9a60065b 398 reg = base->RST;
kadonotakashi 0:8fdf9a60065b 399 reg &= ~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK);
kadonotakashi 0:8fdf9a60065b 400 reg |=
kadonotakashi 0:8fdf9a60065b 401 (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)enableInLowLeakageMode << LLWU_RST_RSTFILT_SHIFT));
kadonotakashi 0:8fdf9a60065b 402 base->RST = reg;
kadonotakashi 0:8fdf9a60065b 403 }
kadonotakashi 0:8fdf9a60065b 404 #endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */