takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_flexio_i2c_master.c@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /*
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
kadonotakashi 0:8fdf9a60065b 3 * All rights reserved.
kadonotakashi 0:8fdf9a60065b 4 *
kadonotakashi 0:8fdf9a60065b 5 * Redistribution and use in source and binary forms, with or without modification,
kadonotakashi 0:8fdf9a60065b 6 * are permitted provided that the following conditions are met:
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * o Redistributions of source code must retain the above copyright notice, this list
kadonotakashi 0:8fdf9a60065b 9 * of conditions and the following disclaimer.
kadonotakashi 0:8fdf9a60065b 10 *
kadonotakashi 0:8fdf9a60065b 11 * o Redistributions in binary form must reproduce the above copyright notice, this
kadonotakashi 0:8fdf9a60065b 12 * list of conditions and the following disclaimer in the documentation and/or
kadonotakashi 0:8fdf9a60065b 13 * other materials provided with the distribution.
kadonotakashi 0:8fdf9a60065b 14 *
kadonotakashi 0:8fdf9a60065b 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kadonotakashi 0:8fdf9a60065b 16 * contributors may be used to endorse or promote products derived from this
kadonotakashi 0:8fdf9a60065b 17 * software without specific prior written permission.
kadonotakashi 0:8fdf9a60065b 18 *
kadonotakashi 0:8fdf9a60065b 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kadonotakashi 0:8fdf9a60065b 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kadonotakashi 0:8fdf9a60065b 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kadonotakashi 0:8fdf9a60065b 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kadonotakashi 0:8fdf9a60065b 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kadonotakashi 0:8fdf9a60065b 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kadonotakashi 0:8fdf9a60065b 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kadonotakashi 0:8fdf9a60065b 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kadonotakashi 0:8fdf9a60065b 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kadonotakashi 0:8fdf9a60065b 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kadonotakashi 0:8fdf9a60065b 29 */
kadonotakashi 0:8fdf9a60065b 30
kadonotakashi 0:8fdf9a60065b 31 #include "fsl_flexio_i2c_master.h"
kadonotakashi 0:8fdf9a60065b 32
kadonotakashi 0:8fdf9a60065b 33 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 34 * Definitions
kadonotakashi 0:8fdf9a60065b 35 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 36
kadonotakashi 0:8fdf9a60065b 37 /*! @brief FLEXIO I2C transfer state */
kadonotakashi 0:8fdf9a60065b 38 enum _flexio_i2c_master_transfer_states
kadonotakashi 0:8fdf9a60065b 39 {
kadonotakashi 0:8fdf9a60065b 40 kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */
kadonotakashi 0:8fdf9a60065b 41 kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */
kadonotakashi 0:8fdf9a60065b 42 kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */
kadonotakashi 0:8fdf9a60065b 43 kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/
kadonotakashi 0:8fdf9a60065b 44 kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/
kadonotakashi 0:8fdf9a60065b 45 kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/
kadonotakashi 0:8fdf9a60065b 46 };
kadonotakashi 0:8fdf9a60065b 47
kadonotakashi 0:8fdf9a60065b 48 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
kadonotakashi 0:8fdf9a60065b 49 extern const clock_ip_name_t s_flexioClocks[];
kadonotakashi 0:8fdf9a60065b 50 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
kadonotakashi 0:8fdf9a60065b 51
kadonotakashi 0:8fdf9a60065b 52 extern FLEXIO_Type *const s_flexioBases[];
kadonotakashi 0:8fdf9a60065b 53
kadonotakashi 0:8fdf9a60065b 54 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 55 * Prototypes
kadonotakashi 0:8fdf9a60065b 56 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 57
kadonotakashi 0:8fdf9a60065b 58 /*!
kadonotakashi 0:8fdf9a60065b 59 * @brief Set up master transfer, send slave address and decide the initial
kadonotakashi 0:8fdf9a60065b 60 * transfer state.
kadonotakashi 0:8fdf9a60065b 61 *
kadonotakashi 0:8fdf9a60065b 62 * @param base pointer to FLEXIO_I2C_Type structure
kadonotakashi 0:8fdf9a60065b 63 * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
kadonotakashi 0:8fdf9a60065b 64 * @param transfer pointer to flexio_i2c_master_transfer_t structure
kadonotakashi 0:8fdf9a60065b 65 */
kadonotakashi 0:8fdf9a60065b 66 static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
kadonotakashi 0:8fdf9a60065b 67 flexio_i2c_master_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 68 flexio_i2c_master_transfer_t *xfer);
kadonotakashi 0:8fdf9a60065b 69
kadonotakashi 0:8fdf9a60065b 70 /*!
kadonotakashi 0:8fdf9a60065b 71 * @brief Master run transfer state machine to perform a byte of transfer.
kadonotakashi 0:8fdf9a60065b 72 *
kadonotakashi 0:8fdf9a60065b 73 * @param base pointer to FLEXIO_I2C_Type structure
kadonotakashi 0:8fdf9a60065b 74 * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
kadonotakashi 0:8fdf9a60065b 75 * @param statusFlags flexio i2c hardware status
kadonotakashi 0:8fdf9a60065b 76 * @retval kStatus_Success Successfully run state machine
kadonotakashi 0:8fdf9a60065b 77 * @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer
kadonotakashi 0:8fdf9a60065b 78 */
kadonotakashi 0:8fdf9a60065b 79 static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
kadonotakashi 0:8fdf9a60065b 80 flexio_i2c_master_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 81 uint32_t statusFlags);
kadonotakashi 0:8fdf9a60065b 82
kadonotakashi 0:8fdf9a60065b 83 /*!
kadonotakashi 0:8fdf9a60065b 84 * @brief Complete transfer, disable interrupt and call callback.
kadonotakashi 0:8fdf9a60065b 85 *
kadonotakashi 0:8fdf9a60065b 86 * @param base pointer to FLEXIO_I2C_Type structure
kadonotakashi 0:8fdf9a60065b 87 * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
kadonotakashi 0:8fdf9a60065b 88 * @param status flexio transfer status
kadonotakashi 0:8fdf9a60065b 89 */
kadonotakashi 0:8fdf9a60065b 90 static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
kadonotakashi 0:8fdf9a60065b 91 flexio_i2c_master_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 92 status_t status);
kadonotakashi 0:8fdf9a60065b 93
kadonotakashi 0:8fdf9a60065b 94 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 95 * Codes
kadonotakashi 0:8fdf9a60065b 96 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 97
kadonotakashi 0:8fdf9a60065b 98 uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base)
kadonotakashi 0:8fdf9a60065b 99 {
kadonotakashi 0:8fdf9a60065b 100 uint32_t instance;
kadonotakashi 0:8fdf9a60065b 101 FLEXIO_Type *flexioBase = base->flexioBase;
kadonotakashi 0:8fdf9a60065b 102
kadonotakashi 0:8fdf9a60065b 103 /* Find the instance index from base address mappings. */
kadonotakashi 0:8fdf9a60065b 104 for (instance = 0; instance < FSL_FEATURE_SOC_FLEXIO_COUNT; instance++)
kadonotakashi 0:8fdf9a60065b 105 {
kadonotakashi 0:8fdf9a60065b 106 if (s_flexioBases[instance] == flexioBase)
kadonotakashi 0:8fdf9a60065b 107 {
kadonotakashi 0:8fdf9a60065b 108 break;
kadonotakashi 0:8fdf9a60065b 109 }
kadonotakashi 0:8fdf9a60065b 110 }
kadonotakashi 0:8fdf9a60065b 111
kadonotakashi 0:8fdf9a60065b 112 assert(instance < FSL_FEATURE_SOC_FLEXIO_COUNT);
kadonotakashi 0:8fdf9a60065b 113
kadonotakashi 0:8fdf9a60065b 114 return instance;
kadonotakashi 0:8fdf9a60065b 115 }
kadonotakashi 0:8fdf9a60065b 116
kadonotakashi 0:8fdf9a60065b 117 static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
kadonotakashi 0:8fdf9a60065b 118 flexio_i2c_master_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 119 flexio_i2c_master_transfer_t *xfer)
kadonotakashi 0:8fdf9a60065b 120 {
kadonotakashi 0:8fdf9a60065b 121 bool needRestart;
kadonotakashi 0:8fdf9a60065b 122 uint32_t byteCount;
kadonotakashi 0:8fdf9a60065b 123
kadonotakashi 0:8fdf9a60065b 124 /* Init the handle member. */
kadonotakashi 0:8fdf9a60065b 125 handle->transfer.slaveAddress = xfer->slaveAddress;
kadonotakashi 0:8fdf9a60065b 126 handle->transfer.direction = xfer->direction;
kadonotakashi 0:8fdf9a60065b 127 handle->transfer.subaddress = xfer->subaddress;
kadonotakashi 0:8fdf9a60065b 128 handle->transfer.subaddressSize = xfer->subaddressSize;
kadonotakashi 0:8fdf9a60065b 129 handle->transfer.data = xfer->data;
kadonotakashi 0:8fdf9a60065b 130 handle->transfer.dataSize = xfer->dataSize;
kadonotakashi 0:8fdf9a60065b 131 handle->transfer.flags = xfer->flags;
kadonotakashi 0:8fdf9a60065b 132 handle->transferSize = xfer->dataSize;
kadonotakashi 0:8fdf9a60065b 133
kadonotakashi 0:8fdf9a60065b 134 /* Initial state, i2c check address state. */
kadonotakashi 0:8fdf9a60065b 135 handle->state = kFLEXIO_I2C_CheckAddress;
kadonotakashi 0:8fdf9a60065b 136
kadonotakashi 0:8fdf9a60065b 137 /* Clear all status before transfer. */
kadonotakashi 0:8fdf9a60065b 138 FLEXIO_I2C_MasterClearStatusFlags(base, kFLEXIO_I2C_ReceiveNakFlag);
kadonotakashi 0:8fdf9a60065b 139
kadonotakashi 0:8fdf9a60065b 140 /* Calculate whether need to send re-start. */
kadonotakashi 0:8fdf9a60065b 141 needRestart = (handle->transfer.subaddressSize != 0) && (handle->transfer.direction == kFLEXIO_I2C_Read);
kadonotakashi 0:8fdf9a60065b 142
kadonotakashi 0:8fdf9a60065b 143 /* Calculate total byte count in a frame. */
kadonotakashi 0:8fdf9a60065b 144 byteCount = 1;
kadonotakashi 0:8fdf9a60065b 145
kadonotakashi 0:8fdf9a60065b 146 if (!needRestart)
kadonotakashi 0:8fdf9a60065b 147 {
kadonotakashi 0:8fdf9a60065b 148 byteCount += handle->transfer.dataSize;
kadonotakashi 0:8fdf9a60065b 149 }
kadonotakashi 0:8fdf9a60065b 150
kadonotakashi 0:8fdf9a60065b 151 if (handle->transfer.subaddressSize != 0)
kadonotakashi 0:8fdf9a60065b 152 {
kadonotakashi 0:8fdf9a60065b 153 byteCount += handle->transfer.subaddressSize;
kadonotakashi 0:8fdf9a60065b 154 /* Next state, send command byte. */
kadonotakashi 0:8fdf9a60065b 155 handle->state = kFLEXIO_I2C_SendCommand;
kadonotakashi 0:8fdf9a60065b 156 }
kadonotakashi 0:8fdf9a60065b 157
kadonotakashi 0:8fdf9a60065b 158 /* Configure data count. */
kadonotakashi 0:8fdf9a60065b 159 if (FLEXIO_I2C_MasterSetTransferCount(base, byteCount) != kStatus_Success)
kadonotakashi 0:8fdf9a60065b 160 {
kadonotakashi 0:8fdf9a60065b 161 return kStatus_InvalidArgument;
kadonotakashi 0:8fdf9a60065b 162 }
kadonotakashi 0:8fdf9a60065b 163
kadonotakashi 0:8fdf9a60065b 164 while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
kadonotakashi 0:8fdf9a60065b 165 {
kadonotakashi 0:8fdf9a60065b 166 }
kadonotakashi 0:8fdf9a60065b 167
kadonotakashi 0:8fdf9a60065b 168 /* Send address byte first. */
kadonotakashi 0:8fdf9a60065b 169 if (needRestart)
kadonotakashi 0:8fdf9a60065b 170 {
kadonotakashi 0:8fdf9a60065b 171 FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write);
kadonotakashi 0:8fdf9a60065b 172 }
kadonotakashi 0:8fdf9a60065b 173 else
kadonotakashi 0:8fdf9a60065b 174 {
kadonotakashi 0:8fdf9a60065b 175 FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction);
kadonotakashi 0:8fdf9a60065b 176 }
kadonotakashi 0:8fdf9a60065b 177
kadonotakashi 0:8fdf9a60065b 178 return kStatus_Success;
kadonotakashi 0:8fdf9a60065b 179 }
kadonotakashi 0:8fdf9a60065b 180
kadonotakashi 0:8fdf9a60065b 181 static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
kadonotakashi 0:8fdf9a60065b 182 flexio_i2c_master_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 183 uint32_t statusFlags)
kadonotakashi 0:8fdf9a60065b 184 {
kadonotakashi 0:8fdf9a60065b 185 if (statusFlags & kFLEXIO_I2C_ReceiveNakFlag)
kadonotakashi 0:8fdf9a60065b 186 {
kadonotakashi 0:8fdf9a60065b 187 /* Clear receive nak flag. */
kadonotakashi 0:8fdf9a60065b 188 FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
kadonotakashi 0:8fdf9a60065b 189
kadonotakashi 0:8fdf9a60065b 190 if ((!((handle->state == kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) &&
kadonotakashi 0:8fdf9a60065b 191 (!(((handle->state == kFLEXIO_I2C_ReceiveData) || (handle->state == kFLEXIO_I2C_ReceiveDataBegin)) &&
kadonotakashi 0:8fdf9a60065b 192 (handle->transfer.dataSize == 1U))))
kadonotakashi 0:8fdf9a60065b 193 {
kadonotakashi 0:8fdf9a60065b 194 FLEXIO_I2C_MasterReadByte(base);
kadonotakashi 0:8fdf9a60065b 195
kadonotakashi 0:8fdf9a60065b 196 FLEXIO_I2C_MasterAbortStop(base);
kadonotakashi 0:8fdf9a60065b 197
kadonotakashi 0:8fdf9a60065b 198 handle->state = kFLEXIO_I2C_Idle;
kadonotakashi 0:8fdf9a60065b 199
kadonotakashi 0:8fdf9a60065b 200 return kStatus_FLEXIO_I2C_Nak;
kadonotakashi 0:8fdf9a60065b 201 }
kadonotakashi 0:8fdf9a60065b 202 }
kadonotakashi 0:8fdf9a60065b 203
kadonotakashi 0:8fdf9a60065b 204 if (handle->state == kFLEXIO_I2C_CheckAddress)
kadonotakashi 0:8fdf9a60065b 205 {
kadonotakashi 0:8fdf9a60065b 206 if (handle->transfer.direction == kFLEXIO_I2C_Write)
kadonotakashi 0:8fdf9a60065b 207 {
kadonotakashi 0:8fdf9a60065b 208 /* Next state, send data. */
kadonotakashi 0:8fdf9a60065b 209 handle->state = kFLEXIO_I2C_SendData;
kadonotakashi 0:8fdf9a60065b 210 }
kadonotakashi 0:8fdf9a60065b 211 else
kadonotakashi 0:8fdf9a60065b 212 {
kadonotakashi 0:8fdf9a60065b 213 /* Next state, receive data begin. */
kadonotakashi 0:8fdf9a60065b 214 handle->state = kFLEXIO_I2C_ReceiveDataBegin;
kadonotakashi 0:8fdf9a60065b 215 }
kadonotakashi 0:8fdf9a60065b 216 }
kadonotakashi 0:8fdf9a60065b 217
kadonotakashi 0:8fdf9a60065b 218 if ((statusFlags & kFLEXIO_I2C_RxFullFlag) && (handle->state != kFLEXIO_I2C_ReceiveData))
kadonotakashi 0:8fdf9a60065b 219 {
kadonotakashi 0:8fdf9a60065b 220 FLEXIO_I2C_MasterReadByte(base);
kadonotakashi 0:8fdf9a60065b 221 }
kadonotakashi 0:8fdf9a60065b 222
kadonotakashi 0:8fdf9a60065b 223 switch (handle->state)
kadonotakashi 0:8fdf9a60065b 224 {
kadonotakashi 0:8fdf9a60065b 225 case kFLEXIO_I2C_SendCommand:
kadonotakashi 0:8fdf9a60065b 226 if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
kadonotakashi 0:8fdf9a60065b 227 {
kadonotakashi 0:8fdf9a60065b 228 if (handle->transfer.subaddressSize > 0)
kadonotakashi 0:8fdf9a60065b 229 {
kadonotakashi 0:8fdf9a60065b 230 handle->transfer.subaddressSize--;
kadonotakashi 0:8fdf9a60065b 231 FLEXIO_I2C_MasterWriteByte(
kadonotakashi 0:8fdf9a60065b 232 base, ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)));
kadonotakashi 0:8fdf9a60065b 233
kadonotakashi 0:8fdf9a60065b 234 if (handle->transfer.subaddressSize == 0)
kadonotakashi 0:8fdf9a60065b 235 {
kadonotakashi 0:8fdf9a60065b 236 /* Load re-start in advance. */
kadonotakashi 0:8fdf9a60065b 237 if (handle->transfer.direction == kFLEXIO_I2C_Read)
kadonotakashi 0:8fdf9a60065b 238 {
kadonotakashi 0:8fdf9a60065b 239 while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
kadonotakashi 0:8fdf9a60065b 240 {
kadonotakashi 0:8fdf9a60065b 241 }
kadonotakashi 0:8fdf9a60065b 242 FLEXIO_I2C_MasterRepeatedStart(base);
kadonotakashi 0:8fdf9a60065b 243 }
kadonotakashi 0:8fdf9a60065b 244 }
kadonotakashi 0:8fdf9a60065b 245 }
kadonotakashi 0:8fdf9a60065b 246 else
kadonotakashi 0:8fdf9a60065b 247 {
kadonotakashi 0:8fdf9a60065b 248 if (handle->transfer.direction == kFLEXIO_I2C_Write)
kadonotakashi 0:8fdf9a60065b 249 {
kadonotakashi 0:8fdf9a60065b 250 /* Next state, send data. */
kadonotakashi 0:8fdf9a60065b 251 handle->state = kFLEXIO_I2C_SendData;
kadonotakashi 0:8fdf9a60065b 252
kadonotakashi 0:8fdf9a60065b 253 /* Send first byte of data. */
kadonotakashi 0:8fdf9a60065b 254 if (handle->transfer.dataSize > 0)
kadonotakashi 0:8fdf9a60065b 255 {
kadonotakashi 0:8fdf9a60065b 256 FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
kadonotakashi 0:8fdf9a60065b 257
kadonotakashi 0:8fdf9a60065b 258 handle->transfer.data++;
kadonotakashi 0:8fdf9a60065b 259 handle->transfer.dataSize--;
kadonotakashi 0:8fdf9a60065b 260 }
kadonotakashi 0:8fdf9a60065b 261 }
kadonotakashi 0:8fdf9a60065b 262 else
kadonotakashi 0:8fdf9a60065b 263 {
kadonotakashi 0:8fdf9a60065b 264 FLEXIO_I2C_MasterSetTransferCount(base, (handle->transfer.dataSize + 1));
kadonotakashi 0:8fdf9a60065b 265 FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read);
kadonotakashi 0:8fdf9a60065b 266
kadonotakashi 0:8fdf9a60065b 267 /* Next state, receive data begin. */
kadonotakashi 0:8fdf9a60065b 268 handle->state = kFLEXIO_I2C_ReceiveDataBegin;
kadonotakashi 0:8fdf9a60065b 269 }
kadonotakashi 0:8fdf9a60065b 270 }
kadonotakashi 0:8fdf9a60065b 271 }
kadonotakashi 0:8fdf9a60065b 272 break;
kadonotakashi 0:8fdf9a60065b 273
kadonotakashi 0:8fdf9a60065b 274 /* Send command byte. */
kadonotakashi 0:8fdf9a60065b 275 case kFLEXIO_I2C_SendData:
kadonotakashi 0:8fdf9a60065b 276 if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
kadonotakashi 0:8fdf9a60065b 277 {
kadonotakashi 0:8fdf9a60065b 278 /* Send one byte of data. */
kadonotakashi 0:8fdf9a60065b 279 if (handle->transfer.dataSize > 0)
kadonotakashi 0:8fdf9a60065b 280 {
kadonotakashi 0:8fdf9a60065b 281 FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
kadonotakashi 0:8fdf9a60065b 282
kadonotakashi 0:8fdf9a60065b 283 handle->transfer.data++;
kadonotakashi 0:8fdf9a60065b 284 handle->transfer.dataSize--;
kadonotakashi 0:8fdf9a60065b 285 }
kadonotakashi 0:8fdf9a60065b 286 else
kadonotakashi 0:8fdf9a60065b 287 {
kadonotakashi 0:8fdf9a60065b 288 FLEXIO_I2C_MasterStop(base);
kadonotakashi 0:8fdf9a60065b 289
kadonotakashi 0:8fdf9a60065b 290 while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag))
kadonotakashi 0:8fdf9a60065b 291 {
kadonotakashi 0:8fdf9a60065b 292 }
kadonotakashi 0:8fdf9a60065b 293 FLEXIO_I2C_MasterReadByte(base);
kadonotakashi 0:8fdf9a60065b 294
kadonotakashi 0:8fdf9a60065b 295 handle->state = kFLEXIO_I2C_Idle;
kadonotakashi 0:8fdf9a60065b 296 }
kadonotakashi 0:8fdf9a60065b 297 }
kadonotakashi 0:8fdf9a60065b 298 break;
kadonotakashi 0:8fdf9a60065b 299
kadonotakashi 0:8fdf9a60065b 300 case kFLEXIO_I2C_ReceiveDataBegin:
kadonotakashi 0:8fdf9a60065b 301 if (statusFlags & kFLEXIO_I2C_RxFullFlag)
kadonotakashi 0:8fdf9a60065b 302 {
kadonotakashi 0:8fdf9a60065b 303 handle->state = kFLEXIO_I2C_ReceiveData;
kadonotakashi 0:8fdf9a60065b 304 /* Send nak at the last receive byte. */
kadonotakashi 0:8fdf9a60065b 305 if (handle->transfer.dataSize == 1)
kadonotakashi 0:8fdf9a60065b 306 {
kadonotakashi 0:8fdf9a60065b 307 FLEXIO_I2C_MasterEnableAck(base, false);
kadonotakashi 0:8fdf9a60065b 308 while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
kadonotakashi 0:8fdf9a60065b 309 {
kadonotakashi 0:8fdf9a60065b 310 }
kadonotakashi 0:8fdf9a60065b 311 FLEXIO_I2C_MasterStop(base);
kadonotakashi 0:8fdf9a60065b 312 }
kadonotakashi 0:8fdf9a60065b 313 else
kadonotakashi 0:8fdf9a60065b 314 {
kadonotakashi 0:8fdf9a60065b 315 FLEXIO_I2C_MasterEnableAck(base, true);
kadonotakashi 0:8fdf9a60065b 316 }
kadonotakashi 0:8fdf9a60065b 317 }
kadonotakashi 0:8fdf9a60065b 318 else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
kadonotakashi 0:8fdf9a60065b 319 {
kadonotakashi 0:8fdf9a60065b 320 /* Read one byte of data. */
kadonotakashi 0:8fdf9a60065b 321 FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
kadonotakashi 0:8fdf9a60065b 322 }
kadonotakashi 0:8fdf9a60065b 323 else
kadonotakashi 0:8fdf9a60065b 324 {
kadonotakashi 0:8fdf9a60065b 325 }
kadonotakashi 0:8fdf9a60065b 326 break;
kadonotakashi 0:8fdf9a60065b 327
kadonotakashi 0:8fdf9a60065b 328 case kFLEXIO_I2C_ReceiveData:
kadonotakashi 0:8fdf9a60065b 329 if (statusFlags & kFLEXIO_I2C_RxFullFlag)
kadonotakashi 0:8fdf9a60065b 330 {
kadonotakashi 0:8fdf9a60065b 331 *handle->transfer.data = FLEXIO_I2C_MasterReadByte(base);
kadonotakashi 0:8fdf9a60065b 332 handle->transfer.data++;
kadonotakashi 0:8fdf9a60065b 333 if (handle->transfer.dataSize--)
kadonotakashi 0:8fdf9a60065b 334 {
kadonotakashi 0:8fdf9a60065b 335 if (handle->transfer.dataSize == 0)
kadonotakashi 0:8fdf9a60065b 336 {
kadonotakashi 0:8fdf9a60065b 337 FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_RxFullInterruptEnable);
kadonotakashi 0:8fdf9a60065b 338 handle->state = kFLEXIO_I2C_Idle;
kadonotakashi 0:8fdf9a60065b 339 }
kadonotakashi 0:8fdf9a60065b 340
kadonotakashi 0:8fdf9a60065b 341 /* Send nak at the last receive byte. */
kadonotakashi 0:8fdf9a60065b 342 if (handle->transfer.dataSize == 1)
kadonotakashi 0:8fdf9a60065b 343 {
kadonotakashi 0:8fdf9a60065b 344 FLEXIO_I2C_MasterEnableAck(base, false);
kadonotakashi 0:8fdf9a60065b 345 while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
kadonotakashi 0:8fdf9a60065b 346 {
kadonotakashi 0:8fdf9a60065b 347 }
kadonotakashi 0:8fdf9a60065b 348 FLEXIO_I2C_MasterStop(base);
kadonotakashi 0:8fdf9a60065b 349 }
kadonotakashi 0:8fdf9a60065b 350 }
kadonotakashi 0:8fdf9a60065b 351 }
kadonotakashi 0:8fdf9a60065b 352 else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
kadonotakashi 0:8fdf9a60065b 353 {
kadonotakashi 0:8fdf9a60065b 354 if (handle->transfer.dataSize > 1)
kadonotakashi 0:8fdf9a60065b 355 {
kadonotakashi 0:8fdf9a60065b 356 FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
kadonotakashi 0:8fdf9a60065b 357 }
kadonotakashi 0:8fdf9a60065b 358 }
kadonotakashi 0:8fdf9a60065b 359 else
kadonotakashi 0:8fdf9a60065b 360 {
kadonotakashi 0:8fdf9a60065b 361 }
kadonotakashi 0:8fdf9a60065b 362 break;
kadonotakashi 0:8fdf9a60065b 363
kadonotakashi 0:8fdf9a60065b 364 default:
kadonotakashi 0:8fdf9a60065b 365 break;
kadonotakashi 0:8fdf9a60065b 366 }
kadonotakashi 0:8fdf9a60065b 367
kadonotakashi 0:8fdf9a60065b 368 return kStatus_Success;
kadonotakashi 0:8fdf9a60065b 369 }
kadonotakashi 0:8fdf9a60065b 370
kadonotakashi 0:8fdf9a60065b 371 static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
kadonotakashi 0:8fdf9a60065b 372 flexio_i2c_master_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 373 status_t status)
kadonotakashi 0:8fdf9a60065b 374 {
kadonotakashi 0:8fdf9a60065b 375 FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
kadonotakashi 0:8fdf9a60065b 376
kadonotakashi 0:8fdf9a60065b 377 if (handle->completionCallback)
kadonotakashi 0:8fdf9a60065b 378 {
kadonotakashi 0:8fdf9a60065b 379 handle->completionCallback(base, handle, status, handle->userData);
kadonotakashi 0:8fdf9a60065b 380 }
kadonotakashi 0:8fdf9a60065b 381 }
kadonotakashi 0:8fdf9a60065b 382
kadonotakashi 0:8fdf9a60065b 383 void FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
kadonotakashi 0:8fdf9a60065b 384 {
kadonotakashi 0:8fdf9a60065b 385 assert(base && masterConfig);
kadonotakashi 0:8fdf9a60065b 386
kadonotakashi 0:8fdf9a60065b 387 flexio_shifter_config_t shifterConfig;
kadonotakashi 0:8fdf9a60065b 388 flexio_timer_config_t timerConfig;
kadonotakashi 0:8fdf9a60065b 389 uint32_t controlVal = 0;
kadonotakashi 0:8fdf9a60065b 390
kadonotakashi 0:8fdf9a60065b 391 memset(&shifterConfig, 0, sizeof(shifterConfig));
kadonotakashi 0:8fdf9a60065b 392 memset(&timerConfig, 0, sizeof(timerConfig));
kadonotakashi 0:8fdf9a60065b 393
kadonotakashi 0:8fdf9a60065b 394 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
kadonotakashi 0:8fdf9a60065b 395 /* Ungate flexio clock. */
kadonotakashi 0:8fdf9a60065b 396 CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2C_GetInstance(base)]);
kadonotakashi 0:8fdf9a60065b 397 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
kadonotakashi 0:8fdf9a60065b 398
kadonotakashi 0:8fdf9a60065b 399 FLEXIO_Reset(base->flexioBase);
kadonotakashi 0:8fdf9a60065b 400
kadonotakashi 0:8fdf9a60065b 401 /* Do hardware configuration. */
kadonotakashi 0:8fdf9a60065b 402 /* 1. Configure the shifter 0 for tx. */
kadonotakashi 0:8fdf9a60065b 403 shifterConfig.timerSelect = base->timerIndex[1];
kadonotakashi 0:8fdf9a60065b 404 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
kadonotakashi 0:8fdf9a60065b 405 shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
kadonotakashi 0:8fdf9a60065b 406 shifterConfig.pinSelect = base->SDAPinIndex;
kadonotakashi 0:8fdf9a60065b 407 shifterConfig.pinPolarity = kFLEXIO_PinActiveLow;
kadonotakashi 0:8fdf9a60065b 408 shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
kadonotakashi 0:8fdf9a60065b 409 shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
kadonotakashi 0:8fdf9a60065b 410 shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
kadonotakashi 0:8fdf9a60065b 411 shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
kadonotakashi 0:8fdf9a60065b 412
kadonotakashi 0:8fdf9a60065b 413 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
kadonotakashi 0:8fdf9a60065b 414
kadonotakashi 0:8fdf9a60065b 415 /* 2. Configure the shifter 1 for rx. */
kadonotakashi 0:8fdf9a60065b 416 shifterConfig.timerSelect = base->timerIndex[1];
kadonotakashi 0:8fdf9a60065b 417 shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
kadonotakashi 0:8fdf9a60065b 418 shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
kadonotakashi 0:8fdf9a60065b 419 shifterConfig.pinSelect = base->SDAPinIndex;
kadonotakashi 0:8fdf9a60065b 420 shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
kadonotakashi 0:8fdf9a60065b 421 shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
kadonotakashi 0:8fdf9a60065b 422 shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
kadonotakashi 0:8fdf9a60065b 423 shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
kadonotakashi 0:8fdf9a60065b 424 shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
kadonotakashi 0:8fdf9a60065b 425
kadonotakashi 0:8fdf9a60065b 426 FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
kadonotakashi 0:8fdf9a60065b 427
kadonotakashi 0:8fdf9a60065b 428 /*3. Configure the timer 0 for generating bit clock. */
kadonotakashi 0:8fdf9a60065b 429 timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
kadonotakashi 0:8fdf9a60065b 430 timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
kadonotakashi 0:8fdf9a60065b 431 timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
kadonotakashi 0:8fdf9a60065b 432 timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
kadonotakashi 0:8fdf9a60065b 433 timerConfig.pinSelect = base->SCLPinIndex;
kadonotakashi 0:8fdf9a60065b 434 timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
kadonotakashi 0:8fdf9a60065b 435 timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
kadonotakashi 0:8fdf9a60065b 436 timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
kadonotakashi 0:8fdf9a60065b 437 timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
kadonotakashi 0:8fdf9a60065b 438 timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput;
kadonotakashi 0:8fdf9a60065b 439 timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
kadonotakashi 0:8fdf9a60065b 440 timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
kadonotakashi 0:8fdf9a60065b 441 timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
kadonotakashi 0:8fdf9a60065b 442 timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
kadonotakashi 0:8fdf9a60065b 443
kadonotakashi 0:8fdf9a60065b 444 /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */
kadonotakashi 0:8fdf9a60065b 445 timerConfig.timerCompare = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1;
kadonotakashi 0:8fdf9a60065b 446
kadonotakashi 0:8fdf9a60065b 447 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
kadonotakashi 0:8fdf9a60065b 448
kadonotakashi 0:8fdf9a60065b 449 /* 4. Configure the timer 1 for controlling shifters. */
kadonotakashi 0:8fdf9a60065b 450 timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
kadonotakashi 0:8fdf9a60065b 451 timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
kadonotakashi 0:8fdf9a60065b 452 timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
kadonotakashi 0:8fdf9a60065b 453 timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
kadonotakashi 0:8fdf9a60065b 454 timerConfig.pinSelect = base->SCLPinIndex;
kadonotakashi 0:8fdf9a60065b 455 timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
kadonotakashi 0:8fdf9a60065b 456 timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
kadonotakashi 0:8fdf9a60065b 457 timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
kadonotakashi 0:8fdf9a60065b 458 timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
kadonotakashi 0:8fdf9a60065b 459 timerConfig.timerReset = kFLEXIO_TimerResetNever;
kadonotakashi 0:8fdf9a60065b 460 timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
kadonotakashi 0:8fdf9a60065b 461 timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
kadonotakashi 0:8fdf9a60065b 462 timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare;
kadonotakashi 0:8fdf9a60065b 463 timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
kadonotakashi 0:8fdf9a60065b 464
kadonotakashi 0:8fdf9a60065b 465 /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */
kadonotakashi 0:8fdf9a60065b 466 timerConfig.timerCompare = 8 * 2 - 1;
kadonotakashi 0:8fdf9a60065b 467
kadonotakashi 0:8fdf9a60065b 468 FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
kadonotakashi 0:8fdf9a60065b 469
kadonotakashi 0:8fdf9a60065b 470 /* Configure FLEXIO I2C Master. */
kadonotakashi 0:8fdf9a60065b 471 controlVal = base->flexioBase->CTRL;
kadonotakashi 0:8fdf9a60065b 472 controlVal &=
kadonotakashi 0:8fdf9a60065b 473 ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
kadonotakashi 0:8fdf9a60065b 474 controlVal |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) |
kadonotakashi 0:8fdf9a60065b 475 FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster));
kadonotakashi 0:8fdf9a60065b 476 if (!masterConfig->enableInDoze)
kadonotakashi 0:8fdf9a60065b 477 {
kadonotakashi 0:8fdf9a60065b 478 controlVal |= FLEXIO_CTRL_DOZEN_MASK;
kadonotakashi 0:8fdf9a60065b 479 }
kadonotakashi 0:8fdf9a60065b 480
kadonotakashi 0:8fdf9a60065b 481 base->flexioBase->CTRL = controlVal;
kadonotakashi 0:8fdf9a60065b 482 }
kadonotakashi 0:8fdf9a60065b 483
kadonotakashi 0:8fdf9a60065b 484 void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
kadonotakashi 0:8fdf9a60065b 485 {
kadonotakashi 0:8fdf9a60065b 486 FLEXIO_Deinit(base->flexioBase);
kadonotakashi 0:8fdf9a60065b 487 }
kadonotakashi 0:8fdf9a60065b 488
kadonotakashi 0:8fdf9a60065b 489 void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
kadonotakashi 0:8fdf9a60065b 490 {
kadonotakashi 0:8fdf9a60065b 491 assert(masterConfig);
kadonotakashi 0:8fdf9a60065b 492
kadonotakashi 0:8fdf9a60065b 493 masterConfig->enableMaster = true;
kadonotakashi 0:8fdf9a60065b 494 masterConfig->enableInDoze = false;
kadonotakashi 0:8fdf9a60065b 495 masterConfig->enableInDebug = true;
kadonotakashi 0:8fdf9a60065b 496 masterConfig->enableFastAccess = false;
kadonotakashi 0:8fdf9a60065b 497
kadonotakashi 0:8fdf9a60065b 498 /* Default baud rate at 100kbps. */
kadonotakashi 0:8fdf9a60065b 499 masterConfig->baudRate_Bps = 100000U;
kadonotakashi 0:8fdf9a60065b 500 }
kadonotakashi 0:8fdf9a60065b 501
kadonotakashi 0:8fdf9a60065b 502 uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
kadonotakashi 0:8fdf9a60065b 503 {
kadonotakashi 0:8fdf9a60065b 504 uint32_t status = 0;
kadonotakashi 0:8fdf9a60065b 505
kadonotakashi 0:8fdf9a60065b 506 status =
kadonotakashi 0:8fdf9a60065b 507 ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]);
kadonotakashi 0:8fdf9a60065b 508 status |=
kadonotakashi 0:8fdf9a60065b 509 (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
kadonotakashi 0:8fdf9a60065b 510 << 1U);
kadonotakashi 0:8fdf9a60065b 511 status |=
kadonotakashi 0:8fdf9a60065b 512 (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
kadonotakashi 0:8fdf9a60065b 513 << 2U);
kadonotakashi 0:8fdf9a60065b 514
kadonotakashi 0:8fdf9a60065b 515 return status;
kadonotakashi 0:8fdf9a60065b 516 }
kadonotakashi 0:8fdf9a60065b 517
kadonotakashi 0:8fdf9a60065b 518 void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 519 {
kadonotakashi 0:8fdf9a60065b 520 if (mask & kFLEXIO_I2C_TxEmptyFlag)
kadonotakashi 0:8fdf9a60065b 521 {
kadonotakashi 0:8fdf9a60065b 522 FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]);
kadonotakashi 0:8fdf9a60065b 523 }
kadonotakashi 0:8fdf9a60065b 524
kadonotakashi 0:8fdf9a60065b 525 if (mask & kFLEXIO_I2C_RxFullFlag)
kadonotakashi 0:8fdf9a60065b 526 {
kadonotakashi 0:8fdf9a60065b 527 FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]);
kadonotakashi 0:8fdf9a60065b 528 }
kadonotakashi 0:8fdf9a60065b 529
kadonotakashi 0:8fdf9a60065b 530 if (mask & kFLEXIO_I2C_ReceiveNakFlag)
kadonotakashi 0:8fdf9a60065b 531 {
kadonotakashi 0:8fdf9a60065b 532 FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
kadonotakashi 0:8fdf9a60065b 533 }
kadonotakashi 0:8fdf9a60065b 534 }
kadonotakashi 0:8fdf9a60065b 535
kadonotakashi 0:8fdf9a60065b 536 void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 537 {
kadonotakashi 0:8fdf9a60065b 538 if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
kadonotakashi 0:8fdf9a60065b 539 {
kadonotakashi 0:8fdf9a60065b 540 FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
kadonotakashi 0:8fdf9a60065b 541 }
kadonotakashi 0:8fdf9a60065b 542 if (mask & kFLEXIO_I2C_RxFullInterruptEnable)
kadonotakashi 0:8fdf9a60065b 543 {
kadonotakashi 0:8fdf9a60065b 544 FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
kadonotakashi 0:8fdf9a60065b 545 }
kadonotakashi 0:8fdf9a60065b 546 }
kadonotakashi 0:8fdf9a60065b 547
kadonotakashi 0:8fdf9a60065b 548 void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 549 {
kadonotakashi 0:8fdf9a60065b 550 if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
kadonotakashi 0:8fdf9a60065b 551 {
kadonotakashi 0:8fdf9a60065b 552 FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
kadonotakashi 0:8fdf9a60065b 553 }
kadonotakashi 0:8fdf9a60065b 554 if (mask & kFLEXIO_I2C_RxFullInterruptEnable)
kadonotakashi 0:8fdf9a60065b 555 {
kadonotakashi 0:8fdf9a60065b 556 FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
kadonotakashi 0:8fdf9a60065b 557 }
kadonotakashi 0:8fdf9a60065b 558 }
kadonotakashi 0:8fdf9a60065b 559
kadonotakashi 0:8fdf9a60065b 560 void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
kadonotakashi 0:8fdf9a60065b 561 {
kadonotakashi 0:8fdf9a60065b 562 uint16_t timerDiv = 0;
kadonotakashi 0:8fdf9a60065b 563 uint16_t timerCmp = 0;
kadonotakashi 0:8fdf9a60065b 564 FLEXIO_Type *flexioBase = base->flexioBase;
kadonotakashi 0:8fdf9a60065b 565
kadonotakashi 0:8fdf9a60065b 566 /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
kadonotakashi 0:8fdf9a60065b 567 timerDiv = srcClock_Hz / baudRate_Bps;
kadonotakashi 0:8fdf9a60065b 568 timerDiv = timerDiv / 2 - 1U;
kadonotakashi 0:8fdf9a60065b 569
kadonotakashi 0:8fdf9a60065b 570 timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
kadonotakashi 0:8fdf9a60065b 571 timerCmp &= 0xFF00;
kadonotakashi 0:8fdf9a60065b 572 timerCmp |= timerDiv;
kadonotakashi 0:8fdf9a60065b 573
kadonotakashi 0:8fdf9a60065b 574 flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
kadonotakashi 0:8fdf9a60065b 575 }
kadonotakashi 0:8fdf9a60065b 576
kadonotakashi 0:8fdf9a60065b 577 status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
kadonotakashi 0:8fdf9a60065b 578 {
kadonotakashi 0:8fdf9a60065b 579 if (count > 14U)
kadonotakashi 0:8fdf9a60065b 580 {
kadonotakashi 0:8fdf9a60065b 581 return kStatus_InvalidArgument;
kadonotakashi 0:8fdf9a60065b 582 }
kadonotakashi 0:8fdf9a60065b 583
kadonotakashi 0:8fdf9a60065b 584 uint16_t timerCmp = 0;
kadonotakashi 0:8fdf9a60065b 585 uint32_t timerConfig = 0;
kadonotakashi 0:8fdf9a60065b 586 FLEXIO_Type *flexioBase = base->flexioBase;
kadonotakashi 0:8fdf9a60065b 587
kadonotakashi 0:8fdf9a60065b 588 timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
kadonotakashi 0:8fdf9a60065b 589 timerCmp &= 0x00FFU;
kadonotakashi 0:8fdf9a60065b 590 timerCmp |= (count * 18 + 1U) << 8U;
kadonotakashi 0:8fdf9a60065b 591 flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
kadonotakashi 0:8fdf9a60065b 592 timerConfig = flexioBase->TIMCFG[base->timerIndex[0]];
kadonotakashi 0:8fdf9a60065b 593 timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
kadonotakashi 0:8fdf9a60065b 594 timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
kadonotakashi 0:8fdf9a60065b 595 flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig;
kadonotakashi 0:8fdf9a60065b 596
kadonotakashi 0:8fdf9a60065b 597 return kStatus_Success;
kadonotakashi 0:8fdf9a60065b 598 }
kadonotakashi 0:8fdf9a60065b 599
kadonotakashi 0:8fdf9a60065b 600 void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)
kadonotakashi 0:8fdf9a60065b 601 {
kadonotakashi 0:8fdf9a60065b 602 uint32_t data;
kadonotakashi 0:8fdf9a60065b 603
kadonotakashi 0:8fdf9a60065b 604 data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U);
kadonotakashi 0:8fdf9a60065b 605
kadonotakashi 0:8fdf9a60065b 606 FLEXIO_I2C_MasterWriteByte(base, data);
kadonotakashi 0:8fdf9a60065b 607 }
kadonotakashi 0:8fdf9a60065b 608
kadonotakashi 0:8fdf9a60065b 609 void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)
kadonotakashi 0:8fdf9a60065b 610 {
kadonotakashi 0:8fdf9a60065b 611 /* Prepare for RESTART condition, no stop.*/
kadonotakashi 0:8fdf9a60065b 612 FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
kadonotakashi 0:8fdf9a60065b 613 }
kadonotakashi 0:8fdf9a60065b 614
kadonotakashi 0:8fdf9a60065b 615 void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
kadonotakashi 0:8fdf9a60065b 616 {
kadonotakashi 0:8fdf9a60065b 617 /* Prepare normal stop. */
kadonotakashi 0:8fdf9a60065b 618 FLEXIO_I2C_MasterSetTransferCount(base, 0x0U);
kadonotakashi 0:8fdf9a60065b 619 FLEXIO_I2C_MasterWriteByte(base, 0x0U);
kadonotakashi 0:8fdf9a60065b 620 }
kadonotakashi 0:8fdf9a60065b 621
kadonotakashi 0:8fdf9a60065b 622 void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
kadonotakashi 0:8fdf9a60065b 623 {
kadonotakashi 0:8fdf9a60065b 624 uint32_t tmpConfig;
kadonotakashi 0:8fdf9a60065b 625
kadonotakashi 0:8fdf9a60065b 626 /* Prepare abort stop. */
kadonotakashi 0:8fdf9a60065b 627 tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]];
kadonotakashi 0:8fdf9a60065b 628 tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
kadonotakashi 0:8fdf9a60065b 629 tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge);
kadonotakashi 0:8fdf9a60065b 630 base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig;
kadonotakashi 0:8fdf9a60065b 631 }
kadonotakashi 0:8fdf9a60065b 632
kadonotakashi 0:8fdf9a60065b 633 void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
kadonotakashi 0:8fdf9a60065b 634 {
kadonotakashi 0:8fdf9a60065b 635 uint32_t tmpConfig = 0;
kadonotakashi 0:8fdf9a60065b 636
kadonotakashi 0:8fdf9a60065b 637 tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]];
kadonotakashi 0:8fdf9a60065b 638 tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK;
kadonotakashi 0:8fdf9a60065b 639 if (enable)
kadonotakashi 0:8fdf9a60065b 640 {
kadonotakashi 0:8fdf9a60065b 641 tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow);
kadonotakashi 0:8fdf9a60065b 642 }
kadonotakashi 0:8fdf9a60065b 643 else
kadonotakashi 0:8fdf9a60065b 644 {
kadonotakashi 0:8fdf9a60065b 645 tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh);
kadonotakashi 0:8fdf9a60065b 646 }
kadonotakashi 0:8fdf9a60065b 647 base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig;
kadonotakashi 0:8fdf9a60065b 648 }
kadonotakashi 0:8fdf9a60065b 649
kadonotakashi 0:8fdf9a60065b 650 status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)
kadonotakashi 0:8fdf9a60065b 651 {
kadonotakashi 0:8fdf9a60065b 652 assert(txBuff);
kadonotakashi 0:8fdf9a60065b 653 assert(txSize);
kadonotakashi 0:8fdf9a60065b 654
kadonotakashi 0:8fdf9a60065b 655 uint32_t status;
kadonotakashi 0:8fdf9a60065b 656
kadonotakashi 0:8fdf9a60065b 657 while (txSize--)
kadonotakashi 0:8fdf9a60065b 658 {
kadonotakashi 0:8fdf9a60065b 659 FLEXIO_I2C_MasterWriteByte(base, *txBuff++);
kadonotakashi 0:8fdf9a60065b 660
kadonotakashi 0:8fdf9a60065b 661 /* Wait until data transfer complete. */
kadonotakashi 0:8fdf9a60065b 662 while (!((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & kFLEXIO_I2C_RxFullFlag))
kadonotakashi 0:8fdf9a60065b 663 {
kadonotakashi 0:8fdf9a60065b 664 }
kadonotakashi 0:8fdf9a60065b 665
kadonotakashi 0:8fdf9a60065b 666 if (status & kFLEXIO_I2C_ReceiveNakFlag)
kadonotakashi 0:8fdf9a60065b 667 {
kadonotakashi 0:8fdf9a60065b 668 FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
kadonotakashi 0:8fdf9a60065b 669 return kStatus_FLEXIO_I2C_Nak;
kadonotakashi 0:8fdf9a60065b 670 }
kadonotakashi 0:8fdf9a60065b 671 }
kadonotakashi 0:8fdf9a60065b 672 return kStatus_Success;
kadonotakashi 0:8fdf9a60065b 673 }
kadonotakashi 0:8fdf9a60065b 674
kadonotakashi 0:8fdf9a60065b 675 void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)
kadonotakashi 0:8fdf9a60065b 676 {
kadonotakashi 0:8fdf9a60065b 677 assert(rxBuff);
kadonotakashi 0:8fdf9a60065b 678 assert(rxSize);
kadonotakashi 0:8fdf9a60065b 679
kadonotakashi 0:8fdf9a60065b 680 while (rxSize--)
kadonotakashi 0:8fdf9a60065b 681 {
kadonotakashi 0:8fdf9a60065b 682 /* Wait until data transfer complete. */
kadonotakashi 0:8fdf9a60065b 683 while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag))
kadonotakashi 0:8fdf9a60065b 684 {
kadonotakashi 0:8fdf9a60065b 685 }
kadonotakashi 0:8fdf9a60065b 686
kadonotakashi 0:8fdf9a60065b 687 *rxBuff++ = FLEXIO_I2C_MasterReadByte(base);
kadonotakashi 0:8fdf9a60065b 688 }
kadonotakashi 0:8fdf9a60065b 689 }
kadonotakashi 0:8fdf9a60065b 690
kadonotakashi 0:8fdf9a60065b 691 status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)
kadonotakashi 0:8fdf9a60065b 692 {
kadonotakashi 0:8fdf9a60065b 693 assert(xfer);
kadonotakashi 0:8fdf9a60065b 694
kadonotakashi 0:8fdf9a60065b 695 flexio_i2c_master_handle_t tmpHandle;
kadonotakashi 0:8fdf9a60065b 696 uint32_t statusFlags;
kadonotakashi 0:8fdf9a60065b 697 uint32_t result = kStatus_Success;
kadonotakashi 0:8fdf9a60065b 698
kadonotakashi 0:8fdf9a60065b 699 /* Zero the handle. */
kadonotakashi 0:8fdf9a60065b 700 memset(&tmpHandle, 0, sizeof(tmpHandle));
kadonotakashi 0:8fdf9a60065b 701
kadonotakashi 0:8fdf9a60065b 702 /* Set up transfer machine. */
kadonotakashi 0:8fdf9a60065b 703 FLEXIO_I2C_MasterTransferInitStateMachine(base, &tmpHandle, xfer);
kadonotakashi 0:8fdf9a60065b 704
kadonotakashi 0:8fdf9a60065b 705 do
kadonotakashi 0:8fdf9a60065b 706 {
kadonotakashi 0:8fdf9a60065b 707 /* Wait either tx empty or rx full flag is asserted. */
kadonotakashi 0:8fdf9a60065b 708 while (!((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) &
kadonotakashi 0:8fdf9a60065b 709 (kFLEXIO_I2C_TxEmptyFlag | kFLEXIO_I2C_RxFullFlag)))
kadonotakashi 0:8fdf9a60065b 710 {
kadonotakashi 0:8fdf9a60065b 711 }
kadonotakashi 0:8fdf9a60065b 712
kadonotakashi 0:8fdf9a60065b 713 result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags);
kadonotakashi 0:8fdf9a60065b 714
kadonotakashi 0:8fdf9a60065b 715 } while ((tmpHandle.state != kFLEXIO_I2C_Idle) && (result == kStatus_Success));
kadonotakashi 0:8fdf9a60065b 716
kadonotakashi 0:8fdf9a60065b 717 return result;
kadonotakashi 0:8fdf9a60065b 718 }
kadonotakashi 0:8fdf9a60065b 719
kadonotakashi 0:8fdf9a60065b 720 status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
kadonotakashi 0:8fdf9a60065b 721 flexio_i2c_master_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 722 flexio_i2c_master_transfer_callback_t callback,
kadonotakashi 0:8fdf9a60065b 723 void *userData)
kadonotakashi 0:8fdf9a60065b 724 {
kadonotakashi 0:8fdf9a60065b 725 assert(handle);
kadonotakashi 0:8fdf9a60065b 726
kadonotakashi 0:8fdf9a60065b 727 IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
kadonotakashi 0:8fdf9a60065b 728
kadonotakashi 0:8fdf9a60065b 729 /* Zero the handle. */
kadonotakashi 0:8fdf9a60065b 730 memset(handle, 0, sizeof(*handle));
kadonotakashi 0:8fdf9a60065b 731
kadonotakashi 0:8fdf9a60065b 732 /* Register callback and userData. */
kadonotakashi 0:8fdf9a60065b 733 handle->completionCallback = callback;
kadonotakashi 0:8fdf9a60065b 734 handle->userData = userData;
kadonotakashi 0:8fdf9a60065b 735
kadonotakashi 0:8fdf9a60065b 736 /* Enable interrupt in NVIC. */
kadonotakashi 0:8fdf9a60065b 737 EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]);
kadonotakashi 0:8fdf9a60065b 738
kadonotakashi 0:8fdf9a60065b 739 /* Save the context in global variables to support the double weak mechanism. */
kadonotakashi 0:8fdf9a60065b 740 return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ);
kadonotakashi 0:8fdf9a60065b 741 }
kadonotakashi 0:8fdf9a60065b 742
kadonotakashi 0:8fdf9a60065b 743 status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
kadonotakashi 0:8fdf9a60065b 744 flexio_i2c_master_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 745 flexio_i2c_master_transfer_t *xfer)
kadonotakashi 0:8fdf9a60065b 746 {
kadonotakashi 0:8fdf9a60065b 747 assert(handle);
kadonotakashi 0:8fdf9a60065b 748 assert(xfer);
kadonotakashi 0:8fdf9a60065b 749
kadonotakashi 0:8fdf9a60065b 750 if (handle->state != kFLEXIO_I2C_Idle)
kadonotakashi 0:8fdf9a60065b 751 {
kadonotakashi 0:8fdf9a60065b 752 return kStatus_FLEXIO_I2C_Busy;
kadonotakashi 0:8fdf9a60065b 753 }
kadonotakashi 0:8fdf9a60065b 754 else
kadonotakashi 0:8fdf9a60065b 755 {
kadonotakashi 0:8fdf9a60065b 756 /* Set up transfer machine. */
kadonotakashi 0:8fdf9a60065b 757 FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer);
kadonotakashi 0:8fdf9a60065b 758
kadonotakashi 0:8fdf9a60065b 759 /* Enable both tx empty and rxfull interrupt. */
kadonotakashi 0:8fdf9a60065b 760 FLEXIO_I2C_MasterEnableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
kadonotakashi 0:8fdf9a60065b 761
kadonotakashi 0:8fdf9a60065b 762 return kStatus_Success;
kadonotakashi 0:8fdf9a60065b 763 }
kadonotakashi 0:8fdf9a60065b 764 }
kadonotakashi 0:8fdf9a60065b 765
kadonotakashi 0:8fdf9a60065b 766 void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)
kadonotakashi 0:8fdf9a60065b 767 {
kadonotakashi 0:8fdf9a60065b 768 assert(handle);
kadonotakashi 0:8fdf9a60065b 769
kadonotakashi 0:8fdf9a60065b 770 /* Disable interrupts. */
kadonotakashi 0:8fdf9a60065b 771 FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
kadonotakashi 0:8fdf9a60065b 772
kadonotakashi 0:8fdf9a60065b 773 /* Reset to idle state. */
kadonotakashi 0:8fdf9a60065b 774 handle->state = kFLEXIO_I2C_Idle;
kadonotakashi 0:8fdf9a60065b 775 }
kadonotakashi 0:8fdf9a60065b 776
kadonotakashi 0:8fdf9a60065b 777 status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)
kadonotakashi 0:8fdf9a60065b 778 {
kadonotakashi 0:8fdf9a60065b 779 if (!count)
kadonotakashi 0:8fdf9a60065b 780 {
kadonotakashi 0:8fdf9a60065b 781 return kStatus_InvalidArgument;
kadonotakashi 0:8fdf9a60065b 782 }
kadonotakashi 0:8fdf9a60065b 783
kadonotakashi 0:8fdf9a60065b 784 *count = handle->transferSize - handle->transfer.dataSize;
kadonotakashi 0:8fdf9a60065b 785
kadonotakashi 0:8fdf9a60065b 786 return kStatus_Success;
kadonotakashi 0:8fdf9a60065b 787 }
kadonotakashi 0:8fdf9a60065b 788
kadonotakashi 0:8fdf9a60065b 789 void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)
kadonotakashi 0:8fdf9a60065b 790 {
kadonotakashi 0:8fdf9a60065b 791 FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType;
kadonotakashi 0:8fdf9a60065b 792 flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle;
kadonotakashi 0:8fdf9a60065b 793 uint32_t statusFlags;
kadonotakashi 0:8fdf9a60065b 794 status_t result;
kadonotakashi 0:8fdf9a60065b 795
kadonotakashi 0:8fdf9a60065b 796 statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base);
kadonotakashi 0:8fdf9a60065b 797
kadonotakashi 0:8fdf9a60065b 798 result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags);
kadonotakashi 0:8fdf9a60065b 799
kadonotakashi 0:8fdf9a60065b 800 if (handle->state == kFLEXIO_I2C_Idle)
kadonotakashi 0:8fdf9a60065b 801 {
kadonotakashi 0:8fdf9a60065b 802 FLEXIO_I2C_MasterTransferComplete(base, handle, result);
kadonotakashi 0:8fdf9a60065b 803 }
kadonotakashi 0:8fdf9a60065b 804 }