takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/MK82F25615.h@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /*
kadonotakashi 0:8fdf9a60065b 2 ** ###################################################################
kadonotakashi 0:8fdf9a60065b 3 ** Processors: MK82FN256CAx15
kadonotakashi 0:8fdf9a60065b 4 ** MK82FN256VDC15
kadonotakashi 0:8fdf9a60065b 5 ** MK82FN256VLL15
kadonotakashi 0:8fdf9a60065b 6 ** MK82FN256VLQ15
kadonotakashi 0:8fdf9a60065b 7 **
kadonotakashi 0:8fdf9a60065b 8 ** Compilers: Keil ARM C/C++ Compiler
kadonotakashi 0:8fdf9a60065b 9 ** Freescale C/C++ for Embedded ARM
kadonotakashi 0:8fdf9a60065b 10 ** GNU C Compiler
kadonotakashi 0:8fdf9a60065b 11 ** IAR ANSI C/C++ Compiler for ARM
kadonotakashi 0:8fdf9a60065b 12 **
kadonotakashi 0:8fdf9a60065b 13 ** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
kadonotakashi 0:8fdf9a60065b 14 ** Version: rev. 1.2, 2015-07-29
kadonotakashi 0:8fdf9a60065b 15 ** Build: b151218
kadonotakashi 0:8fdf9a60065b 16 **
kadonotakashi 0:8fdf9a60065b 17 ** Abstract:
kadonotakashi 0:8fdf9a60065b 18 ** CMSIS Peripheral Access Layer for MK82F25615
kadonotakashi 0:8fdf9a60065b 19 **
kadonotakashi 0:8fdf9a60065b 20 ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
kadonotakashi 0:8fdf9a60065b 21 ** All rights reserved.
kadonotakashi 0:8fdf9a60065b 22 **
kadonotakashi 0:8fdf9a60065b 23 ** Redistribution and use in source and binary forms, with or without modification,
kadonotakashi 0:8fdf9a60065b 24 ** are permitted provided that the following conditions are met:
kadonotakashi 0:8fdf9a60065b 25 **
kadonotakashi 0:8fdf9a60065b 26 ** o Redistributions of source code must retain the above copyright notice, this list
kadonotakashi 0:8fdf9a60065b 27 ** of conditions and the following disclaimer.
kadonotakashi 0:8fdf9a60065b 28 **
kadonotakashi 0:8fdf9a60065b 29 ** o Redistributions in binary form must reproduce the above copyright notice, this
kadonotakashi 0:8fdf9a60065b 30 ** list of conditions and the following disclaimer in the documentation and/or
kadonotakashi 0:8fdf9a60065b 31 ** other materials provided with the distribution.
kadonotakashi 0:8fdf9a60065b 32 **
kadonotakashi 0:8fdf9a60065b 33 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kadonotakashi 0:8fdf9a60065b 34 ** contributors may be used to endorse or promote products derived from this
kadonotakashi 0:8fdf9a60065b 35 ** software without specific prior written permission.
kadonotakashi 0:8fdf9a60065b 36 **
kadonotakashi 0:8fdf9a60065b 37 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kadonotakashi 0:8fdf9a60065b 38 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kadonotakashi 0:8fdf9a60065b 39 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kadonotakashi 0:8fdf9a60065b 40 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kadonotakashi 0:8fdf9a60065b 41 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kadonotakashi 0:8fdf9a60065b 42 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kadonotakashi 0:8fdf9a60065b 43 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kadonotakashi 0:8fdf9a60065b 44 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kadonotakashi 0:8fdf9a60065b 45 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kadonotakashi 0:8fdf9a60065b 46 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kadonotakashi 0:8fdf9a60065b 47 **
kadonotakashi 0:8fdf9a60065b 48 ** http: www.freescale.com
kadonotakashi 0:8fdf9a60065b 49 ** mail: support@freescale.com
kadonotakashi 0:8fdf9a60065b 50 **
kadonotakashi 0:8fdf9a60065b 51 ** Revisions:
kadonotakashi 0:8fdf9a60065b 52 ** - rev. 1.0 (2015-04-09)
kadonotakashi 0:8fdf9a60065b 53 ** Initial version
kadonotakashi 0:8fdf9a60065b 54 ** - rev. 1.1 (2015-05-28)
kadonotakashi 0:8fdf9a60065b 55 ** Update according to the reference manual Rev. 0.
kadonotakashi 0:8fdf9a60065b 56 ** - rev. 1.2 (2015-07-29)
kadonotakashi 0:8fdf9a60065b 57 ** Correction of backward compatibility.
kadonotakashi 0:8fdf9a60065b 58 **
kadonotakashi 0:8fdf9a60065b 59 ** ###################################################################
kadonotakashi 0:8fdf9a60065b 60 */
kadonotakashi 0:8fdf9a60065b 61
kadonotakashi 0:8fdf9a60065b 62 /*!
kadonotakashi 0:8fdf9a60065b 63 * @file MK82F25615.h
kadonotakashi 0:8fdf9a60065b 64 * @version 1.2
kadonotakashi 0:8fdf9a60065b 65 * @date 2015-07-29
kadonotakashi 0:8fdf9a60065b 66 * @brief CMSIS Peripheral Access Layer for MK82F25615
kadonotakashi 0:8fdf9a60065b 67 *
kadonotakashi 0:8fdf9a60065b 68 * CMSIS Peripheral Access Layer for MK82F25615
kadonotakashi 0:8fdf9a60065b 69 */
kadonotakashi 0:8fdf9a60065b 70
kadonotakashi 0:8fdf9a60065b 71 #ifndef _MK82F25615_H_
kadonotakashi 0:8fdf9a60065b 72 #define _MK82F25615_H_ /**< Symbol preventing repeated inclusion */
kadonotakashi 0:8fdf9a60065b 73
kadonotakashi 0:8fdf9a60065b 74 /** Memory map major version (memory maps with equal major version number are
kadonotakashi 0:8fdf9a60065b 75 * compatible) */
kadonotakashi 0:8fdf9a60065b 76 #define MCU_MEM_MAP_VERSION 0x0100U
kadonotakashi 0:8fdf9a60065b 77 /** Memory map minor version */
kadonotakashi 0:8fdf9a60065b 78 #define MCU_MEM_MAP_VERSION_MINOR 0x0002U
kadonotakashi 0:8fdf9a60065b 79
kadonotakashi 0:8fdf9a60065b 80 /**
kadonotakashi 0:8fdf9a60065b 81 * @brief Macro to calculate address of an aliased word in the peripheral
kadonotakashi 0:8fdf9a60065b 82 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
kadonotakashi 0:8fdf9a60065b 83 * 0x400FFFFF).
kadonotakashi 0:8fdf9a60065b 84 * @param Reg Register to access.
kadonotakashi 0:8fdf9a60065b 85 * @param Bit Bit number to access.
kadonotakashi 0:8fdf9a60065b 86 * @return Address of the aliased word in the peripheral bitband area.
kadonotakashi 0:8fdf9a60065b 87 */
kadonotakashi 0:8fdf9a60065b 88 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
kadonotakashi 0:8fdf9a60065b 89 /**
kadonotakashi 0:8fdf9a60065b 90 * @brief Macro to access a single bit of a peripheral register (bit band region
kadonotakashi 0:8fdf9a60065b 91 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
kadonotakashi 0:8fdf9a60065b 92 * be used for peripherals with 32bit access allowed.
kadonotakashi 0:8fdf9a60065b 93 * @param Reg Register to access.
kadonotakashi 0:8fdf9a60065b 94 * @param Bit Bit number to access.
kadonotakashi 0:8fdf9a60065b 95 * @return Value of the targeted bit in the bit band region.
kadonotakashi 0:8fdf9a60065b 96 */
kadonotakashi 0:8fdf9a60065b 97 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
kadonotakashi 0:8fdf9a60065b 98 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
kadonotakashi 0:8fdf9a60065b 99 /**
kadonotakashi 0:8fdf9a60065b 100 * @brief Macro to access a single bit of a peripheral register (bit band region
kadonotakashi 0:8fdf9a60065b 101 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
kadonotakashi 0:8fdf9a60065b 102 * be used for peripherals with 16bit access allowed.
kadonotakashi 0:8fdf9a60065b 103 * @param Reg Register to access.
kadonotakashi 0:8fdf9a60065b 104 * @param Bit Bit number to access.
kadonotakashi 0:8fdf9a60065b 105 * @return Value of the targeted bit in the bit band region.
kadonotakashi 0:8fdf9a60065b 106 */
kadonotakashi 0:8fdf9a60065b 107 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
kadonotakashi 0:8fdf9a60065b 108 /**
kadonotakashi 0:8fdf9a60065b 109 * @brief Macro to access a single bit of a peripheral register (bit band region
kadonotakashi 0:8fdf9a60065b 110 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
kadonotakashi 0:8fdf9a60065b 111 * be used for peripherals with 8bit access allowed.
kadonotakashi 0:8fdf9a60065b 112 * @param Reg Register to access.
kadonotakashi 0:8fdf9a60065b 113 * @param Bit Bit number to access.
kadonotakashi 0:8fdf9a60065b 114 * @return Value of the targeted bit in the bit band region.
kadonotakashi 0:8fdf9a60065b 115 */
kadonotakashi 0:8fdf9a60065b 116 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
kadonotakashi 0:8fdf9a60065b 117
kadonotakashi 0:8fdf9a60065b 118 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 119 -- Interrupt vector numbers
kadonotakashi 0:8fdf9a60065b 120 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 121
kadonotakashi 0:8fdf9a60065b 122 /*!
kadonotakashi 0:8fdf9a60065b 123 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
kadonotakashi 0:8fdf9a60065b 124 * @{
kadonotakashi 0:8fdf9a60065b 125 */
kadonotakashi 0:8fdf9a60065b 126
kadonotakashi 0:8fdf9a60065b 127 /** Interrupt Number Definitions */
kadonotakashi 0:8fdf9a60065b 128 #define NUMBER_OF_INT_VECTORS 123 /**< Number of interrupts in the Vector table */
kadonotakashi 0:8fdf9a60065b 129
kadonotakashi 0:8fdf9a60065b 130 typedef enum IRQn {
kadonotakashi 0:8fdf9a60065b 131 /* Auxiliary constants */
kadonotakashi 0:8fdf9a60065b 132 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
kadonotakashi 0:8fdf9a60065b 133
kadonotakashi 0:8fdf9a60065b 134 /* Core interrupts */
kadonotakashi 0:8fdf9a60065b 135 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
kadonotakashi 0:8fdf9a60065b 136 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
kadonotakashi 0:8fdf9a60065b 137 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
kadonotakashi 0:8fdf9a60065b 138 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
kadonotakashi 0:8fdf9a60065b 139 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
kadonotakashi 0:8fdf9a60065b 140 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
kadonotakashi 0:8fdf9a60065b 141 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
kadonotakashi 0:8fdf9a60065b 142 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
kadonotakashi 0:8fdf9a60065b 143 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
kadonotakashi 0:8fdf9a60065b 144
kadonotakashi 0:8fdf9a60065b 145 /* Device specific interrupts */
kadonotakashi 0:8fdf9a60065b 146 DMA0_DMA16_IRQn = 0, /**< DMA channel 0,16 transfer complete */
kadonotakashi 0:8fdf9a60065b 147 DMA1_DMA17_IRQn = 1, /**< DMA channel 1,17 transfer complete */
kadonotakashi 0:8fdf9a60065b 148 DMA2_DMA18_IRQn = 2, /**< DMA channel 2,18 transfer complete */
kadonotakashi 0:8fdf9a60065b 149 DMA3_DMA19_IRQn = 3, /**< DMA channel 3,19 transfer complete */
kadonotakashi 0:8fdf9a60065b 150 DMA4_DMA20_IRQn = 4, /**< DMA channel 4,20 transfer complete */
kadonotakashi 0:8fdf9a60065b 151 DMA5_DMA21_IRQn = 5, /**< DMA channel 5,21 transfer complete */
kadonotakashi 0:8fdf9a60065b 152 DMA6_DMA22_IRQn = 6, /**< DMA channel 6,22 transfer complete */
kadonotakashi 0:8fdf9a60065b 153 DMA7_DMA23_IRQn = 7, /**< DMA channel 7,23 transfer complete */
kadonotakashi 0:8fdf9a60065b 154 DMA8_DMA24_IRQn = 8, /**< DMA channel 8,24 transfer complete */
kadonotakashi 0:8fdf9a60065b 155 DMA9_DMA25_IRQn = 9, /**< DMA channel 9,25 transfer complete */
kadonotakashi 0:8fdf9a60065b 156 DMA10_DMA26_IRQn = 10, /**< DMA channel 10,26 transfer complete */
kadonotakashi 0:8fdf9a60065b 157 DMA11_DMA27_IRQn = 11, /**< DMA channel 11,27 transfer complete */
kadonotakashi 0:8fdf9a60065b 158 DMA12_DMA28_IRQn = 12, /**< DMA channel 12,28 transfer complete */
kadonotakashi 0:8fdf9a60065b 159 DMA13_DMA29_IRQn = 13, /**< DMA channel 13,29 transfer complete */
kadonotakashi 0:8fdf9a60065b 160 DMA14_DMA30_IRQn = 14, /**< DMA channel 14,30 transfer complete */
kadonotakashi 0:8fdf9a60065b 161 DMA15_DMA31_IRQn = 15, /**< DMA channel 15,31 transfer complete */
kadonotakashi 0:8fdf9a60065b 162 DMA_Error_IRQn = 16, /**< DMA channel 0 - 31 error */
kadonotakashi 0:8fdf9a60065b 163 MCM_IRQn = 17, /**< MCM normal interrupt */
kadonotakashi 0:8fdf9a60065b 164 FTFA_IRQn = 18, /**< FTFA command complete */
kadonotakashi 0:8fdf9a60065b 165 Read_Collision_IRQn = 19, /**< FTFA read collision */
kadonotakashi 0:8fdf9a60065b 166 LVD_LVW_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */
kadonotakashi 0:8fdf9a60065b 167 LLWU_IRQn = 21, /**< Low leakage wakeup unit */
kadonotakashi 0:8fdf9a60065b 168 WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */
kadonotakashi 0:8fdf9a60065b 169 TRNG0_IRQn = 23, /**< True randon number generator */
kadonotakashi 0:8fdf9a60065b 170 I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */
kadonotakashi 0:8fdf9a60065b 171 I2C1_IRQn = 25, /**< Inter-integrated circuit 1 */
kadonotakashi 0:8fdf9a60065b 172 SPI0_IRQn = 26, /**< Serial peripheral Interface 0 */
kadonotakashi 0:8fdf9a60065b 173 SPI1_IRQn = 27, /**< Serial peripheral Interface 1 */
kadonotakashi 0:8fdf9a60065b 174 I2S0_Tx_IRQn = 28, /**< Integrated interchip sound 0 transmit interrupt */
kadonotakashi 0:8fdf9a60065b 175 I2S0_Rx_IRQn = 29, /**< Integrated interchip sound 0 receive interrupt */
kadonotakashi 0:8fdf9a60065b 176 LPUART0_IRQn = 30, /**< LPUART0 receive/transmit/error interrupt */
kadonotakashi 0:8fdf9a60065b 177 LPUART1_IRQn = 31, /**< LPUART1 receive/transmit/error interrupt */
kadonotakashi 0:8fdf9a60065b 178 LPUART2_IRQn = 32, /**< LPUART2 receive/transmit/error interrupt */
kadonotakashi 0:8fdf9a60065b 179 LPUART3_IRQn = 33, /**< LPUART3 receive/transmit/error interrupt */
kadonotakashi 0:8fdf9a60065b 180 LPUART4_IRQn = 34, /**< LPUART4 receive/transmit/error interrupt */
kadonotakashi 0:8fdf9a60065b 181 Reserved51_IRQn = 35, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 182 Reserved52_IRQn = 36, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 183 EMVSIM0_IRQn = 37, /**< EMVSIM0 common interrupt */
kadonotakashi 0:8fdf9a60065b 184 EMVSIM1_IRQn = 38, /**< EMVSIM1 common interrupt */
kadonotakashi 0:8fdf9a60065b 185 ADC0_IRQn = 39, /**< Analog-to-digital converter 0 */
kadonotakashi 0:8fdf9a60065b 186 CMP0_IRQn = 40, /**< Comparator 0 */
kadonotakashi 0:8fdf9a60065b 187 CMP1_IRQn = 41, /**< Comparator 1 */
kadonotakashi 0:8fdf9a60065b 188 FTM0_IRQn = 42, /**< FlexTimer module 0 fault, overflow and channels interrupt */
kadonotakashi 0:8fdf9a60065b 189 FTM1_IRQn = 43, /**< FlexTimer module 1 fault, overflow and channels interrupt */
kadonotakashi 0:8fdf9a60065b 190 FTM2_IRQn = 44, /**< FlexTimer module 2 fault, overflow and channels interrupt */
kadonotakashi 0:8fdf9a60065b 191 CMT_IRQn = 45, /**< Carrier modulator transmitter */
kadonotakashi 0:8fdf9a60065b 192 RTC_IRQn = 46, /**< Real time clock */
kadonotakashi 0:8fdf9a60065b 193 RTC_Seconds_IRQn = 47, /**< Real time clock seconds */
kadonotakashi 0:8fdf9a60065b 194 PIT0CH0_IRQn = 48, /**< Periodic interrupt timer 0 channel 0 */
kadonotakashi 0:8fdf9a60065b 195 PIT0CH1_IRQn = 49, /**< Periodic interrupt timer 0 channel 1 */
kadonotakashi 0:8fdf9a60065b 196 PIT0CH2_IRQn = 50, /**< Periodic interrupt timer 0 channel 2 */
kadonotakashi 0:8fdf9a60065b 197 PIT0CH3_IRQn = 51, /**< Periodic interrupt timer 0 channel 3 */
kadonotakashi 0:8fdf9a60065b 198 PDB0_IRQn = 52, /**< Programmable delay block */
kadonotakashi 0:8fdf9a60065b 199 USB0_IRQn = 53, /**< USB OTG interrupt */
kadonotakashi 0:8fdf9a60065b 200 USBDCD_IRQn = 54, /**< USB charger detect */
kadonotakashi 0:8fdf9a60065b 201 Reserved71_IRQn = 55, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 202 DAC0_IRQn = 56, /**< Digital-to-analog converter 0 */
kadonotakashi 0:8fdf9a60065b 203 MCG_IRQn = 57, /**< Multipurpose clock generator */
kadonotakashi 0:8fdf9a60065b 204 LPTMR0_LPTMR1_IRQn = 58, /**< Single interrupt vector for Low Power Timer 0 and 1 */
kadonotakashi 0:8fdf9a60065b 205 PORTA_IRQn = 59, /**< Port A pin detect interrupt */
kadonotakashi 0:8fdf9a60065b 206 PORTB_IRQn = 60, /**< Port B pin detect interrupt */
kadonotakashi 0:8fdf9a60065b 207 PORTC_IRQn = 61, /**< Port C pin detect interrupt */
kadonotakashi 0:8fdf9a60065b 208 PORTD_IRQn = 62, /**< Port D pin detect interrupt */
kadonotakashi 0:8fdf9a60065b 209 PORTE_IRQn = 63, /**< Port E pin detect interrupt */
kadonotakashi 0:8fdf9a60065b 210 SWI_IRQn = 64, /**< Software interrupt */
kadonotakashi 0:8fdf9a60065b 211 SPI2_IRQn = 65, /**< Serial peripheral Interface 2 */
kadonotakashi 0:8fdf9a60065b 212 Reserved82_IRQn = 66, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 213 Reserved83_IRQn = 67, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 214 Reserved84_IRQn = 68, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 215 Reserved85_IRQn = 69, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 216 FLEXIO0_IRQn = 70, /**< FLEXIO0 */
kadonotakashi 0:8fdf9a60065b 217 FTM3_IRQn = 71, /**< FlexTimer module 3 fault, overflow and channels interrupt */
kadonotakashi 0:8fdf9a60065b 218 Reserved88_IRQn = 72, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 219 Reserved89_IRQn = 73, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 220 I2C2_IRQn = 74, /**< Inter-integrated circuit 2 */
kadonotakashi 0:8fdf9a60065b 221 Reserved91_IRQn = 75, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 222 Reserved92_IRQn = 76, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 223 Reserved93_IRQn = 77, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 224 Reserved94_IRQn = 78, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 225 Reserved95_IRQn = 79, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 226 Reserved96_IRQn = 80, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 227 SDHC_IRQn = 81, /**< Secured digital host controller */
kadonotakashi 0:8fdf9a60065b 228 Reserved98_IRQn = 82, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 229 Reserved99_IRQn = 83, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 230 Reserved100_IRQn = 84, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 231 Reserved101_IRQn = 85, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 232 Reserved102_IRQn = 86, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 233 TSI0_IRQn = 87, /**< Touch Sensing Input */
kadonotakashi 0:8fdf9a60065b 234 TPM1_IRQn = 88, /**< TPM1 single interrupt vector for all sources */
kadonotakashi 0:8fdf9a60065b 235 TPM2_IRQn = 89, /**< TPM2 single interrupt vector for all sources */
kadonotakashi 0:8fdf9a60065b 236 Reserved106_IRQn = 90, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 237 I2C3_IRQn = 91, /**< Inter-integrated circuit 3 */
kadonotakashi 0:8fdf9a60065b 238 Reserved108_IRQn = 92, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 239 Reserved109_IRQn = 93, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 240 Reserved110_IRQn = 94, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 241 Reserved111_IRQn = 95, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 242 Reserved112_IRQn = 96, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 243 Reserved113_IRQn = 97, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 244 Reserved114_IRQn = 98, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 245 Reserved115_IRQn = 99, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 246 QuadSPI0_IRQn = 100, /**< qspi */
kadonotakashi 0:8fdf9a60065b 247 Reserved117_IRQn = 101, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 248 Reserved118_IRQn = 102, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 249 Reserved119_IRQn = 103, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 250 LTC0_IRQn = 104, /**< LP Trusted Cryptography */
kadonotakashi 0:8fdf9a60065b 251 Reserved121_IRQn = 105, /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 252 Reserved122_IRQn = 106 /**< Reserved interrupt */
kadonotakashi 0:8fdf9a60065b 253 } IRQn_Type;
kadonotakashi 0:8fdf9a60065b 254
kadonotakashi 0:8fdf9a60065b 255 /*!
kadonotakashi 0:8fdf9a60065b 256 * @}
kadonotakashi 0:8fdf9a60065b 257 */ /* end of group Interrupt_vector_numbers */
kadonotakashi 0:8fdf9a60065b 258
kadonotakashi 0:8fdf9a60065b 259
kadonotakashi 0:8fdf9a60065b 260 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 261 -- Cortex M4 Core Configuration
kadonotakashi 0:8fdf9a60065b 262 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 263
kadonotakashi 0:8fdf9a60065b 264 /*!
kadonotakashi 0:8fdf9a60065b 265 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
kadonotakashi 0:8fdf9a60065b 266 * @{
kadonotakashi 0:8fdf9a60065b 267 */
kadonotakashi 0:8fdf9a60065b 268
kadonotakashi 0:8fdf9a60065b 269 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
kadonotakashi 0:8fdf9a60065b 270 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
kadonotakashi 0:8fdf9a60065b 271 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
kadonotakashi 0:8fdf9a60065b 272 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
kadonotakashi 0:8fdf9a60065b 273
kadonotakashi 0:8fdf9a60065b 274 #include "core_cm4.h" /* Core Peripheral Access Layer */
kadonotakashi 0:8fdf9a60065b 275 #include "system_MK82F25615.h" /* Device specific configuration file */
kadonotakashi 0:8fdf9a60065b 276
kadonotakashi 0:8fdf9a60065b 277 /*!
kadonotakashi 0:8fdf9a60065b 278 * @}
kadonotakashi 0:8fdf9a60065b 279 */ /* end of group Cortex_Core_Configuration */
kadonotakashi 0:8fdf9a60065b 280
kadonotakashi 0:8fdf9a60065b 281
kadonotakashi 0:8fdf9a60065b 282 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 283 -- Mapping Information
kadonotakashi 0:8fdf9a60065b 284 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 285
kadonotakashi 0:8fdf9a60065b 286 /*!
kadonotakashi 0:8fdf9a60065b 287 * @addtogroup Mapping_Information Mapping Information
kadonotakashi 0:8fdf9a60065b 288 * @{
kadonotakashi 0:8fdf9a60065b 289 */
kadonotakashi 0:8fdf9a60065b 290
kadonotakashi 0:8fdf9a60065b 291 /** Mapping Information */
kadonotakashi 0:8fdf9a60065b 292 /*!
kadonotakashi 0:8fdf9a60065b 293 * @addtogroup edma_request
kadonotakashi 0:8fdf9a60065b 294 * @{
kadonotakashi 0:8fdf9a60065b 295 */
kadonotakashi 0:8fdf9a60065b 296
kadonotakashi 0:8fdf9a60065b 297 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 298 * Definitions
kadonotakashi 0:8fdf9a60065b 299 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 300
kadonotakashi 0:8fdf9a60065b 301 /*!
kadonotakashi 0:8fdf9a60065b 302 * @brief Structure for the DMA hardware request
kadonotakashi 0:8fdf9a60065b 303 *
kadonotakashi 0:8fdf9a60065b 304 * Defines the structure for the DMA hardware request collections. The user can configure the
kadonotakashi 0:8fdf9a60065b 305 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
kadonotakashi 0:8fdf9a60065b 306 * of the hardware request varies according to the to SoC.
kadonotakashi 0:8fdf9a60065b 307 */
kadonotakashi 0:8fdf9a60065b 308 typedef enum _dma_request_source
kadonotakashi 0:8fdf9a60065b 309 {
kadonotakashi 0:8fdf9a60065b 310 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
kadonotakashi 0:8fdf9a60065b 311 kDmaRequestMux0TSI0 = 1|0x100U, /**< TSI0. */
kadonotakashi 0:8fdf9a60065b 312 kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */
kadonotakashi 0:8fdf9a60065b 313 kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */
kadonotakashi 0:8fdf9a60065b 314 kDmaRequestMux0LPUART1Rx = 4|0x100U, /**< LPUART1 Receive. */
kadonotakashi 0:8fdf9a60065b 315 kDmaRequestMux0LPUART1Tx = 5|0x100U, /**< LPUART1 Transmit. */
kadonotakashi 0:8fdf9a60065b 316 kDmaRequestMux0LPUART2Rx = 6|0x100U, /**< LPUART2 Receive. */
kadonotakashi 0:8fdf9a60065b 317 kDmaRequestMux0LPUART2Tx = 7|0x100U, /**< LPUART2 Transmit. */
kadonotakashi 0:8fdf9a60065b 318 kDmaRequestMux0LPUART3Rx = 8|0x100U, /**< LPUART3 Receive. */
kadonotakashi 0:8fdf9a60065b 319 kDmaRequestMux0LPUART3Tx = 9|0x100U, /**< LPUART3 Transmit. */
kadonotakashi 0:8fdf9a60065b 320 kDmaRequestMux0LPUART4Rx = 10|0x100U, /**< LPUART4 Receive. */
kadonotakashi 0:8fdf9a60065b 321 kDmaRequestMux0LPUART4Tx = 11|0x100U, /**< LPUART4 Transmit. */
kadonotakashi 0:8fdf9a60065b 322 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
kadonotakashi 0:8fdf9a60065b 323 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
kadonotakashi 0:8fdf9a60065b 324 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
kadonotakashi 0:8fdf9a60065b 325 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
kadonotakashi 0:8fdf9a60065b 326 kDmaRequestMux0SPI1Rx = 16|0x100U, /**< SPI1 Receive. */
kadonotakashi 0:8fdf9a60065b 327 kDmaRequestMux0SPI1Tx = 17|0x100U, /**< SPI1 Transmit. */
kadonotakashi 0:8fdf9a60065b 328 kDmaRequestMux0I2C0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
kadonotakashi 0:8fdf9a60065b 329 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0 and I2C3. */
kadonotakashi 0:8fdf9a60065b 330 kDmaRequestMux0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
kadonotakashi 0:8fdf9a60065b 331 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
kadonotakashi 0:8fdf9a60065b 332 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
kadonotakashi 0:8fdf9a60065b 333 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
kadonotakashi 0:8fdf9a60065b 334 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
kadonotakashi 0:8fdf9a60065b 335 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
kadonotakashi 0:8fdf9a60065b 336 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
kadonotakashi 0:8fdf9a60065b 337 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
kadonotakashi 0:8fdf9a60065b 338 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
kadonotakashi 0:8fdf9a60065b 339 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
kadonotakashi 0:8fdf9a60065b 340 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
kadonotakashi 0:8fdf9a60065b 341 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
kadonotakashi 0:8fdf9a60065b 342 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
kadonotakashi 0:8fdf9a60065b 343 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
kadonotakashi 0:8fdf9a60065b 344 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
kadonotakashi 0:8fdf9a60065b 345 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
kadonotakashi 0:8fdf9a60065b 346 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
kadonotakashi 0:8fdf9a60065b 347 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
kadonotakashi 0:8fdf9a60065b 348 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
kadonotakashi 0:8fdf9a60065b 349 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
kadonotakashi 0:8fdf9a60065b 350 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
kadonotakashi 0:8fdf9a60065b 351 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
kadonotakashi 0:8fdf9a60065b 352 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */
kadonotakashi 0:8fdf9a60065b 353 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */
kadonotakashi 0:8fdf9a60065b 354 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
kadonotakashi 0:8fdf9a60065b 355 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
kadonotakashi 0:8fdf9a60065b 356 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
kadonotakashi 0:8fdf9a60065b 357 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
kadonotakashi 0:8fdf9a60065b 358 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
kadonotakashi 0:8fdf9a60065b 359 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
kadonotakashi 0:8fdf9a60065b 360 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
kadonotakashi 0:8fdf9a60065b 361 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
kadonotakashi 0:8fdf9a60065b 362 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
kadonotakashi 0:8fdf9a60065b 363 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
kadonotakashi 0:8fdf9a60065b 364 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
kadonotakashi 0:8fdf9a60065b 365 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
kadonotakashi 0:8fdf9a60065b 366 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
kadonotakashi 0:8fdf9a60065b 367 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
kadonotakashi 0:8fdf9a60065b 368 kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
kadonotakashi 0:8fdf9a60065b 369 kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */
kadonotakashi 0:8fdf9a60065b 370 kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */
kadonotakashi 0:8fdf9a60065b 371 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
kadonotakashi 0:8fdf9a60065b 372 kDmaRequestMux0SPI2Rx = 58|0x100U, /**< SPI2 Receive. */
kadonotakashi 0:8fdf9a60065b 373 kDmaRequestMux0SPI2Tx = 59|0x100U, /**< SPI2 Transmit. */
kadonotakashi 0:8fdf9a60065b 374 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
kadonotakashi 0:8fdf9a60065b 375 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
kadonotakashi 0:8fdf9a60065b 376 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
kadonotakashi 0:8fdf9a60065b 377 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
kadonotakashi 0:8fdf9a60065b 378 kDmaRequestMux0Group1Disable = 0|0x200U, /**< DMAMUX TriggerDisabled. */
kadonotakashi 0:8fdf9a60065b 379 kDmaRequestMux0Group1FlexIO0Channel0 = 1|0x200U, /**< FLEXIO0. */
kadonotakashi 0:8fdf9a60065b 380 kDmaRequestMux0Group1FlexIO0Channel1 = 2|0x200U, /**< FLEXIO0. */
kadonotakashi 0:8fdf9a60065b 381 kDmaRequestMux0Group1FlexIO0Channel2 = 3|0x200U, /**< FLEXIO0. */
kadonotakashi 0:8fdf9a60065b 382 kDmaRequestMux0Group1FlexIO0Channel3 = 4|0x200U, /**< FLEXIO0. */
kadonotakashi 0:8fdf9a60065b 383 kDmaRequestMux0Group1FlexIO0Channel4 = 5|0x200U, /**< FLEXIO0. */
kadonotakashi 0:8fdf9a60065b 384 kDmaRequestMux0Group1FlexIO0Channel5 = 6|0x200U, /**< FLEXIO0. */
kadonotakashi 0:8fdf9a60065b 385 kDmaRequestMux0Group1FlexIO0Channel6 = 7|0x200U, /**< FLEXIO0. */
kadonotakashi 0:8fdf9a60065b 386 kDmaRequestMux0Group1FlexIO0Channel7 = 8|0x200U, /**< FLEXIO0. */
kadonotakashi 0:8fdf9a60065b 387 kDmaRequestMux0Group1Reserved9 = 9|0x200U, /**< Reserved9 */
kadonotakashi 0:8fdf9a60065b 388 kDmaRequestMux0Group1Reserved10 = 10|0x200U, /**< Reserved10 */
kadonotakashi 0:8fdf9a60065b 389 kDmaRequestMux0Group1Reserved11 = 11|0x200U, /**< Reserved11 */
kadonotakashi 0:8fdf9a60065b 390 kDmaRequestMux0Group1Reserved12 = 12|0x200U, /**< Reserved12 */
kadonotakashi 0:8fdf9a60065b 391 kDmaRequestMux0Group1Reserved13 = 13|0x200U, /**< Reserved13 */
kadonotakashi 0:8fdf9a60065b 392 kDmaRequestMux0Group1Reserved14 = 14|0x200U, /**< Reserved14 */
kadonotakashi 0:8fdf9a60065b 393 kDmaRequestMux0Group1Reserved15 = 15|0x200U, /**< Reserved15 */
kadonotakashi 0:8fdf9a60065b 394 kDmaRequestMux0Group1Reserved16 = 16|0x200U, /**< Reserved16 */
kadonotakashi 0:8fdf9a60065b 395 kDmaRequestMux0Group1LTC0InputFIFO = 17|0x200U, /**< LTC0 Input FIFO. */
kadonotakashi 0:8fdf9a60065b 396 kDmaRequestMux0Group1LTC0OutputFIFO = 18|0x200U, /**< LTC0 Output FIFO. */
kadonotakashi 0:8fdf9a60065b 397 kDmaRequestMux0Group1LTC0PKHA = 19|0x200U, /**< LTC0 PKHA. */
kadonotakashi 0:8fdf9a60065b 398 kDmaRequestMux0Group1EMVSIM0Rx = 20|0x200U, /**< EMVSIM0 Receive. */
kadonotakashi 0:8fdf9a60065b 399 kDmaRequestMux0Group1EMVSIM0Tx = 21|0x200U, /**< EMVSIM0 Transmit. */
kadonotakashi 0:8fdf9a60065b 400 kDmaRequestMux0Group1EMVSIM1Rx = 22|0x200U, /**< EMVSIM1 Receive. */
kadonotakashi 0:8fdf9a60065b 401 kDmaRequestMux0Group1EMVSIM1Tx = 23|0x200U, /**< EMVSIM1 Transmit. */
kadonotakashi 0:8fdf9a60065b 402 kDmaRequestMux0Group1QSPI0Rx = 24|0x200U, /**< QuadSPI0 Receive. */
kadonotakashi 0:8fdf9a60065b 403 kDmaRequestMux0Group1QSPI0Tx = 25|0x200U, /**< QuadSPI0 Transmit. */
kadonotakashi 0:8fdf9a60065b 404 kDmaRequestMux0Group1Reserved26 = 26|0x200U, /**< Reserved26 */
kadonotakashi 0:8fdf9a60065b 405 kDmaRequestMux0Group1Reserved27 = 27|0x200U, /**< Reserved27 */
kadonotakashi 0:8fdf9a60065b 406 kDmaRequestMux0Group1SPI0Rx = 28|0x200U, /**< SPI0 Receive. */
kadonotakashi 0:8fdf9a60065b 407 kDmaRequestMux0Group1SPI0Tx = 29|0x200U, /**< SPI0 Transmit. */
kadonotakashi 0:8fdf9a60065b 408 kDmaRequestMux0Group1SPI1Rx = 30|0x200U, /**< SPI1 Receive. */
kadonotakashi 0:8fdf9a60065b 409 kDmaRequestMux0Group1SPI1Tx = 31|0x200U, /**< SPI1 Transmit. */
kadonotakashi 0:8fdf9a60065b 410 kDmaRequestMux0Group1Reserved32 = 32|0x200U, /**< Reserved32 */
kadonotakashi 0:8fdf9a60065b 411 kDmaRequestMux0Group1Reserved33 = 33|0x200U, /**< Reserved33 */
kadonotakashi 0:8fdf9a60065b 412 kDmaRequestMux0Group1Reserved34 = 34|0x200U, /**< Reserved34 */
kadonotakashi 0:8fdf9a60065b 413 kDmaRequestMux0Group1Reserved35 = 35|0x200U, /**< Reserved35 */
kadonotakashi 0:8fdf9a60065b 414 kDmaRequestMux0Group1Reserved36 = 36|0x200U, /**< Reserved36 */
kadonotakashi 0:8fdf9a60065b 415 kDmaRequestMux0Group1Reserved37 = 37|0x200U, /**< Reserved37 */
kadonotakashi 0:8fdf9a60065b 416 kDmaRequestMux0Group1Reserved38 = 38|0x200U, /**< Reserved38 */
kadonotakashi 0:8fdf9a60065b 417 kDmaRequestMux0Group1Reserved39 = 39|0x200U, /**< Reserved39 */
kadonotakashi 0:8fdf9a60065b 418 kDmaRequestMux0Group1Reserved40 = 40|0x200U, /**< Reserved40 */
kadonotakashi 0:8fdf9a60065b 419 kDmaRequestMux0Group1Reserved41 = 41|0x200U, /**< Reserved41 */
kadonotakashi 0:8fdf9a60065b 420 kDmaRequestMux0Group1TPM1Channel0 = 42|0x200U, /**< TPM1 C0V. */
kadonotakashi 0:8fdf9a60065b 421 kDmaRequestMux0Group1TPM1Channel1 = 43|0x200U, /**< TPM1 C1V. */
kadonotakashi 0:8fdf9a60065b 422 kDmaRequestMux0Group1TPM2Channel0 = 44|0x200U, /**< TPM2 C0V. */
kadonotakashi 0:8fdf9a60065b 423 kDmaRequestMux0Group1TPM2Channel1 = 45|0x200U, /**< TPM2 C1V. */
kadonotakashi 0:8fdf9a60065b 424 kDmaRequestMux0Group1Reserved46 = 46|0x200U, /**< Reserved46 */
kadonotakashi 0:8fdf9a60065b 425 kDmaRequestMux0Group1Reserved47 = 47|0x200U, /**< Reserved47 */
kadonotakashi 0:8fdf9a60065b 426 kDmaRequestMux0Group1Reserved48 = 48|0x200U, /**< Reserved48 */
kadonotakashi 0:8fdf9a60065b 427 kDmaRequestMux0Group1Reserved49 = 49|0x200U, /**< Reserved49 */
kadonotakashi 0:8fdf9a60065b 428 kDmaRequestMux0Group1Reserved50 = 50|0x200U, /**< Reserved50 */
kadonotakashi 0:8fdf9a60065b 429 kDmaRequestMux0Group1Reserved51 = 51|0x200U, /**< Reserved51 */
kadonotakashi 0:8fdf9a60065b 430 kDmaRequestMux0Group1Reserved52 = 52|0x200U, /**< Reserved52 */
kadonotakashi 0:8fdf9a60065b 431 kDmaRequestMux0Group1Reserved53 = 53|0x200U, /**< Reserved53 */
kadonotakashi 0:8fdf9a60065b 432 kDmaRequestMux0Group1Reserved54 = 54|0x200U, /**< Reserved54 */
kadonotakashi 0:8fdf9a60065b 433 kDmaRequestMux0Group1TPM1Overflow = 55|0x200U, /**< TPM1. */
kadonotakashi 0:8fdf9a60065b 434 kDmaRequestMux0Group1TPM2Overflow = 56|0x200U, /**< TPM2. */
kadonotakashi 0:8fdf9a60065b 435 kDmaRequestMux0Group1Reserved57 = 57|0x200U, /**< Reserved57 */
kadonotakashi 0:8fdf9a60065b 436 kDmaRequestMux0Group1Reserved58 = 58|0x200U, /**< Reserved58 */
kadonotakashi 0:8fdf9a60065b 437 kDmaRequestMux0Group1Reserved59 = 59|0x200U, /**< Reserved59 */
kadonotakashi 0:8fdf9a60065b 438 kDmaRequestMux0Group1AlwaysOn60 = 60|0x200U, /**< DMAMUX Always Enabled slot. */
kadonotakashi 0:8fdf9a60065b 439 kDmaRequestMux0Group1AlwaysOn61 = 61|0x200U, /**< DMAMUX Always Enabled slot. */
kadonotakashi 0:8fdf9a60065b 440 kDmaRequestMux0Group1AlwaysOn62 = 62|0x200U, /**< DMAMUX Always Enabled slot. */
kadonotakashi 0:8fdf9a60065b 441 kDmaRequestMux0Group1AlwaysOn63 = 63|0x200U, /**< DMAMUX Always Enabled slot. */
kadonotakashi 0:8fdf9a60065b 442 } dma_request_source_t;
kadonotakashi 0:8fdf9a60065b 443
kadonotakashi 0:8fdf9a60065b 444 /* @} */
kadonotakashi 0:8fdf9a60065b 445
kadonotakashi 0:8fdf9a60065b 446
kadonotakashi 0:8fdf9a60065b 447 /*!
kadonotakashi 0:8fdf9a60065b 448 * @}
kadonotakashi 0:8fdf9a60065b 449 */ /* end of group Mapping_Information */
kadonotakashi 0:8fdf9a60065b 450
kadonotakashi 0:8fdf9a60065b 451
kadonotakashi 0:8fdf9a60065b 452 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 453 -- Device Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 454 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 455
kadonotakashi 0:8fdf9a60065b 456 /*!
kadonotakashi 0:8fdf9a60065b 457 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 458 * @{
kadonotakashi 0:8fdf9a60065b 459 */
kadonotakashi 0:8fdf9a60065b 460
kadonotakashi 0:8fdf9a60065b 461
kadonotakashi 0:8fdf9a60065b 462 /*
kadonotakashi 0:8fdf9a60065b 463 ** Start of section using anonymous unions
kadonotakashi 0:8fdf9a60065b 464 */
kadonotakashi 0:8fdf9a60065b 465
kadonotakashi 0:8fdf9a60065b 466 #if defined(__ARMCC_VERSION)
kadonotakashi 0:8fdf9a60065b 467 #pragma push
kadonotakashi 0:8fdf9a60065b 468 #pragma anon_unions
kadonotakashi 0:8fdf9a60065b 469 #elif defined(__CWCC__)
kadonotakashi 0:8fdf9a60065b 470 #pragma push
kadonotakashi 0:8fdf9a60065b 471 #pragma cpp_extensions on
kadonotakashi 0:8fdf9a60065b 472 #elif defined(__GNUC__)
kadonotakashi 0:8fdf9a60065b 473 /* anonymous unions are enabled by default */
kadonotakashi 0:8fdf9a60065b 474 #elif defined(__IAR_SYSTEMS_ICC__)
kadonotakashi 0:8fdf9a60065b 475 #pragma language=extended
kadonotakashi 0:8fdf9a60065b 476 #else
kadonotakashi 0:8fdf9a60065b 477 #error Not supported compiler type
kadonotakashi 0:8fdf9a60065b 478 #endif
kadonotakashi 0:8fdf9a60065b 479
kadonotakashi 0:8fdf9a60065b 480 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 481 -- ADC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 482 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 483
kadonotakashi 0:8fdf9a60065b 484 /*!
kadonotakashi 0:8fdf9a60065b 485 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 486 * @{
kadonotakashi 0:8fdf9a60065b 487 */
kadonotakashi 0:8fdf9a60065b 488
kadonotakashi 0:8fdf9a60065b 489 /** ADC - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 490 typedef struct {
kadonotakashi 0:8fdf9a60065b 491 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 492 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 493 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 494 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 495 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 496 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
kadonotakashi 0:8fdf9a60065b 497 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 498 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 499 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
kadonotakashi 0:8fdf9a60065b 500 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
kadonotakashi 0:8fdf9a60065b 501 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
kadonotakashi 0:8fdf9a60065b 502 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 503 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
kadonotakashi 0:8fdf9a60065b 504 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
kadonotakashi 0:8fdf9a60065b 505 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
kadonotakashi 0:8fdf9a60065b 506 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
kadonotakashi 0:8fdf9a60065b 507 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
kadonotakashi 0:8fdf9a60065b 508 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
kadonotakashi 0:8fdf9a60065b 509 uint8_t RESERVED_0[4];
kadonotakashi 0:8fdf9a60065b 510 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
kadonotakashi 0:8fdf9a60065b 511 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
kadonotakashi 0:8fdf9a60065b 512 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
kadonotakashi 0:8fdf9a60065b 513 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
kadonotakashi 0:8fdf9a60065b 514 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
kadonotakashi 0:8fdf9a60065b 515 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
kadonotakashi 0:8fdf9a60065b 516 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
kadonotakashi 0:8fdf9a60065b 517 } ADC_Type;
kadonotakashi 0:8fdf9a60065b 518
kadonotakashi 0:8fdf9a60065b 519 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 520 -- ADC Register Masks
kadonotakashi 0:8fdf9a60065b 521 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 522
kadonotakashi 0:8fdf9a60065b 523 /*!
kadonotakashi 0:8fdf9a60065b 524 * @addtogroup ADC_Register_Masks ADC Register Masks
kadonotakashi 0:8fdf9a60065b 525 * @{
kadonotakashi 0:8fdf9a60065b 526 */
kadonotakashi 0:8fdf9a60065b 527
kadonotakashi 0:8fdf9a60065b 528 /*! @name SC1 - ADC Status and Control Registers 1 */
kadonotakashi 0:8fdf9a60065b 529 #define ADC_SC1_ADCH_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 530 #define ADC_SC1_ADCH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 531 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
kadonotakashi 0:8fdf9a60065b 532 #define ADC_SC1_DIFF_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 533 #define ADC_SC1_DIFF_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 534 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
kadonotakashi 0:8fdf9a60065b 535 #define ADC_SC1_AIEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 536 #define ADC_SC1_AIEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 537 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
kadonotakashi 0:8fdf9a60065b 538 #define ADC_SC1_COCO_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 539 #define ADC_SC1_COCO_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 540 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
kadonotakashi 0:8fdf9a60065b 541
kadonotakashi 0:8fdf9a60065b 542 /* The count of ADC_SC1 */
kadonotakashi 0:8fdf9a60065b 543 #define ADC_SC1_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 544
kadonotakashi 0:8fdf9a60065b 545 /*! @name CFG1 - ADC Configuration Register 1 */
kadonotakashi 0:8fdf9a60065b 546 #define ADC_CFG1_ADICLK_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 547 #define ADC_CFG1_ADICLK_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 548 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
kadonotakashi 0:8fdf9a60065b 549 #define ADC_CFG1_MODE_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 550 #define ADC_CFG1_MODE_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 551 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
kadonotakashi 0:8fdf9a60065b 552 #define ADC_CFG1_ADLSMP_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 553 #define ADC_CFG1_ADLSMP_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 554 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
kadonotakashi 0:8fdf9a60065b 555 #define ADC_CFG1_ADIV_MASK (0x60U)
kadonotakashi 0:8fdf9a60065b 556 #define ADC_CFG1_ADIV_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 557 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
kadonotakashi 0:8fdf9a60065b 558 #define ADC_CFG1_ADLPC_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 559 #define ADC_CFG1_ADLPC_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 560 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
kadonotakashi 0:8fdf9a60065b 561
kadonotakashi 0:8fdf9a60065b 562 /*! @name CFG2 - ADC Configuration Register 2 */
kadonotakashi 0:8fdf9a60065b 563 #define ADC_CFG2_ADLSTS_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 564 #define ADC_CFG2_ADLSTS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 565 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
kadonotakashi 0:8fdf9a60065b 566 #define ADC_CFG2_ADHSC_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 567 #define ADC_CFG2_ADHSC_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 568 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
kadonotakashi 0:8fdf9a60065b 569 #define ADC_CFG2_ADACKEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 570 #define ADC_CFG2_ADACKEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 571 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
kadonotakashi 0:8fdf9a60065b 572 #define ADC_CFG2_MUXSEL_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 573 #define ADC_CFG2_MUXSEL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 574 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
kadonotakashi 0:8fdf9a60065b 575
kadonotakashi 0:8fdf9a60065b 576 /*! @name R - ADC Data Result Register */
kadonotakashi 0:8fdf9a60065b 577 #define ADC_R_D_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 578 #define ADC_R_D_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 579 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
kadonotakashi 0:8fdf9a60065b 580
kadonotakashi 0:8fdf9a60065b 581 /* The count of ADC_R */
kadonotakashi 0:8fdf9a60065b 582 #define ADC_R_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 583
kadonotakashi 0:8fdf9a60065b 584 /*! @name CV1 - Compare Value Registers */
kadonotakashi 0:8fdf9a60065b 585 #define ADC_CV1_CV_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 586 #define ADC_CV1_CV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 587 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
kadonotakashi 0:8fdf9a60065b 588
kadonotakashi 0:8fdf9a60065b 589 /*! @name CV2 - Compare Value Registers */
kadonotakashi 0:8fdf9a60065b 590 #define ADC_CV2_CV_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 591 #define ADC_CV2_CV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 592 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
kadonotakashi 0:8fdf9a60065b 593
kadonotakashi 0:8fdf9a60065b 594 /*! @name SC2 - Status and Control Register 2 */
kadonotakashi 0:8fdf9a60065b 595 #define ADC_SC2_REFSEL_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 596 #define ADC_SC2_REFSEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 597 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
kadonotakashi 0:8fdf9a60065b 598 #define ADC_SC2_DMAEN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 599 #define ADC_SC2_DMAEN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 600 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
kadonotakashi 0:8fdf9a60065b 601 #define ADC_SC2_ACREN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 602 #define ADC_SC2_ACREN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 603 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
kadonotakashi 0:8fdf9a60065b 604 #define ADC_SC2_ACFGT_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 605 #define ADC_SC2_ACFGT_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 606 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
kadonotakashi 0:8fdf9a60065b 607 #define ADC_SC2_ACFE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 608 #define ADC_SC2_ACFE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 609 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
kadonotakashi 0:8fdf9a60065b 610 #define ADC_SC2_ADTRG_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 611 #define ADC_SC2_ADTRG_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 612 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
kadonotakashi 0:8fdf9a60065b 613 #define ADC_SC2_ADACT_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 614 #define ADC_SC2_ADACT_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 615 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
kadonotakashi 0:8fdf9a60065b 616
kadonotakashi 0:8fdf9a60065b 617 /*! @name SC3 - Status and Control Register 3 */
kadonotakashi 0:8fdf9a60065b 618 #define ADC_SC3_AVGS_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 619 #define ADC_SC3_AVGS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 620 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
kadonotakashi 0:8fdf9a60065b 621 #define ADC_SC3_AVGE_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 622 #define ADC_SC3_AVGE_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 623 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
kadonotakashi 0:8fdf9a60065b 624 #define ADC_SC3_ADCO_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 625 #define ADC_SC3_ADCO_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 626 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
kadonotakashi 0:8fdf9a60065b 627 #define ADC_SC3_CALF_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 628 #define ADC_SC3_CALF_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 629 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
kadonotakashi 0:8fdf9a60065b 630 #define ADC_SC3_CAL_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 631 #define ADC_SC3_CAL_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 632 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
kadonotakashi 0:8fdf9a60065b 633
kadonotakashi 0:8fdf9a60065b 634 /*! @name OFS - ADC Offset Correction Register */
kadonotakashi 0:8fdf9a60065b 635 #define ADC_OFS_OFS_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 636 #define ADC_OFS_OFS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 637 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
kadonotakashi 0:8fdf9a60065b 638
kadonotakashi 0:8fdf9a60065b 639 /*! @name PG - ADC Plus-Side Gain Register */
kadonotakashi 0:8fdf9a60065b 640 #define ADC_PG_PG_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 641 #define ADC_PG_PG_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 642 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
kadonotakashi 0:8fdf9a60065b 643
kadonotakashi 0:8fdf9a60065b 644 /*! @name MG - ADC Minus-Side Gain Register */
kadonotakashi 0:8fdf9a60065b 645 #define ADC_MG_MG_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 646 #define ADC_MG_MG_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 647 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
kadonotakashi 0:8fdf9a60065b 648
kadonotakashi 0:8fdf9a60065b 649 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 650 #define ADC_CLPD_CLPD_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 651 #define ADC_CLPD_CLPD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 652 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
kadonotakashi 0:8fdf9a60065b 653
kadonotakashi 0:8fdf9a60065b 654 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 655 #define ADC_CLPS_CLPS_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 656 #define ADC_CLPS_CLPS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 657 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
kadonotakashi 0:8fdf9a60065b 658
kadonotakashi 0:8fdf9a60065b 659 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 660 #define ADC_CLP4_CLP4_MASK (0x3FFU)
kadonotakashi 0:8fdf9a60065b 661 #define ADC_CLP4_CLP4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 662 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
kadonotakashi 0:8fdf9a60065b 663
kadonotakashi 0:8fdf9a60065b 664 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 665 #define ADC_CLP3_CLP3_MASK (0x1FFU)
kadonotakashi 0:8fdf9a60065b 666 #define ADC_CLP3_CLP3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 667 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
kadonotakashi 0:8fdf9a60065b 668
kadonotakashi 0:8fdf9a60065b 669 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 670 #define ADC_CLP2_CLP2_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 671 #define ADC_CLP2_CLP2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 672 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
kadonotakashi 0:8fdf9a60065b 673
kadonotakashi 0:8fdf9a60065b 674 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 675 #define ADC_CLP1_CLP1_MASK (0x7FU)
kadonotakashi 0:8fdf9a60065b 676 #define ADC_CLP1_CLP1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 677 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
kadonotakashi 0:8fdf9a60065b 678
kadonotakashi 0:8fdf9a60065b 679 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 680 #define ADC_CLP0_CLP0_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 681 #define ADC_CLP0_CLP0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 682 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
kadonotakashi 0:8fdf9a60065b 683
kadonotakashi 0:8fdf9a60065b 684 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 685 #define ADC_CLMD_CLMD_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 686 #define ADC_CLMD_CLMD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 687 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
kadonotakashi 0:8fdf9a60065b 688
kadonotakashi 0:8fdf9a60065b 689 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 690 #define ADC_CLMS_CLMS_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 691 #define ADC_CLMS_CLMS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 692 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
kadonotakashi 0:8fdf9a60065b 693
kadonotakashi 0:8fdf9a60065b 694 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 695 #define ADC_CLM4_CLM4_MASK (0x3FFU)
kadonotakashi 0:8fdf9a60065b 696 #define ADC_CLM4_CLM4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 697 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
kadonotakashi 0:8fdf9a60065b 698
kadonotakashi 0:8fdf9a60065b 699 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 700 #define ADC_CLM3_CLM3_MASK (0x1FFU)
kadonotakashi 0:8fdf9a60065b 701 #define ADC_CLM3_CLM3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 702 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
kadonotakashi 0:8fdf9a60065b 703
kadonotakashi 0:8fdf9a60065b 704 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 705 #define ADC_CLM2_CLM2_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 706 #define ADC_CLM2_CLM2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 707 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
kadonotakashi 0:8fdf9a60065b 708
kadonotakashi 0:8fdf9a60065b 709 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 710 #define ADC_CLM1_CLM1_MASK (0x7FU)
kadonotakashi 0:8fdf9a60065b 711 #define ADC_CLM1_CLM1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 712 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
kadonotakashi 0:8fdf9a60065b 713
kadonotakashi 0:8fdf9a60065b 714 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
kadonotakashi 0:8fdf9a60065b 715 #define ADC_CLM0_CLM0_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 716 #define ADC_CLM0_CLM0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 717 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
kadonotakashi 0:8fdf9a60065b 718
kadonotakashi 0:8fdf9a60065b 719
kadonotakashi 0:8fdf9a60065b 720 /*!
kadonotakashi 0:8fdf9a60065b 721 * @}
kadonotakashi 0:8fdf9a60065b 722 */ /* end of group ADC_Register_Masks */
kadonotakashi 0:8fdf9a60065b 723
kadonotakashi 0:8fdf9a60065b 724
kadonotakashi 0:8fdf9a60065b 725 /* ADC - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 726 /** Peripheral ADC0 base address */
kadonotakashi 0:8fdf9a60065b 727 #define ADC0_BASE (0x4003B000u)
kadonotakashi 0:8fdf9a60065b 728 /** Peripheral ADC0 base pointer */
kadonotakashi 0:8fdf9a60065b 729 #define ADC0 ((ADC_Type *)ADC0_BASE)
kadonotakashi 0:8fdf9a60065b 730 /** Array initializer of ADC peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 731 #define ADC_BASE_ADDRS { ADC0_BASE }
kadonotakashi 0:8fdf9a60065b 732 /** Array initializer of ADC peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 733 #define ADC_BASE_PTRS { ADC0 }
kadonotakashi 0:8fdf9a60065b 734 /** Interrupt vectors for the ADC peripheral type */
kadonotakashi 0:8fdf9a60065b 735 #define ADC_IRQS { ADC0_IRQn }
kadonotakashi 0:8fdf9a60065b 736
kadonotakashi 0:8fdf9a60065b 737 /*!
kadonotakashi 0:8fdf9a60065b 738 * @}
kadonotakashi 0:8fdf9a60065b 739 */ /* end of group ADC_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 740
kadonotakashi 0:8fdf9a60065b 741
kadonotakashi 0:8fdf9a60065b 742 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 743 -- AIPS Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 744 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 745
kadonotakashi 0:8fdf9a60065b 746 /*!
kadonotakashi 0:8fdf9a60065b 747 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 748 * @{
kadonotakashi 0:8fdf9a60065b 749 */
kadonotakashi 0:8fdf9a60065b 750
kadonotakashi 0:8fdf9a60065b 751 /** AIPS - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 752 typedef struct {
kadonotakashi 0:8fdf9a60065b 753 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 754 uint8_t RESERVED_0[28];
kadonotakashi 0:8fdf9a60065b 755 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 756 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 757 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
kadonotakashi 0:8fdf9a60065b 758 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
kadonotakashi 0:8fdf9a60065b 759 uint8_t RESERVED_1[16];
kadonotakashi 0:8fdf9a60065b 760 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
kadonotakashi 0:8fdf9a60065b 761 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
kadonotakashi 0:8fdf9a60065b 762 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
kadonotakashi 0:8fdf9a60065b 763 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
kadonotakashi 0:8fdf9a60065b 764 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
kadonotakashi 0:8fdf9a60065b 765 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
kadonotakashi 0:8fdf9a60065b 766 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
kadonotakashi 0:8fdf9a60065b 767 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
kadonotakashi 0:8fdf9a60065b 768 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
kadonotakashi 0:8fdf9a60065b 769 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
kadonotakashi 0:8fdf9a60065b 770 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
kadonotakashi 0:8fdf9a60065b 771 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
kadonotakashi 0:8fdf9a60065b 772 } AIPS_Type;
kadonotakashi 0:8fdf9a60065b 773
kadonotakashi 0:8fdf9a60065b 774 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 775 -- AIPS Register Masks
kadonotakashi 0:8fdf9a60065b 776 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 777
kadonotakashi 0:8fdf9a60065b 778 /*!
kadonotakashi 0:8fdf9a60065b 779 * @addtogroup AIPS_Register_Masks AIPS Register Masks
kadonotakashi 0:8fdf9a60065b 780 * @{
kadonotakashi 0:8fdf9a60065b 781 */
kadonotakashi 0:8fdf9a60065b 782
kadonotakashi 0:8fdf9a60065b 783 /*! @name MPRA - Master Privilege Register A */
kadonotakashi 0:8fdf9a60065b 784 #define AIPS_MPRA_MPL4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 785 #define AIPS_MPRA_MPL4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 786 #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
kadonotakashi 0:8fdf9a60065b 787 #define AIPS_MPRA_MTW4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 788 #define AIPS_MPRA_MTW4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 789 #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
kadonotakashi 0:8fdf9a60065b 790 #define AIPS_MPRA_MTR4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 791 #define AIPS_MPRA_MTR4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 792 #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
kadonotakashi 0:8fdf9a60065b 793 #define AIPS_MPRA_MPL3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 794 #define AIPS_MPRA_MPL3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 795 #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
kadonotakashi 0:8fdf9a60065b 796 #define AIPS_MPRA_MTW3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 797 #define AIPS_MPRA_MTW3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 798 #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
kadonotakashi 0:8fdf9a60065b 799 #define AIPS_MPRA_MTR3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 800 #define AIPS_MPRA_MTR3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 801 #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
kadonotakashi 0:8fdf9a60065b 802 #define AIPS_MPRA_MPL2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 803 #define AIPS_MPRA_MPL2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 804 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
kadonotakashi 0:8fdf9a60065b 805 #define AIPS_MPRA_MTW2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 806 #define AIPS_MPRA_MTW2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 807 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
kadonotakashi 0:8fdf9a60065b 808 #define AIPS_MPRA_MTR2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 809 #define AIPS_MPRA_MTR2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 810 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
kadonotakashi 0:8fdf9a60065b 811 #define AIPS_MPRA_MPL1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 812 #define AIPS_MPRA_MPL1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 813 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
kadonotakashi 0:8fdf9a60065b 814 #define AIPS_MPRA_MTW1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 815 #define AIPS_MPRA_MTW1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 816 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
kadonotakashi 0:8fdf9a60065b 817 #define AIPS_MPRA_MTR1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 818 #define AIPS_MPRA_MTR1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 819 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
kadonotakashi 0:8fdf9a60065b 820 #define AIPS_MPRA_MPL0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 821 #define AIPS_MPRA_MPL0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 822 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
kadonotakashi 0:8fdf9a60065b 823 #define AIPS_MPRA_MTW0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 824 #define AIPS_MPRA_MTW0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 825 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
kadonotakashi 0:8fdf9a60065b 826 #define AIPS_MPRA_MTR0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 827 #define AIPS_MPRA_MTR0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 828 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
kadonotakashi 0:8fdf9a60065b 829
kadonotakashi 0:8fdf9a60065b 830 /*! @name PACRA - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 831 #define AIPS_PACRA_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 832 #define AIPS_PACRA_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 833 #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 834 #define AIPS_PACRA_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 835 #define AIPS_PACRA_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 836 #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 837 #define AIPS_PACRA_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 838 #define AIPS_PACRA_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 839 #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 840 #define AIPS_PACRA_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 841 #define AIPS_PACRA_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 842 #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 843 #define AIPS_PACRA_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 844 #define AIPS_PACRA_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 845 #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 846 #define AIPS_PACRA_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 847 #define AIPS_PACRA_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 848 #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 849 #define AIPS_PACRA_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 850 #define AIPS_PACRA_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 851 #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 852 #define AIPS_PACRA_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 853 #define AIPS_PACRA_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 854 #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 855 #define AIPS_PACRA_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 856 #define AIPS_PACRA_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 857 #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 858 #define AIPS_PACRA_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 859 #define AIPS_PACRA_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 860 #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 861 #define AIPS_PACRA_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 862 #define AIPS_PACRA_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 863 #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 864 #define AIPS_PACRA_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 865 #define AIPS_PACRA_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 866 #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 867 #define AIPS_PACRA_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 868 #define AIPS_PACRA_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 869 #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 870 #define AIPS_PACRA_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 871 #define AIPS_PACRA_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 872 #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 873 #define AIPS_PACRA_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 874 #define AIPS_PACRA_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 875 #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 876 #define AIPS_PACRA_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 877 #define AIPS_PACRA_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 878 #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 879 #define AIPS_PACRA_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 880 #define AIPS_PACRA_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 881 #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 882 #define AIPS_PACRA_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 883 #define AIPS_PACRA_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 884 #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 885 #define AIPS_PACRA_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 886 #define AIPS_PACRA_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 887 #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 888 #define AIPS_PACRA_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 889 #define AIPS_PACRA_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 890 #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 891 #define AIPS_PACRA_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 892 #define AIPS_PACRA_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 893 #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 894 #define AIPS_PACRA_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 895 #define AIPS_PACRA_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 896 #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 897 #define AIPS_PACRA_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 898 #define AIPS_PACRA_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 899 #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 900 #define AIPS_PACRA_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 901 #define AIPS_PACRA_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 902 #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 903
kadonotakashi 0:8fdf9a60065b 904 /*! @name PACRB - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 905 #define AIPS_PACRB_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 906 #define AIPS_PACRB_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 907 #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 908 #define AIPS_PACRB_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 909 #define AIPS_PACRB_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 910 #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 911 #define AIPS_PACRB_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 912 #define AIPS_PACRB_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 913 #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 914 #define AIPS_PACRB_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 915 #define AIPS_PACRB_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 916 #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 917 #define AIPS_PACRB_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 918 #define AIPS_PACRB_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 919 #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 920 #define AIPS_PACRB_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 921 #define AIPS_PACRB_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 922 #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 923 #define AIPS_PACRB_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 924 #define AIPS_PACRB_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 925 #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 926 #define AIPS_PACRB_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 927 #define AIPS_PACRB_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 928 #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 929 #define AIPS_PACRB_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 930 #define AIPS_PACRB_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 931 #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 932 #define AIPS_PACRB_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 933 #define AIPS_PACRB_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 934 #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 935 #define AIPS_PACRB_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 936 #define AIPS_PACRB_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 937 #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 938 #define AIPS_PACRB_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 939 #define AIPS_PACRB_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 940 #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 941 #define AIPS_PACRB_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 942 #define AIPS_PACRB_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 943 #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 944 #define AIPS_PACRB_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 945 #define AIPS_PACRB_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 946 #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 947 #define AIPS_PACRB_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 948 #define AIPS_PACRB_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 949 #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 950 #define AIPS_PACRB_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 951 #define AIPS_PACRB_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 952 #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 953 #define AIPS_PACRB_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 954 #define AIPS_PACRB_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 955 #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 956 #define AIPS_PACRB_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 957 #define AIPS_PACRB_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 958 #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 959 #define AIPS_PACRB_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 960 #define AIPS_PACRB_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 961 #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 962 #define AIPS_PACRB_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 963 #define AIPS_PACRB_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 964 #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 965 #define AIPS_PACRB_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 966 #define AIPS_PACRB_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 967 #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 968 #define AIPS_PACRB_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 969 #define AIPS_PACRB_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 970 #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 971 #define AIPS_PACRB_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 972 #define AIPS_PACRB_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 973 #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 974 #define AIPS_PACRB_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 975 #define AIPS_PACRB_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 976 #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 977
kadonotakashi 0:8fdf9a60065b 978 /*! @name PACRC - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 979 #define AIPS_PACRC_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 980 #define AIPS_PACRC_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 981 #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 982 #define AIPS_PACRC_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 983 #define AIPS_PACRC_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 984 #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 985 #define AIPS_PACRC_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 986 #define AIPS_PACRC_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 987 #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 988 #define AIPS_PACRC_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 989 #define AIPS_PACRC_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 990 #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 991 #define AIPS_PACRC_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 992 #define AIPS_PACRC_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 993 #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 994 #define AIPS_PACRC_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 995 #define AIPS_PACRC_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 996 #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 997 #define AIPS_PACRC_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 998 #define AIPS_PACRC_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 999 #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1000 #define AIPS_PACRC_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1001 #define AIPS_PACRC_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1002 #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1003 #define AIPS_PACRC_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1004 #define AIPS_PACRC_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1005 #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1006 #define AIPS_PACRC_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1007 #define AIPS_PACRC_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1008 #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1009 #define AIPS_PACRC_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1010 #define AIPS_PACRC_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1011 #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1012 #define AIPS_PACRC_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1013 #define AIPS_PACRC_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1014 #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1015 #define AIPS_PACRC_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1016 #define AIPS_PACRC_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1017 #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1018 #define AIPS_PACRC_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1019 #define AIPS_PACRC_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1020 #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1021 #define AIPS_PACRC_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1022 #define AIPS_PACRC_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1023 #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1024 #define AIPS_PACRC_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1025 #define AIPS_PACRC_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1026 #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1027 #define AIPS_PACRC_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1028 #define AIPS_PACRC_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1029 #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1030 #define AIPS_PACRC_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1031 #define AIPS_PACRC_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1032 #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1033 #define AIPS_PACRC_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1034 #define AIPS_PACRC_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1035 #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1036 #define AIPS_PACRC_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1037 #define AIPS_PACRC_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1038 #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1039 #define AIPS_PACRC_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1040 #define AIPS_PACRC_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1041 #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1042 #define AIPS_PACRC_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1043 #define AIPS_PACRC_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1044 #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1045 #define AIPS_PACRC_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1046 #define AIPS_PACRC_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1047 #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1048 #define AIPS_PACRC_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1049 #define AIPS_PACRC_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1050 #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1051
kadonotakashi 0:8fdf9a60065b 1052 /*! @name PACRD - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1053 #define AIPS_PACRD_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1054 #define AIPS_PACRD_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1055 #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1056 #define AIPS_PACRD_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1057 #define AIPS_PACRD_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1058 #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1059 #define AIPS_PACRD_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1060 #define AIPS_PACRD_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1061 #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1062 #define AIPS_PACRD_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1063 #define AIPS_PACRD_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1064 #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1065 #define AIPS_PACRD_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1066 #define AIPS_PACRD_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1067 #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1068 #define AIPS_PACRD_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1069 #define AIPS_PACRD_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1070 #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1071 #define AIPS_PACRD_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1072 #define AIPS_PACRD_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1073 #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1074 #define AIPS_PACRD_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1075 #define AIPS_PACRD_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1076 #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1077 #define AIPS_PACRD_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1078 #define AIPS_PACRD_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1079 #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1080 #define AIPS_PACRD_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1081 #define AIPS_PACRD_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1082 #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1083 #define AIPS_PACRD_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1084 #define AIPS_PACRD_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1085 #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1086 #define AIPS_PACRD_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1087 #define AIPS_PACRD_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1088 #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1089 #define AIPS_PACRD_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1090 #define AIPS_PACRD_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1091 #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1092 #define AIPS_PACRD_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1093 #define AIPS_PACRD_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1094 #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1095 #define AIPS_PACRD_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1096 #define AIPS_PACRD_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1097 #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1098 #define AIPS_PACRD_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1099 #define AIPS_PACRD_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1100 #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1101 #define AIPS_PACRD_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1102 #define AIPS_PACRD_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1103 #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1104 #define AIPS_PACRD_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1105 #define AIPS_PACRD_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1106 #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1107 #define AIPS_PACRD_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1108 #define AIPS_PACRD_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1109 #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1110 #define AIPS_PACRD_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1111 #define AIPS_PACRD_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1112 #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1113 #define AIPS_PACRD_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1114 #define AIPS_PACRD_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1115 #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1116 #define AIPS_PACRD_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1117 #define AIPS_PACRD_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1118 #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1119 #define AIPS_PACRD_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1120 #define AIPS_PACRD_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1121 #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1122 #define AIPS_PACRD_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1123 #define AIPS_PACRD_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1124 #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1125
kadonotakashi 0:8fdf9a60065b 1126 /*! @name PACRE - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1127 #define AIPS_PACRE_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1128 #define AIPS_PACRE_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1129 #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1130 #define AIPS_PACRE_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1131 #define AIPS_PACRE_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1132 #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1133 #define AIPS_PACRE_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1134 #define AIPS_PACRE_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1135 #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1136 #define AIPS_PACRE_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1137 #define AIPS_PACRE_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1138 #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1139 #define AIPS_PACRE_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1140 #define AIPS_PACRE_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1141 #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1142 #define AIPS_PACRE_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1143 #define AIPS_PACRE_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1144 #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1145 #define AIPS_PACRE_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1146 #define AIPS_PACRE_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1147 #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1148 #define AIPS_PACRE_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1149 #define AIPS_PACRE_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1150 #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1151 #define AIPS_PACRE_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1152 #define AIPS_PACRE_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1153 #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1154 #define AIPS_PACRE_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1155 #define AIPS_PACRE_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1156 #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1157 #define AIPS_PACRE_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1158 #define AIPS_PACRE_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1159 #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1160 #define AIPS_PACRE_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1161 #define AIPS_PACRE_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1162 #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1163 #define AIPS_PACRE_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1164 #define AIPS_PACRE_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1165 #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1166 #define AIPS_PACRE_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1167 #define AIPS_PACRE_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1168 #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1169 #define AIPS_PACRE_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1170 #define AIPS_PACRE_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1171 #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1172 #define AIPS_PACRE_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1173 #define AIPS_PACRE_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1174 #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1175 #define AIPS_PACRE_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1176 #define AIPS_PACRE_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1177 #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1178 #define AIPS_PACRE_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1179 #define AIPS_PACRE_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1180 #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1181 #define AIPS_PACRE_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1182 #define AIPS_PACRE_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1183 #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1184 #define AIPS_PACRE_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1185 #define AIPS_PACRE_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1186 #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1187 #define AIPS_PACRE_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1188 #define AIPS_PACRE_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1189 #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1190 #define AIPS_PACRE_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1191 #define AIPS_PACRE_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1192 #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1193 #define AIPS_PACRE_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1194 #define AIPS_PACRE_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1195 #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1196 #define AIPS_PACRE_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1197 #define AIPS_PACRE_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1198 #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1199
kadonotakashi 0:8fdf9a60065b 1200 /*! @name PACRF - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1201 #define AIPS_PACRF_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1202 #define AIPS_PACRF_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1203 #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1204 #define AIPS_PACRF_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1205 #define AIPS_PACRF_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1206 #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1207 #define AIPS_PACRF_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1208 #define AIPS_PACRF_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1209 #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1210 #define AIPS_PACRF_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1211 #define AIPS_PACRF_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1212 #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1213 #define AIPS_PACRF_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1214 #define AIPS_PACRF_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1215 #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1216 #define AIPS_PACRF_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1217 #define AIPS_PACRF_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1218 #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1219 #define AIPS_PACRF_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1220 #define AIPS_PACRF_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1221 #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1222 #define AIPS_PACRF_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1223 #define AIPS_PACRF_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1224 #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1225 #define AIPS_PACRF_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1226 #define AIPS_PACRF_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1227 #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1228 #define AIPS_PACRF_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1229 #define AIPS_PACRF_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1230 #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1231 #define AIPS_PACRF_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1232 #define AIPS_PACRF_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1233 #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1234 #define AIPS_PACRF_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1235 #define AIPS_PACRF_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1236 #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1237 #define AIPS_PACRF_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1238 #define AIPS_PACRF_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1239 #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1240 #define AIPS_PACRF_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1241 #define AIPS_PACRF_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1242 #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1243 #define AIPS_PACRF_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1244 #define AIPS_PACRF_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1245 #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1246 #define AIPS_PACRF_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1247 #define AIPS_PACRF_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1248 #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1249 #define AIPS_PACRF_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1250 #define AIPS_PACRF_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1251 #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1252 #define AIPS_PACRF_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1253 #define AIPS_PACRF_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1254 #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1255 #define AIPS_PACRF_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1256 #define AIPS_PACRF_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1257 #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1258 #define AIPS_PACRF_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1259 #define AIPS_PACRF_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1260 #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1261 #define AIPS_PACRF_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1262 #define AIPS_PACRF_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1263 #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1264 #define AIPS_PACRF_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1265 #define AIPS_PACRF_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1266 #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1267 #define AIPS_PACRF_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1268 #define AIPS_PACRF_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1269 #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1270 #define AIPS_PACRF_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1271 #define AIPS_PACRF_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1272 #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1273
kadonotakashi 0:8fdf9a60065b 1274 /*! @name PACRG - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1275 #define AIPS_PACRG_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1276 #define AIPS_PACRG_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1277 #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1278 #define AIPS_PACRG_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1279 #define AIPS_PACRG_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1280 #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1281 #define AIPS_PACRG_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1282 #define AIPS_PACRG_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1283 #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1284 #define AIPS_PACRG_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1285 #define AIPS_PACRG_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1286 #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1287 #define AIPS_PACRG_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1288 #define AIPS_PACRG_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1289 #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1290 #define AIPS_PACRG_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1291 #define AIPS_PACRG_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1292 #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1293 #define AIPS_PACRG_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1294 #define AIPS_PACRG_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1295 #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1296 #define AIPS_PACRG_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1297 #define AIPS_PACRG_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1298 #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1299 #define AIPS_PACRG_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1300 #define AIPS_PACRG_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1301 #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1302 #define AIPS_PACRG_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1303 #define AIPS_PACRG_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1304 #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1305 #define AIPS_PACRG_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1306 #define AIPS_PACRG_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1307 #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1308 #define AIPS_PACRG_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1309 #define AIPS_PACRG_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1310 #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1311 #define AIPS_PACRG_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1312 #define AIPS_PACRG_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1313 #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1314 #define AIPS_PACRG_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1315 #define AIPS_PACRG_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1316 #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1317 #define AIPS_PACRG_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1318 #define AIPS_PACRG_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1319 #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1320 #define AIPS_PACRG_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1321 #define AIPS_PACRG_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1322 #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1323 #define AIPS_PACRG_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1324 #define AIPS_PACRG_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1325 #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1326 #define AIPS_PACRG_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1327 #define AIPS_PACRG_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1328 #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1329 #define AIPS_PACRG_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1330 #define AIPS_PACRG_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1331 #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1332 #define AIPS_PACRG_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1333 #define AIPS_PACRG_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1334 #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1335 #define AIPS_PACRG_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1336 #define AIPS_PACRG_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1337 #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1338 #define AIPS_PACRG_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1339 #define AIPS_PACRG_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1340 #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1341 #define AIPS_PACRG_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1342 #define AIPS_PACRG_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1343 #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1344 #define AIPS_PACRG_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1345 #define AIPS_PACRG_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1346 #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1347
kadonotakashi 0:8fdf9a60065b 1348 /*! @name PACRH - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1349 #define AIPS_PACRH_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1350 #define AIPS_PACRH_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1351 #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1352 #define AIPS_PACRH_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1353 #define AIPS_PACRH_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1354 #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1355 #define AIPS_PACRH_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1356 #define AIPS_PACRH_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1357 #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1358 #define AIPS_PACRH_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1359 #define AIPS_PACRH_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1360 #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1361 #define AIPS_PACRH_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1362 #define AIPS_PACRH_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1363 #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1364 #define AIPS_PACRH_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1365 #define AIPS_PACRH_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1366 #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1367 #define AIPS_PACRH_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1368 #define AIPS_PACRH_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1369 #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1370 #define AIPS_PACRH_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1371 #define AIPS_PACRH_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1372 #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1373 #define AIPS_PACRH_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1374 #define AIPS_PACRH_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1375 #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1376 #define AIPS_PACRH_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1377 #define AIPS_PACRH_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1378 #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1379 #define AIPS_PACRH_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1380 #define AIPS_PACRH_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1381 #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1382 #define AIPS_PACRH_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1383 #define AIPS_PACRH_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1384 #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1385 #define AIPS_PACRH_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1386 #define AIPS_PACRH_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1387 #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1388 #define AIPS_PACRH_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1389 #define AIPS_PACRH_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1390 #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1391 #define AIPS_PACRH_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1392 #define AIPS_PACRH_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1393 #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1394 #define AIPS_PACRH_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1395 #define AIPS_PACRH_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1396 #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1397 #define AIPS_PACRH_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1398 #define AIPS_PACRH_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1399 #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1400 #define AIPS_PACRH_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1401 #define AIPS_PACRH_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1402 #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1403 #define AIPS_PACRH_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1404 #define AIPS_PACRH_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1405 #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1406 #define AIPS_PACRH_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1407 #define AIPS_PACRH_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1408 #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1409 #define AIPS_PACRH_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1410 #define AIPS_PACRH_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1411 #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1412 #define AIPS_PACRH_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1413 #define AIPS_PACRH_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1414 #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1415 #define AIPS_PACRH_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1416 #define AIPS_PACRH_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1417 #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1418 #define AIPS_PACRH_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1419 #define AIPS_PACRH_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1420 #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1421
kadonotakashi 0:8fdf9a60065b 1422 /*! @name PACRI - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1423 #define AIPS_PACRI_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1424 #define AIPS_PACRI_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1425 #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1426 #define AIPS_PACRI_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1427 #define AIPS_PACRI_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1428 #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1429 #define AIPS_PACRI_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1430 #define AIPS_PACRI_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1431 #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1432 #define AIPS_PACRI_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1433 #define AIPS_PACRI_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1434 #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1435 #define AIPS_PACRI_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1436 #define AIPS_PACRI_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1437 #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1438 #define AIPS_PACRI_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1439 #define AIPS_PACRI_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1440 #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1441 #define AIPS_PACRI_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1442 #define AIPS_PACRI_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1443 #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1444 #define AIPS_PACRI_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1445 #define AIPS_PACRI_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1446 #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1447 #define AIPS_PACRI_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1448 #define AIPS_PACRI_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1449 #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1450 #define AIPS_PACRI_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1451 #define AIPS_PACRI_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1452 #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1453 #define AIPS_PACRI_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1454 #define AIPS_PACRI_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1455 #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1456 #define AIPS_PACRI_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1457 #define AIPS_PACRI_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1458 #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1459 #define AIPS_PACRI_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1460 #define AIPS_PACRI_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1461 #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1462 #define AIPS_PACRI_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1463 #define AIPS_PACRI_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1464 #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1465 #define AIPS_PACRI_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1466 #define AIPS_PACRI_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1467 #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1468 #define AIPS_PACRI_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1469 #define AIPS_PACRI_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1470 #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1471 #define AIPS_PACRI_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1472 #define AIPS_PACRI_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1473 #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1474 #define AIPS_PACRI_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1475 #define AIPS_PACRI_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1476 #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1477 #define AIPS_PACRI_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1478 #define AIPS_PACRI_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1479 #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1480 #define AIPS_PACRI_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1481 #define AIPS_PACRI_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1482 #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1483 #define AIPS_PACRI_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1484 #define AIPS_PACRI_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1485 #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1486 #define AIPS_PACRI_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1487 #define AIPS_PACRI_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1488 #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1489 #define AIPS_PACRI_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1490 #define AIPS_PACRI_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1491 #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1492 #define AIPS_PACRI_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1493 #define AIPS_PACRI_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1494 #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1495
kadonotakashi 0:8fdf9a60065b 1496 /*! @name PACRJ - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1497 #define AIPS_PACRJ_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1498 #define AIPS_PACRJ_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1499 #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1500 #define AIPS_PACRJ_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1501 #define AIPS_PACRJ_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1502 #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1503 #define AIPS_PACRJ_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1504 #define AIPS_PACRJ_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1505 #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1506 #define AIPS_PACRJ_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1507 #define AIPS_PACRJ_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1508 #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1509 #define AIPS_PACRJ_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1510 #define AIPS_PACRJ_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1511 #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1512 #define AIPS_PACRJ_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1513 #define AIPS_PACRJ_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1514 #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1515 #define AIPS_PACRJ_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1516 #define AIPS_PACRJ_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1517 #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1518 #define AIPS_PACRJ_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1519 #define AIPS_PACRJ_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1520 #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1521 #define AIPS_PACRJ_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1522 #define AIPS_PACRJ_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1523 #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1524 #define AIPS_PACRJ_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1525 #define AIPS_PACRJ_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1526 #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1527 #define AIPS_PACRJ_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1528 #define AIPS_PACRJ_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1529 #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1530 #define AIPS_PACRJ_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1531 #define AIPS_PACRJ_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1532 #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1533 #define AIPS_PACRJ_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1534 #define AIPS_PACRJ_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1535 #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1536 #define AIPS_PACRJ_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1537 #define AIPS_PACRJ_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1538 #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1539 #define AIPS_PACRJ_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1540 #define AIPS_PACRJ_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1541 #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1542 #define AIPS_PACRJ_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1543 #define AIPS_PACRJ_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1544 #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1545 #define AIPS_PACRJ_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1546 #define AIPS_PACRJ_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1547 #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1548 #define AIPS_PACRJ_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1549 #define AIPS_PACRJ_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1550 #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1551 #define AIPS_PACRJ_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1552 #define AIPS_PACRJ_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1553 #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1554 #define AIPS_PACRJ_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1555 #define AIPS_PACRJ_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1556 #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1557 #define AIPS_PACRJ_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1558 #define AIPS_PACRJ_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1559 #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1560 #define AIPS_PACRJ_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1561 #define AIPS_PACRJ_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1562 #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1563 #define AIPS_PACRJ_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1564 #define AIPS_PACRJ_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1565 #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1566 #define AIPS_PACRJ_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1567 #define AIPS_PACRJ_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1568 #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1569
kadonotakashi 0:8fdf9a60065b 1570 /*! @name PACRK - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1571 #define AIPS_PACRK_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1572 #define AIPS_PACRK_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1573 #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1574 #define AIPS_PACRK_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1575 #define AIPS_PACRK_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1576 #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1577 #define AIPS_PACRK_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1578 #define AIPS_PACRK_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1579 #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1580 #define AIPS_PACRK_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1581 #define AIPS_PACRK_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1582 #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1583 #define AIPS_PACRK_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1584 #define AIPS_PACRK_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1585 #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1586 #define AIPS_PACRK_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1587 #define AIPS_PACRK_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1588 #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1589 #define AIPS_PACRK_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1590 #define AIPS_PACRK_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1591 #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1592 #define AIPS_PACRK_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1593 #define AIPS_PACRK_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1594 #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1595 #define AIPS_PACRK_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1596 #define AIPS_PACRK_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1597 #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1598 #define AIPS_PACRK_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1599 #define AIPS_PACRK_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1600 #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1601 #define AIPS_PACRK_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1602 #define AIPS_PACRK_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1603 #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1604 #define AIPS_PACRK_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1605 #define AIPS_PACRK_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1606 #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1607 #define AIPS_PACRK_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1608 #define AIPS_PACRK_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1609 #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1610 #define AIPS_PACRK_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1611 #define AIPS_PACRK_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1612 #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1613 #define AIPS_PACRK_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1614 #define AIPS_PACRK_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1615 #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1616 #define AIPS_PACRK_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1617 #define AIPS_PACRK_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1618 #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1619 #define AIPS_PACRK_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1620 #define AIPS_PACRK_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1621 #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1622 #define AIPS_PACRK_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1623 #define AIPS_PACRK_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1624 #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1625 #define AIPS_PACRK_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1626 #define AIPS_PACRK_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1627 #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1628 #define AIPS_PACRK_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1629 #define AIPS_PACRK_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1630 #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1631 #define AIPS_PACRK_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1632 #define AIPS_PACRK_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1633 #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1634 #define AIPS_PACRK_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1635 #define AIPS_PACRK_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1636 #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1637 #define AIPS_PACRK_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1638 #define AIPS_PACRK_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1639 #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1640 #define AIPS_PACRK_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1641 #define AIPS_PACRK_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1642 #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1643
kadonotakashi 0:8fdf9a60065b 1644 /*! @name PACRL - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1645 #define AIPS_PACRL_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1646 #define AIPS_PACRL_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1647 #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1648 #define AIPS_PACRL_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1649 #define AIPS_PACRL_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1650 #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1651 #define AIPS_PACRL_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1652 #define AIPS_PACRL_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1653 #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1654 #define AIPS_PACRL_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1655 #define AIPS_PACRL_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1656 #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1657 #define AIPS_PACRL_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1658 #define AIPS_PACRL_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1659 #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1660 #define AIPS_PACRL_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1661 #define AIPS_PACRL_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1662 #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1663 #define AIPS_PACRL_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1664 #define AIPS_PACRL_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1665 #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1666 #define AIPS_PACRL_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1667 #define AIPS_PACRL_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1668 #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1669 #define AIPS_PACRL_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1670 #define AIPS_PACRL_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1671 #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1672 #define AIPS_PACRL_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1673 #define AIPS_PACRL_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1674 #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1675 #define AIPS_PACRL_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1676 #define AIPS_PACRL_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1677 #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1678 #define AIPS_PACRL_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1679 #define AIPS_PACRL_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1680 #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1681 #define AIPS_PACRL_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1682 #define AIPS_PACRL_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1683 #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1684 #define AIPS_PACRL_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1685 #define AIPS_PACRL_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1686 #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1687 #define AIPS_PACRL_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1688 #define AIPS_PACRL_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1689 #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1690 #define AIPS_PACRL_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1691 #define AIPS_PACRL_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1692 #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1693 #define AIPS_PACRL_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1694 #define AIPS_PACRL_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1695 #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1696 #define AIPS_PACRL_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1697 #define AIPS_PACRL_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1698 #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1699 #define AIPS_PACRL_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1700 #define AIPS_PACRL_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1701 #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1702 #define AIPS_PACRL_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1703 #define AIPS_PACRL_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1704 #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1705 #define AIPS_PACRL_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1706 #define AIPS_PACRL_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1707 #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1708 #define AIPS_PACRL_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1709 #define AIPS_PACRL_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1710 #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1711 #define AIPS_PACRL_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1712 #define AIPS_PACRL_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1713 #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1714 #define AIPS_PACRL_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1715 #define AIPS_PACRL_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1716 #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1717
kadonotakashi 0:8fdf9a60065b 1718 /*! @name PACRM - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1719 #define AIPS_PACRM_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1720 #define AIPS_PACRM_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1721 #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1722 #define AIPS_PACRM_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1723 #define AIPS_PACRM_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1724 #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1725 #define AIPS_PACRM_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1726 #define AIPS_PACRM_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1727 #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1728 #define AIPS_PACRM_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1729 #define AIPS_PACRM_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1730 #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1731 #define AIPS_PACRM_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1732 #define AIPS_PACRM_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1733 #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1734 #define AIPS_PACRM_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1735 #define AIPS_PACRM_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1736 #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1737 #define AIPS_PACRM_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1738 #define AIPS_PACRM_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1739 #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1740 #define AIPS_PACRM_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1741 #define AIPS_PACRM_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1742 #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1743 #define AIPS_PACRM_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1744 #define AIPS_PACRM_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1745 #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1746 #define AIPS_PACRM_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1747 #define AIPS_PACRM_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1748 #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1749 #define AIPS_PACRM_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1750 #define AIPS_PACRM_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1751 #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1752 #define AIPS_PACRM_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1753 #define AIPS_PACRM_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1754 #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1755 #define AIPS_PACRM_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1756 #define AIPS_PACRM_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1757 #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1758 #define AIPS_PACRM_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1759 #define AIPS_PACRM_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1760 #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1761 #define AIPS_PACRM_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1762 #define AIPS_PACRM_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1763 #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1764 #define AIPS_PACRM_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1765 #define AIPS_PACRM_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1766 #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1767 #define AIPS_PACRM_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1768 #define AIPS_PACRM_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1769 #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1770 #define AIPS_PACRM_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1771 #define AIPS_PACRM_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1772 #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1773 #define AIPS_PACRM_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1774 #define AIPS_PACRM_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1775 #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1776 #define AIPS_PACRM_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1777 #define AIPS_PACRM_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1778 #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1779 #define AIPS_PACRM_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1780 #define AIPS_PACRM_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1781 #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1782 #define AIPS_PACRM_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1783 #define AIPS_PACRM_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1784 #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1785 #define AIPS_PACRM_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1786 #define AIPS_PACRM_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1787 #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1788 #define AIPS_PACRM_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1789 #define AIPS_PACRM_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1790 #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1791
kadonotakashi 0:8fdf9a60065b 1792 /*! @name PACRN - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1793 #define AIPS_PACRN_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1794 #define AIPS_PACRN_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1795 #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1796 #define AIPS_PACRN_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1797 #define AIPS_PACRN_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1798 #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1799 #define AIPS_PACRN_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1800 #define AIPS_PACRN_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1801 #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1802 #define AIPS_PACRN_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1803 #define AIPS_PACRN_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1804 #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1805 #define AIPS_PACRN_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1806 #define AIPS_PACRN_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1807 #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1808 #define AIPS_PACRN_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1809 #define AIPS_PACRN_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1810 #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1811 #define AIPS_PACRN_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1812 #define AIPS_PACRN_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1813 #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1814 #define AIPS_PACRN_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1815 #define AIPS_PACRN_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1816 #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1817 #define AIPS_PACRN_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1818 #define AIPS_PACRN_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1819 #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1820 #define AIPS_PACRN_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1821 #define AIPS_PACRN_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1822 #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1823 #define AIPS_PACRN_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1824 #define AIPS_PACRN_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1825 #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1826 #define AIPS_PACRN_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1827 #define AIPS_PACRN_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1828 #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1829 #define AIPS_PACRN_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1830 #define AIPS_PACRN_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1831 #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1832 #define AIPS_PACRN_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1833 #define AIPS_PACRN_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1834 #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1835 #define AIPS_PACRN_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1836 #define AIPS_PACRN_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1837 #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1838 #define AIPS_PACRN_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1839 #define AIPS_PACRN_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1840 #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1841 #define AIPS_PACRN_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1842 #define AIPS_PACRN_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1843 #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1844 #define AIPS_PACRN_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1845 #define AIPS_PACRN_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1846 #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1847 #define AIPS_PACRN_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1848 #define AIPS_PACRN_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1849 #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1850 #define AIPS_PACRN_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1851 #define AIPS_PACRN_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1852 #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1853 #define AIPS_PACRN_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1854 #define AIPS_PACRN_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1855 #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1856 #define AIPS_PACRN_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1857 #define AIPS_PACRN_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1858 #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1859 #define AIPS_PACRN_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1860 #define AIPS_PACRN_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1861 #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1862 #define AIPS_PACRN_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1863 #define AIPS_PACRN_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1864 #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1865
kadonotakashi 0:8fdf9a60065b 1866 /*! @name PACRO - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1867 #define AIPS_PACRO_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1868 #define AIPS_PACRO_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1869 #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1870 #define AIPS_PACRO_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1871 #define AIPS_PACRO_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1872 #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1873 #define AIPS_PACRO_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1874 #define AIPS_PACRO_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1875 #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1876 #define AIPS_PACRO_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1877 #define AIPS_PACRO_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1878 #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1879 #define AIPS_PACRO_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1880 #define AIPS_PACRO_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1881 #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1882 #define AIPS_PACRO_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1883 #define AIPS_PACRO_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1884 #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1885 #define AIPS_PACRO_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1886 #define AIPS_PACRO_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1887 #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1888 #define AIPS_PACRO_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1889 #define AIPS_PACRO_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1890 #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1891 #define AIPS_PACRO_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1892 #define AIPS_PACRO_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1893 #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1894 #define AIPS_PACRO_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1895 #define AIPS_PACRO_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1896 #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1897 #define AIPS_PACRO_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1898 #define AIPS_PACRO_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1899 #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1900 #define AIPS_PACRO_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1901 #define AIPS_PACRO_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1902 #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1903 #define AIPS_PACRO_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1904 #define AIPS_PACRO_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1905 #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1906 #define AIPS_PACRO_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1907 #define AIPS_PACRO_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1908 #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1909 #define AIPS_PACRO_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1910 #define AIPS_PACRO_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1911 #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1912 #define AIPS_PACRO_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1913 #define AIPS_PACRO_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1914 #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1915 #define AIPS_PACRO_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1916 #define AIPS_PACRO_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1917 #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1918 #define AIPS_PACRO_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1919 #define AIPS_PACRO_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1920 #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1921 #define AIPS_PACRO_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1922 #define AIPS_PACRO_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1923 #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1924 #define AIPS_PACRO_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1925 #define AIPS_PACRO_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 1926 #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 1927 #define AIPS_PACRO_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 1928 #define AIPS_PACRO_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 1929 #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 1930 #define AIPS_PACRO_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 1931 #define AIPS_PACRO_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 1932 #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 1933 #define AIPS_PACRO_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 1934 #define AIPS_PACRO_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 1935 #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 1936 #define AIPS_PACRO_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 1937 #define AIPS_PACRO_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 1938 #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 1939
kadonotakashi 0:8fdf9a60065b 1940 /*! @name PACRP - Peripheral Access Control Register */
kadonotakashi 0:8fdf9a60065b 1941 #define AIPS_PACRP_TP7_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 1942 #define AIPS_PACRP_TP7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 1943 #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
kadonotakashi 0:8fdf9a60065b 1944 #define AIPS_PACRP_WP7_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 1945 #define AIPS_PACRP_WP7_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 1946 #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
kadonotakashi 0:8fdf9a60065b 1947 #define AIPS_PACRP_SP7_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 1948 #define AIPS_PACRP_SP7_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 1949 #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
kadonotakashi 0:8fdf9a60065b 1950 #define AIPS_PACRP_TP6_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 1951 #define AIPS_PACRP_TP6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 1952 #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
kadonotakashi 0:8fdf9a60065b 1953 #define AIPS_PACRP_WP6_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 1954 #define AIPS_PACRP_WP6_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 1955 #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
kadonotakashi 0:8fdf9a60065b 1956 #define AIPS_PACRP_SP6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 1957 #define AIPS_PACRP_SP6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 1958 #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
kadonotakashi 0:8fdf9a60065b 1959 #define AIPS_PACRP_TP5_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 1960 #define AIPS_PACRP_TP5_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 1961 #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
kadonotakashi 0:8fdf9a60065b 1962 #define AIPS_PACRP_WP5_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 1963 #define AIPS_PACRP_WP5_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 1964 #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
kadonotakashi 0:8fdf9a60065b 1965 #define AIPS_PACRP_SP5_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 1966 #define AIPS_PACRP_SP5_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 1967 #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
kadonotakashi 0:8fdf9a60065b 1968 #define AIPS_PACRP_TP4_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 1969 #define AIPS_PACRP_TP4_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 1970 #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
kadonotakashi 0:8fdf9a60065b 1971 #define AIPS_PACRP_WP4_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 1972 #define AIPS_PACRP_WP4_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 1973 #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
kadonotakashi 0:8fdf9a60065b 1974 #define AIPS_PACRP_SP4_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 1975 #define AIPS_PACRP_SP4_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 1976 #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
kadonotakashi 0:8fdf9a60065b 1977 #define AIPS_PACRP_TP3_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 1978 #define AIPS_PACRP_TP3_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 1979 #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
kadonotakashi 0:8fdf9a60065b 1980 #define AIPS_PACRP_WP3_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 1981 #define AIPS_PACRP_WP3_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 1982 #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
kadonotakashi 0:8fdf9a60065b 1983 #define AIPS_PACRP_SP3_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 1984 #define AIPS_PACRP_SP3_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 1985 #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
kadonotakashi 0:8fdf9a60065b 1986 #define AIPS_PACRP_TP2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 1987 #define AIPS_PACRP_TP2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 1988 #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
kadonotakashi 0:8fdf9a60065b 1989 #define AIPS_PACRP_WP2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 1990 #define AIPS_PACRP_WP2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 1991 #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
kadonotakashi 0:8fdf9a60065b 1992 #define AIPS_PACRP_SP2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 1993 #define AIPS_PACRP_SP2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 1994 #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
kadonotakashi 0:8fdf9a60065b 1995 #define AIPS_PACRP_TP1_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 1996 #define AIPS_PACRP_TP1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 1997 #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
kadonotakashi 0:8fdf9a60065b 1998 #define AIPS_PACRP_WP1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 1999 #define AIPS_PACRP_WP1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 2000 #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
kadonotakashi 0:8fdf9a60065b 2001 #define AIPS_PACRP_SP1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 2002 #define AIPS_PACRP_SP1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 2003 #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
kadonotakashi 0:8fdf9a60065b 2004 #define AIPS_PACRP_TP0_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 2005 #define AIPS_PACRP_TP0_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 2006 #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
kadonotakashi 0:8fdf9a60065b 2007 #define AIPS_PACRP_WP0_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 2008 #define AIPS_PACRP_WP0_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 2009 #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
kadonotakashi 0:8fdf9a60065b 2010 #define AIPS_PACRP_SP0_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 2011 #define AIPS_PACRP_SP0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 2012 #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
kadonotakashi 0:8fdf9a60065b 2013
kadonotakashi 0:8fdf9a60065b 2014
kadonotakashi 0:8fdf9a60065b 2015 /*!
kadonotakashi 0:8fdf9a60065b 2016 * @}
kadonotakashi 0:8fdf9a60065b 2017 */ /* end of group AIPS_Register_Masks */
kadonotakashi 0:8fdf9a60065b 2018
kadonotakashi 0:8fdf9a60065b 2019
kadonotakashi 0:8fdf9a60065b 2020 /* AIPS - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 2021 /** Peripheral AIPS0 base address */
kadonotakashi 0:8fdf9a60065b 2022 #define AIPS0_BASE (0x40000000u)
kadonotakashi 0:8fdf9a60065b 2023 /** Peripheral AIPS0 base pointer */
kadonotakashi 0:8fdf9a60065b 2024 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
kadonotakashi 0:8fdf9a60065b 2025 /** Peripheral AIPS1 base address */
kadonotakashi 0:8fdf9a60065b 2026 #define AIPS1_BASE (0x40080000u)
kadonotakashi 0:8fdf9a60065b 2027 /** Peripheral AIPS1 base pointer */
kadonotakashi 0:8fdf9a60065b 2028 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
kadonotakashi 0:8fdf9a60065b 2029 /** Array initializer of AIPS peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 2030 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
kadonotakashi 0:8fdf9a60065b 2031 /** Array initializer of AIPS peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 2032 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
kadonotakashi 0:8fdf9a60065b 2033
kadonotakashi 0:8fdf9a60065b 2034 /*!
kadonotakashi 0:8fdf9a60065b 2035 * @}
kadonotakashi 0:8fdf9a60065b 2036 */ /* end of group AIPS_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 2037
kadonotakashi 0:8fdf9a60065b 2038
kadonotakashi 0:8fdf9a60065b 2039 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 2040 -- AXBS Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 2041 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 2042
kadonotakashi 0:8fdf9a60065b 2043 /*!
kadonotakashi 0:8fdf9a60065b 2044 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 2045 * @{
kadonotakashi 0:8fdf9a60065b 2046 */
kadonotakashi 0:8fdf9a60065b 2047
kadonotakashi 0:8fdf9a60065b 2048 /** AXBS - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 2049 typedef struct {
kadonotakashi 0:8fdf9a60065b 2050 struct { /* offset: 0x0, array step: 0x100 */
kadonotakashi 0:8fdf9a60065b 2051 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
kadonotakashi 0:8fdf9a60065b 2052 uint8_t RESERVED_0[12];
kadonotakashi 0:8fdf9a60065b 2053 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
kadonotakashi 0:8fdf9a60065b 2054 uint8_t RESERVED_1[236];
kadonotakashi 0:8fdf9a60065b 2055 } SLAVE[6];
kadonotakashi 0:8fdf9a60065b 2056 uint8_t RESERVED_0[512];
kadonotakashi 0:8fdf9a60065b 2057 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
kadonotakashi 0:8fdf9a60065b 2058 uint8_t RESERVED_1[252];
kadonotakashi 0:8fdf9a60065b 2059 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
kadonotakashi 0:8fdf9a60065b 2060 uint8_t RESERVED_2[252];
kadonotakashi 0:8fdf9a60065b 2061 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
kadonotakashi 0:8fdf9a60065b 2062 uint8_t RESERVED_3[252];
kadonotakashi 0:8fdf9a60065b 2063 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
kadonotakashi 0:8fdf9a60065b 2064 uint8_t RESERVED_4[252];
kadonotakashi 0:8fdf9a60065b 2065 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
kadonotakashi 0:8fdf9a60065b 2066 } AXBS_Type;
kadonotakashi 0:8fdf9a60065b 2067
kadonotakashi 0:8fdf9a60065b 2068 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 2069 -- AXBS Register Masks
kadonotakashi 0:8fdf9a60065b 2070 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 2071
kadonotakashi 0:8fdf9a60065b 2072 /*!
kadonotakashi 0:8fdf9a60065b 2073 * @addtogroup AXBS_Register_Masks AXBS Register Masks
kadonotakashi 0:8fdf9a60065b 2074 * @{
kadonotakashi 0:8fdf9a60065b 2075 */
kadonotakashi 0:8fdf9a60065b 2076
kadonotakashi 0:8fdf9a60065b 2077 /*! @name PRS - Priority Registers Slave */
kadonotakashi 0:8fdf9a60065b 2078 #define AXBS_PRS_M0_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 2079 #define AXBS_PRS_M0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2080 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
kadonotakashi 0:8fdf9a60065b 2081 #define AXBS_PRS_M1_MASK (0x70U)
kadonotakashi 0:8fdf9a60065b 2082 #define AXBS_PRS_M1_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 2083 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
kadonotakashi 0:8fdf9a60065b 2084 #define AXBS_PRS_M2_MASK (0x700U)
kadonotakashi 0:8fdf9a60065b 2085 #define AXBS_PRS_M2_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 2086 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
kadonotakashi 0:8fdf9a60065b 2087 #define AXBS_PRS_M3_MASK (0x7000U)
kadonotakashi 0:8fdf9a60065b 2088 #define AXBS_PRS_M3_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 2089 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
kadonotakashi 0:8fdf9a60065b 2090 #define AXBS_PRS_M4_MASK (0x70000U)
kadonotakashi 0:8fdf9a60065b 2091 #define AXBS_PRS_M4_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 2092 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
kadonotakashi 0:8fdf9a60065b 2093
kadonotakashi 0:8fdf9a60065b 2094 /* The count of AXBS_PRS */
kadonotakashi 0:8fdf9a60065b 2095 #define AXBS_PRS_COUNT (6U)
kadonotakashi 0:8fdf9a60065b 2096
kadonotakashi 0:8fdf9a60065b 2097 /*! @name CRS - Control Register */
kadonotakashi 0:8fdf9a60065b 2098 #define AXBS_CRS_PARK_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 2099 #define AXBS_CRS_PARK_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2100 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
kadonotakashi 0:8fdf9a60065b 2101 #define AXBS_CRS_PCTL_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 2102 #define AXBS_CRS_PCTL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 2103 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
kadonotakashi 0:8fdf9a60065b 2104 #define AXBS_CRS_ARB_MASK (0x300U)
kadonotakashi 0:8fdf9a60065b 2105 #define AXBS_CRS_ARB_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 2106 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
kadonotakashi 0:8fdf9a60065b 2107 #define AXBS_CRS_HLP_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 2108 #define AXBS_CRS_HLP_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 2109 #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
kadonotakashi 0:8fdf9a60065b 2110 #define AXBS_CRS_RO_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 2111 #define AXBS_CRS_RO_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 2112 #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
kadonotakashi 0:8fdf9a60065b 2113
kadonotakashi 0:8fdf9a60065b 2114 /* The count of AXBS_CRS */
kadonotakashi 0:8fdf9a60065b 2115 #define AXBS_CRS_COUNT (6U)
kadonotakashi 0:8fdf9a60065b 2116
kadonotakashi 0:8fdf9a60065b 2117 /*! @name MGPCR0 - Master General Purpose Control Register */
kadonotakashi 0:8fdf9a60065b 2118 #define AXBS_MGPCR0_AULB_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 2119 #define AXBS_MGPCR0_AULB_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2120 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
kadonotakashi 0:8fdf9a60065b 2121
kadonotakashi 0:8fdf9a60065b 2122 /*! @name MGPCR1 - Master General Purpose Control Register */
kadonotakashi 0:8fdf9a60065b 2123 #define AXBS_MGPCR1_AULB_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 2124 #define AXBS_MGPCR1_AULB_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2125 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
kadonotakashi 0:8fdf9a60065b 2126
kadonotakashi 0:8fdf9a60065b 2127 /*! @name MGPCR2 - Master General Purpose Control Register */
kadonotakashi 0:8fdf9a60065b 2128 #define AXBS_MGPCR2_AULB_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 2129 #define AXBS_MGPCR2_AULB_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2130 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
kadonotakashi 0:8fdf9a60065b 2131
kadonotakashi 0:8fdf9a60065b 2132 /*! @name MGPCR3 - Master General Purpose Control Register */
kadonotakashi 0:8fdf9a60065b 2133 #define AXBS_MGPCR3_AULB_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 2134 #define AXBS_MGPCR3_AULB_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2135 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
kadonotakashi 0:8fdf9a60065b 2136
kadonotakashi 0:8fdf9a60065b 2137 /*! @name MGPCR4 - Master General Purpose Control Register */
kadonotakashi 0:8fdf9a60065b 2138 #define AXBS_MGPCR4_AULB_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 2139 #define AXBS_MGPCR4_AULB_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2140 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
kadonotakashi 0:8fdf9a60065b 2141
kadonotakashi 0:8fdf9a60065b 2142
kadonotakashi 0:8fdf9a60065b 2143 /*!
kadonotakashi 0:8fdf9a60065b 2144 * @}
kadonotakashi 0:8fdf9a60065b 2145 */ /* end of group AXBS_Register_Masks */
kadonotakashi 0:8fdf9a60065b 2146
kadonotakashi 0:8fdf9a60065b 2147
kadonotakashi 0:8fdf9a60065b 2148 /* AXBS - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 2149 /** Peripheral AXBS base address */
kadonotakashi 0:8fdf9a60065b 2150 #define AXBS_BASE (0x40004000u)
kadonotakashi 0:8fdf9a60065b 2151 /** Peripheral AXBS base pointer */
kadonotakashi 0:8fdf9a60065b 2152 #define AXBS ((AXBS_Type *)AXBS_BASE)
kadonotakashi 0:8fdf9a60065b 2153 /** Array initializer of AXBS peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 2154 #define AXBS_BASE_ADDRS { AXBS_BASE }
kadonotakashi 0:8fdf9a60065b 2155 /** Array initializer of AXBS peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 2156 #define AXBS_BASE_PTRS { AXBS }
kadonotakashi 0:8fdf9a60065b 2157
kadonotakashi 0:8fdf9a60065b 2158 /*!
kadonotakashi 0:8fdf9a60065b 2159 * @}
kadonotakashi 0:8fdf9a60065b 2160 */ /* end of group AXBS_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 2161
kadonotakashi 0:8fdf9a60065b 2162
kadonotakashi 0:8fdf9a60065b 2163 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 2164 -- CAU Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 2165 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 2166
kadonotakashi 0:8fdf9a60065b 2167 /*!
kadonotakashi 0:8fdf9a60065b 2168 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 2169 * @{
kadonotakashi 0:8fdf9a60065b 2170 */
kadonotakashi 0:8fdf9a60065b 2171
kadonotakashi 0:8fdf9a60065b 2172 /** CAU - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 2173 typedef struct {
kadonotakashi 0:8fdf9a60065b 2174 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 2175 uint8_t RESERVED_0[2048];
kadonotakashi 0:8fdf9a60065b 2176 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
kadonotakashi 0:8fdf9a60065b 2177 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
kadonotakashi 0:8fdf9a60065b 2178 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 2179 uint8_t RESERVED_1[20];
kadonotakashi 0:8fdf9a60065b 2180 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
kadonotakashi 0:8fdf9a60065b 2181 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
kadonotakashi 0:8fdf9a60065b 2182 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 2183 uint8_t RESERVED_2[20];
kadonotakashi 0:8fdf9a60065b 2184 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
kadonotakashi 0:8fdf9a60065b 2185 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
kadonotakashi 0:8fdf9a60065b 2186 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 2187 uint8_t RESERVED_3[20];
kadonotakashi 0:8fdf9a60065b 2188 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
kadonotakashi 0:8fdf9a60065b 2189 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
kadonotakashi 0:8fdf9a60065b 2190 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 2191 uint8_t RESERVED_4[84];
kadonotakashi 0:8fdf9a60065b 2192 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
kadonotakashi 0:8fdf9a60065b 2193 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
kadonotakashi 0:8fdf9a60065b 2194 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 2195 uint8_t RESERVED_5[20];
kadonotakashi 0:8fdf9a60065b 2196 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
kadonotakashi 0:8fdf9a60065b 2197 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
kadonotakashi 0:8fdf9a60065b 2198 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 2199 uint8_t RESERVED_6[276];
kadonotakashi 0:8fdf9a60065b 2200 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
kadonotakashi 0:8fdf9a60065b 2201 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
kadonotakashi 0:8fdf9a60065b 2202 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 2203 uint8_t RESERVED_7[20];
kadonotakashi 0:8fdf9a60065b 2204 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
kadonotakashi 0:8fdf9a60065b 2205 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
kadonotakashi 0:8fdf9a60065b 2206 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 2207 } CAU_Type;
kadonotakashi 0:8fdf9a60065b 2208
kadonotakashi 0:8fdf9a60065b 2209 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 2210 -- CAU Register Masks
kadonotakashi 0:8fdf9a60065b 2211 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 2212
kadonotakashi 0:8fdf9a60065b 2213 /*!
kadonotakashi 0:8fdf9a60065b 2214 * @addtogroup CAU_Register_Masks CAU Register Masks
kadonotakashi 0:8fdf9a60065b 2215 * @{
kadonotakashi 0:8fdf9a60065b 2216 */
kadonotakashi 0:8fdf9a60065b 2217
kadonotakashi 0:8fdf9a60065b 2218 /*! @name DIRECT - Direct access register 0..Direct access register 15 */
kadonotakashi 0:8fdf9a60065b 2219 #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2220 #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2221 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
kadonotakashi 0:8fdf9a60065b 2222 #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2223 #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2224 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
kadonotakashi 0:8fdf9a60065b 2225 #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2226 #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2227 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
kadonotakashi 0:8fdf9a60065b 2228 #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2229 #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2230 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
kadonotakashi 0:8fdf9a60065b 2231 #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2232 #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2233 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
kadonotakashi 0:8fdf9a60065b 2234 #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2235 #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2236 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
kadonotakashi 0:8fdf9a60065b 2237 #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2238 #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2239 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
kadonotakashi 0:8fdf9a60065b 2240 #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2241 #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2242 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
kadonotakashi 0:8fdf9a60065b 2243 #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2244 #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2245 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
kadonotakashi 0:8fdf9a60065b 2246 #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2247 #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2248 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
kadonotakashi 0:8fdf9a60065b 2249 #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2250 #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2251 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
kadonotakashi 0:8fdf9a60065b 2252 #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2253 #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2254 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
kadonotakashi 0:8fdf9a60065b 2255 #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2256 #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2257 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
kadonotakashi 0:8fdf9a60065b 2258 #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2259 #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2260 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
kadonotakashi 0:8fdf9a60065b 2261 #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2262 #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2263 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
kadonotakashi 0:8fdf9a60065b 2264 #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2265 #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2266 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
kadonotakashi 0:8fdf9a60065b 2267
kadonotakashi 0:8fdf9a60065b 2268 /* The count of CAU_DIRECT */
kadonotakashi 0:8fdf9a60065b 2269 #define CAU_DIRECT_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 2270
kadonotakashi 0:8fdf9a60065b 2271 /*! @name LDR_CASR - Status register - Load Register command */
kadonotakashi 0:8fdf9a60065b 2272 #define CAU_LDR_CASR_IC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2273 #define CAU_LDR_CASR_IC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2274 #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
kadonotakashi 0:8fdf9a60065b 2275 #define CAU_LDR_CASR_DPE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 2276 #define CAU_LDR_CASR_DPE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 2277 #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
kadonotakashi 0:8fdf9a60065b 2278 #define CAU_LDR_CASR_VER_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 2279 #define CAU_LDR_CASR_VER_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 2280 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
kadonotakashi 0:8fdf9a60065b 2281
kadonotakashi 0:8fdf9a60065b 2282 /*! @name LDR_CAA - Accumulator register - Load Register command */
kadonotakashi 0:8fdf9a60065b 2283 #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2284 #define CAU_LDR_CAA_ACC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2285 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
kadonotakashi 0:8fdf9a60065b 2286
kadonotakashi 0:8fdf9a60065b 2287 /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
kadonotakashi 0:8fdf9a60065b 2288 #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2289 #define CAU_LDR_CA_CA0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2290 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
kadonotakashi 0:8fdf9a60065b 2291 #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2292 #define CAU_LDR_CA_CA1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2293 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
kadonotakashi 0:8fdf9a60065b 2294 #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2295 #define CAU_LDR_CA_CA2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2296 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
kadonotakashi 0:8fdf9a60065b 2297 #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2298 #define CAU_LDR_CA_CA3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2299 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
kadonotakashi 0:8fdf9a60065b 2300 #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2301 #define CAU_LDR_CA_CA4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2302 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
kadonotakashi 0:8fdf9a60065b 2303 #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2304 #define CAU_LDR_CA_CA5_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2305 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
kadonotakashi 0:8fdf9a60065b 2306 #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2307 #define CAU_LDR_CA_CA6_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2308 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
kadonotakashi 0:8fdf9a60065b 2309 #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2310 #define CAU_LDR_CA_CA7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2311 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
kadonotakashi 0:8fdf9a60065b 2312 #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2313 #define CAU_LDR_CA_CA8_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2314 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
kadonotakashi 0:8fdf9a60065b 2315
kadonotakashi 0:8fdf9a60065b 2316 /* The count of CAU_LDR_CA */
kadonotakashi 0:8fdf9a60065b 2317 #define CAU_LDR_CA_COUNT (9U)
kadonotakashi 0:8fdf9a60065b 2318
kadonotakashi 0:8fdf9a60065b 2319 /*! @name STR_CASR - Status register - Store Register command */
kadonotakashi 0:8fdf9a60065b 2320 #define CAU_STR_CASR_IC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2321 #define CAU_STR_CASR_IC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2322 #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
kadonotakashi 0:8fdf9a60065b 2323 #define CAU_STR_CASR_DPE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 2324 #define CAU_STR_CASR_DPE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 2325 #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
kadonotakashi 0:8fdf9a60065b 2326 #define CAU_STR_CASR_VER_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 2327 #define CAU_STR_CASR_VER_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 2328 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
kadonotakashi 0:8fdf9a60065b 2329
kadonotakashi 0:8fdf9a60065b 2330 /*! @name STR_CAA - Accumulator register - Store Register command */
kadonotakashi 0:8fdf9a60065b 2331 #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2332 #define CAU_STR_CAA_ACC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2333 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
kadonotakashi 0:8fdf9a60065b 2334
kadonotakashi 0:8fdf9a60065b 2335 /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
kadonotakashi 0:8fdf9a60065b 2336 #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2337 #define CAU_STR_CA_CA0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2338 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
kadonotakashi 0:8fdf9a60065b 2339 #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2340 #define CAU_STR_CA_CA1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2341 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
kadonotakashi 0:8fdf9a60065b 2342 #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2343 #define CAU_STR_CA_CA2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2344 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
kadonotakashi 0:8fdf9a60065b 2345 #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2346 #define CAU_STR_CA_CA3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2347 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
kadonotakashi 0:8fdf9a60065b 2348 #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2349 #define CAU_STR_CA_CA4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2350 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
kadonotakashi 0:8fdf9a60065b 2351 #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2352 #define CAU_STR_CA_CA5_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2353 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
kadonotakashi 0:8fdf9a60065b 2354 #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2355 #define CAU_STR_CA_CA6_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2356 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
kadonotakashi 0:8fdf9a60065b 2357 #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2358 #define CAU_STR_CA_CA7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2359 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
kadonotakashi 0:8fdf9a60065b 2360 #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2361 #define CAU_STR_CA_CA8_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2362 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
kadonotakashi 0:8fdf9a60065b 2363
kadonotakashi 0:8fdf9a60065b 2364 /* The count of CAU_STR_CA */
kadonotakashi 0:8fdf9a60065b 2365 #define CAU_STR_CA_COUNT (9U)
kadonotakashi 0:8fdf9a60065b 2366
kadonotakashi 0:8fdf9a60065b 2367 /*! @name ADR_CASR - Status register - Add Register command */
kadonotakashi 0:8fdf9a60065b 2368 #define CAU_ADR_CASR_IC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2369 #define CAU_ADR_CASR_IC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2370 #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
kadonotakashi 0:8fdf9a60065b 2371 #define CAU_ADR_CASR_DPE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 2372 #define CAU_ADR_CASR_DPE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 2373 #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
kadonotakashi 0:8fdf9a60065b 2374 #define CAU_ADR_CASR_VER_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 2375 #define CAU_ADR_CASR_VER_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 2376 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
kadonotakashi 0:8fdf9a60065b 2377
kadonotakashi 0:8fdf9a60065b 2378 /*! @name ADR_CAA - Accumulator register - Add to register command */
kadonotakashi 0:8fdf9a60065b 2379 #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2380 #define CAU_ADR_CAA_ACC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2381 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
kadonotakashi 0:8fdf9a60065b 2382
kadonotakashi 0:8fdf9a60065b 2383 /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
kadonotakashi 0:8fdf9a60065b 2384 #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2385 #define CAU_ADR_CA_CA0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2386 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
kadonotakashi 0:8fdf9a60065b 2387 #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2388 #define CAU_ADR_CA_CA1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2389 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
kadonotakashi 0:8fdf9a60065b 2390 #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2391 #define CAU_ADR_CA_CA2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2392 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
kadonotakashi 0:8fdf9a60065b 2393 #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2394 #define CAU_ADR_CA_CA3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2395 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
kadonotakashi 0:8fdf9a60065b 2396 #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2397 #define CAU_ADR_CA_CA4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2398 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
kadonotakashi 0:8fdf9a60065b 2399 #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2400 #define CAU_ADR_CA_CA5_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2401 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
kadonotakashi 0:8fdf9a60065b 2402 #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2403 #define CAU_ADR_CA_CA6_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2404 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
kadonotakashi 0:8fdf9a60065b 2405 #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2406 #define CAU_ADR_CA_CA7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2407 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
kadonotakashi 0:8fdf9a60065b 2408 #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2409 #define CAU_ADR_CA_CA8_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2410 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
kadonotakashi 0:8fdf9a60065b 2411
kadonotakashi 0:8fdf9a60065b 2412 /* The count of CAU_ADR_CA */
kadonotakashi 0:8fdf9a60065b 2413 #define CAU_ADR_CA_COUNT (9U)
kadonotakashi 0:8fdf9a60065b 2414
kadonotakashi 0:8fdf9a60065b 2415 /*! @name RADR_CASR - Status register - Reverse and Add to Register command */
kadonotakashi 0:8fdf9a60065b 2416 #define CAU_RADR_CASR_IC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2417 #define CAU_RADR_CASR_IC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2418 #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
kadonotakashi 0:8fdf9a60065b 2419 #define CAU_RADR_CASR_DPE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 2420 #define CAU_RADR_CASR_DPE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 2421 #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
kadonotakashi 0:8fdf9a60065b 2422 #define CAU_RADR_CASR_VER_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 2423 #define CAU_RADR_CASR_VER_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 2424 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
kadonotakashi 0:8fdf9a60065b 2425
kadonotakashi 0:8fdf9a60065b 2426 /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
kadonotakashi 0:8fdf9a60065b 2427 #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2428 #define CAU_RADR_CAA_ACC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2429 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
kadonotakashi 0:8fdf9a60065b 2430
kadonotakashi 0:8fdf9a60065b 2431 /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
kadonotakashi 0:8fdf9a60065b 2432 #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2433 #define CAU_RADR_CA_CA0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2434 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
kadonotakashi 0:8fdf9a60065b 2435 #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2436 #define CAU_RADR_CA_CA1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2437 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
kadonotakashi 0:8fdf9a60065b 2438 #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2439 #define CAU_RADR_CA_CA2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2440 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
kadonotakashi 0:8fdf9a60065b 2441 #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2442 #define CAU_RADR_CA_CA3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2443 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
kadonotakashi 0:8fdf9a60065b 2444 #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2445 #define CAU_RADR_CA_CA4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2446 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
kadonotakashi 0:8fdf9a60065b 2447 #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2448 #define CAU_RADR_CA_CA5_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2449 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
kadonotakashi 0:8fdf9a60065b 2450 #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2451 #define CAU_RADR_CA_CA6_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2452 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
kadonotakashi 0:8fdf9a60065b 2453 #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2454 #define CAU_RADR_CA_CA7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2455 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
kadonotakashi 0:8fdf9a60065b 2456 #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2457 #define CAU_RADR_CA_CA8_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2458 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
kadonotakashi 0:8fdf9a60065b 2459
kadonotakashi 0:8fdf9a60065b 2460 /* The count of CAU_RADR_CA */
kadonotakashi 0:8fdf9a60065b 2461 #define CAU_RADR_CA_COUNT (9U)
kadonotakashi 0:8fdf9a60065b 2462
kadonotakashi 0:8fdf9a60065b 2463 /*! @name XOR_CASR - Status register - Exclusive Or command */
kadonotakashi 0:8fdf9a60065b 2464 #define CAU_XOR_CASR_IC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2465 #define CAU_XOR_CASR_IC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2466 #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
kadonotakashi 0:8fdf9a60065b 2467 #define CAU_XOR_CASR_DPE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 2468 #define CAU_XOR_CASR_DPE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 2469 #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
kadonotakashi 0:8fdf9a60065b 2470 #define CAU_XOR_CASR_VER_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 2471 #define CAU_XOR_CASR_VER_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 2472 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
kadonotakashi 0:8fdf9a60065b 2473
kadonotakashi 0:8fdf9a60065b 2474 /*! @name XOR_CAA - Accumulator register - Exclusive Or command */
kadonotakashi 0:8fdf9a60065b 2475 #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2476 #define CAU_XOR_CAA_ACC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2477 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
kadonotakashi 0:8fdf9a60065b 2478
kadonotakashi 0:8fdf9a60065b 2479 /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
kadonotakashi 0:8fdf9a60065b 2480 #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2481 #define CAU_XOR_CA_CA0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2482 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
kadonotakashi 0:8fdf9a60065b 2483 #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2484 #define CAU_XOR_CA_CA1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2485 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
kadonotakashi 0:8fdf9a60065b 2486 #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2487 #define CAU_XOR_CA_CA2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2488 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
kadonotakashi 0:8fdf9a60065b 2489 #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2490 #define CAU_XOR_CA_CA3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2491 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
kadonotakashi 0:8fdf9a60065b 2492 #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2493 #define CAU_XOR_CA_CA4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2494 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
kadonotakashi 0:8fdf9a60065b 2495 #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2496 #define CAU_XOR_CA_CA5_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2497 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
kadonotakashi 0:8fdf9a60065b 2498 #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2499 #define CAU_XOR_CA_CA6_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2500 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
kadonotakashi 0:8fdf9a60065b 2501 #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2502 #define CAU_XOR_CA_CA7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2503 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
kadonotakashi 0:8fdf9a60065b 2504 #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2505 #define CAU_XOR_CA_CA8_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2506 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
kadonotakashi 0:8fdf9a60065b 2507
kadonotakashi 0:8fdf9a60065b 2508 /* The count of CAU_XOR_CA */
kadonotakashi 0:8fdf9a60065b 2509 #define CAU_XOR_CA_COUNT (9U)
kadonotakashi 0:8fdf9a60065b 2510
kadonotakashi 0:8fdf9a60065b 2511 /*! @name ROTL_CASR - Status register - Rotate Left command */
kadonotakashi 0:8fdf9a60065b 2512 #define CAU_ROTL_CASR_IC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2513 #define CAU_ROTL_CASR_IC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2514 #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
kadonotakashi 0:8fdf9a60065b 2515 #define CAU_ROTL_CASR_DPE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 2516 #define CAU_ROTL_CASR_DPE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 2517 #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
kadonotakashi 0:8fdf9a60065b 2518 #define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 2519 #define CAU_ROTL_CASR_VER_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 2520 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
kadonotakashi 0:8fdf9a60065b 2521
kadonotakashi 0:8fdf9a60065b 2522 /*! @name ROTL_CAA - Accumulator register - Rotate Left command */
kadonotakashi 0:8fdf9a60065b 2523 #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2524 #define CAU_ROTL_CAA_ACC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2525 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
kadonotakashi 0:8fdf9a60065b 2526
kadonotakashi 0:8fdf9a60065b 2527 /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
kadonotakashi 0:8fdf9a60065b 2528 #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2529 #define CAU_ROTL_CA_CA0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2530 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
kadonotakashi 0:8fdf9a60065b 2531 #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2532 #define CAU_ROTL_CA_CA1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2533 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
kadonotakashi 0:8fdf9a60065b 2534 #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2535 #define CAU_ROTL_CA_CA2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2536 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
kadonotakashi 0:8fdf9a60065b 2537 #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2538 #define CAU_ROTL_CA_CA3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2539 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
kadonotakashi 0:8fdf9a60065b 2540 #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2541 #define CAU_ROTL_CA_CA4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2542 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
kadonotakashi 0:8fdf9a60065b 2543 #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2544 #define CAU_ROTL_CA_CA5_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2545 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
kadonotakashi 0:8fdf9a60065b 2546 #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2547 #define CAU_ROTL_CA_CA6_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2548 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
kadonotakashi 0:8fdf9a60065b 2549 #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2550 #define CAU_ROTL_CA_CA7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2551 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
kadonotakashi 0:8fdf9a60065b 2552 #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2553 #define CAU_ROTL_CA_CA8_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2554 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
kadonotakashi 0:8fdf9a60065b 2555
kadonotakashi 0:8fdf9a60065b 2556 /* The count of CAU_ROTL_CA */
kadonotakashi 0:8fdf9a60065b 2557 #define CAU_ROTL_CA_COUNT (9U)
kadonotakashi 0:8fdf9a60065b 2558
kadonotakashi 0:8fdf9a60065b 2559 /*! @name AESC_CASR - Status register - AES Column Operation command */
kadonotakashi 0:8fdf9a60065b 2560 #define CAU_AESC_CASR_IC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2561 #define CAU_AESC_CASR_IC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2562 #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
kadonotakashi 0:8fdf9a60065b 2563 #define CAU_AESC_CASR_DPE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 2564 #define CAU_AESC_CASR_DPE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 2565 #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
kadonotakashi 0:8fdf9a60065b 2566 #define CAU_AESC_CASR_VER_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 2567 #define CAU_AESC_CASR_VER_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 2568 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
kadonotakashi 0:8fdf9a60065b 2569
kadonotakashi 0:8fdf9a60065b 2570 /*! @name AESC_CAA - Accumulator register - AES Column Operation command */
kadonotakashi 0:8fdf9a60065b 2571 #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2572 #define CAU_AESC_CAA_ACC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2573 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
kadonotakashi 0:8fdf9a60065b 2574
kadonotakashi 0:8fdf9a60065b 2575 /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
kadonotakashi 0:8fdf9a60065b 2576 #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2577 #define CAU_AESC_CA_CA0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2578 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
kadonotakashi 0:8fdf9a60065b 2579 #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2580 #define CAU_AESC_CA_CA1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2581 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
kadonotakashi 0:8fdf9a60065b 2582 #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2583 #define CAU_AESC_CA_CA2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2584 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
kadonotakashi 0:8fdf9a60065b 2585 #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2586 #define CAU_AESC_CA_CA3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2587 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
kadonotakashi 0:8fdf9a60065b 2588 #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2589 #define CAU_AESC_CA_CA4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2590 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
kadonotakashi 0:8fdf9a60065b 2591 #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2592 #define CAU_AESC_CA_CA5_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2593 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
kadonotakashi 0:8fdf9a60065b 2594 #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2595 #define CAU_AESC_CA_CA6_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2596 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
kadonotakashi 0:8fdf9a60065b 2597 #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2598 #define CAU_AESC_CA_CA7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2599 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
kadonotakashi 0:8fdf9a60065b 2600 #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2601 #define CAU_AESC_CA_CA8_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2602 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
kadonotakashi 0:8fdf9a60065b 2603
kadonotakashi 0:8fdf9a60065b 2604 /* The count of CAU_AESC_CA */
kadonotakashi 0:8fdf9a60065b 2605 #define CAU_AESC_CA_COUNT (9U)
kadonotakashi 0:8fdf9a60065b 2606
kadonotakashi 0:8fdf9a60065b 2607 /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
kadonotakashi 0:8fdf9a60065b 2608 #define CAU_AESIC_CASR_IC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2609 #define CAU_AESIC_CASR_IC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2610 #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
kadonotakashi 0:8fdf9a60065b 2611 #define CAU_AESIC_CASR_DPE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 2612 #define CAU_AESIC_CASR_DPE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 2613 #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
kadonotakashi 0:8fdf9a60065b 2614 #define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 2615 #define CAU_AESIC_CASR_VER_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 2616 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
kadonotakashi 0:8fdf9a60065b 2617
kadonotakashi 0:8fdf9a60065b 2618 /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
kadonotakashi 0:8fdf9a60065b 2619 #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2620 #define CAU_AESIC_CAA_ACC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2621 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
kadonotakashi 0:8fdf9a60065b 2622
kadonotakashi 0:8fdf9a60065b 2623 /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
kadonotakashi 0:8fdf9a60065b 2624 #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2625 #define CAU_AESIC_CA_CA0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2626 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
kadonotakashi 0:8fdf9a60065b 2627 #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2628 #define CAU_AESIC_CA_CA1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2629 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
kadonotakashi 0:8fdf9a60065b 2630 #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2631 #define CAU_AESIC_CA_CA2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2632 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
kadonotakashi 0:8fdf9a60065b 2633 #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2634 #define CAU_AESIC_CA_CA3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2635 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
kadonotakashi 0:8fdf9a60065b 2636 #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2637 #define CAU_AESIC_CA_CA4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2638 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
kadonotakashi 0:8fdf9a60065b 2639 #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2640 #define CAU_AESIC_CA_CA5_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2641 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
kadonotakashi 0:8fdf9a60065b 2642 #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2643 #define CAU_AESIC_CA_CA6_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2644 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
kadonotakashi 0:8fdf9a60065b 2645 #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2646 #define CAU_AESIC_CA_CA7_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2647 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
kadonotakashi 0:8fdf9a60065b 2648 #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 2649 #define CAU_AESIC_CA_CA8_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2650 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
kadonotakashi 0:8fdf9a60065b 2651
kadonotakashi 0:8fdf9a60065b 2652 /* The count of CAU_AESIC_CA */
kadonotakashi 0:8fdf9a60065b 2653 #define CAU_AESIC_CA_COUNT (9U)
kadonotakashi 0:8fdf9a60065b 2654
kadonotakashi 0:8fdf9a60065b 2655
kadonotakashi 0:8fdf9a60065b 2656 /*!
kadonotakashi 0:8fdf9a60065b 2657 * @}
kadonotakashi 0:8fdf9a60065b 2658 */ /* end of group CAU_Register_Masks */
kadonotakashi 0:8fdf9a60065b 2659
kadonotakashi 0:8fdf9a60065b 2660
kadonotakashi 0:8fdf9a60065b 2661 /* CAU - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 2662 /** Peripheral CAU base address */
kadonotakashi 0:8fdf9a60065b 2663 #define CAU_BASE (0xE0081000u)
kadonotakashi 0:8fdf9a60065b 2664 /** Peripheral CAU base pointer */
kadonotakashi 0:8fdf9a60065b 2665 #define CAU ((CAU_Type *)CAU_BASE)
kadonotakashi 0:8fdf9a60065b 2666 /** Array initializer of CAU peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 2667 #define CAU_BASE_ADDRS { CAU_BASE }
kadonotakashi 0:8fdf9a60065b 2668 /** Array initializer of CAU peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 2669 #define CAU_BASE_PTRS { CAU }
kadonotakashi 0:8fdf9a60065b 2670
kadonotakashi 0:8fdf9a60065b 2671 /*!
kadonotakashi 0:8fdf9a60065b 2672 * @}
kadonotakashi 0:8fdf9a60065b 2673 */ /* end of group CAU_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 2674
kadonotakashi 0:8fdf9a60065b 2675
kadonotakashi 0:8fdf9a60065b 2676 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 2677 -- CMP Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 2678 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 2679
kadonotakashi 0:8fdf9a60065b 2680 /*!
kadonotakashi 0:8fdf9a60065b 2681 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 2682 * @{
kadonotakashi 0:8fdf9a60065b 2683 */
kadonotakashi 0:8fdf9a60065b 2684
kadonotakashi 0:8fdf9a60065b 2685 /** CMP - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 2686 typedef struct {
kadonotakashi 0:8fdf9a60065b 2687 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 2688 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 2689 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 2690 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
kadonotakashi 0:8fdf9a60065b 2691 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 2692 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
kadonotakashi 0:8fdf9a60065b 2693 } CMP_Type;
kadonotakashi 0:8fdf9a60065b 2694
kadonotakashi 0:8fdf9a60065b 2695 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 2696 -- CMP Register Masks
kadonotakashi 0:8fdf9a60065b 2697 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 2698
kadonotakashi 0:8fdf9a60065b 2699 /*!
kadonotakashi 0:8fdf9a60065b 2700 * @addtogroup CMP_Register_Masks CMP Register Masks
kadonotakashi 0:8fdf9a60065b 2701 * @{
kadonotakashi 0:8fdf9a60065b 2702 */
kadonotakashi 0:8fdf9a60065b 2703
kadonotakashi 0:8fdf9a60065b 2704 /*! @name CR0 - CMP Control Register 0 */
kadonotakashi 0:8fdf9a60065b 2705 #define CMP_CR0_HYSTCTR_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 2706 #define CMP_CR0_HYSTCTR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2707 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
kadonotakashi 0:8fdf9a60065b 2708 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
kadonotakashi 0:8fdf9a60065b 2709 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 2710 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
kadonotakashi 0:8fdf9a60065b 2711
kadonotakashi 0:8fdf9a60065b 2712 /*! @name CR1 - CMP Control Register 1 */
kadonotakashi 0:8fdf9a60065b 2713 #define CMP_CR1_EN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2714 #define CMP_CR1_EN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2715 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
kadonotakashi 0:8fdf9a60065b 2716 #define CMP_CR1_OPE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 2717 #define CMP_CR1_OPE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 2718 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
kadonotakashi 0:8fdf9a60065b 2719 #define CMP_CR1_COS_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 2720 #define CMP_CR1_COS_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 2721 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
kadonotakashi 0:8fdf9a60065b 2722 #define CMP_CR1_INV_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 2723 #define CMP_CR1_INV_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 2724 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
kadonotakashi 0:8fdf9a60065b 2725 #define CMP_CR1_PMODE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 2726 #define CMP_CR1_PMODE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 2727 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
kadonotakashi 0:8fdf9a60065b 2728 #define CMP_CR1_TRIGM_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 2729 #define CMP_CR1_TRIGM_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 2730 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
kadonotakashi 0:8fdf9a60065b 2731 #define CMP_CR1_WE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 2732 #define CMP_CR1_WE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 2733 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
kadonotakashi 0:8fdf9a60065b 2734 #define CMP_CR1_SE_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 2735 #define CMP_CR1_SE_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 2736 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
kadonotakashi 0:8fdf9a60065b 2737
kadonotakashi 0:8fdf9a60065b 2738 /*! @name FPR - CMP Filter Period Register */
kadonotakashi 0:8fdf9a60065b 2739 #define CMP_FPR_FILT_PER_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 2740 #define CMP_FPR_FILT_PER_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2741 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
kadonotakashi 0:8fdf9a60065b 2742
kadonotakashi 0:8fdf9a60065b 2743 /*! @name SCR - CMP Status and Control Register */
kadonotakashi 0:8fdf9a60065b 2744 #define CMP_SCR_COUT_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2745 #define CMP_SCR_COUT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2746 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
kadonotakashi 0:8fdf9a60065b 2747 #define CMP_SCR_CFF_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 2748 #define CMP_SCR_CFF_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 2749 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
kadonotakashi 0:8fdf9a60065b 2750 #define CMP_SCR_CFR_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 2751 #define CMP_SCR_CFR_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 2752 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
kadonotakashi 0:8fdf9a60065b 2753 #define CMP_SCR_IEF_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 2754 #define CMP_SCR_IEF_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 2755 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
kadonotakashi 0:8fdf9a60065b 2756 #define CMP_SCR_IER_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 2757 #define CMP_SCR_IER_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 2758 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
kadonotakashi 0:8fdf9a60065b 2759 #define CMP_SCR_DMAEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 2760 #define CMP_SCR_DMAEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 2761 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
kadonotakashi 0:8fdf9a60065b 2762
kadonotakashi 0:8fdf9a60065b 2763 /*! @name DACCR - DAC Control Register */
kadonotakashi 0:8fdf9a60065b 2764 #define CMP_DACCR_VOSEL_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 2765 #define CMP_DACCR_VOSEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2766 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
kadonotakashi 0:8fdf9a60065b 2767 #define CMP_DACCR_VRSEL_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 2768 #define CMP_DACCR_VRSEL_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 2769 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
kadonotakashi 0:8fdf9a60065b 2770 #define CMP_DACCR_DACEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 2771 #define CMP_DACCR_DACEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 2772 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
kadonotakashi 0:8fdf9a60065b 2773
kadonotakashi 0:8fdf9a60065b 2774 /*! @name MUXCR - MUX Control Register */
kadonotakashi 0:8fdf9a60065b 2775 #define CMP_MUXCR_MSEL_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 2776 #define CMP_MUXCR_MSEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2777 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
kadonotakashi 0:8fdf9a60065b 2778 #define CMP_MUXCR_PSEL_MASK (0x38U)
kadonotakashi 0:8fdf9a60065b 2779 #define CMP_MUXCR_PSEL_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 2780 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
kadonotakashi 0:8fdf9a60065b 2781
kadonotakashi 0:8fdf9a60065b 2782
kadonotakashi 0:8fdf9a60065b 2783 /*!
kadonotakashi 0:8fdf9a60065b 2784 * @}
kadonotakashi 0:8fdf9a60065b 2785 */ /* end of group CMP_Register_Masks */
kadonotakashi 0:8fdf9a60065b 2786
kadonotakashi 0:8fdf9a60065b 2787
kadonotakashi 0:8fdf9a60065b 2788 /* CMP - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 2789 /** Peripheral CMP0 base address */
kadonotakashi 0:8fdf9a60065b 2790 #define CMP0_BASE (0x40073000u)
kadonotakashi 0:8fdf9a60065b 2791 /** Peripheral CMP0 base pointer */
kadonotakashi 0:8fdf9a60065b 2792 #define CMP0 ((CMP_Type *)CMP0_BASE)
kadonotakashi 0:8fdf9a60065b 2793 /** Peripheral CMP1 base address */
kadonotakashi 0:8fdf9a60065b 2794 #define CMP1_BASE (0x40073008u)
kadonotakashi 0:8fdf9a60065b 2795 /** Peripheral CMP1 base pointer */
kadonotakashi 0:8fdf9a60065b 2796 #define CMP1 ((CMP_Type *)CMP1_BASE)
kadonotakashi 0:8fdf9a60065b 2797 /** Array initializer of CMP peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 2798 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
kadonotakashi 0:8fdf9a60065b 2799 /** Array initializer of CMP peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 2800 #define CMP_BASE_PTRS { CMP0, CMP1 }
kadonotakashi 0:8fdf9a60065b 2801 /** Interrupt vectors for the CMP peripheral type */
kadonotakashi 0:8fdf9a60065b 2802 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
kadonotakashi 0:8fdf9a60065b 2803
kadonotakashi 0:8fdf9a60065b 2804 /*!
kadonotakashi 0:8fdf9a60065b 2805 * @}
kadonotakashi 0:8fdf9a60065b 2806 */ /* end of group CMP_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 2807
kadonotakashi 0:8fdf9a60065b 2808
kadonotakashi 0:8fdf9a60065b 2809 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 2810 -- CMT Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 2811 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 2812
kadonotakashi 0:8fdf9a60065b 2813 /*!
kadonotakashi 0:8fdf9a60065b 2814 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 2815 * @{
kadonotakashi 0:8fdf9a60065b 2816 */
kadonotakashi 0:8fdf9a60065b 2817
kadonotakashi 0:8fdf9a60065b 2818 /** CMT - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 2819 typedef struct {
kadonotakashi 0:8fdf9a60065b 2820 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 2821 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 2822 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 2823 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
kadonotakashi 0:8fdf9a60065b 2824 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 2825 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
kadonotakashi 0:8fdf9a60065b 2826 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
kadonotakashi 0:8fdf9a60065b 2827 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
kadonotakashi 0:8fdf9a60065b 2828 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 2829 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
kadonotakashi 0:8fdf9a60065b 2830 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
kadonotakashi 0:8fdf9a60065b 2831 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
kadonotakashi 0:8fdf9a60065b 2832 } CMT_Type;
kadonotakashi 0:8fdf9a60065b 2833
kadonotakashi 0:8fdf9a60065b 2834 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 2835 -- CMT Register Masks
kadonotakashi 0:8fdf9a60065b 2836 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 2837
kadonotakashi 0:8fdf9a60065b 2838 /*!
kadonotakashi 0:8fdf9a60065b 2839 * @addtogroup CMT_Register_Masks CMT Register Masks
kadonotakashi 0:8fdf9a60065b 2840 * @{
kadonotakashi 0:8fdf9a60065b 2841 */
kadonotakashi 0:8fdf9a60065b 2842
kadonotakashi 0:8fdf9a60065b 2843 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
kadonotakashi 0:8fdf9a60065b 2844 #define CMT_CGH1_PH_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 2845 #define CMT_CGH1_PH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2846 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
kadonotakashi 0:8fdf9a60065b 2847
kadonotakashi 0:8fdf9a60065b 2848 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
kadonotakashi 0:8fdf9a60065b 2849 #define CMT_CGL1_PL_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 2850 #define CMT_CGL1_PL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2851 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
kadonotakashi 0:8fdf9a60065b 2852
kadonotakashi 0:8fdf9a60065b 2853 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
kadonotakashi 0:8fdf9a60065b 2854 #define CMT_CGH2_SH_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 2855 #define CMT_CGH2_SH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2856 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
kadonotakashi 0:8fdf9a60065b 2857
kadonotakashi 0:8fdf9a60065b 2858 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
kadonotakashi 0:8fdf9a60065b 2859 #define CMT_CGL2_SL_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 2860 #define CMT_CGL2_SL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2861 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
kadonotakashi 0:8fdf9a60065b 2862
kadonotakashi 0:8fdf9a60065b 2863 /*! @name OC - CMT Output Control Register */
kadonotakashi 0:8fdf9a60065b 2864 #define CMT_OC_IROPEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 2865 #define CMT_OC_IROPEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 2866 #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
kadonotakashi 0:8fdf9a60065b 2867 #define CMT_OC_CMTPOL_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 2868 #define CMT_OC_CMTPOL_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 2869 #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
kadonotakashi 0:8fdf9a60065b 2870 #define CMT_OC_IROL_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 2871 #define CMT_OC_IROL_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 2872 #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
kadonotakashi 0:8fdf9a60065b 2873
kadonotakashi 0:8fdf9a60065b 2874 /*! @name MSC - CMT Modulator Status and Control Register */
kadonotakashi 0:8fdf9a60065b 2875 #define CMT_MSC_MCGEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2876 #define CMT_MSC_MCGEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2877 #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
kadonotakashi 0:8fdf9a60065b 2878 #define CMT_MSC_EOCIE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 2879 #define CMT_MSC_EOCIE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 2880 #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
kadonotakashi 0:8fdf9a60065b 2881 #define CMT_MSC_FSK_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 2882 #define CMT_MSC_FSK_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 2883 #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
kadonotakashi 0:8fdf9a60065b 2884 #define CMT_MSC_BASE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 2885 #define CMT_MSC_BASE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 2886 #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
kadonotakashi 0:8fdf9a60065b 2887 #define CMT_MSC_EXSPC_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 2888 #define CMT_MSC_EXSPC_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 2889 #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
kadonotakashi 0:8fdf9a60065b 2890 #define CMT_MSC_CMTDIV_MASK (0x60U)
kadonotakashi 0:8fdf9a60065b 2891 #define CMT_MSC_CMTDIV_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 2892 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
kadonotakashi 0:8fdf9a60065b 2893 #define CMT_MSC_EOCF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 2894 #define CMT_MSC_EOCF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 2895 #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
kadonotakashi 0:8fdf9a60065b 2896
kadonotakashi 0:8fdf9a60065b 2897 /*! @name CMD1 - CMT Modulator Data Register Mark High */
kadonotakashi 0:8fdf9a60065b 2898 #define CMT_CMD1_MB_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 2899 #define CMT_CMD1_MB_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2900 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
kadonotakashi 0:8fdf9a60065b 2901
kadonotakashi 0:8fdf9a60065b 2902 /*! @name CMD2 - CMT Modulator Data Register Mark Low */
kadonotakashi 0:8fdf9a60065b 2903 #define CMT_CMD2_MB_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 2904 #define CMT_CMD2_MB_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2905 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
kadonotakashi 0:8fdf9a60065b 2906
kadonotakashi 0:8fdf9a60065b 2907 /*! @name CMD3 - CMT Modulator Data Register Space High */
kadonotakashi 0:8fdf9a60065b 2908 #define CMT_CMD3_SB_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 2909 #define CMT_CMD3_SB_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2910 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
kadonotakashi 0:8fdf9a60065b 2911
kadonotakashi 0:8fdf9a60065b 2912 /*! @name CMD4 - CMT Modulator Data Register Space Low */
kadonotakashi 0:8fdf9a60065b 2913 #define CMT_CMD4_SB_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 2914 #define CMT_CMD4_SB_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2915 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
kadonotakashi 0:8fdf9a60065b 2916
kadonotakashi 0:8fdf9a60065b 2917 /*! @name PPS - CMT Primary Prescaler Register */
kadonotakashi 0:8fdf9a60065b 2918 #define CMT_PPS_PPSDIV_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 2919 #define CMT_PPS_PPSDIV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2920 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
kadonotakashi 0:8fdf9a60065b 2921
kadonotakashi 0:8fdf9a60065b 2922 /*! @name DMA - CMT Direct Memory Access Register */
kadonotakashi 0:8fdf9a60065b 2923 #define CMT_DMA_DMA_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 2924 #define CMT_DMA_DMA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 2925 #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
kadonotakashi 0:8fdf9a60065b 2926
kadonotakashi 0:8fdf9a60065b 2927
kadonotakashi 0:8fdf9a60065b 2928 /*!
kadonotakashi 0:8fdf9a60065b 2929 * @}
kadonotakashi 0:8fdf9a60065b 2930 */ /* end of group CMT_Register_Masks */
kadonotakashi 0:8fdf9a60065b 2931
kadonotakashi 0:8fdf9a60065b 2932
kadonotakashi 0:8fdf9a60065b 2933 /* CMT - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 2934 /** Peripheral CMT base address */
kadonotakashi 0:8fdf9a60065b 2935 #define CMT_BASE (0x40062000u)
kadonotakashi 0:8fdf9a60065b 2936 /** Peripheral CMT base pointer */
kadonotakashi 0:8fdf9a60065b 2937 #define CMT ((CMT_Type *)CMT_BASE)
kadonotakashi 0:8fdf9a60065b 2938 /** Array initializer of CMT peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 2939 #define CMT_BASE_ADDRS { CMT_BASE }
kadonotakashi 0:8fdf9a60065b 2940 /** Array initializer of CMT peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 2941 #define CMT_BASE_PTRS { CMT }
kadonotakashi 0:8fdf9a60065b 2942 /** Interrupt vectors for the CMT peripheral type */
kadonotakashi 0:8fdf9a60065b 2943 #define CMT_IRQS { CMT_IRQn }
kadonotakashi 0:8fdf9a60065b 2944
kadonotakashi 0:8fdf9a60065b 2945 /*!
kadonotakashi 0:8fdf9a60065b 2946 * @}
kadonotakashi 0:8fdf9a60065b 2947 */ /* end of group CMT_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 2948
kadonotakashi 0:8fdf9a60065b 2949
kadonotakashi 0:8fdf9a60065b 2950 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 2951 -- CRC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 2952 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 2953
kadonotakashi 0:8fdf9a60065b 2954 /*!
kadonotakashi 0:8fdf9a60065b 2955 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 2956 * @{
kadonotakashi 0:8fdf9a60065b 2957 */
kadonotakashi 0:8fdf9a60065b 2958
kadonotakashi 0:8fdf9a60065b 2959 /** CRC - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 2960 typedef struct {
kadonotakashi 0:8fdf9a60065b 2961 union { /* offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 2962 struct { /* offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 2963 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 2964 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 2965 } ACCESS16BIT;
kadonotakashi 0:8fdf9a60065b 2966 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 2967 struct { /* offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 2968 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 2969 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 2970 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 2971 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
kadonotakashi 0:8fdf9a60065b 2972 } ACCESS8BIT;
kadonotakashi 0:8fdf9a60065b 2973 };
kadonotakashi 0:8fdf9a60065b 2974 union { /* offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 2975 struct { /* offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 2976 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 2977 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
kadonotakashi 0:8fdf9a60065b 2978 } GPOLY_ACCESS16BIT;
kadonotakashi 0:8fdf9a60065b 2979 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 2980 struct { /* offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 2981 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 2982 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
kadonotakashi 0:8fdf9a60065b 2983 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
kadonotakashi 0:8fdf9a60065b 2984 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
kadonotakashi 0:8fdf9a60065b 2985 } GPOLY_ACCESS8BIT;
kadonotakashi 0:8fdf9a60065b 2986 };
kadonotakashi 0:8fdf9a60065b 2987 union { /* offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 2988 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 2989 struct { /* offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 2990 uint8_t RESERVED_0[3];
kadonotakashi 0:8fdf9a60065b 2991 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
kadonotakashi 0:8fdf9a60065b 2992 } CTRL_ACCESS8BIT;
kadonotakashi 0:8fdf9a60065b 2993 };
kadonotakashi 0:8fdf9a60065b 2994 } CRC_Type;
kadonotakashi 0:8fdf9a60065b 2995
kadonotakashi 0:8fdf9a60065b 2996 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 2997 -- CRC Register Masks
kadonotakashi 0:8fdf9a60065b 2998 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 2999
kadonotakashi 0:8fdf9a60065b 3000 /*!
kadonotakashi 0:8fdf9a60065b 3001 * @addtogroup CRC_Register_Masks CRC Register Masks
kadonotakashi 0:8fdf9a60065b 3002 * @{
kadonotakashi 0:8fdf9a60065b 3003 */
kadonotakashi 0:8fdf9a60065b 3004
kadonotakashi 0:8fdf9a60065b 3005 /*! @name DATAL - CRC_DATAL register. */
kadonotakashi 0:8fdf9a60065b 3006 #define CRC_DATAL_DATAL_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 3007 #define CRC_DATAL_DATAL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3008 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
kadonotakashi 0:8fdf9a60065b 3009
kadonotakashi 0:8fdf9a60065b 3010 /*! @name DATAH - CRC_DATAH register. */
kadonotakashi 0:8fdf9a60065b 3011 #define CRC_DATAH_DATAH_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 3012 #define CRC_DATAH_DATAH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3013 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
kadonotakashi 0:8fdf9a60065b 3014
kadonotakashi 0:8fdf9a60065b 3015 /*! @name DATA - CRC Data register */
kadonotakashi 0:8fdf9a60065b 3016 #define CRC_DATA_LL_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 3017 #define CRC_DATA_LL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3018 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
kadonotakashi 0:8fdf9a60065b 3019 #define CRC_DATA_LU_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 3020 #define CRC_DATA_LU_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 3021 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
kadonotakashi 0:8fdf9a60065b 3022 #define CRC_DATA_HL_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 3023 #define CRC_DATA_HL_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 3024 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
kadonotakashi 0:8fdf9a60065b 3025 #define CRC_DATA_HU_MASK (0xFF000000U)
kadonotakashi 0:8fdf9a60065b 3026 #define CRC_DATA_HU_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 3027 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
kadonotakashi 0:8fdf9a60065b 3028
kadonotakashi 0:8fdf9a60065b 3029 /*! @name DATALL - CRC_DATALL register. */
kadonotakashi 0:8fdf9a60065b 3030 #define CRC_DATALL_DATALL_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 3031 #define CRC_DATALL_DATALL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3032 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
kadonotakashi 0:8fdf9a60065b 3033
kadonotakashi 0:8fdf9a60065b 3034 /*! @name DATALU - CRC_DATALU register. */
kadonotakashi 0:8fdf9a60065b 3035 #define CRC_DATALU_DATALU_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 3036 #define CRC_DATALU_DATALU_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3037 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
kadonotakashi 0:8fdf9a60065b 3038
kadonotakashi 0:8fdf9a60065b 3039 /*! @name DATAHL - CRC_DATAHL register. */
kadonotakashi 0:8fdf9a60065b 3040 #define CRC_DATAHL_DATAHL_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 3041 #define CRC_DATAHL_DATAHL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3042 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
kadonotakashi 0:8fdf9a60065b 3043
kadonotakashi 0:8fdf9a60065b 3044 /*! @name DATAHU - CRC_DATAHU register. */
kadonotakashi 0:8fdf9a60065b 3045 #define CRC_DATAHU_DATAHU_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 3046 #define CRC_DATAHU_DATAHU_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3047 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
kadonotakashi 0:8fdf9a60065b 3048
kadonotakashi 0:8fdf9a60065b 3049 /*! @name GPOLYL - CRC_GPOLYL register. */
kadonotakashi 0:8fdf9a60065b 3050 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 3051 #define CRC_GPOLYL_GPOLYL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3052 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
kadonotakashi 0:8fdf9a60065b 3053
kadonotakashi 0:8fdf9a60065b 3054 /*! @name GPOLYH - CRC_GPOLYH register. */
kadonotakashi 0:8fdf9a60065b 3055 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 3056 #define CRC_GPOLYH_GPOLYH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3057 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
kadonotakashi 0:8fdf9a60065b 3058
kadonotakashi 0:8fdf9a60065b 3059 /*! @name GPOLY - CRC Polynomial register */
kadonotakashi 0:8fdf9a60065b 3060 #define CRC_GPOLY_LOW_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 3061 #define CRC_GPOLY_LOW_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3062 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
kadonotakashi 0:8fdf9a60065b 3063 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 3064 #define CRC_GPOLY_HIGH_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 3065 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
kadonotakashi 0:8fdf9a60065b 3066
kadonotakashi 0:8fdf9a60065b 3067 /*! @name GPOLYLL - CRC_GPOLYLL register. */
kadonotakashi 0:8fdf9a60065b 3068 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 3069 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3070 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
kadonotakashi 0:8fdf9a60065b 3071
kadonotakashi 0:8fdf9a60065b 3072 /*! @name GPOLYLU - CRC_GPOLYLU register. */
kadonotakashi 0:8fdf9a60065b 3073 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 3074 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3075 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
kadonotakashi 0:8fdf9a60065b 3076
kadonotakashi 0:8fdf9a60065b 3077 /*! @name GPOLYHL - CRC_GPOLYHL register. */
kadonotakashi 0:8fdf9a60065b 3078 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 3079 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3080 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
kadonotakashi 0:8fdf9a60065b 3081
kadonotakashi 0:8fdf9a60065b 3082 /*! @name GPOLYHU - CRC_GPOLYHU register. */
kadonotakashi 0:8fdf9a60065b 3083 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 3084 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3085 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
kadonotakashi 0:8fdf9a60065b 3086
kadonotakashi 0:8fdf9a60065b 3087 /*! @name CTRL - CRC Control register */
kadonotakashi 0:8fdf9a60065b 3088 #define CRC_CTRL_TCRC_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 3089 #define CRC_CTRL_TCRC_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 3090 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
kadonotakashi 0:8fdf9a60065b 3091 #define CRC_CTRL_WAS_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 3092 #define CRC_CTRL_WAS_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 3093 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
kadonotakashi 0:8fdf9a60065b 3094 #define CRC_CTRL_FXOR_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 3095 #define CRC_CTRL_FXOR_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 3096 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
kadonotakashi 0:8fdf9a60065b 3097 #define CRC_CTRL_TOTR_MASK (0x30000000U)
kadonotakashi 0:8fdf9a60065b 3098 #define CRC_CTRL_TOTR_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 3099 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
kadonotakashi 0:8fdf9a60065b 3100 #define CRC_CTRL_TOT_MASK (0xC0000000U)
kadonotakashi 0:8fdf9a60065b 3101 #define CRC_CTRL_TOT_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 3102 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
kadonotakashi 0:8fdf9a60065b 3103
kadonotakashi 0:8fdf9a60065b 3104 /*! @name CTRLHU - CRC_CTRLHU register. */
kadonotakashi 0:8fdf9a60065b 3105 #define CRC_CTRLHU_TCRC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 3106 #define CRC_CTRLHU_TCRC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3107 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
kadonotakashi 0:8fdf9a60065b 3108 #define CRC_CTRLHU_WAS_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 3109 #define CRC_CTRLHU_WAS_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 3110 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
kadonotakashi 0:8fdf9a60065b 3111 #define CRC_CTRLHU_FXOR_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 3112 #define CRC_CTRLHU_FXOR_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 3113 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
kadonotakashi 0:8fdf9a60065b 3114 #define CRC_CTRLHU_TOTR_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 3115 #define CRC_CTRLHU_TOTR_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 3116 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
kadonotakashi 0:8fdf9a60065b 3117 #define CRC_CTRLHU_TOT_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 3118 #define CRC_CTRLHU_TOT_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3119 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
kadonotakashi 0:8fdf9a60065b 3120
kadonotakashi 0:8fdf9a60065b 3121
kadonotakashi 0:8fdf9a60065b 3122 /*!
kadonotakashi 0:8fdf9a60065b 3123 * @}
kadonotakashi 0:8fdf9a60065b 3124 */ /* end of group CRC_Register_Masks */
kadonotakashi 0:8fdf9a60065b 3125
kadonotakashi 0:8fdf9a60065b 3126
kadonotakashi 0:8fdf9a60065b 3127 /* CRC - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 3128 /** Peripheral CRC base address */
kadonotakashi 0:8fdf9a60065b 3129 #define CRC_BASE (0x40032000u)
kadonotakashi 0:8fdf9a60065b 3130 /** Peripheral CRC base pointer */
kadonotakashi 0:8fdf9a60065b 3131 #define CRC0 ((CRC_Type *)CRC_BASE)
kadonotakashi 0:8fdf9a60065b 3132 /** Array initializer of CRC peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 3133 #define CRC_BASE_ADDRS { CRC_BASE }
kadonotakashi 0:8fdf9a60065b 3134 /** Array initializer of CRC peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 3135 #define CRC_BASE_PTRS { CRC0 }
kadonotakashi 0:8fdf9a60065b 3136
kadonotakashi 0:8fdf9a60065b 3137 /*!
kadonotakashi 0:8fdf9a60065b 3138 * @}
kadonotakashi 0:8fdf9a60065b 3139 */ /* end of group CRC_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 3140
kadonotakashi 0:8fdf9a60065b 3141
kadonotakashi 0:8fdf9a60065b 3142 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 3143 -- DAC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 3144 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 3145
kadonotakashi 0:8fdf9a60065b 3146 /*!
kadonotakashi 0:8fdf9a60065b 3147 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 3148 * @{
kadonotakashi 0:8fdf9a60065b 3149 */
kadonotakashi 0:8fdf9a60065b 3150
kadonotakashi 0:8fdf9a60065b 3151 /** DAC - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 3152 typedef struct {
kadonotakashi 0:8fdf9a60065b 3153 struct { /* offset: 0x0, array step: 0x2 */
kadonotakashi 0:8fdf9a60065b 3154 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
kadonotakashi 0:8fdf9a60065b 3155 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
kadonotakashi 0:8fdf9a60065b 3156 } DAT[16];
kadonotakashi 0:8fdf9a60065b 3157 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 3158 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
kadonotakashi 0:8fdf9a60065b 3159 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
kadonotakashi 0:8fdf9a60065b 3160 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
kadonotakashi 0:8fdf9a60065b 3161 } DAC_Type;
kadonotakashi 0:8fdf9a60065b 3162
kadonotakashi 0:8fdf9a60065b 3163 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 3164 -- DAC Register Masks
kadonotakashi 0:8fdf9a60065b 3165 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 3166
kadonotakashi 0:8fdf9a60065b 3167 /*!
kadonotakashi 0:8fdf9a60065b 3168 * @addtogroup DAC_Register_Masks DAC Register Masks
kadonotakashi 0:8fdf9a60065b 3169 * @{
kadonotakashi 0:8fdf9a60065b 3170 */
kadonotakashi 0:8fdf9a60065b 3171
kadonotakashi 0:8fdf9a60065b 3172 /*! @name DATL - DAC Data Low Register */
kadonotakashi 0:8fdf9a60065b 3173 #define DAC_DATL_DATA0_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 3174 #define DAC_DATL_DATA0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3175 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
kadonotakashi 0:8fdf9a60065b 3176
kadonotakashi 0:8fdf9a60065b 3177 /* The count of DAC_DATL */
kadonotakashi 0:8fdf9a60065b 3178 #define DAC_DATL_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 3179
kadonotakashi 0:8fdf9a60065b 3180 /*! @name DATH - DAC Data High Register */
kadonotakashi 0:8fdf9a60065b 3181 #define DAC_DATH_DATA1_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 3182 #define DAC_DATH_DATA1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3183 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
kadonotakashi 0:8fdf9a60065b 3184
kadonotakashi 0:8fdf9a60065b 3185 /* The count of DAC_DATH */
kadonotakashi 0:8fdf9a60065b 3186 #define DAC_DATH_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 3187
kadonotakashi 0:8fdf9a60065b 3188 /*! @name SR - DAC Status Register */
kadonotakashi 0:8fdf9a60065b 3189 #define DAC_SR_DACBFRPBF_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 3190 #define DAC_SR_DACBFRPBF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3191 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
kadonotakashi 0:8fdf9a60065b 3192 #define DAC_SR_DACBFRPTF_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 3193 #define DAC_SR_DACBFRPTF_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 3194 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
kadonotakashi 0:8fdf9a60065b 3195 #define DAC_SR_DACBFWMF_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 3196 #define DAC_SR_DACBFWMF_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 3197 #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
kadonotakashi 0:8fdf9a60065b 3198
kadonotakashi 0:8fdf9a60065b 3199 /*! @name C0 - DAC Control Register */
kadonotakashi 0:8fdf9a60065b 3200 #define DAC_C0_DACBBIEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 3201 #define DAC_C0_DACBBIEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3202 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
kadonotakashi 0:8fdf9a60065b 3203 #define DAC_C0_DACBTIEN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 3204 #define DAC_C0_DACBTIEN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 3205 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
kadonotakashi 0:8fdf9a60065b 3206 #define DAC_C0_DACBWIEN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 3207 #define DAC_C0_DACBWIEN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 3208 #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
kadonotakashi 0:8fdf9a60065b 3209 #define DAC_C0_LPEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 3210 #define DAC_C0_LPEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 3211 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
kadonotakashi 0:8fdf9a60065b 3212 #define DAC_C0_DACSWTRG_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 3213 #define DAC_C0_DACSWTRG_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 3214 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
kadonotakashi 0:8fdf9a60065b 3215 #define DAC_C0_DACTRGSEL_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 3216 #define DAC_C0_DACTRGSEL_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 3217 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
kadonotakashi 0:8fdf9a60065b 3218 #define DAC_C0_DACRFS_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3219 #define DAC_C0_DACRFS_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3220 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
kadonotakashi 0:8fdf9a60065b 3221 #define DAC_C0_DACEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3222 #define DAC_C0_DACEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3223 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
kadonotakashi 0:8fdf9a60065b 3224
kadonotakashi 0:8fdf9a60065b 3225 /*! @name C1 - DAC Control Register 1 */
kadonotakashi 0:8fdf9a60065b 3226 #define DAC_C1_DACBFEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 3227 #define DAC_C1_DACBFEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3228 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
kadonotakashi 0:8fdf9a60065b 3229 #define DAC_C1_DACBFMD_MASK (0x6U)
kadonotakashi 0:8fdf9a60065b 3230 #define DAC_C1_DACBFMD_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 3231 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
kadonotakashi 0:8fdf9a60065b 3232 #define DAC_C1_DACBFWM_MASK (0x18U)
kadonotakashi 0:8fdf9a60065b 3233 #define DAC_C1_DACBFWM_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 3234 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
kadonotakashi 0:8fdf9a60065b 3235 #define DAC_C1_DMAEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3236 #define DAC_C1_DMAEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3237 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
kadonotakashi 0:8fdf9a60065b 3238
kadonotakashi 0:8fdf9a60065b 3239 /*! @name C2 - DAC Control Register 2 */
kadonotakashi 0:8fdf9a60065b 3240 #define DAC_C2_DACBFUP_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 3241 #define DAC_C2_DACBFUP_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3242 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
kadonotakashi 0:8fdf9a60065b 3243 #define DAC_C2_DACBFRP_MASK (0xF0U)
kadonotakashi 0:8fdf9a60065b 3244 #define DAC_C2_DACBFRP_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 3245 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
kadonotakashi 0:8fdf9a60065b 3246
kadonotakashi 0:8fdf9a60065b 3247
kadonotakashi 0:8fdf9a60065b 3248 /*!
kadonotakashi 0:8fdf9a60065b 3249 * @}
kadonotakashi 0:8fdf9a60065b 3250 */ /* end of group DAC_Register_Masks */
kadonotakashi 0:8fdf9a60065b 3251
kadonotakashi 0:8fdf9a60065b 3252
kadonotakashi 0:8fdf9a60065b 3253 /* DAC - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 3254 /** Peripheral DAC0 base address */
kadonotakashi 0:8fdf9a60065b 3255 #define DAC0_BASE (0x400CC000u)
kadonotakashi 0:8fdf9a60065b 3256 /** Peripheral DAC0 base pointer */
kadonotakashi 0:8fdf9a60065b 3257 #define DAC0 ((DAC_Type *)DAC0_BASE)
kadonotakashi 0:8fdf9a60065b 3258 /** Array initializer of DAC peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 3259 #define DAC_BASE_ADDRS { DAC0_BASE }
kadonotakashi 0:8fdf9a60065b 3260 /** Array initializer of DAC peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 3261 #define DAC_BASE_PTRS { DAC0 }
kadonotakashi 0:8fdf9a60065b 3262 /** Interrupt vectors for the DAC peripheral type */
kadonotakashi 0:8fdf9a60065b 3263 #define DAC_IRQS { DAC0_IRQn }
kadonotakashi 0:8fdf9a60065b 3264
kadonotakashi 0:8fdf9a60065b 3265 /*!
kadonotakashi 0:8fdf9a60065b 3266 * @}
kadonotakashi 0:8fdf9a60065b 3267 */ /* end of group DAC_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 3268
kadonotakashi 0:8fdf9a60065b 3269
kadonotakashi 0:8fdf9a60065b 3270 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 3271 -- DMA Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 3272 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 3273
kadonotakashi 0:8fdf9a60065b 3274 /*!
kadonotakashi 0:8fdf9a60065b 3275 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 3276 * @{
kadonotakashi 0:8fdf9a60065b 3277 */
kadonotakashi 0:8fdf9a60065b 3278
kadonotakashi 0:8fdf9a60065b 3279 /** DMA - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 3280 typedef struct {
kadonotakashi 0:8fdf9a60065b 3281 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 3282 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 3283 uint8_t RESERVED_0[4];
kadonotakashi 0:8fdf9a60065b 3284 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 3285 uint8_t RESERVED_1[4];
kadonotakashi 0:8fdf9a60065b 3286 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 3287 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 3288 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
kadonotakashi 0:8fdf9a60065b 3289 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
kadonotakashi 0:8fdf9a60065b 3290 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
kadonotakashi 0:8fdf9a60065b 3291 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
kadonotakashi 0:8fdf9a60065b 3292 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
kadonotakashi 0:8fdf9a60065b 3293 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
kadonotakashi 0:8fdf9a60065b 3294 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
kadonotakashi 0:8fdf9a60065b 3295 uint8_t RESERVED_2[4];
kadonotakashi 0:8fdf9a60065b 3296 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 3297 uint8_t RESERVED_3[4];
kadonotakashi 0:8fdf9a60065b 3298 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
kadonotakashi 0:8fdf9a60065b 3299 uint8_t RESERVED_4[4];
kadonotakashi 0:8fdf9a60065b 3300 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 3301 uint8_t RESERVED_5[12];
kadonotakashi 0:8fdf9a60065b 3302 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
kadonotakashi 0:8fdf9a60065b 3303 uint8_t RESERVED_6[184];
kadonotakashi 0:8fdf9a60065b 3304 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
kadonotakashi 0:8fdf9a60065b 3305 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
kadonotakashi 0:8fdf9a60065b 3306 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
kadonotakashi 0:8fdf9a60065b 3307 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
kadonotakashi 0:8fdf9a60065b 3308 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
kadonotakashi 0:8fdf9a60065b 3309 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
kadonotakashi 0:8fdf9a60065b 3310 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
kadonotakashi 0:8fdf9a60065b 3311 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
kadonotakashi 0:8fdf9a60065b 3312 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
kadonotakashi 0:8fdf9a60065b 3313 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
kadonotakashi 0:8fdf9a60065b 3314 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
kadonotakashi 0:8fdf9a60065b 3315 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
kadonotakashi 0:8fdf9a60065b 3316 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
kadonotakashi 0:8fdf9a60065b 3317 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
kadonotakashi 0:8fdf9a60065b 3318 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
kadonotakashi 0:8fdf9a60065b 3319 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
kadonotakashi 0:8fdf9a60065b 3320 __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */
kadonotakashi 0:8fdf9a60065b 3321 __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */
kadonotakashi 0:8fdf9a60065b 3322 __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */
kadonotakashi 0:8fdf9a60065b 3323 __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */
kadonotakashi 0:8fdf9a60065b 3324 __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */
kadonotakashi 0:8fdf9a60065b 3325 __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */
kadonotakashi 0:8fdf9a60065b 3326 __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */
kadonotakashi 0:8fdf9a60065b 3327 __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */
kadonotakashi 0:8fdf9a60065b 3328 __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */
kadonotakashi 0:8fdf9a60065b 3329 __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */
kadonotakashi 0:8fdf9a60065b 3330 __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */
kadonotakashi 0:8fdf9a60065b 3331 __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */
kadonotakashi 0:8fdf9a60065b 3332 __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */
kadonotakashi 0:8fdf9a60065b 3333 __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */
kadonotakashi 0:8fdf9a60065b 3334 __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */
kadonotakashi 0:8fdf9a60065b 3335 __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */
kadonotakashi 0:8fdf9a60065b 3336 uint8_t RESERVED_7[3808];
kadonotakashi 0:8fdf9a60065b 3337 struct { /* offset: 0x1000, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3338 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3339 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3340 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3341 union { /* offset: 0x1008, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3342 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3343 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3344 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3345 };
kadonotakashi 0:8fdf9a60065b 3346 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3347 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3348 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3349 union { /* offset: 0x1016, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3350 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3351 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3352 };
kadonotakashi 0:8fdf9a60065b 3353 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3354 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3355 union { /* offset: 0x101E, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3356 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3357 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
kadonotakashi 0:8fdf9a60065b 3358 };
kadonotakashi 0:8fdf9a60065b 3359 } TCD[32];
kadonotakashi 0:8fdf9a60065b 3360 } DMA_Type;
kadonotakashi 0:8fdf9a60065b 3361
kadonotakashi 0:8fdf9a60065b 3362 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 3363 -- DMA Register Masks
kadonotakashi 0:8fdf9a60065b 3364 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 3365
kadonotakashi 0:8fdf9a60065b 3366 /*!
kadonotakashi 0:8fdf9a60065b 3367 * @addtogroup DMA_Register_Masks DMA Register Masks
kadonotakashi 0:8fdf9a60065b 3368 * @{
kadonotakashi 0:8fdf9a60065b 3369 */
kadonotakashi 0:8fdf9a60065b 3370
kadonotakashi 0:8fdf9a60065b 3371 /*! @name CR - Control Register */
kadonotakashi 0:8fdf9a60065b 3372 #define DMA_CR_EDBG_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 3373 #define DMA_CR_EDBG_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 3374 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
kadonotakashi 0:8fdf9a60065b 3375 #define DMA_CR_ERCA_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 3376 #define DMA_CR_ERCA_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 3377 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
kadonotakashi 0:8fdf9a60065b 3378 #define DMA_CR_ERGA_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 3379 #define DMA_CR_ERGA_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 3380 #define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
kadonotakashi 0:8fdf9a60065b 3381 #define DMA_CR_HOE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 3382 #define DMA_CR_HOE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 3383 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
kadonotakashi 0:8fdf9a60065b 3384 #define DMA_CR_HALT_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 3385 #define DMA_CR_HALT_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 3386 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
kadonotakashi 0:8fdf9a60065b 3387 #define DMA_CR_CLM_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3388 #define DMA_CR_CLM_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3389 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
kadonotakashi 0:8fdf9a60065b 3390 #define DMA_CR_EMLM_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3391 #define DMA_CR_EMLM_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3392 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
kadonotakashi 0:8fdf9a60065b 3393 #define DMA_CR_GRP0PRI_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 3394 #define DMA_CR_GRP0PRI_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 3395 #define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
kadonotakashi 0:8fdf9a60065b 3396 #define DMA_CR_GRP1PRI_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 3397 #define DMA_CR_GRP1PRI_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 3398 #define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
kadonotakashi 0:8fdf9a60065b 3399 #define DMA_CR_ECX_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 3400 #define DMA_CR_ECX_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 3401 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
kadonotakashi 0:8fdf9a60065b 3402 #define DMA_CR_CX_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 3403 #define DMA_CR_CX_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 3404 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
kadonotakashi 0:8fdf9a60065b 3405
kadonotakashi 0:8fdf9a60065b 3406 /*! @name ES - Error Status Register */
kadonotakashi 0:8fdf9a60065b 3407 #define DMA_ES_DBE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 3408 #define DMA_ES_DBE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3409 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
kadonotakashi 0:8fdf9a60065b 3410 #define DMA_ES_SBE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 3411 #define DMA_ES_SBE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 3412 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
kadonotakashi 0:8fdf9a60065b 3413 #define DMA_ES_SGE_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 3414 #define DMA_ES_SGE_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 3415 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
kadonotakashi 0:8fdf9a60065b 3416 #define DMA_ES_NCE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 3417 #define DMA_ES_NCE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 3418 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
kadonotakashi 0:8fdf9a60065b 3419 #define DMA_ES_DOE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 3420 #define DMA_ES_DOE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 3421 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
kadonotakashi 0:8fdf9a60065b 3422 #define DMA_ES_DAE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 3423 #define DMA_ES_DAE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 3424 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
kadonotakashi 0:8fdf9a60065b 3425 #define DMA_ES_SOE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3426 #define DMA_ES_SOE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3427 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
kadonotakashi 0:8fdf9a60065b 3428 #define DMA_ES_SAE_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3429 #define DMA_ES_SAE_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3430 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
kadonotakashi 0:8fdf9a60065b 3431 #define DMA_ES_ERRCHN_MASK (0x1F00U)
kadonotakashi 0:8fdf9a60065b 3432 #define DMA_ES_ERRCHN_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 3433 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
kadonotakashi 0:8fdf9a60065b 3434 #define DMA_ES_CPE_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 3435 #define DMA_ES_CPE_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 3436 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
kadonotakashi 0:8fdf9a60065b 3437 #define DMA_ES_GPE_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 3438 #define DMA_ES_GPE_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 3439 #define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
kadonotakashi 0:8fdf9a60065b 3440 #define DMA_ES_ECX_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 3441 #define DMA_ES_ECX_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 3442 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
kadonotakashi 0:8fdf9a60065b 3443 #define DMA_ES_VLD_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 3444 #define DMA_ES_VLD_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 3445 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
kadonotakashi 0:8fdf9a60065b 3446
kadonotakashi 0:8fdf9a60065b 3447 /*! @name ERQ - Enable Request Register */
kadonotakashi 0:8fdf9a60065b 3448 #define DMA_ERQ_ERQ0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 3449 #define DMA_ERQ_ERQ0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3450 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
kadonotakashi 0:8fdf9a60065b 3451 #define DMA_ERQ_ERQ1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 3452 #define DMA_ERQ_ERQ1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 3453 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
kadonotakashi 0:8fdf9a60065b 3454 #define DMA_ERQ_ERQ2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 3455 #define DMA_ERQ_ERQ2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 3456 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
kadonotakashi 0:8fdf9a60065b 3457 #define DMA_ERQ_ERQ3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 3458 #define DMA_ERQ_ERQ3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 3459 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
kadonotakashi 0:8fdf9a60065b 3460 #define DMA_ERQ_ERQ4_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 3461 #define DMA_ERQ_ERQ4_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 3462 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
kadonotakashi 0:8fdf9a60065b 3463 #define DMA_ERQ_ERQ5_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 3464 #define DMA_ERQ_ERQ5_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 3465 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
kadonotakashi 0:8fdf9a60065b 3466 #define DMA_ERQ_ERQ6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3467 #define DMA_ERQ_ERQ6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3468 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
kadonotakashi 0:8fdf9a60065b 3469 #define DMA_ERQ_ERQ7_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3470 #define DMA_ERQ_ERQ7_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3471 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
kadonotakashi 0:8fdf9a60065b 3472 #define DMA_ERQ_ERQ8_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 3473 #define DMA_ERQ_ERQ8_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 3474 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
kadonotakashi 0:8fdf9a60065b 3475 #define DMA_ERQ_ERQ9_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 3476 #define DMA_ERQ_ERQ9_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 3477 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
kadonotakashi 0:8fdf9a60065b 3478 #define DMA_ERQ_ERQ10_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 3479 #define DMA_ERQ_ERQ10_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 3480 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
kadonotakashi 0:8fdf9a60065b 3481 #define DMA_ERQ_ERQ11_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 3482 #define DMA_ERQ_ERQ11_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 3483 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
kadonotakashi 0:8fdf9a60065b 3484 #define DMA_ERQ_ERQ12_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 3485 #define DMA_ERQ_ERQ12_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 3486 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
kadonotakashi 0:8fdf9a60065b 3487 #define DMA_ERQ_ERQ13_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 3488 #define DMA_ERQ_ERQ13_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 3489 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
kadonotakashi 0:8fdf9a60065b 3490 #define DMA_ERQ_ERQ14_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 3491 #define DMA_ERQ_ERQ14_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 3492 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
kadonotakashi 0:8fdf9a60065b 3493 #define DMA_ERQ_ERQ15_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 3494 #define DMA_ERQ_ERQ15_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 3495 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
kadonotakashi 0:8fdf9a60065b 3496 #define DMA_ERQ_ERQ16_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 3497 #define DMA_ERQ_ERQ16_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 3498 #define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
kadonotakashi 0:8fdf9a60065b 3499 #define DMA_ERQ_ERQ17_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 3500 #define DMA_ERQ_ERQ17_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 3501 #define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
kadonotakashi 0:8fdf9a60065b 3502 #define DMA_ERQ_ERQ18_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 3503 #define DMA_ERQ_ERQ18_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 3504 #define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
kadonotakashi 0:8fdf9a60065b 3505 #define DMA_ERQ_ERQ19_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 3506 #define DMA_ERQ_ERQ19_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 3507 #define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
kadonotakashi 0:8fdf9a60065b 3508 #define DMA_ERQ_ERQ20_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 3509 #define DMA_ERQ_ERQ20_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 3510 #define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
kadonotakashi 0:8fdf9a60065b 3511 #define DMA_ERQ_ERQ21_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 3512 #define DMA_ERQ_ERQ21_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 3513 #define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
kadonotakashi 0:8fdf9a60065b 3514 #define DMA_ERQ_ERQ22_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 3515 #define DMA_ERQ_ERQ22_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 3516 #define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
kadonotakashi 0:8fdf9a60065b 3517 #define DMA_ERQ_ERQ23_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 3518 #define DMA_ERQ_ERQ23_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 3519 #define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
kadonotakashi 0:8fdf9a60065b 3520 #define DMA_ERQ_ERQ24_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 3521 #define DMA_ERQ_ERQ24_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 3522 #define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
kadonotakashi 0:8fdf9a60065b 3523 #define DMA_ERQ_ERQ25_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 3524 #define DMA_ERQ_ERQ25_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 3525 #define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
kadonotakashi 0:8fdf9a60065b 3526 #define DMA_ERQ_ERQ26_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 3527 #define DMA_ERQ_ERQ26_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 3528 #define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
kadonotakashi 0:8fdf9a60065b 3529 #define DMA_ERQ_ERQ27_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 3530 #define DMA_ERQ_ERQ27_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 3531 #define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
kadonotakashi 0:8fdf9a60065b 3532 #define DMA_ERQ_ERQ28_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 3533 #define DMA_ERQ_ERQ28_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 3534 #define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
kadonotakashi 0:8fdf9a60065b 3535 #define DMA_ERQ_ERQ29_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 3536 #define DMA_ERQ_ERQ29_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 3537 #define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
kadonotakashi 0:8fdf9a60065b 3538 #define DMA_ERQ_ERQ30_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 3539 #define DMA_ERQ_ERQ30_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 3540 #define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
kadonotakashi 0:8fdf9a60065b 3541 #define DMA_ERQ_ERQ31_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 3542 #define DMA_ERQ_ERQ31_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 3543 #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
kadonotakashi 0:8fdf9a60065b 3544
kadonotakashi 0:8fdf9a60065b 3545 /*! @name EEI - Enable Error Interrupt Register */
kadonotakashi 0:8fdf9a60065b 3546 #define DMA_EEI_EEI0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 3547 #define DMA_EEI_EEI0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3548 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
kadonotakashi 0:8fdf9a60065b 3549 #define DMA_EEI_EEI1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 3550 #define DMA_EEI_EEI1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 3551 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
kadonotakashi 0:8fdf9a60065b 3552 #define DMA_EEI_EEI2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 3553 #define DMA_EEI_EEI2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 3554 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
kadonotakashi 0:8fdf9a60065b 3555 #define DMA_EEI_EEI3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 3556 #define DMA_EEI_EEI3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 3557 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
kadonotakashi 0:8fdf9a60065b 3558 #define DMA_EEI_EEI4_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 3559 #define DMA_EEI_EEI4_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 3560 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
kadonotakashi 0:8fdf9a60065b 3561 #define DMA_EEI_EEI5_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 3562 #define DMA_EEI_EEI5_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 3563 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
kadonotakashi 0:8fdf9a60065b 3564 #define DMA_EEI_EEI6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3565 #define DMA_EEI_EEI6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3566 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
kadonotakashi 0:8fdf9a60065b 3567 #define DMA_EEI_EEI7_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3568 #define DMA_EEI_EEI7_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3569 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
kadonotakashi 0:8fdf9a60065b 3570 #define DMA_EEI_EEI8_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 3571 #define DMA_EEI_EEI8_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 3572 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
kadonotakashi 0:8fdf9a60065b 3573 #define DMA_EEI_EEI9_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 3574 #define DMA_EEI_EEI9_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 3575 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
kadonotakashi 0:8fdf9a60065b 3576 #define DMA_EEI_EEI10_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 3577 #define DMA_EEI_EEI10_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 3578 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
kadonotakashi 0:8fdf9a60065b 3579 #define DMA_EEI_EEI11_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 3580 #define DMA_EEI_EEI11_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 3581 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
kadonotakashi 0:8fdf9a60065b 3582 #define DMA_EEI_EEI12_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 3583 #define DMA_EEI_EEI12_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 3584 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
kadonotakashi 0:8fdf9a60065b 3585 #define DMA_EEI_EEI13_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 3586 #define DMA_EEI_EEI13_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 3587 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
kadonotakashi 0:8fdf9a60065b 3588 #define DMA_EEI_EEI14_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 3589 #define DMA_EEI_EEI14_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 3590 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
kadonotakashi 0:8fdf9a60065b 3591 #define DMA_EEI_EEI15_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 3592 #define DMA_EEI_EEI15_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 3593 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
kadonotakashi 0:8fdf9a60065b 3594 #define DMA_EEI_EEI16_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 3595 #define DMA_EEI_EEI16_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 3596 #define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
kadonotakashi 0:8fdf9a60065b 3597 #define DMA_EEI_EEI17_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 3598 #define DMA_EEI_EEI17_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 3599 #define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
kadonotakashi 0:8fdf9a60065b 3600 #define DMA_EEI_EEI18_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 3601 #define DMA_EEI_EEI18_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 3602 #define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
kadonotakashi 0:8fdf9a60065b 3603 #define DMA_EEI_EEI19_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 3604 #define DMA_EEI_EEI19_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 3605 #define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
kadonotakashi 0:8fdf9a60065b 3606 #define DMA_EEI_EEI20_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 3607 #define DMA_EEI_EEI20_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 3608 #define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
kadonotakashi 0:8fdf9a60065b 3609 #define DMA_EEI_EEI21_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 3610 #define DMA_EEI_EEI21_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 3611 #define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
kadonotakashi 0:8fdf9a60065b 3612 #define DMA_EEI_EEI22_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 3613 #define DMA_EEI_EEI22_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 3614 #define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
kadonotakashi 0:8fdf9a60065b 3615 #define DMA_EEI_EEI23_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 3616 #define DMA_EEI_EEI23_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 3617 #define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
kadonotakashi 0:8fdf9a60065b 3618 #define DMA_EEI_EEI24_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 3619 #define DMA_EEI_EEI24_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 3620 #define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
kadonotakashi 0:8fdf9a60065b 3621 #define DMA_EEI_EEI25_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 3622 #define DMA_EEI_EEI25_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 3623 #define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
kadonotakashi 0:8fdf9a60065b 3624 #define DMA_EEI_EEI26_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 3625 #define DMA_EEI_EEI26_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 3626 #define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
kadonotakashi 0:8fdf9a60065b 3627 #define DMA_EEI_EEI27_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 3628 #define DMA_EEI_EEI27_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 3629 #define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
kadonotakashi 0:8fdf9a60065b 3630 #define DMA_EEI_EEI28_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 3631 #define DMA_EEI_EEI28_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 3632 #define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
kadonotakashi 0:8fdf9a60065b 3633 #define DMA_EEI_EEI29_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 3634 #define DMA_EEI_EEI29_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 3635 #define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
kadonotakashi 0:8fdf9a60065b 3636 #define DMA_EEI_EEI30_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 3637 #define DMA_EEI_EEI30_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 3638 #define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
kadonotakashi 0:8fdf9a60065b 3639 #define DMA_EEI_EEI31_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 3640 #define DMA_EEI_EEI31_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 3641 #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
kadonotakashi 0:8fdf9a60065b 3642
kadonotakashi 0:8fdf9a60065b 3643 /*! @name CEEI - Clear Enable Error Interrupt Register */
kadonotakashi 0:8fdf9a60065b 3644 #define DMA_CEEI_CEEI_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 3645 #define DMA_CEEI_CEEI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3646 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
kadonotakashi 0:8fdf9a60065b 3647 #define DMA_CEEI_CAEE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3648 #define DMA_CEEI_CAEE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3649 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
kadonotakashi 0:8fdf9a60065b 3650 #define DMA_CEEI_NOP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3651 #define DMA_CEEI_NOP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3652 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
kadonotakashi 0:8fdf9a60065b 3653
kadonotakashi 0:8fdf9a60065b 3654 /*! @name SEEI - Set Enable Error Interrupt Register */
kadonotakashi 0:8fdf9a60065b 3655 #define DMA_SEEI_SEEI_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 3656 #define DMA_SEEI_SEEI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3657 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
kadonotakashi 0:8fdf9a60065b 3658 #define DMA_SEEI_SAEE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3659 #define DMA_SEEI_SAEE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3660 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
kadonotakashi 0:8fdf9a60065b 3661 #define DMA_SEEI_NOP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3662 #define DMA_SEEI_NOP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3663 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
kadonotakashi 0:8fdf9a60065b 3664
kadonotakashi 0:8fdf9a60065b 3665 /*! @name CERQ - Clear Enable Request Register */
kadonotakashi 0:8fdf9a60065b 3666 #define DMA_CERQ_CERQ_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 3667 #define DMA_CERQ_CERQ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3668 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
kadonotakashi 0:8fdf9a60065b 3669 #define DMA_CERQ_CAER_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3670 #define DMA_CERQ_CAER_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3671 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
kadonotakashi 0:8fdf9a60065b 3672 #define DMA_CERQ_NOP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3673 #define DMA_CERQ_NOP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3674 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
kadonotakashi 0:8fdf9a60065b 3675
kadonotakashi 0:8fdf9a60065b 3676 /*! @name SERQ - Set Enable Request Register */
kadonotakashi 0:8fdf9a60065b 3677 #define DMA_SERQ_SERQ_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 3678 #define DMA_SERQ_SERQ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3679 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
kadonotakashi 0:8fdf9a60065b 3680 #define DMA_SERQ_SAER_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3681 #define DMA_SERQ_SAER_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3682 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
kadonotakashi 0:8fdf9a60065b 3683 #define DMA_SERQ_NOP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3684 #define DMA_SERQ_NOP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3685 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
kadonotakashi 0:8fdf9a60065b 3686
kadonotakashi 0:8fdf9a60065b 3687 /*! @name CDNE - Clear DONE Status Bit Register */
kadonotakashi 0:8fdf9a60065b 3688 #define DMA_CDNE_CDNE_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 3689 #define DMA_CDNE_CDNE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3690 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
kadonotakashi 0:8fdf9a60065b 3691 #define DMA_CDNE_CADN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3692 #define DMA_CDNE_CADN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3693 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
kadonotakashi 0:8fdf9a60065b 3694 #define DMA_CDNE_NOP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3695 #define DMA_CDNE_NOP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3696 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
kadonotakashi 0:8fdf9a60065b 3697
kadonotakashi 0:8fdf9a60065b 3698 /*! @name SSRT - Set START Bit Register */
kadonotakashi 0:8fdf9a60065b 3699 #define DMA_SSRT_SSRT_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 3700 #define DMA_SSRT_SSRT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3701 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
kadonotakashi 0:8fdf9a60065b 3702 #define DMA_SSRT_SAST_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3703 #define DMA_SSRT_SAST_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3704 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
kadonotakashi 0:8fdf9a60065b 3705 #define DMA_SSRT_NOP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3706 #define DMA_SSRT_NOP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3707 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
kadonotakashi 0:8fdf9a60065b 3708
kadonotakashi 0:8fdf9a60065b 3709 /*! @name CERR - Clear Error Register */
kadonotakashi 0:8fdf9a60065b 3710 #define DMA_CERR_CERR_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 3711 #define DMA_CERR_CERR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3712 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
kadonotakashi 0:8fdf9a60065b 3713 #define DMA_CERR_CAEI_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3714 #define DMA_CERR_CAEI_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3715 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
kadonotakashi 0:8fdf9a60065b 3716 #define DMA_CERR_NOP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3717 #define DMA_CERR_NOP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3718 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
kadonotakashi 0:8fdf9a60065b 3719
kadonotakashi 0:8fdf9a60065b 3720 /*! @name CINT - Clear Interrupt Request Register */
kadonotakashi 0:8fdf9a60065b 3721 #define DMA_CINT_CINT_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 3722 #define DMA_CINT_CINT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3723 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
kadonotakashi 0:8fdf9a60065b 3724 #define DMA_CINT_CAIR_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3725 #define DMA_CINT_CAIR_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3726 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
kadonotakashi 0:8fdf9a60065b 3727 #define DMA_CINT_NOP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3728 #define DMA_CINT_NOP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3729 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
kadonotakashi 0:8fdf9a60065b 3730
kadonotakashi 0:8fdf9a60065b 3731 /*! @name INT - Interrupt Request Register */
kadonotakashi 0:8fdf9a60065b 3732 #define DMA_INT_INT0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 3733 #define DMA_INT_INT0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3734 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
kadonotakashi 0:8fdf9a60065b 3735 #define DMA_INT_INT1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 3736 #define DMA_INT_INT1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 3737 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
kadonotakashi 0:8fdf9a60065b 3738 #define DMA_INT_INT2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 3739 #define DMA_INT_INT2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 3740 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
kadonotakashi 0:8fdf9a60065b 3741 #define DMA_INT_INT3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 3742 #define DMA_INT_INT3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 3743 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
kadonotakashi 0:8fdf9a60065b 3744 #define DMA_INT_INT4_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 3745 #define DMA_INT_INT4_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 3746 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
kadonotakashi 0:8fdf9a60065b 3747 #define DMA_INT_INT5_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 3748 #define DMA_INT_INT5_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 3749 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
kadonotakashi 0:8fdf9a60065b 3750 #define DMA_INT_INT6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3751 #define DMA_INT_INT6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3752 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
kadonotakashi 0:8fdf9a60065b 3753 #define DMA_INT_INT7_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3754 #define DMA_INT_INT7_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3755 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
kadonotakashi 0:8fdf9a60065b 3756 #define DMA_INT_INT8_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 3757 #define DMA_INT_INT8_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 3758 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
kadonotakashi 0:8fdf9a60065b 3759 #define DMA_INT_INT9_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 3760 #define DMA_INT_INT9_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 3761 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
kadonotakashi 0:8fdf9a60065b 3762 #define DMA_INT_INT10_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 3763 #define DMA_INT_INT10_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 3764 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
kadonotakashi 0:8fdf9a60065b 3765 #define DMA_INT_INT11_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 3766 #define DMA_INT_INT11_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 3767 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
kadonotakashi 0:8fdf9a60065b 3768 #define DMA_INT_INT12_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 3769 #define DMA_INT_INT12_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 3770 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
kadonotakashi 0:8fdf9a60065b 3771 #define DMA_INT_INT13_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 3772 #define DMA_INT_INT13_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 3773 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
kadonotakashi 0:8fdf9a60065b 3774 #define DMA_INT_INT14_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 3775 #define DMA_INT_INT14_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 3776 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
kadonotakashi 0:8fdf9a60065b 3777 #define DMA_INT_INT15_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 3778 #define DMA_INT_INT15_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 3779 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
kadonotakashi 0:8fdf9a60065b 3780 #define DMA_INT_INT16_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 3781 #define DMA_INT_INT16_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 3782 #define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
kadonotakashi 0:8fdf9a60065b 3783 #define DMA_INT_INT17_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 3784 #define DMA_INT_INT17_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 3785 #define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
kadonotakashi 0:8fdf9a60065b 3786 #define DMA_INT_INT18_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 3787 #define DMA_INT_INT18_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 3788 #define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
kadonotakashi 0:8fdf9a60065b 3789 #define DMA_INT_INT19_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 3790 #define DMA_INT_INT19_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 3791 #define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
kadonotakashi 0:8fdf9a60065b 3792 #define DMA_INT_INT20_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 3793 #define DMA_INT_INT20_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 3794 #define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
kadonotakashi 0:8fdf9a60065b 3795 #define DMA_INT_INT21_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 3796 #define DMA_INT_INT21_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 3797 #define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
kadonotakashi 0:8fdf9a60065b 3798 #define DMA_INT_INT22_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 3799 #define DMA_INT_INT22_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 3800 #define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
kadonotakashi 0:8fdf9a60065b 3801 #define DMA_INT_INT23_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 3802 #define DMA_INT_INT23_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 3803 #define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
kadonotakashi 0:8fdf9a60065b 3804 #define DMA_INT_INT24_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 3805 #define DMA_INT_INT24_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 3806 #define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
kadonotakashi 0:8fdf9a60065b 3807 #define DMA_INT_INT25_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 3808 #define DMA_INT_INT25_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 3809 #define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
kadonotakashi 0:8fdf9a60065b 3810 #define DMA_INT_INT26_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 3811 #define DMA_INT_INT26_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 3812 #define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
kadonotakashi 0:8fdf9a60065b 3813 #define DMA_INT_INT27_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 3814 #define DMA_INT_INT27_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 3815 #define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
kadonotakashi 0:8fdf9a60065b 3816 #define DMA_INT_INT28_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 3817 #define DMA_INT_INT28_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 3818 #define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
kadonotakashi 0:8fdf9a60065b 3819 #define DMA_INT_INT29_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 3820 #define DMA_INT_INT29_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 3821 #define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
kadonotakashi 0:8fdf9a60065b 3822 #define DMA_INT_INT30_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 3823 #define DMA_INT_INT30_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 3824 #define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
kadonotakashi 0:8fdf9a60065b 3825 #define DMA_INT_INT31_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 3826 #define DMA_INT_INT31_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 3827 #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
kadonotakashi 0:8fdf9a60065b 3828
kadonotakashi 0:8fdf9a60065b 3829 /*! @name ERR - Error Register */
kadonotakashi 0:8fdf9a60065b 3830 #define DMA_ERR_ERR0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 3831 #define DMA_ERR_ERR0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3832 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
kadonotakashi 0:8fdf9a60065b 3833 #define DMA_ERR_ERR1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 3834 #define DMA_ERR_ERR1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 3835 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
kadonotakashi 0:8fdf9a60065b 3836 #define DMA_ERR_ERR2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 3837 #define DMA_ERR_ERR2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 3838 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
kadonotakashi 0:8fdf9a60065b 3839 #define DMA_ERR_ERR3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 3840 #define DMA_ERR_ERR3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 3841 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
kadonotakashi 0:8fdf9a60065b 3842 #define DMA_ERR_ERR4_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 3843 #define DMA_ERR_ERR4_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 3844 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
kadonotakashi 0:8fdf9a60065b 3845 #define DMA_ERR_ERR5_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 3846 #define DMA_ERR_ERR5_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 3847 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
kadonotakashi 0:8fdf9a60065b 3848 #define DMA_ERR_ERR6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3849 #define DMA_ERR_ERR6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3850 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
kadonotakashi 0:8fdf9a60065b 3851 #define DMA_ERR_ERR7_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3852 #define DMA_ERR_ERR7_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3853 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
kadonotakashi 0:8fdf9a60065b 3854 #define DMA_ERR_ERR8_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 3855 #define DMA_ERR_ERR8_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 3856 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
kadonotakashi 0:8fdf9a60065b 3857 #define DMA_ERR_ERR9_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 3858 #define DMA_ERR_ERR9_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 3859 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
kadonotakashi 0:8fdf9a60065b 3860 #define DMA_ERR_ERR10_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 3861 #define DMA_ERR_ERR10_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 3862 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
kadonotakashi 0:8fdf9a60065b 3863 #define DMA_ERR_ERR11_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 3864 #define DMA_ERR_ERR11_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 3865 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
kadonotakashi 0:8fdf9a60065b 3866 #define DMA_ERR_ERR12_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 3867 #define DMA_ERR_ERR12_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 3868 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
kadonotakashi 0:8fdf9a60065b 3869 #define DMA_ERR_ERR13_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 3870 #define DMA_ERR_ERR13_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 3871 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
kadonotakashi 0:8fdf9a60065b 3872 #define DMA_ERR_ERR14_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 3873 #define DMA_ERR_ERR14_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 3874 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
kadonotakashi 0:8fdf9a60065b 3875 #define DMA_ERR_ERR15_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 3876 #define DMA_ERR_ERR15_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 3877 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
kadonotakashi 0:8fdf9a60065b 3878 #define DMA_ERR_ERR16_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 3879 #define DMA_ERR_ERR16_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 3880 #define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
kadonotakashi 0:8fdf9a60065b 3881 #define DMA_ERR_ERR17_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 3882 #define DMA_ERR_ERR17_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 3883 #define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
kadonotakashi 0:8fdf9a60065b 3884 #define DMA_ERR_ERR18_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 3885 #define DMA_ERR_ERR18_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 3886 #define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
kadonotakashi 0:8fdf9a60065b 3887 #define DMA_ERR_ERR19_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 3888 #define DMA_ERR_ERR19_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 3889 #define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
kadonotakashi 0:8fdf9a60065b 3890 #define DMA_ERR_ERR20_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 3891 #define DMA_ERR_ERR20_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 3892 #define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
kadonotakashi 0:8fdf9a60065b 3893 #define DMA_ERR_ERR21_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 3894 #define DMA_ERR_ERR21_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 3895 #define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
kadonotakashi 0:8fdf9a60065b 3896 #define DMA_ERR_ERR22_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 3897 #define DMA_ERR_ERR22_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 3898 #define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
kadonotakashi 0:8fdf9a60065b 3899 #define DMA_ERR_ERR23_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 3900 #define DMA_ERR_ERR23_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 3901 #define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
kadonotakashi 0:8fdf9a60065b 3902 #define DMA_ERR_ERR24_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 3903 #define DMA_ERR_ERR24_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 3904 #define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
kadonotakashi 0:8fdf9a60065b 3905 #define DMA_ERR_ERR25_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 3906 #define DMA_ERR_ERR25_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 3907 #define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
kadonotakashi 0:8fdf9a60065b 3908 #define DMA_ERR_ERR26_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 3909 #define DMA_ERR_ERR26_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 3910 #define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
kadonotakashi 0:8fdf9a60065b 3911 #define DMA_ERR_ERR27_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 3912 #define DMA_ERR_ERR27_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 3913 #define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
kadonotakashi 0:8fdf9a60065b 3914 #define DMA_ERR_ERR28_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 3915 #define DMA_ERR_ERR28_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 3916 #define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
kadonotakashi 0:8fdf9a60065b 3917 #define DMA_ERR_ERR29_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 3918 #define DMA_ERR_ERR29_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 3919 #define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
kadonotakashi 0:8fdf9a60065b 3920 #define DMA_ERR_ERR30_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 3921 #define DMA_ERR_ERR30_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 3922 #define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
kadonotakashi 0:8fdf9a60065b 3923 #define DMA_ERR_ERR31_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 3924 #define DMA_ERR_ERR31_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 3925 #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
kadonotakashi 0:8fdf9a60065b 3926
kadonotakashi 0:8fdf9a60065b 3927 /*! @name HRS - Hardware Request Status Register */
kadonotakashi 0:8fdf9a60065b 3928 #define DMA_HRS_HRS0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 3929 #define DMA_HRS_HRS0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 3930 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
kadonotakashi 0:8fdf9a60065b 3931 #define DMA_HRS_HRS1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 3932 #define DMA_HRS_HRS1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 3933 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
kadonotakashi 0:8fdf9a60065b 3934 #define DMA_HRS_HRS2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 3935 #define DMA_HRS_HRS2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 3936 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
kadonotakashi 0:8fdf9a60065b 3937 #define DMA_HRS_HRS3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 3938 #define DMA_HRS_HRS3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 3939 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
kadonotakashi 0:8fdf9a60065b 3940 #define DMA_HRS_HRS4_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 3941 #define DMA_HRS_HRS4_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 3942 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
kadonotakashi 0:8fdf9a60065b 3943 #define DMA_HRS_HRS5_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 3944 #define DMA_HRS_HRS5_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 3945 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
kadonotakashi 0:8fdf9a60065b 3946 #define DMA_HRS_HRS6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 3947 #define DMA_HRS_HRS6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 3948 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
kadonotakashi 0:8fdf9a60065b 3949 #define DMA_HRS_HRS7_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 3950 #define DMA_HRS_HRS7_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 3951 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
kadonotakashi 0:8fdf9a60065b 3952 #define DMA_HRS_HRS8_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 3953 #define DMA_HRS_HRS8_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 3954 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
kadonotakashi 0:8fdf9a60065b 3955 #define DMA_HRS_HRS9_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 3956 #define DMA_HRS_HRS9_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 3957 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
kadonotakashi 0:8fdf9a60065b 3958 #define DMA_HRS_HRS10_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 3959 #define DMA_HRS_HRS10_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 3960 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
kadonotakashi 0:8fdf9a60065b 3961 #define DMA_HRS_HRS11_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 3962 #define DMA_HRS_HRS11_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 3963 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
kadonotakashi 0:8fdf9a60065b 3964 #define DMA_HRS_HRS12_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 3965 #define DMA_HRS_HRS12_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 3966 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
kadonotakashi 0:8fdf9a60065b 3967 #define DMA_HRS_HRS13_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 3968 #define DMA_HRS_HRS13_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 3969 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
kadonotakashi 0:8fdf9a60065b 3970 #define DMA_HRS_HRS14_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 3971 #define DMA_HRS_HRS14_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 3972 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
kadonotakashi 0:8fdf9a60065b 3973 #define DMA_HRS_HRS15_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 3974 #define DMA_HRS_HRS15_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 3975 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
kadonotakashi 0:8fdf9a60065b 3976 #define DMA_HRS_HRS16_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 3977 #define DMA_HRS_HRS16_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 3978 #define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
kadonotakashi 0:8fdf9a60065b 3979 #define DMA_HRS_HRS17_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 3980 #define DMA_HRS_HRS17_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 3981 #define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
kadonotakashi 0:8fdf9a60065b 3982 #define DMA_HRS_HRS18_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 3983 #define DMA_HRS_HRS18_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 3984 #define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
kadonotakashi 0:8fdf9a60065b 3985 #define DMA_HRS_HRS19_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 3986 #define DMA_HRS_HRS19_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 3987 #define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
kadonotakashi 0:8fdf9a60065b 3988 #define DMA_HRS_HRS20_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 3989 #define DMA_HRS_HRS20_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 3990 #define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
kadonotakashi 0:8fdf9a60065b 3991 #define DMA_HRS_HRS21_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 3992 #define DMA_HRS_HRS21_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 3993 #define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
kadonotakashi 0:8fdf9a60065b 3994 #define DMA_HRS_HRS22_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 3995 #define DMA_HRS_HRS22_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 3996 #define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
kadonotakashi 0:8fdf9a60065b 3997 #define DMA_HRS_HRS23_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 3998 #define DMA_HRS_HRS23_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 3999 #define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
kadonotakashi 0:8fdf9a60065b 4000 #define DMA_HRS_HRS24_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 4001 #define DMA_HRS_HRS24_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 4002 #define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
kadonotakashi 0:8fdf9a60065b 4003 #define DMA_HRS_HRS25_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 4004 #define DMA_HRS_HRS25_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 4005 #define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
kadonotakashi 0:8fdf9a60065b 4006 #define DMA_HRS_HRS26_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 4007 #define DMA_HRS_HRS26_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 4008 #define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
kadonotakashi 0:8fdf9a60065b 4009 #define DMA_HRS_HRS27_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 4010 #define DMA_HRS_HRS27_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 4011 #define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
kadonotakashi 0:8fdf9a60065b 4012 #define DMA_HRS_HRS28_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 4013 #define DMA_HRS_HRS28_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 4014 #define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
kadonotakashi 0:8fdf9a60065b 4015 #define DMA_HRS_HRS29_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 4016 #define DMA_HRS_HRS29_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 4017 #define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
kadonotakashi 0:8fdf9a60065b 4018 #define DMA_HRS_HRS30_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 4019 #define DMA_HRS_HRS30_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 4020 #define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
kadonotakashi 0:8fdf9a60065b 4021 #define DMA_HRS_HRS31_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 4022 #define DMA_HRS_HRS31_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 4023 #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
kadonotakashi 0:8fdf9a60065b 4024
kadonotakashi 0:8fdf9a60065b 4025 /*! @name EARS - Enable Asynchronous Request in Stop Register */
kadonotakashi 0:8fdf9a60065b 4026 #define DMA_EARS_EDREQ_0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 4027 #define DMA_EARS_EDREQ_0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4028 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
kadonotakashi 0:8fdf9a60065b 4029 #define DMA_EARS_EDREQ_1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 4030 #define DMA_EARS_EDREQ_1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 4031 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
kadonotakashi 0:8fdf9a60065b 4032 #define DMA_EARS_EDREQ_2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 4033 #define DMA_EARS_EDREQ_2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 4034 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
kadonotakashi 0:8fdf9a60065b 4035 #define DMA_EARS_EDREQ_3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 4036 #define DMA_EARS_EDREQ_3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 4037 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
kadonotakashi 0:8fdf9a60065b 4038 #define DMA_EARS_EDREQ_4_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 4039 #define DMA_EARS_EDREQ_4_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4040 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
kadonotakashi 0:8fdf9a60065b 4041 #define DMA_EARS_EDREQ_5_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 4042 #define DMA_EARS_EDREQ_5_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 4043 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
kadonotakashi 0:8fdf9a60065b 4044 #define DMA_EARS_EDREQ_6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4045 #define DMA_EARS_EDREQ_6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4046 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
kadonotakashi 0:8fdf9a60065b 4047 #define DMA_EARS_EDREQ_7_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4048 #define DMA_EARS_EDREQ_7_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4049 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
kadonotakashi 0:8fdf9a60065b 4050 #define DMA_EARS_EDREQ_8_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 4051 #define DMA_EARS_EDREQ_8_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 4052 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
kadonotakashi 0:8fdf9a60065b 4053 #define DMA_EARS_EDREQ_9_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 4054 #define DMA_EARS_EDREQ_9_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 4055 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
kadonotakashi 0:8fdf9a60065b 4056 #define DMA_EARS_EDREQ_10_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 4057 #define DMA_EARS_EDREQ_10_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 4058 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
kadonotakashi 0:8fdf9a60065b 4059 #define DMA_EARS_EDREQ_11_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 4060 #define DMA_EARS_EDREQ_11_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 4061 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
kadonotakashi 0:8fdf9a60065b 4062 #define DMA_EARS_EDREQ_12_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 4063 #define DMA_EARS_EDREQ_12_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 4064 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
kadonotakashi 0:8fdf9a60065b 4065 #define DMA_EARS_EDREQ_13_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 4066 #define DMA_EARS_EDREQ_13_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 4067 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
kadonotakashi 0:8fdf9a60065b 4068 #define DMA_EARS_EDREQ_14_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 4069 #define DMA_EARS_EDREQ_14_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 4070 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
kadonotakashi 0:8fdf9a60065b 4071 #define DMA_EARS_EDREQ_15_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 4072 #define DMA_EARS_EDREQ_15_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 4073 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
kadonotakashi 0:8fdf9a60065b 4074 #define DMA_EARS_EDREQ_16_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 4075 #define DMA_EARS_EDREQ_16_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 4076 #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
kadonotakashi 0:8fdf9a60065b 4077 #define DMA_EARS_EDREQ_17_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 4078 #define DMA_EARS_EDREQ_17_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 4079 #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
kadonotakashi 0:8fdf9a60065b 4080 #define DMA_EARS_EDREQ_18_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 4081 #define DMA_EARS_EDREQ_18_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 4082 #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
kadonotakashi 0:8fdf9a60065b 4083 #define DMA_EARS_EDREQ_19_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 4084 #define DMA_EARS_EDREQ_19_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 4085 #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
kadonotakashi 0:8fdf9a60065b 4086 #define DMA_EARS_EDREQ_20_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 4087 #define DMA_EARS_EDREQ_20_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 4088 #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
kadonotakashi 0:8fdf9a60065b 4089 #define DMA_EARS_EDREQ_21_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 4090 #define DMA_EARS_EDREQ_21_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 4091 #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
kadonotakashi 0:8fdf9a60065b 4092 #define DMA_EARS_EDREQ_22_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 4093 #define DMA_EARS_EDREQ_22_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 4094 #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
kadonotakashi 0:8fdf9a60065b 4095 #define DMA_EARS_EDREQ_23_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 4096 #define DMA_EARS_EDREQ_23_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 4097 #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
kadonotakashi 0:8fdf9a60065b 4098 #define DMA_EARS_EDREQ_24_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 4099 #define DMA_EARS_EDREQ_24_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 4100 #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
kadonotakashi 0:8fdf9a60065b 4101 #define DMA_EARS_EDREQ_25_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 4102 #define DMA_EARS_EDREQ_25_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 4103 #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
kadonotakashi 0:8fdf9a60065b 4104 #define DMA_EARS_EDREQ_26_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 4105 #define DMA_EARS_EDREQ_26_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 4106 #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
kadonotakashi 0:8fdf9a60065b 4107 #define DMA_EARS_EDREQ_27_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 4108 #define DMA_EARS_EDREQ_27_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 4109 #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
kadonotakashi 0:8fdf9a60065b 4110 #define DMA_EARS_EDREQ_28_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 4111 #define DMA_EARS_EDREQ_28_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 4112 #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
kadonotakashi 0:8fdf9a60065b 4113 #define DMA_EARS_EDREQ_29_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 4114 #define DMA_EARS_EDREQ_29_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 4115 #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
kadonotakashi 0:8fdf9a60065b 4116 #define DMA_EARS_EDREQ_30_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 4117 #define DMA_EARS_EDREQ_30_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 4118 #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
kadonotakashi 0:8fdf9a60065b 4119 #define DMA_EARS_EDREQ_31_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 4120 #define DMA_EARS_EDREQ_31_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 4121 #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
kadonotakashi 0:8fdf9a60065b 4122
kadonotakashi 0:8fdf9a60065b 4123 /*! @name DCHPRI3 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4124 #define DMA_DCHPRI3_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4125 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4126 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4127 #define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4128 #define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4129 #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4130 #define DMA_DCHPRI3_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4131 #define DMA_DCHPRI3_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4132 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4133 #define DMA_DCHPRI3_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4134 #define DMA_DCHPRI3_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4135 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4136
kadonotakashi 0:8fdf9a60065b 4137 /*! @name DCHPRI2 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4138 #define DMA_DCHPRI2_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4139 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4140 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4141 #define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4142 #define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4143 #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4144 #define DMA_DCHPRI2_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4145 #define DMA_DCHPRI2_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4146 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4147 #define DMA_DCHPRI2_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4148 #define DMA_DCHPRI2_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4149 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4150
kadonotakashi 0:8fdf9a60065b 4151 /*! @name DCHPRI1 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4152 #define DMA_DCHPRI1_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4153 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4154 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4155 #define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4156 #define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4157 #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4158 #define DMA_DCHPRI1_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4159 #define DMA_DCHPRI1_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4160 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4161 #define DMA_DCHPRI1_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4162 #define DMA_DCHPRI1_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4163 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4164
kadonotakashi 0:8fdf9a60065b 4165 /*! @name DCHPRI0 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4166 #define DMA_DCHPRI0_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4167 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4168 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4169 #define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4170 #define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4171 #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4172 #define DMA_DCHPRI0_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4173 #define DMA_DCHPRI0_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4174 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4175 #define DMA_DCHPRI0_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4176 #define DMA_DCHPRI0_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4177 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4178
kadonotakashi 0:8fdf9a60065b 4179 /*! @name DCHPRI7 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4180 #define DMA_DCHPRI7_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4181 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4182 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4183 #define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4184 #define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4185 #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4186 #define DMA_DCHPRI7_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4187 #define DMA_DCHPRI7_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4188 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4189 #define DMA_DCHPRI7_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4190 #define DMA_DCHPRI7_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4191 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4192
kadonotakashi 0:8fdf9a60065b 4193 /*! @name DCHPRI6 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4194 #define DMA_DCHPRI6_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4195 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4196 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4197 #define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4198 #define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4199 #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4200 #define DMA_DCHPRI6_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4201 #define DMA_DCHPRI6_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4202 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4203 #define DMA_DCHPRI6_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4204 #define DMA_DCHPRI6_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4205 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4206
kadonotakashi 0:8fdf9a60065b 4207 /*! @name DCHPRI5 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4208 #define DMA_DCHPRI5_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4209 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4210 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4211 #define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4212 #define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4213 #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4214 #define DMA_DCHPRI5_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4215 #define DMA_DCHPRI5_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4216 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4217 #define DMA_DCHPRI5_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4218 #define DMA_DCHPRI5_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4219 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4220
kadonotakashi 0:8fdf9a60065b 4221 /*! @name DCHPRI4 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4222 #define DMA_DCHPRI4_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4223 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4224 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4225 #define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4226 #define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4227 #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4228 #define DMA_DCHPRI4_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4229 #define DMA_DCHPRI4_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4230 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4231 #define DMA_DCHPRI4_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4232 #define DMA_DCHPRI4_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4233 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4234
kadonotakashi 0:8fdf9a60065b 4235 /*! @name DCHPRI11 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4236 #define DMA_DCHPRI11_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4237 #define DMA_DCHPRI11_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4238 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4239 #define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4240 #define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4241 #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4242 #define DMA_DCHPRI11_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4243 #define DMA_DCHPRI11_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4244 #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4245 #define DMA_DCHPRI11_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4246 #define DMA_DCHPRI11_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4247 #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4248
kadonotakashi 0:8fdf9a60065b 4249 /*! @name DCHPRI10 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4250 #define DMA_DCHPRI10_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4251 #define DMA_DCHPRI10_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4252 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4253 #define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4254 #define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4255 #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4256 #define DMA_DCHPRI10_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4257 #define DMA_DCHPRI10_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4258 #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4259 #define DMA_DCHPRI10_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4260 #define DMA_DCHPRI10_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4261 #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4262
kadonotakashi 0:8fdf9a60065b 4263 /*! @name DCHPRI9 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4264 #define DMA_DCHPRI9_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4265 #define DMA_DCHPRI9_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4266 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4267 #define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4268 #define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4269 #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4270 #define DMA_DCHPRI9_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4271 #define DMA_DCHPRI9_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4272 #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4273 #define DMA_DCHPRI9_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4274 #define DMA_DCHPRI9_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4275 #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4276
kadonotakashi 0:8fdf9a60065b 4277 /*! @name DCHPRI8 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4278 #define DMA_DCHPRI8_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4279 #define DMA_DCHPRI8_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4280 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4281 #define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4282 #define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4283 #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4284 #define DMA_DCHPRI8_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4285 #define DMA_DCHPRI8_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4286 #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4287 #define DMA_DCHPRI8_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4288 #define DMA_DCHPRI8_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4289 #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4290
kadonotakashi 0:8fdf9a60065b 4291 /*! @name DCHPRI15 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4292 #define DMA_DCHPRI15_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4293 #define DMA_DCHPRI15_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4294 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4295 #define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4296 #define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4297 #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4298 #define DMA_DCHPRI15_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4299 #define DMA_DCHPRI15_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4300 #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4301 #define DMA_DCHPRI15_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4302 #define DMA_DCHPRI15_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4303 #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4304
kadonotakashi 0:8fdf9a60065b 4305 /*! @name DCHPRI14 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4306 #define DMA_DCHPRI14_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4307 #define DMA_DCHPRI14_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4308 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4309 #define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4310 #define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4311 #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4312 #define DMA_DCHPRI14_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4313 #define DMA_DCHPRI14_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4314 #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4315 #define DMA_DCHPRI14_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4316 #define DMA_DCHPRI14_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4317 #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4318
kadonotakashi 0:8fdf9a60065b 4319 /*! @name DCHPRI13 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4320 #define DMA_DCHPRI13_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4321 #define DMA_DCHPRI13_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4322 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4323 #define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4324 #define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4325 #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4326 #define DMA_DCHPRI13_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4327 #define DMA_DCHPRI13_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4328 #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4329 #define DMA_DCHPRI13_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4330 #define DMA_DCHPRI13_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4331 #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4332
kadonotakashi 0:8fdf9a60065b 4333 /*! @name DCHPRI12 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4334 #define DMA_DCHPRI12_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4335 #define DMA_DCHPRI12_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4336 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4337 #define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4338 #define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4339 #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4340 #define DMA_DCHPRI12_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4341 #define DMA_DCHPRI12_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4342 #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4343 #define DMA_DCHPRI12_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4344 #define DMA_DCHPRI12_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4345 #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4346
kadonotakashi 0:8fdf9a60065b 4347 /*! @name DCHPRI19 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4348 #define DMA_DCHPRI19_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4349 #define DMA_DCHPRI19_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4350 #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4351 #define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4352 #define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4353 #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4354 #define DMA_DCHPRI19_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4355 #define DMA_DCHPRI19_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4356 #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4357 #define DMA_DCHPRI19_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4358 #define DMA_DCHPRI19_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4359 #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4360
kadonotakashi 0:8fdf9a60065b 4361 /*! @name DCHPRI18 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4362 #define DMA_DCHPRI18_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4363 #define DMA_DCHPRI18_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4364 #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4365 #define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4366 #define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4367 #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4368 #define DMA_DCHPRI18_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4369 #define DMA_DCHPRI18_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4370 #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4371 #define DMA_DCHPRI18_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4372 #define DMA_DCHPRI18_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4373 #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4374
kadonotakashi 0:8fdf9a60065b 4375 /*! @name DCHPRI17 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4376 #define DMA_DCHPRI17_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4377 #define DMA_DCHPRI17_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4378 #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4379 #define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4380 #define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4381 #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4382 #define DMA_DCHPRI17_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4383 #define DMA_DCHPRI17_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4384 #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4385 #define DMA_DCHPRI17_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4386 #define DMA_DCHPRI17_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4387 #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4388
kadonotakashi 0:8fdf9a60065b 4389 /*! @name DCHPRI16 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4390 #define DMA_DCHPRI16_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4391 #define DMA_DCHPRI16_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4392 #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4393 #define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4394 #define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4395 #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4396 #define DMA_DCHPRI16_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4397 #define DMA_DCHPRI16_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4398 #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4399 #define DMA_DCHPRI16_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4400 #define DMA_DCHPRI16_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4401 #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4402
kadonotakashi 0:8fdf9a60065b 4403 /*! @name DCHPRI23 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4404 #define DMA_DCHPRI23_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4405 #define DMA_DCHPRI23_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4406 #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4407 #define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4408 #define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4409 #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4410 #define DMA_DCHPRI23_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4411 #define DMA_DCHPRI23_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4412 #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4413 #define DMA_DCHPRI23_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4414 #define DMA_DCHPRI23_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4415 #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4416
kadonotakashi 0:8fdf9a60065b 4417 /*! @name DCHPRI22 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4418 #define DMA_DCHPRI22_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4419 #define DMA_DCHPRI22_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4420 #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4421 #define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4422 #define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4423 #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4424 #define DMA_DCHPRI22_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4425 #define DMA_DCHPRI22_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4426 #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4427 #define DMA_DCHPRI22_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4428 #define DMA_DCHPRI22_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4429 #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4430
kadonotakashi 0:8fdf9a60065b 4431 /*! @name DCHPRI21 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4432 #define DMA_DCHPRI21_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4433 #define DMA_DCHPRI21_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4434 #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4435 #define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4436 #define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4437 #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4438 #define DMA_DCHPRI21_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4439 #define DMA_DCHPRI21_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4440 #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4441 #define DMA_DCHPRI21_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4442 #define DMA_DCHPRI21_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4443 #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4444
kadonotakashi 0:8fdf9a60065b 4445 /*! @name DCHPRI20 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4446 #define DMA_DCHPRI20_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4447 #define DMA_DCHPRI20_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4448 #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4449 #define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4450 #define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4451 #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4452 #define DMA_DCHPRI20_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4453 #define DMA_DCHPRI20_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4454 #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4455 #define DMA_DCHPRI20_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4456 #define DMA_DCHPRI20_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4457 #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4458
kadonotakashi 0:8fdf9a60065b 4459 /*! @name DCHPRI27 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4460 #define DMA_DCHPRI27_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4461 #define DMA_DCHPRI27_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4462 #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4463 #define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4464 #define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4465 #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4466 #define DMA_DCHPRI27_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4467 #define DMA_DCHPRI27_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4468 #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4469 #define DMA_DCHPRI27_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4470 #define DMA_DCHPRI27_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4471 #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4472
kadonotakashi 0:8fdf9a60065b 4473 /*! @name DCHPRI26 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4474 #define DMA_DCHPRI26_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4475 #define DMA_DCHPRI26_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4476 #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4477 #define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4478 #define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4479 #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4480 #define DMA_DCHPRI26_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4481 #define DMA_DCHPRI26_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4482 #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4483 #define DMA_DCHPRI26_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4484 #define DMA_DCHPRI26_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4485 #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4486
kadonotakashi 0:8fdf9a60065b 4487 /*! @name DCHPRI25 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4488 #define DMA_DCHPRI25_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4489 #define DMA_DCHPRI25_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4490 #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4491 #define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4492 #define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4493 #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4494 #define DMA_DCHPRI25_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4495 #define DMA_DCHPRI25_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4496 #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4497 #define DMA_DCHPRI25_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4498 #define DMA_DCHPRI25_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4499 #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4500
kadonotakashi 0:8fdf9a60065b 4501 /*! @name DCHPRI24 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4502 #define DMA_DCHPRI24_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4503 #define DMA_DCHPRI24_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4504 #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4505 #define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4506 #define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4507 #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4508 #define DMA_DCHPRI24_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4509 #define DMA_DCHPRI24_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4510 #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4511 #define DMA_DCHPRI24_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4512 #define DMA_DCHPRI24_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4513 #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4514
kadonotakashi 0:8fdf9a60065b 4515 /*! @name DCHPRI31 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4516 #define DMA_DCHPRI31_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4517 #define DMA_DCHPRI31_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4518 #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4519 #define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4520 #define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4521 #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4522 #define DMA_DCHPRI31_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4523 #define DMA_DCHPRI31_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4524 #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4525 #define DMA_DCHPRI31_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4526 #define DMA_DCHPRI31_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4527 #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4528
kadonotakashi 0:8fdf9a60065b 4529 /*! @name DCHPRI30 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4530 #define DMA_DCHPRI30_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4531 #define DMA_DCHPRI30_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4532 #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4533 #define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4534 #define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4535 #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4536 #define DMA_DCHPRI30_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4537 #define DMA_DCHPRI30_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4538 #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4539 #define DMA_DCHPRI30_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4540 #define DMA_DCHPRI30_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4541 #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4542
kadonotakashi 0:8fdf9a60065b 4543 /*! @name DCHPRI29 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4544 #define DMA_DCHPRI29_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4545 #define DMA_DCHPRI29_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4546 #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4547 #define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4548 #define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4549 #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4550 #define DMA_DCHPRI29_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4551 #define DMA_DCHPRI29_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4552 #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4553 #define DMA_DCHPRI29_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4554 #define DMA_DCHPRI29_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4555 #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4556
kadonotakashi 0:8fdf9a60065b 4557 /*! @name DCHPRI28 - Channel n Priority Register */
kadonotakashi 0:8fdf9a60065b 4558 #define DMA_DCHPRI28_CHPRI_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 4559 #define DMA_DCHPRI28_CHPRI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4560 #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4561 #define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 4562 #define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4563 #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
kadonotakashi 0:8fdf9a60065b 4564 #define DMA_DCHPRI28_DPA_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4565 #define DMA_DCHPRI28_DPA_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4566 #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
kadonotakashi 0:8fdf9a60065b 4567 #define DMA_DCHPRI28_ECP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4568 #define DMA_DCHPRI28_ECP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4569 #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
kadonotakashi 0:8fdf9a60065b 4570
kadonotakashi 0:8fdf9a60065b 4571 /*! @name SADDR - TCD Source Address */
kadonotakashi 0:8fdf9a60065b 4572 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 4573 #define DMA_SADDR_SADDR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4574 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
kadonotakashi 0:8fdf9a60065b 4575
kadonotakashi 0:8fdf9a60065b 4576 /* The count of DMA_SADDR */
kadonotakashi 0:8fdf9a60065b 4577 #define DMA_SADDR_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4578
kadonotakashi 0:8fdf9a60065b 4579 /*! @name SOFF - TCD Signed Source Address Offset */
kadonotakashi 0:8fdf9a60065b 4580 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 4581 #define DMA_SOFF_SOFF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4582 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
kadonotakashi 0:8fdf9a60065b 4583
kadonotakashi 0:8fdf9a60065b 4584 /* The count of DMA_SOFF */
kadonotakashi 0:8fdf9a60065b 4585 #define DMA_SOFF_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4586
kadonotakashi 0:8fdf9a60065b 4587 /*! @name ATTR - TCD Transfer Attributes */
kadonotakashi 0:8fdf9a60065b 4588 #define DMA_ATTR_DSIZE_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 4589 #define DMA_ATTR_DSIZE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4590 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
kadonotakashi 0:8fdf9a60065b 4591 #define DMA_ATTR_DMOD_MASK (0xF8U)
kadonotakashi 0:8fdf9a60065b 4592 #define DMA_ATTR_DMOD_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 4593 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
kadonotakashi 0:8fdf9a60065b 4594 #define DMA_ATTR_SSIZE_MASK (0x700U)
kadonotakashi 0:8fdf9a60065b 4595 #define DMA_ATTR_SSIZE_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 4596 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
kadonotakashi 0:8fdf9a60065b 4597 #define DMA_ATTR_SMOD_MASK (0xF800U)
kadonotakashi 0:8fdf9a60065b 4598 #define DMA_ATTR_SMOD_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 4599 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
kadonotakashi 0:8fdf9a60065b 4600
kadonotakashi 0:8fdf9a60065b 4601 /* The count of DMA_ATTR */
kadonotakashi 0:8fdf9a60065b 4602 #define DMA_ATTR_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4603
kadonotakashi 0:8fdf9a60065b 4604 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
kadonotakashi 0:8fdf9a60065b 4605 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 4606 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4607 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
kadonotakashi 0:8fdf9a60065b 4608
kadonotakashi 0:8fdf9a60065b 4609 /* The count of DMA_NBYTES_MLNO */
kadonotakashi 0:8fdf9a60065b 4610 #define DMA_NBYTES_MLNO_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4611
kadonotakashi 0:8fdf9a60065b 4612 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
kadonotakashi 0:8fdf9a60065b 4613 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
kadonotakashi 0:8fdf9a60065b 4614 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4615 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
kadonotakashi 0:8fdf9a60065b 4616 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 4617 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 4618 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
kadonotakashi 0:8fdf9a60065b 4619 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 4620 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 4621 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
kadonotakashi 0:8fdf9a60065b 4622
kadonotakashi 0:8fdf9a60065b 4623 /* The count of DMA_NBYTES_MLOFFNO */
kadonotakashi 0:8fdf9a60065b 4624 #define DMA_NBYTES_MLOFFNO_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4625
kadonotakashi 0:8fdf9a60065b 4626 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
kadonotakashi 0:8fdf9a60065b 4627 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
kadonotakashi 0:8fdf9a60065b 4628 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4629 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
kadonotakashi 0:8fdf9a60065b 4630 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
kadonotakashi 0:8fdf9a60065b 4631 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 4632 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
kadonotakashi 0:8fdf9a60065b 4633 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 4634 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 4635 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
kadonotakashi 0:8fdf9a60065b 4636 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 4637 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 4638 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
kadonotakashi 0:8fdf9a60065b 4639
kadonotakashi 0:8fdf9a60065b 4640 /* The count of DMA_NBYTES_MLOFFYES */
kadonotakashi 0:8fdf9a60065b 4641 #define DMA_NBYTES_MLOFFYES_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4642
kadonotakashi 0:8fdf9a60065b 4643 /*! @name SLAST - TCD Last Source Address Adjustment */
kadonotakashi 0:8fdf9a60065b 4644 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 4645 #define DMA_SLAST_SLAST_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4646 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
kadonotakashi 0:8fdf9a60065b 4647
kadonotakashi 0:8fdf9a60065b 4648 /* The count of DMA_SLAST */
kadonotakashi 0:8fdf9a60065b 4649 #define DMA_SLAST_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4650
kadonotakashi 0:8fdf9a60065b 4651 /*! @name DADDR - TCD Destination Address */
kadonotakashi 0:8fdf9a60065b 4652 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 4653 #define DMA_DADDR_DADDR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4654 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
kadonotakashi 0:8fdf9a60065b 4655
kadonotakashi 0:8fdf9a60065b 4656 /* The count of DMA_DADDR */
kadonotakashi 0:8fdf9a60065b 4657 #define DMA_DADDR_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4658
kadonotakashi 0:8fdf9a60065b 4659 /*! @name DOFF - TCD Signed Destination Address Offset */
kadonotakashi 0:8fdf9a60065b 4660 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 4661 #define DMA_DOFF_DOFF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4662 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
kadonotakashi 0:8fdf9a60065b 4663
kadonotakashi 0:8fdf9a60065b 4664 /* The count of DMA_DOFF */
kadonotakashi 0:8fdf9a60065b 4665 #define DMA_DOFF_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4666
kadonotakashi 0:8fdf9a60065b 4667 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
kadonotakashi 0:8fdf9a60065b 4668 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
kadonotakashi 0:8fdf9a60065b 4669 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4670 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
kadonotakashi 0:8fdf9a60065b 4671 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 4672 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 4673 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
kadonotakashi 0:8fdf9a60065b 4674
kadonotakashi 0:8fdf9a60065b 4675 /* The count of DMA_CITER_ELINKNO */
kadonotakashi 0:8fdf9a60065b 4676 #define DMA_CITER_ELINKNO_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4677
kadonotakashi 0:8fdf9a60065b 4678 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
kadonotakashi 0:8fdf9a60065b 4679 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
kadonotakashi 0:8fdf9a60065b 4680 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4681 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
kadonotakashi 0:8fdf9a60065b 4682 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
kadonotakashi 0:8fdf9a60065b 4683 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 4684 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
kadonotakashi 0:8fdf9a60065b 4685 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 4686 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 4687 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
kadonotakashi 0:8fdf9a60065b 4688
kadonotakashi 0:8fdf9a60065b 4689 /* The count of DMA_CITER_ELINKYES */
kadonotakashi 0:8fdf9a60065b 4690 #define DMA_CITER_ELINKYES_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4691
kadonotakashi 0:8fdf9a60065b 4692 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
kadonotakashi 0:8fdf9a60065b 4693 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 4694 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4695 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
kadonotakashi 0:8fdf9a60065b 4696
kadonotakashi 0:8fdf9a60065b 4697 /* The count of DMA_DLAST_SGA */
kadonotakashi 0:8fdf9a60065b 4698 #define DMA_DLAST_SGA_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4699
kadonotakashi 0:8fdf9a60065b 4700 /*! @name CSR - TCD Control and Status */
kadonotakashi 0:8fdf9a60065b 4701 #define DMA_CSR_START_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 4702 #define DMA_CSR_START_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4703 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
kadonotakashi 0:8fdf9a60065b 4704 #define DMA_CSR_INTMAJOR_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 4705 #define DMA_CSR_INTMAJOR_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 4706 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
kadonotakashi 0:8fdf9a60065b 4707 #define DMA_CSR_INTHALF_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 4708 #define DMA_CSR_INTHALF_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 4709 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
kadonotakashi 0:8fdf9a60065b 4710 #define DMA_CSR_DREQ_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 4711 #define DMA_CSR_DREQ_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 4712 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
kadonotakashi 0:8fdf9a60065b 4713 #define DMA_CSR_ESG_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 4714 #define DMA_CSR_ESG_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4715 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
kadonotakashi 0:8fdf9a60065b 4716 #define DMA_CSR_MAJORELINK_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 4717 #define DMA_CSR_MAJORELINK_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 4718 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
kadonotakashi 0:8fdf9a60065b 4719 #define DMA_CSR_ACTIVE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4720 #define DMA_CSR_ACTIVE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4721 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
kadonotakashi 0:8fdf9a60065b 4722 #define DMA_CSR_DONE_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4723 #define DMA_CSR_DONE_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4724 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
kadonotakashi 0:8fdf9a60065b 4725 #define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
kadonotakashi 0:8fdf9a60065b 4726 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 4727 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
kadonotakashi 0:8fdf9a60065b 4728 #define DMA_CSR_BWC_MASK (0xC000U)
kadonotakashi 0:8fdf9a60065b 4729 #define DMA_CSR_BWC_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 4730 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
kadonotakashi 0:8fdf9a60065b 4731
kadonotakashi 0:8fdf9a60065b 4732 /* The count of DMA_CSR */
kadonotakashi 0:8fdf9a60065b 4733 #define DMA_CSR_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4734
kadonotakashi 0:8fdf9a60065b 4735 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
kadonotakashi 0:8fdf9a60065b 4736 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
kadonotakashi 0:8fdf9a60065b 4737 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4738 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
kadonotakashi 0:8fdf9a60065b 4739 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 4740 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 4741 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
kadonotakashi 0:8fdf9a60065b 4742
kadonotakashi 0:8fdf9a60065b 4743 /* The count of DMA_BITER_ELINKNO */
kadonotakashi 0:8fdf9a60065b 4744 #define DMA_BITER_ELINKNO_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4745
kadonotakashi 0:8fdf9a60065b 4746 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
kadonotakashi 0:8fdf9a60065b 4747 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
kadonotakashi 0:8fdf9a60065b 4748 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4749 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
kadonotakashi 0:8fdf9a60065b 4750 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
kadonotakashi 0:8fdf9a60065b 4751 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 4752 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
kadonotakashi 0:8fdf9a60065b 4753 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 4754 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 4755 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
kadonotakashi 0:8fdf9a60065b 4756
kadonotakashi 0:8fdf9a60065b 4757 /* The count of DMA_BITER_ELINKYES */
kadonotakashi 0:8fdf9a60065b 4758 #define DMA_BITER_ELINKYES_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4759
kadonotakashi 0:8fdf9a60065b 4760
kadonotakashi 0:8fdf9a60065b 4761 /*!
kadonotakashi 0:8fdf9a60065b 4762 * @}
kadonotakashi 0:8fdf9a60065b 4763 */ /* end of group DMA_Register_Masks */
kadonotakashi 0:8fdf9a60065b 4764
kadonotakashi 0:8fdf9a60065b 4765
kadonotakashi 0:8fdf9a60065b 4766 /* DMA - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 4767 /** Peripheral DMA base address */
kadonotakashi 0:8fdf9a60065b 4768 #define DMA_BASE (0x40008000u)
kadonotakashi 0:8fdf9a60065b 4769 /** Peripheral DMA base pointer */
kadonotakashi 0:8fdf9a60065b 4770 #define DMA0 ((DMA_Type *)DMA_BASE)
kadonotakashi 0:8fdf9a60065b 4771 /** Array initializer of DMA peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 4772 #define DMA_BASE_ADDRS { DMA_BASE }
kadonotakashi 0:8fdf9a60065b 4773 /** Array initializer of DMA peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 4774 #define DMA_BASE_PTRS { DMA0 }
kadonotakashi 0:8fdf9a60065b 4775 /** Interrupt vectors for the DMA peripheral type */
kadonotakashi 0:8fdf9a60065b 4776 #define DMA_CHN_IRQS { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn }
kadonotakashi 0:8fdf9a60065b 4777 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
kadonotakashi 0:8fdf9a60065b 4778
kadonotakashi 0:8fdf9a60065b 4779 /*!
kadonotakashi 0:8fdf9a60065b 4780 * @}
kadonotakashi 0:8fdf9a60065b 4781 */ /* end of group DMA_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 4782
kadonotakashi 0:8fdf9a60065b 4783
kadonotakashi 0:8fdf9a60065b 4784 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 4785 -- DMAMUX Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 4786 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 4787
kadonotakashi 0:8fdf9a60065b 4788 /*!
kadonotakashi 0:8fdf9a60065b 4789 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 4790 * @{
kadonotakashi 0:8fdf9a60065b 4791 */
kadonotakashi 0:8fdf9a60065b 4792
kadonotakashi 0:8fdf9a60065b 4793 /** DMAMUX - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 4794 typedef struct {
kadonotakashi 0:8fdf9a60065b 4795 __IO uint8_t CHCFG[32]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
kadonotakashi 0:8fdf9a60065b 4796 } DMAMUX_Type;
kadonotakashi 0:8fdf9a60065b 4797
kadonotakashi 0:8fdf9a60065b 4798 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 4799 -- DMAMUX Register Masks
kadonotakashi 0:8fdf9a60065b 4800 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 4801
kadonotakashi 0:8fdf9a60065b 4802 /*!
kadonotakashi 0:8fdf9a60065b 4803 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
kadonotakashi 0:8fdf9a60065b 4804 * @{
kadonotakashi 0:8fdf9a60065b 4805 */
kadonotakashi 0:8fdf9a60065b 4806
kadonotakashi 0:8fdf9a60065b 4807 /*! @name CHCFG - Channel Configuration register */
kadonotakashi 0:8fdf9a60065b 4808 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 4809 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4810 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
kadonotakashi 0:8fdf9a60065b 4811 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 4812 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 4813 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
kadonotakashi 0:8fdf9a60065b 4814 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 4815 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 4816 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
kadonotakashi 0:8fdf9a60065b 4817
kadonotakashi 0:8fdf9a60065b 4818 /* The count of DMAMUX_CHCFG */
kadonotakashi 0:8fdf9a60065b 4819 #define DMAMUX_CHCFG_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 4820
kadonotakashi 0:8fdf9a60065b 4821
kadonotakashi 0:8fdf9a60065b 4822 /*!
kadonotakashi 0:8fdf9a60065b 4823 * @}
kadonotakashi 0:8fdf9a60065b 4824 */ /* end of group DMAMUX_Register_Masks */
kadonotakashi 0:8fdf9a60065b 4825
kadonotakashi 0:8fdf9a60065b 4826
kadonotakashi 0:8fdf9a60065b 4827 /* DMAMUX - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 4828 /** Peripheral DMAMUX base address */
kadonotakashi 0:8fdf9a60065b 4829 #define DMAMUX_BASE (0x40021000u)
kadonotakashi 0:8fdf9a60065b 4830 /** Peripheral DMAMUX base pointer */
kadonotakashi 0:8fdf9a60065b 4831 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
kadonotakashi 0:8fdf9a60065b 4832 /** Array initializer of DMAMUX peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 4833 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
kadonotakashi 0:8fdf9a60065b 4834 /** Array initializer of DMAMUX peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 4835 #define DMAMUX_BASE_PTRS { DMAMUX }
kadonotakashi 0:8fdf9a60065b 4836
kadonotakashi 0:8fdf9a60065b 4837 /*!
kadonotakashi 0:8fdf9a60065b 4838 * @}
kadonotakashi 0:8fdf9a60065b 4839 */ /* end of group DMAMUX_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 4840
kadonotakashi 0:8fdf9a60065b 4841
kadonotakashi 0:8fdf9a60065b 4842 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 4843 -- EMVSIM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 4844 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 4845
kadonotakashi 0:8fdf9a60065b 4846 /*!
kadonotakashi 0:8fdf9a60065b 4847 * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 4848 * @{
kadonotakashi 0:8fdf9a60065b 4849 */
kadonotakashi 0:8fdf9a60065b 4850
kadonotakashi 0:8fdf9a60065b 4851 /** EMVSIM - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 4852 typedef struct {
kadonotakashi 0:8fdf9a60065b 4853 __I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 4854 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 4855 __IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 4856 __IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 4857 __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 4858 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 4859 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 4860 __IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */
kadonotakashi 0:8fdf9a60065b 4861 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 4862 __IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 4863 __IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */
kadonotakashi 0:8fdf9a60065b 4864 __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */
kadonotakashi 0:8fdf9a60065b 4865 __IO uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */
kadonotakashi 0:8fdf9a60065b 4866 __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 4867 __IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */
kadonotakashi 0:8fdf9a60065b 4868 __IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */
kadonotakashi 0:8fdf9a60065b 4869 __IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */
kadonotakashi 0:8fdf9a60065b 4870 __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
kadonotakashi 0:8fdf9a60065b 4871 __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
kadonotakashi 0:8fdf9a60065b 4872 } EMVSIM_Type;
kadonotakashi 0:8fdf9a60065b 4873
kadonotakashi 0:8fdf9a60065b 4874 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 4875 -- EMVSIM Register Masks
kadonotakashi 0:8fdf9a60065b 4876 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 4877
kadonotakashi 0:8fdf9a60065b 4878 /*!
kadonotakashi 0:8fdf9a60065b 4879 * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
kadonotakashi 0:8fdf9a60065b 4880 * @{
kadonotakashi 0:8fdf9a60065b 4881 */
kadonotakashi 0:8fdf9a60065b 4882
kadonotakashi 0:8fdf9a60065b 4883 /*! @name VER_ID - Version ID Register */
kadonotakashi 0:8fdf9a60065b 4884 #define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 4885 #define EMVSIM_VER_ID_VER_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4886 #define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
kadonotakashi 0:8fdf9a60065b 4887
kadonotakashi 0:8fdf9a60065b 4888 /*! @name PARAM - Parameter Register */
kadonotakashi 0:8fdf9a60065b 4889 #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 4890 #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4891 #define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
kadonotakashi 0:8fdf9a60065b 4892 #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 4893 #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 4894 #define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
kadonotakashi 0:8fdf9a60065b 4895
kadonotakashi 0:8fdf9a60065b 4896 /*! @name CLKCFG - Clock Configuration Register */
kadonotakashi 0:8fdf9a60065b 4897 #define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 4898 #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4899 #define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
kadonotakashi 0:8fdf9a60065b 4900 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U)
kadonotakashi 0:8fdf9a60065b 4901 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 4902 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
kadonotakashi 0:8fdf9a60065b 4903 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U)
kadonotakashi 0:8fdf9a60065b 4904 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 4905 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
kadonotakashi 0:8fdf9a60065b 4906
kadonotakashi 0:8fdf9a60065b 4907 /*! @name DIVISOR - Baud Rate Divisor Register */
kadonotakashi 0:8fdf9a60065b 4908 #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU)
kadonotakashi 0:8fdf9a60065b 4909 #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4910 #define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
kadonotakashi 0:8fdf9a60065b 4911
kadonotakashi 0:8fdf9a60065b 4912 /*! @name CTRL - Control Register */
kadonotakashi 0:8fdf9a60065b 4913 #define EMVSIM_CTRL_IC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 4914 #define EMVSIM_CTRL_IC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4915 #define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
kadonotakashi 0:8fdf9a60065b 4916 #define EMVSIM_CTRL_ICM_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 4917 #define EMVSIM_CTRL_ICM_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 4918 #define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
kadonotakashi 0:8fdf9a60065b 4919 #define EMVSIM_CTRL_ANACK_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 4920 #define EMVSIM_CTRL_ANACK_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 4921 #define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
kadonotakashi 0:8fdf9a60065b 4922 #define EMVSIM_CTRL_ONACK_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 4923 #define EMVSIM_CTRL_ONACK_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 4924 #define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
kadonotakashi 0:8fdf9a60065b 4925 #define EMVSIM_CTRL_FLSH_RX_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 4926 #define EMVSIM_CTRL_FLSH_RX_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 4927 #define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
kadonotakashi 0:8fdf9a60065b 4928 #define EMVSIM_CTRL_FLSH_TX_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 4929 #define EMVSIM_CTRL_FLSH_TX_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 4930 #define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
kadonotakashi 0:8fdf9a60065b 4931 #define EMVSIM_CTRL_SW_RST_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 4932 #define EMVSIM_CTRL_SW_RST_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 4933 #define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
kadonotakashi 0:8fdf9a60065b 4934 #define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 4935 #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 4936 #define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
kadonotakashi 0:8fdf9a60065b 4937 #define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 4938 #define EMVSIM_CTRL_DOZE_EN_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 4939 #define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
kadonotakashi 0:8fdf9a60065b 4940 #define EMVSIM_CTRL_STOP_EN_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 4941 #define EMVSIM_CTRL_STOP_EN_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 4942 #define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
kadonotakashi 0:8fdf9a60065b 4943 #define EMVSIM_CTRL_RCV_EN_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 4944 #define EMVSIM_CTRL_RCV_EN_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 4945 #define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
kadonotakashi 0:8fdf9a60065b 4946 #define EMVSIM_CTRL_XMT_EN_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 4947 #define EMVSIM_CTRL_XMT_EN_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 4948 #define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
kadonotakashi 0:8fdf9a60065b 4949 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 4950 #define EMVSIM_CTRL_RCVR_11_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 4951 #define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
kadonotakashi 0:8fdf9a60065b 4952 #define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 4953 #define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 4954 #define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
kadonotakashi 0:8fdf9a60065b 4955 #define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 4956 #define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 4957 #define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
kadonotakashi 0:8fdf9a60065b 4958 #define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 4959 #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 4960 #define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
kadonotakashi 0:8fdf9a60065b 4961 #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 4962 #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 4963 #define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
kadonotakashi 0:8fdf9a60065b 4964 #define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 4965 #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 4966 #define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
kadonotakashi 0:8fdf9a60065b 4967 #define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 4968 #define EMVSIM_CTRL_CWT_EN_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 4969 #define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
kadonotakashi 0:8fdf9a60065b 4970 #define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 4971 #define EMVSIM_CTRL_LRC_EN_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 4972 #define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
kadonotakashi 0:8fdf9a60065b 4973 #define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 4974 #define EMVSIM_CTRL_CRC_EN_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 4975 #define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
kadonotakashi 0:8fdf9a60065b 4976 #define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 4977 #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 4978 #define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
kadonotakashi 0:8fdf9a60065b 4979 #define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 4980 #define EMVSIM_CTRL_BWT_EN_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 4981 #define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
kadonotakashi 0:8fdf9a60065b 4982
kadonotakashi 0:8fdf9a60065b 4983 /*! @name INT_MASK - Interrupt Mask Register */
kadonotakashi 0:8fdf9a60065b 4984 #define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 4985 #define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 4986 #define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
kadonotakashi 0:8fdf9a60065b 4987 #define EMVSIM_INT_MASK_TC_IM_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 4988 #define EMVSIM_INT_MASK_TC_IM_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 4989 #define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
kadonotakashi 0:8fdf9a60065b 4990 #define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 4991 #define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 4992 #define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
kadonotakashi 0:8fdf9a60065b 4993 #define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 4994 #define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 4995 #define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
kadonotakashi 0:8fdf9a60065b 4996 #define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 4997 #define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 4998 #define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
kadonotakashi 0:8fdf9a60065b 4999 #define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 5000 #define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 5001 #define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
kadonotakashi 0:8fdf9a60065b 5002 #define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 5003 #define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 5004 #define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
kadonotakashi 0:8fdf9a60065b 5005 #define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 5006 #define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 5007 #define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
kadonotakashi 0:8fdf9a60065b 5008 #define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 5009 #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5010 #define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
kadonotakashi 0:8fdf9a60065b 5011 #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 5012 #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 5013 #define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
kadonotakashi 0:8fdf9a60065b 5014 #define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 5015 #define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 5016 #define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
kadonotakashi 0:8fdf9a60065b 5017 #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 5018 #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 5019 #define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
kadonotakashi 0:8fdf9a60065b 5020 #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 5021 #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 5022 #define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
kadonotakashi 0:8fdf9a60065b 5023 #define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 5024 #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 5025 #define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
kadonotakashi 0:8fdf9a60065b 5026 #define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 5027 #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 5028 #define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
kadonotakashi 0:8fdf9a60065b 5029 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 5030 #define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 5031 #define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
kadonotakashi 0:8fdf9a60065b 5032
kadonotakashi 0:8fdf9a60065b 5033 /*! @name RX_THD - Receiver Threshold Register */
kadonotakashi 0:8fdf9a60065b 5034 #define EMVSIM_RX_THD_RDT_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 5035 #define EMVSIM_RX_THD_RDT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5036 #define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
kadonotakashi 0:8fdf9a60065b 5037 #define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 5038 #define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5039 #define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
kadonotakashi 0:8fdf9a60065b 5040
kadonotakashi 0:8fdf9a60065b 5041 /*! @name TX_THD - Transmitter Threshold Register */
kadonotakashi 0:8fdf9a60065b 5042 #define EMVSIM_TX_THD_TDT_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 5043 #define EMVSIM_TX_THD_TDT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5044 #define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
kadonotakashi 0:8fdf9a60065b 5045 #define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 5046 #define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5047 #define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
kadonotakashi 0:8fdf9a60065b 5048
kadonotakashi 0:8fdf9a60065b 5049 /*! @name RX_STATUS - Receive Status Register */
kadonotakashi 0:8fdf9a60065b 5050 #define EMVSIM_RX_STATUS_RFO_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 5051 #define EMVSIM_RX_STATUS_RFO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5052 #define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
kadonotakashi 0:8fdf9a60065b 5053 #define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 5054 #define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 5055 #define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
kadonotakashi 0:8fdf9a60065b 5056 #define EMVSIM_RX_STATUS_RDTF_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 5057 #define EMVSIM_RX_STATUS_RDTF_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 5058 #define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
kadonotakashi 0:8fdf9a60065b 5059 #define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 5060 #define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 5061 #define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
kadonotakashi 0:8fdf9a60065b 5062 #define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 5063 #define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 5064 #define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
kadonotakashi 0:8fdf9a60065b 5065 #define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 5066 #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5067 #define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
kadonotakashi 0:8fdf9a60065b 5068 #define EMVSIM_RX_STATUS_RTE_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 5069 #define EMVSIM_RX_STATUS_RTE_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 5070 #define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
kadonotakashi 0:8fdf9a60065b 5071 #define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 5072 #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 5073 #define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
kadonotakashi 0:8fdf9a60065b 5074 #define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 5075 #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 5076 #define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
kadonotakashi 0:8fdf9a60065b 5077 #define EMVSIM_RX_STATUS_PEF_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 5078 #define EMVSIM_RX_STATUS_PEF_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 5079 #define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
kadonotakashi 0:8fdf9a60065b 5080 #define EMVSIM_RX_STATUS_FEF_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 5081 #define EMVSIM_RX_STATUS_FEF_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 5082 #define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
kadonotakashi 0:8fdf9a60065b 5083 #define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 5084 #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5085 #define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
kadonotakashi 0:8fdf9a60065b 5086 #define EMVSIM_RX_STATUS_RX_CNT_MASK (0x1F000000U)
kadonotakashi 0:8fdf9a60065b 5087 #define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 5088 #define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
kadonotakashi 0:8fdf9a60065b 5089
kadonotakashi 0:8fdf9a60065b 5090 /*! @name TX_STATUS - Transmitter Status Register */
kadonotakashi 0:8fdf9a60065b 5091 #define EMVSIM_TX_STATUS_TNTE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 5092 #define EMVSIM_TX_STATUS_TNTE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5093 #define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
kadonotakashi 0:8fdf9a60065b 5094 #define EMVSIM_TX_STATUS_TFE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 5095 #define EMVSIM_TX_STATUS_TFE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 5096 #define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
kadonotakashi 0:8fdf9a60065b 5097 #define EMVSIM_TX_STATUS_ETCF_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 5098 #define EMVSIM_TX_STATUS_ETCF_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 5099 #define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
kadonotakashi 0:8fdf9a60065b 5100 #define EMVSIM_TX_STATUS_TCF_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 5101 #define EMVSIM_TX_STATUS_TCF_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 5102 #define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
kadonotakashi 0:8fdf9a60065b 5103 #define EMVSIM_TX_STATUS_TFF_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 5104 #define EMVSIM_TX_STATUS_TFF_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 5105 #define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
kadonotakashi 0:8fdf9a60065b 5106 #define EMVSIM_TX_STATUS_TDTF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 5107 #define EMVSIM_TX_STATUS_TDTF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 5108 #define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
kadonotakashi 0:8fdf9a60065b 5109 #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 5110 #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5111 #define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
kadonotakashi 0:8fdf9a60065b 5112 #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 5113 #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 5114 #define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
kadonotakashi 0:8fdf9a60065b 5115 #define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 5116 #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5117 #define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
kadonotakashi 0:8fdf9a60065b 5118 #define EMVSIM_TX_STATUS_TX_CNT_MASK (0x1F000000U)
kadonotakashi 0:8fdf9a60065b 5119 #define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 5120 #define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
kadonotakashi 0:8fdf9a60065b 5121
kadonotakashi 0:8fdf9a60065b 5122 /*! @name PCSR - Port Control and Status Register */
kadonotakashi 0:8fdf9a60065b 5123 #define EMVSIM_PCSR_SAPD_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 5124 #define EMVSIM_PCSR_SAPD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5125 #define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
kadonotakashi 0:8fdf9a60065b 5126 #define EMVSIM_PCSR_SVCC_EN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 5127 #define EMVSIM_PCSR_SVCC_EN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 5128 #define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
kadonotakashi 0:8fdf9a60065b 5129 #define EMVSIM_PCSR_VCCENP_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 5130 #define EMVSIM_PCSR_VCCENP_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 5131 #define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
kadonotakashi 0:8fdf9a60065b 5132 #define EMVSIM_PCSR_SRST_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 5133 #define EMVSIM_PCSR_SRST_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 5134 #define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
kadonotakashi 0:8fdf9a60065b 5135 #define EMVSIM_PCSR_SCEN_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 5136 #define EMVSIM_PCSR_SCEN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 5137 #define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
kadonotakashi 0:8fdf9a60065b 5138 #define EMVSIM_PCSR_SCSP_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 5139 #define EMVSIM_PCSR_SCSP_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 5140 #define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
kadonotakashi 0:8fdf9a60065b 5141 #define EMVSIM_PCSR_SPD_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 5142 #define EMVSIM_PCSR_SPD_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 5143 #define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
kadonotakashi 0:8fdf9a60065b 5144 #define EMVSIM_PCSR_SPDIM_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 5145 #define EMVSIM_PCSR_SPDIM_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 5146 #define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
kadonotakashi 0:8fdf9a60065b 5147 #define EMVSIM_PCSR_SPDIF_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 5148 #define EMVSIM_PCSR_SPDIF_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 5149 #define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
kadonotakashi 0:8fdf9a60065b 5150 #define EMVSIM_PCSR_SPDP_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 5151 #define EMVSIM_PCSR_SPDP_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 5152 #define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
kadonotakashi 0:8fdf9a60065b 5153 #define EMVSIM_PCSR_SPDES_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 5154 #define EMVSIM_PCSR_SPDES_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 5155 #define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
kadonotakashi 0:8fdf9a60065b 5156
kadonotakashi 0:8fdf9a60065b 5157 /*! @name RX_BUF - Receive Data Read Buffer */
kadonotakashi 0:8fdf9a60065b 5158 #define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5159 #define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5160 #define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
kadonotakashi 0:8fdf9a60065b 5161
kadonotakashi 0:8fdf9a60065b 5162 /*! @name TX_BUF - Transmit Data Buffer */
kadonotakashi 0:8fdf9a60065b 5163 #define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5164 #define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5165 #define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
kadonotakashi 0:8fdf9a60065b 5166
kadonotakashi 0:8fdf9a60065b 5167 /*! @name TX_GETU - Transmitter Guard ETU Value Register */
kadonotakashi 0:8fdf9a60065b 5168 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5169 #define EMVSIM_TX_GETU_GETU_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5170 #define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
kadonotakashi 0:8fdf9a60065b 5171
kadonotakashi 0:8fdf9a60065b 5172 /*! @name CWT_VAL - Character Wait Time Value Register */
kadonotakashi 0:8fdf9a60065b 5173 #define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 5174 #define EMVSIM_CWT_VAL_CWT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5175 #define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
kadonotakashi 0:8fdf9a60065b 5176
kadonotakashi 0:8fdf9a60065b 5177 /*! @name BWT_VAL - Block Wait Time Value Register */
kadonotakashi 0:8fdf9a60065b 5178 #define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5179 #define EMVSIM_BWT_VAL_BWT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5180 #define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
kadonotakashi 0:8fdf9a60065b 5181
kadonotakashi 0:8fdf9a60065b 5182 /*! @name BGT_VAL - Block Guard Time Value Register */
kadonotakashi 0:8fdf9a60065b 5183 #define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 5184 #define EMVSIM_BGT_VAL_BGT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5185 #define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
kadonotakashi 0:8fdf9a60065b 5186
kadonotakashi 0:8fdf9a60065b 5187 /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
kadonotakashi 0:8fdf9a60065b 5188 #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 5189 #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5190 #define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
kadonotakashi 0:8fdf9a60065b 5191
kadonotakashi 0:8fdf9a60065b 5192 /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
kadonotakashi 0:8fdf9a60065b 5193 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 5194 #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5195 #define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
kadonotakashi 0:8fdf9a60065b 5196
kadonotakashi 0:8fdf9a60065b 5197
kadonotakashi 0:8fdf9a60065b 5198 /*!
kadonotakashi 0:8fdf9a60065b 5199 * @}
kadonotakashi 0:8fdf9a60065b 5200 */ /* end of group EMVSIM_Register_Masks */
kadonotakashi 0:8fdf9a60065b 5201
kadonotakashi 0:8fdf9a60065b 5202
kadonotakashi 0:8fdf9a60065b 5203 /* EMVSIM - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 5204 /** Peripheral EMVSIM0 base address */
kadonotakashi 0:8fdf9a60065b 5205 #define EMVSIM0_BASE (0x400D4000u)
kadonotakashi 0:8fdf9a60065b 5206 /** Peripheral EMVSIM0 base pointer */
kadonotakashi 0:8fdf9a60065b 5207 #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE)
kadonotakashi 0:8fdf9a60065b 5208 /** Peripheral EMVSIM1 base address */
kadonotakashi 0:8fdf9a60065b 5209 #define EMVSIM1_BASE (0x400D5000u)
kadonotakashi 0:8fdf9a60065b 5210 /** Peripheral EMVSIM1 base pointer */
kadonotakashi 0:8fdf9a60065b 5211 #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE)
kadonotakashi 0:8fdf9a60065b 5212 /** Array initializer of EMVSIM peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 5213 #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE }
kadonotakashi 0:8fdf9a60065b 5214 /** Array initializer of EMVSIM peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 5215 #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 }
kadonotakashi 0:8fdf9a60065b 5216 /** Interrupt vectors for the EMVSIM peripheral type */
kadonotakashi 0:8fdf9a60065b 5217 #define EMVSIM_IRQS { EMVSIM0_IRQn, EMVSIM1_IRQn }
kadonotakashi 0:8fdf9a60065b 5218
kadonotakashi 0:8fdf9a60065b 5219 /*!
kadonotakashi 0:8fdf9a60065b 5220 * @}
kadonotakashi 0:8fdf9a60065b 5221 */ /* end of group EMVSIM_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 5222
kadonotakashi 0:8fdf9a60065b 5223
kadonotakashi 0:8fdf9a60065b 5224 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 5225 -- EWM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 5226 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 5227
kadonotakashi 0:8fdf9a60065b 5228 /*!
kadonotakashi 0:8fdf9a60065b 5229 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 5230 * @{
kadonotakashi 0:8fdf9a60065b 5231 */
kadonotakashi 0:8fdf9a60065b 5232
kadonotakashi 0:8fdf9a60065b 5233 /** EWM - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 5234 typedef struct {
kadonotakashi 0:8fdf9a60065b 5235 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 5236 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 5237 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 5238 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
kadonotakashi 0:8fdf9a60065b 5239 __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 5240 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
kadonotakashi 0:8fdf9a60065b 5241 } EWM_Type;
kadonotakashi 0:8fdf9a60065b 5242
kadonotakashi 0:8fdf9a60065b 5243 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 5244 -- EWM Register Masks
kadonotakashi 0:8fdf9a60065b 5245 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 5246
kadonotakashi 0:8fdf9a60065b 5247 /*!
kadonotakashi 0:8fdf9a60065b 5248 * @addtogroup EWM_Register_Masks EWM Register Masks
kadonotakashi 0:8fdf9a60065b 5249 * @{
kadonotakashi 0:8fdf9a60065b 5250 */
kadonotakashi 0:8fdf9a60065b 5251
kadonotakashi 0:8fdf9a60065b 5252 /*! @name CTRL - Control Register */
kadonotakashi 0:8fdf9a60065b 5253 #define EWM_CTRL_EWMEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 5254 #define EWM_CTRL_EWMEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5255 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
kadonotakashi 0:8fdf9a60065b 5256 #define EWM_CTRL_ASSIN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 5257 #define EWM_CTRL_ASSIN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 5258 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
kadonotakashi 0:8fdf9a60065b 5259 #define EWM_CTRL_INEN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 5260 #define EWM_CTRL_INEN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 5261 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
kadonotakashi 0:8fdf9a60065b 5262 #define EWM_CTRL_INTEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 5263 #define EWM_CTRL_INTEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 5264 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
kadonotakashi 0:8fdf9a60065b 5265
kadonotakashi 0:8fdf9a60065b 5266 /*! @name SERV - Service Register */
kadonotakashi 0:8fdf9a60065b 5267 #define EWM_SERV_SERVICE_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5268 #define EWM_SERV_SERVICE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5269 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
kadonotakashi 0:8fdf9a60065b 5270
kadonotakashi 0:8fdf9a60065b 5271 /*! @name CMPL - Compare Low Register */
kadonotakashi 0:8fdf9a60065b 5272 #define EWM_CMPL_COMPAREL_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5273 #define EWM_CMPL_COMPAREL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5274 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
kadonotakashi 0:8fdf9a60065b 5275
kadonotakashi 0:8fdf9a60065b 5276 /*! @name CMPH - Compare High Register */
kadonotakashi 0:8fdf9a60065b 5277 #define EWM_CMPH_COMPAREH_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5278 #define EWM_CMPH_COMPAREH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5279 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
kadonotakashi 0:8fdf9a60065b 5280
kadonotakashi 0:8fdf9a60065b 5281 /*! @name CLKCTRL - Clock Control Register */
kadonotakashi 0:8fdf9a60065b 5282 #define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 5283 #define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5284 #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
kadonotakashi 0:8fdf9a60065b 5285
kadonotakashi 0:8fdf9a60065b 5286 /*! @name CLKPRESCALER - Clock Prescaler Register */
kadonotakashi 0:8fdf9a60065b 5287 #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5288 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5289 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
kadonotakashi 0:8fdf9a60065b 5290
kadonotakashi 0:8fdf9a60065b 5291
kadonotakashi 0:8fdf9a60065b 5292 /*!
kadonotakashi 0:8fdf9a60065b 5293 * @}
kadonotakashi 0:8fdf9a60065b 5294 */ /* end of group EWM_Register_Masks */
kadonotakashi 0:8fdf9a60065b 5295
kadonotakashi 0:8fdf9a60065b 5296
kadonotakashi 0:8fdf9a60065b 5297 /* EWM - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 5298 /** Peripheral EWM base address */
kadonotakashi 0:8fdf9a60065b 5299 #define EWM_BASE (0x40061000u)
kadonotakashi 0:8fdf9a60065b 5300 /** Peripheral EWM base pointer */
kadonotakashi 0:8fdf9a60065b 5301 #define EWM ((EWM_Type *)EWM_BASE)
kadonotakashi 0:8fdf9a60065b 5302 /** Array initializer of EWM peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 5303 #define EWM_BASE_ADDRS { EWM_BASE }
kadonotakashi 0:8fdf9a60065b 5304 /** Array initializer of EWM peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 5305 #define EWM_BASE_PTRS { EWM }
kadonotakashi 0:8fdf9a60065b 5306 /** Interrupt vectors for the EWM peripheral type */
kadonotakashi 0:8fdf9a60065b 5307 #define EWM_IRQS { WDOG_EWM_IRQn }
kadonotakashi 0:8fdf9a60065b 5308
kadonotakashi 0:8fdf9a60065b 5309 /*!
kadonotakashi 0:8fdf9a60065b 5310 * @}
kadonotakashi 0:8fdf9a60065b 5311 */ /* end of group EWM_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 5312
kadonotakashi 0:8fdf9a60065b 5313
kadonotakashi 0:8fdf9a60065b 5314 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 5315 -- FB Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 5316 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 5317
kadonotakashi 0:8fdf9a60065b 5318 /*!
kadonotakashi 0:8fdf9a60065b 5319 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 5320 * @{
kadonotakashi 0:8fdf9a60065b 5321 */
kadonotakashi 0:8fdf9a60065b 5322
kadonotakashi 0:8fdf9a60065b 5323 /** FB - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 5324 typedef struct {
kadonotakashi 0:8fdf9a60065b 5325 struct { /* offset: 0x0, array step: 0xC */
kadonotakashi 0:8fdf9a60065b 5326 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
kadonotakashi 0:8fdf9a60065b 5327 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
kadonotakashi 0:8fdf9a60065b 5328 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
kadonotakashi 0:8fdf9a60065b 5329 } CS[6];
kadonotakashi 0:8fdf9a60065b 5330 uint8_t RESERVED_0[24];
kadonotakashi 0:8fdf9a60065b 5331 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
kadonotakashi 0:8fdf9a60065b 5332 } FB_Type;
kadonotakashi 0:8fdf9a60065b 5333
kadonotakashi 0:8fdf9a60065b 5334 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 5335 -- FB Register Masks
kadonotakashi 0:8fdf9a60065b 5336 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 5337
kadonotakashi 0:8fdf9a60065b 5338 /*!
kadonotakashi 0:8fdf9a60065b 5339 * @addtogroup FB_Register_Masks FB Register Masks
kadonotakashi 0:8fdf9a60065b 5340 * @{
kadonotakashi 0:8fdf9a60065b 5341 */
kadonotakashi 0:8fdf9a60065b 5342
kadonotakashi 0:8fdf9a60065b 5343 /*! @name CSAR - Chip Select Address Register */
kadonotakashi 0:8fdf9a60065b 5344 #define FB_CSAR_BA_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 5345 #define FB_CSAR_BA_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5346 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
kadonotakashi 0:8fdf9a60065b 5347
kadonotakashi 0:8fdf9a60065b 5348 /* The count of FB_CSAR */
kadonotakashi 0:8fdf9a60065b 5349 #define FB_CSAR_COUNT (6U)
kadonotakashi 0:8fdf9a60065b 5350
kadonotakashi 0:8fdf9a60065b 5351 /*! @name CSMR - Chip Select Mask Register */
kadonotakashi 0:8fdf9a60065b 5352 #define FB_CSMR_V_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 5353 #define FB_CSMR_V_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5354 #define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
kadonotakashi 0:8fdf9a60065b 5355 #define FB_CSMR_WP_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 5356 #define FB_CSMR_WP_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5357 #define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
kadonotakashi 0:8fdf9a60065b 5358 #define FB_CSMR_BAM_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 5359 #define FB_CSMR_BAM_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5360 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
kadonotakashi 0:8fdf9a60065b 5361
kadonotakashi 0:8fdf9a60065b 5362 /* The count of FB_CSMR */
kadonotakashi 0:8fdf9a60065b 5363 #define FB_CSMR_COUNT (6U)
kadonotakashi 0:8fdf9a60065b 5364
kadonotakashi 0:8fdf9a60065b 5365 /*! @name CSCR - Chip Select Control Register */
kadonotakashi 0:8fdf9a60065b 5366 #define FB_CSCR_BSTW_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 5367 #define FB_CSCR_BSTW_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 5368 #define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
kadonotakashi 0:8fdf9a60065b 5369 #define FB_CSCR_BSTR_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 5370 #define FB_CSCR_BSTR_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 5371 #define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
kadonotakashi 0:8fdf9a60065b 5372 #define FB_CSCR_BEM_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 5373 #define FB_CSCR_BEM_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 5374 #define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
kadonotakashi 0:8fdf9a60065b 5375 #define FB_CSCR_PS_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 5376 #define FB_CSCR_PS_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 5377 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
kadonotakashi 0:8fdf9a60065b 5378 #define FB_CSCR_AA_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 5379 #define FB_CSCR_AA_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5380 #define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
kadonotakashi 0:8fdf9a60065b 5381 #define FB_CSCR_BLS_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 5382 #define FB_CSCR_BLS_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 5383 #define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
kadonotakashi 0:8fdf9a60065b 5384 #define FB_CSCR_WS_MASK (0xFC00U)
kadonotakashi 0:8fdf9a60065b 5385 #define FB_CSCR_WS_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 5386 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
kadonotakashi 0:8fdf9a60065b 5387 #define FB_CSCR_WRAH_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 5388 #define FB_CSCR_WRAH_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5389 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
kadonotakashi 0:8fdf9a60065b 5390 #define FB_CSCR_RDAH_MASK (0xC0000U)
kadonotakashi 0:8fdf9a60065b 5391 #define FB_CSCR_RDAH_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 5392 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
kadonotakashi 0:8fdf9a60065b 5393 #define FB_CSCR_ASET_MASK (0x300000U)
kadonotakashi 0:8fdf9a60065b 5394 #define FB_CSCR_ASET_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 5395 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
kadonotakashi 0:8fdf9a60065b 5396 #define FB_CSCR_EXTS_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 5397 #define FB_CSCR_EXTS_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 5398 #define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
kadonotakashi 0:8fdf9a60065b 5399 #define FB_CSCR_SWSEN_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 5400 #define FB_CSCR_SWSEN_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 5401 #define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
kadonotakashi 0:8fdf9a60065b 5402 #define FB_CSCR_SWS_MASK (0xFC000000U)
kadonotakashi 0:8fdf9a60065b 5403 #define FB_CSCR_SWS_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 5404 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
kadonotakashi 0:8fdf9a60065b 5405
kadonotakashi 0:8fdf9a60065b 5406 /* The count of FB_CSCR */
kadonotakashi 0:8fdf9a60065b 5407 #define FB_CSCR_COUNT (6U)
kadonotakashi 0:8fdf9a60065b 5408
kadonotakashi 0:8fdf9a60065b 5409 /*! @name CSPMCR - Chip Select port Multiplexing Control Register */
kadonotakashi 0:8fdf9a60065b 5410 #define FB_CSPMCR_GROUP5_MASK (0xF000U)
kadonotakashi 0:8fdf9a60065b 5411 #define FB_CSPMCR_GROUP5_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 5412 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
kadonotakashi 0:8fdf9a60065b 5413 #define FB_CSPMCR_GROUP4_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 5414 #define FB_CSPMCR_GROUP4_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5415 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
kadonotakashi 0:8fdf9a60065b 5416 #define FB_CSPMCR_GROUP3_MASK (0xF00000U)
kadonotakashi 0:8fdf9a60065b 5417 #define FB_CSPMCR_GROUP3_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 5418 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
kadonotakashi 0:8fdf9a60065b 5419 #define FB_CSPMCR_GROUP2_MASK (0xF000000U)
kadonotakashi 0:8fdf9a60065b 5420 #define FB_CSPMCR_GROUP2_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 5421 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
kadonotakashi 0:8fdf9a60065b 5422 #define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 5423 #define FB_CSPMCR_GROUP1_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 5424 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
kadonotakashi 0:8fdf9a60065b 5425
kadonotakashi 0:8fdf9a60065b 5426
kadonotakashi 0:8fdf9a60065b 5427 /*!
kadonotakashi 0:8fdf9a60065b 5428 * @}
kadonotakashi 0:8fdf9a60065b 5429 */ /* end of group FB_Register_Masks */
kadonotakashi 0:8fdf9a60065b 5430
kadonotakashi 0:8fdf9a60065b 5431
kadonotakashi 0:8fdf9a60065b 5432 /* FB - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 5433 /** Peripheral FB base address */
kadonotakashi 0:8fdf9a60065b 5434 #define FB_BASE (0x4000C000u)
kadonotakashi 0:8fdf9a60065b 5435 /** Peripheral FB base pointer */
kadonotakashi 0:8fdf9a60065b 5436 #define FB ((FB_Type *)FB_BASE)
kadonotakashi 0:8fdf9a60065b 5437 /** Array initializer of FB peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 5438 #define FB_BASE_ADDRS { FB_BASE }
kadonotakashi 0:8fdf9a60065b 5439 /** Array initializer of FB peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 5440 #define FB_BASE_PTRS { FB }
kadonotakashi 0:8fdf9a60065b 5441
kadonotakashi 0:8fdf9a60065b 5442 /*!
kadonotakashi 0:8fdf9a60065b 5443 * @}
kadonotakashi 0:8fdf9a60065b 5444 */ /* end of group FB_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 5445
kadonotakashi 0:8fdf9a60065b 5446
kadonotakashi 0:8fdf9a60065b 5447 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 5448 -- FLEXIO Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 5449 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 5450
kadonotakashi 0:8fdf9a60065b 5451 /*!
kadonotakashi 0:8fdf9a60065b 5452 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 5453 * @{
kadonotakashi 0:8fdf9a60065b 5454 */
kadonotakashi 0:8fdf9a60065b 5455
kadonotakashi 0:8fdf9a60065b 5456 /** FLEXIO - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 5457 typedef struct {
kadonotakashi 0:8fdf9a60065b 5458 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 5459 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 5460 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 5461 __I uint32_t PIN; /**< Pin State Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 5462 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 5463 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 5464 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 5465 uint8_t RESERVED_0[4];
kadonotakashi 0:8fdf9a60065b 5466 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 5467 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 5468 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
kadonotakashi 0:8fdf9a60065b 5469 uint8_t RESERVED_1[4];
kadonotakashi 0:8fdf9a60065b 5470 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
kadonotakashi 0:8fdf9a60065b 5471 uint8_t RESERVED_2[12];
kadonotakashi 0:8fdf9a60065b 5472 __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */
kadonotakashi 0:8fdf9a60065b 5473 uint8_t RESERVED_3[60];
kadonotakashi 0:8fdf9a60065b 5474 __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5475 uint8_t RESERVED_4[96];
kadonotakashi 0:8fdf9a60065b 5476 __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5477 uint8_t RESERVED_5[224];
kadonotakashi 0:8fdf9a60065b 5478 __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5479 uint8_t RESERVED_6[96];
kadonotakashi 0:8fdf9a60065b 5480 __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5481 uint8_t RESERVED_7[96];
kadonotakashi 0:8fdf9a60065b 5482 __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5483 uint8_t RESERVED_8[96];
kadonotakashi 0:8fdf9a60065b 5484 __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5485 uint8_t RESERVED_9[96];
kadonotakashi 0:8fdf9a60065b 5486 __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5487 uint8_t RESERVED_10[96];
kadonotakashi 0:8fdf9a60065b 5488 __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5489 uint8_t RESERVED_11[96];
kadonotakashi 0:8fdf9a60065b 5490 __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5491 uint8_t RESERVED_12[352];
kadonotakashi 0:8fdf9a60065b 5492 __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5493 uint8_t RESERVED_13[96];
kadonotakashi 0:8fdf9a60065b 5494 __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5495 uint8_t RESERVED_14[96];
kadonotakashi 0:8fdf9a60065b 5496 __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5497 } FLEXIO_Type;
kadonotakashi 0:8fdf9a60065b 5498
kadonotakashi 0:8fdf9a60065b 5499 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 5500 -- FLEXIO Register Masks
kadonotakashi 0:8fdf9a60065b 5501 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 5502
kadonotakashi 0:8fdf9a60065b 5503 /*!
kadonotakashi 0:8fdf9a60065b 5504 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
kadonotakashi 0:8fdf9a60065b 5505 * @{
kadonotakashi 0:8fdf9a60065b 5506 */
kadonotakashi 0:8fdf9a60065b 5507
kadonotakashi 0:8fdf9a60065b 5508 /*! @name VERID - Version ID Register */
kadonotakashi 0:8fdf9a60065b 5509 #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 5510 #define FLEXIO_VERID_FEATURE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5511 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
kadonotakashi 0:8fdf9a60065b 5512 #define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 5513 #define FLEXIO_VERID_MINOR_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5514 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
kadonotakashi 0:8fdf9a60065b 5515 #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
kadonotakashi 0:8fdf9a60065b 5516 #define FLEXIO_VERID_MAJOR_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 5517 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
kadonotakashi 0:8fdf9a60065b 5518
kadonotakashi 0:8fdf9a60065b 5519 /*! @name PARAM - Parameter Register */
kadonotakashi 0:8fdf9a60065b 5520 #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5521 #define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5522 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
kadonotakashi 0:8fdf9a60065b 5523 #define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 5524 #define FLEXIO_PARAM_TIMER_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5525 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
kadonotakashi 0:8fdf9a60065b 5526 #define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 5527 #define FLEXIO_PARAM_PIN_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5528 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
kadonotakashi 0:8fdf9a60065b 5529 #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
kadonotakashi 0:8fdf9a60065b 5530 #define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 5531 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
kadonotakashi 0:8fdf9a60065b 5532
kadonotakashi 0:8fdf9a60065b 5533 /*! @name CTRL - FlexIO Control Register */
kadonotakashi 0:8fdf9a60065b 5534 #define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 5535 #define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5536 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
kadonotakashi 0:8fdf9a60065b 5537 #define FLEXIO_CTRL_SWRST_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 5538 #define FLEXIO_CTRL_SWRST_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 5539 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
kadonotakashi 0:8fdf9a60065b 5540 #define FLEXIO_CTRL_FASTACC_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 5541 #define FLEXIO_CTRL_FASTACC_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 5542 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
kadonotakashi 0:8fdf9a60065b 5543 #define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 5544 #define FLEXIO_CTRL_DBGE_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 5545 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
kadonotakashi 0:8fdf9a60065b 5546 #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 5547 #define FLEXIO_CTRL_DOZEN_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 5548 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
kadonotakashi 0:8fdf9a60065b 5549
kadonotakashi 0:8fdf9a60065b 5550 /*! @name PIN - Pin State Register */
kadonotakashi 0:8fdf9a60065b 5551 #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5552 #define FLEXIO_PIN_PDI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5553 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
kadonotakashi 0:8fdf9a60065b 5554
kadonotakashi 0:8fdf9a60065b 5555 /*! @name SHIFTSTAT - Shifter Status Register */
kadonotakashi 0:8fdf9a60065b 5556 #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5557 #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5558 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
kadonotakashi 0:8fdf9a60065b 5559
kadonotakashi 0:8fdf9a60065b 5560 /*! @name SHIFTERR - Shifter Error Register */
kadonotakashi 0:8fdf9a60065b 5561 #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5562 #define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5563 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
kadonotakashi 0:8fdf9a60065b 5564
kadonotakashi 0:8fdf9a60065b 5565 /*! @name TIMSTAT - Timer Status Register */
kadonotakashi 0:8fdf9a60065b 5566 #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5567 #define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5568 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
kadonotakashi 0:8fdf9a60065b 5569
kadonotakashi 0:8fdf9a60065b 5570 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
kadonotakashi 0:8fdf9a60065b 5571 #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5572 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5573 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
kadonotakashi 0:8fdf9a60065b 5574
kadonotakashi 0:8fdf9a60065b 5575 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
kadonotakashi 0:8fdf9a60065b 5576 #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5577 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5578 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
kadonotakashi 0:8fdf9a60065b 5579
kadonotakashi 0:8fdf9a60065b 5580 /*! @name TIMIEN - Timer Interrupt Enable Register */
kadonotakashi 0:8fdf9a60065b 5581 #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5582 #define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5583 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
kadonotakashi 0:8fdf9a60065b 5584
kadonotakashi 0:8fdf9a60065b 5585 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
kadonotakashi 0:8fdf9a60065b 5586 #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 5587 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5588 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
kadonotakashi 0:8fdf9a60065b 5589
kadonotakashi 0:8fdf9a60065b 5590 /*! @name SHIFTSTATE - Shifter State Register */
kadonotakashi 0:8fdf9a60065b 5591 #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 5592 #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5593 #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
kadonotakashi 0:8fdf9a60065b 5594
kadonotakashi 0:8fdf9a60065b 5595 /*! @name SHIFTCTL - Shifter Control N Register */
kadonotakashi 0:8fdf9a60065b 5596 #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 5597 #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5598 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
kadonotakashi 0:8fdf9a60065b 5599 #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 5600 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 5601 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
kadonotakashi 0:8fdf9a60065b 5602 #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
kadonotakashi 0:8fdf9a60065b 5603 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5604 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
kadonotakashi 0:8fdf9a60065b 5605 #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 5606 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5607 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
kadonotakashi 0:8fdf9a60065b 5608 #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 5609 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 5610 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
kadonotakashi 0:8fdf9a60065b 5611 #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U)
kadonotakashi 0:8fdf9a60065b 5612 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 5613 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
kadonotakashi 0:8fdf9a60065b 5614
kadonotakashi 0:8fdf9a60065b 5615 /* The count of FLEXIO_SHIFTCTL */
kadonotakashi 0:8fdf9a60065b 5616 #define FLEXIO_SHIFTCTL_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5617
kadonotakashi 0:8fdf9a60065b 5618 /*! @name SHIFTCFG - Shifter Configuration N Register */
kadonotakashi 0:8fdf9a60065b 5619 #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 5620 #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5621 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
kadonotakashi 0:8fdf9a60065b 5622 #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 5623 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 5624 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
kadonotakashi 0:8fdf9a60065b 5625 #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 5626 #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5627 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
kadonotakashi 0:8fdf9a60065b 5628 #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
kadonotakashi 0:8fdf9a60065b 5629 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5630 #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
kadonotakashi 0:8fdf9a60065b 5631
kadonotakashi 0:8fdf9a60065b 5632 /* The count of FLEXIO_SHIFTCFG */
kadonotakashi 0:8fdf9a60065b 5633 #define FLEXIO_SHIFTCFG_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5634
kadonotakashi 0:8fdf9a60065b 5635 /*! @name SHIFTBUF - Shifter Buffer N Register */
kadonotakashi 0:8fdf9a60065b 5636 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5637 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5638 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
kadonotakashi 0:8fdf9a60065b 5639
kadonotakashi 0:8fdf9a60065b 5640 /* The count of FLEXIO_SHIFTBUF */
kadonotakashi 0:8fdf9a60065b 5641 #define FLEXIO_SHIFTBUF_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5642
kadonotakashi 0:8fdf9a60065b 5643 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
kadonotakashi 0:8fdf9a60065b 5644 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5645 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5646 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
kadonotakashi 0:8fdf9a60065b 5647
kadonotakashi 0:8fdf9a60065b 5648 /* The count of FLEXIO_SHIFTBUFBIS */
kadonotakashi 0:8fdf9a60065b 5649 #define FLEXIO_SHIFTBUFBIS_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5650
kadonotakashi 0:8fdf9a60065b 5651 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
kadonotakashi 0:8fdf9a60065b 5652 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5653 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5654 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
kadonotakashi 0:8fdf9a60065b 5655
kadonotakashi 0:8fdf9a60065b 5656 /* The count of FLEXIO_SHIFTBUFBYS */
kadonotakashi 0:8fdf9a60065b 5657 #define FLEXIO_SHIFTBUFBYS_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5658
kadonotakashi 0:8fdf9a60065b 5659 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
kadonotakashi 0:8fdf9a60065b 5660 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5661 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5662 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
kadonotakashi 0:8fdf9a60065b 5663
kadonotakashi 0:8fdf9a60065b 5664 /* The count of FLEXIO_SHIFTBUFBBS */
kadonotakashi 0:8fdf9a60065b 5665 #define FLEXIO_SHIFTBUFBBS_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5666
kadonotakashi 0:8fdf9a60065b 5667 /*! @name TIMCTL - Timer Control N Register */
kadonotakashi 0:8fdf9a60065b 5668 #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 5669 #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5670 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
kadonotakashi 0:8fdf9a60065b 5671 #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 5672 #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 5673 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
kadonotakashi 0:8fdf9a60065b 5674 #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
kadonotakashi 0:8fdf9a60065b 5675 #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5676 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
kadonotakashi 0:8fdf9a60065b 5677 #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 5678 #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5679 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
kadonotakashi 0:8fdf9a60065b 5680 #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 5681 #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 5682 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
kadonotakashi 0:8fdf9a60065b 5683 #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 5684 #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 5685 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
kadonotakashi 0:8fdf9a60065b 5686 #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
kadonotakashi 0:8fdf9a60065b 5687 #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 5688 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
kadonotakashi 0:8fdf9a60065b 5689
kadonotakashi 0:8fdf9a60065b 5690 /* The count of FLEXIO_TIMCTL */
kadonotakashi 0:8fdf9a60065b 5691 #define FLEXIO_TIMCTL_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5692
kadonotakashi 0:8fdf9a60065b 5693 /*! @name TIMCFG - Timer Configuration N Register */
kadonotakashi 0:8fdf9a60065b 5694 #define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 5695 #define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 5696 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
kadonotakashi 0:8fdf9a60065b 5697 #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 5698 #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 5699 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
kadonotakashi 0:8fdf9a60065b 5700 #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
kadonotakashi 0:8fdf9a60065b 5701 #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5702 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
kadonotakashi 0:8fdf9a60065b 5703 #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
kadonotakashi 0:8fdf9a60065b 5704 #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 5705 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
kadonotakashi 0:8fdf9a60065b 5706 #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
kadonotakashi 0:8fdf9a60065b 5707 #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5708 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
kadonotakashi 0:8fdf9a60065b 5709 #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
kadonotakashi 0:8fdf9a60065b 5710 #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 5711 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
kadonotakashi 0:8fdf9a60065b 5712 #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 5713 #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 5714 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
kadonotakashi 0:8fdf9a60065b 5715
kadonotakashi 0:8fdf9a60065b 5716 /* The count of FLEXIO_TIMCFG */
kadonotakashi 0:8fdf9a60065b 5717 #define FLEXIO_TIMCFG_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5718
kadonotakashi 0:8fdf9a60065b 5719 /*! @name TIMCMP - Timer Compare N Register */
kadonotakashi 0:8fdf9a60065b 5720 #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 5721 #define FLEXIO_TIMCMP_CMP_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5722 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
kadonotakashi 0:8fdf9a60065b 5723
kadonotakashi 0:8fdf9a60065b 5724 /* The count of FLEXIO_TIMCMP */
kadonotakashi 0:8fdf9a60065b 5725 #define FLEXIO_TIMCMP_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5726
kadonotakashi 0:8fdf9a60065b 5727 /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
kadonotakashi 0:8fdf9a60065b 5728 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5729 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5730 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
kadonotakashi 0:8fdf9a60065b 5731
kadonotakashi 0:8fdf9a60065b 5732 /* The count of FLEXIO_SHIFTBUFNBS */
kadonotakashi 0:8fdf9a60065b 5733 #define FLEXIO_SHIFTBUFNBS_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5734
kadonotakashi 0:8fdf9a60065b 5735 /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
kadonotakashi 0:8fdf9a60065b 5736 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5737 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5738 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
kadonotakashi 0:8fdf9a60065b 5739
kadonotakashi 0:8fdf9a60065b 5740 /* The count of FLEXIO_SHIFTBUFHWS */
kadonotakashi 0:8fdf9a60065b 5741 #define FLEXIO_SHIFTBUFHWS_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5742
kadonotakashi 0:8fdf9a60065b 5743 /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
kadonotakashi 0:8fdf9a60065b 5744 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5745 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5746 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
kadonotakashi 0:8fdf9a60065b 5747
kadonotakashi 0:8fdf9a60065b 5748 /* The count of FLEXIO_SHIFTBUFNIS */
kadonotakashi 0:8fdf9a60065b 5749 #define FLEXIO_SHIFTBUFNIS_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 5750
kadonotakashi 0:8fdf9a60065b 5751
kadonotakashi 0:8fdf9a60065b 5752 /*!
kadonotakashi 0:8fdf9a60065b 5753 * @}
kadonotakashi 0:8fdf9a60065b 5754 */ /* end of group FLEXIO_Register_Masks */
kadonotakashi 0:8fdf9a60065b 5755
kadonotakashi 0:8fdf9a60065b 5756
kadonotakashi 0:8fdf9a60065b 5757 /* FLEXIO - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 5758 /** Peripheral FLEXIO0 base address */
kadonotakashi 0:8fdf9a60065b 5759 #define FLEXIO0_BASE (0x400DF000u)
kadonotakashi 0:8fdf9a60065b 5760 /** Peripheral FLEXIO0 base pointer */
kadonotakashi 0:8fdf9a60065b 5761 #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE)
kadonotakashi 0:8fdf9a60065b 5762 /** Array initializer of FLEXIO peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 5763 #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE }
kadonotakashi 0:8fdf9a60065b 5764 /** Array initializer of FLEXIO peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 5765 #define FLEXIO_BASE_PTRS { FLEXIO0 }
kadonotakashi 0:8fdf9a60065b 5766 /** Interrupt vectors for the FLEXIO peripheral type */
kadonotakashi 0:8fdf9a60065b 5767 #define FLEXIO_IRQS { FLEXIO0_IRQn }
kadonotakashi 0:8fdf9a60065b 5768
kadonotakashi 0:8fdf9a60065b 5769 /*!
kadonotakashi 0:8fdf9a60065b 5770 * @}
kadonotakashi 0:8fdf9a60065b 5771 */ /* end of group FLEXIO_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 5772
kadonotakashi 0:8fdf9a60065b 5773
kadonotakashi 0:8fdf9a60065b 5774 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 5775 -- FMC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 5776 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 5777
kadonotakashi 0:8fdf9a60065b 5778 /*!
kadonotakashi 0:8fdf9a60065b 5779 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 5780 * @{
kadonotakashi 0:8fdf9a60065b 5781 */
kadonotakashi 0:8fdf9a60065b 5782
kadonotakashi 0:8fdf9a60065b 5783 /** FMC - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 5784 typedef struct {
kadonotakashi 0:8fdf9a60065b 5785 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 5786 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 5787 __I uint32_t RESERVED; /**< Reserved, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 5788 uint8_t RESERVED_0[244];
kadonotakashi 0:8fdf9a60065b 5789 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5790 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5791 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5792 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 5793 uint8_t RESERVED_1[192];
kadonotakashi 0:8fdf9a60065b 5794 struct { /* offset: 0x200, array step: index*0x40, index2*0x10 */
kadonotakashi 0:8fdf9a60065b 5795 __IO uint32_t DATA_UM; /**< Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 */
kadonotakashi 0:8fdf9a60065b 5796 __IO uint32_t DATA_MU; /**< Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 */
kadonotakashi 0:8fdf9a60065b 5797 __IO uint32_t DATA_ML; /**< Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 */
kadonotakashi 0:8fdf9a60065b 5798 __IO uint32_t DATA_LM; /**< Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 */
kadonotakashi 0:8fdf9a60065b 5799 } SET[4][4];
kadonotakashi 0:8fdf9a60065b 5800 } FMC_Type;
kadonotakashi 0:8fdf9a60065b 5801
kadonotakashi 0:8fdf9a60065b 5802 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 5803 -- FMC Register Masks
kadonotakashi 0:8fdf9a60065b 5804 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 5805
kadonotakashi 0:8fdf9a60065b 5806 /*!
kadonotakashi 0:8fdf9a60065b 5807 * @addtogroup FMC_Register_Masks FMC Register Masks
kadonotakashi 0:8fdf9a60065b 5808 * @{
kadonotakashi 0:8fdf9a60065b 5809 */
kadonotakashi 0:8fdf9a60065b 5810
kadonotakashi 0:8fdf9a60065b 5811 /*! @name PFAPR - Flash Access Protection Register */
kadonotakashi 0:8fdf9a60065b 5812 #define FMC_PFAPR_M0AP_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 5813 #define FMC_PFAPR_M0AP_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5814 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
kadonotakashi 0:8fdf9a60065b 5815 #define FMC_PFAPR_M1AP_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 5816 #define FMC_PFAPR_M1AP_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 5817 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
kadonotakashi 0:8fdf9a60065b 5818 #define FMC_PFAPR_M2AP_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 5819 #define FMC_PFAPR_M2AP_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 5820 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
kadonotakashi 0:8fdf9a60065b 5821 #define FMC_PFAPR_M3AP_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 5822 #define FMC_PFAPR_M3AP_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 5823 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
kadonotakashi 0:8fdf9a60065b 5824 #define FMC_PFAPR_M4AP_MASK (0x300U)
kadonotakashi 0:8fdf9a60065b 5825 #define FMC_PFAPR_M4AP_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 5826 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
kadonotakashi 0:8fdf9a60065b 5827 #define FMC_PFAPR_M0PFD_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 5828 #define FMC_PFAPR_M0PFD_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 5829 #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
kadonotakashi 0:8fdf9a60065b 5830 #define FMC_PFAPR_M1PFD_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 5831 #define FMC_PFAPR_M1PFD_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 5832 #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
kadonotakashi 0:8fdf9a60065b 5833 #define FMC_PFAPR_M2PFD_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 5834 #define FMC_PFAPR_M2PFD_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 5835 #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
kadonotakashi 0:8fdf9a60065b 5836 #define FMC_PFAPR_M3PFD_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 5837 #define FMC_PFAPR_M3PFD_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 5838 #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
kadonotakashi 0:8fdf9a60065b 5839 #define FMC_PFAPR_M4PFD_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 5840 #define FMC_PFAPR_M4PFD_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 5841 #define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
kadonotakashi 0:8fdf9a60065b 5842
kadonotakashi 0:8fdf9a60065b 5843 /*! @name PFB0CR - Flash Bank 0 Control Register */
kadonotakashi 0:8fdf9a60065b 5844 #define FMC_PFB0CR_B0SEBE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 5845 #define FMC_PFB0CR_B0SEBE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5846 #define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
kadonotakashi 0:8fdf9a60065b 5847 #define FMC_PFB0CR_B0IPE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 5848 #define FMC_PFB0CR_B0IPE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 5849 #define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
kadonotakashi 0:8fdf9a60065b 5850 #define FMC_PFB0CR_B0DPE_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 5851 #define FMC_PFB0CR_B0DPE_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 5852 #define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
kadonotakashi 0:8fdf9a60065b 5853 #define FMC_PFB0CR_B0ICE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 5854 #define FMC_PFB0CR_B0ICE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 5855 #define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
kadonotakashi 0:8fdf9a60065b 5856 #define FMC_PFB0CR_B0DCE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 5857 #define FMC_PFB0CR_B0DCE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 5858 #define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
kadonotakashi 0:8fdf9a60065b 5859 #define FMC_PFB0CR_CRC_MASK (0xE0U)
kadonotakashi 0:8fdf9a60065b 5860 #define FMC_PFB0CR_CRC_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 5861 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
kadonotakashi 0:8fdf9a60065b 5862 #define FMC_PFB0CR_B0MW_MASK (0x60000U)
kadonotakashi 0:8fdf9a60065b 5863 #define FMC_PFB0CR_B0MW_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 5864 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
kadonotakashi 0:8fdf9a60065b 5865 #define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 5866 #define FMC_PFB0CR_S_B_INV_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 5867 #define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
kadonotakashi 0:8fdf9a60065b 5868 #define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
kadonotakashi 0:8fdf9a60065b 5869 #define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 5870 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
kadonotakashi 0:8fdf9a60065b 5871 #define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
kadonotakashi 0:8fdf9a60065b 5872 #define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 5873 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
kadonotakashi 0:8fdf9a60065b 5874 #define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 5875 #define FMC_PFB0CR_B0RWSC_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 5876 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
kadonotakashi 0:8fdf9a60065b 5877
kadonotakashi 0:8fdf9a60065b 5878 /*! @name TAGVDW0S - Cache Tag Storage */
kadonotakashi 0:8fdf9a60065b 5879 #define FMC_TAGVDW0S_valid_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 5880 #define FMC_TAGVDW0S_valid_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5881 #define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
kadonotakashi 0:8fdf9a60065b 5882 #define FMC_TAGVDW0S_cache_tag_MASK (0xFFFC0U)
kadonotakashi 0:8fdf9a60065b 5883 #define FMC_TAGVDW0S_cache_tag_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 5884 #define FMC_TAGVDW0S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_cache_tag_SHIFT)) & FMC_TAGVDW0S_cache_tag_MASK)
kadonotakashi 0:8fdf9a60065b 5885
kadonotakashi 0:8fdf9a60065b 5886 /* The count of FMC_TAGVDW0S */
kadonotakashi 0:8fdf9a60065b 5887 #define FMC_TAGVDW0S_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 5888
kadonotakashi 0:8fdf9a60065b 5889 /*! @name TAGVDW1S - Cache Tag Storage */
kadonotakashi 0:8fdf9a60065b 5890 #define FMC_TAGVDW1S_valid_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 5891 #define FMC_TAGVDW1S_valid_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5892 #define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
kadonotakashi 0:8fdf9a60065b 5893 #define FMC_TAGVDW1S_cache_tag_MASK (0xFFFC0U)
kadonotakashi 0:8fdf9a60065b 5894 #define FMC_TAGVDW1S_cache_tag_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 5895 #define FMC_TAGVDW1S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_cache_tag_SHIFT)) & FMC_TAGVDW1S_cache_tag_MASK)
kadonotakashi 0:8fdf9a60065b 5896
kadonotakashi 0:8fdf9a60065b 5897 /* The count of FMC_TAGVDW1S */
kadonotakashi 0:8fdf9a60065b 5898 #define FMC_TAGVDW1S_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 5899
kadonotakashi 0:8fdf9a60065b 5900 /*! @name TAGVDW2S - Cache Tag Storage */
kadonotakashi 0:8fdf9a60065b 5901 #define FMC_TAGVDW2S_valid_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 5902 #define FMC_TAGVDW2S_valid_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5903 #define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
kadonotakashi 0:8fdf9a60065b 5904 #define FMC_TAGVDW2S_cache_tag_MASK (0xFFFC0U)
kadonotakashi 0:8fdf9a60065b 5905 #define FMC_TAGVDW2S_cache_tag_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 5906 #define FMC_TAGVDW2S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_cache_tag_SHIFT)) & FMC_TAGVDW2S_cache_tag_MASK)
kadonotakashi 0:8fdf9a60065b 5907
kadonotakashi 0:8fdf9a60065b 5908 /* The count of FMC_TAGVDW2S */
kadonotakashi 0:8fdf9a60065b 5909 #define FMC_TAGVDW2S_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 5910
kadonotakashi 0:8fdf9a60065b 5911 /*! @name TAGVDW3S - Cache Tag Storage */
kadonotakashi 0:8fdf9a60065b 5912 #define FMC_TAGVDW3S_valid_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 5913 #define FMC_TAGVDW3S_valid_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5914 #define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
kadonotakashi 0:8fdf9a60065b 5915 #define FMC_TAGVDW3S_cache_tag_MASK (0xFFFC0U)
kadonotakashi 0:8fdf9a60065b 5916 #define FMC_TAGVDW3S_cache_tag_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 5917 #define FMC_TAGVDW3S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_cache_tag_SHIFT)) & FMC_TAGVDW3S_cache_tag_MASK)
kadonotakashi 0:8fdf9a60065b 5918
kadonotakashi 0:8fdf9a60065b 5919 /* The count of FMC_TAGVDW3S */
kadonotakashi 0:8fdf9a60065b 5920 #define FMC_TAGVDW3S_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 5921
kadonotakashi 0:8fdf9a60065b 5922 /*! @name DATA_UM - Cache Data Storage (uppermost word) */
kadonotakashi 0:8fdf9a60065b 5923 #define FMC_DATA_UM_data_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5924 #define FMC_DATA_UM_data_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5925 #define FMC_DATA_UM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
kadonotakashi 0:8fdf9a60065b 5926
kadonotakashi 0:8fdf9a60065b 5927 /* The count of FMC_DATA_UM */
kadonotakashi 0:8fdf9a60065b 5928 #define FMC_DATA_UM_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 5929
kadonotakashi 0:8fdf9a60065b 5930 /* The count of FMC_DATA_UM */
kadonotakashi 0:8fdf9a60065b 5931 #define FMC_DATA_UM_COUNT2 (4U)
kadonotakashi 0:8fdf9a60065b 5932
kadonotakashi 0:8fdf9a60065b 5933 /*! @name DATA_MU - Cache Data Storage (mid-upper word) */
kadonotakashi 0:8fdf9a60065b 5934 #define FMC_DATA_MU_data_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5935 #define FMC_DATA_MU_data_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5936 #define FMC_DATA_MU_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
kadonotakashi 0:8fdf9a60065b 5937
kadonotakashi 0:8fdf9a60065b 5938 /* The count of FMC_DATA_MU */
kadonotakashi 0:8fdf9a60065b 5939 #define FMC_DATA_MU_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 5940
kadonotakashi 0:8fdf9a60065b 5941 /* The count of FMC_DATA_MU */
kadonotakashi 0:8fdf9a60065b 5942 #define FMC_DATA_MU_COUNT2 (4U)
kadonotakashi 0:8fdf9a60065b 5943
kadonotakashi 0:8fdf9a60065b 5944 /*! @name DATA_ML - Cache Data Storage (mid-lower word) */
kadonotakashi 0:8fdf9a60065b 5945 #define FMC_DATA_ML_data_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5946 #define FMC_DATA_ML_data_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5947 #define FMC_DATA_ML_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
kadonotakashi 0:8fdf9a60065b 5948
kadonotakashi 0:8fdf9a60065b 5949 /* The count of FMC_DATA_ML */
kadonotakashi 0:8fdf9a60065b 5950 #define FMC_DATA_ML_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 5951
kadonotakashi 0:8fdf9a60065b 5952 /* The count of FMC_DATA_ML */
kadonotakashi 0:8fdf9a60065b 5953 #define FMC_DATA_ML_COUNT2 (4U)
kadonotakashi 0:8fdf9a60065b 5954
kadonotakashi 0:8fdf9a60065b 5955 /*! @name DATA_LM - Cache Data Storage (lowermost word) */
kadonotakashi 0:8fdf9a60065b 5956 #define FMC_DATA_LM_data_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 5957 #define FMC_DATA_LM_data_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 5958 #define FMC_DATA_LM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
kadonotakashi 0:8fdf9a60065b 5959
kadonotakashi 0:8fdf9a60065b 5960 /* The count of FMC_DATA_LM */
kadonotakashi 0:8fdf9a60065b 5961 #define FMC_DATA_LM_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 5962
kadonotakashi 0:8fdf9a60065b 5963 /* The count of FMC_DATA_LM */
kadonotakashi 0:8fdf9a60065b 5964 #define FMC_DATA_LM_COUNT2 (4U)
kadonotakashi 0:8fdf9a60065b 5965
kadonotakashi 0:8fdf9a60065b 5966
kadonotakashi 0:8fdf9a60065b 5967 /*!
kadonotakashi 0:8fdf9a60065b 5968 * @}
kadonotakashi 0:8fdf9a60065b 5969 */ /* end of group FMC_Register_Masks */
kadonotakashi 0:8fdf9a60065b 5970
kadonotakashi 0:8fdf9a60065b 5971
kadonotakashi 0:8fdf9a60065b 5972 /* FMC - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 5973 /** Peripheral FMC base address */
kadonotakashi 0:8fdf9a60065b 5974 #define FMC_BASE (0x4001F000u)
kadonotakashi 0:8fdf9a60065b 5975 /** Peripheral FMC base pointer */
kadonotakashi 0:8fdf9a60065b 5976 #define FMC ((FMC_Type *)FMC_BASE)
kadonotakashi 0:8fdf9a60065b 5977 /** Array initializer of FMC peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 5978 #define FMC_BASE_ADDRS { FMC_BASE }
kadonotakashi 0:8fdf9a60065b 5979 /** Array initializer of FMC peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 5980 #define FMC_BASE_PTRS { FMC }
kadonotakashi 0:8fdf9a60065b 5981
kadonotakashi 0:8fdf9a60065b 5982 /*!
kadonotakashi 0:8fdf9a60065b 5983 * @}
kadonotakashi 0:8fdf9a60065b 5984 */ /* end of group FMC_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 5985
kadonotakashi 0:8fdf9a60065b 5986
kadonotakashi 0:8fdf9a60065b 5987 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 5988 -- FTFA Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 5989 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 5990
kadonotakashi 0:8fdf9a60065b 5991 /*!
kadonotakashi 0:8fdf9a60065b 5992 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 5993 * @{
kadonotakashi 0:8fdf9a60065b 5994 */
kadonotakashi 0:8fdf9a60065b 5995
kadonotakashi 0:8fdf9a60065b 5996 /** FTFA - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 5997 typedef struct {
kadonotakashi 0:8fdf9a60065b 5998 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 5999 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 6000 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 6001 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
kadonotakashi 0:8fdf9a60065b 6002 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 6003 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
kadonotakashi 0:8fdf9a60065b 6004 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
kadonotakashi 0:8fdf9a60065b 6005 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
kadonotakashi 0:8fdf9a60065b 6006 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 6007 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
kadonotakashi 0:8fdf9a60065b 6008 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
kadonotakashi 0:8fdf9a60065b 6009 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
kadonotakashi 0:8fdf9a60065b 6010 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 6011 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
kadonotakashi 0:8fdf9a60065b 6012 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
kadonotakashi 0:8fdf9a60065b 6013 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
kadonotakashi 0:8fdf9a60065b 6014 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 6015 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
kadonotakashi 0:8fdf9a60065b 6016 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
kadonotakashi 0:8fdf9a60065b 6017 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
kadonotakashi 0:8fdf9a60065b 6018 uint8_t RESERVED_0[4];
kadonotakashi 0:8fdf9a60065b 6019 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 6020 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
kadonotakashi 0:8fdf9a60065b 6021 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
kadonotakashi 0:8fdf9a60065b 6022 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
kadonotakashi 0:8fdf9a60065b 6023 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
kadonotakashi 0:8fdf9a60065b 6024 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
kadonotakashi 0:8fdf9a60065b 6025 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
kadonotakashi 0:8fdf9a60065b 6026 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
kadonotakashi 0:8fdf9a60065b 6027 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 6028 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
kadonotakashi 0:8fdf9a60065b 6029 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
kadonotakashi 0:8fdf9a60065b 6030 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
kadonotakashi 0:8fdf9a60065b 6031 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 6032 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
kadonotakashi 0:8fdf9a60065b 6033 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
kadonotakashi 0:8fdf9a60065b 6034 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
kadonotakashi 0:8fdf9a60065b 6035 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
kadonotakashi 0:8fdf9a60065b 6036 uint8_t RESERVED_1[2];
kadonotakashi 0:8fdf9a60065b 6037 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
kadonotakashi 0:8fdf9a60065b 6038 } FTFA_Type;
kadonotakashi 0:8fdf9a60065b 6039
kadonotakashi 0:8fdf9a60065b 6040 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 6041 -- FTFA Register Masks
kadonotakashi 0:8fdf9a60065b 6042 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 6043
kadonotakashi 0:8fdf9a60065b 6044 /*!
kadonotakashi 0:8fdf9a60065b 6045 * @addtogroup FTFA_Register_Masks FTFA Register Masks
kadonotakashi 0:8fdf9a60065b 6046 * @{
kadonotakashi 0:8fdf9a60065b 6047 */
kadonotakashi 0:8fdf9a60065b 6048
kadonotakashi 0:8fdf9a60065b 6049 /*! @name FSTAT - Flash Status Register */
kadonotakashi 0:8fdf9a60065b 6050 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6051 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6052 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
kadonotakashi 0:8fdf9a60065b 6053 #define FTFA_FSTAT_FPVIOL_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6054 #define FTFA_FSTAT_FPVIOL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6055 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
kadonotakashi 0:8fdf9a60065b 6056 #define FTFA_FSTAT_ACCERR_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6057 #define FTFA_FSTAT_ACCERR_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6058 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
kadonotakashi 0:8fdf9a60065b 6059 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6060 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6061 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
kadonotakashi 0:8fdf9a60065b 6062 #define FTFA_FSTAT_CCIF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6063 #define FTFA_FSTAT_CCIF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6064 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
kadonotakashi 0:8fdf9a60065b 6065
kadonotakashi 0:8fdf9a60065b 6066 /*! @name FCNFG - Flash Configuration Register */
kadonotakashi 0:8fdf9a60065b 6067 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6068 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6069 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
kadonotakashi 0:8fdf9a60065b 6070 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6071 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6072 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
kadonotakashi 0:8fdf9a60065b 6073 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6074 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6075 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
kadonotakashi 0:8fdf9a60065b 6076 #define FTFA_FCNFG_CCIE_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6077 #define FTFA_FCNFG_CCIE_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6078 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
kadonotakashi 0:8fdf9a60065b 6079
kadonotakashi 0:8fdf9a60065b 6080 /*! @name FSEC - Flash Security Register */
kadonotakashi 0:8fdf9a60065b 6081 #define FTFA_FSEC_SEC_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 6082 #define FTFA_FSEC_SEC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6083 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
kadonotakashi 0:8fdf9a60065b 6084 #define FTFA_FSEC_FSLACC_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 6085 #define FTFA_FSEC_FSLACC_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6086 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
kadonotakashi 0:8fdf9a60065b 6087 #define FTFA_FSEC_MEEN_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 6088 #define FTFA_FSEC_MEEN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6089 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
kadonotakashi 0:8fdf9a60065b 6090 #define FTFA_FSEC_KEYEN_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 6091 #define FTFA_FSEC_KEYEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6092 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
kadonotakashi 0:8fdf9a60065b 6093
kadonotakashi 0:8fdf9a60065b 6094 /*! @name FOPT - Flash Option Register */
kadonotakashi 0:8fdf9a60065b 6095 #define FTFA_FOPT_OPT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6096 #define FTFA_FOPT_OPT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6097 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
kadonotakashi 0:8fdf9a60065b 6098
kadonotakashi 0:8fdf9a60065b 6099 /*! @name FCCOB3 - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6100 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6101 #define FTFA_FCCOB3_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6102 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6103
kadonotakashi 0:8fdf9a60065b 6104 /*! @name FCCOB2 - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6105 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6106 #define FTFA_FCCOB2_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6107 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6108
kadonotakashi 0:8fdf9a60065b 6109 /*! @name FCCOB1 - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6110 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6111 #define FTFA_FCCOB1_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6112 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6113
kadonotakashi 0:8fdf9a60065b 6114 /*! @name FCCOB0 - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6115 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6116 #define FTFA_FCCOB0_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6117 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6118
kadonotakashi 0:8fdf9a60065b 6119 /*! @name FCCOB7 - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6120 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6121 #define FTFA_FCCOB7_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6122 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6123
kadonotakashi 0:8fdf9a60065b 6124 /*! @name FCCOB6 - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6125 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6126 #define FTFA_FCCOB6_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6127 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6128
kadonotakashi 0:8fdf9a60065b 6129 /*! @name FCCOB5 - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6130 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6131 #define FTFA_FCCOB5_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6132 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6133
kadonotakashi 0:8fdf9a60065b 6134 /*! @name FCCOB4 - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6135 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6136 #define FTFA_FCCOB4_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6137 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6138
kadonotakashi 0:8fdf9a60065b 6139 /*! @name FCCOBB - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6140 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6141 #define FTFA_FCCOBB_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6142 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6143
kadonotakashi 0:8fdf9a60065b 6144 /*! @name FCCOBA - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6145 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6146 #define FTFA_FCCOBA_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6147 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6148
kadonotakashi 0:8fdf9a60065b 6149 /*! @name FCCOB9 - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6150 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6151 #define FTFA_FCCOB9_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6152 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6153
kadonotakashi 0:8fdf9a60065b 6154 /*! @name FCCOB8 - Flash Common Command Object Registers */
kadonotakashi 0:8fdf9a60065b 6155 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6156 #define FTFA_FCCOB8_CCOBn_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6157 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
kadonotakashi 0:8fdf9a60065b 6158
kadonotakashi 0:8fdf9a60065b 6159 /*! @name FPROT3 - Program Flash Protection Registers */
kadonotakashi 0:8fdf9a60065b 6160 #define FTFA_FPROT3_PROT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6161 #define FTFA_FPROT3_PROT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6162 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
kadonotakashi 0:8fdf9a60065b 6163
kadonotakashi 0:8fdf9a60065b 6164 /*! @name FPROT2 - Program Flash Protection Registers */
kadonotakashi 0:8fdf9a60065b 6165 #define FTFA_FPROT2_PROT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6166 #define FTFA_FPROT2_PROT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6167 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
kadonotakashi 0:8fdf9a60065b 6168
kadonotakashi 0:8fdf9a60065b 6169 /*! @name FPROT1 - Program Flash Protection Registers */
kadonotakashi 0:8fdf9a60065b 6170 #define FTFA_FPROT1_PROT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6171 #define FTFA_FPROT1_PROT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6172 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
kadonotakashi 0:8fdf9a60065b 6173
kadonotakashi 0:8fdf9a60065b 6174 /*! @name FPROT0 - Program Flash Protection Registers */
kadonotakashi 0:8fdf9a60065b 6175 #define FTFA_FPROT0_PROT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6176 #define FTFA_FPROT0_PROT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6177 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
kadonotakashi 0:8fdf9a60065b 6178
kadonotakashi 0:8fdf9a60065b 6179 /*! @name XACCH3 - Execute-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6180 #define FTFA_XACCH3_XA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6181 #define FTFA_XACCH3_XA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6182 #define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
kadonotakashi 0:8fdf9a60065b 6183
kadonotakashi 0:8fdf9a60065b 6184 /*! @name XACCH2 - Execute-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6185 #define FTFA_XACCH2_XA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6186 #define FTFA_XACCH2_XA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6187 #define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
kadonotakashi 0:8fdf9a60065b 6188
kadonotakashi 0:8fdf9a60065b 6189 /*! @name XACCH1 - Execute-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6190 #define FTFA_XACCH1_XA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6191 #define FTFA_XACCH1_XA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6192 #define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
kadonotakashi 0:8fdf9a60065b 6193
kadonotakashi 0:8fdf9a60065b 6194 /*! @name XACCH0 - Execute-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6195 #define FTFA_XACCH0_XA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6196 #define FTFA_XACCH0_XA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6197 #define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
kadonotakashi 0:8fdf9a60065b 6198
kadonotakashi 0:8fdf9a60065b 6199 /*! @name XACCL3 - Execute-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6200 #define FTFA_XACCL3_XA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6201 #define FTFA_XACCL3_XA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6202 #define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
kadonotakashi 0:8fdf9a60065b 6203
kadonotakashi 0:8fdf9a60065b 6204 /*! @name XACCL2 - Execute-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6205 #define FTFA_XACCL2_XA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6206 #define FTFA_XACCL2_XA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6207 #define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
kadonotakashi 0:8fdf9a60065b 6208
kadonotakashi 0:8fdf9a60065b 6209 /*! @name XACCL1 - Execute-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6210 #define FTFA_XACCL1_XA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6211 #define FTFA_XACCL1_XA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6212 #define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
kadonotakashi 0:8fdf9a60065b 6213
kadonotakashi 0:8fdf9a60065b 6214 /*! @name XACCL0 - Execute-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6215 #define FTFA_XACCL0_XA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6216 #define FTFA_XACCL0_XA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6217 #define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
kadonotakashi 0:8fdf9a60065b 6218
kadonotakashi 0:8fdf9a60065b 6219 /*! @name SACCH3 - Supervisor-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6220 #define FTFA_SACCH3_SA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6221 #define FTFA_SACCH3_SA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6222 #define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
kadonotakashi 0:8fdf9a60065b 6223
kadonotakashi 0:8fdf9a60065b 6224 /*! @name SACCH2 - Supervisor-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6225 #define FTFA_SACCH2_SA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6226 #define FTFA_SACCH2_SA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6227 #define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
kadonotakashi 0:8fdf9a60065b 6228
kadonotakashi 0:8fdf9a60065b 6229 /*! @name SACCH1 - Supervisor-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6230 #define FTFA_SACCH1_SA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6231 #define FTFA_SACCH1_SA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6232 #define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
kadonotakashi 0:8fdf9a60065b 6233
kadonotakashi 0:8fdf9a60065b 6234 /*! @name SACCH0 - Supervisor-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6235 #define FTFA_SACCH0_SA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6236 #define FTFA_SACCH0_SA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6237 #define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
kadonotakashi 0:8fdf9a60065b 6238
kadonotakashi 0:8fdf9a60065b 6239 /*! @name SACCL3 - Supervisor-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6240 #define FTFA_SACCL3_SA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6241 #define FTFA_SACCL3_SA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6242 #define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
kadonotakashi 0:8fdf9a60065b 6243
kadonotakashi 0:8fdf9a60065b 6244 /*! @name SACCL2 - Supervisor-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6245 #define FTFA_SACCL2_SA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6246 #define FTFA_SACCL2_SA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6247 #define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
kadonotakashi 0:8fdf9a60065b 6248
kadonotakashi 0:8fdf9a60065b 6249 /*! @name SACCL1 - Supervisor-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6250 #define FTFA_SACCL1_SA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6251 #define FTFA_SACCL1_SA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6252 #define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
kadonotakashi 0:8fdf9a60065b 6253
kadonotakashi 0:8fdf9a60065b 6254 /*! @name SACCL0 - Supervisor-only Access Registers */
kadonotakashi 0:8fdf9a60065b 6255 #define FTFA_SACCL0_SA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6256 #define FTFA_SACCL0_SA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6257 #define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
kadonotakashi 0:8fdf9a60065b 6258
kadonotakashi 0:8fdf9a60065b 6259 /*! @name FACSS - Flash Access Segment Size Register */
kadonotakashi 0:8fdf9a60065b 6260 #define FTFA_FACSS_SGSIZE_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6261 #define FTFA_FACSS_SGSIZE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6262 #define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
kadonotakashi 0:8fdf9a60065b 6263
kadonotakashi 0:8fdf9a60065b 6264 /*! @name FACSN - Flash Access Segment Number Register */
kadonotakashi 0:8fdf9a60065b 6265 #define FTFA_FACSN_NUMSG_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 6266 #define FTFA_FACSN_NUMSG_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6267 #define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
kadonotakashi 0:8fdf9a60065b 6268
kadonotakashi 0:8fdf9a60065b 6269
kadonotakashi 0:8fdf9a60065b 6270 /*!
kadonotakashi 0:8fdf9a60065b 6271 * @}
kadonotakashi 0:8fdf9a60065b 6272 */ /* end of group FTFA_Register_Masks */
kadonotakashi 0:8fdf9a60065b 6273
kadonotakashi 0:8fdf9a60065b 6274
kadonotakashi 0:8fdf9a60065b 6275 /* FTFA - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 6276 /** Peripheral FTFA base address */
kadonotakashi 0:8fdf9a60065b 6277 #define FTFA_BASE (0x40020000u)
kadonotakashi 0:8fdf9a60065b 6278 /** Peripheral FTFA base pointer */
kadonotakashi 0:8fdf9a60065b 6279 #define FTFA ((FTFA_Type *)FTFA_BASE)
kadonotakashi 0:8fdf9a60065b 6280 /** Array initializer of FTFA peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 6281 #define FTFA_BASE_ADDRS { FTFA_BASE }
kadonotakashi 0:8fdf9a60065b 6282 /** Array initializer of FTFA peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 6283 #define FTFA_BASE_PTRS { FTFA }
kadonotakashi 0:8fdf9a60065b 6284 /** Interrupt vectors for the FTFA peripheral type */
kadonotakashi 0:8fdf9a60065b 6285 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
kadonotakashi 0:8fdf9a60065b 6286 #define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
kadonotakashi 0:8fdf9a60065b 6287
kadonotakashi 0:8fdf9a60065b 6288 /*!
kadonotakashi 0:8fdf9a60065b 6289 * @}
kadonotakashi 0:8fdf9a60065b 6290 */ /* end of group FTFA_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 6291
kadonotakashi 0:8fdf9a60065b 6292
kadonotakashi 0:8fdf9a60065b 6293 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 6294 -- FTM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 6295 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 6296
kadonotakashi 0:8fdf9a60065b 6297 /*!
kadonotakashi 0:8fdf9a60065b 6298 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 6299 * @{
kadonotakashi 0:8fdf9a60065b 6300 */
kadonotakashi 0:8fdf9a60065b 6301
kadonotakashi 0:8fdf9a60065b 6302 /** FTM - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 6303 typedef struct {
kadonotakashi 0:8fdf9a60065b 6304 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 6305 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 6306 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 6307 struct { /* offset: 0xC, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 6308 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 6309 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 6310 } CONTROLS[8];
kadonotakashi 0:8fdf9a60065b 6311 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
kadonotakashi 0:8fdf9a60065b 6312 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
kadonotakashi 0:8fdf9a60065b 6313 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
kadonotakashi 0:8fdf9a60065b 6314 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
kadonotakashi 0:8fdf9a60065b 6315 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
kadonotakashi 0:8fdf9a60065b 6316 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
kadonotakashi 0:8fdf9a60065b 6317 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
kadonotakashi 0:8fdf9a60065b 6318 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
kadonotakashi 0:8fdf9a60065b 6319 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
kadonotakashi 0:8fdf9a60065b 6320 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
kadonotakashi 0:8fdf9a60065b 6321 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
kadonotakashi 0:8fdf9a60065b 6322 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
kadonotakashi 0:8fdf9a60065b 6323 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
kadonotakashi 0:8fdf9a60065b 6324 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
kadonotakashi 0:8fdf9a60065b 6325 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
kadonotakashi 0:8fdf9a60065b 6326 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
kadonotakashi 0:8fdf9a60065b 6327 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
kadonotakashi 0:8fdf9a60065b 6328 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
kadonotakashi 0:8fdf9a60065b 6329 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
kadonotakashi 0:8fdf9a60065b 6330 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
kadonotakashi 0:8fdf9a60065b 6331 } FTM_Type;
kadonotakashi 0:8fdf9a60065b 6332
kadonotakashi 0:8fdf9a60065b 6333 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 6334 -- FTM Register Masks
kadonotakashi 0:8fdf9a60065b 6335 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 6336
kadonotakashi 0:8fdf9a60065b 6337 /*!
kadonotakashi 0:8fdf9a60065b 6338 * @addtogroup FTM_Register_Masks FTM Register Masks
kadonotakashi 0:8fdf9a60065b 6339 * @{
kadonotakashi 0:8fdf9a60065b 6340 */
kadonotakashi 0:8fdf9a60065b 6341
kadonotakashi 0:8fdf9a60065b 6342 /*! @name SC - Status And Control */
kadonotakashi 0:8fdf9a60065b 6343 #define FTM_SC_PS_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 6344 #define FTM_SC_PS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6345 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
kadonotakashi 0:8fdf9a60065b 6346 #define FTM_SC_CLKS_MASK (0x18U)
kadonotakashi 0:8fdf9a60065b 6347 #define FTM_SC_CLKS_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6348 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
kadonotakashi 0:8fdf9a60065b 6349 #define FTM_SC_CPWMS_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6350 #define FTM_SC_CPWMS_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6351 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
kadonotakashi 0:8fdf9a60065b 6352 #define FTM_SC_TOIE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6353 #define FTM_SC_TOIE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6354 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
kadonotakashi 0:8fdf9a60065b 6355 #define FTM_SC_TOF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6356 #define FTM_SC_TOF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6357 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
kadonotakashi 0:8fdf9a60065b 6358
kadonotakashi 0:8fdf9a60065b 6359 /*! @name CNT - Counter */
kadonotakashi 0:8fdf9a60065b 6360 #define FTM_CNT_COUNT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 6361 #define FTM_CNT_COUNT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6362 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
kadonotakashi 0:8fdf9a60065b 6363
kadonotakashi 0:8fdf9a60065b 6364 /*! @name MOD - Modulo */
kadonotakashi 0:8fdf9a60065b 6365 #define FTM_MOD_MOD_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 6366 #define FTM_MOD_MOD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6367 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
kadonotakashi 0:8fdf9a60065b 6368
kadonotakashi 0:8fdf9a60065b 6369 /*! @name CnSC - Channel (n) Status And Control */
kadonotakashi 0:8fdf9a60065b 6370 #define FTM_CnSC_DMA_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6371 #define FTM_CnSC_DMA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6372 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
kadonotakashi 0:8fdf9a60065b 6373 #define FTM_CnSC_ICRST_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6374 #define FTM_CnSC_ICRST_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6375 #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
kadonotakashi 0:8fdf9a60065b 6376 #define FTM_CnSC_ELSA_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6377 #define FTM_CnSC_ELSA_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6378 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
kadonotakashi 0:8fdf9a60065b 6379 #define FTM_CnSC_ELSB_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6380 #define FTM_CnSC_ELSB_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6381 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
kadonotakashi 0:8fdf9a60065b 6382 #define FTM_CnSC_MSA_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6383 #define FTM_CnSC_MSA_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6384 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
kadonotakashi 0:8fdf9a60065b 6385 #define FTM_CnSC_MSB_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6386 #define FTM_CnSC_MSB_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6387 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
kadonotakashi 0:8fdf9a60065b 6388 #define FTM_CnSC_CHIE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6389 #define FTM_CnSC_CHIE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6390 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
kadonotakashi 0:8fdf9a60065b 6391 #define FTM_CnSC_CHF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6392 #define FTM_CnSC_CHF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6393 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
kadonotakashi 0:8fdf9a60065b 6394
kadonotakashi 0:8fdf9a60065b 6395 /* The count of FTM_CnSC */
kadonotakashi 0:8fdf9a60065b 6396 #define FTM_CnSC_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 6397
kadonotakashi 0:8fdf9a60065b 6398 /*! @name CnV - Channel (n) Value */
kadonotakashi 0:8fdf9a60065b 6399 #define FTM_CnV_VAL_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 6400 #define FTM_CnV_VAL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6401 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
kadonotakashi 0:8fdf9a60065b 6402
kadonotakashi 0:8fdf9a60065b 6403 /* The count of FTM_CnV */
kadonotakashi 0:8fdf9a60065b 6404 #define FTM_CnV_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 6405
kadonotakashi 0:8fdf9a60065b 6406 /*! @name CNTIN - Counter Initial Value */
kadonotakashi 0:8fdf9a60065b 6407 #define FTM_CNTIN_INIT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 6408 #define FTM_CNTIN_INIT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6409 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
kadonotakashi 0:8fdf9a60065b 6410
kadonotakashi 0:8fdf9a60065b 6411 /*! @name STATUS - Capture And Compare Status */
kadonotakashi 0:8fdf9a60065b 6412 #define FTM_STATUS_CH0F_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6413 #define FTM_STATUS_CH0F_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6414 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
kadonotakashi 0:8fdf9a60065b 6415 #define FTM_STATUS_CH1F_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6416 #define FTM_STATUS_CH1F_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6417 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
kadonotakashi 0:8fdf9a60065b 6418 #define FTM_STATUS_CH2F_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6419 #define FTM_STATUS_CH2F_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6420 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
kadonotakashi 0:8fdf9a60065b 6421 #define FTM_STATUS_CH3F_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6422 #define FTM_STATUS_CH3F_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6423 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
kadonotakashi 0:8fdf9a60065b 6424 #define FTM_STATUS_CH4F_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6425 #define FTM_STATUS_CH4F_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6426 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
kadonotakashi 0:8fdf9a60065b 6427 #define FTM_STATUS_CH5F_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6428 #define FTM_STATUS_CH5F_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6429 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
kadonotakashi 0:8fdf9a60065b 6430 #define FTM_STATUS_CH6F_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6431 #define FTM_STATUS_CH6F_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6432 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
kadonotakashi 0:8fdf9a60065b 6433 #define FTM_STATUS_CH7F_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6434 #define FTM_STATUS_CH7F_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6435 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
kadonotakashi 0:8fdf9a60065b 6436
kadonotakashi 0:8fdf9a60065b 6437 /*! @name MODE - Features Mode Selection */
kadonotakashi 0:8fdf9a60065b 6438 #define FTM_MODE_FTMEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6439 #define FTM_MODE_FTMEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6440 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
kadonotakashi 0:8fdf9a60065b 6441 #define FTM_MODE_INIT_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6442 #define FTM_MODE_INIT_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6443 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
kadonotakashi 0:8fdf9a60065b 6444 #define FTM_MODE_WPDIS_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6445 #define FTM_MODE_WPDIS_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6446 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
kadonotakashi 0:8fdf9a60065b 6447 #define FTM_MODE_PWMSYNC_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6448 #define FTM_MODE_PWMSYNC_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6449 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
kadonotakashi 0:8fdf9a60065b 6450 #define FTM_MODE_CAPTEST_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6451 #define FTM_MODE_CAPTEST_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6452 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
kadonotakashi 0:8fdf9a60065b 6453 #define FTM_MODE_FAULTM_MASK (0x60U)
kadonotakashi 0:8fdf9a60065b 6454 #define FTM_MODE_FAULTM_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6455 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
kadonotakashi 0:8fdf9a60065b 6456 #define FTM_MODE_FAULTIE_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6457 #define FTM_MODE_FAULTIE_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6458 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
kadonotakashi 0:8fdf9a60065b 6459
kadonotakashi 0:8fdf9a60065b 6460 /*! @name SYNC - Synchronization */
kadonotakashi 0:8fdf9a60065b 6461 #define FTM_SYNC_CNTMIN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6462 #define FTM_SYNC_CNTMIN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6463 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
kadonotakashi 0:8fdf9a60065b 6464 #define FTM_SYNC_CNTMAX_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6465 #define FTM_SYNC_CNTMAX_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6466 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
kadonotakashi 0:8fdf9a60065b 6467 #define FTM_SYNC_REINIT_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6468 #define FTM_SYNC_REINIT_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6469 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
kadonotakashi 0:8fdf9a60065b 6470 #define FTM_SYNC_SYNCHOM_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6471 #define FTM_SYNC_SYNCHOM_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6472 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
kadonotakashi 0:8fdf9a60065b 6473 #define FTM_SYNC_TRIG0_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6474 #define FTM_SYNC_TRIG0_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6475 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
kadonotakashi 0:8fdf9a60065b 6476 #define FTM_SYNC_TRIG1_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6477 #define FTM_SYNC_TRIG1_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6478 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
kadonotakashi 0:8fdf9a60065b 6479 #define FTM_SYNC_TRIG2_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6480 #define FTM_SYNC_TRIG2_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6481 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
kadonotakashi 0:8fdf9a60065b 6482 #define FTM_SYNC_SWSYNC_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6483 #define FTM_SYNC_SWSYNC_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6484 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
kadonotakashi 0:8fdf9a60065b 6485
kadonotakashi 0:8fdf9a60065b 6486 /*! @name OUTINIT - Initial State For Channels Output */
kadonotakashi 0:8fdf9a60065b 6487 #define FTM_OUTINIT_CH0OI_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6488 #define FTM_OUTINIT_CH0OI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6489 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
kadonotakashi 0:8fdf9a60065b 6490 #define FTM_OUTINIT_CH1OI_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6491 #define FTM_OUTINIT_CH1OI_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6492 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
kadonotakashi 0:8fdf9a60065b 6493 #define FTM_OUTINIT_CH2OI_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6494 #define FTM_OUTINIT_CH2OI_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6495 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
kadonotakashi 0:8fdf9a60065b 6496 #define FTM_OUTINIT_CH3OI_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6497 #define FTM_OUTINIT_CH3OI_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6498 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
kadonotakashi 0:8fdf9a60065b 6499 #define FTM_OUTINIT_CH4OI_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6500 #define FTM_OUTINIT_CH4OI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6501 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
kadonotakashi 0:8fdf9a60065b 6502 #define FTM_OUTINIT_CH5OI_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6503 #define FTM_OUTINIT_CH5OI_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6504 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
kadonotakashi 0:8fdf9a60065b 6505 #define FTM_OUTINIT_CH6OI_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6506 #define FTM_OUTINIT_CH6OI_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6507 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
kadonotakashi 0:8fdf9a60065b 6508 #define FTM_OUTINIT_CH7OI_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6509 #define FTM_OUTINIT_CH7OI_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6510 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
kadonotakashi 0:8fdf9a60065b 6511
kadonotakashi 0:8fdf9a60065b 6512 /*! @name OUTMASK - Output Mask */
kadonotakashi 0:8fdf9a60065b 6513 #define FTM_OUTMASK_CH0OM_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6514 #define FTM_OUTMASK_CH0OM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6515 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
kadonotakashi 0:8fdf9a60065b 6516 #define FTM_OUTMASK_CH1OM_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6517 #define FTM_OUTMASK_CH1OM_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6518 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
kadonotakashi 0:8fdf9a60065b 6519 #define FTM_OUTMASK_CH2OM_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6520 #define FTM_OUTMASK_CH2OM_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6521 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
kadonotakashi 0:8fdf9a60065b 6522 #define FTM_OUTMASK_CH3OM_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6523 #define FTM_OUTMASK_CH3OM_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6524 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
kadonotakashi 0:8fdf9a60065b 6525 #define FTM_OUTMASK_CH4OM_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6526 #define FTM_OUTMASK_CH4OM_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6527 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
kadonotakashi 0:8fdf9a60065b 6528 #define FTM_OUTMASK_CH5OM_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6529 #define FTM_OUTMASK_CH5OM_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6530 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
kadonotakashi 0:8fdf9a60065b 6531 #define FTM_OUTMASK_CH6OM_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6532 #define FTM_OUTMASK_CH6OM_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6533 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
kadonotakashi 0:8fdf9a60065b 6534 #define FTM_OUTMASK_CH7OM_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6535 #define FTM_OUTMASK_CH7OM_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6536 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
kadonotakashi 0:8fdf9a60065b 6537
kadonotakashi 0:8fdf9a60065b 6538 /*! @name COMBINE - Function For Linked Channels */
kadonotakashi 0:8fdf9a60065b 6539 #define FTM_COMBINE_COMBINE0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6540 #define FTM_COMBINE_COMBINE0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6541 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
kadonotakashi 0:8fdf9a60065b 6542 #define FTM_COMBINE_COMP0_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6543 #define FTM_COMBINE_COMP0_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6544 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
kadonotakashi 0:8fdf9a60065b 6545 #define FTM_COMBINE_DECAPEN0_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6546 #define FTM_COMBINE_DECAPEN0_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6547 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
kadonotakashi 0:8fdf9a60065b 6548 #define FTM_COMBINE_DECAP0_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6549 #define FTM_COMBINE_DECAP0_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6550 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
kadonotakashi 0:8fdf9a60065b 6551 #define FTM_COMBINE_DTEN0_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6552 #define FTM_COMBINE_DTEN0_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6553 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
kadonotakashi 0:8fdf9a60065b 6554 #define FTM_COMBINE_SYNCEN0_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6555 #define FTM_COMBINE_SYNCEN0_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6556 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
kadonotakashi 0:8fdf9a60065b 6557 #define FTM_COMBINE_FAULTEN0_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6558 #define FTM_COMBINE_FAULTEN0_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6559 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
kadonotakashi 0:8fdf9a60065b 6560 #define FTM_COMBINE_COMBINE1_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 6561 #define FTM_COMBINE_COMBINE1_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 6562 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
kadonotakashi 0:8fdf9a60065b 6563 #define FTM_COMBINE_COMP1_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 6564 #define FTM_COMBINE_COMP1_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 6565 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
kadonotakashi 0:8fdf9a60065b 6566 #define FTM_COMBINE_DECAPEN1_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 6567 #define FTM_COMBINE_DECAPEN1_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 6568 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
kadonotakashi 0:8fdf9a60065b 6569 #define FTM_COMBINE_DECAP1_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 6570 #define FTM_COMBINE_DECAP1_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 6571 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
kadonotakashi 0:8fdf9a60065b 6572 #define FTM_COMBINE_DTEN1_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 6573 #define FTM_COMBINE_DTEN1_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 6574 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
kadonotakashi 0:8fdf9a60065b 6575 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 6576 #define FTM_COMBINE_SYNCEN1_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 6577 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
kadonotakashi 0:8fdf9a60065b 6578 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 6579 #define FTM_COMBINE_FAULTEN1_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 6580 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
kadonotakashi 0:8fdf9a60065b 6581 #define FTM_COMBINE_COMBINE2_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 6582 #define FTM_COMBINE_COMBINE2_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 6583 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
kadonotakashi 0:8fdf9a60065b 6584 #define FTM_COMBINE_COMP2_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 6585 #define FTM_COMBINE_COMP2_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 6586 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
kadonotakashi 0:8fdf9a60065b 6587 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 6588 #define FTM_COMBINE_DECAPEN2_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 6589 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
kadonotakashi 0:8fdf9a60065b 6590 #define FTM_COMBINE_DECAP2_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 6591 #define FTM_COMBINE_DECAP2_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 6592 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
kadonotakashi 0:8fdf9a60065b 6593 #define FTM_COMBINE_DTEN2_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 6594 #define FTM_COMBINE_DTEN2_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 6595 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
kadonotakashi 0:8fdf9a60065b 6596 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 6597 #define FTM_COMBINE_SYNCEN2_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 6598 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
kadonotakashi 0:8fdf9a60065b 6599 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 6600 #define FTM_COMBINE_FAULTEN2_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 6601 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
kadonotakashi 0:8fdf9a60065b 6602 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 6603 #define FTM_COMBINE_COMBINE3_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 6604 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
kadonotakashi 0:8fdf9a60065b 6605 #define FTM_COMBINE_COMP3_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 6606 #define FTM_COMBINE_COMP3_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 6607 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
kadonotakashi 0:8fdf9a60065b 6608 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 6609 #define FTM_COMBINE_DECAPEN3_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 6610 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
kadonotakashi 0:8fdf9a60065b 6611 #define FTM_COMBINE_DECAP3_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 6612 #define FTM_COMBINE_DECAP3_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 6613 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
kadonotakashi 0:8fdf9a60065b 6614 #define FTM_COMBINE_DTEN3_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 6615 #define FTM_COMBINE_DTEN3_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 6616 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
kadonotakashi 0:8fdf9a60065b 6617 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 6618 #define FTM_COMBINE_SYNCEN3_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 6619 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
kadonotakashi 0:8fdf9a60065b 6620 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 6621 #define FTM_COMBINE_FAULTEN3_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 6622 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
kadonotakashi 0:8fdf9a60065b 6623
kadonotakashi 0:8fdf9a60065b 6624 /*! @name DEADTIME - Deadtime Insertion Control */
kadonotakashi 0:8fdf9a60065b 6625 #define FTM_DEADTIME_DTVAL_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 6626 #define FTM_DEADTIME_DTVAL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6627 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
kadonotakashi 0:8fdf9a60065b 6628 #define FTM_DEADTIME_DTPS_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 6629 #define FTM_DEADTIME_DTPS_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6630 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
kadonotakashi 0:8fdf9a60065b 6631
kadonotakashi 0:8fdf9a60065b 6632 /*! @name EXTTRIG - FTM External Trigger */
kadonotakashi 0:8fdf9a60065b 6633 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6634 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6635 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
kadonotakashi 0:8fdf9a60065b 6636 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6637 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6638 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
kadonotakashi 0:8fdf9a60065b 6639 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6640 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6641 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
kadonotakashi 0:8fdf9a60065b 6642 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6643 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6644 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
kadonotakashi 0:8fdf9a60065b 6645 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6646 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6647 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
kadonotakashi 0:8fdf9a60065b 6648 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6649 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6650 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
kadonotakashi 0:8fdf9a60065b 6651 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6652 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6653 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
kadonotakashi 0:8fdf9a60065b 6654 #define FTM_EXTTRIG_TRIGF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6655 #define FTM_EXTTRIG_TRIGF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6656 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
kadonotakashi 0:8fdf9a60065b 6657
kadonotakashi 0:8fdf9a60065b 6658 /*! @name POL - Channels Polarity */
kadonotakashi 0:8fdf9a60065b 6659 #define FTM_POL_POL0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6660 #define FTM_POL_POL0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6661 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
kadonotakashi 0:8fdf9a60065b 6662 #define FTM_POL_POL1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6663 #define FTM_POL_POL1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6664 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
kadonotakashi 0:8fdf9a60065b 6665 #define FTM_POL_POL2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6666 #define FTM_POL_POL2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6667 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
kadonotakashi 0:8fdf9a60065b 6668 #define FTM_POL_POL3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6669 #define FTM_POL_POL3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6670 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
kadonotakashi 0:8fdf9a60065b 6671 #define FTM_POL_POL4_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6672 #define FTM_POL_POL4_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6673 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
kadonotakashi 0:8fdf9a60065b 6674 #define FTM_POL_POL5_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6675 #define FTM_POL_POL5_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6676 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
kadonotakashi 0:8fdf9a60065b 6677 #define FTM_POL_POL6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6678 #define FTM_POL_POL6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6679 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
kadonotakashi 0:8fdf9a60065b 6680 #define FTM_POL_POL7_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6681 #define FTM_POL_POL7_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6682 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
kadonotakashi 0:8fdf9a60065b 6683
kadonotakashi 0:8fdf9a60065b 6684 /*! @name FMS - Fault Mode Status */
kadonotakashi 0:8fdf9a60065b 6685 #define FTM_FMS_FAULTF0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6686 #define FTM_FMS_FAULTF0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6687 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
kadonotakashi 0:8fdf9a60065b 6688 #define FTM_FMS_FAULTF1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6689 #define FTM_FMS_FAULTF1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6690 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
kadonotakashi 0:8fdf9a60065b 6691 #define FTM_FMS_FAULTF2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6692 #define FTM_FMS_FAULTF2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6693 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
kadonotakashi 0:8fdf9a60065b 6694 #define FTM_FMS_FAULTF3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6695 #define FTM_FMS_FAULTF3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6696 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
kadonotakashi 0:8fdf9a60065b 6697 #define FTM_FMS_FAULTIN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6698 #define FTM_FMS_FAULTIN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6699 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
kadonotakashi 0:8fdf9a60065b 6700 #define FTM_FMS_WPEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6701 #define FTM_FMS_WPEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6702 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
kadonotakashi 0:8fdf9a60065b 6703 #define FTM_FMS_FAULTF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6704 #define FTM_FMS_FAULTF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6705 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
kadonotakashi 0:8fdf9a60065b 6706
kadonotakashi 0:8fdf9a60065b 6707 /*! @name FILTER - Input Capture Filter Control */
kadonotakashi 0:8fdf9a60065b 6708 #define FTM_FILTER_CH0FVAL_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 6709 #define FTM_FILTER_CH0FVAL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6710 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
kadonotakashi 0:8fdf9a60065b 6711 #define FTM_FILTER_CH1FVAL_MASK (0xF0U)
kadonotakashi 0:8fdf9a60065b 6712 #define FTM_FILTER_CH1FVAL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6713 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
kadonotakashi 0:8fdf9a60065b 6714 #define FTM_FILTER_CH2FVAL_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 6715 #define FTM_FILTER_CH2FVAL_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 6716 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
kadonotakashi 0:8fdf9a60065b 6717 #define FTM_FILTER_CH3FVAL_MASK (0xF000U)
kadonotakashi 0:8fdf9a60065b 6718 #define FTM_FILTER_CH3FVAL_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 6719 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
kadonotakashi 0:8fdf9a60065b 6720
kadonotakashi 0:8fdf9a60065b 6721 /*! @name FLTCTRL - Fault Control */
kadonotakashi 0:8fdf9a60065b 6722 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6723 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6724 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
kadonotakashi 0:8fdf9a60065b 6725 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6726 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6727 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
kadonotakashi 0:8fdf9a60065b 6728 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6729 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6730 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
kadonotakashi 0:8fdf9a60065b 6731 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6732 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6733 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
kadonotakashi 0:8fdf9a60065b 6734 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6735 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6736 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
kadonotakashi 0:8fdf9a60065b 6737 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6738 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6739 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
kadonotakashi 0:8fdf9a60065b 6740 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6741 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6742 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
kadonotakashi 0:8fdf9a60065b 6743 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6744 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6745 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
kadonotakashi 0:8fdf9a60065b 6746 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 6747 #define FTM_FLTCTRL_FFVAL_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 6748 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
kadonotakashi 0:8fdf9a60065b 6749
kadonotakashi 0:8fdf9a60065b 6750 /*! @name QDCTRL - Quadrature Decoder Control And Status */
kadonotakashi 0:8fdf9a60065b 6751 #define FTM_QDCTRL_QUADEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6752 #define FTM_QDCTRL_QUADEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6753 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
kadonotakashi 0:8fdf9a60065b 6754 #define FTM_QDCTRL_TOFDIR_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6755 #define FTM_QDCTRL_TOFDIR_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6756 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
kadonotakashi 0:8fdf9a60065b 6757 #define FTM_QDCTRL_QUADIR_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6758 #define FTM_QDCTRL_QUADIR_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6759 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
kadonotakashi 0:8fdf9a60065b 6760 #define FTM_QDCTRL_QUADMODE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6761 #define FTM_QDCTRL_QUADMODE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6762 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
kadonotakashi 0:8fdf9a60065b 6763 #define FTM_QDCTRL_PHBPOL_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6764 #define FTM_QDCTRL_PHBPOL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6765 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
kadonotakashi 0:8fdf9a60065b 6766 #define FTM_QDCTRL_PHAPOL_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6767 #define FTM_QDCTRL_PHAPOL_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6768 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
kadonotakashi 0:8fdf9a60065b 6769 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6770 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6771 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
kadonotakashi 0:8fdf9a60065b 6772 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6773 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6774 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
kadonotakashi 0:8fdf9a60065b 6775
kadonotakashi 0:8fdf9a60065b 6776 /*! @name CONF - Configuration */
kadonotakashi 0:8fdf9a60065b 6777 #define FTM_CONF_NUMTOF_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 6778 #define FTM_CONF_NUMTOF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6779 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
kadonotakashi 0:8fdf9a60065b 6780 #define FTM_CONF_BDMMODE_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 6781 #define FTM_CONF_BDMMODE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6782 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
kadonotakashi 0:8fdf9a60065b 6783 #define FTM_CONF_GTBEEN_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 6784 #define FTM_CONF_GTBEEN_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 6785 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
kadonotakashi 0:8fdf9a60065b 6786 #define FTM_CONF_GTBEOUT_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 6787 #define FTM_CONF_GTBEOUT_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 6788 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
kadonotakashi 0:8fdf9a60065b 6789
kadonotakashi 0:8fdf9a60065b 6790 /*! @name FLTPOL - FTM Fault Input Polarity */
kadonotakashi 0:8fdf9a60065b 6791 #define FTM_FLTPOL_FLT0POL_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6792 #define FTM_FLTPOL_FLT0POL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6793 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
kadonotakashi 0:8fdf9a60065b 6794 #define FTM_FLTPOL_FLT1POL_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6795 #define FTM_FLTPOL_FLT1POL_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6796 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
kadonotakashi 0:8fdf9a60065b 6797 #define FTM_FLTPOL_FLT2POL_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6798 #define FTM_FLTPOL_FLT2POL_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6799 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
kadonotakashi 0:8fdf9a60065b 6800 #define FTM_FLTPOL_FLT3POL_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6801 #define FTM_FLTPOL_FLT3POL_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6802 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
kadonotakashi 0:8fdf9a60065b 6803
kadonotakashi 0:8fdf9a60065b 6804 /*! @name SYNCONF - Synchronization Configuration */
kadonotakashi 0:8fdf9a60065b 6805 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6806 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6807 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
kadonotakashi 0:8fdf9a60065b 6808 #define FTM_SYNCONF_CNTINC_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6809 #define FTM_SYNCONF_CNTINC_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6810 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
kadonotakashi 0:8fdf9a60065b 6811 #define FTM_SYNCONF_INVC_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6812 #define FTM_SYNCONF_INVC_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6813 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
kadonotakashi 0:8fdf9a60065b 6814 #define FTM_SYNCONF_SWOC_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6815 #define FTM_SYNCONF_SWOC_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6816 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
kadonotakashi 0:8fdf9a60065b 6817 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6818 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6819 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
kadonotakashi 0:8fdf9a60065b 6820 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 6821 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 6822 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
kadonotakashi 0:8fdf9a60065b 6823 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 6824 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 6825 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
kadonotakashi 0:8fdf9a60065b 6826 #define FTM_SYNCONF_SWOM_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 6827 #define FTM_SYNCONF_SWOM_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 6828 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
kadonotakashi 0:8fdf9a60065b 6829 #define FTM_SYNCONF_SWINVC_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 6830 #define FTM_SYNCONF_SWINVC_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 6831 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
kadonotakashi 0:8fdf9a60065b 6832 #define FTM_SYNCONF_SWSOC_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 6833 #define FTM_SYNCONF_SWSOC_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 6834 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
kadonotakashi 0:8fdf9a60065b 6835 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 6836 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 6837 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
kadonotakashi 0:8fdf9a60065b 6838 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 6839 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 6840 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
kadonotakashi 0:8fdf9a60065b 6841 #define FTM_SYNCONF_HWOM_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 6842 #define FTM_SYNCONF_HWOM_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 6843 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
kadonotakashi 0:8fdf9a60065b 6844 #define FTM_SYNCONF_HWINVC_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 6845 #define FTM_SYNCONF_HWINVC_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 6846 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
kadonotakashi 0:8fdf9a60065b 6847 #define FTM_SYNCONF_HWSOC_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 6848 #define FTM_SYNCONF_HWSOC_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 6849 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
kadonotakashi 0:8fdf9a60065b 6850
kadonotakashi 0:8fdf9a60065b 6851 /*! @name INVCTRL - FTM Inverting Control */
kadonotakashi 0:8fdf9a60065b 6852 #define FTM_INVCTRL_INV0EN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6853 #define FTM_INVCTRL_INV0EN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6854 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
kadonotakashi 0:8fdf9a60065b 6855 #define FTM_INVCTRL_INV1EN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6856 #define FTM_INVCTRL_INV1EN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6857 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
kadonotakashi 0:8fdf9a60065b 6858 #define FTM_INVCTRL_INV2EN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6859 #define FTM_INVCTRL_INV2EN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6860 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
kadonotakashi 0:8fdf9a60065b 6861 #define FTM_INVCTRL_INV3EN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6862 #define FTM_INVCTRL_INV3EN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6863 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
kadonotakashi 0:8fdf9a60065b 6864
kadonotakashi 0:8fdf9a60065b 6865 /*! @name SWOCTRL - FTM Software Output Control */
kadonotakashi 0:8fdf9a60065b 6866 #define FTM_SWOCTRL_CH0OC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6867 #define FTM_SWOCTRL_CH0OC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6868 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
kadonotakashi 0:8fdf9a60065b 6869 #define FTM_SWOCTRL_CH1OC_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6870 #define FTM_SWOCTRL_CH1OC_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6871 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
kadonotakashi 0:8fdf9a60065b 6872 #define FTM_SWOCTRL_CH2OC_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6873 #define FTM_SWOCTRL_CH2OC_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6874 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
kadonotakashi 0:8fdf9a60065b 6875 #define FTM_SWOCTRL_CH3OC_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6876 #define FTM_SWOCTRL_CH3OC_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6877 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
kadonotakashi 0:8fdf9a60065b 6878 #define FTM_SWOCTRL_CH4OC_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6879 #define FTM_SWOCTRL_CH4OC_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6880 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
kadonotakashi 0:8fdf9a60065b 6881 #define FTM_SWOCTRL_CH5OC_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6882 #define FTM_SWOCTRL_CH5OC_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6883 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
kadonotakashi 0:8fdf9a60065b 6884 #define FTM_SWOCTRL_CH6OC_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6885 #define FTM_SWOCTRL_CH6OC_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6886 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
kadonotakashi 0:8fdf9a60065b 6887 #define FTM_SWOCTRL_CH7OC_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6888 #define FTM_SWOCTRL_CH7OC_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6889 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
kadonotakashi 0:8fdf9a60065b 6890 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 6891 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 6892 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
kadonotakashi 0:8fdf9a60065b 6893 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 6894 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 6895 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
kadonotakashi 0:8fdf9a60065b 6896 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 6897 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 6898 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
kadonotakashi 0:8fdf9a60065b 6899 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 6900 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 6901 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
kadonotakashi 0:8fdf9a60065b 6902 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 6903 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 6904 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
kadonotakashi 0:8fdf9a60065b 6905 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 6906 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 6907 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
kadonotakashi 0:8fdf9a60065b 6908 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 6909 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 6910 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
kadonotakashi 0:8fdf9a60065b 6911 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 6912 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 6913 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
kadonotakashi 0:8fdf9a60065b 6914
kadonotakashi 0:8fdf9a60065b 6915 /*! @name PWMLOAD - FTM PWM Load */
kadonotakashi 0:8fdf9a60065b 6916 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 6917 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 6918 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
kadonotakashi 0:8fdf9a60065b 6919 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 6920 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 6921 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
kadonotakashi 0:8fdf9a60065b 6922 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 6923 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 6924 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
kadonotakashi 0:8fdf9a60065b 6925 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 6926 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 6927 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
kadonotakashi 0:8fdf9a60065b 6928 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 6929 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 6930 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
kadonotakashi 0:8fdf9a60065b 6931 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 6932 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 6933 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
kadonotakashi 0:8fdf9a60065b 6934 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 6935 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 6936 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
kadonotakashi 0:8fdf9a60065b 6937 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 6938 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 6939 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
kadonotakashi 0:8fdf9a60065b 6940 #define FTM_PWMLOAD_LDOK_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 6941 #define FTM_PWMLOAD_LDOK_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 6942 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
kadonotakashi 0:8fdf9a60065b 6943
kadonotakashi 0:8fdf9a60065b 6944
kadonotakashi 0:8fdf9a60065b 6945 /*!
kadonotakashi 0:8fdf9a60065b 6946 * @}
kadonotakashi 0:8fdf9a60065b 6947 */ /* end of group FTM_Register_Masks */
kadonotakashi 0:8fdf9a60065b 6948
kadonotakashi 0:8fdf9a60065b 6949
kadonotakashi 0:8fdf9a60065b 6950 /* FTM - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 6951 /** Peripheral FTM0 base address */
kadonotakashi 0:8fdf9a60065b 6952 #define FTM0_BASE (0x40038000u)
kadonotakashi 0:8fdf9a60065b 6953 /** Peripheral FTM0 base pointer */
kadonotakashi 0:8fdf9a60065b 6954 #define FTM0 ((FTM_Type *)FTM0_BASE)
kadonotakashi 0:8fdf9a60065b 6955 /** Peripheral FTM1 base address */
kadonotakashi 0:8fdf9a60065b 6956 #define FTM1_BASE (0x40039000u)
kadonotakashi 0:8fdf9a60065b 6957 /** Peripheral FTM1 base pointer */
kadonotakashi 0:8fdf9a60065b 6958 #define FTM1 ((FTM_Type *)FTM1_BASE)
kadonotakashi 0:8fdf9a60065b 6959 /** Peripheral FTM2 base address */
kadonotakashi 0:8fdf9a60065b 6960 #define FTM2_BASE (0x4003A000u)
kadonotakashi 0:8fdf9a60065b 6961 /** Peripheral FTM2 base pointer */
kadonotakashi 0:8fdf9a60065b 6962 #define FTM2 ((FTM_Type *)FTM2_BASE)
kadonotakashi 0:8fdf9a60065b 6963 /** Peripheral FTM3 base address */
kadonotakashi 0:8fdf9a60065b 6964 #define FTM3_BASE (0x400B9000u)
kadonotakashi 0:8fdf9a60065b 6965 /** Peripheral FTM3 base pointer */
kadonotakashi 0:8fdf9a60065b 6966 #define FTM3 ((FTM_Type *)FTM3_BASE)
kadonotakashi 0:8fdf9a60065b 6967 /** Array initializer of FTM peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 6968 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
kadonotakashi 0:8fdf9a60065b 6969 /** Array initializer of FTM peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 6970 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
kadonotakashi 0:8fdf9a60065b 6971 /** Interrupt vectors for the FTM peripheral type */
kadonotakashi 0:8fdf9a60065b 6972 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
kadonotakashi 0:8fdf9a60065b 6973
kadonotakashi 0:8fdf9a60065b 6974 /*!
kadonotakashi 0:8fdf9a60065b 6975 * @}
kadonotakashi 0:8fdf9a60065b 6976 */ /* end of group FTM_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 6977
kadonotakashi 0:8fdf9a60065b 6978
kadonotakashi 0:8fdf9a60065b 6979 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 6980 -- GPIO Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 6981 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 6982
kadonotakashi 0:8fdf9a60065b 6983 /*!
kadonotakashi 0:8fdf9a60065b 6984 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 6985 * @{
kadonotakashi 0:8fdf9a60065b 6986 */
kadonotakashi 0:8fdf9a60065b 6987
kadonotakashi 0:8fdf9a60065b 6988 /** GPIO - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 6989 typedef struct {
kadonotakashi 0:8fdf9a60065b 6990 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 6991 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 6992 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 6993 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 6994 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 6995 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 6996 } GPIO_Type;
kadonotakashi 0:8fdf9a60065b 6997
kadonotakashi 0:8fdf9a60065b 6998 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 6999 -- GPIO Register Masks
kadonotakashi 0:8fdf9a60065b 7000 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 7001
kadonotakashi 0:8fdf9a60065b 7002 /*!
kadonotakashi 0:8fdf9a60065b 7003 * @addtogroup GPIO_Register_Masks GPIO Register Masks
kadonotakashi 0:8fdf9a60065b 7004 * @{
kadonotakashi 0:8fdf9a60065b 7005 */
kadonotakashi 0:8fdf9a60065b 7006
kadonotakashi 0:8fdf9a60065b 7007 /*! @name PDOR - Port Data Output Register */
kadonotakashi 0:8fdf9a60065b 7008 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 7009 #define GPIO_PDOR_PDO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7010 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
kadonotakashi 0:8fdf9a60065b 7011
kadonotakashi 0:8fdf9a60065b 7012 /*! @name PSOR - Port Set Output Register */
kadonotakashi 0:8fdf9a60065b 7013 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 7014 #define GPIO_PSOR_PTSO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7015 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
kadonotakashi 0:8fdf9a60065b 7016
kadonotakashi 0:8fdf9a60065b 7017 /*! @name PCOR - Port Clear Output Register */
kadonotakashi 0:8fdf9a60065b 7018 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 7019 #define GPIO_PCOR_PTCO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7020 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
kadonotakashi 0:8fdf9a60065b 7021
kadonotakashi 0:8fdf9a60065b 7022 /*! @name PTOR - Port Toggle Output Register */
kadonotakashi 0:8fdf9a60065b 7023 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 7024 #define GPIO_PTOR_PTTO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7025 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
kadonotakashi 0:8fdf9a60065b 7026
kadonotakashi 0:8fdf9a60065b 7027 /*! @name PDIR - Port Data Input Register */
kadonotakashi 0:8fdf9a60065b 7028 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 7029 #define GPIO_PDIR_PDI_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7030 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
kadonotakashi 0:8fdf9a60065b 7031
kadonotakashi 0:8fdf9a60065b 7032 /*! @name PDDR - Port Data Direction Register */
kadonotakashi 0:8fdf9a60065b 7033 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 7034 #define GPIO_PDDR_PDD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7035 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
kadonotakashi 0:8fdf9a60065b 7036
kadonotakashi 0:8fdf9a60065b 7037
kadonotakashi 0:8fdf9a60065b 7038 /*!
kadonotakashi 0:8fdf9a60065b 7039 * @}
kadonotakashi 0:8fdf9a60065b 7040 */ /* end of group GPIO_Register_Masks */
kadonotakashi 0:8fdf9a60065b 7041
kadonotakashi 0:8fdf9a60065b 7042
kadonotakashi 0:8fdf9a60065b 7043 /* GPIO - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 7044 /** Peripheral GPIOA base address */
kadonotakashi 0:8fdf9a60065b 7045 #define GPIOA_BASE (0x400FF000u)
kadonotakashi 0:8fdf9a60065b 7046 /** Peripheral GPIOA base pointer */
kadonotakashi 0:8fdf9a60065b 7047 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
kadonotakashi 0:8fdf9a60065b 7048 /** Peripheral GPIOB base address */
kadonotakashi 0:8fdf9a60065b 7049 #define GPIOB_BASE (0x400FF040u)
kadonotakashi 0:8fdf9a60065b 7050 /** Peripheral GPIOB base pointer */
kadonotakashi 0:8fdf9a60065b 7051 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
kadonotakashi 0:8fdf9a60065b 7052 /** Peripheral GPIOC base address */
kadonotakashi 0:8fdf9a60065b 7053 #define GPIOC_BASE (0x400FF080u)
kadonotakashi 0:8fdf9a60065b 7054 /** Peripheral GPIOC base pointer */
kadonotakashi 0:8fdf9a60065b 7055 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
kadonotakashi 0:8fdf9a60065b 7056 /** Peripheral GPIOD base address */
kadonotakashi 0:8fdf9a60065b 7057 #define GPIOD_BASE (0x400FF0C0u)
kadonotakashi 0:8fdf9a60065b 7058 /** Peripheral GPIOD base pointer */
kadonotakashi 0:8fdf9a60065b 7059 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
kadonotakashi 0:8fdf9a60065b 7060 /** Peripheral GPIOE base address */
kadonotakashi 0:8fdf9a60065b 7061 #define GPIOE_BASE (0x400FF100u)
kadonotakashi 0:8fdf9a60065b 7062 /** Peripheral GPIOE base pointer */
kadonotakashi 0:8fdf9a60065b 7063 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
kadonotakashi 0:8fdf9a60065b 7064 /** Array initializer of GPIO peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 7065 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
kadonotakashi 0:8fdf9a60065b 7066 /** Array initializer of GPIO peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 7067 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
kadonotakashi 0:8fdf9a60065b 7068
kadonotakashi 0:8fdf9a60065b 7069 /*!
kadonotakashi 0:8fdf9a60065b 7070 * @}
kadonotakashi 0:8fdf9a60065b 7071 */ /* end of group GPIO_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 7072
kadonotakashi 0:8fdf9a60065b 7073
kadonotakashi 0:8fdf9a60065b 7074 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 7075 -- I2C Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 7076 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 7077
kadonotakashi 0:8fdf9a60065b 7078 /*!
kadonotakashi 0:8fdf9a60065b 7079 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 7080 * @{
kadonotakashi 0:8fdf9a60065b 7081 */
kadonotakashi 0:8fdf9a60065b 7082
kadonotakashi 0:8fdf9a60065b 7083 /** I2C - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 7084 typedef struct {
kadonotakashi 0:8fdf9a60065b 7085 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 7086 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 7087 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 7088 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
kadonotakashi 0:8fdf9a60065b 7089 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 7090 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
kadonotakashi 0:8fdf9a60065b 7091 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
kadonotakashi 0:8fdf9a60065b 7092 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
kadonotakashi 0:8fdf9a60065b 7093 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 7094 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
kadonotakashi 0:8fdf9a60065b 7095 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
kadonotakashi 0:8fdf9a60065b 7096 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
kadonotakashi 0:8fdf9a60065b 7097 __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 7098 } I2C_Type;
kadonotakashi 0:8fdf9a60065b 7099
kadonotakashi 0:8fdf9a60065b 7100 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 7101 -- I2C Register Masks
kadonotakashi 0:8fdf9a60065b 7102 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 7103
kadonotakashi 0:8fdf9a60065b 7104 /*!
kadonotakashi 0:8fdf9a60065b 7105 * @addtogroup I2C_Register_Masks I2C Register Masks
kadonotakashi 0:8fdf9a60065b 7106 * @{
kadonotakashi 0:8fdf9a60065b 7107 */
kadonotakashi 0:8fdf9a60065b 7108
kadonotakashi 0:8fdf9a60065b 7109 /*! @name A1 - I2C Address Register 1 */
kadonotakashi 0:8fdf9a60065b 7110 #define I2C_A1_AD_MASK (0xFEU)
kadonotakashi 0:8fdf9a60065b 7111 #define I2C_A1_AD_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7112 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
kadonotakashi 0:8fdf9a60065b 7113
kadonotakashi 0:8fdf9a60065b 7114 /*! @name F - I2C Frequency Divider register */
kadonotakashi 0:8fdf9a60065b 7115 #define I2C_F_ICR_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 7116 #define I2C_F_ICR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7117 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
kadonotakashi 0:8fdf9a60065b 7118 #define I2C_F_MULT_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 7119 #define I2C_F_MULT_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7120 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
kadonotakashi 0:8fdf9a60065b 7121
kadonotakashi 0:8fdf9a60065b 7122 /*! @name C1 - I2C Control Register 1 */
kadonotakashi 0:8fdf9a60065b 7123 #define I2C_C1_DMAEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7124 #define I2C_C1_DMAEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7125 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
kadonotakashi 0:8fdf9a60065b 7126 #define I2C_C1_WUEN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7127 #define I2C_C1_WUEN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7128 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
kadonotakashi 0:8fdf9a60065b 7129 #define I2C_C1_RSTA_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 7130 #define I2C_C1_RSTA_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7131 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
kadonotakashi 0:8fdf9a60065b 7132 #define I2C_C1_TXAK_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 7133 #define I2C_C1_TXAK_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 7134 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
kadonotakashi 0:8fdf9a60065b 7135 #define I2C_C1_TX_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7136 #define I2C_C1_TX_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7137 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
kadonotakashi 0:8fdf9a60065b 7138 #define I2C_C1_MST_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 7139 #define I2C_C1_MST_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 7140 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
kadonotakashi 0:8fdf9a60065b 7141 #define I2C_C1_IICIE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 7142 #define I2C_C1_IICIE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7143 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
kadonotakashi 0:8fdf9a60065b 7144 #define I2C_C1_IICEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 7145 #define I2C_C1_IICEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 7146 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
kadonotakashi 0:8fdf9a60065b 7147
kadonotakashi 0:8fdf9a60065b 7148 /*! @name S - I2C Status register */
kadonotakashi 0:8fdf9a60065b 7149 #define I2C_S_RXAK_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7150 #define I2C_S_RXAK_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7151 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
kadonotakashi 0:8fdf9a60065b 7152 #define I2C_S_IICIF_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7153 #define I2C_S_IICIF_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7154 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
kadonotakashi 0:8fdf9a60065b 7155 #define I2C_S_SRW_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 7156 #define I2C_S_SRW_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7157 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
kadonotakashi 0:8fdf9a60065b 7158 #define I2C_S_RAM_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 7159 #define I2C_S_RAM_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 7160 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
kadonotakashi 0:8fdf9a60065b 7161 #define I2C_S_ARBL_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7162 #define I2C_S_ARBL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7163 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
kadonotakashi 0:8fdf9a60065b 7164 #define I2C_S_BUSY_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 7165 #define I2C_S_BUSY_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 7166 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
kadonotakashi 0:8fdf9a60065b 7167 #define I2C_S_IAAS_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 7168 #define I2C_S_IAAS_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7169 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
kadonotakashi 0:8fdf9a60065b 7170 #define I2C_S_TCF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 7171 #define I2C_S_TCF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 7172 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
kadonotakashi 0:8fdf9a60065b 7173
kadonotakashi 0:8fdf9a60065b 7174 /*! @name D - I2C Data I/O register */
kadonotakashi 0:8fdf9a60065b 7175 #define I2C_D_DATA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 7176 #define I2C_D_DATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7177 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
kadonotakashi 0:8fdf9a60065b 7178
kadonotakashi 0:8fdf9a60065b 7179 /*! @name C2 - I2C Control Register 2 */
kadonotakashi 0:8fdf9a60065b 7180 #define I2C_C2_AD_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 7181 #define I2C_C2_AD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7182 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
kadonotakashi 0:8fdf9a60065b 7183 #define I2C_C2_RMEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 7184 #define I2C_C2_RMEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 7185 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
kadonotakashi 0:8fdf9a60065b 7186 #define I2C_C2_SBRC_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7187 #define I2C_C2_SBRC_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7188 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
kadonotakashi 0:8fdf9a60065b 7189 #define I2C_C2_HDRS_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 7190 #define I2C_C2_HDRS_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 7191 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
kadonotakashi 0:8fdf9a60065b 7192 #define I2C_C2_ADEXT_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 7193 #define I2C_C2_ADEXT_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7194 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
kadonotakashi 0:8fdf9a60065b 7195 #define I2C_C2_GCAEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 7196 #define I2C_C2_GCAEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 7197 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
kadonotakashi 0:8fdf9a60065b 7198
kadonotakashi 0:8fdf9a60065b 7199 /*! @name FLT - I2C Programmable Input Glitch Filter Register */
kadonotakashi 0:8fdf9a60065b 7200 #define I2C_FLT_FLT_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 7201 #define I2C_FLT_FLT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7202 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
kadonotakashi 0:8fdf9a60065b 7203 #define I2C_FLT_STARTF_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7204 #define I2C_FLT_STARTF_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7205 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
kadonotakashi 0:8fdf9a60065b 7206 #define I2C_FLT_SSIE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 7207 #define I2C_FLT_SSIE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 7208 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
kadonotakashi 0:8fdf9a60065b 7209 #define I2C_FLT_STOPF_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 7210 #define I2C_FLT_STOPF_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7211 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
kadonotakashi 0:8fdf9a60065b 7212 #define I2C_FLT_SHEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 7213 #define I2C_FLT_SHEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 7214 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
kadonotakashi 0:8fdf9a60065b 7215
kadonotakashi 0:8fdf9a60065b 7216 /*! @name RA - I2C Range Address register */
kadonotakashi 0:8fdf9a60065b 7217 #define I2C_RA_RAD_MASK (0xFEU)
kadonotakashi 0:8fdf9a60065b 7218 #define I2C_RA_RAD_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7219 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
kadonotakashi 0:8fdf9a60065b 7220
kadonotakashi 0:8fdf9a60065b 7221 /*! @name SMB - I2C SMBus Control and Status register */
kadonotakashi 0:8fdf9a60065b 7222 #define I2C_SMB_SHTF2IE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7223 #define I2C_SMB_SHTF2IE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7224 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
kadonotakashi 0:8fdf9a60065b 7225 #define I2C_SMB_SHTF2_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7226 #define I2C_SMB_SHTF2_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7227 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
kadonotakashi 0:8fdf9a60065b 7228 #define I2C_SMB_SHTF1_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 7229 #define I2C_SMB_SHTF1_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7230 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
kadonotakashi 0:8fdf9a60065b 7231 #define I2C_SMB_SLTF_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 7232 #define I2C_SMB_SLTF_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 7233 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
kadonotakashi 0:8fdf9a60065b 7234 #define I2C_SMB_TCKSEL_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7235 #define I2C_SMB_TCKSEL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7236 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
kadonotakashi 0:8fdf9a60065b 7237 #define I2C_SMB_SIICAEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 7238 #define I2C_SMB_SIICAEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 7239 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
kadonotakashi 0:8fdf9a60065b 7240 #define I2C_SMB_ALERTEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 7241 #define I2C_SMB_ALERTEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7242 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
kadonotakashi 0:8fdf9a60065b 7243 #define I2C_SMB_FACK_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 7244 #define I2C_SMB_FACK_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 7245 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
kadonotakashi 0:8fdf9a60065b 7246
kadonotakashi 0:8fdf9a60065b 7247 /*! @name A2 - I2C Address Register 2 */
kadonotakashi 0:8fdf9a60065b 7248 #define I2C_A2_SAD_MASK (0xFEU)
kadonotakashi 0:8fdf9a60065b 7249 #define I2C_A2_SAD_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7250 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
kadonotakashi 0:8fdf9a60065b 7251
kadonotakashi 0:8fdf9a60065b 7252 /*! @name SLTH - I2C SCL Low Timeout Register High */
kadonotakashi 0:8fdf9a60065b 7253 #define I2C_SLTH_SSLT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 7254 #define I2C_SLTH_SSLT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7255 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
kadonotakashi 0:8fdf9a60065b 7256
kadonotakashi 0:8fdf9a60065b 7257 /*! @name SLTL - I2C SCL Low Timeout Register Low */
kadonotakashi 0:8fdf9a60065b 7258 #define I2C_SLTL_SSLT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 7259 #define I2C_SLTL_SSLT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7260 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
kadonotakashi 0:8fdf9a60065b 7261
kadonotakashi 0:8fdf9a60065b 7262 /*! @name S2 - I2C Status register 2 */
kadonotakashi 0:8fdf9a60065b 7263 #define I2C_S2_EMPTY_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7264 #define I2C_S2_EMPTY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7265 #define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK)
kadonotakashi 0:8fdf9a60065b 7266 #define I2C_S2_ERROR_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7267 #define I2C_S2_ERROR_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7268 #define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK)
kadonotakashi 0:8fdf9a60065b 7269
kadonotakashi 0:8fdf9a60065b 7270
kadonotakashi 0:8fdf9a60065b 7271 /*!
kadonotakashi 0:8fdf9a60065b 7272 * @}
kadonotakashi 0:8fdf9a60065b 7273 */ /* end of group I2C_Register_Masks */
kadonotakashi 0:8fdf9a60065b 7274
kadonotakashi 0:8fdf9a60065b 7275
kadonotakashi 0:8fdf9a60065b 7276 /* I2C - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 7277 /** Peripheral I2C0 base address */
kadonotakashi 0:8fdf9a60065b 7278 #define I2C0_BASE (0x40066000u)
kadonotakashi 0:8fdf9a60065b 7279 /** Peripheral I2C0 base pointer */
kadonotakashi 0:8fdf9a60065b 7280 #define I2C0 ((I2C_Type *)I2C0_BASE)
kadonotakashi 0:8fdf9a60065b 7281 /** Peripheral I2C1 base address */
kadonotakashi 0:8fdf9a60065b 7282 #define I2C1_BASE (0x40067000u)
kadonotakashi 0:8fdf9a60065b 7283 /** Peripheral I2C1 base pointer */
kadonotakashi 0:8fdf9a60065b 7284 #define I2C1 ((I2C_Type *)I2C1_BASE)
kadonotakashi 0:8fdf9a60065b 7285 /** Peripheral I2C2 base address */
kadonotakashi 0:8fdf9a60065b 7286 #define I2C2_BASE (0x400E6000u)
kadonotakashi 0:8fdf9a60065b 7287 /** Peripheral I2C2 base pointer */
kadonotakashi 0:8fdf9a60065b 7288 #define I2C2 ((I2C_Type *)I2C2_BASE)
kadonotakashi 0:8fdf9a60065b 7289 /** Peripheral I2C3 base address */
kadonotakashi 0:8fdf9a60065b 7290 #define I2C3_BASE (0x400E7000u)
kadonotakashi 0:8fdf9a60065b 7291 /** Peripheral I2C3 base pointer */
kadonotakashi 0:8fdf9a60065b 7292 #define I2C3 ((I2C_Type *)I2C3_BASE)
kadonotakashi 0:8fdf9a60065b 7293 /** Array initializer of I2C peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 7294 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }
kadonotakashi 0:8fdf9a60065b 7295 /** Array initializer of I2C peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 7296 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3 }
kadonotakashi 0:8fdf9a60065b 7297 /** Interrupt vectors for the I2C peripheral type */
kadonotakashi 0:8fdf9a60065b 7298 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn }
kadonotakashi 0:8fdf9a60065b 7299
kadonotakashi 0:8fdf9a60065b 7300 /*!
kadonotakashi 0:8fdf9a60065b 7301 * @}
kadonotakashi 0:8fdf9a60065b 7302 */ /* end of group I2C_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 7303
kadonotakashi 0:8fdf9a60065b 7304
kadonotakashi 0:8fdf9a60065b 7305 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 7306 -- I2S Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 7307 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 7308
kadonotakashi 0:8fdf9a60065b 7309 /*!
kadonotakashi 0:8fdf9a60065b 7310 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 7311 * @{
kadonotakashi 0:8fdf9a60065b 7312 */
kadonotakashi 0:8fdf9a60065b 7313
kadonotakashi 0:8fdf9a60065b 7314 /** I2S - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 7315 typedef struct {
kadonotakashi 0:8fdf9a60065b 7316 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 7317 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 7318 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 7319 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 7320 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 7321 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 7322 uint8_t RESERVED_0[8];
kadonotakashi 0:8fdf9a60065b 7323 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 7324 uint8_t RESERVED_1[24];
kadonotakashi 0:8fdf9a60065b 7325 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 7326 uint8_t RESERVED_2[24];
kadonotakashi 0:8fdf9a60065b 7327 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
kadonotakashi 0:8fdf9a60065b 7328 uint8_t RESERVED_3[28];
kadonotakashi 0:8fdf9a60065b 7329 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
kadonotakashi 0:8fdf9a60065b 7330 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
kadonotakashi 0:8fdf9a60065b 7331 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
kadonotakashi 0:8fdf9a60065b 7332 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
kadonotakashi 0:8fdf9a60065b 7333 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
kadonotakashi 0:8fdf9a60065b 7334 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
kadonotakashi 0:8fdf9a60065b 7335 uint8_t RESERVED_4[8];
kadonotakashi 0:8fdf9a60065b 7336 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 7337 uint8_t RESERVED_5[24];
kadonotakashi 0:8fdf9a60065b 7338 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 7339 uint8_t RESERVED_6[24];
kadonotakashi 0:8fdf9a60065b 7340 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
kadonotakashi 0:8fdf9a60065b 7341 uint8_t RESERVED_7[28];
kadonotakashi 0:8fdf9a60065b 7342 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
kadonotakashi 0:8fdf9a60065b 7343 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
kadonotakashi 0:8fdf9a60065b 7344 } I2S_Type;
kadonotakashi 0:8fdf9a60065b 7345
kadonotakashi 0:8fdf9a60065b 7346 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 7347 -- I2S Register Masks
kadonotakashi 0:8fdf9a60065b 7348 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 7349
kadonotakashi 0:8fdf9a60065b 7350 /*!
kadonotakashi 0:8fdf9a60065b 7351 * @addtogroup I2S_Register_Masks I2S Register Masks
kadonotakashi 0:8fdf9a60065b 7352 * @{
kadonotakashi 0:8fdf9a60065b 7353 */
kadonotakashi 0:8fdf9a60065b 7354
kadonotakashi 0:8fdf9a60065b 7355 /*! @name TCSR - SAI Transmit Control Register */
kadonotakashi 0:8fdf9a60065b 7356 #define I2S_TCSR_FRDE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7357 #define I2S_TCSR_FRDE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7358 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
kadonotakashi 0:8fdf9a60065b 7359 #define I2S_TCSR_FWDE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7360 #define I2S_TCSR_FWDE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7361 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
kadonotakashi 0:8fdf9a60065b 7362 #define I2S_TCSR_FRIE_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 7363 #define I2S_TCSR_FRIE_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 7364 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
kadonotakashi 0:8fdf9a60065b 7365 #define I2S_TCSR_FWIE_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 7366 #define I2S_TCSR_FWIE_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 7367 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
kadonotakashi 0:8fdf9a60065b 7368 #define I2S_TCSR_FEIE_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 7369 #define I2S_TCSR_FEIE_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 7370 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
kadonotakashi 0:8fdf9a60065b 7371 #define I2S_TCSR_SEIE_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 7372 #define I2S_TCSR_SEIE_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 7373 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
kadonotakashi 0:8fdf9a60065b 7374 #define I2S_TCSR_WSIE_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 7375 #define I2S_TCSR_WSIE_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 7376 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
kadonotakashi 0:8fdf9a60065b 7377 #define I2S_TCSR_FRF_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 7378 #define I2S_TCSR_FRF_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 7379 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
kadonotakashi 0:8fdf9a60065b 7380 #define I2S_TCSR_FWF_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 7381 #define I2S_TCSR_FWF_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 7382 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
kadonotakashi 0:8fdf9a60065b 7383 #define I2S_TCSR_FEF_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 7384 #define I2S_TCSR_FEF_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 7385 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
kadonotakashi 0:8fdf9a60065b 7386 #define I2S_TCSR_SEF_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 7387 #define I2S_TCSR_SEF_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 7388 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
kadonotakashi 0:8fdf9a60065b 7389 #define I2S_TCSR_WSF_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 7390 #define I2S_TCSR_WSF_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 7391 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
kadonotakashi 0:8fdf9a60065b 7392 #define I2S_TCSR_SR_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 7393 #define I2S_TCSR_SR_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 7394 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
kadonotakashi 0:8fdf9a60065b 7395 #define I2S_TCSR_FR_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 7396 #define I2S_TCSR_FR_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 7397 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
kadonotakashi 0:8fdf9a60065b 7398 #define I2S_TCSR_BCE_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 7399 #define I2S_TCSR_BCE_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 7400 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
kadonotakashi 0:8fdf9a60065b 7401 #define I2S_TCSR_DBGE_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 7402 #define I2S_TCSR_DBGE_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 7403 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
kadonotakashi 0:8fdf9a60065b 7404 #define I2S_TCSR_STOPE_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 7405 #define I2S_TCSR_STOPE_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 7406 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
kadonotakashi 0:8fdf9a60065b 7407 #define I2S_TCSR_TE_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 7408 #define I2S_TCSR_TE_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 7409 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
kadonotakashi 0:8fdf9a60065b 7410
kadonotakashi 0:8fdf9a60065b 7411 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
kadonotakashi 0:8fdf9a60065b 7412 #define I2S_TCR1_TFW_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 7413 #define I2S_TCR1_TFW_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7414 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
kadonotakashi 0:8fdf9a60065b 7415
kadonotakashi 0:8fdf9a60065b 7416 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
kadonotakashi 0:8fdf9a60065b 7417 #define I2S_TCR2_DIV_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 7418 #define I2S_TCR2_DIV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7419 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
kadonotakashi 0:8fdf9a60065b 7420 #define I2S_TCR2_BCD_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 7421 #define I2S_TCR2_BCD_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 7422 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
kadonotakashi 0:8fdf9a60065b 7423 #define I2S_TCR2_BCP_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 7424 #define I2S_TCR2_BCP_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 7425 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
kadonotakashi 0:8fdf9a60065b 7426 #define I2S_TCR2_MSEL_MASK (0xC000000U)
kadonotakashi 0:8fdf9a60065b 7427 #define I2S_TCR2_MSEL_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 7428 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
kadonotakashi 0:8fdf9a60065b 7429 #define I2S_TCR2_BCI_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 7430 #define I2S_TCR2_BCI_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 7431 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
kadonotakashi 0:8fdf9a60065b 7432 #define I2S_TCR2_BCS_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 7433 #define I2S_TCR2_BCS_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 7434 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
kadonotakashi 0:8fdf9a60065b 7435 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
kadonotakashi 0:8fdf9a60065b 7436 #define I2S_TCR2_SYNC_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 7437 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
kadonotakashi 0:8fdf9a60065b 7438
kadonotakashi 0:8fdf9a60065b 7439 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
kadonotakashi 0:8fdf9a60065b 7440 #define I2S_TCR3_WDFL_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 7441 #define I2S_TCR3_WDFL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7442 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
kadonotakashi 0:8fdf9a60065b 7443 #define I2S_TCR3_TCE_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 7444 #define I2S_TCR3_TCE_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 7445 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
kadonotakashi 0:8fdf9a60065b 7446 #define I2S_TCR3_CFR_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 7447 #define I2S_TCR3_CFR_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 7448 #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
kadonotakashi 0:8fdf9a60065b 7449
kadonotakashi 0:8fdf9a60065b 7450 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
kadonotakashi 0:8fdf9a60065b 7451 #define I2S_TCR4_FSD_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7452 #define I2S_TCR4_FSD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7453 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
kadonotakashi 0:8fdf9a60065b 7454 #define I2S_TCR4_FSP_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7455 #define I2S_TCR4_FSP_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7456 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
kadonotakashi 0:8fdf9a60065b 7457 #define I2S_TCR4_ONDEM_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 7458 #define I2S_TCR4_ONDEM_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7459 #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
kadonotakashi 0:8fdf9a60065b 7460 #define I2S_TCR4_FSE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 7461 #define I2S_TCR4_FSE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 7462 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
kadonotakashi 0:8fdf9a60065b 7463 #define I2S_TCR4_MF_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7464 #define I2S_TCR4_MF_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7465 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
kadonotakashi 0:8fdf9a60065b 7466 #define I2S_TCR4_SYWD_MASK (0x1F00U)
kadonotakashi 0:8fdf9a60065b 7467 #define I2S_TCR4_SYWD_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 7468 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
kadonotakashi 0:8fdf9a60065b 7469 #define I2S_TCR4_FRSZ_MASK (0x1F0000U)
kadonotakashi 0:8fdf9a60065b 7470 #define I2S_TCR4_FRSZ_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 7471 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
kadonotakashi 0:8fdf9a60065b 7472 #define I2S_TCR4_FPACK_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 7473 #define I2S_TCR4_FPACK_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 7474 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
kadonotakashi 0:8fdf9a60065b 7475 #define I2S_TCR4_FCOMB_MASK (0xC000000U)
kadonotakashi 0:8fdf9a60065b 7476 #define I2S_TCR4_FCOMB_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 7477 #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
kadonotakashi 0:8fdf9a60065b 7478 #define I2S_TCR4_FCONT_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 7479 #define I2S_TCR4_FCONT_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 7480 #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
kadonotakashi 0:8fdf9a60065b 7481
kadonotakashi 0:8fdf9a60065b 7482 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
kadonotakashi 0:8fdf9a60065b 7483 #define I2S_TCR5_FBT_MASK (0x1F00U)
kadonotakashi 0:8fdf9a60065b 7484 #define I2S_TCR5_FBT_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 7485 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
kadonotakashi 0:8fdf9a60065b 7486 #define I2S_TCR5_W0W_MASK (0x1F0000U)
kadonotakashi 0:8fdf9a60065b 7487 #define I2S_TCR5_W0W_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 7488 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
kadonotakashi 0:8fdf9a60065b 7489 #define I2S_TCR5_WNW_MASK (0x1F000000U)
kadonotakashi 0:8fdf9a60065b 7490 #define I2S_TCR5_WNW_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 7491 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
kadonotakashi 0:8fdf9a60065b 7492
kadonotakashi 0:8fdf9a60065b 7493 /*! @name TDR - SAI Transmit Data Register */
kadonotakashi 0:8fdf9a60065b 7494 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 7495 #define I2S_TDR_TDR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7496 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
kadonotakashi 0:8fdf9a60065b 7497
kadonotakashi 0:8fdf9a60065b 7498 /* The count of I2S_TDR */
kadonotakashi 0:8fdf9a60065b 7499 #define I2S_TDR_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 7500
kadonotakashi 0:8fdf9a60065b 7501 /*! @name TFR - SAI Transmit FIFO Register */
kadonotakashi 0:8fdf9a60065b 7502 #define I2S_TFR_RFP_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 7503 #define I2S_TFR_RFP_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7504 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
kadonotakashi 0:8fdf9a60065b 7505 #define I2S_TFR_WFP_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 7506 #define I2S_TFR_WFP_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 7507 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
kadonotakashi 0:8fdf9a60065b 7508 #define I2S_TFR_WCP_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 7509 #define I2S_TFR_WCP_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 7510 #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
kadonotakashi 0:8fdf9a60065b 7511
kadonotakashi 0:8fdf9a60065b 7512 /* The count of I2S_TFR */
kadonotakashi 0:8fdf9a60065b 7513 #define I2S_TFR_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 7514
kadonotakashi 0:8fdf9a60065b 7515 /*! @name TMR - SAI Transmit Mask Register */
kadonotakashi 0:8fdf9a60065b 7516 #define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 7517 #define I2S_TMR_TWM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7518 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
kadonotakashi 0:8fdf9a60065b 7519
kadonotakashi 0:8fdf9a60065b 7520 /*! @name RCSR - SAI Receive Control Register */
kadonotakashi 0:8fdf9a60065b 7521 #define I2S_RCSR_FRDE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7522 #define I2S_RCSR_FRDE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7523 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
kadonotakashi 0:8fdf9a60065b 7524 #define I2S_RCSR_FWDE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7525 #define I2S_RCSR_FWDE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7526 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
kadonotakashi 0:8fdf9a60065b 7527 #define I2S_RCSR_FRIE_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 7528 #define I2S_RCSR_FRIE_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 7529 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
kadonotakashi 0:8fdf9a60065b 7530 #define I2S_RCSR_FWIE_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 7531 #define I2S_RCSR_FWIE_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 7532 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
kadonotakashi 0:8fdf9a60065b 7533 #define I2S_RCSR_FEIE_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 7534 #define I2S_RCSR_FEIE_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 7535 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
kadonotakashi 0:8fdf9a60065b 7536 #define I2S_RCSR_SEIE_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 7537 #define I2S_RCSR_SEIE_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 7538 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
kadonotakashi 0:8fdf9a60065b 7539 #define I2S_RCSR_WSIE_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 7540 #define I2S_RCSR_WSIE_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 7541 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
kadonotakashi 0:8fdf9a60065b 7542 #define I2S_RCSR_FRF_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 7543 #define I2S_RCSR_FRF_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 7544 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
kadonotakashi 0:8fdf9a60065b 7545 #define I2S_RCSR_FWF_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 7546 #define I2S_RCSR_FWF_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 7547 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
kadonotakashi 0:8fdf9a60065b 7548 #define I2S_RCSR_FEF_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 7549 #define I2S_RCSR_FEF_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 7550 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
kadonotakashi 0:8fdf9a60065b 7551 #define I2S_RCSR_SEF_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 7552 #define I2S_RCSR_SEF_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 7553 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
kadonotakashi 0:8fdf9a60065b 7554 #define I2S_RCSR_WSF_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 7555 #define I2S_RCSR_WSF_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 7556 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
kadonotakashi 0:8fdf9a60065b 7557 #define I2S_RCSR_SR_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 7558 #define I2S_RCSR_SR_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 7559 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
kadonotakashi 0:8fdf9a60065b 7560 #define I2S_RCSR_FR_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 7561 #define I2S_RCSR_FR_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 7562 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
kadonotakashi 0:8fdf9a60065b 7563 #define I2S_RCSR_BCE_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 7564 #define I2S_RCSR_BCE_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 7565 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
kadonotakashi 0:8fdf9a60065b 7566 #define I2S_RCSR_DBGE_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 7567 #define I2S_RCSR_DBGE_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 7568 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
kadonotakashi 0:8fdf9a60065b 7569 #define I2S_RCSR_STOPE_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 7570 #define I2S_RCSR_STOPE_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 7571 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
kadonotakashi 0:8fdf9a60065b 7572 #define I2S_RCSR_RE_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 7573 #define I2S_RCSR_RE_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 7574 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
kadonotakashi 0:8fdf9a60065b 7575
kadonotakashi 0:8fdf9a60065b 7576 /*! @name RCR1 - SAI Receive Configuration 1 Register */
kadonotakashi 0:8fdf9a60065b 7577 #define I2S_RCR1_RFW_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 7578 #define I2S_RCR1_RFW_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7579 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
kadonotakashi 0:8fdf9a60065b 7580
kadonotakashi 0:8fdf9a60065b 7581 /*! @name RCR2 - SAI Receive Configuration 2 Register */
kadonotakashi 0:8fdf9a60065b 7582 #define I2S_RCR2_DIV_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 7583 #define I2S_RCR2_DIV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7584 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
kadonotakashi 0:8fdf9a60065b 7585 #define I2S_RCR2_BCD_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 7586 #define I2S_RCR2_BCD_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 7587 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
kadonotakashi 0:8fdf9a60065b 7588 #define I2S_RCR2_BCP_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 7589 #define I2S_RCR2_BCP_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 7590 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
kadonotakashi 0:8fdf9a60065b 7591 #define I2S_RCR2_MSEL_MASK (0xC000000U)
kadonotakashi 0:8fdf9a60065b 7592 #define I2S_RCR2_MSEL_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 7593 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
kadonotakashi 0:8fdf9a60065b 7594 #define I2S_RCR2_BCI_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 7595 #define I2S_RCR2_BCI_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 7596 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
kadonotakashi 0:8fdf9a60065b 7597 #define I2S_RCR2_BCS_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 7598 #define I2S_RCR2_BCS_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 7599 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
kadonotakashi 0:8fdf9a60065b 7600 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
kadonotakashi 0:8fdf9a60065b 7601 #define I2S_RCR2_SYNC_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 7602 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
kadonotakashi 0:8fdf9a60065b 7603
kadonotakashi 0:8fdf9a60065b 7604 /*! @name RCR3 - SAI Receive Configuration 3 Register */
kadonotakashi 0:8fdf9a60065b 7605 #define I2S_RCR3_WDFL_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 7606 #define I2S_RCR3_WDFL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7607 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
kadonotakashi 0:8fdf9a60065b 7608 #define I2S_RCR3_RCE_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 7609 #define I2S_RCR3_RCE_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 7610 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
kadonotakashi 0:8fdf9a60065b 7611 #define I2S_RCR3_CFR_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 7612 #define I2S_RCR3_CFR_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 7613 #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
kadonotakashi 0:8fdf9a60065b 7614
kadonotakashi 0:8fdf9a60065b 7615 /*! @name RCR4 - SAI Receive Configuration 4 Register */
kadonotakashi 0:8fdf9a60065b 7616 #define I2S_RCR4_FSD_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7617 #define I2S_RCR4_FSD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7618 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
kadonotakashi 0:8fdf9a60065b 7619 #define I2S_RCR4_FSP_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7620 #define I2S_RCR4_FSP_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7621 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
kadonotakashi 0:8fdf9a60065b 7622 #define I2S_RCR4_ONDEM_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 7623 #define I2S_RCR4_ONDEM_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7624 #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
kadonotakashi 0:8fdf9a60065b 7625 #define I2S_RCR4_FSE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 7626 #define I2S_RCR4_FSE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 7627 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
kadonotakashi 0:8fdf9a60065b 7628 #define I2S_RCR4_MF_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7629 #define I2S_RCR4_MF_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7630 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
kadonotakashi 0:8fdf9a60065b 7631 #define I2S_RCR4_SYWD_MASK (0x1F00U)
kadonotakashi 0:8fdf9a60065b 7632 #define I2S_RCR4_SYWD_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 7633 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
kadonotakashi 0:8fdf9a60065b 7634 #define I2S_RCR4_FRSZ_MASK (0x1F0000U)
kadonotakashi 0:8fdf9a60065b 7635 #define I2S_RCR4_FRSZ_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 7636 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
kadonotakashi 0:8fdf9a60065b 7637 #define I2S_RCR4_FPACK_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 7638 #define I2S_RCR4_FPACK_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 7639 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
kadonotakashi 0:8fdf9a60065b 7640 #define I2S_RCR4_FCOMB_MASK (0xC000000U)
kadonotakashi 0:8fdf9a60065b 7641 #define I2S_RCR4_FCOMB_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 7642 #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
kadonotakashi 0:8fdf9a60065b 7643 #define I2S_RCR4_FCONT_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 7644 #define I2S_RCR4_FCONT_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 7645 #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
kadonotakashi 0:8fdf9a60065b 7646
kadonotakashi 0:8fdf9a60065b 7647 /*! @name RCR5 - SAI Receive Configuration 5 Register */
kadonotakashi 0:8fdf9a60065b 7648 #define I2S_RCR5_FBT_MASK (0x1F00U)
kadonotakashi 0:8fdf9a60065b 7649 #define I2S_RCR5_FBT_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 7650 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
kadonotakashi 0:8fdf9a60065b 7651 #define I2S_RCR5_W0W_MASK (0x1F0000U)
kadonotakashi 0:8fdf9a60065b 7652 #define I2S_RCR5_W0W_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 7653 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
kadonotakashi 0:8fdf9a60065b 7654 #define I2S_RCR5_WNW_MASK (0x1F000000U)
kadonotakashi 0:8fdf9a60065b 7655 #define I2S_RCR5_WNW_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 7656 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
kadonotakashi 0:8fdf9a60065b 7657
kadonotakashi 0:8fdf9a60065b 7658 /*! @name RDR - SAI Receive Data Register */
kadonotakashi 0:8fdf9a60065b 7659 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 7660 #define I2S_RDR_RDR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7661 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
kadonotakashi 0:8fdf9a60065b 7662
kadonotakashi 0:8fdf9a60065b 7663 /* The count of I2S_RDR */
kadonotakashi 0:8fdf9a60065b 7664 #define I2S_RDR_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 7665
kadonotakashi 0:8fdf9a60065b 7666 /*! @name RFR - SAI Receive FIFO Register */
kadonotakashi 0:8fdf9a60065b 7667 #define I2S_RFR_RFP_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 7668 #define I2S_RFR_RFP_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7669 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
kadonotakashi 0:8fdf9a60065b 7670 #define I2S_RFR_RCP_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 7671 #define I2S_RFR_RCP_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 7672 #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
kadonotakashi 0:8fdf9a60065b 7673 #define I2S_RFR_WFP_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 7674 #define I2S_RFR_WFP_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 7675 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
kadonotakashi 0:8fdf9a60065b 7676
kadonotakashi 0:8fdf9a60065b 7677 /* The count of I2S_RFR */
kadonotakashi 0:8fdf9a60065b 7678 #define I2S_RFR_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 7679
kadonotakashi 0:8fdf9a60065b 7680 /*! @name RMR - SAI Receive Mask Register */
kadonotakashi 0:8fdf9a60065b 7681 #define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 7682 #define I2S_RMR_RWM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7683 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
kadonotakashi 0:8fdf9a60065b 7684
kadonotakashi 0:8fdf9a60065b 7685 /*! @name MCR - SAI MCLK Control Register */
kadonotakashi 0:8fdf9a60065b 7686 #define I2S_MCR_MICS_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 7687 #define I2S_MCR_MICS_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 7688 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
kadonotakashi 0:8fdf9a60065b 7689 #define I2S_MCR_MOE_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 7690 #define I2S_MCR_MOE_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 7691 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
kadonotakashi 0:8fdf9a60065b 7692 #define I2S_MCR_DUF_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 7693 #define I2S_MCR_DUF_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 7694 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
kadonotakashi 0:8fdf9a60065b 7695
kadonotakashi 0:8fdf9a60065b 7696 /*! @name MDR - SAI MCLK Divide Register */
kadonotakashi 0:8fdf9a60065b 7697 #define I2S_MDR_DIVIDE_MASK (0xFFFU)
kadonotakashi 0:8fdf9a60065b 7698 #define I2S_MDR_DIVIDE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7699 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
kadonotakashi 0:8fdf9a60065b 7700 #define I2S_MDR_FRACT_MASK (0xFF000U)
kadonotakashi 0:8fdf9a60065b 7701 #define I2S_MDR_FRACT_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 7702 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
kadonotakashi 0:8fdf9a60065b 7703
kadonotakashi 0:8fdf9a60065b 7704
kadonotakashi 0:8fdf9a60065b 7705 /*!
kadonotakashi 0:8fdf9a60065b 7706 * @}
kadonotakashi 0:8fdf9a60065b 7707 */ /* end of group I2S_Register_Masks */
kadonotakashi 0:8fdf9a60065b 7708
kadonotakashi 0:8fdf9a60065b 7709
kadonotakashi 0:8fdf9a60065b 7710 /* I2S - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 7711 /** Peripheral I2S0 base address */
kadonotakashi 0:8fdf9a60065b 7712 #define I2S0_BASE (0x4002F000u)
kadonotakashi 0:8fdf9a60065b 7713 /** Peripheral I2S0 base pointer */
kadonotakashi 0:8fdf9a60065b 7714 #define I2S0 ((I2S_Type *)I2S0_BASE)
kadonotakashi 0:8fdf9a60065b 7715 /** Array initializer of I2S peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 7716 #define I2S_BASE_ADDRS { I2S0_BASE }
kadonotakashi 0:8fdf9a60065b 7717 /** Array initializer of I2S peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 7718 #define I2S_BASE_PTRS { I2S0 }
kadonotakashi 0:8fdf9a60065b 7719 /** Interrupt vectors for the I2S peripheral type */
kadonotakashi 0:8fdf9a60065b 7720 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
kadonotakashi 0:8fdf9a60065b 7721 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
kadonotakashi 0:8fdf9a60065b 7722
kadonotakashi 0:8fdf9a60065b 7723 /*!
kadonotakashi 0:8fdf9a60065b 7724 * @}
kadonotakashi 0:8fdf9a60065b 7725 */ /* end of group I2S_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 7726
kadonotakashi 0:8fdf9a60065b 7727
kadonotakashi 0:8fdf9a60065b 7728 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 7729 -- LLWU Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 7730 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 7731
kadonotakashi 0:8fdf9a60065b 7732 /*!
kadonotakashi 0:8fdf9a60065b 7733 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 7734 * @{
kadonotakashi 0:8fdf9a60065b 7735 */
kadonotakashi 0:8fdf9a60065b 7736
kadonotakashi 0:8fdf9a60065b 7737 /** LLWU - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 7738 typedef struct {
kadonotakashi 0:8fdf9a60065b 7739 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 7740 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 7741 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 7742 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
kadonotakashi 0:8fdf9a60065b 7743 __IO uint8_t PE5; /**< LLWU Pin Enable 5 register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 7744 __IO uint8_t PE6; /**< LLWU Pin Enable 6 register, offset: 0x5 */
kadonotakashi 0:8fdf9a60065b 7745 __IO uint8_t PE7; /**< LLWU Pin Enable 7 register, offset: 0x6 */
kadonotakashi 0:8fdf9a60065b 7746 __IO uint8_t PE8; /**< LLWU Pin Enable 8 register, offset: 0x7 */
kadonotakashi 0:8fdf9a60065b 7747 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 7748 __IO uint8_t PF1; /**< LLWU Pin Flag 1 register, offset: 0x9 */
kadonotakashi 0:8fdf9a60065b 7749 __IO uint8_t PF2; /**< LLWU Pin Flag 2 register, offset: 0xA */
kadonotakashi 0:8fdf9a60065b 7750 __IO uint8_t PF3; /**< LLWU Pin Flag 3 register, offset: 0xB */
kadonotakashi 0:8fdf9a60065b 7751 __IO uint8_t PF4; /**< LLWU Pin Flag 4 register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 7752 __I uint8_t MF5; /**< LLWU Module Flag 5 register, offset: 0xD */
kadonotakashi 0:8fdf9a60065b 7753 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0xE */
kadonotakashi 0:8fdf9a60065b 7754 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0xF */
kadonotakashi 0:8fdf9a60065b 7755 __IO uint8_t FILT3; /**< LLWU Pin Filter 3 register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 7756 __IO uint8_t FILT4; /**< LLWU Pin Filter 4 register, offset: 0x11 */
kadonotakashi 0:8fdf9a60065b 7757 } LLWU_Type;
kadonotakashi 0:8fdf9a60065b 7758
kadonotakashi 0:8fdf9a60065b 7759 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 7760 -- LLWU Register Masks
kadonotakashi 0:8fdf9a60065b 7761 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 7762
kadonotakashi 0:8fdf9a60065b 7763 /*!
kadonotakashi 0:8fdf9a60065b 7764 * @addtogroup LLWU_Register_Masks LLWU Register Masks
kadonotakashi 0:8fdf9a60065b 7765 * @{
kadonotakashi 0:8fdf9a60065b 7766 */
kadonotakashi 0:8fdf9a60065b 7767
kadonotakashi 0:8fdf9a60065b 7768 /*! @name PE1 - LLWU Pin Enable 1 register */
kadonotakashi 0:8fdf9a60065b 7769 #define LLWU_PE1_WUPE0_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 7770 #define LLWU_PE1_WUPE0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7771 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
kadonotakashi 0:8fdf9a60065b 7772 #define LLWU_PE1_WUPE1_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 7773 #define LLWU_PE1_WUPE1_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7774 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
kadonotakashi 0:8fdf9a60065b 7775 #define LLWU_PE1_WUPE2_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 7776 #define LLWU_PE1_WUPE2_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7777 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
kadonotakashi 0:8fdf9a60065b 7778 #define LLWU_PE1_WUPE3_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 7779 #define LLWU_PE1_WUPE3_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7780 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
kadonotakashi 0:8fdf9a60065b 7781
kadonotakashi 0:8fdf9a60065b 7782 /*! @name PE2 - LLWU Pin Enable 2 register */
kadonotakashi 0:8fdf9a60065b 7783 #define LLWU_PE2_WUPE4_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 7784 #define LLWU_PE2_WUPE4_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7785 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
kadonotakashi 0:8fdf9a60065b 7786 #define LLWU_PE2_WUPE5_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 7787 #define LLWU_PE2_WUPE5_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7788 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
kadonotakashi 0:8fdf9a60065b 7789 #define LLWU_PE2_WUPE6_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 7790 #define LLWU_PE2_WUPE6_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7791 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
kadonotakashi 0:8fdf9a60065b 7792 #define LLWU_PE2_WUPE7_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 7793 #define LLWU_PE2_WUPE7_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7794 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
kadonotakashi 0:8fdf9a60065b 7795
kadonotakashi 0:8fdf9a60065b 7796 /*! @name PE3 - LLWU Pin Enable 3 register */
kadonotakashi 0:8fdf9a60065b 7797 #define LLWU_PE3_WUPE8_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 7798 #define LLWU_PE3_WUPE8_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7799 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
kadonotakashi 0:8fdf9a60065b 7800 #define LLWU_PE3_WUPE9_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 7801 #define LLWU_PE3_WUPE9_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7802 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
kadonotakashi 0:8fdf9a60065b 7803 #define LLWU_PE3_WUPE10_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 7804 #define LLWU_PE3_WUPE10_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7805 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
kadonotakashi 0:8fdf9a60065b 7806 #define LLWU_PE3_WUPE11_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 7807 #define LLWU_PE3_WUPE11_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7808 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
kadonotakashi 0:8fdf9a60065b 7809
kadonotakashi 0:8fdf9a60065b 7810 /*! @name PE4 - LLWU Pin Enable 4 register */
kadonotakashi 0:8fdf9a60065b 7811 #define LLWU_PE4_WUPE12_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 7812 #define LLWU_PE4_WUPE12_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7813 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
kadonotakashi 0:8fdf9a60065b 7814 #define LLWU_PE4_WUPE13_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 7815 #define LLWU_PE4_WUPE13_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7816 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
kadonotakashi 0:8fdf9a60065b 7817 #define LLWU_PE4_WUPE14_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 7818 #define LLWU_PE4_WUPE14_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7819 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
kadonotakashi 0:8fdf9a60065b 7820 #define LLWU_PE4_WUPE15_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 7821 #define LLWU_PE4_WUPE15_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7822 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
kadonotakashi 0:8fdf9a60065b 7823
kadonotakashi 0:8fdf9a60065b 7824 /*! @name PE5 - LLWU Pin Enable 5 register */
kadonotakashi 0:8fdf9a60065b 7825 #define LLWU_PE5_WUPE16_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 7826 #define LLWU_PE5_WUPE16_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7827 #define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
kadonotakashi 0:8fdf9a60065b 7828 #define LLWU_PE5_WUPE17_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 7829 #define LLWU_PE5_WUPE17_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7830 #define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
kadonotakashi 0:8fdf9a60065b 7831 #define LLWU_PE5_WUPE18_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 7832 #define LLWU_PE5_WUPE18_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7833 #define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
kadonotakashi 0:8fdf9a60065b 7834 #define LLWU_PE5_WUPE19_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 7835 #define LLWU_PE5_WUPE19_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7836 #define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
kadonotakashi 0:8fdf9a60065b 7837
kadonotakashi 0:8fdf9a60065b 7838 /*! @name PE6 - LLWU Pin Enable 6 register */
kadonotakashi 0:8fdf9a60065b 7839 #define LLWU_PE6_WUPE20_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 7840 #define LLWU_PE6_WUPE20_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7841 #define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
kadonotakashi 0:8fdf9a60065b 7842 #define LLWU_PE6_WUPE21_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 7843 #define LLWU_PE6_WUPE21_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7844 #define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
kadonotakashi 0:8fdf9a60065b 7845 #define LLWU_PE6_WUPE22_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 7846 #define LLWU_PE6_WUPE22_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7847 #define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
kadonotakashi 0:8fdf9a60065b 7848 #define LLWU_PE6_WUPE23_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 7849 #define LLWU_PE6_WUPE23_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7850 #define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
kadonotakashi 0:8fdf9a60065b 7851
kadonotakashi 0:8fdf9a60065b 7852 /*! @name PE7 - LLWU Pin Enable 7 register */
kadonotakashi 0:8fdf9a60065b 7853 #define LLWU_PE7_WUPE24_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 7854 #define LLWU_PE7_WUPE24_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7855 #define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
kadonotakashi 0:8fdf9a60065b 7856 #define LLWU_PE7_WUPE25_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 7857 #define LLWU_PE7_WUPE25_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7858 #define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
kadonotakashi 0:8fdf9a60065b 7859 #define LLWU_PE7_WUPE26_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 7860 #define LLWU_PE7_WUPE26_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7861 #define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
kadonotakashi 0:8fdf9a60065b 7862 #define LLWU_PE7_WUPE27_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 7863 #define LLWU_PE7_WUPE27_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7864 #define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
kadonotakashi 0:8fdf9a60065b 7865
kadonotakashi 0:8fdf9a60065b 7866 /*! @name PE8 - LLWU Pin Enable 8 register */
kadonotakashi 0:8fdf9a60065b 7867 #define LLWU_PE8_WUPE28_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 7868 #define LLWU_PE8_WUPE28_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7869 #define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
kadonotakashi 0:8fdf9a60065b 7870 #define LLWU_PE8_WUPE29_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 7871 #define LLWU_PE8_WUPE29_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7872 #define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
kadonotakashi 0:8fdf9a60065b 7873 #define LLWU_PE8_WUPE30_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 7874 #define LLWU_PE8_WUPE30_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7875 #define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
kadonotakashi 0:8fdf9a60065b 7876 #define LLWU_PE8_WUPE31_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 7877 #define LLWU_PE8_WUPE31_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7878 #define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
kadonotakashi 0:8fdf9a60065b 7879
kadonotakashi 0:8fdf9a60065b 7880 /*! @name ME - LLWU Module Enable register */
kadonotakashi 0:8fdf9a60065b 7881 #define LLWU_ME_WUME0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7882 #define LLWU_ME_WUME0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7883 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
kadonotakashi 0:8fdf9a60065b 7884 #define LLWU_ME_WUME1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7885 #define LLWU_ME_WUME1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7886 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
kadonotakashi 0:8fdf9a60065b 7887 #define LLWU_ME_WUME2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 7888 #define LLWU_ME_WUME2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7889 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
kadonotakashi 0:8fdf9a60065b 7890 #define LLWU_ME_WUME3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 7891 #define LLWU_ME_WUME3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 7892 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
kadonotakashi 0:8fdf9a60065b 7893 #define LLWU_ME_WUME4_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7894 #define LLWU_ME_WUME4_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7895 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
kadonotakashi 0:8fdf9a60065b 7896 #define LLWU_ME_WUME5_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 7897 #define LLWU_ME_WUME5_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 7898 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
kadonotakashi 0:8fdf9a60065b 7899 #define LLWU_ME_WUME6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 7900 #define LLWU_ME_WUME6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7901 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
kadonotakashi 0:8fdf9a60065b 7902 #define LLWU_ME_WUME7_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 7903 #define LLWU_ME_WUME7_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 7904 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
kadonotakashi 0:8fdf9a60065b 7905
kadonotakashi 0:8fdf9a60065b 7906 /*! @name PF1 - LLWU Pin Flag 1 register */
kadonotakashi 0:8fdf9a60065b 7907 #define LLWU_PF1_WUF0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7908 #define LLWU_PF1_WUF0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7909 #define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
kadonotakashi 0:8fdf9a60065b 7910 #define LLWU_PF1_WUF1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7911 #define LLWU_PF1_WUF1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7912 #define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
kadonotakashi 0:8fdf9a60065b 7913 #define LLWU_PF1_WUF2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 7914 #define LLWU_PF1_WUF2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7915 #define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
kadonotakashi 0:8fdf9a60065b 7916 #define LLWU_PF1_WUF3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 7917 #define LLWU_PF1_WUF3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 7918 #define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
kadonotakashi 0:8fdf9a60065b 7919 #define LLWU_PF1_WUF4_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7920 #define LLWU_PF1_WUF4_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7921 #define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
kadonotakashi 0:8fdf9a60065b 7922 #define LLWU_PF1_WUF5_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 7923 #define LLWU_PF1_WUF5_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 7924 #define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
kadonotakashi 0:8fdf9a60065b 7925 #define LLWU_PF1_WUF6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 7926 #define LLWU_PF1_WUF6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7927 #define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
kadonotakashi 0:8fdf9a60065b 7928 #define LLWU_PF1_WUF7_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 7929 #define LLWU_PF1_WUF7_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 7930 #define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
kadonotakashi 0:8fdf9a60065b 7931
kadonotakashi 0:8fdf9a60065b 7932 /*! @name PF2 - LLWU Pin Flag 2 register */
kadonotakashi 0:8fdf9a60065b 7933 #define LLWU_PF2_WUF8_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7934 #define LLWU_PF2_WUF8_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7935 #define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
kadonotakashi 0:8fdf9a60065b 7936 #define LLWU_PF2_WUF9_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7937 #define LLWU_PF2_WUF9_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7938 #define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
kadonotakashi 0:8fdf9a60065b 7939 #define LLWU_PF2_WUF10_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 7940 #define LLWU_PF2_WUF10_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7941 #define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
kadonotakashi 0:8fdf9a60065b 7942 #define LLWU_PF2_WUF11_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 7943 #define LLWU_PF2_WUF11_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 7944 #define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
kadonotakashi 0:8fdf9a60065b 7945 #define LLWU_PF2_WUF12_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7946 #define LLWU_PF2_WUF12_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7947 #define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
kadonotakashi 0:8fdf9a60065b 7948 #define LLWU_PF2_WUF13_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 7949 #define LLWU_PF2_WUF13_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 7950 #define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
kadonotakashi 0:8fdf9a60065b 7951 #define LLWU_PF2_WUF14_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 7952 #define LLWU_PF2_WUF14_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7953 #define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
kadonotakashi 0:8fdf9a60065b 7954 #define LLWU_PF2_WUF15_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 7955 #define LLWU_PF2_WUF15_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 7956 #define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
kadonotakashi 0:8fdf9a60065b 7957
kadonotakashi 0:8fdf9a60065b 7958 /*! @name PF3 - LLWU Pin Flag 3 register */
kadonotakashi 0:8fdf9a60065b 7959 #define LLWU_PF3_WUF16_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7960 #define LLWU_PF3_WUF16_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7961 #define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
kadonotakashi 0:8fdf9a60065b 7962 #define LLWU_PF3_WUF17_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7963 #define LLWU_PF3_WUF17_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7964 #define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
kadonotakashi 0:8fdf9a60065b 7965 #define LLWU_PF3_WUF18_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 7966 #define LLWU_PF3_WUF18_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7967 #define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
kadonotakashi 0:8fdf9a60065b 7968 #define LLWU_PF3_WUF19_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 7969 #define LLWU_PF3_WUF19_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 7970 #define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
kadonotakashi 0:8fdf9a60065b 7971 #define LLWU_PF3_WUF20_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7972 #define LLWU_PF3_WUF20_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7973 #define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
kadonotakashi 0:8fdf9a60065b 7974 #define LLWU_PF3_WUF21_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 7975 #define LLWU_PF3_WUF21_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 7976 #define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
kadonotakashi 0:8fdf9a60065b 7977 #define LLWU_PF3_WUF22_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 7978 #define LLWU_PF3_WUF22_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 7979 #define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
kadonotakashi 0:8fdf9a60065b 7980 #define LLWU_PF3_WUF23_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 7981 #define LLWU_PF3_WUF23_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 7982 #define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
kadonotakashi 0:8fdf9a60065b 7983
kadonotakashi 0:8fdf9a60065b 7984 /*! @name PF4 - LLWU Pin Flag 4 register */
kadonotakashi 0:8fdf9a60065b 7985 #define LLWU_PF4_WUF24_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 7986 #define LLWU_PF4_WUF24_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 7987 #define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
kadonotakashi 0:8fdf9a60065b 7988 #define LLWU_PF4_WUF25_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 7989 #define LLWU_PF4_WUF25_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 7990 #define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
kadonotakashi 0:8fdf9a60065b 7991 #define LLWU_PF4_WUF26_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 7992 #define LLWU_PF4_WUF26_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 7993 #define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
kadonotakashi 0:8fdf9a60065b 7994 #define LLWU_PF4_WUF27_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 7995 #define LLWU_PF4_WUF27_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 7996 #define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
kadonotakashi 0:8fdf9a60065b 7997 #define LLWU_PF4_WUF28_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 7998 #define LLWU_PF4_WUF28_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 7999 #define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
kadonotakashi 0:8fdf9a60065b 8000 #define LLWU_PF4_WUF29_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 8001 #define LLWU_PF4_WUF29_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 8002 #define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
kadonotakashi 0:8fdf9a60065b 8003 #define LLWU_PF4_WUF30_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 8004 #define LLWU_PF4_WUF30_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 8005 #define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
kadonotakashi 0:8fdf9a60065b 8006 #define LLWU_PF4_WUF31_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 8007 #define LLWU_PF4_WUF31_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 8008 #define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
kadonotakashi 0:8fdf9a60065b 8009
kadonotakashi 0:8fdf9a60065b 8010 /*! @name MF5 - LLWU Module Flag 5 register */
kadonotakashi 0:8fdf9a60065b 8011 #define LLWU_MF5_MWUF0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8012 #define LLWU_MF5_MWUF0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8013 #define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
kadonotakashi 0:8fdf9a60065b 8014 #define LLWU_MF5_MWUF1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 8015 #define LLWU_MF5_MWUF1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 8016 #define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
kadonotakashi 0:8fdf9a60065b 8017 #define LLWU_MF5_MWUF2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 8018 #define LLWU_MF5_MWUF2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8019 #define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
kadonotakashi 0:8fdf9a60065b 8020 #define LLWU_MF5_MWUF3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 8021 #define LLWU_MF5_MWUF3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 8022 #define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
kadonotakashi 0:8fdf9a60065b 8023 #define LLWU_MF5_MWUF4_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 8024 #define LLWU_MF5_MWUF4_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 8025 #define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
kadonotakashi 0:8fdf9a60065b 8026 #define LLWU_MF5_MWUF5_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 8027 #define LLWU_MF5_MWUF5_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 8028 #define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
kadonotakashi 0:8fdf9a60065b 8029 #define LLWU_MF5_MWUF6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 8030 #define LLWU_MF5_MWUF6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 8031 #define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
kadonotakashi 0:8fdf9a60065b 8032 #define LLWU_MF5_MWUF7_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 8033 #define LLWU_MF5_MWUF7_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 8034 #define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
kadonotakashi 0:8fdf9a60065b 8035
kadonotakashi 0:8fdf9a60065b 8036 /*! @name FILT1 - LLWU Pin Filter 1 register */
kadonotakashi 0:8fdf9a60065b 8037 #define LLWU_FILT1_FILTSEL_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 8038 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8039 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
kadonotakashi 0:8fdf9a60065b 8040 #define LLWU_FILT1_FILTE_MASK (0x60U)
kadonotakashi 0:8fdf9a60065b 8041 #define LLWU_FILT1_FILTE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 8042 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
kadonotakashi 0:8fdf9a60065b 8043 #define LLWU_FILT1_FILTF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 8044 #define LLWU_FILT1_FILTF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 8045 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
kadonotakashi 0:8fdf9a60065b 8046
kadonotakashi 0:8fdf9a60065b 8047 /*! @name FILT2 - LLWU Pin Filter 2 register */
kadonotakashi 0:8fdf9a60065b 8048 #define LLWU_FILT2_FILTSEL_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 8049 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8050 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
kadonotakashi 0:8fdf9a60065b 8051 #define LLWU_FILT2_FILTE_MASK (0x60U)
kadonotakashi 0:8fdf9a60065b 8052 #define LLWU_FILT2_FILTE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 8053 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
kadonotakashi 0:8fdf9a60065b 8054 #define LLWU_FILT2_FILTF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 8055 #define LLWU_FILT2_FILTF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 8056 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
kadonotakashi 0:8fdf9a60065b 8057
kadonotakashi 0:8fdf9a60065b 8058 /*! @name FILT3 - LLWU Pin Filter 3 register */
kadonotakashi 0:8fdf9a60065b 8059 #define LLWU_FILT3_FILTSEL_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 8060 #define LLWU_FILT3_FILTSEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8061 #define LLWU_FILT3_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK)
kadonotakashi 0:8fdf9a60065b 8062 #define LLWU_FILT3_FILTE_MASK (0x60U)
kadonotakashi 0:8fdf9a60065b 8063 #define LLWU_FILT3_FILTE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 8064 #define LLWU_FILT3_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK)
kadonotakashi 0:8fdf9a60065b 8065 #define LLWU_FILT3_FILTF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 8066 #define LLWU_FILT3_FILTF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 8067 #define LLWU_FILT3_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK)
kadonotakashi 0:8fdf9a60065b 8068
kadonotakashi 0:8fdf9a60065b 8069 /*! @name FILT4 - LLWU Pin Filter 4 register */
kadonotakashi 0:8fdf9a60065b 8070 #define LLWU_FILT4_FILTSEL_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 8071 #define LLWU_FILT4_FILTSEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8072 #define LLWU_FILT4_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK)
kadonotakashi 0:8fdf9a60065b 8073 #define LLWU_FILT4_FILTE_MASK (0x60U)
kadonotakashi 0:8fdf9a60065b 8074 #define LLWU_FILT4_FILTE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 8075 #define LLWU_FILT4_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK)
kadonotakashi 0:8fdf9a60065b 8076 #define LLWU_FILT4_FILTF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 8077 #define LLWU_FILT4_FILTF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 8078 #define LLWU_FILT4_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK)
kadonotakashi 0:8fdf9a60065b 8079
kadonotakashi 0:8fdf9a60065b 8080
kadonotakashi 0:8fdf9a60065b 8081 /*!
kadonotakashi 0:8fdf9a60065b 8082 * @}
kadonotakashi 0:8fdf9a60065b 8083 */ /* end of group LLWU_Register_Masks */
kadonotakashi 0:8fdf9a60065b 8084
kadonotakashi 0:8fdf9a60065b 8085
kadonotakashi 0:8fdf9a60065b 8086 /* LLWU - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 8087 /** Peripheral LLWU base address */
kadonotakashi 0:8fdf9a60065b 8088 #define LLWU_BASE (0x4007C000u)
kadonotakashi 0:8fdf9a60065b 8089 /** Peripheral LLWU base pointer */
kadonotakashi 0:8fdf9a60065b 8090 #define LLWU ((LLWU_Type *)LLWU_BASE)
kadonotakashi 0:8fdf9a60065b 8091 /** Array initializer of LLWU peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 8092 #define LLWU_BASE_ADDRS { LLWU_BASE }
kadonotakashi 0:8fdf9a60065b 8093 /** Array initializer of LLWU peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 8094 #define LLWU_BASE_PTRS { LLWU }
kadonotakashi 0:8fdf9a60065b 8095 /** Interrupt vectors for the LLWU peripheral type */
kadonotakashi 0:8fdf9a60065b 8096 #define LLWU_IRQS { LLWU_IRQn }
kadonotakashi 0:8fdf9a60065b 8097
kadonotakashi 0:8fdf9a60065b 8098 /*!
kadonotakashi 0:8fdf9a60065b 8099 * @}
kadonotakashi 0:8fdf9a60065b 8100 */ /* end of group LLWU_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 8101
kadonotakashi 0:8fdf9a60065b 8102
kadonotakashi 0:8fdf9a60065b 8103 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 8104 -- LMEM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 8105 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 8106
kadonotakashi 0:8fdf9a60065b 8107 /*!
kadonotakashi 0:8fdf9a60065b 8108 * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 8109 * @{
kadonotakashi 0:8fdf9a60065b 8110 */
kadonotakashi 0:8fdf9a60065b 8111
kadonotakashi 0:8fdf9a60065b 8112 /** LMEM - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 8113 typedef struct {
kadonotakashi 0:8fdf9a60065b 8114 __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 8115 __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 8116 __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 8117 __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 8118 uint8_t RESERVED_0[16];
kadonotakashi 0:8fdf9a60065b 8119 __IO uint32_t PCCRMR; /**< Cache regions mode register, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 8120 uint8_t RESERVED_1[2012];
kadonotakashi 0:8fdf9a60065b 8121 __IO uint32_t PSCCR; /**< Cache control register, offset: 0x800 */
kadonotakashi 0:8fdf9a60065b 8122 __IO uint32_t PSCLCR; /**< Cache line control register, offset: 0x804 */
kadonotakashi 0:8fdf9a60065b 8123 __IO uint32_t PSCSAR; /**< Cache search address register, offset: 0x808 */
kadonotakashi 0:8fdf9a60065b 8124 __IO uint32_t PSCCVR; /**< Cache read/write value register, offset: 0x80C */
kadonotakashi 0:8fdf9a60065b 8125 uint8_t RESERVED_2[16];
kadonotakashi 0:8fdf9a60065b 8126 __IO uint32_t PSCRMR; /**< Cache regions mode register, offset: 0x820 */
kadonotakashi 0:8fdf9a60065b 8127 } LMEM_Type;
kadonotakashi 0:8fdf9a60065b 8128
kadonotakashi 0:8fdf9a60065b 8129 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 8130 -- LMEM Register Masks
kadonotakashi 0:8fdf9a60065b 8131 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 8132
kadonotakashi 0:8fdf9a60065b 8133 /*!
kadonotakashi 0:8fdf9a60065b 8134 * @addtogroup LMEM_Register_Masks LMEM Register Masks
kadonotakashi 0:8fdf9a60065b 8135 * @{
kadonotakashi 0:8fdf9a60065b 8136 */
kadonotakashi 0:8fdf9a60065b 8137
kadonotakashi 0:8fdf9a60065b 8138 /*! @name PCCCR - Cache control register */
kadonotakashi 0:8fdf9a60065b 8139 #define LMEM_PCCCR_ENCACHE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8140 #define LMEM_PCCCR_ENCACHE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8141 #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
kadonotakashi 0:8fdf9a60065b 8142 #define LMEM_PCCCR_ENWRBUF_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 8143 #define LMEM_PCCCR_ENWRBUF_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 8144 #define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
kadonotakashi 0:8fdf9a60065b 8145 #define LMEM_PCCCR_PCCR2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 8146 #define LMEM_PCCCR_PCCR2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8147 #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
kadonotakashi 0:8fdf9a60065b 8148 #define LMEM_PCCCR_PCCR3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 8149 #define LMEM_PCCCR_PCCR3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 8150 #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
kadonotakashi 0:8fdf9a60065b 8151 #define LMEM_PCCCR_INVW0_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 8152 #define LMEM_PCCCR_INVW0_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 8153 #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
kadonotakashi 0:8fdf9a60065b 8154 #define LMEM_PCCCR_PUSHW0_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 8155 #define LMEM_PCCCR_PUSHW0_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 8156 #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
kadonotakashi 0:8fdf9a60065b 8157 #define LMEM_PCCCR_INVW1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 8158 #define LMEM_PCCCR_INVW1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 8159 #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
kadonotakashi 0:8fdf9a60065b 8160 #define LMEM_PCCCR_PUSHW1_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 8161 #define LMEM_PCCCR_PUSHW1_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 8162 #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
kadonotakashi 0:8fdf9a60065b 8163 #define LMEM_PCCCR_GO_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 8164 #define LMEM_PCCCR_GO_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 8165 #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
kadonotakashi 0:8fdf9a60065b 8166
kadonotakashi 0:8fdf9a60065b 8167 /*! @name PCCLCR - Cache line control register */
kadonotakashi 0:8fdf9a60065b 8168 #define LMEM_PCCLCR_LGO_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8169 #define LMEM_PCCLCR_LGO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8170 #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
kadonotakashi 0:8fdf9a60065b 8171 #define LMEM_PCCLCR_CACHEADDR_MASK (0xFFCU)
kadonotakashi 0:8fdf9a60065b 8172 #define LMEM_PCCLCR_CACHEADDR_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8173 #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
kadonotakashi 0:8fdf9a60065b 8174 #define LMEM_PCCLCR_WSEL_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 8175 #define LMEM_PCCLCR_WSEL_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 8176 #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
kadonotakashi 0:8fdf9a60065b 8177 #define LMEM_PCCLCR_TDSEL_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 8178 #define LMEM_PCCLCR_TDSEL_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 8179 #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
kadonotakashi 0:8fdf9a60065b 8180 #define LMEM_PCCLCR_LCIVB_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 8181 #define LMEM_PCCLCR_LCIVB_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 8182 #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
kadonotakashi 0:8fdf9a60065b 8183 #define LMEM_PCCLCR_LCIMB_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 8184 #define LMEM_PCCLCR_LCIMB_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 8185 #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
kadonotakashi 0:8fdf9a60065b 8186 #define LMEM_PCCLCR_LCWAY_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 8187 #define LMEM_PCCLCR_LCWAY_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 8188 #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
kadonotakashi 0:8fdf9a60065b 8189 #define LMEM_PCCLCR_LCMD_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 8190 #define LMEM_PCCLCR_LCMD_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 8191 #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
kadonotakashi 0:8fdf9a60065b 8192 #define LMEM_PCCLCR_LADSEL_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 8193 #define LMEM_PCCLCR_LADSEL_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 8194 #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
kadonotakashi 0:8fdf9a60065b 8195 #define LMEM_PCCLCR_LACC_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 8196 #define LMEM_PCCLCR_LACC_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 8197 #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
kadonotakashi 0:8fdf9a60065b 8198
kadonotakashi 0:8fdf9a60065b 8199 /*! @name PCCSAR - Cache search address register */
kadonotakashi 0:8fdf9a60065b 8200 #define LMEM_PCCSAR_LGO_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8201 #define LMEM_PCCSAR_LGO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8202 #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
kadonotakashi 0:8fdf9a60065b 8203 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU)
kadonotakashi 0:8fdf9a60065b 8204 #define LMEM_PCCSAR_PHYADDR_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8205 #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
kadonotakashi 0:8fdf9a60065b 8206
kadonotakashi 0:8fdf9a60065b 8207 /*! @name PCCCVR - Cache read/write value register */
kadonotakashi 0:8fdf9a60065b 8208 #define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 8209 #define LMEM_PCCCVR_DATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8210 #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
kadonotakashi 0:8fdf9a60065b 8211
kadonotakashi 0:8fdf9a60065b 8212 /*! @name PCCRMR - Cache regions mode register */
kadonotakashi 0:8fdf9a60065b 8213 #define LMEM_PCCRMR_R15_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 8214 #define LMEM_PCCRMR_R15_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8215 #define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)
kadonotakashi 0:8fdf9a60065b 8216 #define LMEM_PCCRMR_R14_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 8217 #define LMEM_PCCRMR_R14_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8218 #define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)
kadonotakashi 0:8fdf9a60065b 8219 #define LMEM_PCCRMR_R13_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 8220 #define LMEM_PCCRMR_R13_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 8221 #define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)
kadonotakashi 0:8fdf9a60065b 8222 #define LMEM_PCCRMR_R12_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 8223 #define LMEM_PCCRMR_R12_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 8224 #define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)
kadonotakashi 0:8fdf9a60065b 8225 #define LMEM_PCCRMR_R11_MASK (0x300U)
kadonotakashi 0:8fdf9a60065b 8226 #define LMEM_PCCRMR_R11_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 8227 #define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)
kadonotakashi 0:8fdf9a60065b 8228 #define LMEM_PCCRMR_R10_MASK (0xC00U)
kadonotakashi 0:8fdf9a60065b 8229 #define LMEM_PCCRMR_R10_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 8230 #define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)
kadonotakashi 0:8fdf9a60065b 8231 #define LMEM_PCCRMR_R9_MASK (0x3000U)
kadonotakashi 0:8fdf9a60065b 8232 #define LMEM_PCCRMR_R9_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 8233 #define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)
kadonotakashi 0:8fdf9a60065b 8234 #define LMEM_PCCRMR_R8_MASK (0xC000U)
kadonotakashi 0:8fdf9a60065b 8235 #define LMEM_PCCRMR_R8_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 8236 #define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)
kadonotakashi 0:8fdf9a60065b 8237 #define LMEM_PCCRMR_R7_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 8238 #define LMEM_PCCRMR_R7_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 8239 #define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)
kadonotakashi 0:8fdf9a60065b 8240 #define LMEM_PCCRMR_R6_MASK (0xC0000U)
kadonotakashi 0:8fdf9a60065b 8241 #define LMEM_PCCRMR_R6_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 8242 #define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)
kadonotakashi 0:8fdf9a60065b 8243 #define LMEM_PCCRMR_R5_MASK (0x300000U)
kadonotakashi 0:8fdf9a60065b 8244 #define LMEM_PCCRMR_R5_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 8245 #define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)
kadonotakashi 0:8fdf9a60065b 8246 #define LMEM_PCCRMR_R4_MASK (0xC00000U)
kadonotakashi 0:8fdf9a60065b 8247 #define LMEM_PCCRMR_R4_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 8248 #define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)
kadonotakashi 0:8fdf9a60065b 8249 #define LMEM_PCCRMR_R3_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 8250 #define LMEM_PCCRMR_R3_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 8251 #define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)
kadonotakashi 0:8fdf9a60065b 8252 #define LMEM_PCCRMR_R2_MASK (0xC000000U)
kadonotakashi 0:8fdf9a60065b 8253 #define LMEM_PCCRMR_R2_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 8254 #define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)
kadonotakashi 0:8fdf9a60065b 8255 #define LMEM_PCCRMR_R1_MASK (0x30000000U)
kadonotakashi 0:8fdf9a60065b 8256 #define LMEM_PCCRMR_R1_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 8257 #define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)
kadonotakashi 0:8fdf9a60065b 8258 #define LMEM_PCCRMR_R0_MASK (0xC0000000U)
kadonotakashi 0:8fdf9a60065b 8259 #define LMEM_PCCRMR_R0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 8260 #define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)
kadonotakashi 0:8fdf9a60065b 8261
kadonotakashi 0:8fdf9a60065b 8262 /*! @name PSCCR - Cache control register */
kadonotakashi 0:8fdf9a60065b 8263 #define LMEM_PSCCR_ENCACHE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8264 #define LMEM_PSCCR_ENCACHE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8265 #define LMEM_PSCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK)
kadonotakashi 0:8fdf9a60065b 8266 #define LMEM_PSCCR_ENWRBUF_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 8267 #define LMEM_PSCCR_ENWRBUF_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 8268 #define LMEM_PSCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK)
kadonotakashi 0:8fdf9a60065b 8269 #define LMEM_PSCCR_INVW0_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 8270 #define LMEM_PSCCR_INVW0_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 8271 #define LMEM_PSCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK)
kadonotakashi 0:8fdf9a60065b 8272 #define LMEM_PSCCR_PUSHW0_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 8273 #define LMEM_PSCCR_PUSHW0_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 8274 #define LMEM_PSCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK)
kadonotakashi 0:8fdf9a60065b 8275 #define LMEM_PSCCR_INVW1_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 8276 #define LMEM_PSCCR_INVW1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 8277 #define LMEM_PSCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK)
kadonotakashi 0:8fdf9a60065b 8278 #define LMEM_PSCCR_PUSHW1_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 8279 #define LMEM_PSCCR_PUSHW1_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 8280 #define LMEM_PSCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK)
kadonotakashi 0:8fdf9a60065b 8281 #define LMEM_PSCCR_GO_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 8282 #define LMEM_PSCCR_GO_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 8283 #define LMEM_PSCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK)
kadonotakashi 0:8fdf9a60065b 8284
kadonotakashi 0:8fdf9a60065b 8285 /*! @name PSCLCR - Cache line control register */
kadonotakashi 0:8fdf9a60065b 8286 #define LMEM_PSCLCR_LGO_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8287 #define LMEM_PSCLCR_LGO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8288 #define LMEM_PSCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK)
kadonotakashi 0:8fdf9a60065b 8289 #define LMEM_PSCLCR_CACHEADDR_MASK (0xFFCU)
kadonotakashi 0:8fdf9a60065b 8290 #define LMEM_PSCLCR_CACHEADDR_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8291 #define LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK)
kadonotakashi 0:8fdf9a60065b 8292 #define LMEM_PSCLCR_WSEL_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 8293 #define LMEM_PSCLCR_WSEL_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 8294 #define LMEM_PSCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK)
kadonotakashi 0:8fdf9a60065b 8295 #define LMEM_PSCLCR_TDSEL_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 8296 #define LMEM_PSCLCR_TDSEL_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 8297 #define LMEM_PSCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK)
kadonotakashi 0:8fdf9a60065b 8298 #define LMEM_PSCLCR_LCIVB_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 8299 #define LMEM_PSCLCR_LCIVB_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 8300 #define LMEM_PSCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK)
kadonotakashi 0:8fdf9a60065b 8301 #define LMEM_PSCLCR_LCIMB_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 8302 #define LMEM_PSCLCR_LCIMB_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 8303 #define LMEM_PSCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK)
kadonotakashi 0:8fdf9a60065b 8304 #define LMEM_PSCLCR_LCWAY_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 8305 #define LMEM_PSCLCR_LCWAY_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 8306 #define LMEM_PSCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK)
kadonotakashi 0:8fdf9a60065b 8307 #define LMEM_PSCLCR_LCMD_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 8308 #define LMEM_PSCLCR_LCMD_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 8309 #define LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK)
kadonotakashi 0:8fdf9a60065b 8310 #define LMEM_PSCLCR_LADSEL_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 8311 #define LMEM_PSCLCR_LADSEL_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 8312 #define LMEM_PSCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK)
kadonotakashi 0:8fdf9a60065b 8313 #define LMEM_PSCLCR_LACC_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 8314 #define LMEM_PSCLCR_LACC_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 8315 #define LMEM_PSCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK)
kadonotakashi 0:8fdf9a60065b 8316
kadonotakashi 0:8fdf9a60065b 8317 /*! @name PSCSAR - Cache search address register */
kadonotakashi 0:8fdf9a60065b 8318 #define LMEM_PSCSAR_LGO_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8319 #define LMEM_PSCSAR_LGO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8320 #define LMEM_PSCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK)
kadonotakashi 0:8fdf9a60065b 8321 #define LMEM_PSCSAR_PHYADDR_MASK (0xFFFFFFFCU)
kadonotakashi 0:8fdf9a60065b 8322 #define LMEM_PSCSAR_PHYADDR_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8323 #define LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK)
kadonotakashi 0:8fdf9a60065b 8324
kadonotakashi 0:8fdf9a60065b 8325 /*! @name PSCCVR - Cache read/write value register */
kadonotakashi 0:8fdf9a60065b 8326 #define LMEM_PSCCVR_DATA_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 8327 #define LMEM_PSCCVR_DATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8328 #define LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK)
kadonotakashi 0:8fdf9a60065b 8329
kadonotakashi 0:8fdf9a60065b 8330 /*! @name PSCRMR - Cache regions mode register */
kadonotakashi 0:8fdf9a60065b 8331 #define LMEM_PSCRMR_R15_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 8332 #define LMEM_PSCRMR_R15_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8333 #define LMEM_PSCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R15_SHIFT)) & LMEM_PSCRMR_R15_MASK)
kadonotakashi 0:8fdf9a60065b 8334 #define LMEM_PSCRMR_R14_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 8335 #define LMEM_PSCRMR_R14_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8336 #define LMEM_PSCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R14_SHIFT)) & LMEM_PSCRMR_R14_MASK)
kadonotakashi 0:8fdf9a60065b 8337 #define LMEM_PSCRMR_R13_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 8338 #define LMEM_PSCRMR_R13_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 8339 #define LMEM_PSCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R13_SHIFT)) & LMEM_PSCRMR_R13_MASK)
kadonotakashi 0:8fdf9a60065b 8340 #define LMEM_PSCRMR_R12_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 8341 #define LMEM_PSCRMR_R12_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 8342 #define LMEM_PSCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R12_SHIFT)) & LMEM_PSCRMR_R12_MASK)
kadonotakashi 0:8fdf9a60065b 8343 #define LMEM_PSCRMR_R11_MASK (0x300U)
kadonotakashi 0:8fdf9a60065b 8344 #define LMEM_PSCRMR_R11_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 8345 #define LMEM_PSCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R11_SHIFT)) & LMEM_PSCRMR_R11_MASK)
kadonotakashi 0:8fdf9a60065b 8346 #define LMEM_PSCRMR_R10_MASK (0xC00U)
kadonotakashi 0:8fdf9a60065b 8347 #define LMEM_PSCRMR_R10_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 8348 #define LMEM_PSCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R10_SHIFT)) & LMEM_PSCRMR_R10_MASK)
kadonotakashi 0:8fdf9a60065b 8349 #define LMEM_PSCRMR_R9_MASK (0x3000U)
kadonotakashi 0:8fdf9a60065b 8350 #define LMEM_PSCRMR_R9_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 8351 #define LMEM_PSCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R9_SHIFT)) & LMEM_PSCRMR_R9_MASK)
kadonotakashi 0:8fdf9a60065b 8352 #define LMEM_PSCRMR_R8_MASK (0xC000U)
kadonotakashi 0:8fdf9a60065b 8353 #define LMEM_PSCRMR_R8_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 8354 #define LMEM_PSCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R8_SHIFT)) & LMEM_PSCRMR_R8_MASK)
kadonotakashi 0:8fdf9a60065b 8355 #define LMEM_PSCRMR_R7_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 8356 #define LMEM_PSCRMR_R7_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 8357 #define LMEM_PSCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R7_SHIFT)) & LMEM_PSCRMR_R7_MASK)
kadonotakashi 0:8fdf9a60065b 8358 #define LMEM_PSCRMR_R6_MASK (0xC0000U)
kadonotakashi 0:8fdf9a60065b 8359 #define LMEM_PSCRMR_R6_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 8360 #define LMEM_PSCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R6_SHIFT)) & LMEM_PSCRMR_R6_MASK)
kadonotakashi 0:8fdf9a60065b 8361 #define LMEM_PSCRMR_R5_MASK (0x300000U)
kadonotakashi 0:8fdf9a60065b 8362 #define LMEM_PSCRMR_R5_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 8363 #define LMEM_PSCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R5_SHIFT)) & LMEM_PSCRMR_R5_MASK)
kadonotakashi 0:8fdf9a60065b 8364 #define LMEM_PSCRMR_R4_MASK (0xC00000U)
kadonotakashi 0:8fdf9a60065b 8365 #define LMEM_PSCRMR_R4_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 8366 #define LMEM_PSCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R4_SHIFT)) & LMEM_PSCRMR_R4_MASK)
kadonotakashi 0:8fdf9a60065b 8367 #define LMEM_PSCRMR_R3_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 8368 #define LMEM_PSCRMR_R3_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 8369 #define LMEM_PSCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R3_SHIFT)) & LMEM_PSCRMR_R3_MASK)
kadonotakashi 0:8fdf9a60065b 8370 #define LMEM_PSCRMR_R2_MASK (0xC000000U)
kadonotakashi 0:8fdf9a60065b 8371 #define LMEM_PSCRMR_R2_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 8372 #define LMEM_PSCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R2_SHIFT)) & LMEM_PSCRMR_R2_MASK)
kadonotakashi 0:8fdf9a60065b 8373 #define LMEM_PSCRMR_R1_MASK (0x30000000U)
kadonotakashi 0:8fdf9a60065b 8374 #define LMEM_PSCRMR_R1_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 8375 #define LMEM_PSCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R1_SHIFT)) & LMEM_PSCRMR_R1_MASK)
kadonotakashi 0:8fdf9a60065b 8376 #define LMEM_PSCRMR_R0_MASK (0xC0000000U)
kadonotakashi 0:8fdf9a60065b 8377 #define LMEM_PSCRMR_R0_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 8378 #define LMEM_PSCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R0_SHIFT)) & LMEM_PSCRMR_R0_MASK)
kadonotakashi 0:8fdf9a60065b 8379
kadonotakashi 0:8fdf9a60065b 8380
kadonotakashi 0:8fdf9a60065b 8381 /*!
kadonotakashi 0:8fdf9a60065b 8382 * @}
kadonotakashi 0:8fdf9a60065b 8383 */ /* end of group LMEM_Register_Masks */
kadonotakashi 0:8fdf9a60065b 8384
kadonotakashi 0:8fdf9a60065b 8385
kadonotakashi 0:8fdf9a60065b 8386 /* LMEM - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 8387 /** Peripheral LMEM base address */
kadonotakashi 0:8fdf9a60065b 8388 #define LMEM_BASE (0xE0082000u)
kadonotakashi 0:8fdf9a60065b 8389 /** Peripheral LMEM base pointer */
kadonotakashi 0:8fdf9a60065b 8390 #define LMEM ((LMEM_Type *)LMEM_BASE)
kadonotakashi 0:8fdf9a60065b 8391 /** Array initializer of LMEM peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 8392 #define LMEM_BASE_ADDRS { LMEM_BASE }
kadonotakashi 0:8fdf9a60065b 8393 /** Array initializer of LMEM peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 8394 #define LMEM_BASE_PTRS { LMEM }
kadonotakashi 0:8fdf9a60065b 8395
kadonotakashi 0:8fdf9a60065b 8396 /*!
kadonotakashi 0:8fdf9a60065b 8397 * @}
kadonotakashi 0:8fdf9a60065b 8398 */ /* end of group LMEM_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 8399
kadonotakashi 0:8fdf9a60065b 8400
kadonotakashi 0:8fdf9a60065b 8401 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 8402 -- LPTMR Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 8403 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 8404
kadonotakashi 0:8fdf9a60065b 8405 /*!
kadonotakashi 0:8fdf9a60065b 8406 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 8407 * @{
kadonotakashi 0:8fdf9a60065b 8408 */
kadonotakashi 0:8fdf9a60065b 8409
kadonotakashi 0:8fdf9a60065b 8410 /** LPTMR - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 8411 typedef struct {
kadonotakashi 0:8fdf9a60065b 8412 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 8413 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 8414 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 8415 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 8416 } LPTMR_Type;
kadonotakashi 0:8fdf9a60065b 8417
kadonotakashi 0:8fdf9a60065b 8418 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 8419 -- LPTMR Register Masks
kadonotakashi 0:8fdf9a60065b 8420 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 8421
kadonotakashi 0:8fdf9a60065b 8422 /*!
kadonotakashi 0:8fdf9a60065b 8423 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
kadonotakashi 0:8fdf9a60065b 8424 * @{
kadonotakashi 0:8fdf9a60065b 8425 */
kadonotakashi 0:8fdf9a60065b 8426
kadonotakashi 0:8fdf9a60065b 8427 /*! @name CSR - Low Power Timer Control Status Register */
kadonotakashi 0:8fdf9a60065b 8428 #define LPTMR_CSR_TEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8429 #define LPTMR_CSR_TEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8430 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
kadonotakashi 0:8fdf9a60065b 8431 #define LPTMR_CSR_TMS_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 8432 #define LPTMR_CSR_TMS_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 8433 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
kadonotakashi 0:8fdf9a60065b 8434 #define LPTMR_CSR_TFC_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 8435 #define LPTMR_CSR_TFC_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8436 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
kadonotakashi 0:8fdf9a60065b 8437 #define LPTMR_CSR_TPP_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 8438 #define LPTMR_CSR_TPP_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 8439 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
kadonotakashi 0:8fdf9a60065b 8440 #define LPTMR_CSR_TPS_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 8441 #define LPTMR_CSR_TPS_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 8442 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
kadonotakashi 0:8fdf9a60065b 8443 #define LPTMR_CSR_TIE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 8444 #define LPTMR_CSR_TIE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 8445 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
kadonotakashi 0:8fdf9a60065b 8446 #define LPTMR_CSR_TCF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 8447 #define LPTMR_CSR_TCF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 8448 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
kadonotakashi 0:8fdf9a60065b 8449
kadonotakashi 0:8fdf9a60065b 8450 /*! @name PSR - Low Power Timer Prescale Register */
kadonotakashi 0:8fdf9a60065b 8451 #define LPTMR_PSR_PCS_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 8452 #define LPTMR_PSR_PCS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8453 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
kadonotakashi 0:8fdf9a60065b 8454 #define LPTMR_PSR_PBYP_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 8455 #define LPTMR_PSR_PBYP_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8456 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
kadonotakashi 0:8fdf9a60065b 8457 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
kadonotakashi 0:8fdf9a60065b 8458 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 8459 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
kadonotakashi 0:8fdf9a60065b 8460
kadonotakashi 0:8fdf9a60065b 8461 /*! @name CMR - Low Power Timer Compare Register */
kadonotakashi 0:8fdf9a60065b 8462 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 8463 #define LPTMR_CMR_COMPARE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8464 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
kadonotakashi 0:8fdf9a60065b 8465
kadonotakashi 0:8fdf9a60065b 8466 /*! @name CNR - Low Power Timer Counter Register */
kadonotakashi 0:8fdf9a60065b 8467 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 8468 #define LPTMR_CNR_COUNTER_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8469 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
kadonotakashi 0:8fdf9a60065b 8470
kadonotakashi 0:8fdf9a60065b 8471
kadonotakashi 0:8fdf9a60065b 8472 /*!
kadonotakashi 0:8fdf9a60065b 8473 * @}
kadonotakashi 0:8fdf9a60065b 8474 */ /* end of group LPTMR_Register_Masks */
kadonotakashi 0:8fdf9a60065b 8475
kadonotakashi 0:8fdf9a60065b 8476
kadonotakashi 0:8fdf9a60065b 8477 /* LPTMR - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 8478 /** Peripheral LPTMR0 base address */
kadonotakashi 0:8fdf9a60065b 8479 #define LPTMR0_BASE (0x40040000u)
kadonotakashi 0:8fdf9a60065b 8480 /** Peripheral LPTMR0 base pointer */
kadonotakashi 0:8fdf9a60065b 8481 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
kadonotakashi 0:8fdf9a60065b 8482 /** Peripheral LPTMR1 base address */
kadonotakashi 0:8fdf9a60065b 8483 #define LPTMR1_BASE (0x40044000u)
kadonotakashi 0:8fdf9a60065b 8484 /** Peripheral LPTMR1 base pointer */
kadonotakashi 0:8fdf9a60065b 8485 #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE)
kadonotakashi 0:8fdf9a60065b 8486 /** Array initializer of LPTMR peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 8487 #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE }
kadonotakashi 0:8fdf9a60065b 8488 /** Array initializer of LPTMR peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 8489 #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 }
kadonotakashi 0:8fdf9a60065b 8490 /** Interrupt vectors for the LPTMR peripheral type */
kadonotakashi 0:8fdf9a60065b 8491 #define LPTMR_IRQS { LPTMR0_LPTMR1_IRQn, LPTMR0_LPTMR1_IRQn }
kadonotakashi 0:8fdf9a60065b 8492
kadonotakashi 0:8fdf9a60065b 8493 /*!
kadonotakashi 0:8fdf9a60065b 8494 * @}
kadonotakashi 0:8fdf9a60065b 8495 */ /* end of group LPTMR_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 8496
kadonotakashi 0:8fdf9a60065b 8497
kadonotakashi 0:8fdf9a60065b 8498 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 8499 -- LPUART Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 8500 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 8501
kadonotakashi 0:8fdf9a60065b 8502 /*!
kadonotakashi 0:8fdf9a60065b 8503 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 8504 * @{
kadonotakashi 0:8fdf9a60065b 8505 */
kadonotakashi 0:8fdf9a60065b 8506
kadonotakashi 0:8fdf9a60065b 8507 /** LPUART - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 8508 typedef struct {
kadonotakashi 0:8fdf9a60065b 8509 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 8510 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 8511 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 8512 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 8513 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 8514 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 8515 __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 8516 __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x1C */
kadonotakashi 0:8fdf9a60065b 8517 } LPUART_Type;
kadonotakashi 0:8fdf9a60065b 8518
kadonotakashi 0:8fdf9a60065b 8519 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 8520 -- LPUART Register Masks
kadonotakashi 0:8fdf9a60065b 8521 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 8522
kadonotakashi 0:8fdf9a60065b 8523 /*!
kadonotakashi 0:8fdf9a60065b 8524 * @addtogroup LPUART_Register_Masks LPUART Register Masks
kadonotakashi 0:8fdf9a60065b 8525 * @{
kadonotakashi 0:8fdf9a60065b 8526 */
kadonotakashi 0:8fdf9a60065b 8527
kadonotakashi 0:8fdf9a60065b 8528 /*! @name BAUD - LPUART Baud Rate Register */
kadonotakashi 0:8fdf9a60065b 8529 #define LPUART_BAUD_SBR_MASK (0x1FFFU)
kadonotakashi 0:8fdf9a60065b 8530 #define LPUART_BAUD_SBR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8531 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
kadonotakashi 0:8fdf9a60065b 8532 #define LPUART_BAUD_SBNS_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 8533 #define LPUART_BAUD_SBNS_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 8534 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
kadonotakashi 0:8fdf9a60065b 8535 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 8536 #define LPUART_BAUD_RXEDGIE_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 8537 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
kadonotakashi 0:8fdf9a60065b 8538 #define LPUART_BAUD_LBKDIE_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 8539 #define LPUART_BAUD_LBKDIE_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 8540 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
kadonotakashi 0:8fdf9a60065b 8541 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 8542 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 8543 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
kadonotakashi 0:8fdf9a60065b 8544 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 8545 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 8546 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
kadonotakashi 0:8fdf9a60065b 8547 #define LPUART_BAUD_MATCFG_MASK (0xC0000U)
kadonotakashi 0:8fdf9a60065b 8548 #define LPUART_BAUD_MATCFG_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 8549 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
kadonotakashi 0:8fdf9a60065b 8550 #define LPUART_BAUD_RDMAE_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 8551 #define LPUART_BAUD_RDMAE_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 8552 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
kadonotakashi 0:8fdf9a60065b 8553 #define LPUART_BAUD_TDMAE_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 8554 #define LPUART_BAUD_TDMAE_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 8555 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
kadonotakashi 0:8fdf9a60065b 8556 #define LPUART_BAUD_OSR_MASK (0x1F000000U)
kadonotakashi 0:8fdf9a60065b 8557 #define LPUART_BAUD_OSR_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 8558 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
kadonotakashi 0:8fdf9a60065b 8559 #define LPUART_BAUD_M10_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 8560 #define LPUART_BAUD_M10_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 8561 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
kadonotakashi 0:8fdf9a60065b 8562 #define LPUART_BAUD_MAEN2_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 8563 #define LPUART_BAUD_MAEN2_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 8564 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
kadonotakashi 0:8fdf9a60065b 8565 #define LPUART_BAUD_MAEN1_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 8566 #define LPUART_BAUD_MAEN1_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 8567 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
kadonotakashi 0:8fdf9a60065b 8568
kadonotakashi 0:8fdf9a60065b 8569 /*! @name STAT - LPUART Status Register */
kadonotakashi 0:8fdf9a60065b 8570 #define LPUART_STAT_MA2F_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 8571 #define LPUART_STAT_MA2F_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 8572 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
kadonotakashi 0:8fdf9a60065b 8573 #define LPUART_STAT_MA1F_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 8574 #define LPUART_STAT_MA1F_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 8575 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
kadonotakashi 0:8fdf9a60065b 8576 #define LPUART_STAT_PF_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 8577 #define LPUART_STAT_PF_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 8578 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
kadonotakashi 0:8fdf9a60065b 8579 #define LPUART_STAT_FE_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 8580 #define LPUART_STAT_FE_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 8581 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
kadonotakashi 0:8fdf9a60065b 8582 #define LPUART_STAT_NF_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 8583 #define LPUART_STAT_NF_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 8584 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
kadonotakashi 0:8fdf9a60065b 8585 #define LPUART_STAT_OR_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 8586 #define LPUART_STAT_OR_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 8587 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
kadonotakashi 0:8fdf9a60065b 8588 #define LPUART_STAT_IDLE_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 8589 #define LPUART_STAT_IDLE_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 8590 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
kadonotakashi 0:8fdf9a60065b 8591 #define LPUART_STAT_RDRF_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 8592 #define LPUART_STAT_RDRF_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 8593 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
kadonotakashi 0:8fdf9a60065b 8594 #define LPUART_STAT_TC_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 8595 #define LPUART_STAT_TC_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 8596 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
kadonotakashi 0:8fdf9a60065b 8597 #define LPUART_STAT_TDRE_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 8598 #define LPUART_STAT_TDRE_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 8599 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
kadonotakashi 0:8fdf9a60065b 8600 #define LPUART_STAT_RAF_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 8601 #define LPUART_STAT_RAF_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 8602 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
kadonotakashi 0:8fdf9a60065b 8603 #define LPUART_STAT_LBKDE_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 8604 #define LPUART_STAT_LBKDE_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 8605 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
kadonotakashi 0:8fdf9a60065b 8606 #define LPUART_STAT_BRK13_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 8607 #define LPUART_STAT_BRK13_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 8608 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
kadonotakashi 0:8fdf9a60065b 8609 #define LPUART_STAT_RWUID_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 8610 #define LPUART_STAT_RWUID_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 8611 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
kadonotakashi 0:8fdf9a60065b 8612 #define LPUART_STAT_RXINV_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 8613 #define LPUART_STAT_RXINV_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 8614 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
kadonotakashi 0:8fdf9a60065b 8615 #define LPUART_STAT_MSBF_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 8616 #define LPUART_STAT_MSBF_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 8617 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
kadonotakashi 0:8fdf9a60065b 8618 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 8619 #define LPUART_STAT_RXEDGIF_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 8620 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
kadonotakashi 0:8fdf9a60065b 8621 #define LPUART_STAT_LBKDIF_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 8622 #define LPUART_STAT_LBKDIF_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 8623 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
kadonotakashi 0:8fdf9a60065b 8624
kadonotakashi 0:8fdf9a60065b 8625 /*! @name CTRL - LPUART Control Register */
kadonotakashi 0:8fdf9a60065b 8626 #define LPUART_CTRL_PT_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8627 #define LPUART_CTRL_PT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8628 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
kadonotakashi 0:8fdf9a60065b 8629 #define LPUART_CTRL_PE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 8630 #define LPUART_CTRL_PE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 8631 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
kadonotakashi 0:8fdf9a60065b 8632 #define LPUART_CTRL_ILT_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 8633 #define LPUART_CTRL_ILT_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8634 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
kadonotakashi 0:8fdf9a60065b 8635 #define LPUART_CTRL_WAKE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 8636 #define LPUART_CTRL_WAKE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 8637 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
kadonotakashi 0:8fdf9a60065b 8638 #define LPUART_CTRL_M_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 8639 #define LPUART_CTRL_M_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 8640 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
kadonotakashi 0:8fdf9a60065b 8641 #define LPUART_CTRL_RSRC_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 8642 #define LPUART_CTRL_RSRC_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 8643 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
kadonotakashi 0:8fdf9a60065b 8644 #define LPUART_CTRL_DOZEEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 8645 #define LPUART_CTRL_DOZEEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 8646 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
kadonotakashi 0:8fdf9a60065b 8647 #define LPUART_CTRL_LOOPS_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 8648 #define LPUART_CTRL_LOOPS_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 8649 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
kadonotakashi 0:8fdf9a60065b 8650 #define LPUART_CTRL_IDLECFG_MASK (0x700U)
kadonotakashi 0:8fdf9a60065b 8651 #define LPUART_CTRL_IDLECFG_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 8652 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
kadonotakashi 0:8fdf9a60065b 8653 #define LPUART_CTRL_MA2IE_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 8654 #define LPUART_CTRL_MA2IE_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 8655 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
kadonotakashi 0:8fdf9a60065b 8656 #define LPUART_CTRL_MA1IE_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 8657 #define LPUART_CTRL_MA1IE_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 8658 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
kadonotakashi 0:8fdf9a60065b 8659 #define LPUART_CTRL_SBK_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 8660 #define LPUART_CTRL_SBK_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 8661 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
kadonotakashi 0:8fdf9a60065b 8662 #define LPUART_CTRL_RWU_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 8663 #define LPUART_CTRL_RWU_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 8664 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
kadonotakashi 0:8fdf9a60065b 8665 #define LPUART_CTRL_RE_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 8666 #define LPUART_CTRL_RE_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 8667 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
kadonotakashi 0:8fdf9a60065b 8668 #define LPUART_CTRL_TE_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 8669 #define LPUART_CTRL_TE_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 8670 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
kadonotakashi 0:8fdf9a60065b 8671 #define LPUART_CTRL_ILIE_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 8672 #define LPUART_CTRL_ILIE_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 8673 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
kadonotakashi 0:8fdf9a60065b 8674 #define LPUART_CTRL_RIE_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 8675 #define LPUART_CTRL_RIE_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 8676 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
kadonotakashi 0:8fdf9a60065b 8677 #define LPUART_CTRL_TCIE_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 8678 #define LPUART_CTRL_TCIE_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 8679 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
kadonotakashi 0:8fdf9a60065b 8680 #define LPUART_CTRL_TIE_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 8681 #define LPUART_CTRL_TIE_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 8682 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
kadonotakashi 0:8fdf9a60065b 8683 #define LPUART_CTRL_PEIE_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 8684 #define LPUART_CTRL_PEIE_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 8685 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
kadonotakashi 0:8fdf9a60065b 8686 #define LPUART_CTRL_FEIE_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 8687 #define LPUART_CTRL_FEIE_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 8688 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
kadonotakashi 0:8fdf9a60065b 8689 #define LPUART_CTRL_NEIE_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 8690 #define LPUART_CTRL_NEIE_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 8691 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
kadonotakashi 0:8fdf9a60065b 8692 #define LPUART_CTRL_ORIE_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 8693 #define LPUART_CTRL_ORIE_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 8694 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
kadonotakashi 0:8fdf9a60065b 8695 #define LPUART_CTRL_TXINV_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 8696 #define LPUART_CTRL_TXINV_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 8697 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
kadonotakashi 0:8fdf9a60065b 8698 #define LPUART_CTRL_TXDIR_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 8699 #define LPUART_CTRL_TXDIR_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 8700 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
kadonotakashi 0:8fdf9a60065b 8701 #define LPUART_CTRL_R9T8_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 8702 #define LPUART_CTRL_R9T8_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 8703 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
kadonotakashi 0:8fdf9a60065b 8704 #define LPUART_CTRL_R8T9_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 8705 #define LPUART_CTRL_R8T9_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 8706 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
kadonotakashi 0:8fdf9a60065b 8707
kadonotakashi 0:8fdf9a60065b 8708 /*! @name DATA - LPUART Data Register */
kadonotakashi 0:8fdf9a60065b 8709 #define LPUART_DATA_R0T0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8710 #define LPUART_DATA_R0T0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8711 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
kadonotakashi 0:8fdf9a60065b 8712 #define LPUART_DATA_R1T1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 8713 #define LPUART_DATA_R1T1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 8714 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
kadonotakashi 0:8fdf9a60065b 8715 #define LPUART_DATA_R2T2_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 8716 #define LPUART_DATA_R2T2_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8717 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
kadonotakashi 0:8fdf9a60065b 8718 #define LPUART_DATA_R3T3_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 8719 #define LPUART_DATA_R3T3_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 8720 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
kadonotakashi 0:8fdf9a60065b 8721 #define LPUART_DATA_R4T4_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 8722 #define LPUART_DATA_R4T4_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 8723 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
kadonotakashi 0:8fdf9a60065b 8724 #define LPUART_DATA_R5T5_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 8725 #define LPUART_DATA_R5T5_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 8726 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
kadonotakashi 0:8fdf9a60065b 8727 #define LPUART_DATA_R6T6_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 8728 #define LPUART_DATA_R6T6_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 8729 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
kadonotakashi 0:8fdf9a60065b 8730 #define LPUART_DATA_R7T7_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 8731 #define LPUART_DATA_R7T7_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 8732 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
kadonotakashi 0:8fdf9a60065b 8733 #define LPUART_DATA_R8T8_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 8734 #define LPUART_DATA_R8T8_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 8735 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
kadonotakashi 0:8fdf9a60065b 8736 #define LPUART_DATA_R9T9_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 8737 #define LPUART_DATA_R9T9_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 8738 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
kadonotakashi 0:8fdf9a60065b 8739 #define LPUART_DATA_IDLINE_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 8740 #define LPUART_DATA_IDLINE_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 8741 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
kadonotakashi 0:8fdf9a60065b 8742 #define LPUART_DATA_RXEMPT_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 8743 #define LPUART_DATA_RXEMPT_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 8744 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
kadonotakashi 0:8fdf9a60065b 8745 #define LPUART_DATA_FRETSC_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 8746 #define LPUART_DATA_FRETSC_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 8747 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
kadonotakashi 0:8fdf9a60065b 8748 #define LPUART_DATA_PARITYE_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 8749 #define LPUART_DATA_PARITYE_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 8750 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
kadonotakashi 0:8fdf9a60065b 8751 #define LPUART_DATA_NOISY_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 8752 #define LPUART_DATA_NOISY_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 8753 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
kadonotakashi 0:8fdf9a60065b 8754
kadonotakashi 0:8fdf9a60065b 8755 /*! @name MATCH - LPUART Match Address Register */
kadonotakashi 0:8fdf9a60065b 8756 #define LPUART_MATCH_MA1_MASK (0x3FFU)
kadonotakashi 0:8fdf9a60065b 8757 #define LPUART_MATCH_MA1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8758 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
kadonotakashi 0:8fdf9a60065b 8759 #define LPUART_MATCH_MA2_MASK (0x3FF0000U)
kadonotakashi 0:8fdf9a60065b 8760 #define LPUART_MATCH_MA2_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 8761 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
kadonotakashi 0:8fdf9a60065b 8762
kadonotakashi 0:8fdf9a60065b 8763 /*! @name MODIR - LPUART Modem IrDA Register */
kadonotakashi 0:8fdf9a60065b 8764 #define LPUART_MODIR_TXCTSE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8765 #define LPUART_MODIR_TXCTSE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8766 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
kadonotakashi 0:8fdf9a60065b 8767 #define LPUART_MODIR_TXRTSE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 8768 #define LPUART_MODIR_TXRTSE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 8769 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
kadonotakashi 0:8fdf9a60065b 8770 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 8771 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 8772 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
kadonotakashi 0:8fdf9a60065b 8773 #define LPUART_MODIR_RXRTSE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 8774 #define LPUART_MODIR_RXRTSE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 8775 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
kadonotakashi 0:8fdf9a60065b 8776 #define LPUART_MODIR_TXCTSC_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 8777 #define LPUART_MODIR_TXCTSC_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 8778 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
kadonotakashi 0:8fdf9a60065b 8779 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 8780 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 8781 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
kadonotakashi 0:8fdf9a60065b 8782 #define LPUART_MODIR_RTSWATER_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 8783 #define LPUART_MODIR_RTSWATER_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 8784 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
kadonotakashi 0:8fdf9a60065b 8785 #define LPUART_MODIR_TNP_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 8786 #define LPUART_MODIR_TNP_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 8787 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
kadonotakashi 0:8fdf9a60065b 8788 #define LPUART_MODIR_IREN_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 8789 #define LPUART_MODIR_IREN_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 8790 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
kadonotakashi 0:8fdf9a60065b 8791
kadonotakashi 0:8fdf9a60065b 8792 /*! @name FIFO - LPUART FIFO Register */
kadonotakashi 0:8fdf9a60065b 8793 #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 8794 #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8795 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
kadonotakashi 0:8fdf9a60065b 8796 #define LPUART_FIFO_RXFE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 8797 #define LPUART_FIFO_RXFE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 8798 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
kadonotakashi 0:8fdf9a60065b 8799 #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
kadonotakashi 0:8fdf9a60065b 8800 #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 8801 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
kadonotakashi 0:8fdf9a60065b 8802 #define LPUART_FIFO_TXFE_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 8803 #define LPUART_FIFO_TXFE_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 8804 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
kadonotakashi 0:8fdf9a60065b 8805 #define LPUART_FIFO_RXUFE_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 8806 #define LPUART_FIFO_RXUFE_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 8807 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
kadonotakashi 0:8fdf9a60065b 8808 #define LPUART_FIFO_TXOFE_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 8809 #define LPUART_FIFO_TXOFE_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 8810 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
kadonotakashi 0:8fdf9a60065b 8811 #define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
kadonotakashi 0:8fdf9a60065b 8812 #define LPUART_FIFO_RXIDEN_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 8813 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
kadonotakashi 0:8fdf9a60065b 8814 #define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 8815 #define LPUART_FIFO_RXFLUSH_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 8816 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
kadonotakashi 0:8fdf9a60065b 8817 #define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 8818 #define LPUART_FIFO_TXFLUSH_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 8819 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
kadonotakashi 0:8fdf9a60065b 8820 #define LPUART_FIFO_RXUF_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 8821 #define LPUART_FIFO_RXUF_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 8822 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
kadonotakashi 0:8fdf9a60065b 8823 #define LPUART_FIFO_TXOF_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 8824 #define LPUART_FIFO_TXOF_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 8825 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
kadonotakashi 0:8fdf9a60065b 8826 #define LPUART_FIFO_RXEMPT_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 8827 #define LPUART_FIFO_RXEMPT_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 8828 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
kadonotakashi 0:8fdf9a60065b 8829 #define LPUART_FIFO_TXEMPT_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 8830 #define LPUART_FIFO_TXEMPT_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 8831 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
kadonotakashi 0:8fdf9a60065b 8832
kadonotakashi 0:8fdf9a60065b 8833 /*! @name WATER - LPUART Watermark Register */
kadonotakashi 0:8fdf9a60065b 8834 #define LPUART_WATER_TXWATER_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 8835 #define LPUART_WATER_TXWATER_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8836 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
kadonotakashi 0:8fdf9a60065b 8837 #define LPUART_WATER_TXCOUNT_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 8838 #define LPUART_WATER_TXCOUNT_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 8839 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
kadonotakashi 0:8fdf9a60065b 8840 #define LPUART_WATER_RXWATER_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 8841 #define LPUART_WATER_RXWATER_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 8842 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
kadonotakashi 0:8fdf9a60065b 8843 #define LPUART_WATER_RXCOUNT_MASK (0xFF000000U)
kadonotakashi 0:8fdf9a60065b 8844 #define LPUART_WATER_RXCOUNT_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 8845 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
kadonotakashi 0:8fdf9a60065b 8846
kadonotakashi 0:8fdf9a60065b 8847
kadonotakashi 0:8fdf9a60065b 8848 /*!
kadonotakashi 0:8fdf9a60065b 8849 * @}
kadonotakashi 0:8fdf9a60065b 8850 */ /* end of group LPUART_Register_Masks */
kadonotakashi 0:8fdf9a60065b 8851
kadonotakashi 0:8fdf9a60065b 8852
kadonotakashi 0:8fdf9a60065b 8853 /* LPUART - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 8854 /** Peripheral LPUART0 base address */
kadonotakashi 0:8fdf9a60065b 8855 #define LPUART0_BASE (0x400C4000u)
kadonotakashi 0:8fdf9a60065b 8856 /** Peripheral LPUART0 base pointer */
kadonotakashi 0:8fdf9a60065b 8857 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
kadonotakashi 0:8fdf9a60065b 8858 /** Peripheral LPUART1 base address */
kadonotakashi 0:8fdf9a60065b 8859 #define LPUART1_BASE (0x400C5000u)
kadonotakashi 0:8fdf9a60065b 8860 /** Peripheral LPUART1 base pointer */
kadonotakashi 0:8fdf9a60065b 8861 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
kadonotakashi 0:8fdf9a60065b 8862 /** Peripheral LPUART2 base address */
kadonotakashi 0:8fdf9a60065b 8863 #define LPUART2_BASE (0x400C6000u)
kadonotakashi 0:8fdf9a60065b 8864 /** Peripheral LPUART2 base pointer */
kadonotakashi 0:8fdf9a60065b 8865 #define LPUART2 ((LPUART_Type *)LPUART2_BASE)
kadonotakashi 0:8fdf9a60065b 8866 /** Peripheral LPUART3 base address */
kadonotakashi 0:8fdf9a60065b 8867 #define LPUART3_BASE (0x400C7000u)
kadonotakashi 0:8fdf9a60065b 8868 /** Peripheral LPUART3 base pointer */
kadonotakashi 0:8fdf9a60065b 8869 #define LPUART3 ((LPUART_Type *)LPUART3_BASE)
kadonotakashi 0:8fdf9a60065b 8870 /** Peripheral LPUART4 base address */
kadonotakashi 0:8fdf9a60065b 8871 #define LPUART4_BASE (0x400D6000u)
kadonotakashi 0:8fdf9a60065b 8872 /** Peripheral LPUART4 base pointer */
kadonotakashi 0:8fdf9a60065b 8873 #define LPUART4 ((LPUART_Type *)LPUART4_BASE)
kadonotakashi 0:8fdf9a60065b 8874 /** Array initializer of LPUART peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 8875 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE }
kadonotakashi 0:8fdf9a60065b 8876 /** Array initializer of LPUART peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 8877 #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4 }
kadonotakashi 0:8fdf9a60065b 8878 /** Interrupt vectors for the LPUART peripheral type */
kadonotakashi 0:8fdf9a60065b 8879 #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn }
kadonotakashi 0:8fdf9a60065b 8880 #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn }
kadonotakashi 0:8fdf9a60065b 8881
kadonotakashi 0:8fdf9a60065b 8882 /*!
kadonotakashi 0:8fdf9a60065b 8883 * @}
kadonotakashi 0:8fdf9a60065b 8884 */ /* end of group LPUART_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 8885
kadonotakashi 0:8fdf9a60065b 8886
kadonotakashi 0:8fdf9a60065b 8887 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 8888 -- LTC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 8889 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 8890
kadonotakashi 0:8fdf9a60065b 8891 /*!
kadonotakashi 0:8fdf9a60065b 8892 * @addtogroup LTC_Peripheral_Access_Layer LTC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 8893 * @{
kadonotakashi 0:8fdf9a60065b 8894 */
kadonotakashi 0:8fdf9a60065b 8895
kadonotakashi 0:8fdf9a60065b 8896 /** LTC - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 8897 typedef struct {
kadonotakashi 0:8fdf9a60065b 8898 union { /* offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 8899 __IO uint32_t MD; /**< LTC Mode Register (non-PKHA/non-RNG use), offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 8900 __IO uint32_t MDPK; /**< LTC Mode Register (PublicKey), offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 8901 };
kadonotakashi 0:8fdf9a60065b 8902 uint8_t RESERVED_0[4];
kadonotakashi 0:8fdf9a60065b 8903 __IO uint32_t KS; /**< LTC Key Size Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 8904 uint8_t RESERVED_1[4];
kadonotakashi 0:8fdf9a60065b 8905 __IO uint32_t DS; /**< LTC Data Size Register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 8906 uint8_t RESERVED_2[4];
kadonotakashi 0:8fdf9a60065b 8907 __IO uint32_t ICVS; /**< LTC ICV Size Register, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 8908 uint8_t RESERVED_3[20];
kadonotakashi 0:8fdf9a60065b 8909 __IO uint32_t COM; /**< LTC Command Register, offset: 0x30 */
kadonotakashi 0:8fdf9a60065b 8910 __IO uint32_t CTL; /**< LTC Control Register, offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 8911 uint8_t RESERVED_4[8];
kadonotakashi 0:8fdf9a60065b 8912 __IO uint32_t CW; /**< LTC Clear Written Register, offset: 0x40 */
kadonotakashi 0:8fdf9a60065b 8913 uint8_t RESERVED_5[4];
kadonotakashi 0:8fdf9a60065b 8914 __IO uint32_t STA; /**< LTC Status Register, offset: 0x48 */
kadonotakashi 0:8fdf9a60065b 8915 __I uint32_t ESTA; /**< LTC Error Status Register, offset: 0x4C */
kadonotakashi 0:8fdf9a60065b 8916 uint8_t RESERVED_6[8];
kadonotakashi 0:8fdf9a60065b 8917 __IO uint32_t AADSZ; /**< LTC AAD Size Register, offset: 0x58 */
kadonotakashi 0:8fdf9a60065b 8918 uint8_t RESERVED_7[4];
kadonotakashi 0:8fdf9a60065b 8919 __IO uint32_t IVSZ; /**< LTC IV Size Register, offset: 0x60 */
kadonotakashi 0:8fdf9a60065b 8920 uint8_t RESERVED_8[4];
kadonotakashi 0:8fdf9a60065b 8921 __O uint32_t DPAMS; /**< LTC DPA Mask Seed Register, offset: 0x68 */
kadonotakashi 0:8fdf9a60065b 8922 uint8_t RESERVED_9[20];
kadonotakashi 0:8fdf9a60065b 8923 __IO uint32_t PKASZ; /**< LTC PKHA A Size Register, offset: 0x80 */
kadonotakashi 0:8fdf9a60065b 8924 uint8_t RESERVED_10[4];
kadonotakashi 0:8fdf9a60065b 8925 __IO uint32_t PKBSZ; /**< LTC PKHA B Size Register, offset: 0x88 */
kadonotakashi 0:8fdf9a60065b 8926 uint8_t RESERVED_11[4];
kadonotakashi 0:8fdf9a60065b 8927 __IO uint32_t PKNSZ; /**< LTC PKHA N Size Register, offset: 0x90 */
kadonotakashi 0:8fdf9a60065b 8928 uint8_t RESERVED_12[4];
kadonotakashi 0:8fdf9a60065b 8929 __IO uint32_t PKESZ; /**< LTC PKHA E Size Register, offset: 0x98 */
kadonotakashi 0:8fdf9a60065b 8930 uint8_t RESERVED_13[100];
kadonotakashi 0:8fdf9a60065b 8931 __IO uint32_t CTX[16]; /**< LTC Context Register, array offset: 0x100, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8932 uint8_t RESERVED_14[192];
kadonotakashi 0:8fdf9a60065b 8933 __IO uint32_t KEY[8]; /**< LTC Key Registers, array offset: 0x200, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8934 uint8_t RESERVED_15[720];
kadonotakashi 0:8fdf9a60065b 8935 __I uint32_t VID1; /**< LTC Version ID Register, offset: 0x4F0 */
kadonotakashi 0:8fdf9a60065b 8936 uint8_t RESERVED_16[4];
kadonotakashi 0:8fdf9a60065b 8937 __I uint32_t CHAVID; /**< LTC CHA Version ID Register, offset: 0x4F8 */
kadonotakashi 0:8fdf9a60065b 8938 uint8_t RESERVED_17[708];
kadonotakashi 0:8fdf9a60065b 8939 __I uint32_t FIFOSTA; /**< LTC FIFO Status Register, offset: 0x7C0 */
kadonotakashi 0:8fdf9a60065b 8940 uint8_t RESERVED_18[28];
kadonotakashi 0:8fdf9a60065b 8941 __O uint32_t IFIFO; /**< LTC Input Data FIFO, offset: 0x7E0 */
kadonotakashi 0:8fdf9a60065b 8942 uint8_t RESERVED_19[12];
kadonotakashi 0:8fdf9a60065b 8943 __I uint32_t OFIFO; /**< LTC Output Data FIFO, offset: 0x7F0 */
kadonotakashi 0:8fdf9a60065b 8944 uint8_t RESERVED_20[12];
kadonotakashi 0:8fdf9a60065b 8945 union { /* offset: 0x800 */
kadonotakashi 0:8fdf9a60065b 8946 __IO uint32_t PKA[64]; /**< LTC PKHA A 0 Register..LTC PKHA A 63 Register, array offset: 0x800, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8947 struct { /* offset: 0x800 */
kadonotakashi 0:8fdf9a60065b 8948 __IO uint32_t PKA0[16]; /**< LTC PKHA A0 0 Register..LTC PKHA A0 15 Register, array offset: 0x800, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8949 __IO uint32_t PKA1[16]; /**< LTC PKHA A1 0 Register..LTC PKHA A1 15 Register, array offset: 0x840, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8950 __IO uint32_t PKA2[16]; /**< LTC PKHA A2 0 Register..LTC PKHA A2 15 Register, array offset: 0x880, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8951 __IO uint32_t PKA3[16]; /**< LTC PKHA A3 0 Register..LTC PKHA A3 15 Register, array offset: 0x8C0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8952 } PKA_SHORT;
kadonotakashi 0:8fdf9a60065b 8953 };
kadonotakashi 0:8fdf9a60065b 8954 uint8_t RESERVED_21[256];
kadonotakashi 0:8fdf9a60065b 8955 union { /* offset: 0xA00 */
kadonotakashi 0:8fdf9a60065b 8956 __IO uint32_t PKB[64]; /**< LTC PKHA B 0 Register..LTC PKHA B 63 Register, array offset: 0xA00, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8957 struct { /* offset: 0xA00 */
kadonotakashi 0:8fdf9a60065b 8958 __IO uint32_t PKB0[16]; /**< LTC PKHA B0 0 Register..LTC PKHA B0 15 Register, array offset: 0xA00, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8959 __IO uint32_t PKB1[16]; /**< LTC PKHA B1 0 Register..LTC PKHA B1 15 Register, array offset: 0xA40, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8960 __IO uint32_t PKB2[16]; /**< LTC PKHA B2 0 Register..LTC PKHA B2 15 Register, array offset: 0xA80, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8961 __IO uint32_t PKB3[16]; /**< LTC PKHA B3 0 Register..LTC PKHA B3 15 Register, array offset: 0xAC0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8962 } PKB_SHORT;
kadonotakashi 0:8fdf9a60065b 8963 };
kadonotakashi 0:8fdf9a60065b 8964 uint8_t RESERVED_22[256];
kadonotakashi 0:8fdf9a60065b 8965 union { /* offset: 0xC00 */
kadonotakashi 0:8fdf9a60065b 8966 __IO uint32_t PKN[64]; /**< LTC PKHA N 0 Register..LTC PKHA N 63 Register, array offset: 0xC00, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8967 struct { /* offset: 0xC00 */
kadonotakashi 0:8fdf9a60065b 8968 __IO uint32_t PKN0[16]; /**< LTC PKHA N0 0 Register..LTC PKHA N0 15 Register, array offset: 0xC00, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8969 __IO uint32_t PKN1[16]; /**< LTC PKHA N1 0 Register..LTC PKHA N1 15 Register, array offset: 0xC40, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8970 __IO uint32_t PKN2[16]; /**< LTC PKHA N2 0 Register..LTC PKHA N2 15 Register, array offset: 0xC80, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8971 __IO uint32_t PKN3[16]; /**< LTC PKHA N3 0 Register..LTC PKHA N3 15 Register, array offset: 0xCC0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8972 } PKN_SHORT;
kadonotakashi 0:8fdf9a60065b 8973 };
kadonotakashi 0:8fdf9a60065b 8974 uint8_t RESERVED_23[256];
kadonotakashi 0:8fdf9a60065b 8975 union { /* offset: 0xE00 */
kadonotakashi 0:8fdf9a60065b 8976 __IO uint32_t PKE[64]; /**< LTC PKHA E 0 Register..LTC PKHA E 63 Register, array offset: 0xE00, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8977 struct { /* offset: 0xE00 */
kadonotakashi 0:8fdf9a60065b 8978 __IO uint32_t PKE0[16]; /**< LTC PKHA E0 0 Register..LTC PKHA E0 15 Register, array offset: 0xE00, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8979 __IO uint32_t PKE1[16]; /**< LTC PKHA E1 0 Register..LTC PKHA E1 15 Register, array offset: 0xE40, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8980 __IO uint32_t PKE2[16]; /**< LTC PKHA E2 0 Register..LTC PKHA E2 15 Register, array offset: 0xE80, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8981 __IO uint32_t PKE3[16]; /**< LTC PKHA E3 0 Register..LTC PKHA E3 15 Register, array offset: 0xEC0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 8982 } PKE_SHORT;
kadonotakashi 0:8fdf9a60065b 8983 };
kadonotakashi 0:8fdf9a60065b 8984 } LTC_Type;
kadonotakashi 0:8fdf9a60065b 8985
kadonotakashi 0:8fdf9a60065b 8986 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 8987 -- LTC Register Masks
kadonotakashi 0:8fdf9a60065b 8988 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 8989
kadonotakashi 0:8fdf9a60065b 8990 /*!
kadonotakashi 0:8fdf9a60065b 8991 * @addtogroup LTC_Register_Masks LTC Register Masks
kadonotakashi 0:8fdf9a60065b 8992 * @{
kadonotakashi 0:8fdf9a60065b 8993 */
kadonotakashi 0:8fdf9a60065b 8994
kadonotakashi 0:8fdf9a60065b 8995 /*! @name MD - LTC Mode Register (non-PKHA/non-RNG use) */
kadonotakashi 0:8fdf9a60065b 8996 #define LTC_MD_ENC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 8997 #define LTC_MD_ENC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 8998 #define LTC_MD_ENC(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ENC_SHIFT)) & LTC_MD_ENC_MASK)
kadonotakashi 0:8fdf9a60065b 8999 #define LTC_MD_ICV_TEST_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 9000 #define LTC_MD_ICV_TEST_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 9001 #define LTC_MD_ICV_TEST(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
kadonotakashi 0:8fdf9a60065b 9002 #define LTC_MD_AS_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 9003 #define LTC_MD_AS_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 9004 #define LTC_MD_AS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AS_SHIFT)) & LTC_MD_AS_MASK)
kadonotakashi 0:8fdf9a60065b 9005 #define LTC_MD_AAI_MASK (0x1FF0U)
kadonotakashi 0:8fdf9a60065b 9006 #define LTC_MD_AAI_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 9007 #define LTC_MD_AAI(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AAI_SHIFT)) & LTC_MD_AAI_MASK)
kadonotakashi 0:8fdf9a60065b 9008 #define LTC_MD_ALG_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 9009 #define LTC_MD_ALG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 9010 #define LTC_MD_ALG(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ALG_SHIFT)) & LTC_MD_ALG_MASK)
kadonotakashi 0:8fdf9a60065b 9011
kadonotakashi 0:8fdf9a60065b 9012 /*! @name MDPK - LTC Mode Register (PublicKey) */
kadonotakashi 0:8fdf9a60065b 9013 #define LTC_MDPK_PKHA_MODE_LS_MASK (0xFFFU)
kadonotakashi 0:8fdf9a60065b 9014 #define LTC_MDPK_PKHA_MODE_LS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9015 #define LTC_MDPK_PKHA_MODE_LS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_PKHA_MODE_LS_SHIFT)) & LTC_MDPK_PKHA_MODE_LS_MASK)
kadonotakashi 0:8fdf9a60065b 9016 #define LTC_MDPK_PKHA_MODE_MS_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 9017 #define LTC_MDPK_PKHA_MODE_MS_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 9018 #define LTC_MDPK_PKHA_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_PKHA_MODE_MS_SHIFT)) & LTC_MDPK_PKHA_MODE_MS_MASK)
kadonotakashi 0:8fdf9a60065b 9019 #define LTC_MDPK_ALG_MASK (0xF00000U)
kadonotakashi 0:8fdf9a60065b 9020 #define LTC_MDPK_ALG_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 9021 #define LTC_MDPK_ALG(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_ALG_SHIFT)) & LTC_MDPK_ALG_MASK)
kadonotakashi 0:8fdf9a60065b 9022
kadonotakashi 0:8fdf9a60065b 9023 /*! @name KS - LTC Key Size Register */
kadonotakashi 0:8fdf9a60065b 9024 #define LTC_KS_KS_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 9025 #define LTC_KS_KS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9026 #define LTC_KS_KS(x) (((uint32_t)(((uint32_t)(x)) << LTC_KS_KS_SHIFT)) & LTC_KS_KS_MASK)
kadonotakashi 0:8fdf9a60065b 9027
kadonotakashi 0:8fdf9a60065b 9028 /*! @name DS - LTC Data Size Register */
kadonotakashi 0:8fdf9a60065b 9029 #define LTC_DS_DS_MASK (0xFFFU)
kadonotakashi 0:8fdf9a60065b 9030 #define LTC_DS_DS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9031 #define LTC_DS_DS(x) (((uint32_t)(((uint32_t)(x)) << LTC_DS_DS_SHIFT)) & LTC_DS_DS_MASK)
kadonotakashi 0:8fdf9a60065b 9032
kadonotakashi 0:8fdf9a60065b 9033 /*! @name ICVS - LTC ICV Size Register */
kadonotakashi 0:8fdf9a60065b 9034 #define LTC_ICVS_ICVS_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 9035 #define LTC_ICVS_ICVS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9036 #define LTC_ICVS_ICVS(x) (((uint32_t)(((uint32_t)(x)) << LTC_ICVS_ICVS_SHIFT)) & LTC_ICVS_ICVS_MASK)
kadonotakashi 0:8fdf9a60065b 9037
kadonotakashi 0:8fdf9a60065b 9038 /*! @name COM - LTC Command Register */
kadonotakashi 0:8fdf9a60065b 9039 #define LTC_COM_ALL_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9040 #define LTC_COM_ALL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9041 #define LTC_COM_ALL(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_ALL_SHIFT)) & LTC_COM_ALL_MASK)
kadonotakashi 0:8fdf9a60065b 9042 #define LTC_COM_AES_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 9043 #define LTC_COM_AES_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 9044 #define LTC_COM_AES(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_AES_SHIFT)) & LTC_COM_AES_MASK)
kadonotakashi 0:8fdf9a60065b 9045 #define LTC_COM_DES_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 9046 #define LTC_COM_DES_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 9047 #define LTC_COM_DES(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_DES_SHIFT)) & LTC_COM_DES_MASK)
kadonotakashi 0:8fdf9a60065b 9048 #define LTC_COM_PK_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 9049 #define LTC_COM_PK_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 9050 #define LTC_COM_PK(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_PK_SHIFT)) & LTC_COM_PK_MASK)
kadonotakashi 0:8fdf9a60065b 9051
kadonotakashi 0:8fdf9a60065b 9052 /*! @name CTL - LTC Control Register */
kadonotakashi 0:8fdf9a60065b 9053 #define LTC_CTL_IM_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9054 #define LTC_CTL_IM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9055 #define LTC_CTL_IM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IM_SHIFT)) & LTC_CTL_IM_MASK)
kadonotakashi 0:8fdf9a60065b 9056 #define LTC_CTL_PDE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 9057 #define LTC_CTL_PDE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 9058 #define LTC_CTL_PDE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_PDE_SHIFT)) & LTC_CTL_PDE_MASK)
kadonotakashi 0:8fdf9a60065b 9059 #define LTC_CTL_IFE_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 9060 #define LTC_CTL_IFE_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 9061 #define LTC_CTL_IFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFE_SHIFT)) & LTC_CTL_IFE_MASK)
kadonotakashi 0:8fdf9a60065b 9062 #define LTC_CTL_IFR_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 9063 #define LTC_CTL_IFR_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 9064 #define LTC_CTL_IFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
kadonotakashi 0:8fdf9a60065b 9065 #define LTC_CTL_OFE_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 9066 #define LTC_CTL_OFE_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 9067 #define LTC_CTL_OFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFE_SHIFT)) & LTC_CTL_OFE_MASK)
kadonotakashi 0:8fdf9a60065b 9068 #define LTC_CTL_OFR_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 9069 #define LTC_CTL_OFR_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 9070 #define LTC_CTL_OFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFR_SHIFT)) & LTC_CTL_OFR_MASK)
kadonotakashi 0:8fdf9a60065b 9071 #define LTC_CTL_IFS_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 9072 #define LTC_CTL_IFS_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 9073 #define LTC_CTL_IFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFS_SHIFT)) & LTC_CTL_IFS_MASK)
kadonotakashi 0:8fdf9a60065b 9074 #define LTC_CTL_OFS_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 9075 #define LTC_CTL_OFS_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 9076 #define LTC_CTL_OFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFS_SHIFT)) & LTC_CTL_OFS_MASK)
kadonotakashi 0:8fdf9a60065b 9077 #define LTC_CTL_KIS_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 9078 #define LTC_CTL_KIS_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 9079 #define LTC_CTL_KIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KIS_SHIFT)) & LTC_CTL_KIS_MASK)
kadonotakashi 0:8fdf9a60065b 9080 #define LTC_CTL_KOS_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 9081 #define LTC_CTL_KOS_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 9082 #define LTC_CTL_KOS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KOS_SHIFT)) & LTC_CTL_KOS_MASK)
kadonotakashi 0:8fdf9a60065b 9083 #define LTC_CTL_CIS_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 9084 #define LTC_CTL_CIS_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 9085 #define LTC_CTL_CIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_CIS_SHIFT)) & LTC_CTL_CIS_MASK)
kadonotakashi 0:8fdf9a60065b 9086 #define LTC_CTL_COS_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 9087 #define LTC_CTL_COS_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 9088 #define LTC_CTL_COS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_COS_SHIFT)) & LTC_CTL_COS_MASK)
kadonotakashi 0:8fdf9a60065b 9089 #define LTC_CTL_KAL_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 9090 #define LTC_CTL_KAL_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 9091 #define LTC_CTL_KAL(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KAL_SHIFT)) & LTC_CTL_KAL_MASK)
kadonotakashi 0:8fdf9a60065b 9092
kadonotakashi 0:8fdf9a60065b 9093 /*! @name CW - LTC Clear Written Register */
kadonotakashi 0:8fdf9a60065b 9094 #define LTC_CW_CM_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9095 #define LTC_CW_CM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9096 #define LTC_CW_CM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CM_SHIFT)) & LTC_CW_CM_MASK)
kadonotakashi 0:8fdf9a60065b 9097 #define LTC_CW_CDS_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 9098 #define LTC_CW_CDS_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 9099 #define LTC_CW_CDS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CDS_SHIFT)) & LTC_CW_CDS_MASK)
kadonotakashi 0:8fdf9a60065b 9100 #define LTC_CW_CICV_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 9101 #define LTC_CW_CICV_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 9102 #define LTC_CW_CICV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CICV_SHIFT)) & LTC_CW_CICV_MASK)
kadonotakashi 0:8fdf9a60065b 9103 #define LTC_CW_CCR_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 9104 #define LTC_CW_CCR_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 9105 #define LTC_CW_CCR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CCR_SHIFT)) & LTC_CW_CCR_MASK)
kadonotakashi 0:8fdf9a60065b 9106 #define LTC_CW_CKR_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 9107 #define LTC_CW_CKR_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 9108 #define LTC_CW_CKR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CKR_SHIFT)) & LTC_CW_CKR_MASK)
kadonotakashi 0:8fdf9a60065b 9109 #define LTC_CW_CPKA_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 9110 #define LTC_CW_CPKA_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 9111 #define LTC_CW_CPKA(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKA_SHIFT)) & LTC_CW_CPKA_MASK)
kadonotakashi 0:8fdf9a60065b 9112 #define LTC_CW_CPKB_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 9113 #define LTC_CW_CPKB_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 9114 #define LTC_CW_CPKB(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKB_SHIFT)) & LTC_CW_CPKB_MASK)
kadonotakashi 0:8fdf9a60065b 9115 #define LTC_CW_CPKN_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 9116 #define LTC_CW_CPKN_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 9117 #define LTC_CW_CPKN(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKN_SHIFT)) & LTC_CW_CPKN_MASK)
kadonotakashi 0:8fdf9a60065b 9118 #define LTC_CW_CPKE_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 9119 #define LTC_CW_CPKE_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 9120 #define LTC_CW_CPKE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKE_SHIFT)) & LTC_CW_CPKE_MASK)
kadonotakashi 0:8fdf9a60065b 9121 #define LTC_CW_COF_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 9122 #define LTC_CW_COF_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 9123 #define LTC_CW_COF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_COF_SHIFT)) & LTC_CW_COF_MASK)
kadonotakashi 0:8fdf9a60065b 9124 #define LTC_CW_CIF_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 9125 #define LTC_CW_CIF_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 9126 #define LTC_CW_CIF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CIF_SHIFT)) & LTC_CW_CIF_MASK)
kadonotakashi 0:8fdf9a60065b 9127
kadonotakashi 0:8fdf9a60065b 9128 /*! @name STA - LTC Status Register */
kadonotakashi 0:8fdf9a60065b 9129 #define LTC_STA_AB_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 9130 #define LTC_STA_AB_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 9131 #define LTC_STA_AB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_AB_SHIFT)) & LTC_STA_AB_MASK)
kadonotakashi 0:8fdf9a60065b 9132 #define LTC_STA_DB_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 9133 #define LTC_STA_DB_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 9134 #define LTC_STA_DB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DB_SHIFT)) & LTC_STA_DB_MASK)
kadonotakashi 0:8fdf9a60065b 9135 #define LTC_STA_PB_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 9136 #define LTC_STA_PB_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 9137 #define LTC_STA_PB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PB_SHIFT)) & LTC_STA_PB_MASK)
kadonotakashi 0:8fdf9a60065b 9138 #define LTC_STA_DI_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 9139 #define LTC_STA_DI_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 9140 #define LTC_STA_DI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DI_SHIFT)) & LTC_STA_DI_MASK)
kadonotakashi 0:8fdf9a60065b 9141 #define LTC_STA_EI_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 9142 #define LTC_STA_EI_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 9143 #define LTC_STA_EI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_EI_SHIFT)) & LTC_STA_EI_MASK)
kadonotakashi 0:8fdf9a60065b 9144 #define LTC_STA_PKP_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 9145 #define LTC_STA_PKP_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 9146 #define LTC_STA_PKP(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKP_SHIFT)) & LTC_STA_PKP_MASK)
kadonotakashi 0:8fdf9a60065b 9147 #define LTC_STA_PKO_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 9148 #define LTC_STA_PKO_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 9149 #define LTC_STA_PKO(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKO_SHIFT)) & LTC_STA_PKO_MASK)
kadonotakashi 0:8fdf9a60065b 9150 #define LTC_STA_PKZ_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 9151 #define LTC_STA_PKZ_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 9152 #define LTC_STA_PKZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKZ_SHIFT)) & LTC_STA_PKZ_MASK)
kadonotakashi 0:8fdf9a60065b 9153
kadonotakashi 0:8fdf9a60065b 9154 /*! @name ESTA - LTC Error Status Register */
kadonotakashi 0:8fdf9a60065b 9155 #define LTC_ESTA_ERRID1_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 9156 #define LTC_ESTA_ERRID1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9157 #define LTC_ESTA_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_ERRID1_SHIFT)) & LTC_ESTA_ERRID1_MASK)
kadonotakashi 0:8fdf9a60065b 9158 #define LTC_ESTA_CL1_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 9159 #define LTC_ESTA_CL1_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 9160 #define LTC_ESTA_CL1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_CL1_SHIFT)) & LTC_ESTA_CL1_MASK)
kadonotakashi 0:8fdf9a60065b 9161
kadonotakashi 0:8fdf9a60065b 9162 /*! @name AADSZ - LTC AAD Size Register */
kadonotakashi 0:8fdf9a60065b 9163 #define LTC_AADSZ_AADSZ_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 9164 #define LTC_AADSZ_AADSZ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9165 #define LTC_AADSZ_AADSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AADSZ_SHIFT)) & LTC_AADSZ_AADSZ_MASK)
kadonotakashi 0:8fdf9a60065b 9166 #define LTC_AADSZ_AL_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 9167 #define LTC_AADSZ_AL_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 9168 #define LTC_AADSZ_AL(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AL_SHIFT)) & LTC_AADSZ_AL_MASK)
kadonotakashi 0:8fdf9a60065b 9169
kadonotakashi 0:8fdf9a60065b 9170 /*! @name IVSZ - LTC IV Size Register */
kadonotakashi 0:8fdf9a60065b 9171 #define LTC_IVSZ_IVSZ_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 9172 #define LTC_IVSZ_IVSZ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9173 #define LTC_IVSZ_IVSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_IVSZ_IVSZ_SHIFT)) & LTC_IVSZ_IVSZ_MASK)
kadonotakashi 0:8fdf9a60065b 9174 #define LTC_IVSZ_IL_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 9175 #define LTC_IVSZ_IL_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 9176 #define LTC_IVSZ_IL(x) (((uint32_t)(((uint32_t)(x)) << LTC_IVSZ_IL_SHIFT)) & LTC_IVSZ_IL_MASK)
kadonotakashi 0:8fdf9a60065b 9177
kadonotakashi 0:8fdf9a60065b 9178 /*! @name DPAMS - LTC DPA Mask Seed Register */
kadonotakashi 0:8fdf9a60065b 9179 #define LTC_DPAMS_DPAMS_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9180 #define LTC_DPAMS_DPAMS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9181 #define LTC_DPAMS_DPAMS(x) (((uint32_t)(((uint32_t)(x)) << LTC_DPAMS_DPAMS_SHIFT)) & LTC_DPAMS_DPAMS_MASK)
kadonotakashi 0:8fdf9a60065b 9182
kadonotakashi 0:8fdf9a60065b 9183 /*! @name PKASZ - LTC PKHA A Size Register */
kadonotakashi 0:8fdf9a60065b 9184 #define LTC_PKASZ_PKASZ_MASK (0x1FFU)
kadonotakashi 0:8fdf9a60065b 9185 #define LTC_PKASZ_PKASZ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9186 #define LTC_PKASZ_PKASZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKASZ_PKASZ_SHIFT)) & LTC_PKASZ_PKASZ_MASK)
kadonotakashi 0:8fdf9a60065b 9187
kadonotakashi 0:8fdf9a60065b 9188 /*! @name PKBSZ - LTC PKHA B Size Register */
kadonotakashi 0:8fdf9a60065b 9189 #define LTC_PKBSZ_PKBSZ_MASK (0x1FFU)
kadonotakashi 0:8fdf9a60065b 9190 #define LTC_PKBSZ_PKBSZ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9191 #define LTC_PKBSZ_PKBSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKBSZ_PKBSZ_SHIFT)) & LTC_PKBSZ_PKBSZ_MASK)
kadonotakashi 0:8fdf9a60065b 9192
kadonotakashi 0:8fdf9a60065b 9193 /*! @name PKNSZ - LTC PKHA N Size Register */
kadonotakashi 0:8fdf9a60065b 9194 #define LTC_PKNSZ_PKNSZ_MASK (0x1FFU)
kadonotakashi 0:8fdf9a60065b 9195 #define LTC_PKNSZ_PKNSZ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9196 #define LTC_PKNSZ_PKNSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKNSZ_PKNSZ_SHIFT)) & LTC_PKNSZ_PKNSZ_MASK)
kadonotakashi 0:8fdf9a60065b 9197
kadonotakashi 0:8fdf9a60065b 9198 /*! @name PKESZ - LTC PKHA E Size Register */
kadonotakashi 0:8fdf9a60065b 9199 #define LTC_PKESZ_PKESZ_MASK (0x1FFU)
kadonotakashi 0:8fdf9a60065b 9200 #define LTC_PKESZ_PKESZ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9201 #define LTC_PKESZ_PKESZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKESZ_PKESZ_SHIFT)) & LTC_PKESZ_PKESZ_MASK)
kadonotakashi 0:8fdf9a60065b 9202
kadonotakashi 0:8fdf9a60065b 9203 /*! @name CTX - LTC Context Register */
kadonotakashi 0:8fdf9a60065b 9204 #define LTC_CTX_CTX_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9205 #define LTC_CTX_CTX_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9206 #define LTC_CTX_CTX(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTX_CTX_SHIFT)) & LTC_CTX_CTX_MASK)
kadonotakashi 0:8fdf9a60065b 9207
kadonotakashi 0:8fdf9a60065b 9208 /* The count of LTC_CTX */
kadonotakashi 0:8fdf9a60065b 9209 #define LTC_CTX_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9210
kadonotakashi 0:8fdf9a60065b 9211 /*! @name KEY - LTC Key Registers */
kadonotakashi 0:8fdf9a60065b 9212 #define LTC_KEY_KEY_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9213 #define LTC_KEY_KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9214 #define LTC_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << LTC_KEY_KEY_SHIFT)) & LTC_KEY_KEY_MASK)
kadonotakashi 0:8fdf9a60065b 9215
kadonotakashi 0:8fdf9a60065b 9216 /* The count of LTC_KEY */
kadonotakashi 0:8fdf9a60065b 9217 #define LTC_KEY_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 9218
kadonotakashi 0:8fdf9a60065b 9219 /*! @name VID1 - LTC Version ID Register */
kadonotakashi 0:8fdf9a60065b 9220 #define LTC_VID1_MIN_REV_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 9221 #define LTC_VID1_MIN_REV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9222 #define LTC_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MIN_REV_SHIFT)) & LTC_VID1_MIN_REV_MASK)
kadonotakashi 0:8fdf9a60065b 9223 #define LTC_VID1_MAJ_REV_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 9224 #define LTC_VID1_MAJ_REV_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 9225 #define LTC_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MAJ_REV_SHIFT)) & LTC_VID1_MAJ_REV_MASK)
kadonotakashi 0:8fdf9a60065b 9226 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 9227 #define LTC_VID1_IP_ID_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 9228 #define LTC_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
kadonotakashi 0:8fdf9a60065b 9229
kadonotakashi 0:8fdf9a60065b 9230 /*! @name CHAVID - LTC CHA Version ID Register */
kadonotakashi 0:8fdf9a60065b 9231 #define LTC_CHAVID_AESREV_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 9232 #define LTC_CHAVID_AESREV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9233 #define LTC_CHAVID_AESREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESREV_SHIFT)) & LTC_CHAVID_AESREV_MASK)
kadonotakashi 0:8fdf9a60065b 9234 #define LTC_CHAVID_AESVID_MASK (0xF0U)
kadonotakashi 0:8fdf9a60065b 9235 #define LTC_CHAVID_AESVID_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 9236 #define LTC_CHAVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
kadonotakashi 0:8fdf9a60065b 9237 #define LTC_CHAVID_DESREV_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 9238 #define LTC_CHAVID_DESREV_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 9239 #define LTC_CHAVID_DESREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_DESREV_SHIFT)) & LTC_CHAVID_DESREV_MASK)
kadonotakashi 0:8fdf9a60065b 9240 #define LTC_CHAVID_DESVID_MASK (0xF000U)
kadonotakashi 0:8fdf9a60065b 9241 #define LTC_CHAVID_DESVID_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 9242 #define LTC_CHAVID_DESVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_DESVID_SHIFT)) & LTC_CHAVID_DESVID_MASK)
kadonotakashi 0:8fdf9a60065b 9243 #define LTC_CHAVID_PKHAREV_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 9244 #define LTC_CHAVID_PKHAREV_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 9245 #define LTC_CHAVID_PKHAREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_PKHAREV_SHIFT)) & LTC_CHAVID_PKHAREV_MASK)
kadonotakashi 0:8fdf9a60065b 9246 #define LTC_CHAVID_PKHAVID_MASK (0xF00000U)
kadonotakashi 0:8fdf9a60065b 9247 #define LTC_CHAVID_PKHAVID_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 9248 #define LTC_CHAVID_PKHAVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_PKHAVID_SHIFT)) & LTC_CHAVID_PKHAVID_MASK)
kadonotakashi 0:8fdf9a60065b 9249
kadonotakashi 0:8fdf9a60065b 9250 /*! @name FIFOSTA - LTC FIFO Status Register */
kadonotakashi 0:8fdf9a60065b 9251 #define LTC_FIFOSTA_IFL_MASK (0x7FU)
kadonotakashi 0:8fdf9a60065b 9252 #define LTC_FIFOSTA_IFL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9253 #define LTC_FIFOSTA_IFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFL_SHIFT)) & LTC_FIFOSTA_IFL_MASK)
kadonotakashi 0:8fdf9a60065b 9254 #define LTC_FIFOSTA_IFF_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 9255 #define LTC_FIFOSTA_IFF_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 9256 #define LTC_FIFOSTA_IFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFF_SHIFT)) & LTC_FIFOSTA_IFF_MASK)
kadonotakashi 0:8fdf9a60065b 9257 #define LTC_FIFOSTA_OFL_MASK (0x7F0000U)
kadonotakashi 0:8fdf9a60065b 9258 #define LTC_FIFOSTA_OFL_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 9259 #define LTC_FIFOSTA_OFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFL_SHIFT)) & LTC_FIFOSTA_OFL_MASK)
kadonotakashi 0:8fdf9a60065b 9260 #define LTC_FIFOSTA_OFF_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 9261 #define LTC_FIFOSTA_OFF_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 9262 #define LTC_FIFOSTA_OFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFF_SHIFT)) & LTC_FIFOSTA_OFF_MASK)
kadonotakashi 0:8fdf9a60065b 9263
kadonotakashi 0:8fdf9a60065b 9264 /*! @name IFIFO - LTC Input Data FIFO */
kadonotakashi 0:8fdf9a60065b 9265 #define LTC_IFIFO_IFIFO_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9266 #define LTC_IFIFO_IFIFO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9267 #define LTC_IFIFO_IFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_IFIFO_IFIFO_SHIFT)) & LTC_IFIFO_IFIFO_MASK)
kadonotakashi 0:8fdf9a60065b 9268
kadonotakashi 0:8fdf9a60065b 9269 /*! @name OFIFO - LTC Output Data FIFO */
kadonotakashi 0:8fdf9a60065b 9270 #define LTC_OFIFO_OFIFO_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9271 #define LTC_OFIFO_OFIFO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9272 #define LTC_OFIFO_OFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_OFIFO_OFIFO_SHIFT)) & LTC_OFIFO_OFIFO_MASK)
kadonotakashi 0:8fdf9a60065b 9273
kadonotakashi 0:8fdf9a60065b 9274 /* The count of LTC_PKA */
kadonotakashi 0:8fdf9a60065b 9275 #define LTC_PKA_COUNT (64U)
kadonotakashi 0:8fdf9a60065b 9276
kadonotakashi 0:8fdf9a60065b 9277 /*! @name PKA0 - LTC PKHA A0 0 Register..LTC PKHA A0 15 Register */
kadonotakashi 0:8fdf9a60065b 9278 #define LTC_PKA0_PKHA_A0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9279 #define LTC_PKA0_PKHA_A0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9280 #define LTC_PKA0_PKHA_A0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA0_PKHA_A0_SHIFT)) & LTC_PKA0_PKHA_A0_MASK)
kadonotakashi 0:8fdf9a60065b 9281
kadonotakashi 0:8fdf9a60065b 9282 /* The count of LTC_PKA0 */
kadonotakashi 0:8fdf9a60065b 9283 #define LTC_PKA0_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9284
kadonotakashi 0:8fdf9a60065b 9285 /*! @name PKA1 - LTC PKHA A1 0 Register..LTC PKHA A1 15 Register */
kadonotakashi 0:8fdf9a60065b 9286 #define LTC_PKA1_PKHA_A1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9287 #define LTC_PKA1_PKHA_A1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9288 #define LTC_PKA1_PKHA_A1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA1_PKHA_A1_SHIFT)) & LTC_PKA1_PKHA_A1_MASK)
kadonotakashi 0:8fdf9a60065b 9289
kadonotakashi 0:8fdf9a60065b 9290 /* The count of LTC_PKA1 */
kadonotakashi 0:8fdf9a60065b 9291 #define LTC_PKA1_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9292
kadonotakashi 0:8fdf9a60065b 9293 /*! @name PKA2 - LTC PKHA A2 0 Register..LTC PKHA A2 15 Register */
kadonotakashi 0:8fdf9a60065b 9294 #define LTC_PKA2_PKHA_A2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9295 #define LTC_PKA2_PKHA_A2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9296 #define LTC_PKA2_PKHA_A2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA2_PKHA_A2_SHIFT)) & LTC_PKA2_PKHA_A2_MASK)
kadonotakashi 0:8fdf9a60065b 9297
kadonotakashi 0:8fdf9a60065b 9298 /* The count of LTC_PKA2 */
kadonotakashi 0:8fdf9a60065b 9299 #define LTC_PKA2_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9300
kadonotakashi 0:8fdf9a60065b 9301 /*! @name PKA3 - LTC PKHA A3 0 Register..LTC PKHA A3 15 Register */
kadonotakashi 0:8fdf9a60065b 9302 #define LTC_PKA3_PKHA_A3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9303 #define LTC_PKA3_PKHA_A3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9304 #define LTC_PKA3_PKHA_A3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA3_PKHA_A3_SHIFT)) & LTC_PKA3_PKHA_A3_MASK)
kadonotakashi 0:8fdf9a60065b 9305
kadonotakashi 0:8fdf9a60065b 9306 /* The count of LTC_PKA3 */
kadonotakashi 0:8fdf9a60065b 9307 #define LTC_PKA3_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9308
kadonotakashi 0:8fdf9a60065b 9309 /* The count of LTC_PKB */
kadonotakashi 0:8fdf9a60065b 9310 #define LTC_PKB_COUNT (64U)
kadonotakashi 0:8fdf9a60065b 9311
kadonotakashi 0:8fdf9a60065b 9312 /*! @name PKB0 - LTC PKHA B0 0 Register..LTC PKHA B0 15 Register */
kadonotakashi 0:8fdf9a60065b 9313 #define LTC_PKB0_PKHA_B0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9314 #define LTC_PKB0_PKHA_B0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9315 #define LTC_PKB0_PKHA_B0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB0_PKHA_B0_SHIFT)) & LTC_PKB0_PKHA_B0_MASK)
kadonotakashi 0:8fdf9a60065b 9316
kadonotakashi 0:8fdf9a60065b 9317 /* The count of LTC_PKB0 */
kadonotakashi 0:8fdf9a60065b 9318 #define LTC_PKB0_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9319
kadonotakashi 0:8fdf9a60065b 9320 /*! @name PKB1 - LTC PKHA B1 0 Register..LTC PKHA B1 15 Register */
kadonotakashi 0:8fdf9a60065b 9321 #define LTC_PKB1_PKHA_B1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9322 #define LTC_PKB1_PKHA_B1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9323 #define LTC_PKB1_PKHA_B1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB1_PKHA_B1_SHIFT)) & LTC_PKB1_PKHA_B1_MASK)
kadonotakashi 0:8fdf9a60065b 9324
kadonotakashi 0:8fdf9a60065b 9325 /* The count of LTC_PKB1 */
kadonotakashi 0:8fdf9a60065b 9326 #define LTC_PKB1_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9327
kadonotakashi 0:8fdf9a60065b 9328 /*! @name PKB2 - LTC PKHA B2 0 Register..LTC PKHA B2 15 Register */
kadonotakashi 0:8fdf9a60065b 9329 #define LTC_PKB2_PKHA_B2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9330 #define LTC_PKB2_PKHA_B2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9331 #define LTC_PKB2_PKHA_B2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB2_PKHA_B2_SHIFT)) & LTC_PKB2_PKHA_B2_MASK)
kadonotakashi 0:8fdf9a60065b 9332
kadonotakashi 0:8fdf9a60065b 9333 /* The count of LTC_PKB2 */
kadonotakashi 0:8fdf9a60065b 9334 #define LTC_PKB2_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9335
kadonotakashi 0:8fdf9a60065b 9336 /*! @name PKB3 - LTC PKHA B3 0 Register..LTC PKHA B3 15 Register */
kadonotakashi 0:8fdf9a60065b 9337 #define LTC_PKB3_PKHA_B3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9338 #define LTC_PKB3_PKHA_B3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9339 #define LTC_PKB3_PKHA_B3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB3_PKHA_B3_SHIFT)) & LTC_PKB3_PKHA_B3_MASK)
kadonotakashi 0:8fdf9a60065b 9340
kadonotakashi 0:8fdf9a60065b 9341 /* The count of LTC_PKB3 */
kadonotakashi 0:8fdf9a60065b 9342 #define LTC_PKB3_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9343
kadonotakashi 0:8fdf9a60065b 9344 /* The count of LTC_PKN */
kadonotakashi 0:8fdf9a60065b 9345 #define LTC_PKN_COUNT (64U)
kadonotakashi 0:8fdf9a60065b 9346
kadonotakashi 0:8fdf9a60065b 9347 /*! @name PKN0 - LTC PKHA N0 0 Register..LTC PKHA N0 15 Register */
kadonotakashi 0:8fdf9a60065b 9348 #define LTC_PKN0_PKHA_N0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9349 #define LTC_PKN0_PKHA_N0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9350 #define LTC_PKN0_PKHA_N0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN0_PKHA_N0_SHIFT)) & LTC_PKN0_PKHA_N0_MASK)
kadonotakashi 0:8fdf9a60065b 9351
kadonotakashi 0:8fdf9a60065b 9352 /* The count of LTC_PKN0 */
kadonotakashi 0:8fdf9a60065b 9353 #define LTC_PKN0_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9354
kadonotakashi 0:8fdf9a60065b 9355 /*! @name PKN1 - LTC PKHA N1 0 Register..LTC PKHA N1 15 Register */
kadonotakashi 0:8fdf9a60065b 9356 #define LTC_PKN1_PKHA_N1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9357 #define LTC_PKN1_PKHA_N1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9358 #define LTC_PKN1_PKHA_N1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN1_PKHA_N1_SHIFT)) & LTC_PKN1_PKHA_N1_MASK)
kadonotakashi 0:8fdf9a60065b 9359
kadonotakashi 0:8fdf9a60065b 9360 /* The count of LTC_PKN1 */
kadonotakashi 0:8fdf9a60065b 9361 #define LTC_PKN1_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9362
kadonotakashi 0:8fdf9a60065b 9363 /*! @name PKN2 - LTC PKHA N2 0 Register..LTC PKHA N2 15 Register */
kadonotakashi 0:8fdf9a60065b 9364 #define LTC_PKN2_PKHA_N2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9365 #define LTC_PKN2_PKHA_N2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9366 #define LTC_PKN2_PKHA_N2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN2_PKHA_N2_SHIFT)) & LTC_PKN2_PKHA_N2_MASK)
kadonotakashi 0:8fdf9a60065b 9367
kadonotakashi 0:8fdf9a60065b 9368 /* The count of LTC_PKN2 */
kadonotakashi 0:8fdf9a60065b 9369 #define LTC_PKN2_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9370
kadonotakashi 0:8fdf9a60065b 9371 /*! @name PKN3 - LTC PKHA N3 0 Register..LTC PKHA N3 15 Register */
kadonotakashi 0:8fdf9a60065b 9372 #define LTC_PKN3_PKHA_N3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9373 #define LTC_PKN3_PKHA_N3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9374 #define LTC_PKN3_PKHA_N3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN3_PKHA_N3_SHIFT)) & LTC_PKN3_PKHA_N3_MASK)
kadonotakashi 0:8fdf9a60065b 9375
kadonotakashi 0:8fdf9a60065b 9376 /* The count of LTC_PKN3 */
kadonotakashi 0:8fdf9a60065b 9377 #define LTC_PKN3_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9378
kadonotakashi 0:8fdf9a60065b 9379 /* The count of LTC_PKE */
kadonotakashi 0:8fdf9a60065b 9380 #define LTC_PKE_COUNT (64U)
kadonotakashi 0:8fdf9a60065b 9381
kadonotakashi 0:8fdf9a60065b 9382 /*! @name PKE0 - LTC PKHA E0 0 Register..LTC PKHA E0 15 Register */
kadonotakashi 0:8fdf9a60065b 9383 #define LTC_PKE0_PKHA_E0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9384 #define LTC_PKE0_PKHA_E0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9385 #define LTC_PKE0_PKHA_E0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE0_PKHA_E0_SHIFT)) & LTC_PKE0_PKHA_E0_MASK)
kadonotakashi 0:8fdf9a60065b 9386
kadonotakashi 0:8fdf9a60065b 9387 /* The count of LTC_PKE0 */
kadonotakashi 0:8fdf9a60065b 9388 #define LTC_PKE0_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9389
kadonotakashi 0:8fdf9a60065b 9390 /*! @name PKE1 - LTC PKHA E1 0 Register..LTC PKHA E1 15 Register */
kadonotakashi 0:8fdf9a60065b 9391 #define LTC_PKE1_PKHA_E1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9392 #define LTC_PKE1_PKHA_E1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9393 #define LTC_PKE1_PKHA_E1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE1_PKHA_E1_SHIFT)) & LTC_PKE1_PKHA_E1_MASK)
kadonotakashi 0:8fdf9a60065b 9394
kadonotakashi 0:8fdf9a60065b 9395 /* The count of LTC_PKE1 */
kadonotakashi 0:8fdf9a60065b 9396 #define LTC_PKE1_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9397
kadonotakashi 0:8fdf9a60065b 9398 /*! @name PKE2 - LTC PKHA E2 0 Register..LTC PKHA E2 15 Register */
kadonotakashi 0:8fdf9a60065b 9399 #define LTC_PKE2_PKHA_E2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9400 #define LTC_PKE2_PKHA_E2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9401 #define LTC_PKE2_PKHA_E2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE2_PKHA_E2_SHIFT)) & LTC_PKE2_PKHA_E2_MASK)
kadonotakashi 0:8fdf9a60065b 9402
kadonotakashi 0:8fdf9a60065b 9403 /* The count of LTC_PKE2 */
kadonotakashi 0:8fdf9a60065b 9404 #define LTC_PKE2_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9405
kadonotakashi 0:8fdf9a60065b 9406 /*! @name PKE3 - LTC PKHA E3 0 Register..LTC PKHA E3 15 Register */
kadonotakashi 0:8fdf9a60065b 9407 #define LTC_PKE3_PKHA_E3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9408 #define LTC_PKE3_PKHA_E3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9409 #define LTC_PKE3_PKHA_E3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE3_PKHA_E3_SHIFT)) & LTC_PKE3_PKHA_E3_MASK)
kadonotakashi 0:8fdf9a60065b 9410
kadonotakashi 0:8fdf9a60065b 9411 /* The count of LTC_PKE3 */
kadonotakashi 0:8fdf9a60065b 9412 #define LTC_PKE3_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 9413
kadonotakashi 0:8fdf9a60065b 9414
kadonotakashi 0:8fdf9a60065b 9415 /*!
kadonotakashi 0:8fdf9a60065b 9416 * @}
kadonotakashi 0:8fdf9a60065b 9417 */ /* end of group LTC_Register_Masks */
kadonotakashi 0:8fdf9a60065b 9418
kadonotakashi 0:8fdf9a60065b 9419
kadonotakashi 0:8fdf9a60065b 9420 /* LTC - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 9421 /** Peripheral LTC0 base address */
kadonotakashi 0:8fdf9a60065b 9422 #define LTC0_BASE (0x400D1000u)
kadonotakashi 0:8fdf9a60065b 9423 /** Peripheral LTC0 base pointer */
kadonotakashi 0:8fdf9a60065b 9424 #define LTC0 ((LTC_Type *)LTC0_BASE)
kadonotakashi 0:8fdf9a60065b 9425 /** Array initializer of LTC peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 9426 #define LTC_BASE_ADDRS { LTC0_BASE }
kadonotakashi 0:8fdf9a60065b 9427 /** Array initializer of LTC peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 9428 #define LTC_BASE_PTRS { LTC0 }
kadonotakashi 0:8fdf9a60065b 9429 /** Interrupt vectors for the LTC peripheral type */
kadonotakashi 0:8fdf9a60065b 9430 #define LTC_IRQS { LTC0_IRQn }
kadonotakashi 0:8fdf9a60065b 9431
kadonotakashi 0:8fdf9a60065b 9432 /*!
kadonotakashi 0:8fdf9a60065b 9433 * @}
kadonotakashi 0:8fdf9a60065b 9434 */ /* end of group LTC_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 9435
kadonotakashi 0:8fdf9a60065b 9436
kadonotakashi 0:8fdf9a60065b 9437 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 9438 -- MCG Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 9439 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 9440
kadonotakashi 0:8fdf9a60065b 9441 /*!
kadonotakashi 0:8fdf9a60065b 9442 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 9443 * @{
kadonotakashi 0:8fdf9a60065b 9444 */
kadonotakashi 0:8fdf9a60065b 9445
kadonotakashi 0:8fdf9a60065b 9446 /** MCG - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 9447 typedef struct {
kadonotakashi 0:8fdf9a60065b 9448 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 9449 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 9450 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 9451 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
kadonotakashi 0:8fdf9a60065b 9452 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 9453 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
kadonotakashi 0:8fdf9a60065b 9454 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
kadonotakashi 0:8fdf9a60065b 9455 uint8_t RESERVED_0[1];
kadonotakashi 0:8fdf9a60065b 9456 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 9457 uint8_t RESERVED_1[1];
kadonotakashi 0:8fdf9a60065b 9458 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
kadonotakashi 0:8fdf9a60065b 9459 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
kadonotakashi 0:8fdf9a60065b 9460 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 9461 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
kadonotakashi 0:8fdf9a60065b 9462 } MCG_Type;
kadonotakashi 0:8fdf9a60065b 9463
kadonotakashi 0:8fdf9a60065b 9464 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 9465 -- MCG Register Masks
kadonotakashi 0:8fdf9a60065b 9466 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 9467
kadonotakashi 0:8fdf9a60065b 9468 /*!
kadonotakashi 0:8fdf9a60065b 9469 * @addtogroup MCG_Register_Masks MCG Register Masks
kadonotakashi 0:8fdf9a60065b 9470 * @{
kadonotakashi 0:8fdf9a60065b 9471 */
kadonotakashi 0:8fdf9a60065b 9472
kadonotakashi 0:8fdf9a60065b 9473 /*! @name C1 - MCG Control 1 Register */
kadonotakashi 0:8fdf9a60065b 9474 #define MCG_C1_IREFSTEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9475 #define MCG_C1_IREFSTEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9476 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
kadonotakashi 0:8fdf9a60065b 9477 #define MCG_C1_IRCLKEN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 9478 #define MCG_C1_IRCLKEN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 9479 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
kadonotakashi 0:8fdf9a60065b 9480 #define MCG_C1_IREFS_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 9481 #define MCG_C1_IREFS_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 9482 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
kadonotakashi 0:8fdf9a60065b 9483 #define MCG_C1_FRDIV_MASK (0x38U)
kadonotakashi 0:8fdf9a60065b 9484 #define MCG_C1_FRDIV_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 9485 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
kadonotakashi 0:8fdf9a60065b 9486 #define MCG_C1_CLKS_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 9487 #define MCG_C1_CLKS_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 9488 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
kadonotakashi 0:8fdf9a60065b 9489
kadonotakashi 0:8fdf9a60065b 9490 /*! @name C2 - MCG Control 2 Register */
kadonotakashi 0:8fdf9a60065b 9491 #define MCG_C2_IRCS_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9492 #define MCG_C2_IRCS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9493 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
kadonotakashi 0:8fdf9a60065b 9494 #define MCG_C2_LP_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 9495 #define MCG_C2_LP_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 9496 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
kadonotakashi 0:8fdf9a60065b 9497 #define MCG_C2_EREFS_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 9498 #define MCG_C2_EREFS_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 9499 #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
kadonotakashi 0:8fdf9a60065b 9500 #define MCG_C2_HGO_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 9501 #define MCG_C2_HGO_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 9502 #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
kadonotakashi 0:8fdf9a60065b 9503 #define MCG_C2_RANGE_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 9504 #define MCG_C2_RANGE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 9505 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
kadonotakashi 0:8fdf9a60065b 9506 #define MCG_C2_FCFTRIM_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 9507 #define MCG_C2_FCFTRIM_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 9508 #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
kadonotakashi 0:8fdf9a60065b 9509 #define MCG_C2_LOCRE0_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 9510 #define MCG_C2_LOCRE0_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 9511 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
kadonotakashi 0:8fdf9a60065b 9512
kadonotakashi 0:8fdf9a60065b 9513 /*! @name C3 - MCG Control 3 Register */
kadonotakashi 0:8fdf9a60065b 9514 #define MCG_C3_SCTRIM_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 9515 #define MCG_C3_SCTRIM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9516 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
kadonotakashi 0:8fdf9a60065b 9517
kadonotakashi 0:8fdf9a60065b 9518 /*! @name C4 - MCG Control 4 Register */
kadonotakashi 0:8fdf9a60065b 9519 #define MCG_C4_SCFTRIM_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9520 #define MCG_C4_SCFTRIM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9521 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
kadonotakashi 0:8fdf9a60065b 9522 #define MCG_C4_FCTRIM_MASK (0x1EU)
kadonotakashi 0:8fdf9a60065b 9523 #define MCG_C4_FCTRIM_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 9524 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
kadonotakashi 0:8fdf9a60065b 9525 #define MCG_C4_DRST_DRS_MASK (0x60U)
kadonotakashi 0:8fdf9a60065b 9526 #define MCG_C4_DRST_DRS_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 9527 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
kadonotakashi 0:8fdf9a60065b 9528 #define MCG_C4_DMX32_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 9529 #define MCG_C4_DMX32_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 9530 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
kadonotakashi 0:8fdf9a60065b 9531
kadonotakashi 0:8fdf9a60065b 9532 /*! @name C5 - MCG Control 5 Register */
kadonotakashi 0:8fdf9a60065b 9533 #define MCG_C5_PRDIV_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 9534 #define MCG_C5_PRDIV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9535 #define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
kadonotakashi 0:8fdf9a60065b 9536 #define MCG_C5_PLLSTEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 9537 #define MCG_C5_PLLSTEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 9538 #define MCG_C5_PLLSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
kadonotakashi 0:8fdf9a60065b 9539 #define MCG_C5_PLLCLKEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 9540 #define MCG_C5_PLLCLKEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 9541 #define MCG_C5_PLLCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
kadonotakashi 0:8fdf9a60065b 9542
kadonotakashi 0:8fdf9a60065b 9543 /*! @name C6 - MCG Control 6 Register */
kadonotakashi 0:8fdf9a60065b 9544 #define MCG_C6_VDIV_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 9545 #define MCG_C6_VDIV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9546 #define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
kadonotakashi 0:8fdf9a60065b 9547 #define MCG_C6_CME0_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 9548 #define MCG_C6_CME0_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 9549 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
kadonotakashi 0:8fdf9a60065b 9550 #define MCG_C6_PLLS_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 9551 #define MCG_C6_PLLS_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 9552 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
kadonotakashi 0:8fdf9a60065b 9553 #define MCG_C6_LOLIE0_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 9554 #define MCG_C6_LOLIE0_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 9555 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
kadonotakashi 0:8fdf9a60065b 9556
kadonotakashi 0:8fdf9a60065b 9557 /*! @name S - MCG Status Register */
kadonotakashi 0:8fdf9a60065b 9558 #define MCG_S_IRCST_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9559 #define MCG_S_IRCST_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9560 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
kadonotakashi 0:8fdf9a60065b 9561 #define MCG_S_OSCINIT0_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 9562 #define MCG_S_OSCINIT0_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 9563 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
kadonotakashi 0:8fdf9a60065b 9564 #define MCG_S_CLKST_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 9565 #define MCG_S_CLKST_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 9566 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
kadonotakashi 0:8fdf9a60065b 9567 #define MCG_S_IREFST_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 9568 #define MCG_S_IREFST_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 9569 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
kadonotakashi 0:8fdf9a60065b 9570 #define MCG_S_PLLST_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 9571 #define MCG_S_PLLST_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 9572 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
kadonotakashi 0:8fdf9a60065b 9573 #define MCG_S_LOCK0_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 9574 #define MCG_S_LOCK0_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 9575 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
kadonotakashi 0:8fdf9a60065b 9576 #define MCG_S_LOLS0_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 9577 #define MCG_S_LOLS0_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 9578 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
kadonotakashi 0:8fdf9a60065b 9579
kadonotakashi 0:8fdf9a60065b 9580 /*! @name SC - MCG Status and Control Register */
kadonotakashi 0:8fdf9a60065b 9581 #define MCG_SC_LOCS0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9582 #define MCG_SC_LOCS0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9583 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
kadonotakashi 0:8fdf9a60065b 9584 #define MCG_SC_FCRDIV_MASK (0xEU)
kadonotakashi 0:8fdf9a60065b 9585 #define MCG_SC_FCRDIV_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 9586 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
kadonotakashi 0:8fdf9a60065b 9587 #define MCG_SC_FLTPRSRV_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 9588 #define MCG_SC_FLTPRSRV_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 9589 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
kadonotakashi 0:8fdf9a60065b 9590 #define MCG_SC_ATMF_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 9591 #define MCG_SC_ATMF_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 9592 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
kadonotakashi 0:8fdf9a60065b 9593 #define MCG_SC_ATMS_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 9594 #define MCG_SC_ATMS_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 9595 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
kadonotakashi 0:8fdf9a60065b 9596 #define MCG_SC_ATME_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 9597 #define MCG_SC_ATME_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 9598 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
kadonotakashi 0:8fdf9a60065b 9599
kadonotakashi 0:8fdf9a60065b 9600 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
kadonotakashi 0:8fdf9a60065b 9601 #define MCG_ATCVH_ATCVH_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 9602 #define MCG_ATCVH_ATCVH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9603 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
kadonotakashi 0:8fdf9a60065b 9604
kadonotakashi 0:8fdf9a60065b 9605 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
kadonotakashi 0:8fdf9a60065b 9606 #define MCG_ATCVL_ATCVL_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 9607 #define MCG_ATCVL_ATCVL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9608 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
kadonotakashi 0:8fdf9a60065b 9609
kadonotakashi 0:8fdf9a60065b 9610 /*! @name C7 - MCG Control 7 Register */
kadonotakashi 0:8fdf9a60065b 9611 #define MCG_C7_OSCSEL_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 9612 #define MCG_C7_OSCSEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9613 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
kadonotakashi 0:8fdf9a60065b 9614
kadonotakashi 0:8fdf9a60065b 9615 /*! @name C8 - MCG Control 8 Register */
kadonotakashi 0:8fdf9a60065b 9616 #define MCG_C8_LOCS1_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9617 #define MCG_C8_LOCS1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9618 #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
kadonotakashi 0:8fdf9a60065b 9619 #define MCG_C8_CME1_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 9620 #define MCG_C8_CME1_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 9621 #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
kadonotakashi 0:8fdf9a60065b 9622 #define MCG_C8_LOLRE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 9623 #define MCG_C8_LOLRE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 9624 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
kadonotakashi 0:8fdf9a60065b 9625 #define MCG_C8_LOCRE1_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 9626 #define MCG_C8_LOCRE1_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 9627 #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
kadonotakashi 0:8fdf9a60065b 9628
kadonotakashi 0:8fdf9a60065b 9629
kadonotakashi 0:8fdf9a60065b 9630 /*!
kadonotakashi 0:8fdf9a60065b 9631 * @}
kadonotakashi 0:8fdf9a60065b 9632 */ /* end of group MCG_Register_Masks */
kadonotakashi 0:8fdf9a60065b 9633
kadonotakashi 0:8fdf9a60065b 9634
kadonotakashi 0:8fdf9a60065b 9635 /* MCG - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 9636 /** Peripheral MCG base address */
kadonotakashi 0:8fdf9a60065b 9637 #define MCG_BASE (0x40064000u)
kadonotakashi 0:8fdf9a60065b 9638 /** Peripheral MCG base pointer */
kadonotakashi 0:8fdf9a60065b 9639 #define MCG ((MCG_Type *)MCG_BASE)
kadonotakashi 0:8fdf9a60065b 9640 /** Array initializer of MCG peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 9641 #define MCG_BASE_ADDRS { MCG_BASE }
kadonotakashi 0:8fdf9a60065b 9642 /** Array initializer of MCG peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 9643 #define MCG_BASE_PTRS { MCG }
kadonotakashi 0:8fdf9a60065b 9644 /** Interrupt vectors for the MCG peripheral type */
kadonotakashi 0:8fdf9a60065b 9645 #define MCG_IRQS { MCG_IRQn }
kadonotakashi 0:8fdf9a60065b 9646 /* MCG C5[PLLCLKEN0] backward compatibility */
kadonotakashi 0:8fdf9a60065b 9647 #define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK)
kadonotakashi 0:8fdf9a60065b 9648 #define MCG_C5_PLLCLKEN0_SHIFT (MCG_C5_PLLCLKEN_SHIFT)
kadonotakashi 0:8fdf9a60065b 9649 #define MCG_C5_PLLCLKEN0_WIDTH (MCG_C5_PLLCLKEN_WIDTH)
kadonotakashi 0:8fdf9a60065b 9650 #define MCG_C5_PLLCLKEN0(x) (MCG_C5_PLLCLKEN(x))
kadonotakashi 0:8fdf9a60065b 9651
kadonotakashi 0:8fdf9a60065b 9652 /* MCG C5[PLLSTEN0] backward compatibility */
kadonotakashi 0:8fdf9a60065b 9653 #define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK)
kadonotakashi 0:8fdf9a60065b 9654 #define MCG_C5_PLLSTEN0_SHIFT (MCG_C5_PLLSTEN_SHIFT)
kadonotakashi 0:8fdf9a60065b 9655 #define MCG_C5_PLLSTEN0_WIDTH (MCG_C5_PLLSTEN_WIDTH)
kadonotakashi 0:8fdf9a60065b 9656 #define MCG_C5_PLLSTEN0(x) (MCG_C5_PLLSTEN(x))
kadonotakashi 0:8fdf9a60065b 9657
kadonotakashi 0:8fdf9a60065b 9658 /* MCG C5[PRDIV0] backward compatibility */
kadonotakashi 0:8fdf9a60065b 9659 #define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK)
kadonotakashi 0:8fdf9a60065b 9660 #define MCG_C5_PRDIV0_SHIFT (MCG_C5_PRDIV_SHIFT)
kadonotakashi 0:8fdf9a60065b 9661 #define MCG_C5_PRDIV0_WIDTH (MCG_C5_PRDIV_WIDTH)
kadonotakashi 0:8fdf9a60065b 9662 #define MCG_C5_PRDIV0(x) (MCG_C5_PRDIV(x))
kadonotakashi 0:8fdf9a60065b 9663
kadonotakashi 0:8fdf9a60065b 9664 /* MCG C6[VDIV0] backward compatibility */
kadonotakashi 0:8fdf9a60065b 9665 #define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK)
kadonotakashi 0:8fdf9a60065b 9666 #define MCG_C6_VDIV0_SHIFT (MCG_C6_VDIV_SHIFT)
kadonotakashi 0:8fdf9a60065b 9667 #define MCG_C6_VDIV0_WIDTH (MCG_C6_VDIV_WIDTH)
kadonotakashi 0:8fdf9a60065b 9668 #define MCG_C6_VDIV0(x) (MCG_C6_VDIV(x))
kadonotakashi 0:8fdf9a60065b 9669
kadonotakashi 0:8fdf9a60065b 9670
kadonotakashi 0:8fdf9a60065b 9671 /*!
kadonotakashi 0:8fdf9a60065b 9672 * @}
kadonotakashi 0:8fdf9a60065b 9673 */ /* end of group MCG_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 9674
kadonotakashi 0:8fdf9a60065b 9675
kadonotakashi 0:8fdf9a60065b 9676 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 9677 -- MCM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 9678 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 9679
kadonotakashi 0:8fdf9a60065b 9680 /*!
kadonotakashi 0:8fdf9a60065b 9681 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 9682 * @{
kadonotakashi 0:8fdf9a60065b 9683 */
kadonotakashi 0:8fdf9a60065b 9684
kadonotakashi 0:8fdf9a60065b 9685 /** MCM - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 9686 typedef struct {
kadonotakashi 0:8fdf9a60065b 9687 uint8_t RESERVED_0[8];
kadonotakashi 0:8fdf9a60065b 9688 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 9689 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
kadonotakashi 0:8fdf9a60065b 9690 __IO uint32_t CR; /**< Control Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 9691 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 9692 uint8_t RESERVED_1[12];
kadonotakashi 0:8fdf9a60065b 9693 __I uint32_t FADR; /**< Fault address register, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 9694 __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 9695 __I uint32_t FDR; /**< Fault data register, offset: 0x28 */
kadonotakashi 0:8fdf9a60065b 9696 uint8_t RESERVED_2[4];
kadonotakashi 0:8fdf9a60065b 9697 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
kadonotakashi 0:8fdf9a60065b 9698 uint8_t RESERVED_3[12];
kadonotakashi 0:8fdf9a60065b 9699 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
kadonotakashi 0:8fdf9a60065b 9700 } MCM_Type;
kadonotakashi 0:8fdf9a60065b 9701
kadonotakashi 0:8fdf9a60065b 9702 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 9703 -- MCM Register Masks
kadonotakashi 0:8fdf9a60065b 9704 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 9705
kadonotakashi 0:8fdf9a60065b 9706 /*!
kadonotakashi 0:8fdf9a60065b 9707 * @addtogroup MCM_Register_Masks MCM Register Masks
kadonotakashi 0:8fdf9a60065b 9708 * @{
kadonotakashi 0:8fdf9a60065b 9709 */
kadonotakashi 0:8fdf9a60065b 9710
kadonotakashi 0:8fdf9a60065b 9711 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
kadonotakashi 0:8fdf9a60065b 9712 #define MCM_PLASC_ASC_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 9713 #define MCM_PLASC_ASC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9714 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
kadonotakashi 0:8fdf9a60065b 9715
kadonotakashi 0:8fdf9a60065b 9716 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
kadonotakashi 0:8fdf9a60065b 9717 #define MCM_PLAMC_AMC_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 9718 #define MCM_PLAMC_AMC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9719 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
kadonotakashi 0:8fdf9a60065b 9720
kadonotakashi 0:8fdf9a60065b 9721 /*! @name CR - Control Register */
kadonotakashi 0:8fdf9a60065b 9722 #define MCM_CR_SRAMUAP_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 9723 #define MCM_CR_SRAMUAP_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 9724 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
kadonotakashi 0:8fdf9a60065b 9725 #define MCM_CR_SRAMUWP_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 9726 #define MCM_CR_SRAMUWP_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 9727 #define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
kadonotakashi 0:8fdf9a60065b 9728 #define MCM_CR_SRAMLAP_MASK (0x30000000U)
kadonotakashi 0:8fdf9a60065b 9729 #define MCM_CR_SRAMLAP_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 9730 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
kadonotakashi 0:8fdf9a60065b 9731 #define MCM_CR_SRAMLWP_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 9732 #define MCM_CR_SRAMLWP_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 9733 #define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
kadonotakashi 0:8fdf9a60065b 9734
kadonotakashi 0:8fdf9a60065b 9735 /*! @name ISCR - Interrupt Status Register */
kadonotakashi 0:8fdf9a60065b 9736 #define MCM_ISCR_FIOC_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 9737 #define MCM_ISCR_FIOC_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 9738 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
kadonotakashi 0:8fdf9a60065b 9739 #define MCM_ISCR_FDZC_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 9740 #define MCM_ISCR_FDZC_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 9741 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
kadonotakashi 0:8fdf9a60065b 9742 #define MCM_ISCR_FOFC_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 9743 #define MCM_ISCR_FOFC_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 9744 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
kadonotakashi 0:8fdf9a60065b 9745 #define MCM_ISCR_FUFC_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 9746 #define MCM_ISCR_FUFC_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 9747 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
kadonotakashi 0:8fdf9a60065b 9748 #define MCM_ISCR_FIXC_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 9749 #define MCM_ISCR_FIXC_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 9750 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
kadonotakashi 0:8fdf9a60065b 9751 #define MCM_ISCR_FIDC_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 9752 #define MCM_ISCR_FIDC_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 9753 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
kadonotakashi 0:8fdf9a60065b 9754 #define MCM_ISCR_FIOCE_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 9755 #define MCM_ISCR_FIOCE_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 9756 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
kadonotakashi 0:8fdf9a60065b 9757 #define MCM_ISCR_FDZCE_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 9758 #define MCM_ISCR_FDZCE_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 9759 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
kadonotakashi 0:8fdf9a60065b 9760 #define MCM_ISCR_FOFCE_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 9761 #define MCM_ISCR_FOFCE_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 9762 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
kadonotakashi 0:8fdf9a60065b 9763 #define MCM_ISCR_FUFCE_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 9764 #define MCM_ISCR_FUFCE_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 9765 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
kadonotakashi 0:8fdf9a60065b 9766 #define MCM_ISCR_FIXCE_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 9767 #define MCM_ISCR_FIXCE_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 9768 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
kadonotakashi 0:8fdf9a60065b 9769 #define MCM_ISCR_FIDCE_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 9770 #define MCM_ISCR_FIDCE_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 9771 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
kadonotakashi 0:8fdf9a60065b 9772
kadonotakashi 0:8fdf9a60065b 9773 /*! @name FADR - Fault address register */
kadonotakashi 0:8fdf9a60065b 9774 #define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9775 #define MCM_FADR_ADDRESS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9776 #define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
kadonotakashi 0:8fdf9a60065b 9777
kadonotakashi 0:8fdf9a60065b 9778 /*! @name FATR - Fault attributes register */
kadonotakashi 0:8fdf9a60065b 9779 #define MCM_FATR_BEDA_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9780 #define MCM_FATR_BEDA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9781 #define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
kadonotakashi 0:8fdf9a60065b 9782 #define MCM_FATR_BEMD_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 9783 #define MCM_FATR_BEMD_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 9784 #define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
kadonotakashi 0:8fdf9a60065b 9785 #define MCM_FATR_BESZ_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 9786 #define MCM_FATR_BESZ_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 9787 #define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
kadonotakashi 0:8fdf9a60065b 9788 #define MCM_FATR_BEWT_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 9789 #define MCM_FATR_BEWT_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 9790 #define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
kadonotakashi 0:8fdf9a60065b 9791 #define MCM_FATR_BEMN_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 9792 #define MCM_FATR_BEMN_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 9793 #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
kadonotakashi 0:8fdf9a60065b 9794 #define MCM_FATR_BEOVR_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 9795 #define MCM_FATR_BEOVR_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 9796 #define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
kadonotakashi 0:8fdf9a60065b 9797
kadonotakashi 0:8fdf9a60065b 9798 /*! @name FDR - Fault data register */
kadonotakashi 0:8fdf9a60065b 9799 #define MCM_FDR_DATA_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9800 #define MCM_FDR_DATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9801 #define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
kadonotakashi 0:8fdf9a60065b 9802
kadonotakashi 0:8fdf9a60065b 9803 /*! @name PID - Process ID register */
kadonotakashi 0:8fdf9a60065b 9804 #define MCM_PID_PID_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 9805 #define MCM_PID_PID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9806 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
kadonotakashi 0:8fdf9a60065b 9807
kadonotakashi 0:8fdf9a60065b 9808 /*! @name CPO - Compute Operation Control Register */
kadonotakashi 0:8fdf9a60065b 9809 #define MCM_CPO_CPOREQ_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9810 #define MCM_CPO_CPOREQ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9811 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
kadonotakashi 0:8fdf9a60065b 9812 #define MCM_CPO_CPOACK_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 9813 #define MCM_CPO_CPOACK_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 9814 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
kadonotakashi 0:8fdf9a60065b 9815 #define MCM_CPO_CPOWOI_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 9816 #define MCM_CPO_CPOWOI_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 9817 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
kadonotakashi 0:8fdf9a60065b 9818
kadonotakashi 0:8fdf9a60065b 9819
kadonotakashi 0:8fdf9a60065b 9820 /*!
kadonotakashi 0:8fdf9a60065b 9821 * @}
kadonotakashi 0:8fdf9a60065b 9822 */ /* end of group MCM_Register_Masks */
kadonotakashi 0:8fdf9a60065b 9823
kadonotakashi 0:8fdf9a60065b 9824
kadonotakashi 0:8fdf9a60065b 9825 /* MCM - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 9826 /** Peripheral MCM base address */
kadonotakashi 0:8fdf9a60065b 9827 #define MCM_BASE (0xE0080000u)
kadonotakashi 0:8fdf9a60065b 9828 /** Peripheral MCM base pointer */
kadonotakashi 0:8fdf9a60065b 9829 #define MCM ((MCM_Type *)MCM_BASE)
kadonotakashi 0:8fdf9a60065b 9830 /** Array initializer of MCM peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 9831 #define MCM_BASE_ADDRS { MCM_BASE }
kadonotakashi 0:8fdf9a60065b 9832 /** Array initializer of MCM peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 9833 #define MCM_BASE_PTRS { MCM }
kadonotakashi 0:8fdf9a60065b 9834 /** Interrupt vectors for the MCM peripheral type */
kadonotakashi 0:8fdf9a60065b 9835 #define MCM_IRQS { MCM_IRQn }
kadonotakashi 0:8fdf9a60065b 9836
kadonotakashi 0:8fdf9a60065b 9837 /*!
kadonotakashi 0:8fdf9a60065b 9838 * @}
kadonotakashi 0:8fdf9a60065b 9839 */ /* end of group MCM_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 9840
kadonotakashi 0:8fdf9a60065b 9841
kadonotakashi 0:8fdf9a60065b 9842 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 9843 -- MPU Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 9844 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 9845
kadonotakashi 0:8fdf9a60065b 9846 /*!
kadonotakashi 0:8fdf9a60065b 9847 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 9848 * @{
kadonotakashi 0:8fdf9a60065b 9849 */
kadonotakashi 0:8fdf9a60065b 9850
kadonotakashi 0:8fdf9a60065b 9851 /** MPU - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 9852 typedef struct {
kadonotakashi 0:8fdf9a60065b 9853 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 9854 uint8_t RESERVED_0[12];
kadonotakashi 0:8fdf9a60065b 9855 struct { /* offset: 0x10, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 9856 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 9857 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 9858 } SP[5];
kadonotakashi 0:8fdf9a60065b 9859 uint8_t RESERVED_1[968];
kadonotakashi 0:8fdf9a60065b 9860 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
kadonotakashi 0:8fdf9a60065b 9861 uint8_t RESERVED_2[832];
kadonotakashi 0:8fdf9a60065b 9862 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 9863 } MPU_Type;
kadonotakashi 0:8fdf9a60065b 9864
kadonotakashi 0:8fdf9a60065b 9865 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 9866 -- MPU Register Masks
kadonotakashi 0:8fdf9a60065b 9867 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 9868
kadonotakashi 0:8fdf9a60065b 9869 /*!
kadonotakashi 0:8fdf9a60065b 9870 * @addtogroup MPU_Register_Masks MPU Register Masks
kadonotakashi 0:8fdf9a60065b 9871 * @{
kadonotakashi 0:8fdf9a60065b 9872 */
kadonotakashi 0:8fdf9a60065b 9873
kadonotakashi 0:8fdf9a60065b 9874 /*! @name CESR - Control/Error Status Register */
kadonotakashi 0:8fdf9a60065b 9875 #define MPU_CESR_VLD_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9876 #define MPU_CESR_VLD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9877 #define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK)
kadonotakashi 0:8fdf9a60065b 9878 #define MPU_CESR_NRGD_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 9879 #define MPU_CESR_NRGD_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 9880 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK)
kadonotakashi 0:8fdf9a60065b 9881 #define MPU_CESR_NSP_MASK (0xF000U)
kadonotakashi 0:8fdf9a60065b 9882 #define MPU_CESR_NSP_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 9883 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK)
kadonotakashi 0:8fdf9a60065b 9884 #define MPU_CESR_HRL_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 9885 #define MPU_CESR_HRL_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 9886 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK)
kadonotakashi 0:8fdf9a60065b 9887 #define MPU_CESR_SPERR_MASK (0xF8000000U)
kadonotakashi 0:8fdf9a60065b 9888 #define MPU_CESR_SPERR_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 9889 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK)
kadonotakashi 0:8fdf9a60065b 9890
kadonotakashi 0:8fdf9a60065b 9891 /*! @name EAR - Error Address Register, slave port n */
kadonotakashi 0:8fdf9a60065b 9892 #define MPU_EAR_EADDR_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 9893 #define MPU_EAR_EADDR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9894 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK)
kadonotakashi 0:8fdf9a60065b 9895
kadonotakashi 0:8fdf9a60065b 9896 /* The count of MPU_EAR */
kadonotakashi 0:8fdf9a60065b 9897 #define MPU_EAR_COUNT (5U)
kadonotakashi 0:8fdf9a60065b 9898
kadonotakashi 0:8fdf9a60065b 9899 /*! @name EDR - Error Detail Register, slave port n */
kadonotakashi 0:8fdf9a60065b 9900 #define MPU_EDR_ERW_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9901 #define MPU_EDR_ERW_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9902 #define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK)
kadonotakashi 0:8fdf9a60065b 9903 #define MPU_EDR_EATTR_MASK (0xEU)
kadonotakashi 0:8fdf9a60065b 9904 #define MPU_EDR_EATTR_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 9905 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK)
kadonotakashi 0:8fdf9a60065b 9906 #define MPU_EDR_EMN_MASK (0xF0U)
kadonotakashi 0:8fdf9a60065b 9907 #define MPU_EDR_EMN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 9908 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK)
kadonotakashi 0:8fdf9a60065b 9909 #define MPU_EDR_EPID_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 9910 #define MPU_EDR_EPID_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 9911 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK)
kadonotakashi 0:8fdf9a60065b 9912 #define MPU_EDR_EACD_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 9913 #define MPU_EDR_EACD_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 9914 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK)
kadonotakashi 0:8fdf9a60065b 9915
kadonotakashi 0:8fdf9a60065b 9916 /* The count of MPU_EDR */
kadonotakashi 0:8fdf9a60065b 9917 #define MPU_EDR_COUNT (5U)
kadonotakashi 0:8fdf9a60065b 9918
kadonotakashi 0:8fdf9a60065b 9919 /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
kadonotakashi 0:8fdf9a60065b 9920 #define MPU_WORD_VLD_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 9921 #define MPU_WORD_VLD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9922 #define MPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_VLD_SHIFT)) & MPU_WORD_VLD_MASK)
kadonotakashi 0:8fdf9a60065b 9923 #define MPU_WORD_M0UM_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 9924 #define MPU_WORD_M0UM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 9925 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK)
kadonotakashi 0:8fdf9a60065b 9926 #define MPU_WORD_M0SM_MASK (0x18U)
kadonotakashi 0:8fdf9a60065b 9927 #define MPU_WORD_M0SM_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 9928 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK)
kadonotakashi 0:8fdf9a60065b 9929 #define MPU_WORD_M0PE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 9930 #define MPU_WORD_M0PE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 9931 #define MPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0PE_SHIFT)) & MPU_WORD_M0PE_MASK)
kadonotakashi 0:8fdf9a60065b 9932 #define MPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
kadonotakashi 0:8fdf9a60065b 9933 #define MPU_WORD_ENDADDR_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 9934 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK)
kadonotakashi 0:8fdf9a60065b 9935 #define MPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
kadonotakashi 0:8fdf9a60065b 9936 #define MPU_WORD_SRTADDR_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 9937 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK)
kadonotakashi 0:8fdf9a60065b 9938 #define MPU_WORD_M1UM_MASK (0x1C0U)
kadonotakashi 0:8fdf9a60065b 9939 #define MPU_WORD_M1UM_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 9940 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK)
kadonotakashi 0:8fdf9a60065b 9941 #define MPU_WORD_M1SM_MASK (0x600U)
kadonotakashi 0:8fdf9a60065b 9942 #define MPU_WORD_M1SM_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 9943 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK)
kadonotakashi 0:8fdf9a60065b 9944 #define MPU_WORD_M1PE_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 9945 #define MPU_WORD_M1PE_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 9946 #define MPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1PE_SHIFT)) & MPU_WORD_M1PE_MASK)
kadonotakashi 0:8fdf9a60065b 9947 #define MPU_WORD_M2UM_MASK (0x7000U)
kadonotakashi 0:8fdf9a60065b 9948 #define MPU_WORD_M2UM_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 9949 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK)
kadonotakashi 0:8fdf9a60065b 9950 #define MPU_WORD_M2SM_MASK (0x18000U)
kadonotakashi 0:8fdf9a60065b 9951 #define MPU_WORD_M2SM_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 9952 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK)
kadonotakashi 0:8fdf9a60065b 9953 #define MPU_WORD_PIDMASK_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 9954 #define MPU_WORD_PIDMASK_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 9955 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK)
kadonotakashi 0:8fdf9a60065b 9956 #define MPU_WORD_M2PE_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 9957 #define MPU_WORD_M2PE_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 9958 #define MPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2PE_SHIFT)) & MPU_WORD_M2PE_MASK)
kadonotakashi 0:8fdf9a60065b 9959 #define MPU_WORD_M3UM_MASK (0x1C0000U)
kadonotakashi 0:8fdf9a60065b 9960 #define MPU_WORD_M3UM_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 9961 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK)
kadonotakashi 0:8fdf9a60065b 9962 #define MPU_WORD_M3SM_MASK (0x600000U)
kadonotakashi 0:8fdf9a60065b 9963 #define MPU_WORD_M3SM_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 9964 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK)
kadonotakashi 0:8fdf9a60065b 9965 #define MPU_WORD_M3PE_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 9966 #define MPU_WORD_M3PE_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 9967 #define MPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3PE_SHIFT)) & MPU_WORD_M3PE_MASK)
kadonotakashi 0:8fdf9a60065b 9968 #define MPU_WORD_PID_MASK (0xFF000000U)
kadonotakashi 0:8fdf9a60065b 9969 #define MPU_WORD_PID_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 9970 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK)
kadonotakashi 0:8fdf9a60065b 9971 #define MPU_WORD_M4WE_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 9972 #define MPU_WORD_M4WE_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 9973 #define MPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4WE_SHIFT)) & MPU_WORD_M4WE_MASK)
kadonotakashi 0:8fdf9a60065b 9974 #define MPU_WORD_M4RE_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 9975 #define MPU_WORD_M4RE_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 9976 #define MPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4RE_SHIFT)) & MPU_WORD_M4RE_MASK)
kadonotakashi 0:8fdf9a60065b 9977 #define MPU_WORD_M5WE_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 9978 #define MPU_WORD_M5WE_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 9979 #define MPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5WE_SHIFT)) & MPU_WORD_M5WE_MASK)
kadonotakashi 0:8fdf9a60065b 9980 #define MPU_WORD_M5RE_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 9981 #define MPU_WORD_M5RE_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 9982 #define MPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5RE_SHIFT)) & MPU_WORD_M5RE_MASK)
kadonotakashi 0:8fdf9a60065b 9983 #define MPU_WORD_M6WE_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 9984 #define MPU_WORD_M6WE_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 9985 #define MPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6WE_SHIFT)) & MPU_WORD_M6WE_MASK)
kadonotakashi 0:8fdf9a60065b 9986 #define MPU_WORD_M6RE_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 9987 #define MPU_WORD_M6RE_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 9988 #define MPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6RE_SHIFT)) & MPU_WORD_M6RE_MASK)
kadonotakashi 0:8fdf9a60065b 9989 #define MPU_WORD_M7WE_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 9990 #define MPU_WORD_M7WE_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 9991 #define MPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7WE_SHIFT)) & MPU_WORD_M7WE_MASK)
kadonotakashi 0:8fdf9a60065b 9992 #define MPU_WORD_M7RE_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 9993 #define MPU_WORD_M7RE_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 9994 #define MPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7RE_SHIFT)) & MPU_WORD_M7RE_MASK)
kadonotakashi 0:8fdf9a60065b 9995
kadonotakashi 0:8fdf9a60065b 9996 /* The count of MPU_WORD */
kadonotakashi 0:8fdf9a60065b 9997 #define MPU_WORD_COUNT (12U)
kadonotakashi 0:8fdf9a60065b 9998
kadonotakashi 0:8fdf9a60065b 9999 /* The count of MPU_WORD */
kadonotakashi 0:8fdf9a60065b 10000 #define MPU_WORD_COUNT2 (4U)
kadonotakashi 0:8fdf9a60065b 10001
kadonotakashi 0:8fdf9a60065b 10002 /*! @name RGDAAC - Region Descriptor Alternate Access Control n */
kadonotakashi 0:8fdf9a60065b 10003 #define MPU_RGDAAC_M0UM_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 10004 #define MPU_RGDAAC_M0UM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10005 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK)
kadonotakashi 0:8fdf9a60065b 10006 #define MPU_RGDAAC_M0SM_MASK (0x18U)
kadonotakashi 0:8fdf9a60065b 10007 #define MPU_RGDAAC_M0SM_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 10008 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK)
kadonotakashi 0:8fdf9a60065b 10009 #define MPU_RGDAAC_M0PE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 10010 #define MPU_RGDAAC_M0PE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 10011 #define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK)
kadonotakashi 0:8fdf9a60065b 10012 #define MPU_RGDAAC_M1UM_MASK (0x1C0U)
kadonotakashi 0:8fdf9a60065b 10013 #define MPU_RGDAAC_M1UM_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 10014 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK)
kadonotakashi 0:8fdf9a60065b 10015 #define MPU_RGDAAC_M1SM_MASK (0x600U)
kadonotakashi 0:8fdf9a60065b 10016 #define MPU_RGDAAC_M1SM_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 10017 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK)
kadonotakashi 0:8fdf9a60065b 10018 #define MPU_RGDAAC_M1PE_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 10019 #define MPU_RGDAAC_M1PE_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 10020 #define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK)
kadonotakashi 0:8fdf9a60065b 10021 #define MPU_RGDAAC_M2UM_MASK (0x7000U)
kadonotakashi 0:8fdf9a60065b 10022 #define MPU_RGDAAC_M2UM_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 10023 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK)
kadonotakashi 0:8fdf9a60065b 10024 #define MPU_RGDAAC_M2SM_MASK (0x18000U)
kadonotakashi 0:8fdf9a60065b 10025 #define MPU_RGDAAC_M2SM_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 10026 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK)
kadonotakashi 0:8fdf9a60065b 10027 #define MPU_RGDAAC_M2PE_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 10028 #define MPU_RGDAAC_M2PE_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 10029 #define MPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2PE_SHIFT)) & MPU_RGDAAC_M2PE_MASK)
kadonotakashi 0:8fdf9a60065b 10030 #define MPU_RGDAAC_M3UM_MASK (0x1C0000U)
kadonotakashi 0:8fdf9a60065b 10031 #define MPU_RGDAAC_M3UM_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 10032 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK)
kadonotakashi 0:8fdf9a60065b 10033 #define MPU_RGDAAC_M3SM_MASK (0x600000U)
kadonotakashi 0:8fdf9a60065b 10034 #define MPU_RGDAAC_M3SM_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 10035 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK)
kadonotakashi 0:8fdf9a60065b 10036 #define MPU_RGDAAC_M3PE_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 10037 #define MPU_RGDAAC_M3PE_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 10038 #define MPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3PE_SHIFT)) & MPU_RGDAAC_M3PE_MASK)
kadonotakashi 0:8fdf9a60065b 10039 #define MPU_RGDAAC_M4WE_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 10040 #define MPU_RGDAAC_M4WE_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 10041 #define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK)
kadonotakashi 0:8fdf9a60065b 10042 #define MPU_RGDAAC_M4RE_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 10043 #define MPU_RGDAAC_M4RE_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 10044 #define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK)
kadonotakashi 0:8fdf9a60065b 10045 #define MPU_RGDAAC_M5WE_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 10046 #define MPU_RGDAAC_M5WE_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 10047 #define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK)
kadonotakashi 0:8fdf9a60065b 10048 #define MPU_RGDAAC_M5RE_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 10049 #define MPU_RGDAAC_M5RE_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 10050 #define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK)
kadonotakashi 0:8fdf9a60065b 10051 #define MPU_RGDAAC_M6WE_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 10052 #define MPU_RGDAAC_M6WE_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 10053 #define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK)
kadonotakashi 0:8fdf9a60065b 10054 #define MPU_RGDAAC_M6RE_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 10055 #define MPU_RGDAAC_M6RE_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 10056 #define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK)
kadonotakashi 0:8fdf9a60065b 10057 #define MPU_RGDAAC_M7WE_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 10058 #define MPU_RGDAAC_M7WE_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 10059 #define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK)
kadonotakashi 0:8fdf9a60065b 10060 #define MPU_RGDAAC_M7RE_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 10061 #define MPU_RGDAAC_M7RE_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 10062 #define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK)
kadonotakashi 0:8fdf9a60065b 10063
kadonotakashi 0:8fdf9a60065b 10064 /* The count of MPU_RGDAAC */
kadonotakashi 0:8fdf9a60065b 10065 #define MPU_RGDAAC_COUNT (12U)
kadonotakashi 0:8fdf9a60065b 10066
kadonotakashi 0:8fdf9a60065b 10067
kadonotakashi 0:8fdf9a60065b 10068 /*!
kadonotakashi 0:8fdf9a60065b 10069 * @}
kadonotakashi 0:8fdf9a60065b 10070 */ /* end of group MPU_Register_Masks */
kadonotakashi 0:8fdf9a60065b 10071
kadonotakashi 0:8fdf9a60065b 10072
kadonotakashi 0:8fdf9a60065b 10073 /* MPU - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 10074 /** Peripheral MPU base address */
kadonotakashi 0:8fdf9a60065b 10075 #define MPU_BASE (0x4000D000u)
kadonotakashi 0:8fdf9a60065b 10076 /** Peripheral MPU base pointer */
kadonotakashi 0:8fdf9a60065b 10077 #define MPU ((MPU_Type *)MPU_BASE)
kadonotakashi 0:8fdf9a60065b 10078 /** Array initializer of MPU peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 10079 #define MPU_BASE_ADDRS { MPU_BASE }
kadonotakashi 0:8fdf9a60065b 10080 /** Array initializer of MPU peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 10081 #define MPU_BASE_PTRS { MPU }
kadonotakashi 0:8fdf9a60065b 10082
kadonotakashi 0:8fdf9a60065b 10083 /*!
kadonotakashi 0:8fdf9a60065b 10084 * @}
kadonotakashi 0:8fdf9a60065b 10085 */ /* end of group MPU_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 10086
kadonotakashi 0:8fdf9a60065b 10087
kadonotakashi 0:8fdf9a60065b 10088 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10089 -- NV Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10090 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10091
kadonotakashi 0:8fdf9a60065b 10092 /*!
kadonotakashi 0:8fdf9a60065b 10093 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10094 * @{
kadonotakashi 0:8fdf9a60065b 10095 */
kadonotakashi 0:8fdf9a60065b 10096
kadonotakashi 0:8fdf9a60065b 10097 /** NV - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 10098 typedef struct {
kadonotakashi 0:8fdf9a60065b 10099 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 10100 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 10101 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 10102 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
kadonotakashi 0:8fdf9a60065b 10103 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 10104 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
kadonotakashi 0:8fdf9a60065b 10105 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
kadonotakashi 0:8fdf9a60065b 10106 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
kadonotakashi 0:8fdf9a60065b 10107 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 10108 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
kadonotakashi 0:8fdf9a60065b 10109 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
kadonotakashi 0:8fdf9a60065b 10110 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
kadonotakashi 0:8fdf9a60065b 10111 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 10112 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
kadonotakashi 0:8fdf9a60065b 10113 } NV_Type;
kadonotakashi 0:8fdf9a60065b 10114
kadonotakashi 0:8fdf9a60065b 10115 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10116 -- NV Register Masks
kadonotakashi 0:8fdf9a60065b 10117 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10118
kadonotakashi 0:8fdf9a60065b 10119 /*!
kadonotakashi 0:8fdf9a60065b 10120 * @addtogroup NV_Register_Masks NV Register Masks
kadonotakashi 0:8fdf9a60065b 10121 * @{
kadonotakashi 0:8fdf9a60065b 10122 */
kadonotakashi 0:8fdf9a60065b 10123
kadonotakashi 0:8fdf9a60065b 10124 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
kadonotakashi 0:8fdf9a60065b 10125 #define NV_BACKKEY3_KEY_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10126 #define NV_BACKKEY3_KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10127 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10128
kadonotakashi 0:8fdf9a60065b 10129 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
kadonotakashi 0:8fdf9a60065b 10130 #define NV_BACKKEY2_KEY_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10131 #define NV_BACKKEY2_KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10132 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10133
kadonotakashi 0:8fdf9a60065b 10134 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
kadonotakashi 0:8fdf9a60065b 10135 #define NV_BACKKEY1_KEY_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10136 #define NV_BACKKEY1_KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10137 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10138
kadonotakashi 0:8fdf9a60065b 10139 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
kadonotakashi 0:8fdf9a60065b 10140 #define NV_BACKKEY0_KEY_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10141 #define NV_BACKKEY0_KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10142 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10143
kadonotakashi 0:8fdf9a60065b 10144 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
kadonotakashi 0:8fdf9a60065b 10145 #define NV_BACKKEY7_KEY_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10146 #define NV_BACKKEY7_KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10147 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10148
kadonotakashi 0:8fdf9a60065b 10149 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
kadonotakashi 0:8fdf9a60065b 10150 #define NV_BACKKEY6_KEY_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10151 #define NV_BACKKEY6_KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10152 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10153
kadonotakashi 0:8fdf9a60065b 10154 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
kadonotakashi 0:8fdf9a60065b 10155 #define NV_BACKKEY5_KEY_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10156 #define NV_BACKKEY5_KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10157 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10158
kadonotakashi 0:8fdf9a60065b 10159 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
kadonotakashi 0:8fdf9a60065b 10160 #define NV_BACKKEY4_KEY_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10161 #define NV_BACKKEY4_KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10162 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10163
kadonotakashi 0:8fdf9a60065b 10164 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
kadonotakashi 0:8fdf9a60065b 10165 #define NV_FPROT3_PROT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10166 #define NV_FPROT3_PROT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10167 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
kadonotakashi 0:8fdf9a60065b 10168
kadonotakashi 0:8fdf9a60065b 10169 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
kadonotakashi 0:8fdf9a60065b 10170 #define NV_FPROT2_PROT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10171 #define NV_FPROT2_PROT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10172 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
kadonotakashi 0:8fdf9a60065b 10173
kadonotakashi 0:8fdf9a60065b 10174 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
kadonotakashi 0:8fdf9a60065b 10175 #define NV_FPROT1_PROT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10176 #define NV_FPROT1_PROT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10177 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
kadonotakashi 0:8fdf9a60065b 10178
kadonotakashi 0:8fdf9a60065b 10179 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
kadonotakashi 0:8fdf9a60065b 10180 #define NV_FPROT0_PROT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10181 #define NV_FPROT0_PROT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10182 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
kadonotakashi 0:8fdf9a60065b 10183
kadonotakashi 0:8fdf9a60065b 10184 /*! @name FSEC - Non-volatile Flash Security Register */
kadonotakashi 0:8fdf9a60065b 10185 #define NV_FSEC_SEC_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 10186 #define NV_FSEC_SEC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10187 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
kadonotakashi 0:8fdf9a60065b 10188 #define NV_FSEC_FSLACC_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 10189 #define NV_FSEC_FSLACC_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 10190 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
kadonotakashi 0:8fdf9a60065b 10191 #define NV_FSEC_MEEN_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 10192 #define NV_FSEC_MEEN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 10193 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
kadonotakashi 0:8fdf9a60065b 10194 #define NV_FSEC_KEYEN_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 10195 #define NV_FSEC_KEYEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 10196 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
kadonotakashi 0:8fdf9a60065b 10197
kadonotakashi 0:8fdf9a60065b 10198 /*! @name FOPT - Non-volatile Flash Option Register */
kadonotakashi 0:8fdf9a60065b 10199 #define NV_FOPT_LPBOOT_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10200 #define NV_FOPT_LPBOOT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10201 #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
kadonotakashi 0:8fdf9a60065b 10202 #define NV_FOPT_BOOTPIN_OPT_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 10203 #define NV_FOPT_BOOTPIN_OPT_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 10204 #define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK)
kadonotakashi 0:8fdf9a60065b 10205 #define NV_FOPT_NMI_DIS_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 10206 #define NV_FOPT_NMI_DIS_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 10207 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
kadonotakashi 0:8fdf9a60065b 10208 #define NV_FOPT_FAST_INIT_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 10209 #define NV_FOPT_FAST_INIT_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 10210 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
kadonotakashi 0:8fdf9a60065b 10211 #define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 10212 #define NV_FOPT_BOOTSRC_SEL_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 10213 #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK)
kadonotakashi 0:8fdf9a60065b 10214
kadonotakashi 0:8fdf9a60065b 10215
kadonotakashi 0:8fdf9a60065b 10216 /*!
kadonotakashi 0:8fdf9a60065b 10217 * @}
kadonotakashi 0:8fdf9a60065b 10218 */ /* end of group NV_Register_Masks */
kadonotakashi 0:8fdf9a60065b 10219
kadonotakashi 0:8fdf9a60065b 10220
kadonotakashi 0:8fdf9a60065b 10221 /* NV - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 10222 /** Peripheral FTFA_FlashConfig base address */
kadonotakashi 0:8fdf9a60065b 10223 #define FTFA_FlashConfig_BASE (0x400u)
kadonotakashi 0:8fdf9a60065b 10224 /** Peripheral FTFA_FlashConfig base pointer */
kadonotakashi 0:8fdf9a60065b 10225 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
kadonotakashi 0:8fdf9a60065b 10226 /** Array initializer of NV peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 10227 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
kadonotakashi 0:8fdf9a60065b 10228 /** Array initializer of NV peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 10229 #define NV_BASE_PTRS { FTFA_FlashConfig }
kadonotakashi 0:8fdf9a60065b 10230
kadonotakashi 0:8fdf9a60065b 10231 /*!
kadonotakashi 0:8fdf9a60065b 10232 * @}
kadonotakashi 0:8fdf9a60065b 10233 */ /* end of group NV_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 10234
kadonotakashi 0:8fdf9a60065b 10235
kadonotakashi 0:8fdf9a60065b 10236 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10237 -- OSC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10238 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10239
kadonotakashi 0:8fdf9a60065b 10240 /*!
kadonotakashi 0:8fdf9a60065b 10241 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10242 * @{
kadonotakashi 0:8fdf9a60065b 10243 */
kadonotakashi 0:8fdf9a60065b 10244
kadonotakashi 0:8fdf9a60065b 10245 /** OSC - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 10246 typedef struct {
kadonotakashi 0:8fdf9a60065b 10247 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 10248 uint8_t RESERVED_0[1];
kadonotakashi 0:8fdf9a60065b 10249 __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 10250 } OSC_Type;
kadonotakashi 0:8fdf9a60065b 10251
kadonotakashi 0:8fdf9a60065b 10252 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10253 -- OSC Register Masks
kadonotakashi 0:8fdf9a60065b 10254 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10255
kadonotakashi 0:8fdf9a60065b 10256 /*!
kadonotakashi 0:8fdf9a60065b 10257 * @addtogroup OSC_Register_Masks OSC Register Masks
kadonotakashi 0:8fdf9a60065b 10258 * @{
kadonotakashi 0:8fdf9a60065b 10259 */
kadonotakashi 0:8fdf9a60065b 10260
kadonotakashi 0:8fdf9a60065b 10261 /*! @name CR - OSC Control Register */
kadonotakashi 0:8fdf9a60065b 10262 #define OSC_CR_SC16P_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10263 #define OSC_CR_SC16P_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10264 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
kadonotakashi 0:8fdf9a60065b 10265 #define OSC_CR_SC8P_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 10266 #define OSC_CR_SC8P_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 10267 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
kadonotakashi 0:8fdf9a60065b 10268 #define OSC_CR_SC4P_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 10269 #define OSC_CR_SC4P_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 10270 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
kadonotakashi 0:8fdf9a60065b 10271 #define OSC_CR_SC2P_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 10272 #define OSC_CR_SC2P_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 10273 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
kadonotakashi 0:8fdf9a60065b 10274 #define OSC_CR_EREFSTEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 10275 #define OSC_CR_EREFSTEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 10276 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
kadonotakashi 0:8fdf9a60065b 10277 #define OSC_CR_ERCLKEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 10278 #define OSC_CR_ERCLKEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 10279 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
kadonotakashi 0:8fdf9a60065b 10280
kadonotakashi 0:8fdf9a60065b 10281 /*! @name DIV - OSC_DIV */
kadonotakashi 0:8fdf9a60065b 10282 #define OSC_DIV_ERPS_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 10283 #define OSC_DIV_ERPS_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 10284 #define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
kadonotakashi 0:8fdf9a60065b 10285
kadonotakashi 0:8fdf9a60065b 10286
kadonotakashi 0:8fdf9a60065b 10287 /*!
kadonotakashi 0:8fdf9a60065b 10288 * @}
kadonotakashi 0:8fdf9a60065b 10289 */ /* end of group OSC_Register_Masks */
kadonotakashi 0:8fdf9a60065b 10290
kadonotakashi 0:8fdf9a60065b 10291
kadonotakashi 0:8fdf9a60065b 10292 /* OSC - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 10293 /** Peripheral OSC base address */
kadonotakashi 0:8fdf9a60065b 10294 #define OSC_BASE (0x40065000u)
kadonotakashi 0:8fdf9a60065b 10295 /** Peripheral OSC base pointer */
kadonotakashi 0:8fdf9a60065b 10296 #define OSC ((OSC_Type *)OSC_BASE)
kadonotakashi 0:8fdf9a60065b 10297 /** Array initializer of OSC peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 10298 #define OSC_BASE_ADDRS { OSC_BASE }
kadonotakashi 0:8fdf9a60065b 10299 /** Array initializer of OSC peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 10300 #define OSC_BASE_PTRS { OSC }
kadonotakashi 0:8fdf9a60065b 10301
kadonotakashi 0:8fdf9a60065b 10302 /*!
kadonotakashi 0:8fdf9a60065b 10303 * @}
kadonotakashi 0:8fdf9a60065b 10304 */ /* end of group OSC_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 10305
kadonotakashi 0:8fdf9a60065b 10306
kadonotakashi 0:8fdf9a60065b 10307 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10308 -- OTFAD Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10309 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10310
kadonotakashi 0:8fdf9a60065b 10311 /*!
kadonotakashi 0:8fdf9a60065b 10312 * @addtogroup OTFAD_Peripheral_Access_Layer OTFAD Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10313 * @{
kadonotakashi 0:8fdf9a60065b 10314 */
kadonotakashi 0:8fdf9a60065b 10315
kadonotakashi 0:8fdf9a60065b 10316 /** OTFAD - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 10317 typedef struct {
kadonotakashi 0:8fdf9a60065b 10318 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 10319 __I uint32_t SR; /**< Status Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 10320 __IO uint32_t CRC; /**< Cyclic Redundancy Check Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 10321 uint8_t RESERVED_0[244];
kadonotakashi 0:8fdf9a60065b 10322 struct { /* offset: 0x100, array step: 0x40 */
kadonotakashi 0:8fdf9a60065b 10323 __IO uint32_t CTX_KEY[4]; /**< AES Key Word0..AES Key Word3, array offset: 0x100, array step: index*0x40, index2*0x4 */
kadonotakashi 0:8fdf9a60065b 10324 __IO uint32_t CTX_CTR[2]; /**< AES Counter Word0..AES Counter Word1, array offset: 0x110, array step: index*0x40, index2*0x4 */
kadonotakashi 0:8fdf9a60065b 10325 __IO uint32_t CTX_RGD[2]; /**< AES Region Descriptor Word0..AES Region Descriptor Word1, array offset: 0x118, array step: index*0x40, index2*0x4 */
kadonotakashi 0:8fdf9a60065b 10326 uint8_t RESERVED_0[32];
kadonotakashi 0:8fdf9a60065b 10327 } CTX[4];
kadonotakashi 0:8fdf9a60065b 10328 } OTFAD_Type;
kadonotakashi 0:8fdf9a60065b 10329
kadonotakashi 0:8fdf9a60065b 10330 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10331 -- OTFAD Register Masks
kadonotakashi 0:8fdf9a60065b 10332 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10333
kadonotakashi 0:8fdf9a60065b 10334 /*!
kadonotakashi 0:8fdf9a60065b 10335 * @addtogroup OTFAD_Register_Masks OTFAD Register Masks
kadonotakashi 0:8fdf9a60065b 10336 * @{
kadonotakashi 0:8fdf9a60065b 10337 */
kadonotakashi 0:8fdf9a60065b 10338
kadonotakashi 0:8fdf9a60065b 10339 /*! @name CR - Control Register */
kadonotakashi 0:8fdf9a60065b 10340 #define OTFAD_CR_FSVM_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 10341 #define OTFAD_CR_FSVM_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 10342 #define OTFAD_CR_FSVM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FSVM_SHIFT)) & OTFAD_CR_FSVM_MASK)
kadonotakashi 0:8fdf9a60065b 10343 #define OTFAD_CR_FLDM_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 10344 #define OTFAD_CR_FLDM_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 10345 #define OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)
kadonotakashi 0:8fdf9a60065b 10346 #define OTFAD_CR_RRAE_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 10347 #define OTFAD_CR_RRAE_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 10348 #define OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)
kadonotakashi 0:8fdf9a60065b 10349 #define OTFAD_CR_CCTX_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 10350 #define OTFAD_CR_CCTX_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 10351 #define OTFAD_CR_CCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CCTX_SHIFT)) & OTFAD_CR_CCTX_MASK)
kadonotakashi 0:8fdf9a60065b 10352 #define OTFAD_CR_CRCE_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 10353 #define OTFAD_CR_CRCE_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 10354 #define OTFAD_CR_CRCE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CRCE_SHIFT)) & OTFAD_CR_CRCE_MASK)
kadonotakashi 0:8fdf9a60065b 10355 #define OTFAD_CR_CRCI_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 10356 #define OTFAD_CR_CRCI_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 10357 #define OTFAD_CR_CRCI(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CRCI_SHIFT)) & OTFAD_CR_CRCI_MASK)
kadonotakashi 0:8fdf9a60065b 10358 #define OTFAD_CR_GE_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 10359 #define OTFAD_CR_GE_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 10360 #define OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)
kadonotakashi 0:8fdf9a60065b 10361
kadonotakashi 0:8fdf9a60065b 10362 /*! @name SR - Status Register */
kadonotakashi 0:8fdf9a60065b 10363 #define OTFAD_SR_MDPCP_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 10364 #define OTFAD_SR_MDPCP_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 10365 #define OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)
kadonotakashi 0:8fdf9a60065b 10366 #define OTFAD_SR_MODE_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 10367 #define OTFAD_SR_MODE_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 10368 #define OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)
kadonotakashi 0:8fdf9a60065b 10369 #define OTFAD_SR_NCTX_MASK (0xF0U)
kadonotakashi 0:8fdf9a60065b 10370 #define OTFAD_SR_NCTX_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 10371 #define OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)
kadonotakashi 0:8fdf9a60065b 10372 #define OTFAD_SR_HRL_MASK (0xF000000U)
kadonotakashi 0:8fdf9a60065b 10373 #define OTFAD_SR_HRL_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 10374 #define OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)
kadonotakashi 0:8fdf9a60065b 10375 #define OTFAD_SR_RRAM_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 10376 #define OTFAD_SR_RRAM_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 10377 #define OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
kadonotakashi 0:8fdf9a60065b 10378 #define OTFAD_SR_GEM_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 10379 #define OTFAD_SR_GEM_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 10380 #define OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)
kadonotakashi 0:8fdf9a60065b 10381
kadonotakashi 0:8fdf9a60065b 10382 /*! @name CRC - Cyclic Redundancy Check Register */
kadonotakashi 0:8fdf9a60065b 10383 #define OTFAD_CRC_CRCD_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 10384 #define OTFAD_CRC_CRCD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10385 #define OTFAD_CRC_CRCD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CRC_CRCD_SHIFT)) & OTFAD_CRC_CRCD_MASK)
kadonotakashi 0:8fdf9a60065b 10386
kadonotakashi 0:8fdf9a60065b 10387 /*! @name CTX_KEY - AES Key Word0..AES Key Word3 */
kadonotakashi 0:8fdf9a60065b 10388 #define OTFAD_CTX_KEY_W0KEY_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 10389 #define OTFAD_CTX_KEY_W0KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10390 #define OTFAD_CTX_KEY_W0KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W0KEY_SHIFT)) & OTFAD_CTX_KEY_W0KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10391 #define OTFAD_CTX_KEY_W1KEY_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 10392 #define OTFAD_CTX_KEY_W1KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10393 #define OTFAD_CTX_KEY_W1KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W1KEY_SHIFT)) & OTFAD_CTX_KEY_W1KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10394 #define OTFAD_CTX_KEY_W2KEY_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 10395 #define OTFAD_CTX_KEY_W2KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10396 #define OTFAD_CTX_KEY_W2KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W2KEY_SHIFT)) & OTFAD_CTX_KEY_W2KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10397 #define OTFAD_CTX_KEY_W3KEY_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 10398 #define OTFAD_CTX_KEY_W3KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10399 #define OTFAD_CTX_KEY_W3KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W3KEY_SHIFT)) & OTFAD_CTX_KEY_W3KEY_MASK)
kadonotakashi 0:8fdf9a60065b 10400
kadonotakashi 0:8fdf9a60065b 10401 /* The count of OTFAD_CTX_KEY */
kadonotakashi 0:8fdf9a60065b 10402 #define OTFAD_CTX_KEY_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 10403
kadonotakashi 0:8fdf9a60065b 10404 /* The count of OTFAD_CTX_KEY */
kadonotakashi 0:8fdf9a60065b 10405 #define OTFAD_CTX_KEY_COUNT2 (4U)
kadonotakashi 0:8fdf9a60065b 10406
kadonotakashi 0:8fdf9a60065b 10407 /*! @name CTX_CTR - AES Counter Word0..AES Counter Word1 */
kadonotakashi 0:8fdf9a60065b 10408 #define OTFAD_CTX_CTR_W0CTR_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 10409 #define OTFAD_CTX_CTR_W0CTR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10410 #define OTFAD_CTX_CTR_W0CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_CTR_W0CTR_SHIFT)) & OTFAD_CTX_CTR_W0CTR_MASK)
kadonotakashi 0:8fdf9a60065b 10411 #define OTFAD_CTX_CTR_W1CTR_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 10412 #define OTFAD_CTX_CTR_W1CTR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10413 #define OTFAD_CTX_CTR_W1CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_CTR_W1CTR_SHIFT)) & OTFAD_CTX_CTR_W1CTR_MASK)
kadonotakashi 0:8fdf9a60065b 10414
kadonotakashi 0:8fdf9a60065b 10415 /* The count of OTFAD_CTX_CTR */
kadonotakashi 0:8fdf9a60065b 10416 #define OTFAD_CTX_CTR_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 10417
kadonotakashi 0:8fdf9a60065b 10418 /* The count of OTFAD_CTX_CTR */
kadonotakashi 0:8fdf9a60065b 10419 #define OTFAD_CTX_CTR_COUNT2 (2U)
kadonotakashi 0:8fdf9a60065b 10420
kadonotakashi 0:8fdf9a60065b 10421 /*! @name CTX_RGD - AES Region Descriptor Word0..AES Region Descriptor Word1 */
kadonotakashi 0:8fdf9a60065b 10422 #define OTFAD_CTX_RGD_VLD_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10423 #define OTFAD_CTX_RGD_VLD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10424 #define OTFAD_CTX_RGD_VLD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_VLD_SHIFT)) & OTFAD_CTX_RGD_VLD_MASK)
kadonotakashi 0:8fdf9a60065b 10425 #define OTFAD_CTX_RGD_ADE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 10426 #define OTFAD_CTX_RGD_ADE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 10427 #define OTFAD_CTX_RGD_ADE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_ADE_SHIFT)) & OTFAD_CTX_RGD_ADE_MASK)
kadonotakashi 0:8fdf9a60065b 10428 #define OTFAD_CTX_RGD_RO_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 10429 #define OTFAD_CTX_RGD_RO_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 10430 #define OTFAD_CTX_RGD_RO(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_RO_SHIFT)) & OTFAD_CTX_RGD_RO_MASK)
kadonotakashi 0:8fdf9a60065b 10431 #define OTFAD_CTX_RGD_ENDADDR_MASK (0xFFFFFC00U)
kadonotakashi 0:8fdf9a60065b 10432 #define OTFAD_CTX_RGD_ENDADDR_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 10433 #define OTFAD_CTX_RGD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_ENDADDR_SHIFT)) & OTFAD_CTX_RGD_ENDADDR_MASK)
kadonotakashi 0:8fdf9a60065b 10434 #define OTFAD_CTX_RGD_SRTADDR_MASK (0xFFFFFC00U)
kadonotakashi 0:8fdf9a60065b 10435 #define OTFAD_CTX_RGD_SRTADDR_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 10436 #define OTFAD_CTX_RGD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_SRTADDR_SHIFT)) & OTFAD_CTX_RGD_SRTADDR_MASK)
kadonotakashi 0:8fdf9a60065b 10437
kadonotakashi 0:8fdf9a60065b 10438 /* The count of OTFAD_CTX_RGD */
kadonotakashi 0:8fdf9a60065b 10439 #define OTFAD_CTX_RGD_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 10440
kadonotakashi 0:8fdf9a60065b 10441 /* The count of OTFAD_CTX_RGD */
kadonotakashi 0:8fdf9a60065b 10442 #define OTFAD_CTX_RGD_COUNT2 (2U)
kadonotakashi 0:8fdf9a60065b 10443
kadonotakashi 0:8fdf9a60065b 10444
kadonotakashi 0:8fdf9a60065b 10445 /*!
kadonotakashi 0:8fdf9a60065b 10446 * @}
kadonotakashi 0:8fdf9a60065b 10447 */ /* end of group OTFAD_Register_Masks */
kadonotakashi 0:8fdf9a60065b 10448
kadonotakashi 0:8fdf9a60065b 10449
kadonotakashi 0:8fdf9a60065b 10450 /* OTFAD - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 10451 /** Peripheral OTFAD base address */
kadonotakashi 0:8fdf9a60065b 10452 #define OTFAD_BASE (0x400DAC00u)
kadonotakashi 0:8fdf9a60065b 10453 /** Peripheral OTFAD base pointer */
kadonotakashi 0:8fdf9a60065b 10454 #define OTFAD ((OTFAD_Type *)OTFAD_BASE)
kadonotakashi 0:8fdf9a60065b 10455 /** Array initializer of OTFAD peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 10456 #define OTFAD_BASE_ADDRS { OTFAD_BASE }
kadonotakashi 0:8fdf9a60065b 10457 /** Array initializer of OTFAD peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 10458 #define OTFAD_BASE_PTRS { OTFAD }
kadonotakashi 0:8fdf9a60065b 10459
kadonotakashi 0:8fdf9a60065b 10460 /*!
kadonotakashi 0:8fdf9a60065b 10461 * @}
kadonotakashi 0:8fdf9a60065b 10462 */ /* end of group OTFAD_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 10463
kadonotakashi 0:8fdf9a60065b 10464
kadonotakashi 0:8fdf9a60065b 10465 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10466 -- PDB Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10467 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10468
kadonotakashi 0:8fdf9a60065b 10469 /*!
kadonotakashi 0:8fdf9a60065b 10470 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10471 * @{
kadonotakashi 0:8fdf9a60065b 10472 */
kadonotakashi 0:8fdf9a60065b 10473
kadonotakashi 0:8fdf9a60065b 10474 /** PDB - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 10475 typedef struct {
kadonotakashi 0:8fdf9a60065b 10476 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 10477 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 10478 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 10479 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 10480 struct { /* offset: 0x10, array step: 0x10 */
kadonotakashi 0:8fdf9a60065b 10481 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x10 */
kadonotakashi 0:8fdf9a60065b 10482 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x10 */
kadonotakashi 0:8fdf9a60065b 10483 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x10, index2*0x4 */
kadonotakashi 0:8fdf9a60065b 10484 } CH[1];
kadonotakashi 0:8fdf9a60065b 10485 uint8_t RESERVED_0[304];
kadonotakashi 0:8fdf9a60065b 10486 struct { /* offset: 0x150, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 10487 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 10488 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 10489 } DAC[1];
kadonotakashi 0:8fdf9a60065b 10490 uint8_t RESERVED_1[56];
kadonotakashi 0:8fdf9a60065b 10491 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
kadonotakashi 0:8fdf9a60065b 10492 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 10493 } PDB_Type;
kadonotakashi 0:8fdf9a60065b 10494
kadonotakashi 0:8fdf9a60065b 10495 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10496 -- PDB Register Masks
kadonotakashi 0:8fdf9a60065b 10497 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10498
kadonotakashi 0:8fdf9a60065b 10499 /*!
kadonotakashi 0:8fdf9a60065b 10500 * @addtogroup PDB_Register_Masks PDB Register Masks
kadonotakashi 0:8fdf9a60065b 10501 * @{
kadonotakashi 0:8fdf9a60065b 10502 */
kadonotakashi 0:8fdf9a60065b 10503
kadonotakashi 0:8fdf9a60065b 10504 /*! @name SC - Status and Control register */
kadonotakashi 0:8fdf9a60065b 10505 #define PDB_SC_LDOK_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10506 #define PDB_SC_LDOK_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10507 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
kadonotakashi 0:8fdf9a60065b 10508 #define PDB_SC_CONT_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 10509 #define PDB_SC_CONT_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 10510 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
kadonotakashi 0:8fdf9a60065b 10511 #define PDB_SC_MULT_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 10512 #define PDB_SC_MULT_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 10513 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
kadonotakashi 0:8fdf9a60065b 10514 #define PDB_SC_PDBIE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 10515 #define PDB_SC_PDBIE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 10516 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
kadonotakashi 0:8fdf9a60065b 10517 #define PDB_SC_PDBIF_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 10518 #define PDB_SC_PDBIF_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 10519 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
kadonotakashi 0:8fdf9a60065b 10520 #define PDB_SC_PDBEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 10521 #define PDB_SC_PDBEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 10522 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
kadonotakashi 0:8fdf9a60065b 10523 #define PDB_SC_TRGSEL_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 10524 #define PDB_SC_TRGSEL_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 10525 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
kadonotakashi 0:8fdf9a60065b 10526 #define PDB_SC_PRESCALER_MASK (0x7000U)
kadonotakashi 0:8fdf9a60065b 10527 #define PDB_SC_PRESCALER_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 10528 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
kadonotakashi 0:8fdf9a60065b 10529 #define PDB_SC_DMAEN_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 10530 #define PDB_SC_DMAEN_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 10531 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
kadonotakashi 0:8fdf9a60065b 10532 #define PDB_SC_SWTRIG_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 10533 #define PDB_SC_SWTRIG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 10534 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
kadonotakashi 0:8fdf9a60065b 10535 #define PDB_SC_PDBEIE_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 10536 #define PDB_SC_PDBEIE_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 10537 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
kadonotakashi 0:8fdf9a60065b 10538 #define PDB_SC_LDMOD_MASK (0xC0000U)
kadonotakashi 0:8fdf9a60065b 10539 #define PDB_SC_LDMOD_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 10540 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
kadonotakashi 0:8fdf9a60065b 10541
kadonotakashi 0:8fdf9a60065b 10542 /*! @name MOD - Modulus register */
kadonotakashi 0:8fdf9a60065b 10543 #define PDB_MOD_MOD_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 10544 #define PDB_MOD_MOD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10545 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
kadonotakashi 0:8fdf9a60065b 10546
kadonotakashi 0:8fdf9a60065b 10547 /*! @name CNT - Counter register */
kadonotakashi 0:8fdf9a60065b 10548 #define PDB_CNT_CNT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 10549 #define PDB_CNT_CNT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10550 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
kadonotakashi 0:8fdf9a60065b 10551
kadonotakashi 0:8fdf9a60065b 10552 /*! @name IDLY - Interrupt Delay register */
kadonotakashi 0:8fdf9a60065b 10553 #define PDB_IDLY_IDLY_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 10554 #define PDB_IDLY_IDLY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10555 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
kadonotakashi 0:8fdf9a60065b 10556
kadonotakashi 0:8fdf9a60065b 10557 /*! @name C1 - Channel n Control register 1 */
kadonotakashi 0:8fdf9a60065b 10558 #define PDB_C1_EN_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10559 #define PDB_C1_EN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10560 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
kadonotakashi 0:8fdf9a60065b 10561 #define PDB_C1_TOS_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 10562 #define PDB_C1_TOS_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 10563 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
kadonotakashi 0:8fdf9a60065b 10564 #define PDB_C1_BB_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 10565 #define PDB_C1_BB_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 10566 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
kadonotakashi 0:8fdf9a60065b 10567
kadonotakashi 0:8fdf9a60065b 10568 /* The count of PDB_C1 */
kadonotakashi 0:8fdf9a60065b 10569 #define PDB_C1_COUNT (1U)
kadonotakashi 0:8fdf9a60065b 10570
kadonotakashi 0:8fdf9a60065b 10571 /*! @name S - Channel n Status register */
kadonotakashi 0:8fdf9a60065b 10572 #define PDB_S_ERR_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10573 #define PDB_S_ERR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10574 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
kadonotakashi 0:8fdf9a60065b 10575 #define PDB_S_CF_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 10576 #define PDB_S_CF_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 10577 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
kadonotakashi 0:8fdf9a60065b 10578
kadonotakashi 0:8fdf9a60065b 10579 /* The count of PDB_S */
kadonotakashi 0:8fdf9a60065b 10580 #define PDB_S_COUNT (1U)
kadonotakashi 0:8fdf9a60065b 10581
kadonotakashi 0:8fdf9a60065b 10582 /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
kadonotakashi 0:8fdf9a60065b 10583 #define PDB_DLY_DLY_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 10584 #define PDB_DLY_DLY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10585 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
kadonotakashi 0:8fdf9a60065b 10586
kadonotakashi 0:8fdf9a60065b 10587 /* The count of PDB_DLY */
kadonotakashi 0:8fdf9a60065b 10588 #define PDB_DLY_COUNT (1U)
kadonotakashi 0:8fdf9a60065b 10589
kadonotakashi 0:8fdf9a60065b 10590 /* The count of PDB_DLY */
kadonotakashi 0:8fdf9a60065b 10591 #define PDB_DLY_COUNT2 (2U)
kadonotakashi 0:8fdf9a60065b 10592
kadonotakashi 0:8fdf9a60065b 10593 /*! @name INTC - DAC Interval Trigger n Control register */
kadonotakashi 0:8fdf9a60065b 10594 #define PDB_INTC_TOE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10595 #define PDB_INTC_TOE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10596 #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
kadonotakashi 0:8fdf9a60065b 10597 #define PDB_INTC_EXT_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 10598 #define PDB_INTC_EXT_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 10599 #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
kadonotakashi 0:8fdf9a60065b 10600
kadonotakashi 0:8fdf9a60065b 10601 /* The count of PDB_INTC */
kadonotakashi 0:8fdf9a60065b 10602 #define PDB_INTC_COUNT (1U)
kadonotakashi 0:8fdf9a60065b 10603
kadonotakashi 0:8fdf9a60065b 10604 /*! @name INT - DAC Interval n register */
kadonotakashi 0:8fdf9a60065b 10605 #define PDB_INT_INT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 10606 #define PDB_INT_INT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10607 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
kadonotakashi 0:8fdf9a60065b 10608
kadonotakashi 0:8fdf9a60065b 10609 /* The count of PDB_INT */
kadonotakashi 0:8fdf9a60065b 10610 #define PDB_INT_COUNT (1U)
kadonotakashi 0:8fdf9a60065b 10611
kadonotakashi 0:8fdf9a60065b 10612 /*! @name POEN - Pulse-Out n Enable register */
kadonotakashi 0:8fdf9a60065b 10613 #define PDB_POEN_POEN_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 10614 #define PDB_POEN_POEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10615 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
kadonotakashi 0:8fdf9a60065b 10616
kadonotakashi 0:8fdf9a60065b 10617 /*! @name PODLY - Pulse-Out n Delay register */
kadonotakashi 0:8fdf9a60065b 10618 #define PDB_PODLY_DLY2_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 10619 #define PDB_PODLY_DLY2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10620 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
kadonotakashi 0:8fdf9a60065b 10621 #define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 10622 #define PDB_PODLY_DLY1_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 10623 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
kadonotakashi 0:8fdf9a60065b 10624
kadonotakashi 0:8fdf9a60065b 10625 /* The count of PDB_PODLY */
kadonotakashi 0:8fdf9a60065b 10626 #define PDB_PODLY_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 10627
kadonotakashi 0:8fdf9a60065b 10628
kadonotakashi 0:8fdf9a60065b 10629 /*!
kadonotakashi 0:8fdf9a60065b 10630 * @}
kadonotakashi 0:8fdf9a60065b 10631 */ /* end of group PDB_Register_Masks */
kadonotakashi 0:8fdf9a60065b 10632
kadonotakashi 0:8fdf9a60065b 10633
kadonotakashi 0:8fdf9a60065b 10634 /* PDB - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 10635 /** Peripheral PDB0 base address */
kadonotakashi 0:8fdf9a60065b 10636 #define PDB0_BASE (0x40036000u)
kadonotakashi 0:8fdf9a60065b 10637 /** Peripheral PDB0 base pointer */
kadonotakashi 0:8fdf9a60065b 10638 #define PDB0 ((PDB_Type *)PDB0_BASE)
kadonotakashi 0:8fdf9a60065b 10639 /** Array initializer of PDB peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 10640 #define PDB_BASE_ADDRS { PDB0_BASE }
kadonotakashi 0:8fdf9a60065b 10641 /** Array initializer of PDB peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 10642 #define PDB_BASE_PTRS { PDB0 }
kadonotakashi 0:8fdf9a60065b 10643 /** Interrupt vectors for the PDB peripheral type */
kadonotakashi 0:8fdf9a60065b 10644 #define PDB_IRQS { PDB0_IRQn }
kadonotakashi 0:8fdf9a60065b 10645
kadonotakashi 0:8fdf9a60065b 10646 /*!
kadonotakashi 0:8fdf9a60065b 10647 * @}
kadonotakashi 0:8fdf9a60065b 10648 */ /* end of group PDB_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 10649
kadonotakashi 0:8fdf9a60065b 10650
kadonotakashi 0:8fdf9a60065b 10651 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10652 -- PIT Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10653 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10654
kadonotakashi 0:8fdf9a60065b 10655 /*!
kadonotakashi 0:8fdf9a60065b 10656 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10657 * @{
kadonotakashi 0:8fdf9a60065b 10658 */
kadonotakashi 0:8fdf9a60065b 10659
kadonotakashi 0:8fdf9a60065b 10660 /** PIT - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 10661 typedef struct {
kadonotakashi 0:8fdf9a60065b 10662 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 10663 uint8_t RESERVED_0[252];
kadonotakashi 0:8fdf9a60065b 10664 struct { /* offset: 0x100, array step: 0x10 */
kadonotakashi 0:8fdf9a60065b 10665 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
kadonotakashi 0:8fdf9a60065b 10666 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
kadonotakashi 0:8fdf9a60065b 10667 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
kadonotakashi 0:8fdf9a60065b 10668 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
kadonotakashi 0:8fdf9a60065b 10669 } CHANNEL[4];
kadonotakashi 0:8fdf9a60065b 10670 } PIT_Type;
kadonotakashi 0:8fdf9a60065b 10671
kadonotakashi 0:8fdf9a60065b 10672 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10673 -- PIT Register Masks
kadonotakashi 0:8fdf9a60065b 10674 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10675
kadonotakashi 0:8fdf9a60065b 10676 /*!
kadonotakashi 0:8fdf9a60065b 10677 * @addtogroup PIT_Register_Masks PIT Register Masks
kadonotakashi 0:8fdf9a60065b 10678 * @{
kadonotakashi 0:8fdf9a60065b 10679 */
kadonotakashi 0:8fdf9a60065b 10680
kadonotakashi 0:8fdf9a60065b 10681 /*! @name MCR - PIT Module Control Register */
kadonotakashi 0:8fdf9a60065b 10682 #define PIT_MCR_FRZ_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10683 #define PIT_MCR_FRZ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10684 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
kadonotakashi 0:8fdf9a60065b 10685 #define PIT_MCR_MDIS_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 10686 #define PIT_MCR_MDIS_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 10687 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
kadonotakashi 0:8fdf9a60065b 10688
kadonotakashi 0:8fdf9a60065b 10689 /*! @name LDVAL - Timer Load Value Register */
kadonotakashi 0:8fdf9a60065b 10690 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 10691 #define PIT_LDVAL_TSV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10692 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
kadonotakashi 0:8fdf9a60065b 10693
kadonotakashi 0:8fdf9a60065b 10694 /* The count of PIT_LDVAL */
kadonotakashi 0:8fdf9a60065b 10695 #define PIT_LDVAL_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 10696
kadonotakashi 0:8fdf9a60065b 10697 /*! @name CVAL - Current Timer Value Register */
kadonotakashi 0:8fdf9a60065b 10698 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 10699 #define PIT_CVAL_TVL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10700 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
kadonotakashi 0:8fdf9a60065b 10701
kadonotakashi 0:8fdf9a60065b 10702 /* The count of PIT_CVAL */
kadonotakashi 0:8fdf9a60065b 10703 #define PIT_CVAL_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 10704
kadonotakashi 0:8fdf9a60065b 10705 /*! @name TCTRL - Timer Control Register */
kadonotakashi 0:8fdf9a60065b 10706 #define PIT_TCTRL_TEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10707 #define PIT_TCTRL_TEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10708 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
kadonotakashi 0:8fdf9a60065b 10709 #define PIT_TCTRL_TIE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 10710 #define PIT_TCTRL_TIE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 10711 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
kadonotakashi 0:8fdf9a60065b 10712 #define PIT_TCTRL_CHN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 10713 #define PIT_TCTRL_CHN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 10714 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
kadonotakashi 0:8fdf9a60065b 10715
kadonotakashi 0:8fdf9a60065b 10716 /* The count of PIT_TCTRL */
kadonotakashi 0:8fdf9a60065b 10717 #define PIT_TCTRL_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 10718
kadonotakashi 0:8fdf9a60065b 10719 /*! @name TFLG - Timer Flag Register */
kadonotakashi 0:8fdf9a60065b 10720 #define PIT_TFLG_TIF_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10721 #define PIT_TFLG_TIF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10722 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
kadonotakashi 0:8fdf9a60065b 10723
kadonotakashi 0:8fdf9a60065b 10724 /* The count of PIT_TFLG */
kadonotakashi 0:8fdf9a60065b 10725 #define PIT_TFLG_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 10726
kadonotakashi 0:8fdf9a60065b 10727
kadonotakashi 0:8fdf9a60065b 10728 /*!
kadonotakashi 0:8fdf9a60065b 10729 * @}
kadonotakashi 0:8fdf9a60065b 10730 */ /* end of group PIT_Register_Masks */
kadonotakashi 0:8fdf9a60065b 10731
kadonotakashi 0:8fdf9a60065b 10732
kadonotakashi 0:8fdf9a60065b 10733 /* PIT - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 10734 /** Peripheral PIT0 base address */
kadonotakashi 0:8fdf9a60065b 10735 #define PIT0_BASE (0x40037000u)
kadonotakashi 0:8fdf9a60065b 10736 /** Peripheral PIT0 base pointer */
kadonotakashi 0:8fdf9a60065b 10737 #define PIT0 ((PIT_Type *)PIT0_BASE)
kadonotakashi 0:8fdf9a60065b 10738 /** Array initializer of PIT peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 10739 #define PIT_BASE_ADDRS { PIT0_BASE }
kadonotakashi 0:8fdf9a60065b 10740 /** Array initializer of PIT peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 10741 #define PIT_BASE_PTRS { PIT0 }
kadonotakashi 0:8fdf9a60065b 10742 /** Interrupt vectors for the PIT peripheral type */
kadonotakashi 0:8fdf9a60065b 10743 #define PIT_IRQS { PIT0CH0_IRQn, PIT0CH1_IRQn, PIT0CH2_IRQn, PIT0CH3_IRQn }
kadonotakashi 0:8fdf9a60065b 10744
kadonotakashi 0:8fdf9a60065b 10745 /*!
kadonotakashi 0:8fdf9a60065b 10746 * @}
kadonotakashi 0:8fdf9a60065b 10747 */ /* end of group PIT_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 10748
kadonotakashi 0:8fdf9a60065b 10749
kadonotakashi 0:8fdf9a60065b 10750 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10751 -- PMC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10752 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10753
kadonotakashi 0:8fdf9a60065b 10754 /*!
kadonotakashi 0:8fdf9a60065b 10755 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10756 * @{
kadonotakashi 0:8fdf9a60065b 10757 */
kadonotakashi 0:8fdf9a60065b 10758
kadonotakashi 0:8fdf9a60065b 10759 /** PMC - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 10760 typedef struct {
kadonotakashi 0:8fdf9a60065b 10761 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 10762 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 10763 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 10764 uint8_t RESERVED_0[8];
kadonotakashi 0:8fdf9a60065b 10765 __IO uint8_t HVDSC1; /**< High Voltage Detect Status And Control 1 register, offset: 0xB */
kadonotakashi 0:8fdf9a60065b 10766 } PMC_Type;
kadonotakashi 0:8fdf9a60065b 10767
kadonotakashi 0:8fdf9a60065b 10768 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10769 -- PMC Register Masks
kadonotakashi 0:8fdf9a60065b 10770 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10771
kadonotakashi 0:8fdf9a60065b 10772 /*!
kadonotakashi 0:8fdf9a60065b 10773 * @addtogroup PMC_Register_Masks PMC Register Masks
kadonotakashi 0:8fdf9a60065b 10774 * @{
kadonotakashi 0:8fdf9a60065b 10775 */
kadonotakashi 0:8fdf9a60065b 10776
kadonotakashi 0:8fdf9a60065b 10777 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
kadonotakashi 0:8fdf9a60065b 10778 #define PMC_LVDSC1_LVDV_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 10779 #define PMC_LVDSC1_LVDV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10780 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
kadonotakashi 0:8fdf9a60065b 10781 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 10782 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 10783 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
kadonotakashi 0:8fdf9a60065b 10784 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 10785 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 10786 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
kadonotakashi 0:8fdf9a60065b 10787 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 10788 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 10789 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
kadonotakashi 0:8fdf9a60065b 10790 #define PMC_LVDSC1_LVDF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 10791 #define PMC_LVDSC1_LVDF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 10792 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
kadonotakashi 0:8fdf9a60065b 10793
kadonotakashi 0:8fdf9a60065b 10794 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
kadonotakashi 0:8fdf9a60065b 10795 #define PMC_LVDSC2_LVWV_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 10796 #define PMC_LVDSC2_LVWV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10797 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
kadonotakashi 0:8fdf9a60065b 10798 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 10799 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 10800 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
kadonotakashi 0:8fdf9a60065b 10801 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 10802 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 10803 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
kadonotakashi 0:8fdf9a60065b 10804 #define PMC_LVDSC2_LVWF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 10805 #define PMC_LVDSC2_LVWF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 10806 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
kadonotakashi 0:8fdf9a60065b 10807
kadonotakashi 0:8fdf9a60065b 10808 /*! @name REGSC - Regulator Status And Control register */
kadonotakashi 0:8fdf9a60065b 10809 #define PMC_REGSC_BGBE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10810 #define PMC_REGSC_BGBE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10811 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
kadonotakashi 0:8fdf9a60065b 10812 #define PMC_REGSC_REGONS_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 10813 #define PMC_REGSC_REGONS_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 10814 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
kadonotakashi 0:8fdf9a60065b 10815 #define PMC_REGSC_ACKISO_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 10816 #define PMC_REGSC_ACKISO_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 10817 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
kadonotakashi 0:8fdf9a60065b 10818 #define PMC_REGSC_BGEN_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 10819 #define PMC_REGSC_BGEN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 10820 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
kadonotakashi 0:8fdf9a60065b 10821
kadonotakashi 0:8fdf9a60065b 10822 /*! @name HVDSC1 - High Voltage Detect Status And Control 1 register */
kadonotakashi 0:8fdf9a60065b 10823 #define PMC_HVDSC1_HVDV_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10824 #define PMC_HVDSC1_HVDV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10825 #define PMC_HVDSC1_HVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDV_SHIFT)) & PMC_HVDSC1_HVDV_MASK)
kadonotakashi 0:8fdf9a60065b 10826 #define PMC_HVDSC1_HVDRE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 10827 #define PMC_HVDSC1_HVDRE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 10828 #define PMC_HVDSC1_HVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDRE_SHIFT)) & PMC_HVDSC1_HVDRE_MASK)
kadonotakashi 0:8fdf9a60065b 10829 #define PMC_HVDSC1_HVDIE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 10830 #define PMC_HVDSC1_HVDIE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 10831 #define PMC_HVDSC1_HVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDIE_SHIFT)) & PMC_HVDSC1_HVDIE_MASK)
kadonotakashi 0:8fdf9a60065b 10832 #define PMC_HVDSC1_HVDACK_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 10833 #define PMC_HVDSC1_HVDACK_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 10834 #define PMC_HVDSC1_HVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDACK_SHIFT)) & PMC_HVDSC1_HVDACK_MASK)
kadonotakashi 0:8fdf9a60065b 10835 #define PMC_HVDSC1_HVDF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 10836 #define PMC_HVDSC1_HVDF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 10837 #define PMC_HVDSC1_HVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDF_SHIFT)) & PMC_HVDSC1_HVDF_MASK)
kadonotakashi 0:8fdf9a60065b 10838
kadonotakashi 0:8fdf9a60065b 10839
kadonotakashi 0:8fdf9a60065b 10840 /*!
kadonotakashi 0:8fdf9a60065b 10841 * @}
kadonotakashi 0:8fdf9a60065b 10842 */ /* end of group PMC_Register_Masks */
kadonotakashi 0:8fdf9a60065b 10843
kadonotakashi 0:8fdf9a60065b 10844
kadonotakashi 0:8fdf9a60065b 10845 /* PMC - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 10846 /** Peripheral PMC base address */
kadonotakashi 0:8fdf9a60065b 10847 #define PMC_BASE (0x4007D000u)
kadonotakashi 0:8fdf9a60065b 10848 /** Peripheral PMC base pointer */
kadonotakashi 0:8fdf9a60065b 10849 #define PMC ((PMC_Type *)PMC_BASE)
kadonotakashi 0:8fdf9a60065b 10850 /** Array initializer of PMC peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 10851 #define PMC_BASE_ADDRS { PMC_BASE }
kadonotakashi 0:8fdf9a60065b 10852 /** Array initializer of PMC peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 10853 #define PMC_BASE_PTRS { PMC }
kadonotakashi 0:8fdf9a60065b 10854 /** Interrupt vectors for the PMC peripheral type */
kadonotakashi 0:8fdf9a60065b 10855 #define PMC_IRQS { LVD_LVW_IRQn }
kadonotakashi 0:8fdf9a60065b 10856
kadonotakashi 0:8fdf9a60065b 10857 /*!
kadonotakashi 0:8fdf9a60065b 10858 * @}
kadonotakashi 0:8fdf9a60065b 10859 */ /* end of group PMC_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 10860
kadonotakashi 0:8fdf9a60065b 10861
kadonotakashi 0:8fdf9a60065b 10862 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10863 -- PORT Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10864 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10865
kadonotakashi 0:8fdf9a60065b 10866 /*!
kadonotakashi 0:8fdf9a60065b 10867 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 10868 * @{
kadonotakashi 0:8fdf9a60065b 10869 */
kadonotakashi 0:8fdf9a60065b 10870
kadonotakashi 0:8fdf9a60065b 10871 /** PORT - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 10872 typedef struct {
kadonotakashi 0:8fdf9a60065b 10873 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 10874 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
kadonotakashi 0:8fdf9a60065b 10875 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
kadonotakashi 0:8fdf9a60065b 10876 uint8_t RESERVED_0[24];
kadonotakashi 0:8fdf9a60065b 10877 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
kadonotakashi 0:8fdf9a60065b 10878 uint8_t RESERVED_1[28];
kadonotakashi 0:8fdf9a60065b 10879 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
kadonotakashi 0:8fdf9a60065b 10880 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
kadonotakashi 0:8fdf9a60065b 10881 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
kadonotakashi 0:8fdf9a60065b 10882 } PORT_Type;
kadonotakashi 0:8fdf9a60065b 10883
kadonotakashi 0:8fdf9a60065b 10884 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 10885 -- PORT Register Masks
kadonotakashi 0:8fdf9a60065b 10886 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 10887
kadonotakashi 0:8fdf9a60065b 10888 /*!
kadonotakashi 0:8fdf9a60065b 10889 * @addtogroup PORT_Register_Masks PORT Register Masks
kadonotakashi 0:8fdf9a60065b 10890 * @{
kadonotakashi 0:8fdf9a60065b 10891 */
kadonotakashi 0:8fdf9a60065b 10892
kadonotakashi 0:8fdf9a60065b 10893 /*! @name PCR - Pin Control Register n */
kadonotakashi 0:8fdf9a60065b 10894 #define PORT_PCR_PS_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10895 #define PORT_PCR_PS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10896 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
kadonotakashi 0:8fdf9a60065b 10897 #define PORT_PCR_PE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 10898 #define PORT_PCR_PE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 10899 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
kadonotakashi 0:8fdf9a60065b 10900 #define PORT_PCR_SRE_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 10901 #define PORT_PCR_SRE_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 10902 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
kadonotakashi 0:8fdf9a60065b 10903 #define PORT_PCR_PFE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 10904 #define PORT_PCR_PFE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 10905 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
kadonotakashi 0:8fdf9a60065b 10906 #define PORT_PCR_ODE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 10907 #define PORT_PCR_ODE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 10908 #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
kadonotakashi 0:8fdf9a60065b 10909 #define PORT_PCR_DSE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 10910 #define PORT_PCR_DSE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 10911 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
kadonotakashi 0:8fdf9a60065b 10912 #define PORT_PCR_MUX_MASK (0x700U)
kadonotakashi 0:8fdf9a60065b 10913 #define PORT_PCR_MUX_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 10914 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
kadonotakashi 0:8fdf9a60065b 10915 #define PORT_PCR_LK_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 10916 #define PORT_PCR_LK_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 10917 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
kadonotakashi 0:8fdf9a60065b 10918 #define PORT_PCR_IRQC_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 10919 #define PORT_PCR_IRQC_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 10920 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
kadonotakashi 0:8fdf9a60065b 10921 #define PORT_PCR_ISF_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 10922 #define PORT_PCR_ISF_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 10923 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
kadonotakashi 0:8fdf9a60065b 10924
kadonotakashi 0:8fdf9a60065b 10925 /* The count of PORT_PCR */
kadonotakashi 0:8fdf9a60065b 10926 #define PORT_PCR_COUNT (32U)
kadonotakashi 0:8fdf9a60065b 10927
kadonotakashi 0:8fdf9a60065b 10928 /*! @name GPCLR - Global Pin Control Low Register */
kadonotakashi 0:8fdf9a60065b 10929 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 10930 #define PORT_GPCLR_GPWD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10931 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
kadonotakashi 0:8fdf9a60065b 10932 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 10933 #define PORT_GPCLR_GPWE_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 10934 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
kadonotakashi 0:8fdf9a60065b 10935
kadonotakashi 0:8fdf9a60065b 10936 /*! @name GPCHR - Global Pin Control High Register */
kadonotakashi 0:8fdf9a60065b 10937 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 10938 #define PORT_GPCHR_GPWD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10939 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
kadonotakashi 0:8fdf9a60065b 10940 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 10941 #define PORT_GPCHR_GPWE_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 10942 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
kadonotakashi 0:8fdf9a60065b 10943
kadonotakashi 0:8fdf9a60065b 10944 /*! @name ISFR - Interrupt Status Flag Register */
kadonotakashi 0:8fdf9a60065b 10945 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 10946 #define PORT_ISFR_ISF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10947 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
kadonotakashi 0:8fdf9a60065b 10948
kadonotakashi 0:8fdf9a60065b 10949 /*! @name DFER - Digital Filter Enable Register */
kadonotakashi 0:8fdf9a60065b 10950 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 10951 #define PORT_DFER_DFE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10952 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
kadonotakashi 0:8fdf9a60065b 10953
kadonotakashi 0:8fdf9a60065b 10954 /*! @name DFCR - Digital Filter Clock Register */
kadonotakashi 0:8fdf9a60065b 10955 #define PORT_DFCR_CS_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 10956 #define PORT_DFCR_CS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10957 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
kadonotakashi 0:8fdf9a60065b 10958
kadonotakashi 0:8fdf9a60065b 10959 /*! @name DFWR - Digital Filter Width Register */
kadonotakashi 0:8fdf9a60065b 10960 #define PORT_DFWR_FILT_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 10961 #define PORT_DFWR_FILT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 10962 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
kadonotakashi 0:8fdf9a60065b 10963
kadonotakashi 0:8fdf9a60065b 10964
kadonotakashi 0:8fdf9a60065b 10965 /*!
kadonotakashi 0:8fdf9a60065b 10966 * @}
kadonotakashi 0:8fdf9a60065b 10967 */ /* end of group PORT_Register_Masks */
kadonotakashi 0:8fdf9a60065b 10968
kadonotakashi 0:8fdf9a60065b 10969
kadonotakashi 0:8fdf9a60065b 10970 /* PORT - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 10971 /** Peripheral PORTA base address */
kadonotakashi 0:8fdf9a60065b 10972 #define PORTA_BASE (0x40049000u)
kadonotakashi 0:8fdf9a60065b 10973 /** Peripheral PORTA base pointer */
kadonotakashi 0:8fdf9a60065b 10974 #define PORTA ((PORT_Type *)PORTA_BASE)
kadonotakashi 0:8fdf9a60065b 10975 /** Peripheral PORTB base address */
kadonotakashi 0:8fdf9a60065b 10976 #define PORTB_BASE (0x4004A000u)
kadonotakashi 0:8fdf9a60065b 10977 /** Peripheral PORTB base pointer */
kadonotakashi 0:8fdf9a60065b 10978 #define PORTB ((PORT_Type *)PORTB_BASE)
kadonotakashi 0:8fdf9a60065b 10979 /** Peripheral PORTC base address */
kadonotakashi 0:8fdf9a60065b 10980 #define PORTC_BASE (0x4004B000u)
kadonotakashi 0:8fdf9a60065b 10981 /** Peripheral PORTC base pointer */
kadonotakashi 0:8fdf9a60065b 10982 #define PORTC ((PORT_Type *)PORTC_BASE)
kadonotakashi 0:8fdf9a60065b 10983 /** Peripheral PORTD base address */
kadonotakashi 0:8fdf9a60065b 10984 #define PORTD_BASE (0x4004C000u)
kadonotakashi 0:8fdf9a60065b 10985 /** Peripheral PORTD base pointer */
kadonotakashi 0:8fdf9a60065b 10986 #define PORTD ((PORT_Type *)PORTD_BASE)
kadonotakashi 0:8fdf9a60065b 10987 /** Peripheral PORTE base address */
kadonotakashi 0:8fdf9a60065b 10988 #define PORTE_BASE (0x4004D000u)
kadonotakashi 0:8fdf9a60065b 10989 /** Peripheral PORTE base pointer */
kadonotakashi 0:8fdf9a60065b 10990 #define PORTE ((PORT_Type *)PORTE_BASE)
kadonotakashi 0:8fdf9a60065b 10991 /** Array initializer of PORT peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 10992 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
kadonotakashi 0:8fdf9a60065b 10993 /** Array initializer of PORT peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 10994 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
kadonotakashi 0:8fdf9a60065b 10995 /** Interrupt vectors for the PORT peripheral type */
kadonotakashi 0:8fdf9a60065b 10996 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
kadonotakashi 0:8fdf9a60065b 10997
kadonotakashi 0:8fdf9a60065b 10998 /*!
kadonotakashi 0:8fdf9a60065b 10999 * @}
kadonotakashi 0:8fdf9a60065b 11000 */ /* end of group PORT_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 11001
kadonotakashi 0:8fdf9a60065b 11002
kadonotakashi 0:8fdf9a60065b 11003 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 11004 -- QuadSPI Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 11005 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 11006
kadonotakashi 0:8fdf9a60065b 11007 /*!
kadonotakashi 0:8fdf9a60065b 11008 * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 11009 * @{
kadonotakashi 0:8fdf9a60065b 11010 */
kadonotakashi 0:8fdf9a60065b 11011
kadonotakashi 0:8fdf9a60065b 11012 /** QuadSPI - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 11013 typedef struct {
kadonotakashi 0:8fdf9a60065b 11014 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 11015 uint8_t RESERVED_0[4];
kadonotakashi 0:8fdf9a60065b 11016 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 11017 __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 11018 __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 11019 __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 11020 __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 11021 __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */
kadonotakashi 0:8fdf9a60065b 11022 __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 11023 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 11024 uint8_t RESERVED_1[8];
kadonotakashi 0:8fdf9a60065b 11025 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */
kadonotakashi 0:8fdf9a60065b 11026 __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 11027 __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */
kadonotakashi 0:8fdf9a60065b 11028 uint8_t RESERVED_2[196];
kadonotakashi 0:8fdf9a60065b 11029 __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */
kadonotakashi 0:8fdf9a60065b 11030 __IO uint32_t SFACR; /**< Serial Flash Address Configuration Register, offset: 0x104 */
kadonotakashi 0:8fdf9a60065b 11031 __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */
kadonotakashi 0:8fdf9a60065b 11032 __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */
kadonotakashi 0:8fdf9a60065b 11033 __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */
kadonotakashi 0:8fdf9a60065b 11034 uint8_t RESERVED_3[60];
kadonotakashi 0:8fdf9a60065b 11035 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */
kadonotakashi 0:8fdf9a60065b 11036 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */
kadonotakashi 0:8fdf9a60065b 11037 __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */
kadonotakashi 0:8fdf9a60065b 11038 __I uint32_t SR; /**< Status Register, offset: 0x15C */
kadonotakashi 0:8fdf9a60065b 11039 __IO uint32_t FR; /**< Flag Register, offset: 0x160 */
kadonotakashi 0:8fdf9a60065b 11040 __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */
kadonotakashi 0:8fdf9a60065b 11041 __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */
kadonotakashi 0:8fdf9a60065b 11042 __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */
kadonotakashi 0:8fdf9a60065b 11043 uint8_t RESERVED_4[16];
kadonotakashi 0:8fdf9a60065b 11044 __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */
kadonotakashi 0:8fdf9a60065b 11045 __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */
kadonotakashi 0:8fdf9a60065b 11046 __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */
kadonotakashi 0:8fdf9a60065b 11047 __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */
kadonotakashi 0:8fdf9a60065b 11048 __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0x190 */
kadonotakashi 0:8fdf9a60065b 11049 uint8_t RESERVED_5[108];
kadonotakashi 0:8fdf9a60065b 11050 __I uint32_t RBDR[16]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 11051 uint8_t RESERVED_6[192];
kadonotakashi 0:8fdf9a60065b 11052 __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */
kadonotakashi 0:8fdf9a60065b 11053 __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */
kadonotakashi 0:8fdf9a60065b 11054 uint8_t RESERVED_7[8];
kadonotakashi 0:8fdf9a60065b 11055 __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 11056 } QuadSPI_Type;
kadonotakashi 0:8fdf9a60065b 11057
kadonotakashi 0:8fdf9a60065b 11058 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 11059 -- QuadSPI Register Masks
kadonotakashi 0:8fdf9a60065b 11060 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 11061
kadonotakashi 0:8fdf9a60065b 11062 /*!
kadonotakashi 0:8fdf9a60065b 11063 * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks
kadonotakashi 0:8fdf9a60065b 11064 * @{
kadonotakashi 0:8fdf9a60065b 11065 */
kadonotakashi 0:8fdf9a60065b 11066
kadonotakashi 0:8fdf9a60065b 11067 /*! @name MCR - Module Configuration Register */
kadonotakashi 0:8fdf9a60065b 11068 #define QuadSPI_MCR_SWRSTSD_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11069 #define QuadSPI_MCR_SWRSTSD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11070 #define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK)
kadonotakashi 0:8fdf9a60065b 11071 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11072 #define QuadSPI_MCR_SWRSTHD_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11073 #define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
kadonotakashi 0:8fdf9a60065b 11074 #define QuadSPI_MCR_END_CFG_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 11075 #define QuadSPI_MCR_END_CFG_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11076 #define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK)
kadonotakashi 0:8fdf9a60065b 11077 #define QuadSPI_MCR_DQS_LAT_EN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 11078 #define QuadSPI_MCR_DQS_LAT_EN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 11079 #define QuadSPI_MCR_DQS_LAT_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LAT_EN_SHIFT)) & QuadSPI_MCR_DQS_LAT_EN_MASK)
kadonotakashi 0:8fdf9a60065b 11080 #define QuadSPI_MCR_DQS_EN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 11081 #define QuadSPI_MCR_DQS_EN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 11082 #define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK)
kadonotakashi 0:8fdf9a60065b 11083 #define QuadSPI_MCR_DDR_EN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 11084 #define QuadSPI_MCR_DDR_EN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 11085 #define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK)
kadonotakashi 0:8fdf9a60065b 11086 #define QuadSPI_MCR_CLR_RXF_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 11087 #define QuadSPI_MCR_CLR_RXF_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 11088 #define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK)
kadonotakashi 0:8fdf9a60065b 11089 #define QuadSPI_MCR_CLR_TXF_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 11090 #define QuadSPI_MCR_CLR_TXF_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 11091 #define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK)
kadonotakashi 0:8fdf9a60065b 11092 #define QuadSPI_MCR_MDIS_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 11093 #define QuadSPI_MCR_MDIS_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 11094 #define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK)
kadonotakashi 0:8fdf9a60065b 11095 #define QuadSPI_MCR_SCLKCFG_MASK (0xFF000000U)
kadonotakashi 0:8fdf9a60065b 11096 #define QuadSPI_MCR_SCLKCFG_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 11097 #define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SCLKCFG_SHIFT)) & QuadSPI_MCR_SCLKCFG_MASK)
kadonotakashi 0:8fdf9a60065b 11098
kadonotakashi 0:8fdf9a60065b 11099 /*! @name IPCR - IP Configuration Register */
kadonotakashi 0:8fdf9a60065b 11100 #define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 11101 #define QuadSPI_IPCR_IDATSZ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11102 #define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK)
kadonotakashi 0:8fdf9a60065b 11103 #define QuadSPI_IPCR_PAR_EN_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 11104 #define QuadSPI_IPCR_PAR_EN_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11105 #define QuadSPI_IPCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK)
kadonotakashi 0:8fdf9a60065b 11106 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U)
kadonotakashi 0:8fdf9a60065b 11107 #define QuadSPI_IPCR_SEQID_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 11108 #define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
kadonotakashi 0:8fdf9a60065b 11109
kadonotakashi 0:8fdf9a60065b 11110 /*! @name FLSHCR - Flash Configuration Register */
kadonotakashi 0:8fdf9a60065b 11111 #define QuadSPI_FLSHCR_TCSS_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 11112 #define QuadSPI_FLSHCR_TCSS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11113 #define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK)
kadonotakashi 0:8fdf9a60065b 11114 #define QuadSPI_FLSHCR_TCSH_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 11115 #define QuadSPI_FLSHCR_TCSH_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11116 #define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK)
kadonotakashi 0:8fdf9a60065b 11117 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 11118 #define QuadSPI_FLSHCR_TDH_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11119 #define QuadSPI_FLSHCR_TDH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
kadonotakashi 0:8fdf9a60065b 11120
kadonotakashi 0:8fdf9a60065b 11121 /*! @name BUF0CR - Buffer0 Configuration Register */
kadonotakashi 0:8fdf9a60065b 11122 #define QuadSPI_BUF0CR_MSTRID_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 11123 #define QuadSPI_BUF0CR_MSTRID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11124 #define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK)
kadonotakashi 0:8fdf9a60065b 11125 #define QuadSPI_BUF0CR_ADATSZ_MASK (0x7F00U)
kadonotakashi 0:8fdf9a60065b 11126 #define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11127 #define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK)
kadonotakashi 0:8fdf9a60065b 11128 #define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 11129 #define QuadSPI_BUF0CR_HP_EN_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 11130 #define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK)
kadonotakashi 0:8fdf9a60065b 11131
kadonotakashi 0:8fdf9a60065b 11132 /*! @name BUF1CR - Buffer1 Configuration Register */
kadonotakashi 0:8fdf9a60065b 11133 #define QuadSPI_BUF1CR_MSTRID_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 11134 #define QuadSPI_BUF1CR_MSTRID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11135 #define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK)
kadonotakashi 0:8fdf9a60065b 11136 #define QuadSPI_BUF1CR_ADATSZ_MASK (0x7F00U)
kadonotakashi 0:8fdf9a60065b 11137 #define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11138 #define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK)
kadonotakashi 0:8fdf9a60065b 11139
kadonotakashi 0:8fdf9a60065b 11140 /*! @name BUF2CR - Buffer2 Configuration Register */
kadonotakashi 0:8fdf9a60065b 11141 #define QuadSPI_BUF2CR_MSTRID_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 11142 #define QuadSPI_BUF2CR_MSTRID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11143 #define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK)
kadonotakashi 0:8fdf9a60065b 11144 #define QuadSPI_BUF2CR_ADATSZ_MASK (0x7F00U)
kadonotakashi 0:8fdf9a60065b 11145 #define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11146 #define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK)
kadonotakashi 0:8fdf9a60065b 11147
kadonotakashi 0:8fdf9a60065b 11148 /*! @name BUF3CR - Buffer3 Configuration Register */
kadonotakashi 0:8fdf9a60065b 11149 #define QuadSPI_BUF3CR_MSTRID_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 11150 #define QuadSPI_BUF3CR_MSTRID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11151 #define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK)
kadonotakashi 0:8fdf9a60065b 11152 #define QuadSPI_BUF3CR_ADATSZ_MASK (0x7F00U)
kadonotakashi 0:8fdf9a60065b 11153 #define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11154 #define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK)
kadonotakashi 0:8fdf9a60065b 11155 #define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 11156 #define QuadSPI_BUF3CR_ALLMST_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 11157 #define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK)
kadonotakashi 0:8fdf9a60065b 11158
kadonotakashi 0:8fdf9a60065b 11159 /*! @name BFGENCR - Buffer Generic Configuration Register */
kadonotakashi 0:8fdf9a60065b 11160 #define QuadSPI_BFGENCR_SEQID_MASK (0xF000U)
kadonotakashi 0:8fdf9a60065b 11161 #define QuadSPI_BFGENCR_SEQID_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 11162 #define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK)
kadonotakashi 0:8fdf9a60065b 11163 #define QuadSPI_BFGENCR_PAR_EN_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 11164 #define QuadSPI_BFGENCR_PAR_EN_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11165 #define QuadSPI_BFGENCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK)
kadonotakashi 0:8fdf9a60065b 11166
kadonotakashi 0:8fdf9a60065b 11167 /*! @name SOCCR - SOC Configuration Register */
kadonotakashi 0:8fdf9a60065b 11168 #define QuadSPI_SOCCR_QSPISRC_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 11169 #define QuadSPI_SOCCR_QSPISRC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11170 #define QuadSPI_SOCCR_QSPISRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_QSPISRC_SHIFT)) & QuadSPI_SOCCR_QSPISRC_MASK)
kadonotakashi 0:8fdf9a60065b 11171 #define QuadSPI_SOCCR_DQSLPEN_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 11172 #define QuadSPI_SOCCR_DQSLPEN_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11173 #define QuadSPI_SOCCR_DQSLPEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSLPEN_SHIFT)) & QuadSPI_SOCCR_DQSLPEN_MASK)
kadonotakashi 0:8fdf9a60065b 11174 #define QuadSPI_SOCCR_DQSPADLPEN_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 11175 #define QuadSPI_SOCCR_DQSPADLPEN_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 11176 #define QuadSPI_SOCCR_DQSPADLPEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSPADLPEN_SHIFT)) & QuadSPI_SOCCR_DQSPADLPEN_MASK)
kadonotakashi 0:8fdf9a60065b 11177 #define QuadSPI_SOCCR_DQSPHASEL_MASK (0xC00U)
kadonotakashi 0:8fdf9a60065b 11178 #define QuadSPI_SOCCR_DQSPHASEL_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 11179 #define QuadSPI_SOCCR_DQSPHASEL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSPHASEL_SHIFT)) & QuadSPI_SOCCR_DQSPHASEL_MASK)
kadonotakashi 0:8fdf9a60065b 11180 #define QuadSPI_SOCCR_DQSINVSEL_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 11181 #define QuadSPI_SOCCR_DQSINVSEL_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 11182 #define QuadSPI_SOCCR_DQSINVSEL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSINVSEL_SHIFT)) & QuadSPI_SOCCR_DQSINVSEL_MASK)
kadonotakashi 0:8fdf9a60065b 11183 #define QuadSPI_SOCCR_CK2EN_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 11184 #define QuadSPI_SOCCR_CK2EN_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 11185 #define QuadSPI_SOCCR_CK2EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_CK2EN_SHIFT)) & QuadSPI_SOCCR_CK2EN_MASK)
kadonotakashi 0:8fdf9a60065b 11186 #define QuadSPI_SOCCR_DIFFCKEN_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 11187 #define QuadSPI_SOCCR_DIFFCKEN_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 11188 #define QuadSPI_SOCCR_DIFFCKEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DIFFCKEN_SHIFT)) & QuadSPI_SOCCR_DIFFCKEN_MASK)
kadonotakashi 0:8fdf9a60065b 11189 #define QuadSPI_SOCCR_OCTEN_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 11190 #define QuadSPI_SOCCR_OCTEN_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 11191 #define QuadSPI_SOCCR_OCTEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_OCTEN_SHIFT)) & QuadSPI_SOCCR_OCTEN_MASK)
kadonotakashi 0:8fdf9a60065b 11192 #define QuadSPI_SOCCR_DLYTAPSELA_MASK (0x3F0000U)
kadonotakashi 0:8fdf9a60065b 11193 #define QuadSPI_SOCCR_DLYTAPSELA_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11194 #define QuadSPI_SOCCR_DLYTAPSELA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DLYTAPSELA_SHIFT)) & QuadSPI_SOCCR_DLYTAPSELA_MASK)
kadonotakashi 0:8fdf9a60065b 11195 #define QuadSPI_SOCCR_DLYTAPSELB_MASK (0x3F000000U)
kadonotakashi 0:8fdf9a60065b 11196 #define QuadSPI_SOCCR_DLYTAPSELB_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 11197 #define QuadSPI_SOCCR_DLYTAPSELB(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DLYTAPSELB_SHIFT)) & QuadSPI_SOCCR_DLYTAPSELB_MASK)
kadonotakashi 0:8fdf9a60065b 11198
kadonotakashi 0:8fdf9a60065b 11199 /*! @name BUF0IND - Buffer0 Top Index Register */
kadonotakashi 0:8fdf9a60065b 11200 #define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U)
kadonotakashi 0:8fdf9a60065b 11201 #define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 11202 #define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK)
kadonotakashi 0:8fdf9a60065b 11203
kadonotakashi 0:8fdf9a60065b 11204 /*! @name BUF1IND - Buffer1 Top Index Register */
kadonotakashi 0:8fdf9a60065b 11205 #define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U)
kadonotakashi 0:8fdf9a60065b 11206 #define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 11207 #define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK)
kadonotakashi 0:8fdf9a60065b 11208
kadonotakashi 0:8fdf9a60065b 11209 /*! @name BUF2IND - Buffer2 Top Index Register */
kadonotakashi 0:8fdf9a60065b 11210 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U)
kadonotakashi 0:8fdf9a60065b 11211 #define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 11212 #define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
kadonotakashi 0:8fdf9a60065b 11213
kadonotakashi 0:8fdf9a60065b 11214 /*! @name SFAR - Serial Flash Address Register */
kadonotakashi 0:8fdf9a60065b 11215 #define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 11216 #define QuadSPI_SFAR_SFADR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11217 #define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK)
kadonotakashi 0:8fdf9a60065b 11218
kadonotakashi 0:8fdf9a60065b 11219 /*! @name SFACR - Serial Flash Address Configuration Register */
kadonotakashi 0:8fdf9a60065b 11220 #define QuadSPI_SFACR_CAS_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 11221 #define QuadSPI_SFACR_CAS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11222 #define QuadSPI_SFACR_CAS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_CAS_SHIFT)) & QuadSPI_SFACR_CAS_MASK)
kadonotakashi 0:8fdf9a60065b 11223 #define QuadSPI_SFACR_WA_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 11224 #define QuadSPI_SFACR_WA_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11225 #define QuadSPI_SFACR_WA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_WA_SHIFT)) & QuadSPI_SFACR_WA_MASK)
kadonotakashi 0:8fdf9a60065b 11226
kadonotakashi 0:8fdf9a60065b 11227 /*! @name SMPR - Sampling Register */
kadonotakashi 0:8fdf9a60065b 11228 #define QuadSPI_SMPR_HSENA_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11229 #define QuadSPI_SMPR_HSENA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11230 #define QuadSPI_SMPR_HSENA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK)
kadonotakashi 0:8fdf9a60065b 11231 #define QuadSPI_SMPR_HSPHS_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11232 #define QuadSPI_SMPR_HSPHS_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11233 #define QuadSPI_SMPR_HSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSPHS_SHIFT)) & QuadSPI_SMPR_HSPHS_MASK)
kadonotakashi 0:8fdf9a60065b 11234 #define QuadSPI_SMPR_HSDLY_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 11235 #define QuadSPI_SMPR_HSDLY_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11236 #define QuadSPI_SMPR_HSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSDLY_SHIFT)) & QuadSPI_SMPR_HSDLY_MASK)
kadonotakashi 0:8fdf9a60065b 11237 #define QuadSPI_SMPR_FSPHS_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 11238 #define QuadSPI_SMPR_FSPHS_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 11239 #define QuadSPI_SMPR_FSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSPHS_SHIFT)) & QuadSPI_SMPR_FSPHS_MASK)
kadonotakashi 0:8fdf9a60065b 11240 #define QuadSPI_SMPR_FSDLY_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 11241 #define QuadSPI_SMPR_FSDLY_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 11242 #define QuadSPI_SMPR_FSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSDLY_SHIFT)) & QuadSPI_SMPR_FSDLY_MASK)
kadonotakashi 0:8fdf9a60065b 11243 #define QuadSPI_SMPR_DDRSMP_MASK (0x70000U)
kadonotakashi 0:8fdf9a60065b 11244 #define QuadSPI_SMPR_DDRSMP_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11245 #define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK)
kadonotakashi 0:8fdf9a60065b 11246
kadonotakashi 0:8fdf9a60065b 11247 /*! @name RBSR - RX Buffer Status Register */
kadonotakashi 0:8fdf9a60065b 11248 #define QuadSPI_RBSR_RDBFL_MASK (0x1F00U)
kadonotakashi 0:8fdf9a60065b 11249 #define QuadSPI_RBSR_RDBFL_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11250 #define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK)
kadonotakashi 0:8fdf9a60065b 11251 #define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 11252 #define QuadSPI_RBSR_RDCTR_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11253 #define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK)
kadonotakashi 0:8fdf9a60065b 11254
kadonotakashi 0:8fdf9a60065b 11255 /*! @name RBCT - RX Buffer Control Register */
kadonotakashi 0:8fdf9a60065b 11256 #define QuadSPI_RBCT_WMRK_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 11257 #define QuadSPI_RBCT_WMRK_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11258 #define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK)
kadonotakashi 0:8fdf9a60065b 11259 #define QuadSPI_RBCT_RXBRD_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 11260 #define QuadSPI_RBCT_RXBRD_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11261 #define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK)
kadonotakashi 0:8fdf9a60065b 11262
kadonotakashi 0:8fdf9a60065b 11263 /*! @name TBSR - TX Buffer Status Register */
kadonotakashi 0:8fdf9a60065b 11264 #define QuadSPI_TBSR_TRBFL_MASK (0x1F00U)
kadonotakashi 0:8fdf9a60065b 11265 #define QuadSPI_TBSR_TRBFL_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11266 #define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK)
kadonotakashi 0:8fdf9a60065b 11267 #define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 11268 #define QuadSPI_TBSR_TRCTR_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11269 #define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK)
kadonotakashi 0:8fdf9a60065b 11270
kadonotakashi 0:8fdf9a60065b 11271 /*! @name TBDR - TX Buffer Data Register */
kadonotakashi 0:8fdf9a60065b 11272 #define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 11273 #define QuadSPI_TBDR_TXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11274 #define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 11275
kadonotakashi 0:8fdf9a60065b 11276 /*! @name TBCT - Tx Buffer Control Register */
kadonotakashi 0:8fdf9a60065b 11277 #define QuadSPI_TBCT_WMRK_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 11278 #define QuadSPI_TBCT_WMRK_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11279 #define QuadSPI_TBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBCT_WMRK_SHIFT)) & QuadSPI_TBCT_WMRK_MASK)
kadonotakashi 0:8fdf9a60065b 11280
kadonotakashi 0:8fdf9a60065b 11281 /*! @name SR - Status Register */
kadonotakashi 0:8fdf9a60065b 11282 #define QuadSPI_SR_BUSY_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11283 #define QuadSPI_SR_BUSY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11284 #define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK)
kadonotakashi 0:8fdf9a60065b 11285 #define QuadSPI_SR_IP_ACC_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11286 #define QuadSPI_SR_IP_ACC_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11287 #define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK)
kadonotakashi 0:8fdf9a60065b 11288 #define QuadSPI_SR_AHB_ACC_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 11289 #define QuadSPI_SR_AHB_ACC_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11290 #define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK)
kadonotakashi 0:8fdf9a60065b 11291 #define QuadSPI_SR_AHBGNT_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 11292 #define QuadSPI_SR_AHBGNT_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 11293 #define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK)
kadonotakashi 0:8fdf9a60065b 11294 #define QuadSPI_SR_AHBTRN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 11295 #define QuadSPI_SR_AHBTRN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 11296 #define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK)
kadonotakashi 0:8fdf9a60065b 11297 #define QuadSPI_SR_AHB0NE_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 11298 #define QuadSPI_SR_AHB0NE_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 11299 #define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
kadonotakashi 0:8fdf9a60065b 11300 #define QuadSPI_SR_AHB1NE_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 11301 #define QuadSPI_SR_AHB1NE_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11302 #define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK)
kadonotakashi 0:8fdf9a60065b 11303 #define QuadSPI_SR_AHB2NE_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 11304 #define QuadSPI_SR_AHB2NE_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 11305 #define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK)
kadonotakashi 0:8fdf9a60065b 11306 #define QuadSPI_SR_AHB3NE_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 11307 #define QuadSPI_SR_AHB3NE_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 11308 #define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK)
kadonotakashi 0:8fdf9a60065b 11309 #define QuadSPI_SR_AHB0FUL_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 11310 #define QuadSPI_SR_AHB0FUL_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 11311 #define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
kadonotakashi 0:8fdf9a60065b 11312 #define QuadSPI_SR_AHB1FUL_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 11313 #define QuadSPI_SR_AHB1FUL_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 11314 #define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK)
kadonotakashi 0:8fdf9a60065b 11315 #define QuadSPI_SR_AHB2FUL_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 11316 #define QuadSPI_SR_AHB2FUL_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 11317 #define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK)
kadonotakashi 0:8fdf9a60065b 11318 #define QuadSPI_SR_AHB3FUL_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 11319 #define QuadSPI_SR_AHB3FUL_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 11320 #define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK)
kadonotakashi 0:8fdf9a60065b 11321 #define QuadSPI_SR_RXWE_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 11322 #define QuadSPI_SR_RXWE_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11323 #define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
kadonotakashi 0:8fdf9a60065b 11324 #define QuadSPI_SR_RXFULL_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 11325 #define QuadSPI_SR_RXFULL_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 11326 #define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
kadonotakashi 0:8fdf9a60065b 11327 #define QuadSPI_SR_RXDMA_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 11328 #define QuadSPI_SR_RXDMA_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 11329 #define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK)
kadonotakashi 0:8fdf9a60065b 11330 #define QuadSPI_SR_TXEDA_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 11331 #define QuadSPI_SR_TXEDA_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 11332 #define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK)
kadonotakashi 0:8fdf9a60065b 11333 #define QuadSPI_SR_TXWA_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 11334 #define QuadSPI_SR_TXWA_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 11335 #define QuadSPI_SR_TXWA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXWA_SHIFT)) & QuadSPI_SR_TXWA_MASK)
kadonotakashi 0:8fdf9a60065b 11336 #define QuadSPI_SR_TXDMA_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 11337 #define QuadSPI_SR_TXDMA_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 11338 #define QuadSPI_SR_TXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXDMA_SHIFT)) & QuadSPI_SR_TXDMA_MASK)
kadonotakashi 0:8fdf9a60065b 11339 #define QuadSPI_SR_TXFULL_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 11340 #define QuadSPI_SR_TXFULL_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 11341 #define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
kadonotakashi 0:8fdf9a60065b 11342 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U)
kadonotakashi 0:8fdf9a60065b 11343 #define QuadSPI_SR_DLPSMP_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 11344 #define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
kadonotakashi 0:8fdf9a60065b 11345
kadonotakashi 0:8fdf9a60065b 11346 /*! @name FR - Flag Register */
kadonotakashi 0:8fdf9a60065b 11347 #define QuadSPI_FR_TFF_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11348 #define QuadSPI_FR_TFF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11349 #define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK)
kadonotakashi 0:8fdf9a60065b 11350 #define QuadSPI_FR_IPGEF_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 11351 #define QuadSPI_FR_IPGEF_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 11352 #define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK)
kadonotakashi 0:8fdf9a60065b 11353 #define QuadSPI_FR_IPIEF_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 11354 #define QuadSPI_FR_IPIEF_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 11355 #define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK)
kadonotakashi 0:8fdf9a60065b 11356 #define QuadSPI_FR_IPAEF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 11357 #define QuadSPI_FR_IPAEF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 11358 #define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK)
kadonotakashi 0:8fdf9a60065b 11359 #define QuadSPI_FR_IUEF_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 11360 #define QuadSPI_FR_IUEF_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 11361 #define QuadSPI_FR_IUEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK)
kadonotakashi 0:8fdf9a60065b 11362 #define QuadSPI_FR_ABOF_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 11363 #define QuadSPI_FR_ABOF_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 11364 #define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK)
kadonotakashi 0:8fdf9a60065b 11365 #define QuadSPI_FR_AIBSEF_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 11366 #define QuadSPI_FR_AIBSEF_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 11367 #define QuadSPI_FR_AIBSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
kadonotakashi 0:8fdf9a60065b 11368 #define QuadSPI_FR_AITEF_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 11369 #define QuadSPI_FR_AITEF_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 11370 #define QuadSPI_FR_AITEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AITEF_SHIFT)) & QuadSPI_FR_AITEF_MASK)
kadonotakashi 0:8fdf9a60065b 11371 #define QuadSPI_FR_ABSEF_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 11372 #define QuadSPI_FR_ABSEF_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 11373 #define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
kadonotakashi 0:8fdf9a60065b 11374 #define QuadSPI_FR_RBDF_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 11375 #define QuadSPI_FR_RBDF_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11376 #define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK)
kadonotakashi 0:8fdf9a60065b 11377 #define QuadSPI_FR_RBOF_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 11378 #define QuadSPI_FR_RBOF_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 11379 #define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK)
kadonotakashi 0:8fdf9a60065b 11380 #define QuadSPI_FR_ILLINE_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 11381 #define QuadSPI_FR_ILLINE_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 11382 #define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
kadonotakashi 0:8fdf9a60065b 11383 #define QuadSPI_FR_TBUF_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 11384 #define QuadSPI_FR_TBUF_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 11385 #define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK)
kadonotakashi 0:8fdf9a60065b 11386 #define QuadSPI_FR_TBFF_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 11387 #define QuadSPI_FR_TBFF_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 11388 #define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK)
kadonotakashi 0:8fdf9a60065b 11389 #define QuadSPI_FR_DLPFF_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 11390 #define QuadSPI_FR_DLPFF_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 11391 #define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK)
kadonotakashi 0:8fdf9a60065b 11392
kadonotakashi 0:8fdf9a60065b 11393 /*! @name RSER - Interrupt and DMA Request Select and Enable Register */
kadonotakashi 0:8fdf9a60065b 11394 #define QuadSPI_RSER_TFIE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11395 #define QuadSPI_RSER_TFIE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11396 #define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK)
kadonotakashi 0:8fdf9a60065b 11397 #define QuadSPI_RSER_IPGEIE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 11398 #define QuadSPI_RSER_IPGEIE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 11399 #define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK)
kadonotakashi 0:8fdf9a60065b 11400 #define QuadSPI_RSER_IPIEIE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 11401 #define QuadSPI_RSER_IPIEIE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 11402 #define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK)
kadonotakashi 0:8fdf9a60065b 11403 #define QuadSPI_RSER_IPAEIE_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 11404 #define QuadSPI_RSER_IPAEIE_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 11405 #define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK)
kadonotakashi 0:8fdf9a60065b 11406 #define QuadSPI_RSER_IUEIE_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 11407 #define QuadSPI_RSER_IUEIE_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 11408 #define QuadSPI_RSER_IUEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK)
kadonotakashi 0:8fdf9a60065b 11409 #define QuadSPI_RSER_ABOIE_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 11410 #define QuadSPI_RSER_ABOIE_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 11411 #define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK)
kadonotakashi 0:8fdf9a60065b 11412 #define QuadSPI_RSER_AIBSIE_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 11413 #define QuadSPI_RSER_AIBSIE_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 11414 #define QuadSPI_RSER_AIBSIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AIBSIE_SHIFT)) & QuadSPI_RSER_AIBSIE_MASK)
kadonotakashi 0:8fdf9a60065b 11415 #define QuadSPI_RSER_AITIE_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 11416 #define QuadSPI_RSER_AITIE_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 11417 #define QuadSPI_RSER_AITIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AITIE_SHIFT)) & QuadSPI_RSER_AITIE_MASK)
kadonotakashi 0:8fdf9a60065b 11418 #define QuadSPI_RSER_ABSEIE_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 11419 #define QuadSPI_RSER_ABSEIE_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 11420 #define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK)
kadonotakashi 0:8fdf9a60065b 11421 #define QuadSPI_RSER_RBDIE_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 11422 #define QuadSPI_RSER_RBDIE_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11423 #define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK)
kadonotakashi 0:8fdf9a60065b 11424 #define QuadSPI_RSER_RBOIE_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 11425 #define QuadSPI_RSER_RBOIE_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 11426 #define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK)
kadonotakashi 0:8fdf9a60065b 11427 #define QuadSPI_RSER_RBDDE_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 11428 #define QuadSPI_RSER_RBDDE_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 11429 #define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK)
kadonotakashi 0:8fdf9a60065b 11430 #define QuadSPI_RSER_ILLINIE_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 11431 #define QuadSPI_RSER_ILLINIE_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 11432 #define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK)
kadonotakashi 0:8fdf9a60065b 11433 #define QuadSPI_RSER_TBFDE_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 11434 #define QuadSPI_RSER_TBFDE_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 11435 #define QuadSPI_RSER_TBFDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFDE_SHIFT)) & QuadSPI_RSER_TBFDE_MASK)
kadonotakashi 0:8fdf9a60065b 11436 #define QuadSPI_RSER_TBUIE_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 11437 #define QuadSPI_RSER_TBUIE_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 11438 #define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK)
kadonotakashi 0:8fdf9a60065b 11439 #define QuadSPI_RSER_TBFIE_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 11440 #define QuadSPI_RSER_TBFIE_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 11441 #define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK)
kadonotakashi 0:8fdf9a60065b 11442 #define QuadSPI_RSER_DLPFIE_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 11443 #define QuadSPI_RSER_DLPFIE_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 11444 #define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK)
kadonotakashi 0:8fdf9a60065b 11445
kadonotakashi 0:8fdf9a60065b 11446 /*! @name SPNDST - Sequence Suspend Status Register */
kadonotakashi 0:8fdf9a60065b 11447 #define QuadSPI_SPNDST_SUSPND_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11448 #define QuadSPI_SPNDST_SUSPND_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11449 #define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK)
kadonotakashi 0:8fdf9a60065b 11450 #define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 11451 #define QuadSPI_SPNDST_SPDBUF_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 11452 #define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK)
kadonotakashi 0:8fdf9a60065b 11453 #define QuadSPI_SPNDST_DATLFT_MASK (0x7E00U)
kadonotakashi 0:8fdf9a60065b 11454 #define QuadSPI_SPNDST_DATLFT_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 11455 #define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK)
kadonotakashi 0:8fdf9a60065b 11456
kadonotakashi 0:8fdf9a60065b 11457 /*! @name SPTRCLR - Sequence Pointer Clear Register */
kadonotakashi 0:8fdf9a60065b 11458 #define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11459 #define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11460 #define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK)
kadonotakashi 0:8fdf9a60065b 11461 #define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 11462 #define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11463 #define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK)
kadonotakashi 0:8fdf9a60065b 11464
kadonotakashi 0:8fdf9a60065b 11465 /*! @name SFA1AD - Serial Flash A1 Top Address */
kadonotakashi 0:8fdf9a60065b 11466 #define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U)
kadonotakashi 0:8fdf9a60065b 11467 #define QuadSPI_SFA1AD_TPADA1_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 11468 #define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK)
kadonotakashi 0:8fdf9a60065b 11469
kadonotakashi 0:8fdf9a60065b 11470 /*! @name SFA2AD - Serial Flash A2 Top Address */
kadonotakashi 0:8fdf9a60065b 11471 #define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U)
kadonotakashi 0:8fdf9a60065b 11472 #define QuadSPI_SFA2AD_TPADA2_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 11473 #define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK)
kadonotakashi 0:8fdf9a60065b 11474
kadonotakashi 0:8fdf9a60065b 11475 /*! @name SFB1AD - Serial Flash B1Top Address */
kadonotakashi 0:8fdf9a60065b 11476 #define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U)
kadonotakashi 0:8fdf9a60065b 11477 #define QuadSPI_SFB1AD_TPADB1_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 11478 #define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK)
kadonotakashi 0:8fdf9a60065b 11479
kadonotakashi 0:8fdf9a60065b 11480 /*! @name SFB2AD - Serial Flash B2Top Address */
kadonotakashi 0:8fdf9a60065b 11481 #define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U)
kadonotakashi 0:8fdf9a60065b 11482 #define QuadSPI_SFB2AD_TPADB2_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 11483 #define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK)
kadonotakashi 0:8fdf9a60065b 11484
kadonotakashi 0:8fdf9a60065b 11485 /*! @name DLPR - Data Learn Pattern Register */
kadonotakashi 0:8fdf9a60065b 11486 #define QuadSPI_DLPR_DLPV_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 11487 #define QuadSPI_DLPR_DLPV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11488 #define QuadSPI_DLPR_DLPV(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLPR_DLPV_SHIFT)) & QuadSPI_DLPR_DLPV_MASK)
kadonotakashi 0:8fdf9a60065b 11489
kadonotakashi 0:8fdf9a60065b 11490 /*! @name RBDR - RX Buffer Data Register */
kadonotakashi 0:8fdf9a60065b 11491 #define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 11492 #define QuadSPI_RBDR_RXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11493 #define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 11494
kadonotakashi 0:8fdf9a60065b 11495 /* The count of QuadSPI_RBDR */
kadonotakashi 0:8fdf9a60065b 11496 #define QuadSPI_RBDR_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 11497
kadonotakashi 0:8fdf9a60065b 11498 /*! @name LUTKEY - LUT Key Register */
kadonotakashi 0:8fdf9a60065b 11499 #define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 11500 #define QuadSPI_LUTKEY_KEY_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11501 #define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK)
kadonotakashi 0:8fdf9a60065b 11502
kadonotakashi 0:8fdf9a60065b 11503 /*! @name LCKCR - LUT Lock Configuration Register */
kadonotakashi 0:8fdf9a60065b 11504 #define QuadSPI_LCKCR_LOCK_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11505 #define QuadSPI_LCKCR_LOCK_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11506 #define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
kadonotakashi 0:8fdf9a60065b 11507 #define QuadSPI_LCKCR_UNLOCK_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11508 #define QuadSPI_LCKCR_UNLOCK_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11509 #define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK)
kadonotakashi 0:8fdf9a60065b 11510
kadonotakashi 0:8fdf9a60065b 11511 /*! @name LUT - Look-up Table register */
kadonotakashi 0:8fdf9a60065b 11512 #define QuadSPI_LUT_OPRND0_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 11513 #define QuadSPI_LUT_OPRND0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11514 #define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK)
kadonotakashi 0:8fdf9a60065b 11515 #define QuadSPI_LUT_PAD0_MASK (0x300U)
kadonotakashi 0:8fdf9a60065b 11516 #define QuadSPI_LUT_PAD0_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11517 #define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK)
kadonotakashi 0:8fdf9a60065b 11518 #define QuadSPI_LUT_INSTR0_MASK (0xFC00U)
kadonotakashi 0:8fdf9a60065b 11519 #define QuadSPI_LUT_INSTR0_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 11520 #define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK)
kadonotakashi 0:8fdf9a60065b 11521 #define QuadSPI_LUT_OPRND1_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 11522 #define QuadSPI_LUT_OPRND1_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11523 #define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK)
kadonotakashi 0:8fdf9a60065b 11524 #define QuadSPI_LUT_PAD1_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 11525 #define QuadSPI_LUT_PAD1_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 11526 #define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK)
kadonotakashi 0:8fdf9a60065b 11527 #define QuadSPI_LUT_INSTR1_MASK (0xFC000000U)
kadonotakashi 0:8fdf9a60065b 11528 #define QuadSPI_LUT_INSTR1_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 11529 #define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK)
kadonotakashi 0:8fdf9a60065b 11530
kadonotakashi 0:8fdf9a60065b 11531 /* The count of QuadSPI_LUT */
kadonotakashi 0:8fdf9a60065b 11532 #define QuadSPI_LUT_COUNT (64U)
kadonotakashi 0:8fdf9a60065b 11533
kadonotakashi 0:8fdf9a60065b 11534
kadonotakashi 0:8fdf9a60065b 11535 /*!
kadonotakashi 0:8fdf9a60065b 11536 * @}
kadonotakashi 0:8fdf9a60065b 11537 */ /* end of group QuadSPI_Register_Masks */
kadonotakashi 0:8fdf9a60065b 11538
kadonotakashi 0:8fdf9a60065b 11539
kadonotakashi 0:8fdf9a60065b 11540 /* QuadSPI - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 11541 /** Peripheral QuadSPI0 base address */
kadonotakashi 0:8fdf9a60065b 11542 #define QuadSPI0_BASE (0x400DA000u)
kadonotakashi 0:8fdf9a60065b 11543 /** Peripheral QuadSPI0 base pointer */
kadonotakashi 0:8fdf9a60065b 11544 #define QuadSPI0 ((QuadSPI_Type *)QuadSPI0_BASE)
kadonotakashi 0:8fdf9a60065b 11545 /** Array initializer of QuadSPI peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 11546 #define QuadSPI_BASE_ADDRS { QuadSPI0_BASE }
kadonotakashi 0:8fdf9a60065b 11547 /** Array initializer of QuadSPI peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 11548 #define QuadSPI_BASE_PTRS { QuadSPI0 }
kadonotakashi 0:8fdf9a60065b 11549 /** Interrupt vectors for the QuadSPI peripheral type */
kadonotakashi 0:8fdf9a60065b 11550 #define QuadSPI_IRQS { QuadSPI0_IRQn }
kadonotakashi 0:8fdf9a60065b 11551
kadonotakashi 0:8fdf9a60065b 11552 /*!
kadonotakashi 0:8fdf9a60065b 11553 * @}
kadonotakashi 0:8fdf9a60065b 11554 */ /* end of group QuadSPI_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 11555
kadonotakashi 0:8fdf9a60065b 11556
kadonotakashi 0:8fdf9a60065b 11557 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 11558 -- RCM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 11559 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 11560
kadonotakashi 0:8fdf9a60065b 11561 /*!
kadonotakashi 0:8fdf9a60065b 11562 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 11563 * @{
kadonotakashi 0:8fdf9a60065b 11564 */
kadonotakashi 0:8fdf9a60065b 11565
kadonotakashi 0:8fdf9a60065b 11566 /** RCM - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 11567 typedef struct {
kadonotakashi 0:8fdf9a60065b 11568 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 11569 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 11570 uint8_t RESERVED_0[2];
kadonotakashi 0:8fdf9a60065b 11571 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 11572 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
kadonotakashi 0:8fdf9a60065b 11573 __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */
kadonotakashi 0:8fdf9a60065b 11574 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */
kadonotakashi 0:8fdf9a60065b 11575 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 11576 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
kadonotakashi 0:8fdf9a60065b 11577 } RCM_Type;
kadonotakashi 0:8fdf9a60065b 11578
kadonotakashi 0:8fdf9a60065b 11579 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 11580 -- RCM Register Masks
kadonotakashi 0:8fdf9a60065b 11581 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 11582
kadonotakashi 0:8fdf9a60065b 11583 /*!
kadonotakashi 0:8fdf9a60065b 11584 * @addtogroup RCM_Register_Masks RCM Register Masks
kadonotakashi 0:8fdf9a60065b 11585 * @{
kadonotakashi 0:8fdf9a60065b 11586 */
kadonotakashi 0:8fdf9a60065b 11587
kadonotakashi 0:8fdf9a60065b 11588 /*! @name SRS0 - System Reset Status Register 0 */
kadonotakashi 0:8fdf9a60065b 11589 #define RCM_SRS0_WAKEUP_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11590 #define RCM_SRS0_WAKEUP_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11591 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
kadonotakashi 0:8fdf9a60065b 11592 #define RCM_SRS0_LVD_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11593 #define RCM_SRS0_LVD_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11594 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
kadonotakashi 0:8fdf9a60065b 11595 #define RCM_SRS0_LOC_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 11596 #define RCM_SRS0_LOC_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11597 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
kadonotakashi 0:8fdf9a60065b 11598 #define RCM_SRS0_LOL_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 11599 #define RCM_SRS0_LOL_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 11600 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
kadonotakashi 0:8fdf9a60065b 11601 #define RCM_SRS0_WDOG_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 11602 #define RCM_SRS0_WDOG_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 11603 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
kadonotakashi 0:8fdf9a60065b 11604 #define RCM_SRS0_PIN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 11605 #define RCM_SRS0_PIN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 11606 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
kadonotakashi 0:8fdf9a60065b 11607 #define RCM_SRS0_POR_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 11608 #define RCM_SRS0_POR_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 11609 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
kadonotakashi 0:8fdf9a60065b 11610
kadonotakashi 0:8fdf9a60065b 11611 /*! @name SRS1 - System Reset Status Register 1 */
kadonotakashi 0:8fdf9a60065b 11612 #define RCM_SRS1_JTAG_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11613 #define RCM_SRS1_JTAG_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11614 #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
kadonotakashi 0:8fdf9a60065b 11615 #define RCM_SRS1_LOCKUP_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11616 #define RCM_SRS1_LOCKUP_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11617 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
kadonotakashi 0:8fdf9a60065b 11618 #define RCM_SRS1_SW_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 11619 #define RCM_SRS1_SW_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11620 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
kadonotakashi 0:8fdf9a60065b 11621 #define RCM_SRS1_MDM_AP_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 11622 #define RCM_SRS1_MDM_AP_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 11623 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
kadonotakashi 0:8fdf9a60065b 11624 #define RCM_SRS1_SACKERR_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 11625 #define RCM_SRS1_SACKERR_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 11626 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
kadonotakashi 0:8fdf9a60065b 11627
kadonotakashi 0:8fdf9a60065b 11628 /*! @name RPFC - Reset Pin Filter Control register */
kadonotakashi 0:8fdf9a60065b 11629 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 11630 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11631 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
kadonotakashi 0:8fdf9a60065b 11632 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 11633 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11634 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
kadonotakashi 0:8fdf9a60065b 11635
kadonotakashi 0:8fdf9a60065b 11636 /*! @name RPFW - Reset Pin Filter Width register */
kadonotakashi 0:8fdf9a60065b 11637 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
kadonotakashi 0:8fdf9a60065b 11638 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11639 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
kadonotakashi 0:8fdf9a60065b 11640
kadonotakashi 0:8fdf9a60065b 11641 /*! @name FM - Force Mode Register */
kadonotakashi 0:8fdf9a60065b 11642 #define RCM_FM_FORCEROM_MASK (0x6U)
kadonotakashi 0:8fdf9a60065b 11643 #define RCM_FM_FORCEROM_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11644 #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK)
kadonotakashi 0:8fdf9a60065b 11645
kadonotakashi 0:8fdf9a60065b 11646 /*! @name MR - Mode Register */
kadonotakashi 0:8fdf9a60065b 11647 #define RCM_MR_BOOTROM_MASK (0x6U)
kadonotakashi 0:8fdf9a60065b 11648 #define RCM_MR_BOOTROM_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11649 #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK)
kadonotakashi 0:8fdf9a60065b 11650
kadonotakashi 0:8fdf9a60065b 11651 /*! @name SSRS0 - Sticky System Reset Status Register 0 */
kadonotakashi 0:8fdf9a60065b 11652 #define RCM_SSRS0_SWAKEUP_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11653 #define RCM_SSRS0_SWAKEUP_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11654 #define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
kadonotakashi 0:8fdf9a60065b 11655 #define RCM_SSRS0_SLVD_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11656 #define RCM_SSRS0_SLVD_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11657 #define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
kadonotakashi 0:8fdf9a60065b 11658 #define RCM_SSRS0_SLOC_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 11659 #define RCM_SSRS0_SLOC_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11660 #define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
kadonotakashi 0:8fdf9a60065b 11661 #define RCM_SSRS0_SLOL_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 11662 #define RCM_SSRS0_SLOL_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 11663 #define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
kadonotakashi 0:8fdf9a60065b 11664 #define RCM_SSRS0_SWDOG_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 11665 #define RCM_SSRS0_SWDOG_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 11666 #define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
kadonotakashi 0:8fdf9a60065b 11667 #define RCM_SSRS0_SPIN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 11668 #define RCM_SSRS0_SPIN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 11669 #define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
kadonotakashi 0:8fdf9a60065b 11670 #define RCM_SSRS0_SPOR_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 11671 #define RCM_SSRS0_SPOR_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 11672 #define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
kadonotakashi 0:8fdf9a60065b 11673
kadonotakashi 0:8fdf9a60065b 11674 /*! @name SSRS1 - Sticky System Reset Status Register 1 */
kadonotakashi 0:8fdf9a60065b 11675 #define RCM_SSRS1_SJTAG_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11676 #define RCM_SSRS1_SJTAG_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11677 #define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
kadonotakashi 0:8fdf9a60065b 11678 #define RCM_SSRS1_SLOCKUP_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11679 #define RCM_SSRS1_SLOCKUP_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11680 #define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
kadonotakashi 0:8fdf9a60065b 11681 #define RCM_SSRS1_SSW_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 11682 #define RCM_SSRS1_SSW_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11683 #define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
kadonotakashi 0:8fdf9a60065b 11684 #define RCM_SSRS1_SMDM_AP_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 11685 #define RCM_SSRS1_SMDM_AP_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 11686 #define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
kadonotakashi 0:8fdf9a60065b 11687 #define RCM_SSRS1_SSACKERR_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 11688 #define RCM_SSRS1_SSACKERR_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 11689 #define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
kadonotakashi 0:8fdf9a60065b 11690
kadonotakashi 0:8fdf9a60065b 11691
kadonotakashi 0:8fdf9a60065b 11692 /*!
kadonotakashi 0:8fdf9a60065b 11693 * @}
kadonotakashi 0:8fdf9a60065b 11694 */ /* end of group RCM_Register_Masks */
kadonotakashi 0:8fdf9a60065b 11695
kadonotakashi 0:8fdf9a60065b 11696
kadonotakashi 0:8fdf9a60065b 11697 /* RCM - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 11698 /** Peripheral RCM base address */
kadonotakashi 0:8fdf9a60065b 11699 #define RCM_BASE (0x4007F000u)
kadonotakashi 0:8fdf9a60065b 11700 /** Peripheral RCM base pointer */
kadonotakashi 0:8fdf9a60065b 11701 #define RCM ((RCM_Type *)RCM_BASE)
kadonotakashi 0:8fdf9a60065b 11702 /** Array initializer of RCM peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 11703 #define RCM_BASE_ADDRS { RCM_BASE }
kadonotakashi 0:8fdf9a60065b 11704 /** Array initializer of RCM peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 11705 #define RCM_BASE_PTRS { RCM }
kadonotakashi 0:8fdf9a60065b 11706
kadonotakashi 0:8fdf9a60065b 11707 /*!
kadonotakashi 0:8fdf9a60065b 11708 * @}
kadonotakashi 0:8fdf9a60065b 11709 */ /* end of group RCM_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 11710
kadonotakashi 0:8fdf9a60065b 11711
kadonotakashi 0:8fdf9a60065b 11712 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 11713 -- RFSYS Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 11714 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 11715
kadonotakashi 0:8fdf9a60065b 11716 /*!
kadonotakashi 0:8fdf9a60065b 11717 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 11718 * @{
kadonotakashi 0:8fdf9a60065b 11719 */
kadonotakashi 0:8fdf9a60065b 11720
kadonotakashi 0:8fdf9a60065b 11721 /** RFSYS - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 11722 typedef struct {
kadonotakashi 0:8fdf9a60065b 11723 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 11724 } RFSYS_Type;
kadonotakashi 0:8fdf9a60065b 11725
kadonotakashi 0:8fdf9a60065b 11726 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 11727 -- RFSYS Register Masks
kadonotakashi 0:8fdf9a60065b 11728 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 11729
kadonotakashi 0:8fdf9a60065b 11730 /*!
kadonotakashi 0:8fdf9a60065b 11731 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
kadonotakashi 0:8fdf9a60065b 11732 * @{
kadonotakashi 0:8fdf9a60065b 11733 */
kadonotakashi 0:8fdf9a60065b 11734
kadonotakashi 0:8fdf9a60065b 11735 /*! @name REG - Register file register */
kadonotakashi 0:8fdf9a60065b 11736 #define RFSYS_REG_LL_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 11737 #define RFSYS_REG_LL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11738 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
kadonotakashi 0:8fdf9a60065b 11739 #define RFSYS_REG_LH_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 11740 #define RFSYS_REG_LH_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11741 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
kadonotakashi 0:8fdf9a60065b 11742 #define RFSYS_REG_HL_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 11743 #define RFSYS_REG_HL_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11744 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
kadonotakashi 0:8fdf9a60065b 11745 #define RFSYS_REG_HH_MASK (0xFF000000U)
kadonotakashi 0:8fdf9a60065b 11746 #define RFSYS_REG_HH_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 11747 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
kadonotakashi 0:8fdf9a60065b 11748
kadonotakashi 0:8fdf9a60065b 11749 /* The count of RFSYS_REG */
kadonotakashi 0:8fdf9a60065b 11750 #define RFSYS_REG_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 11751
kadonotakashi 0:8fdf9a60065b 11752
kadonotakashi 0:8fdf9a60065b 11753 /*!
kadonotakashi 0:8fdf9a60065b 11754 * @}
kadonotakashi 0:8fdf9a60065b 11755 */ /* end of group RFSYS_Register_Masks */
kadonotakashi 0:8fdf9a60065b 11756
kadonotakashi 0:8fdf9a60065b 11757
kadonotakashi 0:8fdf9a60065b 11758 /* RFSYS - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 11759 /** Peripheral RFSYS base address */
kadonotakashi 0:8fdf9a60065b 11760 #define RFSYS_BASE (0x40041000u)
kadonotakashi 0:8fdf9a60065b 11761 /** Peripheral RFSYS base pointer */
kadonotakashi 0:8fdf9a60065b 11762 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
kadonotakashi 0:8fdf9a60065b 11763 /** Array initializer of RFSYS peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 11764 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
kadonotakashi 0:8fdf9a60065b 11765 /** Array initializer of RFSYS peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 11766 #define RFSYS_BASE_PTRS { RFSYS }
kadonotakashi 0:8fdf9a60065b 11767
kadonotakashi 0:8fdf9a60065b 11768 /*!
kadonotakashi 0:8fdf9a60065b 11769 * @}
kadonotakashi 0:8fdf9a60065b 11770 */ /* end of group RFSYS_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 11771
kadonotakashi 0:8fdf9a60065b 11772
kadonotakashi 0:8fdf9a60065b 11773 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 11774 -- RFVBAT Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 11775 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 11776
kadonotakashi 0:8fdf9a60065b 11777 /*!
kadonotakashi 0:8fdf9a60065b 11778 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 11779 * @{
kadonotakashi 0:8fdf9a60065b 11780 */
kadonotakashi 0:8fdf9a60065b 11781
kadonotakashi 0:8fdf9a60065b 11782 /** RFVBAT - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 11783 typedef struct {
kadonotakashi 0:8fdf9a60065b 11784 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 11785 } RFVBAT_Type;
kadonotakashi 0:8fdf9a60065b 11786
kadonotakashi 0:8fdf9a60065b 11787 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 11788 -- RFVBAT Register Masks
kadonotakashi 0:8fdf9a60065b 11789 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 11790
kadonotakashi 0:8fdf9a60065b 11791 /*!
kadonotakashi 0:8fdf9a60065b 11792 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
kadonotakashi 0:8fdf9a60065b 11793 * @{
kadonotakashi 0:8fdf9a60065b 11794 */
kadonotakashi 0:8fdf9a60065b 11795
kadonotakashi 0:8fdf9a60065b 11796 /*! @name REG - VBAT register file register */
kadonotakashi 0:8fdf9a60065b 11797 #define RFVBAT_REG_LL_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 11798 #define RFVBAT_REG_LL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11799 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
kadonotakashi 0:8fdf9a60065b 11800 #define RFVBAT_REG_LH_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 11801 #define RFVBAT_REG_LH_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11802 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
kadonotakashi 0:8fdf9a60065b 11803 #define RFVBAT_REG_HL_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 11804 #define RFVBAT_REG_HL_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11805 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
kadonotakashi 0:8fdf9a60065b 11806 #define RFVBAT_REG_HH_MASK (0xFF000000U)
kadonotakashi 0:8fdf9a60065b 11807 #define RFVBAT_REG_HH_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 11808 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
kadonotakashi 0:8fdf9a60065b 11809
kadonotakashi 0:8fdf9a60065b 11810 /* The count of RFVBAT_REG */
kadonotakashi 0:8fdf9a60065b 11811 #define RFVBAT_REG_COUNT (8U)
kadonotakashi 0:8fdf9a60065b 11812
kadonotakashi 0:8fdf9a60065b 11813
kadonotakashi 0:8fdf9a60065b 11814 /*!
kadonotakashi 0:8fdf9a60065b 11815 * @}
kadonotakashi 0:8fdf9a60065b 11816 */ /* end of group RFVBAT_Register_Masks */
kadonotakashi 0:8fdf9a60065b 11817
kadonotakashi 0:8fdf9a60065b 11818
kadonotakashi 0:8fdf9a60065b 11819 /* RFVBAT - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 11820 /** Peripheral RFVBAT base address */
kadonotakashi 0:8fdf9a60065b 11821 #define RFVBAT_BASE (0x4003E000u)
kadonotakashi 0:8fdf9a60065b 11822 /** Peripheral RFVBAT base pointer */
kadonotakashi 0:8fdf9a60065b 11823 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
kadonotakashi 0:8fdf9a60065b 11824 /** Array initializer of RFVBAT peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 11825 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
kadonotakashi 0:8fdf9a60065b 11826 /** Array initializer of RFVBAT peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 11827 #define RFVBAT_BASE_PTRS { RFVBAT }
kadonotakashi 0:8fdf9a60065b 11828
kadonotakashi 0:8fdf9a60065b 11829 /*!
kadonotakashi 0:8fdf9a60065b 11830 * @}
kadonotakashi 0:8fdf9a60065b 11831 */ /* end of group RFVBAT_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 11832
kadonotakashi 0:8fdf9a60065b 11833
kadonotakashi 0:8fdf9a60065b 11834 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 11835 -- RTC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 11836 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 11837
kadonotakashi 0:8fdf9a60065b 11838 /*!
kadonotakashi 0:8fdf9a60065b 11839 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 11840 * @{
kadonotakashi 0:8fdf9a60065b 11841 */
kadonotakashi 0:8fdf9a60065b 11842
kadonotakashi 0:8fdf9a60065b 11843 /** RTC - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 11844 typedef struct {
kadonotakashi 0:8fdf9a60065b 11845 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 11846 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 11847 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 11848 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 11849 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 11850 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 11851 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 11852 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
kadonotakashi 0:8fdf9a60065b 11853 uint8_t RESERVED_0[2016];
kadonotakashi 0:8fdf9a60065b 11854 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
kadonotakashi 0:8fdf9a60065b 11855 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
kadonotakashi 0:8fdf9a60065b 11856 } RTC_Type;
kadonotakashi 0:8fdf9a60065b 11857
kadonotakashi 0:8fdf9a60065b 11858 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 11859 -- RTC Register Masks
kadonotakashi 0:8fdf9a60065b 11860 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 11861
kadonotakashi 0:8fdf9a60065b 11862 /*!
kadonotakashi 0:8fdf9a60065b 11863 * @addtogroup RTC_Register_Masks RTC Register Masks
kadonotakashi 0:8fdf9a60065b 11864 * @{
kadonotakashi 0:8fdf9a60065b 11865 */
kadonotakashi 0:8fdf9a60065b 11866
kadonotakashi 0:8fdf9a60065b 11867 /*! @name TSR - RTC Time Seconds Register */
kadonotakashi 0:8fdf9a60065b 11868 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 11869 #define RTC_TSR_TSR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11870 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
kadonotakashi 0:8fdf9a60065b 11871
kadonotakashi 0:8fdf9a60065b 11872 /*! @name TPR - RTC Time Prescaler Register */
kadonotakashi 0:8fdf9a60065b 11873 #define RTC_TPR_TPR_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 11874 #define RTC_TPR_TPR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11875 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
kadonotakashi 0:8fdf9a60065b 11876
kadonotakashi 0:8fdf9a60065b 11877 /*! @name TAR - RTC Time Alarm Register */
kadonotakashi 0:8fdf9a60065b 11878 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 11879 #define RTC_TAR_TAR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11880 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
kadonotakashi 0:8fdf9a60065b 11881
kadonotakashi 0:8fdf9a60065b 11882 /*! @name TCR - RTC Time Compensation Register */
kadonotakashi 0:8fdf9a60065b 11883 #define RTC_TCR_TCR_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 11884 #define RTC_TCR_TCR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11885 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
kadonotakashi 0:8fdf9a60065b 11886 #define RTC_TCR_CIR_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 11887 #define RTC_TCR_CIR_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11888 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
kadonotakashi 0:8fdf9a60065b 11889 #define RTC_TCR_TCV_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 11890 #define RTC_TCR_TCV_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 11891 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
kadonotakashi 0:8fdf9a60065b 11892 #define RTC_TCR_CIC_MASK (0xFF000000U)
kadonotakashi 0:8fdf9a60065b 11893 #define RTC_TCR_CIC_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 11894 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
kadonotakashi 0:8fdf9a60065b 11895
kadonotakashi 0:8fdf9a60065b 11896 /*! @name CR - RTC Control Register */
kadonotakashi 0:8fdf9a60065b 11897 #define RTC_CR_SWR_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11898 #define RTC_CR_SWR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11899 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
kadonotakashi 0:8fdf9a60065b 11900 #define RTC_CR_WPE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11901 #define RTC_CR_WPE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11902 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
kadonotakashi 0:8fdf9a60065b 11903 #define RTC_CR_SUP_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 11904 #define RTC_CR_SUP_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11905 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
kadonotakashi 0:8fdf9a60065b 11906 #define RTC_CR_UM_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 11907 #define RTC_CR_UM_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 11908 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
kadonotakashi 0:8fdf9a60065b 11909 #define RTC_CR_WPS_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 11910 #define RTC_CR_WPS_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 11911 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
kadonotakashi 0:8fdf9a60065b 11912 #define RTC_CR_OSCE_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 11913 #define RTC_CR_OSCE_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 11914 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
kadonotakashi 0:8fdf9a60065b 11915 #define RTC_CR_CLKO_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 11916 #define RTC_CR_CLKO_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 11917 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
kadonotakashi 0:8fdf9a60065b 11918 #define RTC_CR_SC16P_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 11919 #define RTC_CR_SC16P_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 11920 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
kadonotakashi 0:8fdf9a60065b 11921 #define RTC_CR_SC8P_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 11922 #define RTC_CR_SC8P_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 11923 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
kadonotakashi 0:8fdf9a60065b 11924 #define RTC_CR_SC4P_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 11925 #define RTC_CR_SC4P_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 11926 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
kadonotakashi 0:8fdf9a60065b 11927 #define RTC_CR_SC2P_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 11928 #define RTC_CR_SC2P_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 11929 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
kadonotakashi 0:8fdf9a60065b 11930
kadonotakashi 0:8fdf9a60065b 11931 /*! @name SR - RTC Status Register */
kadonotakashi 0:8fdf9a60065b 11932 #define RTC_SR_TIF_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11933 #define RTC_SR_TIF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11934 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
kadonotakashi 0:8fdf9a60065b 11935 #define RTC_SR_TOF_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11936 #define RTC_SR_TOF_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11937 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
kadonotakashi 0:8fdf9a60065b 11938 #define RTC_SR_TAF_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 11939 #define RTC_SR_TAF_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11940 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
kadonotakashi 0:8fdf9a60065b 11941 #define RTC_SR_TCE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 11942 #define RTC_SR_TCE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 11943 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
kadonotakashi 0:8fdf9a60065b 11944
kadonotakashi 0:8fdf9a60065b 11945 /*! @name LR - RTC Lock Register */
kadonotakashi 0:8fdf9a60065b 11946 #define RTC_LR_TCL_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 11947 #define RTC_LR_TCL_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 11948 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
kadonotakashi 0:8fdf9a60065b 11949 #define RTC_LR_CRL_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 11950 #define RTC_LR_CRL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 11951 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
kadonotakashi 0:8fdf9a60065b 11952 #define RTC_LR_SRL_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 11953 #define RTC_LR_SRL_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 11954 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
kadonotakashi 0:8fdf9a60065b 11955 #define RTC_LR_LRL_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 11956 #define RTC_LR_LRL_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 11957 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
kadonotakashi 0:8fdf9a60065b 11958
kadonotakashi 0:8fdf9a60065b 11959 /*! @name IER - RTC Interrupt Enable Register */
kadonotakashi 0:8fdf9a60065b 11960 #define RTC_IER_TIIE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11961 #define RTC_IER_TIIE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11962 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
kadonotakashi 0:8fdf9a60065b 11963 #define RTC_IER_TOIE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11964 #define RTC_IER_TOIE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11965 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
kadonotakashi 0:8fdf9a60065b 11966 #define RTC_IER_TAIE_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 11967 #define RTC_IER_TAIE_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11968 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
kadonotakashi 0:8fdf9a60065b 11969 #define RTC_IER_TSIE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 11970 #define RTC_IER_TSIE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 11971 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
kadonotakashi 0:8fdf9a60065b 11972 #define RTC_IER_WPON_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 11973 #define RTC_IER_WPON_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 11974 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
kadonotakashi 0:8fdf9a60065b 11975
kadonotakashi 0:8fdf9a60065b 11976 /*! @name WAR - RTC Write Access Register */
kadonotakashi 0:8fdf9a60065b 11977 #define RTC_WAR_TSRW_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 11978 #define RTC_WAR_TSRW_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 11979 #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
kadonotakashi 0:8fdf9a60065b 11980 #define RTC_WAR_TPRW_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 11981 #define RTC_WAR_TPRW_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 11982 #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
kadonotakashi 0:8fdf9a60065b 11983 #define RTC_WAR_TARW_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 11984 #define RTC_WAR_TARW_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 11985 #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
kadonotakashi 0:8fdf9a60065b 11986 #define RTC_WAR_TCRW_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 11987 #define RTC_WAR_TCRW_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 11988 #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
kadonotakashi 0:8fdf9a60065b 11989 #define RTC_WAR_CRW_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 11990 #define RTC_WAR_CRW_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 11991 #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
kadonotakashi 0:8fdf9a60065b 11992 #define RTC_WAR_SRW_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 11993 #define RTC_WAR_SRW_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 11994 #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
kadonotakashi 0:8fdf9a60065b 11995 #define RTC_WAR_LRW_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 11996 #define RTC_WAR_LRW_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 11997 #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
kadonotakashi 0:8fdf9a60065b 11998 #define RTC_WAR_IERW_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 11999 #define RTC_WAR_IERW_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 12000 #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
kadonotakashi 0:8fdf9a60065b 12001
kadonotakashi 0:8fdf9a60065b 12002 /*! @name RAR - RTC Read Access Register */
kadonotakashi 0:8fdf9a60065b 12003 #define RTC_RAR_TSRR_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12004 #define RTC_RAR_TSRR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12005 #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
kadonotakashi 0:8fdf9a60065b 12006 #define RTC_RAR_TPRR_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12007 #define RTC_RAR_TPRR_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12008 #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
kadonotakashi 0:8fdf9a60065b 12009 #define RTC_RAR_TARR_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 12010 #define RTC_RAR_TARR_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12011 #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
kadonotakashi 0:8fdf9a60065b 12012 #define RTC_RAR_TCRR_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12013 #define RTC_RAR_TCRR_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12014 #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
kadonotakashi 0:8fdf9a60065b 12015 #define RTC_RAR_CRR_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12016 #define RTC_RAR_CRR_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12017 #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
kadonotakashi 0:8fdf9a60065b 12018 #define RTC_RAR_SRR_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 12019 #define RTC_RAR_SRR_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 12020 #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
kadonotakashi 0:8fdf9a60065b 12021 #define RTC_RAR_LRR_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 12022 #define RTC_RAR_LRR_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 12023 #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
kadonotakashi 0:8fdf9a60065b 12024 #define RTC_RAR_IERR_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 12025 #define RTC_RAR_IERR_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 12026 #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
kadonotakashi 0:8fdf9a60065b 12027
kadonotakashi 0:8fdf9a60065b 12028
kadonotakashi 0:8fdf9a60065b 12029 /*!
kadonotakashi 0:8fdf9a60065b 12030 * @}
kadonotakashi 0:8fdf9a60065b 12031 */ /* end of group RTC_Register_Masks */
kadonotakashi 0:8fdf9a60065b 12032
kadonotakashi 0:8fdf9a60065b 12033
kadonotakashi 0:8fdf9a60065b 12034 /* RTC - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 12035 /** Peripheral RTC base address */
kadonotakashi 0:8fdf9a60065b 12036 #define RTC_BASE (0x4003D000u)
kadonotakashi 0:8fdf9a60065b 12037 /** Peripheral RTC base pointer */
kadonotakashi 0:8fdf9a60065b 12038 #define RTC ((RTC_Type *)RTC_BASE)
kadonotakashi 0:8fdf9a60065b 12039 /** Array initializer of RTC peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 12040 #define RTC_BASE_ADDRS { RTC_BASE }
kadonotakashi 0:8fdf9a60065b 12041 /** Array initializer of RTC peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 12042 #define RTC_BASE_PTRS { RTC }
kadonotakashi 0:8fdf9a60065b 12043 /** Interrupt vectors for the RTC peripheral type */
kadonotakashi 0:8fdf9a60065b 12044 #define RTC_IRQS { RTC_IRQn }
kadonotakashi 0:8fdf9a60065b 12045 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
kadonotakashi 0:8fdf9a60065b 12046
kadonotakashi 0:8fdf9a60065b 12047 /*!
kadonotakashi 0:8fdf9a60065b 12048 * @}
kadonotakashi 0:8fdf9a60065b 12049 */ /* end of group RTC_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 12050
kadonotakashi 0:8fdf9a60065b 12051
kadonotakashi 0:8fdf9a60065b 12052 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 12053 -- SDHC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 12054 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 12055
kadonotakashi 0:8fdf9a60065b 12056 /*!
kadonotakashi 0:8fdf9a60065b 12057 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 12058 * @{
kadonotakashi 0:8fdf9a60065b 12059 */
kadonotakashi 0:8fdf9a60065b 12060
kadonotakashi 0:8fdf9a60065b 12061 /** SDHC - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 12062 typedef struct {
kadonotakashi 0:8fdf9a60065b 12063 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 12064 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 12065 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 12066 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 12067 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 12068 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 12069 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 12070 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
kadonotakashi 0:8fdf9a60065b 12071 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
kadonotakashi 0:8fdf9a60065b 12072 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
kadonotakashi 0:8fdf9a60065b 12073 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 12074 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
kadonotakashi 0:8fdf9a60065b 12075 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
kadonotakashi 0:8fdf9a60065b 12076 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
kadonotakashi 0:8fdf9a60065b 12077 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
kadonotakashi 0:8fdf9a60065b 12078 uint8_t RESERVED_0[8];
kadonotakashi 0:8fdf9a60065b 12079 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
kadonotakashi 0:8fdf9a60065b 12080 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
kadonotakashi 0:8fdf9a60065b 12081 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
kadonotakashi 0:8fdf9a60065b 12082 uint8_t RESERVED_1[100];
kadonotakashi 0:8fdf9a60065b 12083 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
kadonotakashi 0:8fdf9a60065b 12084 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
kadonotakashi 0:8fdf9a60065b 12085 uint8_t RESERVED_2[52];
kadonotakashi 0:8fdf9a60065b 12086 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
kadonotakashi 0:8fdf9a60065b 12087 } SDHC_Type;
kadonotakashi 0:8fdf9a60065b 12088
kadonotakashi 0:8fdf9a60065b 12089 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 12090 -- SDHC Register Masks
kadonotakashi 0:8fdf9a60065b 12091 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 12092
kadonotakashi 0:8fdf9a60065b 12093 /*!
kadonotakashi 0:8fdf9a60065b 12094 * @addtogroup SDHC_Register_Masks SDHC Register Masks
kadonotakashi 0:8fdf9a60065b 12095 * @{
kadonotakashi 0:8fdf9a60065b 12096 */
kadonotakashi 0:8fdf9a60065b 12097
kadonotakashi 0:8fdf9a60065b 12098 /*! @name DSADDR - DMA System Address register */
kadonotakashi 0:8fdf9a60065b 12099 #define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
kadonotakashi 0:8fdf9a60065b 12100 #define SDHC_DSADDR_DSADDR_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12101 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
kadonotakashi 0:8fdf9a60065b 12102
kadonotakashi 0:8fdf9a60065b 12103 /*! @name BLKATTR - Block Attributes register */
kadonotakashi 0:8fdf9a60065b 12104 #define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
kadonotakashi 0:8fdf9a60065b 12105 #define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12106 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
kadonotakashi 0:8fdf9a60065b 12107 #define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 12108 #define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12109 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
kadonotakashi 0:8fdf9a60065b 12110
kadonotakashi 0:8fdf9a60065b 12111 /*! @name CMDARG - Command Argument register */
kadonotakashi 0:8fdf9a60065b 12112 #define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 12113 #define SDHC_CMDARG_CMDARG_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12114 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
kadonotakashi 0:8fdf9a60065b 12115
kadonotakashi 0:8fdf9a60065b 12116 /*! @name XFERTYP - Transfer Type register */
kadonotakashi 0:8fdf9a60065b 12117 #define SDHC_XFERTYP_DMAEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12118 #define SDHC_XFERTYP_DMAEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12119 #define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
kadonotakashi 0:8fdf9a60065b 12120 #define SDHC_XFERTYP_BCEN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12121 #define SDHC_XFERTYP_BCEN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12122 #define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
kadonotakashi 0:8fdf9a60065b 12123 #define SDHC_XFERTYP_AC12EN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 12124 #define SDHC_XFERTYP_AC12EN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12125 #define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
kadonotakashi 0:8fdf9a60065b 12126 #define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12127 #define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12128 #define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12129 #define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 12130 #define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 12131 #define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12132 #define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 12133 #define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12134 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
kadonotakashi 0:8fdf9a60065b 12135 #define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 12136 #define SDHC_XFERTYP_CCCEN_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 12137 #define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
kadonotakashi 0:8fdf9a60065b 12138 #define SDHC_XFERTYP_CICEN_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 12139 #define SDHC_XFERTYP_CICEN_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 12140 #define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
kadonotakashi 0:8fdf9a60065b 12141 #define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 12142 #define SDHC_XFERTYP_DPSEL_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 12143 #define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12144 #define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
kadonotakashi 0:8fdf9a60065b 12145 #define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 12146 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
kadonotakashi 0:8fdf9a60065b 12147 #define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
kadonotakashi 0:8fdf9a60065b 12148 #define SDHC_XFERTYP_CMDINX_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12149 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
kadonotakashi 0:8fdf9a60065b 12150
kadonotakashi 0:8fdf9a60065b 12151 /*! @name CMDRSP - Command Response 0..Command Response 3 */
kadonotakashi 0:8fdf9a60065b 12152 #define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 12153 #define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12154 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
kadonotakashi 0:8fdf9a60065b 12155 #define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 12156 #define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12157 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
kadonotakashi 0:8fdf9a60065b 12158 #define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 12159 #define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12160 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
kadonotakashi 0:8fdf9a60065b 12161 #define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 12162 #define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12163 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
kadonotakashi 0:8fdf9a60065b 12164
kadonotakashi 0:8fdf9a60065b 12165 /* The count of SDHC_CMDRSP */
kadonotakashi 0:8fdf9a60065b 12166 #define SDHC_CMDRSP_COUNT (4U)
kadonotakashi 0:8fdf9a60065b 12167
kadonotakashi 0:8fdf9a60065b 12168 /*! @name DATPORT - Buffer Data Port register */
kadonotakashi 0:8fdf9a60065b 12169 #define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 12170 #define SDHC_DATPORT_DATCONT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12171 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
kadonotakashi 0:8fdf9a60065b 12172
kadonotakashi 0:8fdf9a60065b 12173 /*! @name PRSSTAT - Present State register */
kadonotakashi 0:8fdf9a60065b 12174 #define SDHC_PRSSTAT_CIHB_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12175 #define SDHC_PRSSTAT_CIHB_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12176 #define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
kadonotakashi 0:8fdf9a60065b 12177 #define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12178 #define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12179 #define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
kadonotakashi 0:8fdf9a60065b 12180 #define SDHC_PRSSTAT_DLA_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 12181 #define SDHC_PRSSTAT_DLA_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12182 #define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
kadonotakashi 0:8fdf9a60065b 12183 #define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12184 #define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12185 #define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
kadonotakashi 0:8fdf9a60065b 12186 #define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12187 #define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12188 #define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
kadonotakashi 0:8fdf9a60065b 12189 #define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 12190 #define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 12191 #define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
kadonotakashi 0:8fdf9a60065b 12192 #define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 12193 #define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 12194 #define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
kadonotakashi 0:8fdf9a60065b 12195 #define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 12196 #define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 12197 #define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
kadonotakashi 0:8fdf9a60065b 12198 #define SDHC_PRSSTAT_WTA_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 12199 #define SDHC_PRSSTAT_WTA_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 12200 #define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
kadonotakashi 0:8fdf9a60065b 12201 #define SDHC_PRSSTAT_RTA_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 12202 #define SDHC_PRSSTAT_RTA_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 12203 #define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
kadonotakashi 0:8fdf9a60065b 12204 #define SDHC_PRSSTAT_BWEN_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 12205 #define SDHC_PRSSTAT_BWEN_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 12206 #define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
kadonotakashi 0:8fdf9a60065b 12207 #define SDHC_PRSSTAT_BREN_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 12208 #define SDHC_PRSSTAT_BREN_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 12209 #define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
kadonotakashi 0:8fdf9a60065b 12210 #define SDHC_PRSSTAT_CINS_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 12211 #define SDHC_PRSSTAT_CINS_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12212 #define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
kadonotakashi 0:8fdf9a60065b 12213 #define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 12214 #define SDHC_PRSSTAT_CLSL_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 12215 #define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
kadonotakashi 0:8fdf9a60065b 12216 #define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
kadonotakashi 0:8fdf9a60065b 12217 #define SDHC_PRSSTAT_DLSL_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12218 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
kadonotakashi 0:8fdf9a60065b 12219
kadonotakashi 0:8fdf9a60065b 12220 /*! @name PROCTL - Protocol Control register */
kadonotakashi 0:8fdf9a60065b 12221 #define SDHC_PROCTL_LCTL_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12222 #define SDHC_PROCTL_LCTL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12223 #define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
kadonotakashi 0:8fdf9a60065b 12224 #define SDHC_PROCTL_DTW_MASK (0x6U)
kadonotakashi 0:8fdf9a60065b 12225 #define SDHC_PROCTL_DTW_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12226 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
kadonotakashi 0:8fdf9a60065b 12227 #define SDHC_PROCTL_D3CD_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12228 #define SDHC_PROCTL_D3CD_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12229 #define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
kadonotakashi 0:8fdf9a60065b 12230 #define SDHC_PROCTL_EMODE_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 12231 #define SDHC_PROCTL_EMODE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12232 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
kadonotakashi 0:8fdf9a60065b 12233 #define SDHC_PROCTL_CDTL_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 12234 #define SDHC_PROCTL_CDTL_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 12235 #define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
kadonotakashi 0:8fdf9a60065b 12236 #define SDHC_PROCTL_CDSS_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 12237 #define SDHC_PROCTL_CDSS_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 12238 #define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
kadonotakashi 0:8fdf9a60065b 12239 #define SDHC_PROCTL_DMAS_MASK (0x300U)
kadonotakashi 0:8fdf9a60065b 12240 #define SDHC_PROCTL_DMAS_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 12241 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
kadonotakashi 0:8fdf9a60065b 12242 #define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 12243 #define SDHC_PROCTL_SABGREQ_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12244 #define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
kadonotakashi 0:8fdf9a60065b 12245 #define SDHC_PROCTL_CREQ_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 12246 #define SDHC_PROCTL_CREQ_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 12247 #define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
kadonotakashi 0:8fdf9a60065b 12248 #define SDHC_PROCTL_RWCTL_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 12249 #define SDHC_PROCTL_RWCTL_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12250 #define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
kadonotakashi 0:8fdf9a60065b 12251 #define SDHC_PROCTL_IABG_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 12252 #define SDHC_PROCTL_IABG_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 12253 #define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
kadonotakashi 0:8fdf9a60065b 12254 #define SDHC_PROCTL_WECINT_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 12255 #define SDHC_PROCTL_WECINT_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12256 #define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
kadonotakashi 0:8fdf9a60065b 12257 #define SDHC_PROCTL_WECINS_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 12258 #define SDHC_PROCTL_WECINS_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 12259 #define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
kadonotakashi 0:8fdf9a60065b 12260 #define SDHC_PROCTL_WECRM_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 12261 #define SDHC_PROCTL_WECRM_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 12262 #define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
kadonotakashi 0:8fdf9a60065b 12263
kadonotakashi 0:8fdf9a60065b 12264 /*! @name SYSCTL - System Control register */
kadonotakashi 0:8fdf9a60065b 12265 #define SDHC_SYSCTL_IPGEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12266 #define SDHC_SYSCTL_IPGEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12267 #define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
kadonotakashi 0:8fdf9a60065b 12268 #define SDHC_SYSCTL_HCKEN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12269 #define SDHC_SYSCTL_HCKEN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12270 #define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
kadonotakashi 0:8fdf9a60065b 12271 #define SDHC_SYSCTL_PEREN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 12272 #define SDHC_SYSCTL_PEREN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12273 #define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
kadonotakashi 0:8fdf9a60065b 12274 #define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12275 #define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12276 #define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
kadonotakashi 0:8fdf9a60065b 12277 #define SDHC_SYSCTL_DVS_MASK (0xF0U)
kadonotakashi 0:8fdf9a60065b 12278 #define SDHC_SYSCTL_DVS_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12279 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
kadonotakashi 0:8fdf9a60065b 12280 #define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 12281 #define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 12282 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
kadonotakashi 0:8fdf9a60065b 12283 #define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 12284 #define SDHC_SYSCTL_DTOCV_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12285 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
kadonotakashi 0:8fdf9a60065b 12286 #define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 12287 #define SDHC_SYSCTL_RSTA_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12288 #define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
kadonotakashi 0:8fdf9a60065b 12289 #define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 12290 #define SDHC_SYSCTL_RSTC_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 12291 #define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
kadonotakashi 0:8fdf9a60065b 12292 #define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 12293 #define SDHC_SYSCTL_RSTD_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 12294 #define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
kadonotakashi 0:8fdf9a60065b 12295 #define SDHC_SYSCTL_INITA_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 12296 #define SDHC_SYSCTL_INITA_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 12297 #define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
kadonotakashi 0:8fdf9a60065b 12298
kadonotakashi 0:8fdf9a60065b 12299 /*! @name IRQSTAT - Interrupt Status register */
kadonotakashi 0:8fdf9a60065b 12300 #define SDHC_IRQSTAT_CC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12301 #define SDHC_IRQSTAT_CC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12302 #define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
kadonotakashi 0:8fdf9a60065b 12303 #define SDHC_IRQSTAT_TC_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12304 #define SDHC_IRQSTAT_TC_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12305 #define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
kadonotakashi 0:8fdf9a60065b 12306 #define SDHC_IRQSTAT_BGE_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 12307 #define SDHC_IRQSTAT_BGE_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12308 #define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
kadonotakashi 0:8fdf9a60065b 12309 #define SDHC_IRQSTAT_DINT_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12310 #define SDHC_IRQSTAT_DINT_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12311 #define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
kadonotakashi 0:8fdf9a60065b 12312 #define SDHC_IRQSTAT_BWR_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12313 #define SDHC_IRQSTAT_BWR_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12314 #define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
kadonotakashi 0:8fdf9a60065b 12315 #define SDHC_IRQSTAT_BRR_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 12316 #define SDHC_IRQSTAT_BRR_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 12317 #define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
kadonotakashi 0:8fdf9a60065b 12318 #define SDHC_IRQSTAT_CINS_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 12319 #define SDHC_IRQSTAT_CINS_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 12320 #define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
kadonotakashi 0:8fdf9a60065b 12321 #define SDHC_IRQSTAT_CRM_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 12322 #define SDHC_IRQSTAT_CRM_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 12323 #define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
kadonotakashi 0:8fdf9a60065b 12324 #define SDHC_IRQSTAT_CINT_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 12325 #define SDHC_IRQSTAT_CINT_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 12326 #define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
kadonotakashi 0:8fdf9a60065b 12327 #define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 12328 #define SDHC_IRQSTAT_CTOE_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12329 #define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
kadonotakashi 0:8fdf9a60065b 12330 #define SDHC_IRQSTAT_CCE_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 12331 #define SDHC_IRQSTAT_CCE_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 12332 #define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
kadonotakashi 0:8fdf9a60065b 12333 #define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 12334 #define SDHC_IRQSTAT_CEBE_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12335 #define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
kadonotakashi 0:8fdf9a60065b 12336 #define SDHC_IRQSTAT_CIE_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 12337 #define SDHC_IRQSTAT_CIE_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 12338 #define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
kadonotakashi 0:8fdf9a60065b 12339 #define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 12340 #define SDHC_IRQSTAT_DTOE_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 12341 #define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
kadonotakashi 0:8fdf9a60065b 12342 #define SDHC_IRQSTAT_DCE_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 12343 #define SDHC_IRQSTAT_DCE_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 12344 #define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
kadonotakashi 0:8fdf9a60065b 12345 #define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 12346 #define SDHC_IRQSTAT_DEBE_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 12347 #define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
kadonotakashi 0:8fdf9a60065b 12348 #define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 12349 #define SDHC_IRQSTAT_AC12E_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12350 #define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
kadonotakashi 0:8fdf9a60065b 12351 #define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 12352 #define SDHC_IRQSTAT_DMAE_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 12353 #define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
kadonotakashi 0:8fdf9a60065b 12354
kadonotakashi 0:8fdf9a60065b 12355 /*! @name IRQSTATEN - Interrupt Status Enable register */
kadonotakashi 0:8fdf9a60065b 12356 #define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12357 #define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12358 #define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
kadonotakashi 0:8fdf9a60065b 12359 #define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12360 #define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12361 #define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
kadonotakashi 0:8fdf9a60065b 12362 #define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 12363 #define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12364 #define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
kadonotakashi 0:8fdf9a60065b 12365 #define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12366 #define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12367 #define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
kadonotakashi 0:8fdf9a60065b 12368 #define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12369 #define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12370 #define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
kadonotakashi 0:8fdf9a60065b 12371 #define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 12372 #define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 12373 #define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
kadonotakashi 0:8fdf9a60065b 12374 #define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 12375 #define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 12376 #define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
kadonotakashi 0:8fdf9a60065b 12377 #define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 12378 #define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 12379 #define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
kadonotakashi 0:8fdf9a60065b 12380 #define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 12381 #define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 12382 #define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
kadonotakashi 0:8fdf9a60065b 12383 #define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 12384 #define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12385 #define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
kadonotakashi 0:8fdf9a60065b 12386 #define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 12387 #define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 12388 #define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
kadonotakashi 0:8fdf9a60065b 12389 #define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 12390 #define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12391 #define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
kadonotakashi 0:8fdf9a60065b 12392 #define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 12393 #define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 12394 #define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
kadonotakashi 0:8fdf9a60065b 12395 #define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 12396 #define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 12397 #define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
kadonotakashi 0:8fdf9a60065b 12398 #define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 12399 #define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 12400 #define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
kadonotakashi 0:8fdf9a60065b 12401 #define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 12402 #define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 12403 #define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
kadonotakashi 0:8fdf9a60065b 12404 #define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 12405 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12406 #define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
kadonotakashi 0:8fdf9a60065b 12407 #define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 12408 #define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 12409 #define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
kadonotakashi 0:8fdf9a60065b 12410
kadonotakashi 0:8fdf9a60065b 12411 /*! @name IRQSIGEN - Interrupt Signal Enable register */
kadonotakashi 0:8fdf9a60065b 12412 #define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12413 #define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12414 #define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12415 #define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12416 #define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12417 #define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12418 #define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 12419 #define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12420 #define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12421 #define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12422 #define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12423 #define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12424 #define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12425 #define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12426 #define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12427 #define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 12428 #define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 12429 #define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12430 #define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 12431 #define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 12432 #define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12433 #define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 12434 #define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 12435 #define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12436 #define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 12437 #define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 12438 #define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12439 #define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 12440 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12441 #define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12442 #define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 12443 #define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 12444 #define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12445 #define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 12446 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12447 #define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12448 #define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 12449 #define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 12450 #define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12451 #define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 12452 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 12453 #define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12454 #define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 12455 #define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 12456 #define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12457 #define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 12458 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 12459 #define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12460 #define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 12461 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12462 #define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12463 #define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 12464 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 12465 #define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
kadonotakashi 0:8fdf9a60065b 12466
kadonotakashi 0:8fdf9a60065b 12467 /*! @name AC12ERR - Auto CMD12 Error Status Register */
kadonotakashi 0:8fdf9a60065b 12468 #define SDHC_AC12ERR_AC12NE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12469 #define SDHC_AC12ERR_AC12NE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12470 #define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
kadonotakashi 0:8fdf9a60065b 12471 #define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12472 #define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12473 #define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
kadonotakashi 0:8fdf9a60065b 12474 #define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 12475 #define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12476 #define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
kadonotakashi 0:8fdf9a60065b 12477 #define SDHC_AC12ERR_AC12CE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12478 #define SDHC_AC12ERR_AC12CE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12479 #define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
kadonotakashi 0:8fdf9a60065b 12480 #define SDHC_AC12ERR_AC12IE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12481 #define SDHC_AC12ERR_AC12IE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12482 #define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
kadonotakashi 0:8fdf9a60065b 12483 #define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 12484 #define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 12485 #define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
kadonotakashi 0:8fdf9a60065b 12486
kadonotakashi 0:8fdf9a60065b 12487 /*! @name HTCAPBLT - Host Controller Capabilities */
kadonotakashi 0:8fdf9a60065b 12488 #define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
kadonotakashi 0:8fdf9a60065b 12489 #define SDHC_HTCAPBLT_MBL_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12490 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
kadonotakashi 0:8fdf9a60065b 12491 #define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 12492 #define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 12493 #define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
kadonotakashi 0:8fdf9a60065b 12494 #define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 12495 #define SDHC_HTCAPBLT_HSS_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 12496 #define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
kadonotakashi 0:8fdf9a60065b 12497 #define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 12498 #define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 12499 #define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
kadonotakashi 0:8fdf9a60065b 12500 #define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 12501 #define SDHC_HTCAPBLT_SRS_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 12502 #define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
kadonotakashi 0:8fdf9a60065b 12503 #define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 12504 #define SDHC_HTCAPBLT_VS33_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12505 #define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
kadonotakashi 0:8fdf9a60065b 12506
kadonotakashi 0:8fdf9a60065b 12507 /*! @name WML - Watermark Level Register */
kadonotakashi 0:8fdf9a60065b 12508 #define SDHC_WML_RDWML_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 12509 #define SDHC_WML_RDWML_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12510 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
kadonotakashi 0:8fdf9a60065b 12511 #define SDHC_WML_WRWML_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 12512 #define SDHC_WML_WRWML_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12513 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
kadonotakashi 0:8fdf9a60065b 12514
kadonotakashi 0:8fdf9a60065b 12515 /*! @name FEVT - Force Event register */
kadonotakashi 0:8fdf9a60065b 12516 #define SDHC_FEVT_AC12NE_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12517 #define SDHC_FEVT_AC12NE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12518 #define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
kadonotakashi 0:8fdf9a60065b 12519 #define SDHC_FEVT_AC12TOE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12520 #define SDHC_FEVT_AC12TOE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12521 #define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
kadonotakashi 0:8fdf9a60065b 12522 #define SDHC_FEVT_AC12CE_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 12523 #define SDHC_FEVT_AC12CE_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12524 #define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
kadonotakashi 0:8fdf9a60065b 12525 #define SDHC_FEVT_AC12EBE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12526 #define SDHC_FEVT_AC12EBE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12527 #define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
kadonotakashi 0:8fdf9a60065b 12528 #define SDHC_FEVT_AC12IE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12529 #define SDHC_FEVT_AC12IE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12530 #define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
kadonotakashi 0:8fdf9a60065b 12531 #define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 12532 #define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 12533 #define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
kadonotakashi 0:8fdf9a60065b 12534 #define SDHC_FEVT_CTOE_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 12535 #define SDHC_FEVT_CTOE_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12536 #define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
kadonotakashi 0:8fdf9a60065b 12537 #define SDHC_FEVT_CCE_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 12538 #define SDHC_FEVT_CCE_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 12539 #define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
kadonotakashi 0:8fdf9a60065b 12540 #define SDHC_FEVT_CEBE_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 12541 #define SDHC_FEVT_CEBE_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12542 #define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
kadonotakashi 0:8fdf9a60065b 12543 #define SDHC_FEVT_CIE_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 12544 #define SDHC_FEVT_CIE_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 12545 #define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
kadonotakashi 0:8fdf9a60065b 12546 #define SDHC_FEVT_DTOE_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 12547 #define SDHC_FEVT_DTOE_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 12548 #define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
kadonotakashi 0:8fdf9a60065b 12549 #define SDHC_FEVT_DCE_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 12550 #define SDHC_FEVT_DCE_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 12551 #define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
kadonotakashi 0:8fdf9a60065b 12552 #define SDHC_FEVT_DEBE_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 12553 #define SDHC_FEVT_DEBE_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 12554 #define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
kadonotakashi 0:8fdf9a60065b 12555 #define SDHC_FEVT_AC12E_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 12556 #define SDHC_FEVT_AC12E_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12557 #define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
kadonotakashi 0:8fdf9a60065b 12558 #define SDHC_FEVT_DMAE_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 12559 #define SDHC_FEVT_DMAE_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 12560 #define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
kadonotakashi 0:8fdf9a60065b 12561 #define SDHC_FEVT_CINT_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 12562 #define SDHC_FEVT_CINT_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 12563 #define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
kadonotakashi 0:8fdf9a60065b 12564
kadonotakashi 0:8fdf9a60065b 12565 /*! @name ADMAES - ADMA Error Status register */
kadonotakashi 0:8fdf9a60065b 12566 #define SDHC_ADMAES_ADMAES_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 12567 #define SDHC_ADMAES_ADMAES_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12568 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
kadonotakashi 0:8fdf9a60065b 12569 #define SDHC_ADMAES_ADMALME_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 12570 #define SDHC_ADMAES_ADMALME_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12571 #define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
kadonotakashi 0:8fdf9a60065b 12572 #define SDHC_ADMAES_ADMADCE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12573 #define SDHC_ADMAES_ADMADCE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12574 #define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
kadonotakashi 0:8fdf9a60065b 12575
kadonotakashi 0:8fdf9a60065b 12576 /*! @name ADSADDR - ADMA System Addressregister */
kadonotakashi 0:8fdf9a60065b 12577 #define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
kadonotakashi 0:8fdf9a60065b 12578 #define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12579 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
kadonotakashi 0:8fdf9a60065b 12580
kadonotakashi 0:8fdf9a60065b 12581 /*! @name VENDOR - Vendor Specific register */
kadonotakashi 0:8fdf9a60065b 12582 #define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12583 #define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12584 #define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
kadonotakashi 0:8fdf9a60065b 12585 #define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 12586 #define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12587 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
kadonotakashi 0:8fdf9a60065b 12588
kadonotakashi 0:8fdf9a60065b 12589 /*! @name MMCBOOT - MMC Boot register */
kadonotakashi 0:8fdf9a60065b 12590 #define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 12591 #define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12592 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
kadonotakashi 0:8fdf9a60065b 12593 #define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12594 #define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12595 #define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
kadonotakashi 0:8fdf9a60065b 12596 #define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 12597 #define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 12598 #define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
kadonotakashi 0:8fdf9a60065b 12599 #define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 12600 #define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 12601 #define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
kadonotakashi 0:8fdf9a60065b 12602 #define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 12603 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 12604 #define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
kadonotakashi 0:8fdf9a60065b 12605 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 12606 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12607 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
kadonotakashi 0:8fdf9a60065b 12608
kadonotakashi 0:8fdf9a60065b 12609 /*! @name HOSTVER - Host Controller Version */
kadonotakashi 0:8fdf9a60065b 12610 #define SDHC_HOSTVER_SVN_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 12611 #define SDHC_HOSTVER_SVN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12612 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
kadonotakashi 0:8fdf9a60065b 12613 #define SDHC_HOSTVER_VVN_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 12614 #define SDHC_HOSTVER_VVN_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 12615 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
kadonotakashi 0:8fdf9a60065b 12616
kadonotakashi 0:8fdf9a60065b 12617
kadonotakashi 0:8fdf9a60065b 12618 /*!
kadonotakashi 0:8fdf9a60065b 12619 * @}
kadonotakashi 0:8fdf9a60065b 12620 */ /* end of group SDHC_Register_Masks */
kadonotakashi 0:8fdf9a60065b 12621
kadonotakashi 0:8fdf9a60065b 12622
kadonotakashi 0:8fdf9a60065b 12623 /* SDHC - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 12624 /** Peripheral SDHC base address */
kadonotakashi 0:8fdf9a60065b 12625 #define SDHC_BASE (0x400B1000u)
kadonotakashi 0:8fdf9a60065b 12626 /** Peripheral SDHC base pointer */
kadonotakashi 0:8fdf9a60065b 12627 #define SDHC ((SDHC_Type *)SDHC_BASE)
kadonotakashi 0:8fdf9a60065b 12628 /** Array initializer of SDHC peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 12629 #define SDHC_BASE_ADDRS { SDHC_BASE }
kadonotakashi 0:8fdf9a60065b 12630 /** Array initializer of SDHC peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 12631 #define SDHC_BASE_PTRS { SDHC }
kadonotakashi 0:8fdf9a60065b 12632 /** Interrupt vectors for the SDHC peripheral type */
kadonotakashi 0:8fdf9a60065b 12633 #define SDHC_IRQS { SDHC_IRQn }
kadonotakashi 0:8fdf9a60065b 12634
kadonotakashi 0:8fdf9a60065b 12635 /*!
kadonotakashi 0:8fdf9a60065b 12636 * @}
kadonotakashi 0:8fdf9a60065b 12637 */ /* end of group SDHC_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 12638
kadonotakashi 0:8fdf9a60065b 12639
kadonotakashi 0:8fdf9a60065b 12640 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 12641 -- SDRAM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 12642 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 12643
kadonotakashi 0:8fdf9a60065b 12644 /*!
kadonotakashi 0:8fdf9a60065b 12645 * @addtogroup SDRAM_Peripheral_Access_Layer SDRAM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 12646 * @{
kadonotakashi 0:8fdf9a60065b 12647 */
kadonotakashi 0:8fdf9a60065b 12648
kadonotakashi 0:8fdf9a60065b 12649 /** SDRAM - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 12650 typedef struct {
kadonotakashi 0:8fdf9a60065b 12651 uint8_t RESERVED_0[66];
kadonotakashi 0:8fdf9a60065b 12652 __IO uint16_t CTRL; /**< Control Register, offset: 0x42 */
kadonotakashi 0:8fdf9a60065b 12653 uint8_t RESERVED_1[4];
kadonotakashi 0:8fdf9a60065b 12654 struct { /* offset: 0x48, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 12655 __IO uint32_t AC; /**< Address and Control Register, array offset: 0x48, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 12656 __IO uint32_t CM; /**< Control Mask, array offset: 0x4C, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 12657 } BLOCK[2];
kadonotakashi 0:8fdf9a60065b 12658 } SDRAM_Type;
kadonotakashi 0:8fdf9a60065b 12659
kadonotakashi 0:8fdf9a60065b 12660 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 12661 -- SDRAM Register Masks
kadonotakashi 0:8fdf9a60065b 12662 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 12663
kadonotakashi 0:8fdf9a60065b 12664 /*!
kadonotakashi 0:8fdf9a60065b 12665 * @addtogroup SDRAM_Register_Masks SDRAM Register Masks
kadonotakashi 0:8fdf9a60065b 12666 * @{
kadonotakashi 0:8fdf9a60065b 12667 */
kadonotakashi 0:8fdf9a60065b 12668
kadonotakashi 0:8fdf9a60065b 12669 /*! @name CTRL - Control Register */
kadonotakashi 0:8fdf9a60065b 12670 #define SDRAM_CTRL_RC_MASK (0x1FFU)
kadonotakashi 0:8fdf9a60065b 12671 #define SDRAM_CTRL_RC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12672 #define SDRAM_CTRL_RC(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)
kadonotakashi 0:8fdf9a60065b 12673 #define SDRAM_CTRL_RTIM_MASK (0x600U)
kadonotakashi 0:8fdf9a60065b 12674 #define SDRAM_CTRL_RTIM_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 12675 #define SDRAM_CTRL_RTIM(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)
kadonotakashi 0:8fdf9a60065b 12676 #define SDRAM_CTRL_IS_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 12677 #define SDRAM_CTRL_IS_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 12678 #define SDRAM_CTRL_IS(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)
kadonotakashi 0:8fdf9a60065b 12679
kadonotakashi 0:8fdf9a60065b 12680 /*! @name AC - Address and Control Register */
kadonotakashi 0:8fdf9a60065b 12681 #define SDRAM_AC_IP_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12682 #define SDRAM_AC_IP_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12683 #define SDRAM_AC_IP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)
kadonotakashi 0:8fdf9a60065b 12684 #define SDRAM_AC_PS_MASK (0x30U)
kadonotakashi 0:8fdf9a60065b 12685 #define SDRAM_AC_PS_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12686 #define SDRAM_AC_PS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)
kadonotakashi 0:8fdf9a60065b 12687 #define SDRAM_AC_IMRS_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 12688 #define SDRAM_AC_IMRS_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 12689 #define SDRAM_AC_IMRS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)
kadonotakashi 0:8fdf9a60065b 12690 #define SDRAM_AC_CBM_MASK (0x700U)
kadonotakashi 0:8fdf9a60065b 12691 #define SDRAM_AC_CBM_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 12692 #define SDRAM_AC_CBM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)
kadonotakashi 0:8fdf9a60065b 12693 #define SDRAM_AC_CASL_MASK (0x3000U)
kadonotakashi 0:8fdf9a60065b 12694 #define SDRAM_AC_CASL_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 12695 #define SDRAM_AC_CASL(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)
kadonotakashi 0:8fdf9a60065b 12696 #define SDRAM_AC_RE_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 12697 #define SDRAM_AC_RE_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 12698 #define SDRAM_AC_RE(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)
kadonotakashi 0:8fdf9a60065b 12699 #define SDRAM_AC_BA_MASK (0xFFFC0000U)
kadonotakashi 0:8fdf9a60065b 12700 #define SDRAM_AC_BA_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12701 #define SDRAM_AC_BA(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)
kadonotakashi 0:8fdf9a60065b 12702
kadonotakashi 0:8fdf9a60065b 12703 /* The count of SDRAM_AC */
kadonotakashi 0:8fdf9a60065b 12704 #define SDRAM_AC_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 12705
kadonotakashi 0:8fdf9a60065b 12706 /*! @name CM - Control Mask */
kadonotakashi 0:8fdf9a60065b 12707 #define SDRAM_CM_V_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12708 #define SDRAM_CM_V_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12709 #define SDRAM_CM_V(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)
kadonotakashi 0:8fdf9a60065b 12710 #define SDRAM_CM_WP_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 12711 #define SDRAM_CM_WP_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 12712 #define SDRAM_CM_WP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)
kadonotakashi 0:8fdf9a60065b 12713 #define SDRAM_CM_BAM_MASK (0xFFFC0000U)
kadonotakashi 0:8fdf9a60065b 12714 #define SDRAM_CM_BAM_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12715 #define SDRAM_CM_BAM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)
kadonotakashi 0:8fdf9a60065b 12716
kadonotakashi 0:8fdf9a60065b 12717 /* The count of SDRAM_CM */
kadonotakashi 0:8fdf9a60065b 12718 #define SDRAM_CM_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 12719
kadonotakashi 0:8fdf9a60065b 12720
kadonotakashi 0:8fdf9a60065b 12721 /*!
kadonotakashi 0:8fdf9a60065b 12722 * @}
kadonotakashi 0:8fdf9a60065b 12723 */ /* end of group SDRAM_Register_Masks */
kadonotakashi 0:8fdf9a60065b 12724
kadonotakashi 0:8fdf9a60065b 12725
kadonotakashi 0:8fdf9a60065b 12726 /* SDRAM - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 12727 /** Peripheral SDRAM base address */
kadonotakashi 0:8fdf9a60065b 12728 #define SDRAM_BASE (0x4000F000u)
kadonotakashi 0:8fdf9a60065b 12729 /** Peripheral SDRAM base pointer */
kadonotakashi 0:8fdf9a60065b 12730 #define SDRAM ((SDRAM_Type *)SDRAM_BASE)
kadonotakashi 0:8fdf9a60065b 12731 /** Array initializer of SDRAM peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 12732 #define SDRAM_BASE_ADDRS { SDRAM_BASE }
kadonotakashi 0:8fdf9a60065b 12733 /** Array initializer of SDRAM peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 12734 #define SDRAM_BASE_PTRS { SDRAM }
kadonotakashi 0:8fdf9a60065b 12735
kadonotakashi 0:8fdf9a60065b 12736 /*!
kadonotakashi 0:8fdf9a60065b 12737 * @}
kadonotakashi 0:8fdf9a60065b 12738 */ /* end of group SDRAM_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 12739
kadonotakashi 0:8fdf9a60065b 12740
kadonotakashi 0:8fdf9a60065b 12741 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 12742 -- SIM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 12743 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 12744
kadonotakashi 0:8fdf9a60065b 12745 /*!
kadonotakashi 0:8fdf9a60065b 12746 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 12747 * @{
kadonotakashi 0:8fdf9a60065b 12748 */
kadonotakashi 0:8fdf9a60065b 12749
kadonotakashi 0:8fdf9a60065b 12750 /** SIM - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 12751 typedef struct {
kadonotakashi 0:8fdf9a60065b 12752 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 12753 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 12754 uint8_t RESERVED_0[4092];
kadonotakashi 0:8fdf9a60065b 12755 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
kadonotakashi 0:8fdf9a60065b 12756 uint8_t RESERVED_1[4];
kadonotakashi 0:8fdf9a60065b 12757 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
kadonotakashi 0:8fdf9a60065b 12758 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
kadonotakashi 0:8fdf9a60065b 12759 uint8_t RESERVED_2[4];
kadonotakashi 0:8fdf9a60065b 12760 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
kadonotakashi 0:8fdf9a60065b 12761 __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
kadonotakashi 0:8fdf9a60065b 12762 __IO uint32_t SOPT9; /**< System Options Register 9, offset: 0x1020 */
kadonotakashi 0:8fdf9a60065b 12763 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
kadonotakashi 0:8fdf9a60065b 12764 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
kadonotakashi 0:8fdf9a60065b 12765 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
kadonotakashi 0:8fdf9a60065b 12766 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
kadonotakashi 0:8fdf9a60065b 12767 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
kadonotakashi 0:8fdf9a60065b 12768 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
kadonotakashi 0:8fdf9a60065b 12769 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
kadonotakashi 0:8fdf9a60065b 12770 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
kadonotakashi 0:8fdf9a60065b 12771 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
kadonotakashi 0:8fdf9a60065b 12772 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
kadonotakashi 0:8fdf9a60065b 12773 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
kadonotakashi 0:8fdf9a60065b 12774 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
kadonotakashi 0:8fdf9a60065b 12775 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
kadonotakashi 0:8fdf9a60065b 12776 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
kadonotakashi 0:8fdf9a60065b 12777 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
kadonotakashi 0:8fdf9a60065b 12778 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
kadonotakashi 0:8fdf9a60065b 12779 __IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1064 */
kadonotakashi 0:8fdf9a60065b 12780 __IO uint32_t CLKDIV4; /**< System Clock Divider Register 4, offset: 0x1068 */
kadonotakashi 0:8fdf9a60065b 12781 } SIM_Type;
kadonotakashi 0:8fdf9a60065b 12782
kadonotakashi 0:8fdf9a60065b 12783 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 12784 -- SIM Register Masks
kadonotakashi 0:8fdf9a60065b 12785 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 12786
kadonotakashi 0:8fdf9a60065b 12787 /*!
kadonotakashi 0:8fdf9a60065b 12788 * @addtogroup SIM_Register_Masks SIM Register Masks
kadonotakashi 0:8fdf9a60065b 12789 * @{
kadonotakashi 0:8fdf9a60065b 12790 */
kadonotakashi 0:8fdf9a60065b 12791
kadonotakashi 0:8fdf9a60065b 12792 /*! @name SOPT1 - System Options Register 1 */
kadonotakashi 0:8fdf9a60065b 12793 #define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
kadonotakashi 0:8fdf9a60065b 12794 #define SIM_SOPT1_RAMSIZE_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 12795 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
kadonotakashi 0:8fdf9a60065b 12796 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
kadonotakashi 0:8fdf9a60065b 12797 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12798 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12799 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 12800 #define SIM_SOPT1_USBVSTBY_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 12801 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
kadonotakashi 0:8fdf9a60065b 12802 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 12803 #define SIM_SOPT1_USBSSTBY_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 12804 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
kadonotakashi 0:8fdf9a60065b 12805 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 12806 #define SIM_SOPT1_USBREGEN_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 12807 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
kadonotakashi 0:8fdf9a60065b 12808
kadonotakashi 0:8fdf9a60065b 12809 /*! @name SOPT1CFG - SOPT1 Configuration Register */
kadonotakashi 0:8fdf9a60065b 12810 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 12811 #define SIM_SOPT1CFG_URWE_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12812 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
kadonotakashi 0:8fdf9a60065b 12813 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 12814 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 12815 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
kadonotakashi 0:8fdf9a60065b 12816 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 12817 #define SIM_SOPT1CFG_USSWE_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 12818 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
kadonotakashi 0:8fdf9a60065b 12819
kadonotakashi 0:8fdf9a60065b 12820 /*! @name SOPT2 - System Options Register 2 */
kadonotakashi 0:8fdf9a60065b 12821 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12822 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12823 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12824 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
kadonotakashi 0:8fdf9a60065b 12825 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 12826 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12827 #define SIM_SOPT2_FBSL_MASK (0x300U)
kadonotakashi 0:8fdf9a60065b 12828 #define SIM_SOPT2_FBSL_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 12829 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
kadonotakashi 0:8fdf9a60065b 12830 #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 12831 #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 12832 #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12833 #define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 12834 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12835 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12836 #define SIM_SOPT2_USBSRC_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 12837 #define SIM_SOPT2_USBSRC_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12838 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
kadonotakashi 0:8fdf9a60065b 12839 #define SIM_SOPT2_FLEXIOSRC_MASK (0xC00000U)
kadonotakashi 0:8fdf9a60065b 12840 #define SIM_SOPT2_FLEXIOSRC_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 12841 #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FLEXIOSRC_SHIFT)) & SIM_SOPT2_FLEXIOSRC_MASK)
kadonotakashi 0:8fdf9a60065b 12842 #define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
kadonotakashi 0:8fdf9a60065b 12843 #define SIM_SOPT2_TPMSRC_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12844 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
kadonotakashi 0:8fdf9a60065b 12845 #define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U)
kadonotakashi 0:8fdf9a60065b 12846 #define SIM_SOPT2_LPUARTSRC_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 12847 #define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
kadonotakashi 0:8fdf9a60065b 12848 #define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
kadonotakashi 0:8fdf9a60065b 12849 #define SIM_SOPT2_SDHCSRC_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 12850 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
kadonotakashi 0:8fdf9a60065b 12851 #define SIM_SOPT2_EMVSIMSRC_MASK (0xC0000000U)
kadonotakashi 0:8fdf9a60065b 12852 #define SIM_SOPT2_EMVSIMSRC_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 12853 #define SIM_SOPT2_EMVSIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_EMVSIMSRC_SHIFT)) & SIM_SOPT2_EMVSIMSRC_MASK)
kadonotakashi 0:8fdf9a60065b 12854
kadonotakashi 0:8fdf9a60065b 12855 /*! @name SOPT4 - System Options Register 4 */
kadonotakashi 0:8fdf9a60065b 12856 #define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12857 #define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12858 #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
kadonotakashi 0:8fdf9a60065b 12859 #define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12860 #define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12861 #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
kadonotakashi 0:8fdf9a60065b 12862 #define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12863 #define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12864 #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
kadonotakashi 0:8fdf9a60065b 12865 #define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 12866 #define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 12867 #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
kadonotakashi 0:8fdf9a60065b 12868 #define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 12869 #define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 12870 #define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
kadonotakashi 0:8fdf9a60065b 12871 #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
kadonotakashi 0:8fdf9a60065b 12872 #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12873 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12874 #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
kadonotakashi 0:8fdf9a60065b 12875 #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 12876 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12877 #define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 12878 #define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 12879 #define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12880 #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 12881 #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12882 #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12883 #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 12884 #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 12885 #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12886 #define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 12887 #define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 12888 #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12889 #define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 12890 #define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 12891 #define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12892 #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 12893 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 12894 #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12895 #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 12896 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 12897 #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12898 #define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 12899 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 12900 #define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12901 #define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 12902 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 12903 #define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12904
kadonotakashi 0:8fdf9a60065b 12905 /*! @name SOPT5 - System Options Register 5 */
kadonotakashi 0:8fdf9a60065b 12906 #define SIM_SOPT5_LPUART0TXSRC_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 12907 #define SIM_SOPT5_LPUART0TXSRC_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12908 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
kadonotakashi 0:8fdf9a60065b 12909 #define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U)
kadonotakashi 0:8fdf9a60065b 12910 #define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12911 #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
kadonotakashi 0:8fdf9a60065b 12912 #define SIM_SOPT5_LPUART1TXSRC_MASK (0x300000U)
kadonotakashi 0:8fdf9a60065b 12913 #define SIM_SOPT5_LPUART1TXSRC_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 12914 #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1TXSRC_SHIFT)) & SIM_SOPT5_LPUART1TXSRC_MASK)
kadonotakashi 0:8fdf9a60065b 12915 #define SIM_SOPT5_LPUART1RXSRC_MASK (0xC00000U)
kadonotakashi 0:8fdf9a60065b 12916 #define SIM_SOPT5_LPUART1RXSRC_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 12917 #define SIM_SOPT5_LPUART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1RXSRC_SHIFT)) & SIM_SOPT5_LPUART1RXSRC_MASK)
kadonotakashi 0:8fdf9a60065b 12918
kadonotakashi 0:8fdf9a60065b 12919 /*! @name SOPT7 - System Options Register 7 */
kadonotakashi 0:8fdf9a60065b 12920 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 12921 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12922 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12923 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 12924 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 12925 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
kadonotakashi 0:8fdf9a60065b 12926 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 12927 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 12928 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
kadonotakashi 0:8fdf9a60065b 12929
kadonotakashi 0:8fdf9a60065b 12930 /*! @name SOPT8 - System Options Register 8 */
kadonotakashi 0:8fdf9a60065b 12931 #define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 12932 #define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 12933 #define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
kadonotakashi 0:8fdf9a60065b 12934 #define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 12935 #define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 12936 #define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
kadonotakashi 0:8fdf9a60065b 12937 #define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 12938 #define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 12939 #define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
kadonotakashi 0:8fdf9a60065b 12940 #define SIM_SOPT8_FTM3SYNCBIT_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 12941 #define SIM_SOPT8_FTM3SYNCBIT_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 12942 #define SIM_SOPT8_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
kadonotakashi 0:8fdf9a60065b 12943 #define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 12944 #define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 12945 #define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12946 #define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 12947 #define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 12948 #define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12949 #define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 12950 #define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12951 #define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12952 #define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 12953 #define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 12954 #define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12955 #define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 12956 #define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 12957 #define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12958 #define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 12959 #define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 12960 #define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12961 #define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 12962 #define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 12963 #define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12964 #define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 12965 #define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 12966 #define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12967 #define SIM_SOPT8_FTM3OCH0SRC_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 12968 #define SIM_SOPT8_FTM3OCH0SRC_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 12969 #define SIM_SOPT8_FTM3OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12970 #define SIM_SOPT8_FTM3OCH1SRC_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 12971 #define SIM_SOPT8_FTM3OCH1SRC_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 12972 #define SIM_SOPT8_FTM3OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12973 #define SIM_SOPT8_FTM3OCH2SRC_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 12974 #define SIM_SOPT8_FTM3OCH2SRC_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 12975 #define SIM_SOPT8_FTM3OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12976 #define SIM_SOPT8_FTM3OCH3SRC_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 12977 #define SIM_SOPT8_FTM3OCH3SRC_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 12978 #define SIM_SOPT8_FTM3OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12979 #define SIM_SOPT8_FTM3OCH4SRC_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 12980 #define SIM_SOPT8_FTM3OCH4SRC_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 12981 #define SIM_SOPT8_FTM3OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12982 #define SIM_SOPT8_FTM3OCH5SRC_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 12983 #define SIM_SOPT8_FTM3OCH5SRC_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 12984 #define SIM_SOPT8_FTM3OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12985 #define SIM_SOPT8_FTM3OCH6SRC_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 12986 #define SIM_SOPT8_FTM3OCH6SRC_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 12987 #define SIM_SOPT8_FTM3OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12988 #define SIM_SOPT8_FTM3OCH7SRC_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 12989 #define SIM_SOPT8_FTM3OCH7SRC_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 12990 #define SIM_SOPT8_FTM3OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12991
kadonotakashi 0:8fdf9a60065b 12992 /*! @name SOPT9 - System Options Register 9 */
kadonotakashi 0:8fdf9a60065b 12993 #define SIM_SOPT9_TPM1CH0SRC_MASK (0xC0000U)
kadonotakashi 0:8fdf9a60065b 12994 #define SIM_SOPT9_TPM1CH0SRC_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 12995 #define SIM_SOPT9_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12996 #define SIM_SOPT9_TPM2CH0SRC_MASK (0x300000U)
kadonotakashi 0:8fdf9a60065b 12997 #define SIM_SOPT9_TPM2CH0SRC_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 12998 #define SIM_SOPT9_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
kadonotakashi 0:8fdf9a60065b 12999 #define SIM_SOPT9_TPM1CLKSEL_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 13000 #define SIM_SOPT9_TPM1CLKSEL_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 13001 #define SIM_SOPT9_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
kadonotakashi 0:8fdf9a60065b 13002 #define SIM_SOPT9_TPM2CLKSEL_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 13003 #define SIM_SOPT9_TPM2CLKSEL_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 13004 #define SIM_SOPT9_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
kadonotakashi 0:8fdf9a60065b 13005
kadonotakashi 0:8fdf9a60065b 13006 /*! @name SDID - System Device Identification Register */
kadonotakashi 0:8fdf9a60065b 13007 #define SIM_SDID_PINID_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 13008 #define SIM_SDID_PINID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13009 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
kadonotakashi 0:8fdf9a60065b 13010 #define SIM_SDID_FAMID_MASK (0x70U)
kadonotakashi 0:8fdf9a60065b 13011 #define SIM_SDID_FAMID_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 13012 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
kadonotakashi 0:8fdf9a60065b 13013 #define SIM_SDID_DIEID_MASK (0xF80U)
kadonotakashi 0:8fdf9a60065b 13014 #define SIM_SDID_DIEID_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 13015 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
kadonotakashi 0:8fdf9a60065b 13016 #define SIM_SDID_REVID_MASK (0xF000U)
kadonotakashi 0:8fdf9a60065b 13017 #define SIM_SDID_REVID_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 13018 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
kadonotakashi 0:8fdf9a60065b 13019 #define SIM_SDID_SERIESID_MASK (0xF00000U)
kadonotakashi 0:8fdf9a60065b 13020 #define SIM_SDID_SERIESID_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 13021 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
kadonotakashi 0:8fdf9a60065b 13022 #define SIM_SDID_SUBFAMID_MASK (0xF000000U)
kadonotakashi 0:8fdf9a60065b 13023 #define SIM_SDID_SUBFAMID_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 13024 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
kadonotakashi 0:8fdf9a60065b 13025 #define SIM_SDID_FAMILYID_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 13026 #define SIM_SDID_FAMILYID_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 13027 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
kadonotakashi 0:8fdf9a60065b 13028
kadonotakashi 0:8fdf9a60065b 13029 /*! @name SCGC1 - System Clock Gating Control Register 1 */
kadonotakashi 0:8fdf9a60065b 13030 #define SIM_SCGC1_I2C2_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 13031 #define SIM_SCGC1_I2C2_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 13032 #define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
kadonotakashi 0:8fdf9a60065b 13033 #define SIM_SCGC1_I2C3_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 13034 #define SIM_SCGC1_I2C3_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 13035 #define SIM_SCGC1_I2C3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
kadonotakashi 0:8fdf9a60065b 13036
kadonotakashi 0:8fdf9a60065b 13037 /*! @name SCGC2 - System Clock Gating Control Register 2 */
kadonotakashi 0:8fdf9a60065b 13038 #define SIM_SCGC2_LPUART0_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 13039 #define SIM_SCGC2_LPUART0_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 13040 #define SIM_SCGC2_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
kadonotakashi 0:8fdf9a60065b 13041 #define SIM_SCGC2_LPUART1_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 13042 #define SIM_SCGC2_LPUART1_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 13043 #define SIM_SCGC2_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART1_SHIFT)) & SIM_SCGC2_LPUART1_MASK)
kadonotakashi 0:8fdf9a60065b 13044 #define SIM_SCGC2_LPUART2_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 13045 #define SIM_SCGC2_LPUART2_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 13046 #define SIM_SCGC2_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART2_SHIFT)) & SIM_SCGC2_LPUART2_MASK)
kadonotakashi 0:8fdf9a60065b 13047 #define SIM_SCGC2_LPUART3_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 13048 #define SIM_SCGC2_LPUART3_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 13049 #define SIM_SCGC2_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART3_SHIFT)) & SIM_SCGC2_LPUART3_MASK)
kadonotakashi 0:8fdf9a60065b 13050 #define SIM_SCGC2_TPM1_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 13051 #define SIM_SCGC2_TPM1_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 13052 #define SIM_SCGC2_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
kadonotakashi 0:8fdf9a60065b 13053 #define SIM_SCGC2_TPM2_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 13054 #define SIM_SCGC2_TPM2_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 13055 #define SIM_SCGC2_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
kadonotakashi 0:8fdf9a60065b 13056 #define SIM_SCGC2_DAC0_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 13057 #define SIM_SCGC2_DAC0_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 13058 #define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
kadonotakashi 0:8fdf9a60065b 13059 #define SIM_SCGC2_LTC_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 13060 #define SIM_SCGC2_LTC_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 13061 #define SIM_SCGC2_LTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LTC_SHIFT)) & SIM_SCGC2_LTC_MASK)
kadonotakashi 0:8fdf9a60065b 13062 #define SIM_SCGC2_EMVSIM0_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 13063 #define SIM_SCGC2_EMVSIM0_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 13064 #define SIM_SCGC2_EMVSIM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_EMVSIM0_SHIFT)) & SIM_SCGC2_EMVSIM0_MASK)
kadonotakashi 0:8fdf9a60065b 13065 #define SIM_SCGC2_EMVSIM1_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 13066 #define SIM_SCGC2_EMVSIM1_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 13067 #define SIM_SCGC2_EMVSIM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_EMVSIM1_SHIFT)) & SIM_SCGC2_EMVSIM1_MASK)
kadonotakashi 0:8fdf9a60065b 13068 #define SIM_SCGC2_LPUART4_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 13069 #define SIM_SCGC2_LPUART4_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 13070 #define SIM_SCGC2_LPUART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART4_SHIFT)) & SIM_SCGC2_LPUART4_MASK)
kadonotakashi 0:8fdf9a60065b 13071 #define SIM_SCGC2_QSPI_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 13072 #define SIM_SCGC2_QSPI_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 13073 #define SIM_SCGC2_QSPI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_QSPI_SHIFT)) & SIM_SCGC2_QSPI_MASK)
kadonotakashi 0:8fdf9a60065b 13074 #define SIM_SCGC2_FLEXIO_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 13075 #define SIM_SCGC2_FLEXIO_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 13076 #define SIM_SCGC2_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_FLEXIO_SHIFT)) & SIM_SCGC2_FLEXIO_MASK)
kadonotakashi 0:8fdf9a60065b 13077
kadonotakashi 0:8fdf9a60065b 13078 /*! @name SCGC3 - System Clock Gating Control Register 3 */
kadonotakashi 0:8fdf9a60065b 13079 #define SIM_SCGC3_TRNG_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13080 #define SIM_SCGC3_TRNG_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13081 #define SIM_SCGC3_TRNG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_TRNG_SHIFT)) & SIM_SCGC3_TRNG_MASK)
kadonotakashi 0:8fdf9a60065b 13082 #define SIM_SCGC3_SPI2_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 13083 #define SIM_SCGC3_SPI2_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 13084 #define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
kadonotakashi 0:8fdf9a60065b 13085 #define SIM_SCGC3_SDHC_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 13086 #define SIM_SCGC3_SDHC_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 13087 #define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
kadonotakashi 0:8fdf9a60065b 13088 #define SIM_SCGC3_FTM2_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 13089 #define SIM_SCGC3_FTM2_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 13090 #define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
kadonotakashi 0:8fdf9a60065b 13091 #define SIM_SCGC3_FTM3_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 13092 #define SIM_SCGC3_FTM3_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 13093 #define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
kadonotakashi 0:8fdf9a60065b 13094
kadonotakashi 0:8fdf9a60065b 13095 /*! @name SCGC4 - System Clock Gating Control Register 4 */
kadonotakashi 0:8fdf9a60065b 13096 #define SIM_SCGC4_EWM_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 13097 #define SIM_SCGC4_EWM_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13098 #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
kadonotakashi 0:8fdf9a60065b 13099 #define SIM_SCGC4_CMT_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 13100 #define SIM_SCGC4_CMT_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 13101 #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
kadonotakashi 0:8fdf9a60065b 13102 #define SIM_SCGC4_I2C0_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 13103 #define SIM_SCGC4_I2C0_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 13104 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
kadonotakashi 0:8fdf9a60065b 13105 #define SIM_SCGC4_I2C1_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 13106 #define SIM_SCGC4_I2C1_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 13107 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
kadonotakashi 0:8fdf9a60065b 13108 #define SIM_SCGC4_USBOTG_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 13109 #define SIM_SCGC4_USBOTG_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 13110 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
kadonotakashi 0:8fdf9a60065b 13111 #define SIM_SCGC4_CMP_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 13112 #define SIM_SCGC4_CMP_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 13113 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
kadonotakashi 0:8fdf9a60065b 13114 #define SIM_SCGC4_VREF_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 13115 #define SIM_SCGC4_VREF_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 13116 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
kadonotakashi 0:8fdf9a60065b 13117
kadonotakashi 0:8fdf9a60065b 13118 /*! @name SCGC5 - System Clock Gating Control Register 5 */
kadonotakashi 0:8fdf9a60065b 13119 #define SIM_SCGC5_LPTMR_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13120 #define SIM_SCGC5_LPTMR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13121 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
kadonotakashi 0:8fdf9a60065b 13122 #define SIM_SCGC5_LPTMR1_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 13123 #define SIM_SCGC5_LPTMR1_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 13124 #define SIM_SCGC5_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR1_SHIFT)) & SIM_SCGC5_LPTMR1_MASK)
kadonotakashi 0:8fdf9a60065b 13125 #define SIM_SCGC5_TSI_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 13126 #define SIM_SCGC5_TSI_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 13127 #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
kadonotakashi 0:8fdf9a60065b 13128 #define SIM_SCGC5_PORTA_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 13129 #define SIM_SCGC5_PORTA_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 13130 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
kadonotakashi 0:8fdf9a60065b 13131 #define SIM_SCGC5_PORTB_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 13132 #define SIM_SCGC5_PORTB_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 13133 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
kadonotakashi 0:8fdf9a60065b 13134 #define SIM_SCGC5_PORTC_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 13135 #define SIM_SCGC5_PORTC_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 13136 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
kadonotakashi 0:8fdf9a60065b 13137 #define SIM_SCGC5_PORTD_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 13138 #define SIM_SCGC5_PORTD_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 13139 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
kadonotakashi 0:8fdf9a60065b 13140 #define SIM_SCGC5_PORTE_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 13141 #define SIM_SCGC5_PORTE_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 13142 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
kadonotakashi 0:8fdf9a60065b 13143
kadonotakashi 0:8fdf9a60065b 13144 /*! @name SCGC6 - System Clock Gating Control Register 6 */
kadonotakashi 0:8fdf9a60065b 13145 #define SIM_SCGC6_FTF_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13146 #define SIM_SCGC6_FTF_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13147 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
kadonotakashi 0:8fdf9a60065b 13148 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 13149 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13150 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
kadonotakashi 0:8fdf9a60065b 13151 #define SIM_SCGC6_SPI0_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 13152 #define SIM_SCGC6_SPI0_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 13153 #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
kadonotakashi 0:8fdf9a60065b 13154 #define SIM_SCGC6_SPI1_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 13155 #define SIM_SCGC6_SPI1_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 13156 #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
kadonotakashi 0:8fdf9a60065b 13157 #define SIM_SCGC6_I2S_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 13158 #define SIM_SCGC6_I2S_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 13159 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
kadonotakashi 0:8fdf9a60065b 13160 #define SIM_SCGC6_CRC_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 13161 #define SIM_SCGC6_CRC_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 13162 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
kadonotakashi 0:8fdf9a60065b 13163 #define SIM_SCGC6_USBDCD_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 13164 #define SIM_SCGC6_USBDCD_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 13165 #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
kadonotakashi 0:8fdf9a60065b 13166 #define SIM_SCGC6_PDB_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 13167 #define SIM_SCGC6_PDB_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 13168 #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
kadonotakashi 0:8fdf9a60065b 13169 #define SIM_SCGC6_PIT_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 13170 #define SIM_SCGC6_PIT_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 13171 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
kadonotakashi 0:8fdf9a60065b 13172 #define SIM_SCGC6_FTM0_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 13173 #define SIM_SCGC6_FTM0_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 13174 #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
kadonotakashi 0:8fdf9a60065b 13175 #define SIM_SCGC6_FTM1_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 13176 #define SIM_SCGC6_FTM1_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 13177 #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
kadonotakashi 0:8fdf9a60065b 13178 #define SIM_SCGC6_FTM2_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 13179 #define SIM_SCGC6_FTM2_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 13180 #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
kadonotakashi 0:8fdf9a60065b 13181 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 13182 #define SIM_SCGC6_ADC0_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 13183 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
kadonotakashi 0:8fdf9a60065b 13184 #define SIM_SCGC6_RTC_MASK (0x20000000U)
kadonotakashi 0:8fdf9a60065b 13185 #define SIM_SCGC6_RTC_SHIFT (29U)
kadonotakashi 0:8fdf9a60065b 13186 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
kadonotakashi 0:8fdf9a60065b 13187 #define SIM_SCGC6_DAC0_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 13188 #define SIM_SCGC6_DAC0_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 13189 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
kadonotakashi 0:8fdf9a60065b 13190
kadonotakashi 0:8fdf9a60065b 13191 /*! @name SCGC7 - System Clock Gating Control Register 7 */
kadonotakashi 0:8fdf9a60065b 13192 #define SIM_SCGC7_FLEXBUS_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13193 #define SIM_SCGC7_FLEXBUS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13194 #define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
kadonotakashi 0:8fdf9a60065b 13195 #define SIM_SCGC7_DMA_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 13196 #define SIM_SCGC7_DMA_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13197 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
kadonotakashi 0:8fdf9a60065b 13198 #define SIM_SCGC7_MPU_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 13199 #define SIM_SCGC7_MPU_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 13200 #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
kadonotakashi 0:8fdf9a60065b 13201 #define SIM_SCGC7_SDRAMC_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 13202 #define SIM_SCGC7_SDRAMC_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 13203 #define SIM_SCGC7_SDRAMC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
kadonotakashi 0:8fdf9a60065b 13204
kadonotakashi 0:8fdf9a60065b 13205 /*! @name CLKDIV1 - System Clock Divider Register 1 */
kadonotakashi 0:8fdf9a60065b 13206 #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 13207 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13208 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
kadonotakashi 0:8fdf9a60065b 13209 #define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
kadonotakashi 0:8fdf9a60065b 13210 #define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 13211 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
kadonotakashi 0:8fdf9a60065b 13212 #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
kadonotakashi 0:8fdf9a60065b 13213 #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 13214 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
kadonotakashi 0:8fdf9a60065b 13215 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 13216 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 13217 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
kadonotakashi 0:8fdf9a60065b 13218
kadonotakashi 0:8fdf9a60065b 13219 /*! @name CLKDIV2 - System Clock Divider Register 2 */
kadonotakashi 0:8fdf9a60065b 13220 #define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13221 #define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13222 #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
kadonotakashi 0:8fdf9a60065b 13223 #define SIM_CLKDIV2_USBDIV_MASK (0xEU)
kadonotakashi 0:8fdf9a60065b 13224 #define SIM_CLKDIV2_USBDIV_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13225 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
kadonotakashi 0:8fdf9a60065b 13226
kadonotakashi 0:8fdf9a60065b 13227 /*! @name FCFG1 - Flash Configuration Register 1 */
kadonotakashi 0:8fdf9a60065b 13228 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13229 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13230 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
kadonotakashi 0:8fdf9a60065b 13231 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 13232 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13233 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
kadonotakashi 0:8fdf9a60065b 13234 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
kadonotakashi 0:8fdf9a60065b 13235 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 13236 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
kadonotakashi 0:8fdf9a60065b 13237
kadonotakashi 0:8fdf9a60065b 13238 /*! @name FCFG2 - Flash Configuration Register 2 */
kadonotakashi 0:8fdf9a60065b 13239 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
kadonotakashi 0:8fdf9a60065b 13240 #define SIM_FCFG2_MAXADDR1_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13241 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
kadonotakashi 0:8fdf9a60065b 13242 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
kadonotakashi 0:8fdf9a60065b 13243 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 13244 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
kadonotakashi 0:8fdf9a60065b 13245
kadonotakashi 0:8fdf9a60065b 13246 /*! @name UIDH - Unique Identification Register High */
kadonotakashi 0:8fdf9a60065b 13247 #define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 13248 #define SIM_UIDH_UID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13249 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
kadonotakashi 0:8fdf9a60065b 13250
kadonotakashi 0:8fdf9a60065b 13251 /*! @name UIDMH - Unique Identification Register Mid-High */
kadonotakashi 0:8fdf9a60065b 13252 #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 13253 #define SIM_UIDMH_UID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13254 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
kadonotakashi 0:8fdf9a60065b 13255
kadonotakashi 0:8fdf9a60065b 13256 /*! @name UIDML - Unique Identification Register Mid Low */
kadonotakashi 0:8fdf9a60065b 13257 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 13258 #define SIM_UIDML_UID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13259 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
kadonotakashi 0:8fdf9a60065b 13260
kadonotakashi 0:8fdf9a60065b 13261 /*! @name UIDL - Unique Identification Register Low */
kadonotakashi 0:8fdf9a60065b 13262 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 13263 #define SIM_UIDL_UID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13264 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
kadonotakashi 0:8fdf9a60065b 13265
kadonotakashi 0:8fdf9a60065b 13266 /*! @name CLKDIV3 - System Clock Divider Register 3 */
kadonotakashi 0:8fdf9a60065b 13267 #define SIM_CLKDIV3_PLLFLLFRAC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13268 #define SIM_CLKDIV3_PLLFLLFRAC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13269 #define SIM_CLKDIV3_PLLFLLFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
kadonotakashi 0:8fdf9a60065b 13270 #define SIM_CLKDIV3_PLLFLLDIV_MASK (0xEU)
kadonotakashi 0:8fdf9a60065b 13271 #define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13272 #define SIM_CLKDIV3_PLLFLLDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
kadonotakashi 0:8fdf9a60065b 13273
kadonotakashi 0:8fdf9a60065b 13274 /*! @name CLKDIV4 - System Clock Divider Register 4 */
kadonotakashi 0:8fdf9a60065b 13275 #define SIM_CLKDIV4_TRACEFRAC_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13276 #define SIM_CLKDIV4_TRACEFRAC_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13277 #define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
kadonotakashi 0:8fdf9a60065b 13278 #define SIM_CLKDIV4_TRACEDIV_MASK (0xEU)
kadonotakashi 0:8fdf9a60065b 13279 #define SIM_CLKDIV4_TRACEDIV_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13280 #define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
kadonotakashi 0:8fdf9a60065b 13281
kadonotakashi 0:8fdf9a60065b 13282
kadonotakashi 0:8fdf9a60065b 13283 /*!
kadonotakashi 0:8fdf9a60065b 13284 * @}
kadonotakashi 0:8fdf9a60065b 13285 */ /* end of group SIM_Register_Masks */
kadonotakashi 0:8fdf9a60065b 13286
kadonotakashi 0:8fdf9a60065b 13287
kadonotakashi 0:8fdf9a60065b 13288 /* SIM - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 13289 /** Peripheral SIM base address */
kadonotakashi 0:8fdf9a60065b 13290 #define SIM_BASE (0x40047000u)
kadonotakashi 0:8fdf9a60065b 13291 /** Peripheral SIM base pointer */
kadonotakashi 0:8fdf9a60065b 13292 #define SIM ((SIM_Type *)SIM_BASE)
kadonotakashi 0:8fdf9a60065b 13293 /** Array initializer of SIM peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 13294 #define SIM_BASE_ADDRS { SIM_BASE }
kadonotakashi 0:8fdf9a60065b 13295 /** Array initializer of SIM peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 13296 #define SIM_BASE_PTRS { SIM }
kadonotakashi 0:8fdf9a60065b 13297
kadonotakashi 0:8fdf9a60065b 13298 /*!
kadonotakashi 0:8fdf9a60065b 13299 * @}
kadonotakashi 0:8fdf9a60065b 13300 */ /* end of group SIM_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 13301
kadonotakashi 0:8fdf9a60065b 13302
kadonotakashi 0:8fdf9a60065b 13303 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 13304 -- SMC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 13305 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 13306
kadonotakashi 0:8fdf9a60065b 13307 /*!
kadonotakashi 0:8fdf9a60065b 13308 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 13309 * @{
kadonotakashi 0:8fdf9a60065b 13310 */
kadonotakashi 0:8fdf9a60065b 13311
kadonotakashi 0:8fdf9a60065b 13312 /** SMC - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 13313 typedef struct {
kadonotakashi 0:8fdf9a60065b 13314 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 13315 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 13316 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 13317 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
kadonotakashi 0:8fdf9a60065b 13318 } SMC_Type;
kadonotakashi 0:8fdf9a60065b 13319
kadonotakashi 0:8fdf9a60065b 13320 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 13321 -- SMC Register Masks
kadonotakashi 0:8fdf9a60065b 13322 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 13323
kadonotakashi 0:8fdf9a60065b 13324 /*!
kadonotakashi 0:8fdf9a60065b 13325 * @addtogroup SMC_Register_Masks SMC Register Masks
kadonotakashi 0:8fdf9a60065b 13326 * @{
kadonotakashi 0:8fdf9a60065b 13327 */
kadonotakashi 0:8fdf9a60065b 13328
kadonotakashi 0:8fdf9a60065b 13329 /*! @name PMPROT - Power Mode Protection register */
kadonotakashi 0:8fdf9a60065b 13330 #define SMC_PMPROT_AVLLS_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 13331 #define SMC_PMPROT_AVLLS_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13332 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
kadonotakashi 0:8fdf9a60065b 13333 #define SMC_PMPROT_ALLS_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 13334 #define SMC_PMPROT_ALLS_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 13335 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
kadonotakashi 0:8fdf9a60065b 13336 #define SMC_PMPROT_AVLP_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 13337 #define SMC_PMPROT_AVLP_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 13338 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
kadonotakashi 0:8fdf9a60065b 13339 #define SMC_PMPROT_AHSRUN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 13340 #define SMC_PMPROT_AHSRUN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 13341 #define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
kadonotakashi 0:8fdf9a60065b 13342
kadonotakashi 0:8fdf9a60065b 13343 /*! @name PMCTRL - Power Mode Control register */
kadonotakashi 0:8fdf9a60065b 13344 #define SMC_PMCTRL_STOPM_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 13345 #define SMC_PMCTRL_STOPM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13346 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
kadonotakashi 0:8fdf9a60065b 13347 #define SMC_PMCTRL_STOPA_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 13348 #define SMC_PMCTRL_STOPA_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 13349 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
kadonotakashi 0:8fdf9a60065b 13350 #define SMC_PMCTRL_RUNM_MASK (0x60U)
kadonotakashi 0:8fdf9a60065b 13351 #define SMC_PMCTRL_RUNM_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 13352 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
kadonotakashi 0:8fdf9a60065b 13353
kadonotakashi 0:8fdf9a60065b 13354 /*! @name STOPCTRL - Stop Control Register */
kadonotakashi 0:8fdf9a60065b 13355 #define SMC_STOPCTRL_LLSM_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 13356 #define SMC_STOPCTRL_LLSM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13357 #define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
kadonotakashi 0:8fdf9a60065b 13358 #define SMC_STOPCTRL_LPOPO_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 13359 #define SMC_STOPCTRL_LPOPO_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 13360 #define SMC_STOPCTRL_LPOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK)
kadonotakashi 0:8fdf9a60065b 13361 #define SMC_STOPCTRL_RAM2PO_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 13362 #define SMC_STOPCTRL_RAM2PO_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 13363 #define SMC_STOPCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
kadonotakashi 0:8fdf9a60065b 13364 #define SMC_STOPCTRL_PORPO_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 13365 #define SMC_STOPCTRL_PORPO_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 13366 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
kadonotakashi 0:8fdf9a60065b 13367 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 13368 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 13369 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
kadonotakashi 0:8fdf9a60065b 13370
kadonotakashi 0:8fdf9a60065b 13371 /*! @name PMSTAT - Power Mode Status register */
kadonotakashi 0:8fdf9a60065b 13372 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 13373 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13374 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
kadonotakashi 0:8fdf9a60065b 13375
kadonotakashi 0:8fdf9a60065b 13376
kadonotakashi 0:8fdf9a60065b 13377 /*!
kadonotakashi 0:8fdf9a60065b 13378 * @}
kadonotakashi 0:8fdf9a60065b 13379 */ /* end of group SMC_Register_Masks */
kadonotakashi 0:8fdf9a60065b 13380
kadonotakashi 0:8fdf9a60065b 13381
kadonotakashi 0:8fdf9a60065b 13382 /* SMC - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 13383 /** Peripheral SMC base address */
kadonotakashi 0:8fdf9a60065b 13384 #define SMC_BASE (0x4007E000u)
kadonotakashi 0:8fdf9a60065b 13385 /** Peripheral SMC base pointer */
kadonotakashi 0:8fdf9a60065b 13386 #define SMC ((SMC_Type *)SMC_BASE)
kadonotakashi 0:8fdf9a60065b 13387 /** Array initializer of SMC peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 13388 #define SMC_BASE_ADDRS { SMC_BASE }
kadonotakashi 0:8fdf9a60065b 13389 /** Array initializer of SMC peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 13390 #define SMC_BASE_PTRS { SMC }
kadonotakashi 0:8fdf9a60065b 13391
kadonotakashi 0:8fdf9a60065b 13392 /*!
kadonotakashi 0:8fdf9a60065b 13393 * @}
kadonotakashi 0:8fdf9a60065b 13394 */ /* end of group SMC_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 13395
kadonotakashi 0:8fdf9a60065b 13396
kadonotakashi 0:8fdf9a60065b 13397 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 13398 -- SPI Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 13399 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 13400
kadonotakashi 0:8fdf9a60065b 13401 /*!
kadonotakashi 0:8fdf9a60065b 13402 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 13403 * @{
kadonotakashi 0:8fdf9a60065b 13404 */
kadonotakashi 0:8fdf9a60065b 13405
kadonotakashi 0:8fdf9a60065b 13406 /** SPI - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 13407 typedef struct {
kadonotakashi 0:8fdf9a60065b 13408 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 13409 uint8_t RESERVED_0[4];
kadonotakashi 0:8fdf9a60065b 13410 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 13411 union { /* offset: 0xC */
kadonotakashi 0:8fdf9a60065b 13412 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 13413 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 13414 };
kadonotakashi 0:8fdf9a60065b 13415 uint8_t RESERVED_1[24];
kadonotakashi 0:8fdf9a60065b 13416 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
kadonotakashi 0:8fdf9a60065b 13417 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
kadonotakashi 0:8fdf9a60065b 13418 union { /* offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 13419 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 13420 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 13421 };
kadonotakashi 0:8fdf9a60065b 13422 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
kadonotakashi 0:8fdf9a60065b 13423 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
kadonotakashi 0:8fdf9a60065b 13424 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
kadonotakashi 0:8fdf9a60065b 13425 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
kadonotakashi 0:8fdf9a60065b 13426 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
kadonotakashi 0:8fdf9a60065b 13427 uint8_t RESERVED_2[48];
kadonotakashi 0:8fdf9a60065b 13428 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
kadonotakashi 0:8fdf9a60065b 13429 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
kadonotakashi 0:8fdf9a60065b 13430 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
kadonotakashi 0:8fdf9a60065b 13431 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
kadonotakashi 0:8fdf9a60065b 13432 } SPI_Type;
kadonotakashi 0:8fdf9a60065b 13433
kadonotakashi 0:8fdf9a60065b 13434 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 13435 -- SPI Register Masks
kadonotakashi 0:8fdf9a60065b 13436 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 13437
kadonotakashi 0:8fdf9a60065b 13438 /*!
kadonotakashi 0:8fdf9a60065b 13439 * @addtogroup SPI_Register_Masks SPI Register Masks
kadonotakashi 0:8fdf9a60065b 13440 * @{
kadonotakashi 0:8fdf9a60065b 13441 */
kadonotakashi 0:8fdf9a60065b 13442
kadonotakashi 0:8fdf9a60065b 13443 /*! @name MCR - Module Configuration Register */
kadonotakashi 0:8fdf9a60065b 13444 #define SPI_MCR_HALT_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13445 #define SPI_MCR_HALT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13446 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
kadonotakashi 0:8fdf9a60065b 13447 #define SPI_MCR_SMPL_PT_MASK (0x300U)
kadonotakashi 0:8fdf9a60065b 13448 #define SPI_MCR_SMPL_PT_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 13449 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
kadonotakashi 0:8fdf9a60065b 13450 #define SPI_MCR_CLR_RXF_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 13451 #define SPI_MCR_CLR_RXF_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 13452 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
kadonotakashi 0:8fdf9a60065b 13453 #define SPI_MCR_CLR_TXF_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 13454 #define SPI_MCR_CLR_TXF_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 13455 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
kadonotakashi 0:8fdf9a60065b 13456 #define SPI_MCR_DIS_RXF_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 13457 #define SPI_MCR_DIS_RXF_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 13458 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
kadonotakashi 0:8fdf9a60065b 13459 #define SPI_MCR_DIS_TXF_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 13460 #define SPI_MCR_DIS_TXF_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 13461 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
kadonotakashi 0:8fdf9a60065b 13462 #define SPI_MCR_MDIS_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 13463 #define SPI_MCR_MDIS_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 13464 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
kadonotakashi 0:8fdf9a60065b 13465 #define SPI_MCR_DOZE_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 13466 #define SPI_MCR_DOZE_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 13467 #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
kadonotakashi 0:8fdf9a60065b 13468 #define SPI_MCR_PCSIS_MASK (0x3F0000U)
kadonotakashi 0:8fdf9a60065b 13469 #define SPI_MCR_PCSIS_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13470 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
kadonotakashi 0:8fdf9a60065b 13471 #define SPI_MCR_ROOE_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 13472 #define SPI_MCR_ROOE_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 13473 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
kadonotakashi 0:8fdf9a60065b 13474 #define SPI_MCR_PCSSE_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 13475 #define SPI_MCR_PCSSE_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 13476 #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
kadonotakashi 0:8fdf9a60065b 13477 #define SPI_MCR_MTFE_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 13478 #define SPI_MCR_MTFE_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 13479 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
kadonotakashi 0:8fdf9a60065b 13480 #define SPI_MCR_FRZ_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 13481 #define SPI_MCR_FRZ_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 13482 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
kadonotakashi 0:8fdf9a60065b 13483 #define SPI_MCR_DCONF_MASK (0x30000000U)
kadonotakashi 0:8fdf9a60065b 13484 #define SPI_MCR_DCONF_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 13485 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
kadonotakashi 0:8fdf9a60065b 13486 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 13487 #define SPI_MCR_CONT_SCKE_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 13488 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
kadonotakashi 0:8fdf9a60065b 13489 #define SPI_MCR_MSTR_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 13490 #define SPI_MCR_MSTR_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 13491 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
kadonotakashi 0:8fdf9a60065b 13492
kadonotakashi 0:8fdf9a60065b 13493 /*! @name TCR - Transfer Count Register */
kadonotakashi 0:8fdf9a60065b 13494 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 13495 #define SPI_TCR_SPI_TCNT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13496 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
kadonotakashi 0:8fdf9a60065b 13497
kadonotakashi 0:8fdf9a60065b 13498 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
kadonotakashi 0:8fdf9a60065b 13499 #define SPI_CTAR_BR_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 13500 #define SPI_CTAR_BR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13501 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
kadonotakashi 0:8fdf9a60065b 13502 #define SPI_CTAR_DT_MASK (0xF0U)
kadonotakashi 0:8fdf9a60065b 13503 #define SPI_CTAR_DT_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 13504 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
kadonotakashi 0:8fdf9a60065b 13505 #define SPI_CTAR_ASC_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 13506 #define SPI_CTAR_ASC_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 13507 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
kadonotakashi 0:8fdf9a60065b 13508 #define SPI_CTAR_CSSCK_MASK (0xF000U)
kadonotakashi 0:8fdf9a60065b 13509 #define SPI_CTAR_CSSCK_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 13510 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
kadonotakashi 0:8fdf9a60065b 13511 #define SPI_CTAR_PBR_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 13512 #define SPI_CTAR_PBR_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13513 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
kadonotakashi 0:8fdf9a60065b 13514 #define SPI_CTAR_PDT_MASK (0xC0000U)
kadonotakashi 0:8fdf9a60065b 13515 #define SPI_CTAR_PDT_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 13516 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
kadonotakashi 0:8fdf9a60065b 13517 #define SPI_CTAR_PASC_MASK (0x300000U)
kadonotakashi 0:8fdf9a60065b 13518 #define SPI_CTAR_PASC_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 13519 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
kadonotakashi 0:8fdf9a60065b 13520 #define SPI_CTAR_PCSSCK_MASK (0xC00000U)
kadonotakashi 0:8fdf9a60065b 13521 #define SPI_CTAR_PCSSCK_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 13522 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
kadonotakashi 0:8fdf9a60065b 13523 #define SPI_CTAR_LSBFE_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 13524 #define SPI_CTAR_LSBFE_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 13525 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
kadonotakashi 0:8fdf9a60065b 13526 #define SPI_CTAR_CPHA_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 13527 #define SPI_CTAR_CPHA_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 13528 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
kadonotakashi 0:8fdf9a60065b 13529 #define SPI_CTAR_CPOL_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 13530 #define SPI_CTAR_CPOL_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 13531 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
kadonotakashi 0:8fdf9a60065b 13532 #define SPI_CTAR_FMSZ_MASK (0x78000000U)
kadonotakashi 0:8fdf9a60065b 13533 #define SPI_CTAR_FMSZ_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 13534 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
kadonotakashi 0:8fdf9a60065b 13535 #define SPI_CTAR_DBR_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 13536 #define SPI_CTAR_DBR_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 13537 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
kadonotakashi 0:8fdf9a60065b 13538
kadonotakashi 0:8fdf9a60065b 13539 /* The count of SPI_CTAR */
kadonotakashi 0:8fdf9a60065b 13540 #define SPI_CTAR_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 13541
kadonotakashi 0:8fdf9a60065b 13542 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
kadonotakashi 0:8fdf9a60065b 13543 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 13544 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 13545 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
kadonotakashi 0:8fdf9a60065b 13546 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 13547 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 13548 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
kadonotakashi 0:8fdf9a60065b 13549 #define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U)
kadonotakashi 0:8fdf9a60065b 13550 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 13551 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
kadonotakashi 0:8fdf9a60065b 13552
kadonotakashi 0:8fdf9a60065b 13553 /* The count of SPI_CTAR_SLAVE */
kadonotakashi 0:8fdf9a60065b 13554 #define SPI_CTAR_SLAVE_COUNT (1U)
kadonotakashi 0:8fdf9a60065b 13555
kadonotakashi 0:8fdf9a60065b 13556 /*! @name SR - Status Register */
kadonotakashi 0:8fdf9a60065b 13557 #define SPI_SR_POPNXTPTR_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 13558 #define SPI_SR_POPNXTPTR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13559 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
kadonotakashi 0:8fdf9a60065b 13560 #define SPI_SR_RXCTR_MASK (0xF0U)
kadonotakashi 0:8fdf9a60065b 13561 #define SPI_SR_RXCTR_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 13562 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
kadonotakashi 0:8fdf9a60065b 13563 #define SPI_SR_TXNXTPTR_MASK (0xF00U)
kadonotakashi 0:8fdf9a60065b 13564 #define SPI_SR_TXNXTPTR_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 13565 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
kadonotakashi 0:8fdf9a60065b 13566 #define SPI_SR_TXCTR_MASK (0xF000U)
kadonotakashi 0:8fdf9a60065b 13567 #define SPI_SR_TXCTR_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 13568 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
kadonotakashi 0:8fdf9a60065b 13569 #define SPI_SR_RFDF_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 13570 #define SPI_SR_RFDF_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 13571 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
kadonotakashi 0:8fdf9a60065b 13572 #define SPI_SR_RFOF_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 13573 #define SPI_SR_RFOF_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 13574 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
kadonotakashi 0:8fdf9a60065b 13575 #define SPI_SR_TFFF_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 13576 #define SPI_SR_TFFF_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 13577 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
kadonotakashi 0:8fdf9a60065b 13578 #define SPI_SR_TFUF_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 13579 #define SPI_SR_TFUF_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 13580 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
kadonotakashi 0:8fdf9a60065b 13581 #define SPI_SR_EOQF_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 13582 #define SPI_SR_EOQF_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 13583 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
kadonotakashi 0:8fdf9a60065b 13584 #define SPI_SR_TXRXS_MASK (0x40000000U)
kadonotakashi 0:8fdf9a60065b 13585 #define SPI_SR_TXRXS_SHIFT (30U)
kadonotakashi 0:8fdf9a60065b 13586 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
kadonotakashi 0:8fdf9a60065b 13587 #define SPI_SR_TCF_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 13588 #define SPI_SR_TCF_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 13589 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
kadonotakashi 0:8fdf9a60065b 13590
kadonotakashi 0:8fdf9a60065b 13591 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
kadonotakashi 0:8fdf9a60065b 13592 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 13593 #define SPI_RSER_RFDF_DIRS_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13594 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
kadonotakashi 0:8fdf9a60065b 13595 #define SPI_RSER_RFDF_RE_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 13596 #define SPI_RSER_RFDF_RE_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 13597 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
kadonotakashi 0:8fdf9a60065b 13598 #define SPI_RSER_RFOF_RE_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 13599 #define SPI_RSER_RFOF_RE_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 13600 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
kadonotakashi 0:8fdf9a60065b 13601 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 13602 #define SPI_RSER_TFFF_DIRS_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 13603 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
kadonotakashi 0:8fdf9a60065b 13604 #define SPI_RSER_TFFF_RE_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 13605 #define SPI_RSER_TFFF_RE_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 13606 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
kadonotakashi 0:8fdf9a60065b 13607 #define SPI_RSER_TFUF_RE_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 13608 #define SPI_RSER_TFUF_RE_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 13609 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
kadonotakashi 0:8fdf9a60065b 13610 #define SPI_RSER_EOQF_RE_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 13611 #define SPI_RSER_EOQF_RE_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 13612 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
kadonotakashi 0:8fdf9a60065b 13613 #define SPI_RSER_TCF_RE_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 13614 #define SPI_RSER_TCF_RE_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 13615 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
kadonotakashi 0:8fdf9a60065b 13616
kadonotakashi 0:8fdf9a60065b 13617 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
kadonotakashi 0:8fdf9a60065b 13618 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 13619 #define SPI_PUSHR_TXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13620 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13621 #define SPI_PUSHR_PCS_MASK (0x3F0000U)
kadonotakashi 0:8fdf9a60065b 13622 #define SPI_PUSHR_PCS_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13623 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
kadonotakashi 0:8fdf9a60065b 13624 #define SPI_PUSHR_CTCNT_MASK (0x4000000U)
kadonotakashi 0:8fdf9a60065b 13625 #define SPI_PUSHR_CTCNT_SHIFT (26U)
kadonotakashi 0:8fdf9a60065b 13626 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
kadonotakashi 0:8fdf9a60065b 13627 #define SPI_PUSHR_EOQ_MASK (0x8000000U)
kadonotakashi 0:8fdf9a60065b 13628 #define SPI_PUSHR_EOQ_SHIFT (27U)
kadonotakashi 0:8fdf9a60065b 13629 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
kadonotakashi 0:8fdf9a60065b 13630 #define SPI_PUSHR_CTAS_MASK (0x70000000U)
kadonotakashi 0:8fdf9a60065b 13631 #define SPI_PUSHR_CTAS_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 13632 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
kadonotakashi 0:8fdf9a60065b 13633 #define SPI_PUSHR_CONT_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 13634 #define SPI_PUSHR_CONT_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 13635 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
kadonotakashi 0:8fdf9a60065b 13636
kadonotakashi 0:8fdf9a60065b 13637 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
kadonotakashi 0:8fdf9a60065b 13638 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 13639 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13640 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13641
kadonotakashi 0:8fdf9a60065b 13642 /*! @name POPR - POP RX FIFO Register */
kadonotakashi 0:8fdf9a60065b 13643 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 13644 #define SPI_POPR_RXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13645 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13646
kadonotakashi 0:8fdf9a60065b 13647 /*! @name TXFR0 - Transmit FIFO Registers */
kadonotakashi 0:8fdf9a60065b 13648 #define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 13649 #define SPI_TXFR0_TXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13650 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13651 #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 13652 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13653 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13654
kadonotakashi 0:8fdf9a60065b 13655 /*! @name TXFR1 - Transmit FIFO Registers */
kadonotakashi 0:8fdf9a60065b 13656 #define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 13657 #define SPI_TXFR1_TXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13658 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13659 #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 13660 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13661 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13662
kadonotakashi 0:8fdf9a60065b 13663 /*! @name TXFR2 - Transmit FIFO Registers */
kadonotakashi 0:8fdf9a60065b 13664 #define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 13665 #define SPI_TXFR2_TXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13666 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13667 #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 13668 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13669 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13670
kadonotakashi 0:8fdf9a60065b 13671 /*! @name TXFR3 - Transmit FIFO Registers */
kadonotakashi 0:8fdf9a60065b 13672 #define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 13673 #define SPI_TXFR3_TXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13674 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13675 #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 13676 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13677 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13678
kadonotakashi 0:8fdf9a60065b 13679 /*! @name RXFR0 - Receive FIFO Registers */
kadonotakashi 0:8fdf9a60065b 13680 #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 13681 #define SPI_RXFR0_RXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13682 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13683
kadonotakashi 0:8fdf9a60065b 13684 /*! @name RXFR1 - Receive FIFO Registers */
kadonotakashi 0:8fdf9a60065b 13685 #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 13686 #define SPI_RXFR1_RXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13687 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13688
kadonotakashi 0:8fdf9a60065b 13689 /*! @name RXFR2 - Receive FIFO Registers */
kadonotakashi 0:8fdf9a60065b 13690 #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 13691 #define SPI_RXFR2_RXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13692 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13693
kadonotakashi 0:8fdf9a60065b 13694 /*! @name RXFR3 - Receive FIFO Registers */
kadonotakashi 0:8fdf9a60065b 13695 #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 13696 #define SPI_RXFR3_RXDATA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13697 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
kadonotakashi 0:8fdf9a60065b 13698
kadonotakashi 0:8fdf9a60065b 13699
kadonotakashi 0:8fdf9a60065b 13700 /*!
kadonotakashi 0:8fdf9a60065b 13701 * @}
kadonotakashi 0:8fdf9a60065b 13702 */ /* end of group SPI_Register_Masks */
kadonotakashi 0:8fdf9a60065b 13703
kadonotakashi 0:8fdf9a60065b 13704
kadonotakashi 0:8fdf9a60065b 13705 /* SPI - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 13706 /** Peripheral SPI0 base address */
kadonotakashi 0:8fdf9a60065b 13707 #define SPI0_BASE (0x4002C000u)
kadonotakashi 0:8fdf9a60065b 13708 /** Peripheral SPI0 base pointer */
kadonotakashi 0:8fdf9a60065b 13709 #define SPI0 ((SPI_Type *)SPI0_BASE)
kadonotakashi 0:8fdf9a60065b 13710 /** Peripheral SPI1 base address */
kadonotakashi 0:8fdf9a60065b 13711 #define SPI1_BASE (0x4002D000u)
kadonotakashi 0:8fdf9a60065b 13712 /** Peripheral SPI1 base pointer */
kadonotakashi 0:8fdf9a60065b 13713 #define SPI1 ((SPI_Type *)SPI1_BASE)
kadonotakashi 0:8fdf9a60065b 13714 /** Peripheral SPI2 base address */
kadonotakashi 0:8fdf9a60065b 13715 #define SPI2_BASE (0x400AC000u)
kadonotakashi 0:8fdf9a60065b 13716 /** Peripheral SPI2 base pointer */
kadonotakashi 0:8fdf9a60065b 13717 #define SPI2 ((SPI_Type *)SPI2_BASE)
kadonotakashi 0:8fdf9a60065b 13718 /** Array initializer of SPI peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 13719 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
kadonotakashi 0:8fdf9a60065b 13720 /** Array initializer of SPI peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 13721 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
kadonotakashi 0:8fdf9a60065b 13722 /** Interrupt vectors for the SPI peripheral type */
kadonotakashi 0:8fdf9a60065b 13723 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
kadonotakashi 0:8fdf9a60065b 13724
kadonotakashi 0:8fdf9a60065b 13725 /*!
kadonotakashi 0:8fdf9a60065b 13726 * @}
kadonotakashi 0:8fdf9a60065b 13727 */ /* end of group SPI_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 13728
kadonotakashi 0:8fdf9a60065b 13729
kadonotakashi 0:8fdf9a60065b 13730 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 13731 -- TPM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 13732 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 13733
kadonotakashi 0:8fdf9a60065b 13734 /*!
kadonotakashi 0:8fdf9a60065b 13735 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 13736 * @{
kadonotakashi 0:8fdf9a60065b 13737 */
kadonotakashi 0:8fdf9a60065b 13738
kadonotakashi 0:8fdf9a60065b 13739 /** TPM - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 13740 typedef struct {
kadonotakashi 0:8fdf9a60065b 13741 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 13742 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 13743 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 13744 struct { /* offset: 0xC, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 13745 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 13746 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
kadonotakashi 0:8fdf9a60065b 13747 } CONTROLS[2];
kadonotakashi 0:8fdf9a60065b 13748 uint8_t RESERVED_0[52];
kadonotakashi 0:8fdf9a60065b 13749 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
kadonotakashi 0:8fdf9a60065b 13750 uint8_t RESERVED_1[16];
kadonotakashi 0:8fdf9a60065b 13751 __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */
kadonotakashi 0:8fdf9a60065b 13752 uint8_t RESERVED_2[8];
kadonotakashi 0:8fdf9a60065b 13753 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
kadonotakashi 0:8fdf9a60065b 13754 uint8_t RESERVED_3[4];
kadonotakashi 0:8fdf9a60065b 13755 __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */
kadonotakashi 0:8fdf9a60065b 13756 uint8_t RESERVED_4[4];
kadonotakashi 0:8fdf9a60065b 13757 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
kadonotakashi 0:8fdf9a60065b 13758 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
kadonotakashi 0:8fdf9a60065b 13759 } TPM_Type;
kadonotakashi 0:8fdf9a60065b 13760
kadonotakashi 0:8fdf9a60065b 13761 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 13762 -- TPM Register Masks
kadonotakashi 0:8fdf9a60065b 13763 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 13764
kadonotakashi 0:8fdf9a60065b 13765 /*!
kadonotakashi 0:8fdf9a60065b 13766 * @addtogroup TPM_Register_Masks TPM Register Masks
kadonotakashi 0:8fdf9a60065b 13767 * @{
kadonotakashi 0:8fdf9a60065b 13768 */
kadonotakashi 0:8fdf9a60065b 13769
kadonotakashi 0:8fdf9a60065b 13770 /*! @name SC - Status and Control */
kadonotakashi 0:8fdf9a60065b 13771 #define TPM_SC_PS_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 13772 #define TPM_SC_PS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13773 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
kadonotakashi 0:8fdf9a60065b 13774 #define TPM_SC_CMOD_MASK (0x18U)
kadonotakashi 0:8fdf9a60065b 13775 #define TPM_SC_CMOD_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 13776 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
kadonotakashi 0:8fdf9a60065b 13777 #define TPM_SC_CPWMS_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 13778 #define TPM_SC_CPWMS_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 13779 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
kadonotakashi 0:8fdf9a60065b 13780 #define TPM_SC_TOIE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 13781 #define TPM_SC_TOIE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 13782 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
kadonotakashi 0:8fdf9a60065b 13783 #define TPM_SC_TOF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 13784 #define TPM_SC_TOF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 13785 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
kadonotakashi 0:8fdf9a60065b 13786 #define TPM_SC_DMA_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 13787 #define TPM_SC_DMA_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 13788 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
kadonotakashi 0:8fdf9a60065b 13789
kadonotakashi 0:8fdf9a60065b 13790 /*! @name CNT - Counter */
kadonotakashi 0:8fdf9a60065b 13791 #define TPM_CNT_COUNT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 13792 #define TPM_CNT_COUNT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13793 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
kadonotakashi 0:8fdf9a60065b 13794
kadonotakashi 0:8fdf9a60065b 13795 /*! @name MOD - Modulo */
kadonotakashi 0:8fdf9a60065b 13796 #define TPM_MOD_MOD_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 13797 #define TPM_MOD_MOD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13798 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
kadonotakashi 0:8fdf9a60065b 13799
kadonotakashi 0:8fdf9a60065b 13800 /*! @name CnSC - Channel (n) Status and Control */
kadonotakashi 0:8fdf9a60065b 13801 #define TPM_CnSC_DMA_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13802 #define TPM_CnSC_DMA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13803 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
kadonotakashi 0:8fdf9a60065b 13804 #define TPM_CnSC_ELSA_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 13805 #define TPM_CnSC_ELSA_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 13806 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
kadonotakashi 0:8fdf9a60065b 13807 #define TPM_CnSC_ELSB_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 13808 #define TPM_CnSC_ELSB_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 13809 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
kadonotakashi 0:8fdf9a60065b 13810 #define TPM_CnSC_MSA_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 13811 #define TPM_CnSC_MSA_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 13812 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
kadonotakashi 0:8fdf9a60065b 13813 #define TPM_CnSC_MSB_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 13814 #define TPM_CnSC_MSB_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 13815 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
kadonotakashi 0:8fdf9a60065b 13816 #define TPM_CnSC_CHIE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 13817 #define TPM_CnSC_CHIE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 13818 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
kadonotakashi 0:8fdf9a60065b 13819 #define TPM_CnSC_CHF_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 13820 #define TPM_CnSC_CHF_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 13821 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
kadonotakashi 0:8fdf9a60065b 13822
kadonotakashi 0:8fdf9a60065b 13823 /* The count of TPM_CnSC */
kadonotakashi 0:8fdf9a60065b 13824 #define TPM_CnSC_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 13825
kadonotakashi 0:8fdf9a60065b 13826 /*! @name CnV - Channel (n) Value */
kadonotakashi 0:8fdf9a60065b 13827 #define TPM_CnV_VAL_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 13828 #define TPM_CnV_VAL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13829 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
kadonotakashi 0:8fdf9a60065b 13830
kadonotakashi 0:8fdf9a60065b 13831 /* The count of TPM_CnV */
kadonotakashi 0:8fdf9a60065b 13832 #define TPM_CnV_COUNT (2U)
kadonotakashi 0:8fdf9a60065b 13833
kadonotakashi 0:8fdf9a60065b 13834 /*! @name STATUS - Capture and Compare Status */
kadonotakashi 0:8fdf9a60065b 13835 #define TPM_STATUS_CH0F_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13836 #define TPM_STATUS_CH0F_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13837 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
kadonotakashi 0:8fdf9a60065b 13838 #define TPM_STATUS_CH1F_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 13839 #define TPM_STATUS_CH1F_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13840 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
kadonotakashi 0:8fdf9a60065b 13841 #define TPM_STATUS_TOF_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 13842 #define TPM_STATUS_TOF_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 13843 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
kadonotakashi 0:8fdf9a60065b 13844
kadonotakashi 0:8fdf9a60065b 13845 /*! @name COMBINE - Combine Channel Register */
kadonotakashi 0:8fdf9a60065b 13846 #define TPM_COMBINE_COMBINE0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13847 #define TPM_COMBINE_COMBINE0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13848 #define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
kadonotakashi 0:8fdf9a60065b 13849 #define TPM_COMBINE_COMSWAP0_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 13850 #define TPM_COMBINE_COMSWAP0_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13851 #define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
kadonotakashi 0:8fdf9a60065b 13852
kadonotakashi 0:8fdf9a60065b 13853 /*! @name POL - Channel Polarity */
kadonotakashi 0:8fdf9a60065b 13854 #define TPM_POL_POL0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13855 #define TPM_POL_POL0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13856 #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
kadonotakashi 0:8fdf9a60065b 13857 #define TPM_POL_POL1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 13858 #define TPM_POL_POL1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13859 #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
kadonotakashi 0:8fdf9a60065b 13860
kadonotakashi 0:8fdf9a60065b 13861 /*! @name FILTER - Filter Control */
kadonotakashi 0:8fdf9a60065b 13862 #define TPM_FILTER_CH0FVAL_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 13863 #define TPM_FILTER_CH0FVAL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13864 #define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
kadonotakashi 0:8fdf9a60065b 13865 #define TPM_FILTER_CH1FVAL_MASK (0xF0U)
kadonotakashi 0:8fdf9a60065b 13866 #define TPM_FILTER_CH1FVAL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 13867 #define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
kadonotakashi 0:8fdf9a60065b 13868
kadonotakashi 0:8fdf9a60065b 13869 /*! @name QDCTRL - Quadrature Decoder Control and Status */
kadonotakashi 0:8fdf9a60065b 13870 #define TPM_QDCTRL_QUADEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 13871 #define TPM_QDCTRL_QUADEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 13872 #define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
kadonotakashi 0:8fdf9a60065b 13873 #define TPM_QDCTRL_TOFDIR_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 13874 #define TPM_QDCTRL_TOFDIR_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 13875 #define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
kadonotakashi 0:8fdf9a60065b 13876 #define TPM_QDCTRL_QUADIR_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 13877 #define TPM_QDCTRL_QUADIR_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 13878 #define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
kadonotakashi 0:8fdf9a60065b 13879 #define TPM_QDCTRL_QUADMODE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 13880 #define TPM_QDCTRL_QUADMODE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 13881 #define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
kadonotakashi 0:8fdf9a60065b 13882
kadonotakashi 0:8fdf9a60065b 13883 /*! @name CONF - Configuration */
kadonotakashi 0:8fdf9a60065b 13884 #define TPM_CONF_DOZEEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 13885 #define TPM_CONF_DOZEEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 13886 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
kadonotakashi 0:8fdf9a60065b 13887 #define TPM_CONF_DBGMODE_MASK (0xC0U)
kadonotakashi 0:8fdf9a60065b 13888 #define TPM_CONF_DBGMODE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 13889 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
kadonotakashi 0:8fdf9a60065b 13890 #define TPM_CONF_GTBSYNC_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 13891 #define TPM_CONF_GTBSYNC_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 13892 #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
kadonotakashi 0:8fdf9a60065b 13893 #define TPM_CONF_GTBEEN_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 13894 #define TPM_CONF_GTBEEN_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 13895 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
kadonotakashi 0:8fdf9a60065b 13896 #define TPM_CONF_CSOT_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 13897 #define TPM_CONF_CSOT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 13898 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
kadonotakashi 0:8fdf9a60065b 13899 #define TPM_CONF_CSOO_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 13900 #define TPM_CONF_CSOO_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 13901 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
kadonotakashi 0:8fdf9a60065b 13902 #define TPM_CONF_CROT_MASK (0x40000U)
kadonotakashi 0:8fdf9a60065b 13903 #define TPM_CONF_CROT_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 13904 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
kadonotakashi 0:8fdf9a60065b 13905 #define TPM_CONF_CPOT_MASK (0x80000U)
kadonotakashi 0:8fdf9a60065b 13906 #define TPM_CONF_CPOT_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 13907 #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
kadonotakashi 0:8fdf9a60065b 13908 #define TPM_CONF_TRGPOL_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 13909 #define TPM_CONF_TRGPOL_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 13910 #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
kadonotakashi 0:8fdf9a60065b 13911 #define TPM_CONF_TRGSRC_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 13912 #define TPM_CONF_TRGSRC_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 13913 #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
kadonotakashi 0:8fdf9a60065b 13914 #define TPM_CONF_TRGSEL_MASK (0xF000000U)
kadonotakashi 0:8fdf9a60065b 13915 #define TPM_CONF_TRGSEL_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 13916 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
kadonotakashi 0:8fdf9a60065b 13917
kadonotakashi 0:8fdf9a60065b 13918
kadonotakashi 0:8fdf9a60065b 13919 /*!
kadonotakashi 0:8fdf9a60065b 13920 * @}
kadonotakashi 0:8fdf9a60065b 13921 */ /* end of group TPM_Register_Masks */
kadonotakashi 0:8fdf9a60065b 13922
kadonotakashi 0:8fdf9a60065b 13923
kadonotakashi 0:8fdf9a60065b 13924 /* TPM - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 13925 /** Peripheral TPM1 base address */
kadonotakashi 0:8fdf9a60065b 13926 #define TPM1_BASE (0x400C9000u)
kadonotakashi 0:8fdf9a60065b 13927 /** Peripheral TPM1 base pointer */
kadonotakashi 0:8fdf9a60065b 13928 #define TPM1 ((TPM_Type *)TPM1_BASE)
kadonotakashi 0:8fdf9a60065b 13929 /** Peripheral TPM2 base address */
kadonotakashi 0:8fdf9a60065b 13930 #define TPM2_BASE (0x400CA000u)
kadonotakashi 0:8fdf9a60065b 13931 /** Peripheral TPM2 base pointer */
kadonotakashi 0:8fdf9a60065b 13932 #define TPM2 ((TPM_Type *)TPM2_BASE)
kadonotakashi 0:8fdf9a60065b 13933 /** Array initializer of TPM peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 13934 #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE }
kadonotakashi 0:8fdf9a60065b 13935 /** Array initializer of TPM peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 13936 #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2 }
kadonotakashi 0:8fdf9a60065b 13937 /** Interrupt vectors for the TPM peripheral type */
kadonotakashi 0:8fdf9a60065b 13938 #define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn }
kadonotakashi 0:8fdf9a60065b 13939
kadonotakashi 0:8fdf9a60065b 13940 /*!
kadonotakashi 0:8fdf9a60065b 13941 * @}
kadonotakashi 0:8fdf9a60065b 13942 */ /* end of group TPM_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 13943
kadonotakashi 0:8fdf9a60065b 13944
kadonotakashi 0:8fdf9a60065b 13945 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 13946 -- TRNG Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 13947 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 13948
kadonotakashi 0:8fdf9a60065b 13949 /*!
kadonotakashi 0:8fdf9a60065b 13950 * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 13951 * @{
kadonotakashi 0:8fdf9a60065b 13952 */
kadonotakashi 0:8fdf9a60065b 13953
kadonotakashi 0:8fdf9a60065b 13954 /** TRNG - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 13955 typedef struct {
kadonotakashi 0:8fdf9a60065b 13956 __IO uint32_t MCTL; /**< RNG Miscellaneous Control Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 13957 __IO uint32_t SCMISC; /**< RNG Statistical Check Miscellaneous Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 13958 __IO uint32_t PKRRNG; /**< RNG Poker Range Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 13959 union { /* offset: 0xC */
kadonotakashi 0:8fdf9a60065b 13960 __IO uint32_t PKRMAX; /**< RNG Poker Maximum Limit Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 13961 __I uint32_t PKRSQ; /**< RNG Poker Square Calculation Result Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 13962 };
kadonotakashi 0:8fdf9a60065b 13963 __IO uint32_t SDCTL; /**< RNG Seed Control Register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 13964 union { /* offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 13965 __IO uint32_t SBLIM; /**< RNG Sparse Bit Limit Register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 13966 __I uint32_t TOTSAM; /**< RNG Total Samples Register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 13967 };
kadonotakashi 0:8fdf9a60065b 13968 __IO uint32_t FRQMIN; /**< RNG Frequency Count Minimum Limit Register, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 13969 union { /* offset: 0x1C */
kadonotakashi 0:8fdf9a60065b 13970 __I uint32_t FRQCNT; /**< RNG Frequency Count Register, offset: 0x1C */
kadonotakashi 0:8fdf9a60065b 13971 __IO uint32_t FRQMAX; /**< RNG Frequency Count Maximum Limit Register, offset: 0x1C */
kadonotakashi 0:8fdf9a60065b 13972 };
kadonotakashi 0:8fdf9a60065b 13973 union { /* offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 13974 __I uint32_t SCMC; /**< RNG Statistical Check Monobit Count Register, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 13975 __IO uint32_t SCML; /**< RNG Statistical Check Monobit Limit Register, offset: 0x20 */
kadonotakashi 0:8fdf9a60065b 13976 };
kadonotakashi 0:8fdf9a60065b 13977 union { /* offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 13978 __I uint32_t SCR1C; /**< RNG Statistical Check Run Length 1 Count Register, offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 13979 __IO uint32_t SCR1L; /**< RNG Statistical Check Run Length 1 Limit Register, offset: 0x24 */
kadonotakashi 0:8fdf9a60065b 13980 };
kadonotakashi 0:8fdf9a60065b 13981 union { /* offset: 0x28 */
kadonotakashi 0:8fdf9a60065b 13982 __I uint32_t SCR2C; /**< RNG Statistical Check Run Length 2 Count Register, offset: 0x28 */
kadonotakashi 0:8fdf9a60065b 13983 __IO uint32_t SCR2L; /**< RNG Statistical Check Run Length 2 Limit Register, offset: 0x28 */
kadonotakashi 0:8fdf9a60065b 13984 };
kadonotakashi 0:8fdf9a60065b 13985 union { /* offset: 0x2C */
kadonotakashi 0:8fdf9a60065b 13986 __I uint32_t SCR3C; /**< RNG Statistical Check Run Length 3 Count Register, offset: 0x2C */
kadonotakashi 0:8fdf9a60065b 13987 __IO uint32_t SCR3L; /**< RNG Statistical Check Run Length 3 Limit Register, offset: 0x2C */
kadonotakashi 0:8fdf9a60065b 13988 };
kadonotakashi 0:8fdf9a60065b 13989 union { /* offset: 0x30 */
kadonotakashi 0:8fdf9a60065b 13990 __I uint32_t SCR4C; /**< RNG Statistical Check Run Length 4 Count Register, offset: 0x30 */
kadonotakashi 0:8fdf9a60065b 13991 __IO uint32_t SCR4L; /**< RNG Statistical Check Run Length 4 Limit Register, offset: 0x30 */
kadonotakashi 0:8fdf9a60065b 13992 };
kadonotakashi 0:8fdf9a60065b 13993 union { /* offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 13994 __I uint32_t SCR5C; /**< RNG Statistical Check Run Length 5 Count Register, offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 13995 __IO uint32_t SCR5L; /**< RNG Statistical Check Run Length 5 Limit Register, offset: 0x34 */
kadonotakashi 0:8fdf9a60065b 13996 };
kadonotakashi 0:8fdf9a60065b 13997 union { /* offset: 0x38 */
kadonotakashi 0:8fdf9a60065b 13998 __I uint32_t SCR6PC; /**< RNG Statistical Check Run Length 6+ Count Register, offset: 0x38 */
kadonotakashi 0:8fdf9a60065b 13999 __IO uint32_t SCR6PL; /**< RNG Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
kadonotakashi 0:8fdf9a60065b 14000 };
kadonotakashi 0:8fdf9a60065b 14001 __I uint32_t STATUS; /**< RNG Status Register, offset: 0x3C */
kadonotakashi 0:8fdf9a60065b 14002 __I uint32_t ENT[16]; /**< RNG TRNG Entropy Read Register, array offset: 0x40, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 14003 __I uint32_t PKRCNT10; /**< RNG Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
kadonotakashi 0:8fdf9a60065b 14004 __I uint32_t PKRCNT32; /**< RNG Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
kadonotakashi 0:8fdf9a60065b 14005 __I uint32_t PKRCNT54; /**< RNG Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
kadonotakashi 0:8fdf9a60065b 14006 __I uint32_t PKRCNT76; /**< RNG Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
kadonotakashi 0:8fdf9a60065b 14007 __I uint32_t PKRCNT98; /**< RNG Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
kadonotakashi 0:8fdf9a60065b 14008 __I uint32_t PKRCNTBA; /**< RNG Statistical Check Poker Count B and A Register, offset: 0x94 */
kadonotakashi 0:8fdf9a60065b 14009 __I uint32_t PKRCNTDC; /**< RNG Statistical Check Poker Count D and C Register, offset: 0x98 */
kadonotakashi 0:8fdf9a60065b 14010 __I uint32_t PKRCNTFE; /**< RNG Statistical Check Poker Count F and E Register, offset: 0x9C */
kadonotakashi 0:8fdf9a60065b 14011 uint8_t RESERVED_0[16];
kadonotakashi 0:8fdf9a60065b 14012 __IO uint32_t SEC_CFG; /**< RNG Security Configuration Register, offset: 0xB0 */
kadonotakashi 0:8fdf9a60065b 14013 __IO uint32_t INT_CTRL; /**< RNG Interrupt Control Register, offset: 0xB4 */
kadonotakashi 0:8fdf9a60065b 14014 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */
kadonotakashi 0:8fdf9a60065b 14015 __IO uint32_t INT_STATUS; /**< RNG Interrupt Status Register, offset: 0xBC */
kadonotakashi 0:8fdf9a60065b 14016 uint8_t RESERVED_1[48];
kadonotakashi 0:8fdf9a60065b 14017 __I uint32_t VID1; /**< RNG Version ID Register (MS), offset: 0xF0 */
kadonotakashi 0:8fdf9a60065b 14018 __I uint32_t VID2; /**< RNG Version ID Register (LS), offset: 0xF4 */
kadonotakashi 0:8fdf9a60065b 14019 } TRNG_Type;
kadonotakashi 0:8fdf9a60065b 14020
kadonotakashi 0:8fdf9a60065b 14021 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 14022 -- TRNG Register Masks
kadonotakashi 0:8fdf9a60065b 14023 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 14024
kadonotakashi 0:8fdf9a60065b 14025 /*!
kadonotakashi 0:8fdf9a60065b 14026 * @addtogroup TRNG_Register_Masks TRNG Register Masks
kadonotakashi 0:8fdf9a60065b 14027 * @{
kadonotakashi 0:8fdf9a60065b 14028 */
kadonotakashi 0:8fdf9a60065b 14029
kadonotakashi 0:8fdf9a60065b 14030 /*! @name MCTL - RNG Miscellaneous Control Register */
kadonotakashi 0:8fdf9a60065b 14031 #define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 14032 #define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14033 #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
kadonotakashi 0:8fdf9a60065b 14034 #define TRNG_MCTL_OSC_DIV_MASK (0xCU)
kadonotakashi 0:8fdf9a60065b 14035 #define TRNG_MCTL_OSC_DIV_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14036 #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
kadonotakashi 0:8fdf9a60065b 14037 #define TRNG_MCTL_UNUSED_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14038 #define TRNG_MCTL_UNUSED_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14039 #define TRNG_MCTL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED_SHIFT)) & TRNG_MCTL_UNUSED_MASK)
kadonotakashi 0:8fdf9a60065b 14040 #define TRNG_MCTL_TRNG_ACC_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14041 #define TRNG_MCTL_TRNG_ACC_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14042 #define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
kadonotakashi 0:8fdf9a60065b 14043 #define TRNG_MCTL_RST_DEF_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14044 #define TRNG_MCTL_RST_DEF_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14045 #define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
kadonotakashi 0:8fdf9a60065b 14046 #define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14047 #define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14048 #define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
kadonotakashi 0:8fdf9a60065b 14049 #define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 14050 #define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 14051 #define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
kadonotakashi 0:8fdf9a60065b 14052 #define TRNG_MCTL_FCT_VAL_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 14053 #define TRNG_MCTL_FCT_VAL_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 14054 #define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
kadonotakashi 0:8fdf9a60065b 14055 #define TRNG_MCTL_ENT_VAL_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 14056 #define TRNG_MCTL_ENT_VAL_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 14057 #define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
kadonotakashi 0:8fdf9a60065b 14058 #define TRNG_MCTL_TST_OUT_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 14059 #define TRNG_MCTL_TST_OUT_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 14060 #define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
kadonotakashi 0:8fdf9a60065b 14061 #define TRNG_MCTL_ERR_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 14062 #define TRNG_MCTL_ERR_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 14063 #define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
kadonotakashi 0:8fdf9a60065b 14064 #define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 14065 #define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 14066 #define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
kadonotakashi 0:8fdf9a60065b 14067 #define TRNG_MCTL_PRGM_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 14068 #define TRNG_MCTL_PRGM_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14069 #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
kadonotakashi 0:8fdf9a60065b 14070
kadonotakashi 0:8fdf9a60065b 14071 /*! @name SCMISC - RNG Statistical Check Miscellaneous Register */
kadonotakashi 0:8fdf9a60065b 14072 #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 14073 #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14074 #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
kadonotakashi 0:8fdf9a60065b 14075 #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 14076 #define TRNG_SCMISC_RTY_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14077 #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14078
kadonotakashi 0:8fdf9a60065b 14079 /*! @name PKRRNG - RNG Poker Range Register */
kadonotakashi 0:8fdf9a60065b 14080 #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14081 #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14082 #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
kadonotakashi 0:8fdf9a60065b 14083
kadonotakashi 0:8fdf9a60065b 14084 /*! @name PKRMAX - RNG Poker Maximum Limit Register */
kadonotakashi 0:8fdf9a60065b 14085 #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
kadonotakashi 0:8fdf9a60065b 14086 #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14087 #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
kadonotakashi 0:8fdf9a60065b 14088
kadonotakashi 0:8fdf9a60065b 14089 /*! @name PKRSQ - RNG Poker Square Calculation Result Register */
kadonotakashi 0:8fdf9a60065b 14090 #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
kadonotakashi 0:8fdf9a60065b 14091 #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14092 #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
kadonotakashi 0:8fdf9a60065b 14093
kadonotakashi 0:8fdf9a60065b 14094 /*! @name SDCTL - RNG Seed Control Register */
kadonotakashi 0:8fdf9a60065b 14095 #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14096 #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14097 #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
kadonotakashi 0:8fdf9a60065b 14098 #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14099 #define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14100 #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
kadonotakashi 0:8fdf9a60065b 14101
kadonotakashi 0:8fdf9a60065b 14102 /*! @name SBLIM - RNG Sparse Bit Limit Register */
kadonotakashi 0:8fdf9a60065b 14103 #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
kadonotakashi 0:8fdf9a60065b 14104 #define TRNG_SBLIM_SB_LIM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14105 #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
kadonotakashi 0:8fdf9a60065b 14106
kadonotakashi 0:8fdf9a60065b 14107 /*! @name TOTSAM - RNG Total Samples Register */
kadonotakashi 0:8fdf9a60065b 14108 #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
kadonotakashi 0:8fdf9a60065b 14109 #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14110 #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
kadonotakashi 0:8fdf9a60065b 14111
kadonotakashi 0:8fdf9a60065b 14112 /*! @name FRQMIN - RNG Frequency Count Minimum Limit Register */
kadonotakashi 0:8fdf9a60065b 14113 #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
kadonotakashi 0:8fdf9a60065b 14114 #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14115 #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
kadonotakashi 0:8fdf9a60065b 14116
kadonotakashi 0:8fdf9a60065b 14117 /*! @name FRQCNT - RNG Frequency Count Register */
kadonotakashi 0:8fdf9a60065b 14118 #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
kadonotakashi 0:8fdf9a60065b 14119 #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14120 #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14121
kadonotakashi 0:8fdf9a60065b 14122 /*! @name FRQMAX - RNG Frequency Count Maximum Limit Register */
kadonotakashi 0:8fdf9a60065b 14123 #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
kadonotakashi 0:8fdf9a60065b 14124 #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14125 #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
kadonotakashi 0:8fdf9a60065b 14126
kadonotakashi 0:8fdf9a60065b 14127 /*! @name SCMC - RNG Statistical Check Monobit Count Register */
kadonotakashi 0:8fdf9a60065b 14128 #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14129 #define TRNG_SCMC_MONO_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14130 #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14131
kadonotakashi 0:8fdf9a60065b 14132 /*! @name SCML - RNG Statistical Check Monobit Limit Register */
kadonotakashi 0:8fdf9a60065b 14133 #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14134 #define TRNG_SCML_MONO_MAX_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14135 #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
kadonotakashi 0:8fdf9a60065b 14136 #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14137 #define TRNG_SCML_MONO_RNG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14138 #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
kadonotakashi 0:8fdf9a60065b 14139
kadonotakashi 0:8fdf9a60065b 14140 /*! @name SCR1C - RNG Statistical Check Run Length 1 Count Register */
kadonotakashi 0:8fdf9a60065b 14141 #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
kadonotakashi 0:8fdf9a60065b 14142 #define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14143 #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14144 #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
kadonotakashi 0:8fdf9a60065b 14145 #define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14146 #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14147
kadonotakashi 0:8fdf9a60065b 14148 /*! @name SCR1L - RNG Statistical Check Run Length 1 Limit Register */
kadonotakashi 0:8fdf9a60065b 14149 #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
kadonotakashi 0:8fdf9a60065b 14150 #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14151 #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
kadonotakashi 0:8fdf9a60065b 14152 #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
kadonotakashi 0:8fdf9a60065b 14153 #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14154 #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
kadonotakashi 0:8fdf9a60065b 14155
kadonotakashi 0:8fdf9a60065b 14156 /*! @name SCR2C - RNG Statistical Check Run Length 2 Count Register */
kadonotakashi 0:8fdf9a60065b 14157 #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
kadonotakashi 0:8fdf9a60065b 14158 #define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14159 #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14160 #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
kadonotakashi 0:8fdf9a60065b 14161 #define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14162 #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14163
kadonotakashi 0:8fdf9a60065b 14164 /*! @name SCR2L - RNG Statistical Check Run Length 2 Limit Register */
kadonotakashi 0:8fdf9a60065b 14165 #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
kadonotakashi 0:8fdf9a60065b 14166 #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14167 #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
kadonotakashi 0:8fdf9a60065b 14168 #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
kadonotakashi 0:8fdf9a60065b 14169 #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14170 #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
kadonotakashi 0:8fdf9a60065b 14171
kadonotakashi 0:8fdf9a60065b 14172 /*! @name SCR3C - RNG Statistical Check Run Length 3 Count Register */
kadonotakashi 0:8fdf9a60065b 14173 #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
kadonotakashi 0:8fdf9a60065b 14174 #define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14175 #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14176 #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
kadonotakashi 0:8fdf9a60065b 14177 #define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14178 #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14179
kadonotakashi 0:8fdf9a60065b 14180 /*! @name SCR3L - RNG Statistical Check Run Length 3 Limit Register */
kadonotakashi 0:8fdf9a60065b 14181 #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
kadonotakashi 0:8fdf9a60065b 14182 #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14183 #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
kadonotakashi 0:8fdf9a60065b 14184 #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
kadonotakashi 0:8fdf9a60065b 14185 #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14186 #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
kadonotakashi 0:8fdf9a60065b 14187
kadonotakashi 0:8fdf9a60065b 14188 /*! @name SCR4C - RNG Statistical Check Run Length 4 Count Register */
kadonotakashi 0:8fdf9a60065b 14189 #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
kadonotakashi 0:8fdf9a60065b 14190 #define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14191 #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14192 #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
kadonotakashi 0:8fdf9a60065b 14193 #define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14194 #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14195
kadonotakashi 0:8fdf9a60065b 14196 /*! @name SCR4L - RNG Statistical Check Run Length 4 Limit Register */
kadonotakashi 0:8fdf9a60065b 14197 #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
kadonotakashi 0:8fdf9a60065b 14198 #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14199 #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
kadonotakashi 0:8fdf9a60065b 14200 #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
kadonotakashi 0:8fdf9a60065b 14201 #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14202 #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
kadonotakashi 0:8fdf9a60065b 14203
kadonotakashi 0:8fdf9a60065b 14204 /*! @name SCR5C - RNG Statistical Check Run Length 5 Count Register */
kadonotakashi 0:8fdf9a60065b 14205 #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
kadonotakashi 0:8fdf9a60065b 14206 #define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14207 #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14208 #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
kadonotakashi 0:8fdf9a60065b 14209 #define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14210 #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14211
kadonotakashi 0:8fdf9a60065b 14212 /*! @name SCR5L - RNG Statistical Check Run Length 5 Limit Register */
kadonotakashi 0:8fdf9a60065b 14213 #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
kadonotakashi 0:8fdf9a60065b 14214 #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14215 #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
kadonotakashi 0:8fdf9a60065b 14216 #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
kadonotakashi 0:8fdf9a60065b 14217 #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14218 #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
kadonotakashi 0:8fdf9a60065b 14219
kadonotakashi 0:8fdf9a60065b 14220 /*! @name SCR6PC - RNG Statistical Check Run Length 6+ Count Register */
kadonotakashi 0:8fdf9a60065b 14221 #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
kadonotakashi 0:8fdf9a60065b 14222 #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14223 #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14224 #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
kadonotakashi 0:8fdf9a60065b 14225 #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14226 #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14227
kadonotakashi 0:8fdf9a60065b 14228 /*! @name SCR6PL - RNG Statistical Check Run Length 6+ Limit Register */
kadonotakashi 0:8fdf9a60065b 14229 #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
kadonotakashi 0:8fdf9a60065b 14230 #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14231 #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
kadonotakashi 0:8fdf9a60065b 14232 #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
kadonotakashi 0:8fdf9a60065b 14233 #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14234 #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
kadonotakashi 0:8fdf9a60065b 14235
kadonotakashi 0:8fdf9a60065b 14236 /*! @name STATUS - RNG Status Register */
kadonotakashi 0:8fdf9a60065b 14237 #define TRNG_STATUS_TF1BR0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14238 #define TRNG_STATUS_TF1BR0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14239 #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
kadonotakashi 0:8fdf9a60065b 14240 #define TRNG_STATUS_TF1BR1_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14241 #define TRNG_STATUS_TF1BR1_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14242 #define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
kadonotakashi 0:8fdf9a60065b 14243 #define TRNG_STATUS_TF2BR0_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14244 #define TRNG_STATUS_TF2BR0_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14245 #define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
kadonotakashi 0:8fdf9a60065b 14246 #define TRNG_STATUS_TF2BR1_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14247 #define TRNG_STATUS_TF2BR1_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14248 #define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
kadonotakashi 0:8fdf9a60065b 14249 #define TRNG_STATUS_TF3BR0_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14250 #define TRNG_STATUS_TF3BR0_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14251 #define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
kadonotakashi 0:8fdf9a60065b 14252 #define TRNG_STATUS_TF3BR1_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14253 #define TRNG_STATUS_TF3BR1_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14254 #define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
kadonotakashi 0:8fdf9a60065b 14255 #define TRNG_STATUS_TF4BR0_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14256 #define TRNG_STATUS_TF4BR0_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14257 #define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
kadonotakashi 0:8fdf9a60065b 14258 #define TRNG_STATUS_TF4BR1_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14259 #define TRNG_STATUS_TF4BR1_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14260 #define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
kadonotakashi 0:8fdf9a60065b 14261 #define TRNG_STATUS_TF5BR0_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 14262 #define TRNG_STATUS_TF5BR0_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 14263 #define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
kadonotakashi 0:8fdf9a60065b 14264 #define TRNG_STATUS_TF5BR1_MASK (0x200U)
kadonotakashi 0:8fdf9a60065b 14265 #define TRNG_STATUS_TF5BR1_SHIFT (9U)
kadonotakashi 0:8fdf9a60065b 14266 #define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
kadonotakashi 0:8fdf9a60065b 14267 #define TRNG_STATUS_TF6PBR0_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 14268 #define TRNG_STATUS_TF6PBR0_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 14269 #define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
kadonotakashi 0:8fdf9a60065b 14270 #define TRNG_STATUS_TF6PBR1_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 14271 #define TRNG_STATUS_TF6PBR1_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 14272 #define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
kadonotakashi 0:8fdf9a60065b 14273 #define TRNG_STATUS_TFSB_MASK (0x1000U)
kadonotakashi 0:8fdf9a60065b 14274 #define TRNG_STATUS_TFSB_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 14275 #define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
kadonotakashi 0:8fdf9a60065b 14276 #define TRNG_STATUS_TFLR_MASK (0x2000U)
kadonotakashi 0:8fdf9a60065b 14277 #define TRNG_STATUS_TFLR_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 14278 #define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
kadonotakashi 0:8fdf9a60065b 14279 #define TRNG_STATUS_TFP_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 14280 #define TRNG_STATUS_TFP_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 14281 #define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
kadonotakashi 0:8fdf9a60065b 14282 #define TRNG_STATUS_TFMB_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 14283 #define TRNG_STATUS_TFMB_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 14284 #define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
kadonotakashi 0:8fdf9a60065b 14285 #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
kadonotakashi 0:8fdf9a60065b 14286 #define TRNG_STATUS_RETRY_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14287 #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14288
kadonotakashi 0:8fdf9a60065b 14289 /*! @name ENT - RNG TRNG Entropy Read Register */
kadonotakashi 0:8fdf9a60065b 14290 #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
kadonotakashi 0:8fdf9a60065b 14291 #define TRNG_ENT_ENT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14292 #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
kadonotakashi 0:8fdf9a60065b 14293
kadonotakashi 0:8fdf9a60065b 14294 /* The count of TRNG_ENT */
kadonotakashi 0:8fdf9a60065b 14295 #define TRNG_ENT_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 14296
kadonotakashi 0:8fdf9a60065b 14297 /*! @name PKRCNT10 - RNG Statistical Check Poker Count 1 and 0 Register */
kadonotakashi 0:8fdf9a60065b 14298 #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14299 #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14300 #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14301 #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14302 #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14303 #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14304
kadonotakashi 0:8fdf9a60065b 14305 /*! @name PKRCNT32 - RNG Statistical Check Poker Count 3 and 2 Register */
kadonotakashi 0:8fdf9a60065b 14306 #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14307 #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14308 #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14309 #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14310 #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14311 #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14312
kadonotakashi 0:8fdf9a60065b 14313 /*! @name PKRCNT54 - RNG Statistical Check Poker Count 5 and 4 Register */
kadonotakashi 0:8fdf9a60065b 14314 #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14315 #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14316 #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14317 #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14318 #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14319 #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14320
kadonotakashi 0:8fdf9a60065b 14321 /*! @name PKRCNT76 - RNG Statistical Check Poker Count 7 and 6 Register */
kadonotakashi 0:8fdf9a60065b 14322 #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14323 #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14324 #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14325 #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14326 #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14327 #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14328
kadonotakashi 0:8fdf9a60065b 14329 /*! @name PKRCNT98 - RNG Statistical Check Poker Count 9 and 8 Register */
kadonotakashi 0:8fdf9a60065b 14330 #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14331 #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14332 #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14333 #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14334 #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14335 #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14336
kadonotakashi 0:8fdf9a60065b 14337 /*! @name PKRCNTBA - RNG Statistical Check Poker Count B and A Register */
kadonotakashi 0:8fdf9a60065b 14338 #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14339 #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14340 #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14341 #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14342 #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14343 #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14344
kadonotakashi 0:8fdf9a60065b 14345 /*! @name PKRCNTDC - RNG Statistical Check Poker Count D and C Register */
kadonotakashi 0:8fdf9a60065b 14346 #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14347 #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14348 #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14349 #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14350 #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14351 #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14352
kadonotakashi 0:8fdf9a60065b 14353 /*! @name PKRCNTFE - RNG Statistical Check Poker Count F and E Register */
kadonotakashi 0:8fdf9a60065b 14354 #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14355 #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14356 #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14357 #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14358 #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14359 #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
kadonotakashi 0:8fdf9a60065b 14360
kadonotakashi 0:8fdf9a60065b 14361 /*! @name SEC_CFG - RNG Security Configuration Register */
kadonotakashi 0:8fdf9a60065b 14362 #define TRNG_SEC_CFG_SH0_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14363 #define TRNG_SEC_CFG_SH0_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14364 #define TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)
kadonotakashi 0:8fdf9a60065b 14365 #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14366 #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14367 #define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
kadonotakashi 0:8fdf9a60065b 14368 #define TRNG_SEC_CFG_SK_VAL_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14369 #define TRNG_SEC_CFG_SK_VAL_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14370 #define TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)
kadonotakashi 0:8fdf9a60065b 14371
kadonotakashi 0:8fdf9a60065b 14372 /*! @name INT_CTRL - RNG Interrupt Control Register */
kadonotakashi 0:8fdf9a60065b 14373 #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14374 #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14375 #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
kadonotakashi 0:8fdf9a60065b 14376 #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14377 #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14378 #define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
kadonotakashi 0:8fdf9a60065b 14379 #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14380 #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14381 #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
kadonotakashi 0:8fdf9a60065b 14382 #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
kadonotakashi 0:8fdf9a60065b 14383 #define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14384 #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
kadonotakashi 0:8fdf9a60065b 14385
kadonotakashi 0:8fdf9a60065b 14386 /*! @name INT_MASK - RNG Mask Register */
kadonotakashi 0:8fdf9a60065b 14387 #define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14388 #define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14389 #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
kadonotakashi 0:8fdf9a60065b 14390 #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14391 #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14392 #define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
kadonotakashi 0:8fdf9a60065b 14393 #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14394 #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14395 #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
kadonotakashi 0:8fdf9a60065b 14396
kadonotakashi 0:8fdf9a60065b 14397 /*! @name INT_STATUS - RNG Interrupt Status Register */
kadonotakashi 0:8fdf9a60065b 14398 #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14399 #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14400 #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
kadonotakashi 0:8fdf9a60065b 14401 #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14402 #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14403 #define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
kadonotakashi 0:8fdf9a60065b 14404 #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14405 #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14406 #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
kadonotakashi 0:8fdf9a60065b 14407
kadonotakashi 0:8fdf9a60065b 14408 /*! @name VID1 - RNG Version ID Register (MS) */
kadonotakashi 0:8fdf9a60065b 14409 #define TRNG_VID1_RNG_MIN_REV_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 14410 #define TRNG_VID1_RNG_MIN_REV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14411 #define TRNG_VID1_RNG_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_MIN_REV_SHIFT)) & TRNG_VID1_RNG_MIN_REV_MASK)
kadonotakashi 0:8fdf9a60065b 14412 #define TRNG_VID1_RNG_MAJ_REV_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 14413 #define TRNG_VID1_RNG_MAJ_REV_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 14414 #define TRNG_VID1_RNG_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_MAJ_REV_SHIFT)) & TRNG_VID1_RNG_MAJ_REV_MASK)
kadonotakashi 0:8fdf9a60065b 14415 #define TRNG_VID1_RNG_IP_ID_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14416 #define TRNG_VID1_RNG_IP_ID_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14417 #define TRNG_VID1_RNG_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_IP_ID_SHIFT)) & TRNG_VID1_RNG_IP_ID_MASK)
kadonotakashi 0:8fdf9a60065b 14418
kadonotakashi 0:8fdf9a60065b 14419 /*! @name VID2 - RNG Version ID Register (LS) */
kadonotakashi 0:8fdf9a60065b 14420 #define TRNG_VID2_RNG_CONFIG_OPT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 14421 #define TRNG_VID2_RNG_CONFIG_OPT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14422 #define TRNG_VID2_RNG_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_CONFIG_OPT_SHIFT)) & TRNG_VID2_RNG_CONFIG_OPT_MASK)
kadonotakashi 0:8fdf9a60065b 14423 #define TRNG_VID2_RNG_ECO_REV_MASK (0xFF00U)
kadonotakashi 0:8fdf9a60065b 14424 #define TRNG_VID2_RNG_ECO_REV_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 14425 #define TRNG_VID2_RNG_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_ECO_REV_SHIFT)) & TRNG_VID2_RNG_ECO_REV_MASK)
kadonotakashi 0:8fdf9a60065b 14426 #define TRNG_VID2_RNG_INTG_OPT_MASK (0xFF0000U)
kadonotakashi 0:8fdf9a60065b 14427 #define TRNG_VID2_RNG_INTG_OPT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14428 #define TRNG_VID2_RNG_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_INTG_OPT_SHIFT)) & TRNG_VID2_RNG_INTG_OPT_MASK)
kadonotakashi 0:8fdf9a60065b 14429 #define TRNG_VID2_RNG_ERA_MASK (0xFF000000U)
kadonotakashi 0:8fdf9a60065b 14430 #define TRNG_VID2_RNG_ERA_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 14431 #define TRNG_VID2_RNG_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_ERA_SHIFT)) & TRNG_VID2_RNG_ERA_MASK)
kadonotakashi 0:8fdf9a60065b 14432
kadonotakashi 0:8fdf9a60065b 14433
kadonotakashi 0:8fdf9a60065b 14434 /*!
kadonotakashi 0:8fdf9a60065b 14435 * @}
kadonotakashi 0:8fdf9a60065b 14436 */ /* end of group TRNG_Register_Masks */
kadonotakashi 0:8fdf9a60065b 14437
kadonotakashi 0:8fdf9a60065b 14438
kadonotakashi 0:8fdf9a60065b 14439 /* TRNG - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 14440 /** Peripheral TRNG0 base address */
kadonotakashi 0:8fdf9a60065b 14441 #define TRNG0_BASE (0x400A0000u)
kadonotakashi 0:8fdf9a60065b 14442 /** Peripheral TRNG0 base pointer */
kadonotakashi 0:8fdf9a60065b 14443 #define TRNG0 ((TRNG_Type *)TRNG0_BASE)
kadonotakashi 0:8fdf9a60065b 14444 /** Array initializer of TRNG peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 14445 #define TRNG_BASE_ADDRS { TRNG0_BASE }
kadonotakashi 0:8fdf9a60065b 14446 /** Array initializer of TRNG peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 14447 #define TRNG_BASE_PTRS { TRNG0 }
kadonotakashi 0:8fdf9a60065b 14448 /** Interrupt vectors for the TRNG peripheral type */
kadonotakashi 0:8fdf9a60065b 14449 #define TRNG_IRQS { TRNG0_IRQn }
kadonotakashi 0:8fdf9a60065b 14450
kadonotakashi 0:8fdf9a60065b 14451 /*!
kadonotakashi 0:8fdf9a60065b 14452 * @}
kadonotakashi 0:8fdf9a60065b 14453 */ /* end of group TRNG_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 14454
kadonotakashi 0:8fdf9a60065b 14455
kadonotakashi 0:8fdf9a60065b 14456 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 14457 -- TSI Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 14458 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 14459
kadonotakashi 0:8fdf9a60065b 14460 /*!
kadonotakashi 0:8fdf9a60065b 14461 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 14462 * @{
kadonotakashi 0:8fdf9a60065b 14463 */
kadonotakashi 0:8fdf9a60065b 14464
kadonotakashi 0:8fdf9a60065b 14465 /** TSI - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 14466 typedef struct {
kadonotakashi 0:8fdf9a60065b 14467 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 14468 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 14469 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 14470 } TSI_Type;
kadonotakashi 0:8fdf9a60065b 14471
kadonotakashi 0:8fdf9a60065b 14472 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 14473 -- TSI Register Masks
kadonotakashi 0:8fdf9a60065b 14474 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 14475
kadonotakashi 0:8fdf9a60065b 14476 /*!
kadonotakashi 0:8fdf9a60065b 14477 * @addtogroup TSI_Register_Masks TSI Register Masks
kadonotakashi 0:8fdf9a60065b 14478 * @{
kadonotakashi 0:8fdf9a60065b 14479 */
kadonotakashi 0:8fdf9a60065b 14480
kadonotakashi 0:8fdf9a60065b 14481 /*! @name GENCS - TSI General Control and Status Register */
kadonotakashi 0:8fdf9a60065b 14482 #define TSI_GENCS_EOSDMEO_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14483 #define TSI_GENCS_EOSDMEO_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14484 #define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
kadonotakashi 0:8fdf9a60065b 14485 #define TSI_GENCS_CURSW_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14486 #define TSI_GENCS_CURSW_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14487 #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
kadonotakashi 0:8fdf9a60065b 14488 #define TSI_GENCS_EOSF_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14489 #define TSI_GENCS_EOSF_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14490 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
kadonotakashi 0:8fdf9a60065b 14491 #define TSI_GENCS_SCNIP_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14492 #define TSI_GENCS_SCNIP_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14493 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
kadonotakashi 0:8fdf9a60065b 14494 #define TSI_GENCS_STM_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14495 #define TSI_GENCS_STM_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14496 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
kadonotakashi 0:8fdf9a60065b 14497 #define TSI_GENCS_STPE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14498 #define TSI_GENCS_STPE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14499 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
kadonotakashi 0:8fdf9a60065b 14500 #define TSI_GENCS_TSIIEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14501 #define TSI_GENCS_TSIIEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14502 #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
kadonotakashi 0:8fdf9a60065b 14503 #define TSI_GENCS_TSIEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14504 #define TSI_GENCS_TSIEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14505 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
kadonotakashi 0:8fdf9a60065b 14506 #define TSI_GENCS_NSCN_MASK (0x1F00U)
kadonotakashi 0:8fdf9a60065b 14507 #define TSI_GENCS_NSCN_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 14508 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
kadonotakashi 0:8fdf9a60065b 14509 #define TSI_GENCS_PS_MASK (0xE000U)
kadonotakashi 0:8fdf9a60065b 14510 #define TSI_GENCS_PS_SHIFT (13U)
kadonotakashi 0:8fdf9a60065b 14511 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
kadonotakashi 0:8fdf9a60065b 14512 #define TSI_GENCS_EXTCHRG_MASK (0x70000U)
kadonotakashi 0:8fdf9a60065b 14513 #define TSI_GENCS_EXTCHRG_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14514 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
kadonotakashi 0:8fdf9a60065b 14515 #define TSI_GENCS_DVOLT_MASK (0x180000U)
kadonotakashi 0:8fdf9a60065b 14516 #define TSI_GENCS_DVOLT_SHIFT (19U)
kadonotakashi 0:8fdf9a60065b 14517 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
kadonotakashi 0:8fdf9a60065b 14518 #define TSI_GENCS_REFCHRG_MASK (0xE00000U)
kadonotakashi 0:8fdf9a60065b 14519 #define TSI_GENCS_REFCHRG_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 14520 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
kadonotakashi 0:8fdf9a60065b 14521 #define TSI_GENCS_MODE_MASK (0xF000000U)
kadonotakashi 0:8fdf9a60065b 14522 #define TSI_GENCS_MODE_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 14523 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
kadonotakashi 0:8fdf9a60065b 14524 #define TSI_GENCS_ESOR_MASK (0x10000000U)
kadonotakashi 0:8fdf9a60065b 14525 #define TSI_GENCS_ESOR_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 14526 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
kadonotakashi 0:8fdf9a60065b 14527 #define TSI_GENCS_OUTRGF_MASK (0x80000000U)
kadonotakashi 0:8fdf9a60065b 14528 #define TSI_GENCS_OUTRGF_SHIFT (31U)
kadonotakashi 0:8fdf9a60065b 14529 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
kadonotakashi 0:8fdf9a60065b 14530
kadonotakashi 0:8fdf9a60065b 14531 /*! @name DATA - TSI DATA Register */
kadonotakashi 0:8fdf9a60065b 14532 #define TSI_DATA_TSICNT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14533 #define TSI_DATA_TSICNT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14534 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
kadonotakashi 0:8fdf9a60065b 14535 #define TSI_DATA_SWTS_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 14536 #define TSI_DATA_SWTS_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 14537 #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
kadonotakashi 0:8fdf9a60065b 14538 #define TSI_DATA_DMAEN_MASK (0x800000U)
kadonotakashi 0:8fdf9a60065b 14539 #define TSI_DATA_DMAEN_SHIFT (23U)
kadonotakashi 0:8fdf9a60065b 14540 #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
kadonotakashi 0:8fdf9a60065b 14541 #define TSI_DATA_TSICH_MASK (0xF0000000U)
kadonotakashi 0:8fdf9a60065b 14542 #define TSI_DATA_TSICH_SHIFT (28U)
kadonotakashi 0:8fdf9a60065b 14543 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
kadonotakashi 0:8fdf9a60065b 14544
kadonotakashi 0:8fdf9a60065b 14545 /*! @name TSHD - TSI Threshold Register */
kadonotakashi 0:8fdf9a60065b 14546 #define TSI_TSHD_THRESL_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 14547 #define TSI_TSHD_THRESL_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14548 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
kadonotakashi 0:8fdf9a60065b 14549 #define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
kadonotakashi 0:8fdf9a60065b 14550 #define TSI_TSHD_THRESH_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 14551 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
kadonotakashi 0:8fdf9a60065b 14552
kadonotakashi 0:8fdf9a60065b 14553
kadonotakashi 0:8fdf9a60065b 14554 /*!
kadonotakashi 0:8fdf9a60065b 14555 * @}
kadonotakashi 0:8fdf9a60065b 14556 */ /* end of group TSI_Register_Masks */
kadonotakashi 0:8fdf9a60065b 14557
kadonotakashi 0:8fdf9a60065b 14558
kadonotakashi 0:8fdf9a60065b 14559 /* TSI - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 14560 /** Peripheral TSI0 base address */
kadonotakashi 0:8fdf9a60065b 14561 #define TSI0_BASE (0x40045000u)
kadonotakashi 0:8fdf9a60065b 14562 /** Peripheral TSI0 base pointer */
kadonotakashi 0:8fdf9a60065b 14563 #define TSI0 ((TSI_Type *)TSI0_BASE)
kadonotakashi 0:8fdf9a60065b 14564 /** Array initializer of TSI peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 14565 #define TSI_BASE_ADDRS { TSI0_BASE }
kadonotakashi 0:8fdf9a60065b 14566 /** Array initializer of TSI peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 14567 #define TSI_BASE_PTRS { TSI0 }
kadonotakashi 0:8fdf9a60065b 14568 /** Interrupt vectors for the TSI peripheral type */
kadonotakashi 0:8fdf9a60065b 14569 #define TSI_IRQS { TSI0_IRQn }
kadonotakashi 0:8fdf9a60065b 14570
kadonotakashi 0:8fdf9a60065b 14571 /*!
kadonotakashi 0:8fdf9a60065b 14572 * @}
kadonotakashi 0:8fdf9a60065b 14573 */ /* end of group TSI_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 14574
kadonotakashi 0:8fdf9a60065b 14575
kadonotakashi 0:8fdf9a60065b 14576 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 14577 -- USB Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 14578 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 14579
kadonotakashi 0:8fdf9a60065b 14580 /*!
kadonotakashi 0:8fdf9a60065b 14581 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 14582 * @{
kadonotakashi 0:8fdf9a60065b 14583 */
kadonotakashi 0:8fdf9a60065b 14584
kadonotakashi 0:8fdf9a60065b 14585 /** USB - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 14586 typedef struct {
kadonotakashi 0:8fdf9a60065b 14587 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 14588 uint8_t RESERVED_0[3];
kadonotakashi 0:8fdf9a60065b 14589 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 14590 uint8_t RESERVED_1[3];
kadonotakashi 0:8fdf9a60065b 14591 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 14592 uint8_t RESERVED_2[3];
kadonotakashi 0:8fdf9a60065b 14593 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 14594 uint8_t RESERVED_3[3];
kadonotakashi 0:8fdf9a60065b 14595 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 14596 uint8_t RESERVED_4[3];
kadonotakashi 0:8fdf9a60065b 14597 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 14598 uint8_t RESERVED_5[3];
kadonotakashi 0:8fdf9a60065b 14599 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 14600 uint8_t RESERVED_6[3];
kadonotakashi 0:8fdf9a60065b 14601 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
kadonotakashi 0:8fdf9a60065b 14602 uint8_t RESERVED_7[99];
kadonotakashi 0:8fdf9a60065b 14603 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
kadonotakashi 0:8fdf9a60065b 14604 uint8_t RESERVED_8[3];
kadonotakashi 0:8fdf9a60065b 14605 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
kadonotakashi 0:8fdf9a60065b 14606 uint8_t RESERVED_9[3];
kadonotakashi 0:8fdf9a60065b 14607 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
kadonotakashi 0:8fdf9a60065b 14608 uint8_t RESERVED_10[3];
kadonotakashi 0:8fdf9a60065b 14609 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
kadonotakashi 0:8fdf9a60065b 14610 uint8_t RESERVED_11[3];
kadonotakashi 0:8fdf9a60065b 14611 __I uint8_t STAT; /**< Status register, offset: 0x90 */
kadonotakashi 0:8fdf9a60065b 14612 uint8_t RESERVED_12[3];
kadonotakashi 0:8fdf9a60065b 14613 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
kadonotakashi 0:8fdf9a60065b 14614 uint8_t RESERVED_13[3];
kadonotakashi 0:8fdf9a60065b 14615 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
kadonotakashi 0:8fdf9a60065b 14616 uint8_t RESERVED_14[3];
kadonotakashi 0:8fdf9a60065b 14617 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
kadonotakashi 0:8fdf9a60065b 14618 uint8_t RESERVED_15[3];
kadonotakashi 0:8fdf9a60065b 14619 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
kadonotakashi 0:8fdf9a60065b 14620 uint8_t RESERVED_16[3];
kadonotakashi 0:8fdf9a60065b 14621 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
kadonotakashi 0:8fdf9a60065b 14622 uint8_t RESERVED_17[3];
kadonotakashi 0:8fdf9a60065b 14623 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
kadonotakashi 0:8fdf9a60065b 14624 uint8_t RESERVED_18[3];
kadonotakashi 0:8fdf9a60065b 14625 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
kadonotakashi 0:8fdf9a60065b 14626 uint8_t RESERVED_19[3];
kadonotakashi 0:8fdf9a60065b 14627 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
kadonotakashi 0:8fdf9a60065b 14628 uint8_t RESERVED_20[3];
kadonotakashi 0:8fdf9a60065b 14629 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
kadonotakashi 0:8fdf9a60065b 14630 uint8_t RESERVED_21[11];
kadonotakashi 0:8fdf9a60065b 14631 struct { /* offset: 0xC0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 14632 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
kadonotakashi 0:8fdf9a60065b 14633 uint8_t RESERVED_0[3];
kadonotakashi 0:8fdf9a60065b 14634 } ENDPOINT[16];
kadonotakashi 0:8fdf9a60065b 14635 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
kadonotakashi 0:8fdf9a60065b 14636 uint8_t RESERVED_22[3];
kadonotakashi 0:8fdf9a60065b 14637 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
kadonotakashi 0:8fdf9a60065b 14638 uint8_t RESERVED_23[3];
kadonotakashi 0:8fdf9a60065b 14639 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
kadonotakashi 0:8fdf9a60065b 14640 uint8_t RESERVED_24[3];
kadonotakashi 0:8fdf9a60065b 14641 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
kadonotakashi 0:8fdf9a60065b 14642 uint8_t RESERVED_25[7];
kadonotakashi 0:8fdf9a60065b 14643 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
kadonotakashi 0:8fdf9a60065b 14644 uint8_t RESERVED_26[23];
kadonotakashi 0:8fdf9a60065b 14645 __IO uint8_t MISCCTRL; /**< Miscellaneous Control register, offset: 0x12C */
kadonotakashi 0:8fdf9a60065b 14646 uint8_t RESERVED_27[19];
kadonotakashi 0:8fdf9a60065b 14647 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
kadonotakashi 0:8fdf9a60065b 14648 uint8_t RESERVED_28[3];
kadonotakashi 0:8fdf9a60065b 14649 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
kadonotakashi 0:8fdf9a60065b 14650 uint8_t RESERVED_29[15];
kadonotakashi 0:8fdf9a60065b 14651 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
kadonotakashi 0:8fdf9a60065b 14652 uint8_t RESERVED_30[7];
kadonotakashi 0:8fdf9a60065b 14653 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
kadonotakashi 0:8fdf9a60065b 14654 } USB_Type;
kadonotakashi 0:8fdf9a60065b 14655
kadonotakashi 0:8fdf9a60065b 14656 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 14657 -- USB Register Masks
kadonotakashi 0:8fdf9a60065b 14658 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 14659
kadonotakashi 0:8fdf9a60065b 14660 /*!
kadonotakashi 0:8fdf9a60065b 14661 * @addtogroup USB_Register_Masks USB Register Masks
kadonotakashi 0:8fdf9a60065b 14662 * @{
kadonotakashi 0:8fdf9a60065b 14663 */
kadonotakashi 0:8fdf9a60065b 14664
kadonotakashi 0:8fdf9a60065b 14665 /*! @name PERID - Peripheral ID register */
kadonotakashi 0:8fdf9a60065b 14666 #define USB_PERID_ID_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 14667 #define USB_PERID_ID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14668 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
kadonotakashi 0:8fdf9a60065b 14669
kadonotakashi 0:8fdf9a60065b 14670 /*! @name IDCOMP - Peripheral ID Complement register */
kadonotakashi 0:8fdf9a60065b 14671 #define USB_IDCOMP_NID_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 14672 #define USB_IDCOMP_NID_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14673 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
kadonotakashi 0:8fdf9a60065b 14674
kadonotakashi 0:8fdf9a60065b 14675 /*! @name REV - Peripheral Revision register */
kadonotakashi 0:8fdf9a60065b 14676 #define USB_REV_REV_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 14677 #define USB_REV_REV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14678 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
kadonotakashi 0:8fdf9a60065b 14679
kadonotakashi 0:8fdf9a60065b 14680 /*! @name ADDINFO - Peripheral Additional Info register */
kadonotakashi 0:8fdf9a60065b 14681 #define USB_ADDINFO_IEHOST_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14682 #define USB_ADDINFO_IEHOST_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14683 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
kadonotakashi 0:8fdf9a60065b 14684
kadonotakashi 0:8fdf9a60065b 14685 /*! @name OTGISTAT - OTG Interrupt Status register */
kadonotakashi 0:8fdf9a60065b 14686 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14687 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14688 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
kadonotakashi 0:8fdf9a60065b 14689 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14690 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14691 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
kadonotakashi 0:8fdf9a60065b 14692 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14693 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14694 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
kadonotakashi 0:8fdf9a60065b 14695 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14696 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14697 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
kadonotakashi 0:8fdf9a60065b 14698 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14699 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14700 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
kadonotakashi 0:8fdf9a60065b 14701 #define USB_OTGISTAT_IDCHG_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14702 #define USB_OTGISTAT_IDCHG_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14703 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
kadonotakashi 0:8fdf9a60065b 14704
kadonotakashi 0:8fdf9a60065b 14705 /*! @name OTGICR - OTG Interrupt Control register */
kadonotakashi 0:8fdf9a60065b 14706 #define USB_OTGICR_AVBUSEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14707 #define USB_OTGICR_AVBUSEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14708 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
kadonotakashi 0:8fdf9a60065b 14709 #define USB_OTGICR_BSESSEN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14710 #define USB_OTGICR_BSESSEN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14711 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
kadonotakashi 0:8fdf9a60065b 14712 #define USB_OTGICR_SESSVLDEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14713 #define USB_OTGICR_SESSVLDEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14714 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
kadonotakashi 0:8fdf9a60065b 14715 #define USB_OTGICR_LINESTATEEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14716 #define USB_OTGICR_LINESTATEEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14717 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
kadonotakashi 0:8fdf9a60065b 14718 #define USB_OTGICR_ONEMSECEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14719 #define USB_OTGICR_ONEMSECEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14720 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
kadonotakashi 0:8fdf9a60065b 14721 #define USB_OTGICR_IDEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14722 #define USB_OTGICR_IDEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14723 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
kadonotakashi 0:8fdf9a60065b 14724
kadonotakashi 0:8fdf9a60065b 14725 /*! @name OTGSTAT - OTG Status register */
kadonotakashi 0:8fdf9a60065b 14726 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14727 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14728 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
kadonotakashi 0:8fdf9a60065b 14729 #define USB_OTGSTAT_BSESSEND_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14730 #define USB_OTGSTAT_BSESSEND_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14731 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
kadonotakashi 0:8fdf9a60065b 14732 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14733 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14734 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
kadonotakashi 0:8fdf9a60065b 14735 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14736 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14737 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
kadonotakashi 0:8fdf9a60065b 14738 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14739 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14740 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
kadonotakashi 0:8fdf9a60065b 14741 #define USB_OTGSTAT_ID_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14742 #define USB_OTGSTAT_ID_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14743 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
kadonotakashi 0:8fdf9a60065b 14744
kadonotakashi 0:8fdf9a60065b 14745 /*! @name OTGCTL - OTG Control register */
kadonotakashi 0:8fdf9a60065b 14746 #define USB_OTGCTL_OTGEN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14747 #define USB_OTGCTL_OTGEN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14748 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
kadonotakashi 0:8fdf9a60065b 14749 #define USB_OTGCTL_DMLOW_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14750 #define USB_OTGCTL_DMLOW_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14751 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
kadonotakashi 0:8fdf9a60065b 14752 #define USB_OTGCTL_DPLOW_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14753 #define USB_OTGCTL_DPLOW_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14754 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
kadonotakashi 0:8fdf9a60065b 14755 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14756 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14757 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
kadonotakashi 0:8fdf9a60065b 14758
kadonotakashi 0:8fdf9a60065b 14759 /*! @name ISTAT - Interrupt Status register */
kadonotakashi 0:8fdf9a60065b 14760 #define USB_ISTAT_USBRST_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14761 #define USB_ISTAT_USBRST_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14762 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
kadonotakashi 0:8fdf9a60065b 14763 #define USB_ISTAT_ERROR_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14764 #define USB_ISTAT_ERROR_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14765 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
kadonotakashi 0:8fdf9a60065b 14766 #define USB_ISTAT_SOFTOK_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14767 #define USB_ISTAT_SOFTOK_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14768 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
kadonotakashi 0:8fdf9a60065b 14769 #define USB_ISTAT_TOKDNE_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14770 #define USB_ISTAT_TOKDNE_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14771 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
kadonotakashi 0:8fdf9a60065b 14772 #define USB_ISTAT_SLEEP_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14773 #define USB_ISTAT_SLEEP_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14774 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
kadonotakashi 0:8fdf9a60065b 14775 #define USB_ISTAT_RESUME_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14776 #define USB_ISTAT_RESUME_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14777 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
kadonotakashi 0:8fdf9a60065b 14778 #define USB_ISTAT_ATTACH_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14779 #define USB_ISTAT_ATTACH_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14780 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
kadonotakashi 0:8fdf9a60065b 14781 #define USB_ISTAT_STALL_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14782 #define USB_ISTAT_STALL_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14783 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
kadonotakashi 0:8fdf9a60065b 14784
kadonotakashi 0:8fdf9a60065b 14785 /*! @name INTEN - Interrupt Enable register */
kadonotakashi 0:8fdf9a60065b 14786 #define USB_INTEN_USBRSTEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14787 #define USB_INTEN_USBRSTEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14788 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
kadonotakashi 0:8fdf9a60065b 14789 #define USB_INTEN_ERROREN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14790 #define USB_INTEN_ERROREN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14791 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
kadonotakashi 0:8fdf9a60065b 14792 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14793 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14794 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
kadonotakashi 0:8fdf9a60065b 14795 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14796 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14797 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
kadonotakashi 0:8fdf9a60065b 14798 #define USB_INTEN_SLEEPEN_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14799 #define USB_INTEN_SLEEPEN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14800 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
kadonotakashi 0:8fdf9a60065b 14801 #define USB_INTEN_RESUMEEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14802 #define USB_INTEN_RESUMEEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14803 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
kadonotakashi 0:8fdf9a60065b 14804 #define USB_INTEN_ATTACHEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14805 #define USB_INTEN_ATTACHEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14806 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
kadonotakashi 0:8fdf9a60065b 14807 #define USB_INTEN_STALLEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14808 #define USB_INTEN_STALLEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14809 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
kadonotakashi 0:8fdf9a60065b 14810
kadonotakashi 0:8fdf9a60065b 14811 /*! @name ERRSTAT - Error Interrupt Status register */
kadonotakashi 0:8fdf9a60065b 14812 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14813 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14814 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
kadonotakashi 0:8fdf9a60065b 14815 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14816 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14817 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
kadonotakashi 0:8fdf9a60065b 14818 #define USB_ERRSTAT_CRC16_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14819 #define USB_ERRSTAT_CRC16_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14820 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
kadonotakashi 0:8fdf9a60065b 14821 #define USB_ERRSTAT_DFN8_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14822 #define USB_ERRSTAT_DFN8_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14823 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
kadonotakashi 0:8fdf9a60065b 14824 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14825 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14826 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
kadonotakashi 0:8fdf9a60065b 14827 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14828 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14829 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
kadonotakashi 0:8fdf9a60065b 14830 #define USB_ERRSTAT_OWNERR_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14831 #define USB_ERRSTAT_OWNERR_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14832 #define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
kadonotakashi 0:8fdf9a60065b 14833 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14834 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14835 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
kadonotakashi 0:8fdf9a60065b 14836
kadonotakashi 0:8fdf9a60065b 14837 /*! @name ERREN - Error Interrupt Enable register */
kadonotakashi 0:8fdf9a60065b 14838 #define USB_ERREN_PIDERREN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14839 #define USB_ERREN_PIDERREN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14840 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
kadonotakashi 0:8fdf9a60065b 14841 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14842 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14843 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
kadonotakashi 0:8fdf9a60065b 14844 #define USB_ERREN_CRC16EN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14845 #define USB_ERREN_CRC16EN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14846 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
kadonotakashi 0:8fdf9a60065b 14847 #define USB_ERREN_DFN8EN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14848 #define USB_ERREN_DFN8EN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14849 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
kadonotakashi 0:8fdf9a60065b 14850 #define USB_ERREN_BTOERREN_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14851 #define USB_ERREN_BTOERREN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14852 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
kadonotakashi 0:8fdf9a60065b 14853 #define USB_ERREN_DMAERREN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14854 #define USB_ERREN_DMAERREN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14855 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
kadonotakashi 0:8fdf9a60065b 14856 #define USB_ERREN_OWNERREN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14857 #define USB_ERREN_OWNERREN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14858 #define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
kadonotakashi 0:8fdf9a60065b 14859 #define USB_ERREN_BTSERREN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14860 #define USB_ERREN_BTSERREN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14861 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
kadonotakashi 0:8fdf9a60065b 14862
kadonotakashi 0:8fdf9a60065b 14863 /*! @name STAT - Status register */
kadonotakashi 0:8fdf9a60065b 14864 #define USB_STAT_ODD_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14865 #define USB_STAT_ODD_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14866 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
kadonotakashi 0:8fdf9a60065b 14867 #define USB_STAT_TX_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14868 #define USB_STAT_TX_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14869 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
kadonotakashi 0:8fdf9a60065b 14870 #define USB_STAT_ENDP_MASK (0xF0U)
kadonotakashi 0:8fdf9a60065b 14871 #define USB_STAT_ENDP_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14872 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
kadonotakashi 0:8fdf9a60065b 14873
kadonotakashi 0:8fdf9a60065b 14874 /*! @name CTL - Control register */
kadonotakashi 0:8fdf9a60065b 14875 #define USB_CTL_USBENSOFEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14876 #define USB_CTL_USBENSOFEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14877 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
kadonotakashi 0:8fdf9a60065b 14878 #define USB_CTL_ODDRST_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14879 #define USB_CTL_ODDRST_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14880 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
kadonotakashi 0:8fdf9a60065b 14881 #define USB_CTL_RESUME_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14882 #define USB_CTL_RESUME_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14883 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
kadonotakashi 0:8fdf9a60065b 14884 #define USB_CTL_HOSTMODEEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14885 #define USB_CTL_HOSTMODEEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14886 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
kadonotakashi 0:8fdf9a60065b 14887 #define USB_CTL_RESET_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14888 #define USB_CTL_RESET_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14889 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
kadonotakashi 0:8fdf9a60065b 14890 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14891 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14892 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
kadonotakashi 0:8fdf9a60065b 14893 #define USB_CTL_SE0_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14894 #define USB_CTL_SE0_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14895 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
kadonotakashi 0:8fdf9a60065b 14896 #define USB_CTL_JSTATE_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14897 #define USB_CTL_JSTATE_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14898 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
kadonotakashi 0:8fdf9a60065b 14899
kadonotakashi 0:8fdf9a60065b 14900 /*! @name ADDR - Address register */
kadonotakashi 0:8fdf9a60065b 14901 #define USB_ADDR_ADDR_MASK (0x7FU)
kadonotakashi 0:8fdf9a60065b 14902 #define USB_ADDR_ADDR_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14903 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
kadonotakashi 0:8fdf9a60065b 14904 #define USB_ADDR_LSEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14905 #define USB_ADDR_LSEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14906 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
kadonotakashi 0:8fdf9a60065b 14907
kadonotakashi 0:8fdf9a60065b 14908 /*! @name BDTPAGE1 - BDT Page register 1 */
kadonotakashi 0:8fdf9a60065b 14909 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
kadonotakashi 0:8fdf9a60065b 14910 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14911 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
kadonotakashi 0:8fdf9a60065b 14912
kadonotakashi 0:8fdf9a60065b 14913 /*! @name FRMNUML - Frame Number register Low */
kadonotakashi 0:8fdf9a60065b 14914 #define USB_FRMNUML_FRM_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 14915 #define USB_FRMNUML_FRM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14916 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
kadonotakashi 0:8fdf9a60065b 14917
kadonotakashi 0:8fdf9a60065b 14918 /*! @name FRMNUMH - Frame Number register High */
kadonotakashi 0:8fdf9a60065b 14919 #define USB_FRMNUMH_FRM_MASK (0x7U)
kadonotakashi 0:8fdf9a60065b 14920 #define USB_FRMNUMH_FRM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14921 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
kadonotakashi 0:8fdf9a60065b 14922
kadonotakashi 0:8fdf9a60065b 14923 /*! @name TOKEN - Token register */
kadonotakashi 0:8fdf9a60065b 14924 #define USB_TOKEN_TOKENENDPT_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 14925 #define USB_TOKEN_TOKENENDPT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14926 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
kadonotakashi 0:8fdf9a60065b 14927 #define USB_TOKEN_TOKENPID_MASK (0xF0U)
kadonotakashi 0:8fdf9a60065b 14928 #define USB_TOKEN_TOKENPID_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14929 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
kadonotakashi 0:8fdf9a60065b 14930
kadonotakashi 0:8fdf9a60065b 14931 /*! @name SOFTHLD - SOF Threshold register */
kadonotakashi 0:8fdf9a60065b 14932 #define USB_SOFTHLD_CNT_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 14933 #define USB_SOFTHLD_CNT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14934 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
kadonotakashi 0:8fdf9a60065b 14935
kadonotakashi 0:8fdf9a60065b 14936 /*! @name BDTPAGE2 - BDT Page Register 2 */
kadonotakashi 0:8fdf9a60065b 14937 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 14938 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14939 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
kadonotakashi 0:8fdf9a60065b 14940
kadonotakashi 0:8fdf9a60065b 14941 /*! @name BDTPAGE3 - BDT Page Register 3 */
kadonotakashi 0:8fdf9a60065b 14942 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 14943 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14944 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
kadonotakashi 0:8fdf9a60065b 14945
kadonotakashi 0:8fdf9a60065b 14946 /*! @name ENDPT - Endpoint Control register */
kadonotakashi 0:8fdf9a60065b 14947 #define USB_ENDPT_EPHSHK_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 14948 #define USB_ENDPT_EPHSHK_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 14949 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
kadonotakashi 0:8fdf9a60065b 14950 #define USB_ENDPT_EPSTALL_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 14951 #define USB_ENDPT_EPSTALL_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 14952 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
kadonotakashi 0:8fdf9a60065b 14953 #define USB_ENDPT_EPTXEN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 14954 #define USB_ENDPT_EPTXEN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 14955 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
kadonotakashi 0:8fdf9a60065b 14956 #define USB_ENDPT_EPRXEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 14957 #define USB_ENDPT_EPRXEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 14958 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
kadonotakashi 0:8fdf9a60065b 14959 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14960 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14961 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
kadonotakashi 0:8fdf9a60065b 14962 #define USB_ENDPT_RETRYDIS_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14963 #define USB_ENDPT_RETRYDIS_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14964 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
kadonotakashi 0:8fdf9a60065b 14965 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14966 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14967 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
kadonotakashi 0:8fdf9a60065b 14968
kadonotakashi 0:8fdf9a60065b 14969 /* The count of USB_ENDPT */
kadonotakashi 0:8fdf9a60065b 14970 #define USB_ENDPT_COUNT (16U)
kadonotakashi 0:8fdf9a60065b 14971
kadonotakashi 0:8fdf9a60065b 14972 /*! @name USBCTRL - USB Control register */
kadonotakashi 0:8fdf9a60065b 14973 #define USB_USBCTRL_UARTSEL_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14974 #define USB_USBCTRL_UARTSEL_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14975 #define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
kadonotakashi 0:8fdf9a60065b 14976 #define USB_USBCTRL_UARTCHLS_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 14977 #define USB_USBCTRL_UARTCHLS_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 14978 #define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
kadonotakashi 0:8fdf9a60065b 14979 #define USB_USBCTRL_PDE_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14980 #define USB_USBCTRL_PDE_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14981 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
kadonotakashi 0:8fdf9a60065b 14982 #define USB_USBCTRL_SUSP_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14983 #define USB_USBCTRL_SUSP_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14984 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
kadonotakashi 0:8fdf9a60065b 14985
kadonotakashi 0:8fdf9a60065b 14986 /*! @name OBSERVE - USB OTG Observe register */
kadonotakashi 0:8fdf9a60065b 14987 #define USB_OBSERVE_DMPD_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14988 #define USB_OBSERVE_DMPD_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 14989 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
kadonotakashi 0:8fdf9a60065b 14990 #define USB_OBSERVE_DPPD_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 14991 #define USB_OBSERVE_DPPD_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 14992 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
kadonotakashi 0:8fdf9a60065b 14993 #define USB_OBSERVE_DPPU_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 14994 #define USB_OBSERVE_DPPU_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 14995 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
kadonotakashi 0:8fdf9a60065b 14996
kadonotakashi 0:8fdf9a60065b 14997 /*! @name CONTROL - USB OTG Control register */
kadonotakashi 0:8fdf9a60065b 14998 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 14999 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 15000 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
kadonotakashi 0:8fdf9a60065b 15001
kadonotakashi 0:8fdf9a60065b 15002 /*! @name USBTRC0 - USB Transceiver Control register 0 */
kadonotakashi 0:8fdf9a60065b 15003 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 15004 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15005 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
kadonotakashi 0:8fdf9a60065b 15006 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 15007 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 15008 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
kadonotakashi 0:8fdf9a60065b 15009 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 15010 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 15011 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
kadonotakashi 0:8fdf9a60065b 15012 #define USB_USBTRC0_VREDG_DET_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 15013 #define USB_USBTRC0_VREDG_DET_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 15014 #define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
kadonotakashi 0:8fdf9a60065b 15015 #define USB_USBTRC0_VFEDG_DET_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 15016 #define USB_USBTRC0_VFEDG_DET_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 15017 #define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
kadonotakashi 0:8fdf9a60065b 15018 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 15019 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 15020 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
kadonotakashi 0:8fdf9a60065b 15021 #define USB_USBTRC0_USBRESET_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 15022 #define USB_USBTRC0_USBRESET_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 15023 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
kadonotakashi 0:8fdf9a60065b 15024
kadonotakashi 0:8fdf9a60065b 15025 /*! @name USBFRMADJUST - Frame Adjust Register */
kadonotakashi 0:8fdf9a60065b 15026 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
kadonotakashi 0:8fdf9a60065b 15027 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15028 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
kadonotakashi 0:8fdf9a60065b 15029
kadonotakashi 0:8fdf9a60065b 15030 /*! @name MISCCTRL - Miscellaneous Control register */
kadonotakashi 0:8fdf9a60065b 15031 #define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 15032 #define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15033 #define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
kadonotakashi 0:8fdf9a60065b 15034 #define USB_MISCCTRL_SOFBUSSET_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 15035 #define USB_MISCCTRL_SOFBUSSET_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 15036 #define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
kadonotakashi 0:8fdf9a60065b 15037 #define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 15038 #define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 15039 #define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
kadonotakashi 0:8fdf9a60065b 15040 #define USB_MISCCTRL_VREDG_EN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 15041 #define USB_MISCCTRL_VREDG_EN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 15042 #define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
kadonotakashi 0:8fdf9a60065b 15043 #define USB_MISCCTRL_VFEDG_EN_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 15044 #define USB_MISCCTRL_VFEDG_EN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 15045 #define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
kadonotakashi 0:8fdf9a60065b 15046
kadonotakashi 0:8fdf9a60065b 15047 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
kadonotakashi 0:8fdf9a60065b 15048 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 15049 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 15050 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
kadonotakashi 0:8fdf9a60065b 15051 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 15052 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 15053 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
kadonotakashi 0:8fdf9a60065b 15054 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 15055 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 15056 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
kadonotakashi 0:8fdf9a60065b 15057
kadonotakashi 0:8fdf9a60065b 15058 /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
kadonotakashi 0:8fdf9a60065b 15059 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 15060 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15061 #define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
kadonotakashi 0:8fdf9a60065b 15062 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 15063 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 15064 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
kadonotakashi 0:8fdf9a60065b 15065
kadonotakashi 0:8fdf9a60065b 15066 /*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
kadonotakashi 0:8fdf9a60065b 15067 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 15068 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 15069 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
kadonotakashi 0:8fdf9a60065b 15070
kadonotakashi 0:8fdf9a60065b 15071 /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
kadonotakashi 0:8fdf9a60065b 15072 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 15073 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 15074 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
kadonotakashi 0:8fdf9a60065b 15075
kadonotakashi 0:8fdf9a60065b 15076
kadonotakashi 0:8fdf9a60065b 15077 /*!
kadonotakashi 0:8fdf9a60065b 15078 * @}
kadonotakashi 0:8fdf9a60065b 15079 */ /* end of group USB_Register_Masks */
kadonotakashi 0:8fdf9a60065b 15080
kadonotakashi 0:8fdf9a60065b 15081
kadonotakashi 0:8fdf9a60065b 15082 /* USB - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 15083 /** Peripheral USB0 base address */
kadonotakashi 0:8fdf9a60065b 15084 #define USB0_BASE (0x40072000u)
kadonotakashi 0:8fdf9a60065b 15085 /** Peripheral USB0 base pointer */
kadonotakashi 0:8fdf9a60065b 15086 #define USB0 ((USB_Type *)USB0_BASE)
kadonotakashi 0:8fdf9a60065b 15087 /** Array initializer of USB peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 15088 #define USB_BASE_ADDRS { USB0_BASE }
kadonotakashi 0:8fdf9a60065b 15089 /** Array initializer of USB peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 15090 #define USB_BASE_PTRS { USB0 }
kadonotakashi 0:8fdf9a60065b 15091 /** Interrupt vectors for the USB peripheral type */
kadonotakashi 0:8fdf9a60065b 15092 #define USB_IRQS { USB0_IRQn }
kadonotakashi 0:8fdf9a60065b 15093
kadonotakashi 0:8fdf9a60065b 15094 /*!
kadonotakashi 0:8fdf9a60065b 15095 * @}
kadonotakashi 0:8fdf9a60065b 15096 */ /* end of group USB_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 15097
kadonotakashi 0:8fdf9a60065b 15098
kadonotakashi 0:8fdf9a60065b 15099 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 15100 -- USBDCD Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 15101 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 15102
kadonotakashi 0:8fdf9a60065b 15103 /*!
kadonotakashi 0:8fdf9a60065b 15104 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 15105 * @{
kadonotakashi 0:8fdf9a60065b 15106 */
kadonotakashi 0:8fdf9a60065b 15107
kadonotakashi 0:8fdf9a60065b 15108 /** USBDCD - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 15109 typedef struct {
kadonotakashi 0:8fdf9a60065b 15110 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 15111 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 15112 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 15113 __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 15114 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 15115 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 15116 union { /* offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 15117 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 15118 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
kadonotakashi 0:8fdf9a60065b 15119 };
kadonotakashi 0:8fdf9a60065b 15120 } USBDCD_Type;
kadonotakashi 0:8fdf9a60065b 15121
kadonotakashi 0:8fdf9a60065b 15122 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 15123 -- USBDCD Register Masks
kadonotakashi 0:8fdf9a60065b 15124 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 15125
kadonotakashi 0:8fdf9a60065b 15126 /*!
kadonotakashi 0:8fdf9a60065b 15127 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
kadonotakashi 0:8fdf9a60065b 15128 * @{
kadonotakashi 0:8fdf9a60065b 15129 */
kadonotakashi 0:8fdf9a60065b 15130
kadonotakashi 0:8fdf9a60065b 15131 /*! @name CONTROL - Control register */
kadonotakashi 0:8fdf9a60065b 15132 #define USBDCD_CONTROL_IACK_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 15133 #define USBDCD_CONTROL_IACK_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15134 #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
kadonotakashi 0:8fdf9a60065b 15135 #define USBDCD_CONTROL_IF_MASK (0x100U)
kadonotakashi 0:8fdf9a60065b 15136 #define USBDCD_CONTROL_IF_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 15137 #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
kadonotakashi 0:8fdf9a60065b 15138 #define USBDCD_CONTROL_IE_MASK (0x10000U)
kadonotakashi 0:8fdf9a60065b 15139 #define USBDCD_CONTROL_IE_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 15140 #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
kadonotakashi 0:8fdf9a60065b 15141 #define USBDCD_CONTROL_BC12_MASK (0x20000U)
kadonotakashi 0:8fdf9a60065b 15142 #define USBDCD_CONTROL_BC12_SHIFT (17U)
kadonotakashi 0:8fdf9a60065b 15143 #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
kadonotakashi 0:8fdf9a60065b 15144 #define USBDCD_CONTROL_START_MASK (0x1000000U)
kadonotakashi 0:8fdf9a60065b 15145 #define USBDCD_CONTROL_START_SHIFT (24U)
kadonotakashi 0:8fdf9a60065b 15146 #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
kadonotakashi 0:8fdf9a60065b 15147 #define USBDCD_CONTROL_SR_MASK (0x2000000U)
kadonotakashi 0:8fdf9a60065b 15148 #define USBDCD_CONTROL_SR_SHIFT (25U)
kadonotakashi 0:8fdf9a60065b 15149 #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
kadonotakashi 0:8fdf9a60065b 15150
kadonotakashi 0:8fdf9a60065b 15151 /*! @name CLOCK - Clock register */
kadonotakashi 0:8fdf9a60065b 15152 #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 15153 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15154 #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
kadonotakashi 0:8fdf9a60065b 15155 #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
kadonotakashi 0:8fdf9a60065b 15156 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 15157 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
kadonotakashi 0:8fdf9a60065b 15158
kadonotakashi 0:8fdf9a60065b 15159 /*! @name STATUS - Status register */
kadonotakashi 0:8fdf9a60065b 15160 #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
kadonotakashi 0:8fdf9a60065b 15161 #define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 15162 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
kadonotakashi 0:8fdf9a60065b 15163 #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
kadonotakashi 0:8fdf9a60065b 15164 #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
kadonotakashi 0:8fdf9a60065b 15165 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
kadonotakashi 0:8fdf9a60065b 15166 #define USBDCD_STATUS_ERR_MASK (0x100000U)
kadonotakashi 0:8fdf9a60065b 15167 #define USBDCD_STATUS_ERR_SHIFT (20U)
kadonotakashi 0:8fdf9a60065b 15168 #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
kadonotakashi 0:8fdf9a60065b 15169 #define USBDCD_STATUS_TO_MASK (0x200000U)
kadonotakashi 0:8fdf9a60065b 15170 #define USBDCD_STATUS_TO_SHIFT (21U)
kadonotakashi 0:8fdf9a60065b 15171 #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
kadonotakashi 0:8fdf9a60065b 15172 #define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
kadonotakashi 0:8fdf9a60065b 15173 #define USBDCD_STATUS_ACTIVE_SHIFT (22U)
kadonotakashi 0:8fdf9a60065b 15174 #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
kadonotakashi 0:8fdf9a60065b 15175
kadonotakashi 0:8fdf9a60065b 15176 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
kadonotakashi 0:8fdf9a60065b 15177 #define USBDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 15178 #define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15179 #define USBDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
kadonotakashi 0:8fdf9a60065b 15180
kadonotakashi 0:8fdf9a60065b 15181 /*! @name TIMER0 - TIMER0 register */
kadonotakashi 0:8fdf9a60065b 15182 #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
kadonotakashi 0:8fdf9a60065b 15183 #define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15184 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
kadonotakashi 0:8fdf9a60065b 15185 #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
kadonotakashi 0:8fdf9a60065b 15186 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 15187 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
kadonotakashi 0:8fdf9a60065b 15188
kadonotakashi 0:8fdf9a60065b 15189 /*! @name TIMER1 - TIMER1 register */
kadonotakashi 0:8fdf9a60065b 15190 #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
kadonotakashi 0:8fdf9a60065b 15191 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15192 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
kadonotakashi 0:8fdf9a60065b 15193 #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
kadonotakashi 0:8fdf9a60065b 15194 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 15195 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
kadonotakashi 0:8fdf9a60065b 15196
kadonotakashi 0:8fdf9a60065b 15197 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
kadonotakashi 0:8fdf9a60065b 15198 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
kadonotakashi 0:8fdf9a60065b 15199 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15200 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
kadonotakashi 0:8fdf9a60065b 15201 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
kadonotakashi 0:8fdf9a60065b 15202 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 15203 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
kadonotakashi 0:8fdf9a60065b 15204
kadonotakashi 0:8fdf9a60065b 15205 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
kadonotakashi 0:8fdf9a60065b 15206 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
kadonotakashi 0:8fdf9a60065b 15207 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15208 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
kadonotakashi 0:8fdf9a60065b 15209 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
kadonotakashi 0:8fdf9a60065b 15210 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 15211 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
kadonotakashi 0:8fdf9a60065b 15212
kadonotakashi 0:8fdf9a60065b 15213
kadonotakashi 0:8fdf9a60065b 15214 /*!
kadonotakashi 0:8fdf9a60065b 15215 * @}
kadonotakashi 0:8fdf9a60065b 15216 */ /* end of group USBDCD_Register_Masks */
kadonotakashi 0:8fdf9a60065b 15217
kadonotakashi 0:8fdf9a60065b 15218
kadonotakashi 0:8fdf9a60065b 15219 /* USBDCD - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 15220 /** Peripheral USBDCD base address */
kadonotakashi 0:8fdf9a60065b 15221 #define USBDCD_BASE (0x40035000u)
kadonotakashi 0:8fdf9a60065b 15222 /** Peripheral USBDCD base pointer */
kadonotakashi 0:8fdf9a60065b 15223 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
kadonotakashi 0:8fdf9a60065b 15224 /** Array initializer of USBDCD peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 15225 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
kadonotakashi 0:8fdf9a60065b 15226 /** Array initializer of USBDCD peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 15227 #define USBDCD_BASE_PTRS { USBDCD }
kadonotakashi 0:8fdf9a60065b 15228 /** Interrupt vectors for the USBDCD peripheral type */
kadonotakashi 0:8fdf9a60065b 15229 #define USBDCD_IRQS { USBDCD_IRQn }
kadonotakashi 0:8fdf9a60065b 15230
kadonotakashi 0:8fdf9a60065b 15231 /*!
kadonotakashi 0:8fdf9a60065b 15232 * @}
kadonotakashi 0:8fdf9a60065b 15233 */ /* end of group USBDCD_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 15234
kadonotakashi 0:8fdf9a60065b 15235
kadonotakashi 0:8fdf9a60065b 15236 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 15237 -- VREF Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 15238 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 15239
kadonotakashi 0:8fdf9a60065b 15240 /*!
kadonotakashi 0:8fdf9a60065b 15241 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 15242 * @{
kadonotakashi 0:8fdf9a60065b 15243 */
kadonotakashi 0:8fdf9a60065b 15244
kadonotakashi 0:8fdf9a60065b 15245 /** VREF - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 15246 typedef struct {
kadonotakashi 0:8fdf9a60065b 15247 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 15248 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
kadonotakashi 0:8fdf9a60065b 15249 } VREF_Type;
kadonotakashi 0:8fdf9a60065b 15250
kadonotakashi 0:8fdf9a60065b 15251 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 15252 -- VREF Register Masks
kadonotakashi 0:8fdf9a60065b 15253 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 15254
kadonotakashi 0:8fdf9a60065b 15255 /*!
kadonotakashi 0:8fdf9a60065b 15256 * @addtogroup VREF_Register_Masks VREF Register Masks
kadonotakashi 0:8fdf9a60065b 15257 * @{
kadonotakashi 0:8fdf9a60065b 15258 */
kadonotakashi 0:8fdf9a60065b 15259
kadonotakashi 0:8fdf9a60065b 15260 /*! @name TRM - VREF Trim Register */
kadonotakashi 0:8fdf9a60065b 15261 #define VREF_TRM_TRIM_MASK (0x3FU)
kadonotakashi 0:8fdf9a60065b 15262 #define VREF_TRM_TRIM_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15263 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
kadonotakashi 0:8fdf9a60065b 15264 #define VREF_TRM_CHOPEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 15265 #define VREF_TRM_CHOPEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 15266 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
kadonotakashi 0:8fdf9a60065b 15267
kadonotakashi 0:8fdf9a60065b 15268 /*! @name SC - VREF Status and Control Register */
kadonotakashi 0:8fdf9a60065b 15269 #define VREF_SC_MODE_LV_MASK (0x3U)
kadonotakashi 0:8fdf9a60065b 15270 #define VREF_SC_MODE_LV_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15271 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
kadonotakashi 0:8fdf9a60065b 15272 #define VREF_SC_VREFST_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 15273 #define VREF_SC_VREFST_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 15274 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
kadonotakashi 0:8fdf9a60065b 15275 #define VREF_SC_ICOMPEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 15276 #define VREF_SC_ICOMPEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 15277 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
kadonotakashi 0:8fdf9a60065b 15278 #define VREF_SC_REGEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 15279 #define VREF_SC_REGEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 15280 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
kadonotakashi 0:8fdf9a60065b 15281 #define VREF_SC_VREFEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 15282 #define VREF_SC_VREFEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 15283 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
kadonotakashi 0:8fdf9a60065b 15284
kadonotakashi 0:8fdf9a60065b 15285
kadonotakashi 0:8fdf9a60065b 15286 /*!
kadonotakashi 0:8fdf9a60065b 15287 * @}
kadonotakashi 0:8fdf9a60065b 15288 */ /* end of group VREF_Register_Masks */
kadonotakashi 0:8fdf9a60065b 15289
kadonotakashi 0:8fdf9a60065b 15290
kadonotakashi 0:8fdf9a60065b 15291 /* VREF - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 15292 /** Peripheral VREF base address */
kadonotakashi 0:8fdf9a60065b 15293 #define VREF_BASE (0x40074000u)
kadonotakashi 0:8fdf9a60065b 15294 /** Peripheral VREF base pointer */
kadonotakashi 0:8fdf9a60065b 15295 #define VREF ((VREF_Type *)VREF_BASE)
kadonotakashi 0:8fdf9a60065b 15296 /** Array initializer of VREF peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 15297 #define VREF_BASE_ADDRS { VREF_BASE }
kadonotakashi 0:8fdf9a60065b 15298 /** Array initializer of VREF peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 15299 #define VREF_BASE_PTRS { VREF }
kadonotakashi 0:8fdf9a60065b 15300
kadonotakashi 0:8fdf9a60065b 15301 /*!
kadonotakashi 0:8fdf9a60065b 15302 * @}
kadonotakashi 0:8fdf9a60065b 15303 */ /* end of group VREF_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 15304
kadonotakashi 0:8fdf9a60065b 15305
kadonotakashi 0:8fdf9a60065b 15306 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 15307 -- WDOG Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 15308 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 15309
kadonotakashi 0:8fdf9a60065b 15310 /*!
kadonotakashi 0:8fdf9a60065b 15311 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
kadonotakashi 0:8fdf9a60065b 15312 * @{
kadonotakashi 0:8fdf9a60065b 15313 */
kadonotakashi 0:8fdf9a60065b 15314
kadonotakashi 0:8fdf9a60065b 15315 /** WDOG - Register Layout Typedef */
kadonotakashi 0:8fdf9a60065b 15316 typedef struct {
kadonotakashi 0:8fdf9a60065b 15317 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
kadonotakashi 0:8fdf9a60065b 15318 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
kadonotakashi 0:8fdf9a60065b 15319 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
kadonotakashi 0:8fdf9a60065b 15320 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
kadonotakashi 0:8fdf9a60065b 15321 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
kadonotakashi 0:8fdf9a60065b 15322 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
kadonotakashi 0:8fdf9a60065b 15323 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
kadonotakashi 0:8fdf9a60065b 15324 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
kadonotakashi 0:8fdf9a60065b 15325 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
kadonotakashi 0:8fdf9a60065b 15326 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
kadonotakashi 0:8fdf9a60065b 15327 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
kadonotakashi 0:8fdf9a60065b 15328 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
kadonotakashi 0:8fdf9a60065b 15329 } WDOG_Type;
kadonotakashi 0:8fdf9a60065b 15330
kadonotakashi 0:8fdf9a60065b 15331 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 15332 -- WDOG Register Masks
kadonotakashi 0:8fdf9a60065b 15333 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 15334
kadonotakashi 0:8fdf9a60065b 15335 /*!
kadonotakashi 0:8fdf9a60065b 15336 * @addtogroup WDOG_Register_Masks WDOG Register Masks
kadonotakashi 0:8fdf9a60065b 15337 * @{
kadonotakashi 0:8fdf9a60065b 15338 */
kadonotakashi 0:8fdf9a60065b 15339
kadonotakashi 0:8fdf9a60065b 15340 /*! @name STCTRLH - Watchdog Status and Control Register High */
kadonotakashi 0:8fdf9a60065b 15341 #define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
kadonotakashi 0:8fdf9a60065b 15342 #define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15343 #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
kadonotakashi 0:8fdf9a60065b 15344 #define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
kadonotakashi 0:8fdf9a60065b 15345 #define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
kadonotakashi 0:8fdf9a60065b 15346 #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
kadonotakashi 0:8fdf9a60065b 15347 #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
kadonotakashi 0:8fdf9a60065b 15348 #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
kadonotakashi 0:8fdf9a60065b 15349 #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
kadonotakashi 0:8fdf9a60065b 15350 #define WDOG_STCTRLH_WINEN_MASK (0x8U)
kadonotakashi 0:8fdf9a60065b 15351 #define WDOG_STCTRLH_WINEN_SHIFT (3U)
kadonotakashi 0:8fdf9a60065b 15352 #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
kadonotakashi 0:8fdf9a60065b 15353 #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
kadonotakashi 0:8fdf9a60065b 15354 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
kadonotakashi 0:8fdf9a60065b 15355 #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
kadonotakashi 0:8fdf9a60065b 15356 #define WDOG_STCTRLH_DBGEN_MASK (0x20U)
kadonotakashi 0:8fdf9a60065b 15357 #define WDOG_STCTRLH_DBGEN_SHIFT (5U)
kadonotakashi 0:8fdf9a60065b 15358 #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
kadonotakashi 0:8fdf9a60065b 15359 #define WDOG_STCTRLH_STOPEN_MASK (0x40U)
kadonotakashi 0:8fdf9a60065b 15360 #define WDOG_STCTRLH_STOPEN_SHIFT (6U)
kadonotakashi 0:8fdf9a60065b 15361 #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
kadonotakashi 0:8fdf9a60065b 15362 #define WDOG_STCTRLH_WAITEN_MASK (0x80U)
kadonotakashi 0:8fdf9a60065b 15363 #define WDOG_STCTRLH_WAITEN_SHIFT (7U)
kadonotakashi 0:8fdf9a60065b 15364 #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
kadonotakashi 0:8fdf9a60065b 15365 #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
kadonotakashi 0:8fdf9a60065b 15366 #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
kadonotakashi 0:8fdf9a60065b 15367 #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
kadonotakashi 0:8fdf9a60065b 15368 #define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
kadonotakashi 0:8fdf9a60065b 15369 #define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
kadonotakashi 0:8fdf9a60065b 15370 #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
kadonotakashi 0:8fdf9a60065b 15371 #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
kadonotakashi 0:8fdf9a60065b 15372 #define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 15373 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
kadonotakashi 0:8fdf9a60065b 15374 #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
kadonotakashi 0:8fdf9a60065b 15375 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
kadonotakashi 0:8fdf9a60065b 15376 #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
kadonotakashi 0:8fdf9a60065b 15377
kadonotakashi 0:8fdf9a60065b 15378 /*! @name STCTRLL - Watchdog Status and Control Register Low */
kadonotakashi 0:8fdf9a60065b 15379 #define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
kadonotakashi 0:8fdf9a60065b 15380 #define WDOG_STCTRLL_INTFLG_SHIFT (15U)
kadonotakashi 0:8fdf9a60065b 15381 #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
kadonotakashi 0:8fdf9a60065b 15382
kadonotakashi 0:8fdf9a60065b 15383 /*! @name TOVALH - Watchdog Time-out Value Register High */
kadonotakashi 0:8fdf9a60065b 15384 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 15385 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15386 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
kadonotakashi 0:8fdf9a60065b 15387
kadonotakashi 0:8fdf9a60065b 15388 /*! @name TOVALL - Watchdog Time-out Value Register Low */
kadonotakashi 0:8fdf9a60065b 15389 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 15390 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15391 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
kadonotakashi 0:8fdf9a60065b 15392
kadonotakashi 0:8fdf9a60065b 15393 /*! @name WINH - Watchdog Window Register High */
kadonotakashi 0:8fdf9a60065b 15394 #define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 15395 #define WDOG_WINH_WINHIGH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15396 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
kadonotakashi 0:8fdf9a60065b 15397
kadonotakashi 0:8fdf9a60065b 15398 /*! @name WINL - Watchdog Window Register Low */
kadonotakashi 0:8fdf9a60065b 15399 #define WDOG_WINL_WINLOW_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 15400 #define WDOG_WINL_WINLOW_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15401 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
kadonotakashi 0:8fdf9a60065b 15402
kadonotakashi 0:8fdf9a60065b 15403 /*! @name REFRESH - Watchdog Refresh register */
kadonotakashi 0:8fdf9a60065b 15404 #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 15405 #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15406 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
kadonotakashi 0:8fdf9a60065b 15407
kadonotakashi 0:8fdf9a60065b 15408 /*! @name UNLOCK - Watchdog Unlock register */
kadonotakashi 0:8fdf9a60065b 15409 #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 15410 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15411 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
kadonotakashi 0:8fdf9a60065b 15412
kadonotakashi 0:8fdf9a60065b 15413 /*! @name TMROUTH - Watchdog Timer Output Register High */
kadonotakashi 0:8fdf9a60065b 15414 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 15415 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15416 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
kadonotakashi 0:8fdf9a60065b 15417
kadonotakashi 0:8fdf9a60065b 15418 /*! @name TMROUTL - Watchdog Timer Output Register Low */
kadonotakashi 0:8fdf9a60065b 15419 #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 15420 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15421 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
kadonotakashi 0:8fdf9a60065b 15422
kadonotakashi 0:8fdf9a60065b 15423 /*! @name RSTCNT - Watchdog Reset Count register */
kadonotakashi 0:8fdf9a60065b 15424 #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 15425 #define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
kadonotakashi 0:8fdf9a60065b 15426 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
kadonotakashi 0:8fdf9a60065b 15427
kadonotakashi 0:8fdf9a60065b 15428 /*! @name PRESC - Watchdog Prescaler register */
kadonotakashi 0:8fdf9a60065b 15429 #define WDOG_PRESC_PRESCVAL_MASK (0x700U)
kadonotakashi 0:8fdf9a60065b 15430 #define WDOG_PRESC_PRESCVAL_SHIFT (8U)
kadonotakashi 0:8fdf9a60065b 15431 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
kadonotakashi 0:8fdf9a60065b 15432
kadonotakashi 0:8fdf9a60065b 15433
kadonotakashi 0:8fdf9a60065b 15434 /*!
kadonotakashi 0:8fdf9a60065b 15435 * @}
kadonotakashi 0:8fdf9a60065b 15436 */ /* end of group WDOG_Register_Masks */
kadonotakashi 0:8fdf9a60065b 15437
kadonotakashi 0:8fdf9a60065b 15438
kadonotakashi 0:8fdf9a60065b 15439 /* WDOG - Peripheral instance base addresses */
kadonotakashi 0:8fdf9a60065b 15440 /** Peripheral WDOG base address */
kadonotakashi 0:8fdf9a60065b 15441 #define WDOG_BASE (0x40052000u)
kadonotakashi 0:8fdf9a60065b 15442 /** Peripheral WDOG base pointer */
kadonotakashi 0:8fdf9a60065b 15443 #define WDOG ((WDOG_Type *)WDOG_BASE)
kadonotakashi 0:8fdf9a60065b 15444 /** Array initializer of WDOG peripheral base addresses */
kadonotakashi 0:8fdf9a60065b 15445 #define WDOG_BASE_ADDRS { WDOG_BASE }
kadonotakashi 0:8fdf9a60065b 15446 /** Array initializer of WDOG peripheral base pointers */
kadonotakashi 0:8fdf9a60065b 15447 #define WDOG_BASE_PTRS { WDOG }
kadonotakashi 0:8fdf9a60065b 15448 /** Interrupt vectors for the WDOG peripheral type */
kadonotakashi 0:8fdf9a60065b 15449 #define WDOG_IRQS { WDOG_EWM_IRQn }
kadonotakashi 0:8fdf9a60065b 15450
kadonotakashi 0:8fdf9a60065b 15451 /*!
kadonotakashi 0:8fdf9a60065b 15452 * @}
kadonotakashi 0:8fdf9a60065b 15453 */ /* end of group WDOG_Peripheral_Access_Layer */
kadonotakashi 0:8fdf9a60065b 15454
kadonotakashi 0:8fdf9a60065b 15455
kadonotakashi 0:8fdf9a60065b 15456 /*
kadonotakashi 0:8fdf9a60065b 15457 ** End of section using anonymous unions
kadonotakashi 0:8fdf9a60065b 15458 */
kadonotakashi 0:8fdf9a60065b 15459
kadonotakashi 0:8fdf9a60065b 15460 #if defined(__ARMCC_VERSION)
kadonotakashi 0:8fdf9a60065b 15461 #pragma pop
kadonotakashi 0:8fdf9a60065b 15462 #elif defined(__CWCC__)
kadonotakashi 0:8fdf9a60065b 15463 #pragma pop
kadonotakashi 0:8fdf9a60065b 15464 #elif defined(__GNUC__)
kadonotakashi 0:8fdf9a60065b 15465 /* leave anonymous unions enabled */
kadonotakashi 0:8fdf9a60065b 15466 #elif defined(__IAR_SYSTEMS_ICC__)
kadonotakashi 0:8fdf9a60065b 15467 #pragma language=default
kadonotakashi 0:8fdf9a60065b 15468 #else
kadonotakashi 0:8fdf9a60065b 15469 #error Not supported compiler type
kadonotakashi 0:8fdf9a60065b 15470 #endif
kadonotakashi 0:8fdf9a60065b 15471
kadonotakashi 0:8fdf9a60065b 15472 /*!
kadonotakashi 0:8fdf9a60065b 15473 * @}
kadonotakashi 0:8fdf9a60065b 15474 */ /* end of group Peripheral_access_layer */
kadonotakashi 0:8fdf9a60065b 15475
kadonotakashi 0:8fdf9a60065b 15476
kadonotakashi 0:8fdf9a60065b 15477 /* ----------------------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 15478 -- SDK Compatibility
kadonotakashi 0:8fdf9a60065b 15479 ---------------------------------------------------------------------------- */
kadonotakashi 0:8fdf9a60065b 15480
kadonotakashi 0:8fdf9a60065b 15481 /*!
kadonotakashi 0:8fdf9a60065b 15482 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
kadonotakashi 0:8fdf9a60065b 15483 * @{
kadonotakashi 0:8fdf9a60065b 15484 */
kadonotakashi 0:8fdf9a60065b 15485
kadonotakashi 0:8fdf9a60065b 15486 #define PIT0_IRQn PIT0CH0_IRQn
kadonotakashi 0:8fdf9a60065b 15487 #define PIT1_IRQn PIT0CH1_IRQn
kadonotakashi 0:8fdf9a60065b 15488 #define PIT2_IRQn PIT0CH2_IRQn
kadonotakashi 0:8fdf9a60065b 15489 #define PIT3_IRQn PIT0CH3_IRQn
kadonotakashi 0:8fdf9a60065b 15490 #define PIT_BASE PIT0_BASE
kadonotakashi 0:8fdf9a60065b 15491 #define PIT PIT0
kadonotakashi 0:8fdf9a60065b 15492 #define PIT_MCR PIT0_MCR
kadonotakashi 0:8fdf9a60065b 15493 #define PIT_LDVAL0 PIT0_LDVAL0
kadonotakashi 0:8fdf9a60065b 15494 #define PIT_CVAL0 PIT0_CVAL0
kadonotakashi 0:8fdf9a60065b 15495 #define PIT_TCTRL0 PIT0_TCTRL0
kadonotakashi 0:8fdf9a60065b 15496 #define PIT_TFLG0 PIT0_TFLG0
kadonotakashi 0:8fdf9a60065b 15497 #define PIT_LDVAL1 PIT0_LDVAL1
kadonotakashi 0:8fdf9a60065b 15498 #define PIT_CVAL1 PIT0_CVAL1
kadonotakashi 0:8fdf9a60065b 15499 #define PIT_TCTRL1 PIT0_TCTRL1
kadonotakashi 0:8fdf9a60065b 15500 #define PIT_TFLG1 PIT0_TFLG1
kadonotakashi 0:8fdf9a60065b 15501 #define PIT_LDVAL2 PIT0_LDVAL2
kadonotakashi 0:8fdf9a60065b 15502 #define PIT_CVAL2 PIT0_CVAL2
kadonotakashi 0:8fdf9a60065b 15503 #define PIT_TCTRL2 PIT0_TCTRL2
kadonotakashi 0:8fdf9a60065b 15504 #define PIT_TFLG2 PIT0_TFLG2
kadonotakashi 0:8fdf9a60065b 15505 #define PIT_LDVAL3 PIT0_LDVAL3
kadonotakashi 0:8fdf9a60065b 15506 #define PIT_CVAL3 PIT0_CVAL3
kadonotakashi 0:8fdf9a60065b 15507 #define PIT_TCTRL3 PIT0_TCTRL3
kadonotakashi 0:8fdf9a60065b 15508 #define PIT_TFLG3 PIT0_TFLG3
kadonotakashi 0:8fdf9a60065b 15509 #define PIT_LDVAL(index) PIT0_LDVAL(index)
kadonotakashi 0:8fdf9a60065b 15510 #define PIT_CVAL(index) PIT0_CVAL(index)
kadonotakashi 0:8fdf9a60065b 15511 #define PIT_TCTRL(index) PIT0_TCTRL(index)
kadonotakashi 0:8fdf9a60065b 15512 #define PIT_TFLG(index) PIT0_TFLG(index)
kadonotakashi 0:8fdf9a60065b 15513 #define PIT0_IRQHandler PIT0CH0_IRQHandler
kadonotakashi 0:8fdf9a60065b 15514 #define PIT1_IRQHandler PIT0CH1_IRQHandler
kadonotakashi 0:8fdf9a60065b 15515 #define PIT2_IRQHandler PIT0CH2_IRQHandler
kadonotakashi 0:8fdf9a60065b 15516 #define PIT3_IRQHandler PIT0CH3_IRQHandler
kadonotakashi 0:8fdf9a60065b 15517 #define DSPI0 SPI0
kadonotakashi 0:8fdf9a60065b 15518 #define DSPI1 SPI1
kadonotakashi 0:8fdf9a60065b 15519 #define DSPI2 SPI2
kadonotakashi 0:8fdf9a60065b 15520 #define DMAMUX0 DMAMUX
kadonotakashi 0:8fdf9a60065b 15521
kadonotakashi 0:8fdf9a60065b 15522 /*!
kadonotakashi 0:8fdf9a60065b 15523 * @}
kadonotakashi 0:8fdf9a60065b 15524 */ /* end of group SDK_Compatibility_Symbols */
kadonotakashi 0:8fdf9a60065b 15525
kadonotakashi 0:8fdf9a60065b 15526
kadonotakashi 0:8fdf9a60065b 15527 #endif /* _MK82F25615_H_ */
kadonotakashi 0:8fdf9a60065b 15528