takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_KLXX/sleep.c@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /* mbed Microcontroller Library
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2006-2013 ARM Limited
kadonotakashi 0:8fdf9a60065b 3 *
kadonotakashi 0:8fdf9a60065b 4 * Licensed under the Apache License, Version 2.0 (the "License");
kadonotakashi 0:8fdf9a60065b 5 * you may not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 6 * You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * http://www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 11 * distributed under the License is distributed on an "AS IS" BASIS,
kadonotakashi 0:8fdf9a60065b 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 13 * See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 14 * limitations under the License.
kadonotakashi 0:8fdf9a60065b 15 */
kadonotakashi 0:8fdf9a60065b 16 #include "sleep_api.h"
kadonotakashi 0:8fdf9a60065b 17 #include "cmsis.h"
kadonotakashi 0:8fdf9a60065b 18 #include "PeripheralPins.h"
kadonotakashi 0:8fdf9a60065b 19
kadonotakashi 0:8fdf9a60065b 20 //Normal wait mode
kadonotakashi 0:8fdf9a60065b 21 void hal_sleep(void)
kadonotakashi 0:8fdf9a60065b 22 {
kadonotakashi 0:8fdf9a60065b 23 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
kadonotakashi 0:8fdf9a60065b 24
kadonotakashi 0:8fdf9a60065b 25 //Normal sleep mode for ARM core:
kadonotakashi 0:8fdf9a60065b 26 SCB->SCR = 0;
kadonotakashi 0:8fdf9a60065b 27 __WFI();
kadonotakashi 0:8fdf9a60065b 28 }
kadonotakashi 0:8fdf9a60065b 29
kadonotakashi 0:8fdf9a60065b 30 //Very low-power stop mode
kadonotakashi 0:8fdf9a60065b 31 void hal_deepsleep(void)
kadonotakashi 0:8fdf9a60065b 32 {
kadonotakashi 0:8fdf9a60065b 33 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
kadonotakashi 0:8fdf9a60065b 34 uint8_t ADC_HSC = 0;
kadonotakashi 0:8fdf9a60065b 35 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
kadonotakashi 0:8fdf9a60065b 36 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
kadonotakashi 0:8fdf9a60065b 37 ADC_HSC = 1;
kadonotakashi 0:8fdf9a60065b 38 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
kadonotakashi 0:8fdf9a60065b 39 }
kadonotakashi 0:8fdf9a60065b 40 }
kadonotakashi 0:8fdf9a60065b 41
kadonotakashi 0:8fdf9a60065b 42 #if ! defined(TARGET_KL43Z)
kadonotakashi 0:8fdf9a60065b 43 //Check if PLL/FLL is enabled:
kadonotakashi 0:8fdf9a60065b 44 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
kadonotakashi 0:8fdf9a60065b 45 #endif
kadonotakashi 0:8fdf9a60065b 46
kadonotakashi 0:8fdf9a60065b 47 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
kadonotakashi 0:8fdf9a60065b 48 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
kadonotakashi 0:8fdf9a60065b 49
kadonotakashi 0:8fdf9a60065b 50 //Deep sleep for ARM core:
kadonotakashi 0:8fdf9a60065b 51 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
kadonotakashi 0:8fdf9a60065b 52
kadonotakashi 0:8fdf9a60065b 53 __WFI();
kadonotakashi 0:8fdf9a60065b 54
kadonotakashi 0:8fdf9a60065b 55 #if ! defined(TARGET_KL43Z)
kadonotakashi 0:8fdf9a60065b 56 //Switch back to PLL as clock source if needed
kadonotakashi 0:8fdf9a60065b 57 //The interrupt that woke up the device will run at reduced speed
kadonotakashi 0:8fdf9a60065b 58 if (PLL_FLL_en) {
kadonotakashi 0:8fdf9a60065b 59 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
kadonotakashi 0:8fdf9a60065b 60 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
kadonotakashi 0:8fdf9a60065b 61 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
kadonotakashi 0:8fdf9a60065b 62 #endif
kadonotakashi 0:8fdf9a60065b 63 MCG->C1 &= ~MCG_C1_CLKS_MASK;
kadonotakashi 0:8fdf9a60065b 64 }
kadonotakashi 0:8fdf9a60065b 65 #endif
kadonotakashi 0:8fdf9a60065b 66
kadonotakashi 0:8fdf9a60065b 67 if (ADC_HSC) {
kadonotakashi 0:8fdf9a60065b 68 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
kadonotakashi 0:8fdf9a60065b 69 }
kadonotakashi 0:8fdf9a60065b 70 }