takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_K20XX/sleep.c@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /* mbed Microcontroller Library
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2006-2015 ARM Limited
kadonotakashi 0:8fdf9a60065b 3 *
kadonotakashi 0:8fdf9a60065b 4 * Licensed under the Apache License, Version 2.0 (the "License");
kadonotakashi 0:8fdf9a60065b 5 * you may not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 6 * You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * http://www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 11 * distributed under the License is distributed on an "AS IS" BASIS,
kadonotakashi 0:8fdf9a60065b 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 13 * See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 14 * limitations under the License.
kadonotakashi 0:8fdf9a60065b 15 */
kadonotakashi 0:8fdf9a60065b 16 #include "sleep_api.h"
kadonotakashi 0:8fdf9a60065b 17 #include "cmsis.h"
kadonotakashi 0:8fdf9a60065b 18
kadonotakashi 0:8fdf9a60065b 19 //Normal wait mode
kadonotakashi 0:8fdf9a60065b 20 void hal_sleep(void)
kadonotakashi 0:8fdf9a60065b 21 {
kadonotakashi 0:8fdf9a60065b 22 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
kadonotakashi 0:8fdf9a60065b 23
kadonotakashi 0:8fdf9a60065b 24 //Normal sleep mode for ARM core:
kadonotakashi 0:8fdf9a60065b 25 SCB->SCR = 0;
kadonotakashi 0:8fdf9a60065b 26 __WFI();
kadonotakashi 0:8fdf9a60065b 27 }
kadonotakashi 0:8fdf9a60065b 28
kadonotakashi 0:8fdf9a60065b 29 //Very low-power stop mode
kadonotakashi 0:8fdf9a60065b 30 void hal_deepsleep(void)
kadonotakashi 0:8fdf9a60065b 31 {
kadonotakashi 0:8fdf9a60065b 32 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
kadonotakashi 0:8fdf9a60065b 33 uint8_t ADC_HSC = 0;
kadonotakashi 0:8fdf9a60065b 34 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
kadonotakashi 0:8fdf9a60065b 35 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
kadonotakashi 0:8fdf9a60065b 36 ADC_HSC = 1;
kadonotakashi 0:8fdf9a60065b 37 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
kadonotakashi 0:8fdf9a60065b 38 }
kadonotakashi 0:8fdf9a60065b 39 }
kadonotakashi 0:8fdf9a60065b 40
kadonotakashi 0:8fdf9a60065b 41 //Check if PLL/FLL is enabled:
kadonotakashi 0:8fdf9a60065b 42 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
kadonotakashi 0:8fdf9a60065b 43
kadonotakashi 0:8fdf9a60065b 44 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
kadonotakashi 0:8fdf9a60065b 45 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
kadonotakashi 0:8fdf9a60065b 46
kadonotakashi 0:8fdf9a60065b 47 //Deep sleep for ARM core:
kadonotakashi 0:8fdf9a60065b 48 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
kadonotakashi 0:8fdf9a60065b 49
kadonotakashi 0:8fdf9a60065b 50 __WFI();
kadonotakashi 0:8fdf9a60065b 51 //Switch back to PLL as clock source if needed
kadonotakashi 0:8fdf9a60065b 52 //The interrupt that woke up the device will run at reduced speed
kadonotakashi 0:8fdf9a60065b 53 if (PLL_FLL_en) {
kadonotakashi 0:8fdf9a60065b 54
kadonotakashi 0:8fdf9a60065b 55 #if defined (TARGET_K20D50M)
kadonotakashi 0:8fdf9a60065b 56 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
kadonotakashi 0:8fdf9a60065b 57 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
kadonotakashi 0:8fdf9a60065b 58 MCG->C1 &= ~MCG_C1_CLKS_MASK;
kadonotakashi 0:8fdf9a60065b 59 #else
kadonotakashi 0:8fdf9a60065b 60 // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
kadonotakashi 0:8fdf9a60065b 61 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
kadonotakashi 0:8fdf9a60065b 62 // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0
kadonotakashi 0:8fdf9a60065b 63 MCG->C6 = MCG_C6_VDIV0(0);
kadonotakashi 0:8fdf9a60065b 64 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running
kadonotakashi 0:8fdf9a60065b 65 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
kadonotakashi 0:8fdf9a60065b 66 // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3
kadonotakashi 0:8fdf9a60065b 67 MCG->C5 = MCG_C5_PRDIV0(5);
kadonotakashi 0:8fdf9a60065b 68 // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3
kadonotakashi 0:8fdf9a60065b 69 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
kadonotakashi 0:8fdf9a60065b 70 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
kadonotakashi 0:8fdf9a60065b 71 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL
kadonotakashi 0:8fdf9a60065b 72 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
kadonotakashi 0:8fdf9a60065b 73 // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0
kadonotakashi 0:8fdf9a60065b 74 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;;
kadonotakashi 0:8fdf9a60065b 75 while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected
kadonotakashi 0:8fdf9a60065b 76 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
kadonotakashi 0:8fdf9a60065b 77 #endif
kadonotakashi 0:8fdf9a60065b 78 }
kadonotakashi 0:8fdf9a60065b 79
kadonotakashi 0:8fdf9a60065b 80 if (ADC_HSC) {
kadonotakashi 0:8fdf9a60065b 81 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
kadonotakashi 0:8fdf9a60065b 82 }
kadonotakashi 0:8fdf9a60065b 83 }