takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Atmel/TARGET_SAM_CortexM4/us_ticker.c@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /* mbed Microcontroller Library
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2006-2015 ARM Limited
kadonotakashi 0:8fdf9a60065b 3 *
kadonotakashi 0:8fdf9a60065b 4 * Licensed under the Apache License, Version 2.0 (the "License");
kadonotakashi 0:8fdf9a60065b 5 * you may not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 6 * You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * http://www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 11 * distributed under the License is distributed on an "AS IS" BASIS,
kadonotakashi 0:8fdf9a60065b 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 13 * See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 14 * limitations under the License.
kadonotakashi 0:8fdf9a60065b 15 */
kadonotakashi 0:8fdf9a60065b 16 #include <stddef.h>
kadonotakashi 0:8fdf9a60065b 17 #include "us_ticker_api.h"
kadonotakashi 0:8fdf9a60065b 18 #include "cmsis.h"
kadonotakashi 0:8fdf9a60065b 19 #include "mbed_assert.h"
kadonotakashi 0:8fdf9a60065b 20 #include "compiler.h"
kadonotakashi 0:8fdf9a60065b 21 #include "sysclk.h"
kadonotakashi 0:8fdf9a60065b 22 #include "tc.h"
kadonotakashi 0:8fdf9a60065b 23
kadonotakashi 0:8fdf9a60065b 24 uint8_t us_ticker_inited = 0;
kadonotakashi 0:8fdf9a60065b 25 extern uint8_t g_sys_init;
kadonotakashi 0:8fdf9a60065b 26 volatile uint16_t us_ticker_16bit_counter;
kadonotakashi 0:8fdf9a60065b 27 volatile uint16_t us_ticker_interrupt_counter;
kadonotakashi 0:8fdf9a60065b 28 volatile uint16_t us_ticker_interrupt_offset;
kadonotakashi 0:8fdf9a60065b 29 volatile uint32_t overflow32bitcounter = 0;
kadonotakashi 0:8fdf9a60065b 30
kadonotakashi 0:8fdf9a60065b 31 #define TICKER_COUNTER_uS TC1
kadonotakashi 0:8fdf9a60065b 32
kadonotakashi 0:8fdf9a60065b 33 #define TICKER_COUNTER_CLK0 ID_TC3
kadonotakashi 0:8fdf9a60065b 34 #define TICKER_COUNTER_CLK1 ID_TC4
kadonotakashi 0:8fdf9a60065b 35
kadonotakashi 0:8fdf9a60065b 36 #define TICKER_COUNTER_CHANNEL0 0
kadonotakashi 0:8fdf9a60065b 37 #define TICKER_COUNTER_IRQn0 TC3_IRQn
kadonotakashi 0:8fdf9a60065b 38 #define TICKER_COUNTER_Handlr0 TC3_Handler
kadonotakashi 0:8fdf9a60065b 39
kadonotakashi 0:8fdf9a60065b 40 #define TICKER_COUNTER_CHANNEL1 1
kadonotakashi 0:8fdf9a60065b 41 #define TICKER_COUNTER_IRQn1 TC4_IRQn
kadonotakashi 0:8fdf9a60065b 42 #define TICKER_COUNTER_Handlr1 TC4_Handler
kadonotakashi 0:8fdf9a60065b 43
kadonotakashi 0:8fdf9a60065b 44 #define OVERFLOW_16bit_VALUE 0xFFFF
kadonotakashi 0:8fdf9a60065b 45
kadonotakashi 0:8fdf9a60065b 46
kadonotakashi 0:8fdf9a60065b 47 void TICKER_COUNTER_Handlr1(void)
kadonotakashi 0:8fdf9a60065b 48 {
kadonotakashi 0:8fdf9a60065b 49 uint32_t status=tc_get_status(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
kadonotakashi 0:8fdf9a60065b 50 uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
kadonotakashi 0:8fdf9a60065b 51
kadonotakashi 0:8fdf9a60065b 52 if (((status & interrupmask) & TC_IER_CPCS)) {
kadonotakashi 0:8fdf9a60065b 53 if(us_ticker_interrupt_counter) {
kadonotakashi 0:8fdf9a60065b 54 us_ticker_interrupt_counter--;
kadonotakashi 0:8fdf9a60065b 55 } else {
kadonotakashi 0:8fdf9a60065b 56 if(us_ticker_interrupt_offset) {
kadonotakashi 0:8fdf9a60065b 57 us_ticker_interrupt_offset=0;
kadonotakashi 0:8fdf9a60065b 58 tc_stop(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
kadonotakashi 0:8fdf9a60065b 59 tc_write_rc(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, (uint32_t)us_ticker_interrupt_offset);
kadonotakashi 0:8fdf9a60065b 60 tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
kadonotakashi 0:8fdf9a60065b 61 } else
kadonotakashi 0:8fdf9a60065b 62 us_ticker_irq_handler();
kadonotakashi 0:8fdf9a60065b 63 }
kadonotakashi 0:8fdf9a60065b 64 }
kadonotakashi 0:8fdf9a60065b 65 }
kadonotakashi 0:8fdf9a60065b 66
kadonotakashi 0:8fdf9a60065b 67 void TICKER_COUNTER_Handlr0(void)
kadonotakashi 0:8fdf9a60065b 68 {
kadonotakashi 0:8fdf9a60065b 69 uint32_t status=tc_get_status(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
kadonotakashi 0:8fdf9a60065b 70 uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
kadonotakashi 0:8fdf9a60065b 71
kadonotakashi 0:8fdf9a60065b 72 if (((status & interrupmask) & TC_IER_COVFS)) {
kadonotakashi 0:8fdf9a60065b 73 us_ticker_16bit_counter++;
kadonotakashi 0:8fdf9a60065b 74 if(us_ticker_16bit_counter == 0xFFFF)
kadonotakashi 0:8fdf9a60065b 75 overflow32bitcounter++;
kadonotakashi 0:8fdf9a60065b 76 }
kadonotakashi 0:8fdf9a60065b 77 }
kadonotakashi 0:8fdf9a60065b 78
kadonotakashi 0:8fdf9a60065b 79 void us_ticker_init(void)
kadonotakashi 0:8fdf9a60065b 80 {
kadonotakashi 0:8fdf9a60065b 81 if (us_ticker_inited) return;
kadonotakashi 0:8fdf9a60065b 82 us_ticker_inited = 1;
kadonotakashi 0:8fdf9a60065b 83
kadonotakashi 0:8fdf9a60065b 84 us_ticker_16bit_counter=0;
kadonotakashi 0:8fdf9a60065b 85 us_ticker_interrupt_counter=0;
kadonotakashi 0:8fdf9a60065b 86 us_ticker_interrupt_offset=0;
kadonotakashi 0:8fdf9a60065b 87
kadonotakashi 0:8fdf9a60065b 88 if (g_sys_init == 0) {
kadonotakashi 0:8fdf9a60065b 89 sysclk_init();
kadonotakashi 0:8fdf9a60065b 90 system_board_init();
kadonotakashi 0:8fdf9a60065b 91 g_sys_init = 1;
kadonotakashi 0:8fdf9a60065b 92 }
kadonotakashi 0:8fdf9a60065b 93
kadonotakashi 0:8fdf9a60065b 94 /* Configure the PMC to enable the TC module. */
kadonotakashi 0:8fdf9a60065b 95 sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK0);
kadonotakashi 0:8fdf9a60065b 96 sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK1);
kadonotakashi 0:8fdf9a60065b 97
kadonotakashi 0:8fdf9a60065b 98 #if SAMG55
kadonotakashi 0:8fdf9a60065b 99 /* Enable PCK output */
kadonotakashi 0:8fdf9a60065b 100 pmc_disable_pck(PMC_PCK_3);
kadonotakashi 0:8fdf9a60065b 101 pmc_switch_pck_to_mck(PMC_PCK_3, PMC_PCK_PRES_CLK_1);
kadonotakashi 0:8fdf9a60065b 102 pmc_enable_pck(PMC_PCK_3);
kadonotakashi 0:8fdf9a60065b 103 #endif
kadonotakashi 0:8fdf9a60065b 104
kadonotakashi 0:8fdf9a60065b 105 /* Init TC to Counter mode. */
kadonotakashi 0:8fdf9a60065b 106 tc_init(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0, TC_CMR_TCCLKS_TIMER_CLOCK4);
kadonotakashi 0:8fdf9a60065b 107 tc_init(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_CMR_TCCLKS_TIMER_CLOCK4);
kadonotakashi 0:8fdf9a60065b 108
kadonotakashi 0:8fdf9a60065b 109
kadonotakashi 0:8fdf9a60065b 110 NVIC_DisableIRQ(TICKER_COUNTER_IRQn0);
kadonotakashi 0:8fdf9a60065b 111
kadonotakashi 0:8fdf9a60065b 112 NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn0);
kadonotakashi 0:8fdf9a60065b 113 NVIC_SetPriority(TICKER_COUNTER_IRQn0, 0);
kadonotakashi 0:8fdf9a60065b 114 NVIC_EnableIRQ(TICKER_COUNTER_IRQn0);
kadonotakashi 0:8fdf9a60065b 115 tc_enable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0, TC_IER_COVFS);
kadonotakashi 0:8fdf9a60065b 116
kadonotakashi 0:8fdf9a60065b 117 tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
kadonotakashi 0:8fdf9a60065b 118 }
kadonotakashi 0:8fdf9a60065b 119
kadonotakashi 0:8fdf9a60065b 120
kadonotakashi 0:8fdf9a60065b 121 uint32_t us_ticker_read()
kadonotakashi 0:8fdf9a60065b 122 {
kadonotakashi 0:8fdf9a60065b 123 if (!us_ticker_inited)
kadonotakashi 0:8fdf9a60065b 124 us_ticker_init();
kadonotakashi 0:8fdf9a60065b 125
kadonotakashi 0:8fdf9a60065b 126 uint32_t counter_value=0;
kadonotakashi 0:8fdf9a60065b 127 uint16_t tickerbefore=0;
kadonotakashi 0:8fdf9a60065b 128 do {
kadonotakashi 0:8fdf9a60065b 129 tickerbefore=us_ticker_16bit_counter;
kadonotakashi 0:8fdf9a60065b 130 counter_value=tc_read_cv(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
kadonotakashi 0:8fdf9a60065b 131 } while(tickerbefore!=us_ticker_16bit_counter);
kadonotakashi 0:8fdf9a60065b 132
kadonotakashi 0:8fdf9a60065b 133 return counter_value+(OVERFLOW_16bit_VALUE*us_ticker_16bit_counter);
kadonotakashi 0:8fdf9a60065b 134 }
kadonotakashi 0:8fdf9a60065b 135
kadonotakashi 0:8fdf9a60065b 136 void us_ticker_set_interrupt(timestamp_t timestamp)
kadonotakashi 0:8fdf9a60065b 137 {
kadonotakashi 0:8fdf9a60065b 138 uint32_t cur_time;
kadonotakashi 0:8fdf9a60065b 139 int32_t delta;
kadonotakashi 0:8fdf9a60065b 140
kadonotakashi 0:8fdf9a60065b 141 cur_time = us_ticker_read();
kadonotakashi 0:8fdf9a60065b 142 delta = (int32_t)((uint32_t)timestamp - cur_time);
kadonotakashi 0:8fdf9a60065b 143 if (delta < 0) {
kadonotakashi 0:8fdf9a60065b 144 /* Event already occurred in past */
kadonotakashi 0:8fdf9a60065b 145 us_ticker_irq_handler();
kadonotakashi 0:8fdf9a60065b 146 return;
kadonotakashi 0:8fdf9a60065b 147 }
kadonotakashi 0:8fdf9a60065b 148
kadonotakashi 0:8fdf9a60065b 149 uint16_t interruptat=0;
kadonotakashi 0:8fdf9a60065b 150
kadonotakashi 0:8fdf9a60065b 151 if(delta > OVERFLOW_16bit_VALUE) {
kadonotakashi 0:8fdf9a60065b 152 us_ticker_interrupt_counter= (delta/OVERFLOW_16bit_VALUE) -1;
kadonotakashi 0:8fdf9a60065b 153 us_ticker_interrupt_offset=delta%OVERFLOW_16bit_VALUE;
kadonotakashi 0:8fdf9a60065b 154 interruptat=OVERFLOW_16bit_VALUE;
kadonotakashi 0:8fdf9a60065b 155 } else {
kadonotakashi 0:8fdf9a60065b 156 us_ticker_interrupt_counter=0;
kadonotakashi 0:8fdf9a60065b 157 us_ticker_interrupt_offset=0;
kadonotakashi 0:8fdf9a60065b 158 interruptat=delta;
kadonotakashi 0:8fdf9a60065b 159 }
kadonotakashi 0:8fdf9a60065b 160
kadonotakashi 0:8fdf9a60065b 161 NVIC_DisableIRQ(TICKER_COUNTER_IRQn1);
kadonotakashi 0:8fdf9a60065b 162
kadonotakashi 0:8fdf9a60065b 163 tc_write_rc(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, (uint32_t)interruptat);
kadonotakashi 0:8fdf9a60065b 164
kadonotakashi 0:8fdf9a60065b 165 NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn1);
kadonotakashi 0:8fdf9a60065b 166 NVIC_SetPriority(TICKER_COUNTER_IRQn1, 0);
kadonotakashi 0:8fdf9a60065b 167 NVIC_EnableIRQ(TICKER_COUNTER_IRQn1);
kadonotakashi 0:8fdf9a60065b 168 tc_enable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_IDR_CPCS );
kadonotakashi 0:8fdf9a60065b 169
kadonotakashi 0:8fdf9a60065b 170 tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
kadonotakashi 0:8fdf9a60065b 171 }
kadonotakashi 0:8fdf9a60065b 172
kadonotakashi 0:8fdf9a60065b 173 void us_ticker_fire_interrupt(void)
kadonotakashi 0:8fdf9a60065b 174 {
kadonotakashi 0:8fdf9a60065b 175 NVIC_SetPendingIRQ(TICKER_COUNTER_IRQn1);
kadonotakashi 0:8fdf9a60065b 176 }
kadonotakashi 0:8fdf9a60065b 177
kadonotakashi 0:8fdf9a60065b 178 void us_ticker_disable_interrupt(void)
kadonotakashi 0:8fdf9a60065b 179 {
kadonotakashi 0:8fdf9a60065b 180 tc_stop(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
kadonotakashi 0:8fdf9a60065b 181 tc_disable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_IDR_CPCS);
kadonotakashi 0:8fdf9a60065b 182 NVIC_DisableIRQ(TICKER_COUNTER_IRQn1);
kadonotakashi 0:8fdf9a60065b 183 }
kadonotakashi 0:8fdf9a60065b 184
kadonotakashi 0:8fdf9a60065b 185 void us_ticker_clear_interrupt(void)
kadonotakashi 0:8fdf9a60065b 186 {
kadonotakashi 0:8fdf9a60065b 187 NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn1);
kadonotakashi 0:8fdf9a60065b 188 }
kadonotakashi 0:8fdf9a60065b 189
kadonotakashi 0:8fdf9a60065b 190 void us_ticker_free(void)
kadonotakashi 0:8fdf9a60065b 191 {
kadonotakashi 0:8fdf9a60065b 192
kadonotakashi 0:8fdf9a60065b 193 }