takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/spi/spi_driver.h@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /**
kadonotakashi 0:8fdf9a60065b 2 * \file
kadonotakashi 0:8fdf9a60065b 3 *
kadonotakashi 0:8fdf9a60065b 4 * \brief Serial Peripheral Interface (SPI) driver for SAM.
kadonotakashi 0:8fdf9a60065b 5 *
kadonotakashi 0:8fdf9a60065b 6 * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * \asf_license_start
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * \page License
kadonotakashi 0:8fdf9a60065b 11 *
kadonotakashi 0:8fdf9a60065b 12 * Redistribution and use in source and binary forms, with or without
kadonotakashi 0:8fdf9a60065b 13 * modification, are permitted provided that the following conditions are met:
kadonotakashi 0:8fdf9a60065b 14 *
kadonotakashi 0:8fdf9a60065b 15 * 1. Redistributions of source code must retain the above copyright notice,
kadonotakashi 0:8fdf9a60065b 16 * this list of conditions and the following disclaimer.
kadonotakashi 0:8fdf9a60065b 17 *
kadonotakashi 0:8fdf9a60065b 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
kadonotakashi 0:8fdf9a60065b 19 * this list of conditions and the following disclaimer in the documentation
kadonotakashi 0:8fdf9a60065b 20 * and/or other materials provided with the distribution.
kadonotakashi 0:8fdf9a60065b 21 *
kadonotakashi 0:8fdf9a60065b 22 * 3. The name of Atmel may not be used to endorse or promote products derived
kadonotakashi 0:8fdf9a60065b 23 * from this software without specific prior written permission.
kadonotakashi 0:8fdf9a60065b 24 *
kadonotakashi 0:8fdf9a60065b 25 * 4. This software may only be redistributed and used in connection with an
kadonotakashi 0:8fdf9a60065b 26 * Atmel microcontroller product.
kadonotakashi 0:8fdf9a60065b 27 *
kadonotakashi 0:8fdf9a60065b 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
kadonotakashi 0:8fdf9a60065b 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
kadonotakashi 0:8fdf9a60065b 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
kadonotakashi 0:8fdf9a60065b 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
kadonotakashi 0:8fdf9a60065b 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
kadonotakashi 0:8fdf9a60065b 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
kadonotakashi 0:8fdf9a60065b 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
kadonotakashi 0:8fdf9a60065b 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
kadonotakashi 0:8fdf9a60065b 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
kadonotakashi 0:8fdf9a60065b 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
kadonotakashi 0:8fdf9a60065b 38 * POSSIBILITY OF SUCH DAMAGE.
kadonotakashi 0:8fdf9a60065b 39 *
kadonotakashi 0:8fdf9a60065b 40 * \asf_license_stop
kadonotakashi 0:8fdf9a60065b 41 *
kadonotakashi 0:8fdf9a60065b 42 */
kadonotakashi 0:8fdf9a60065b 43 /*
kadonotakashi 0:8fdf9a60065b 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
kadonotakashi 0:8fdf9a60065b 45 */
kadonotakashi 0:8fdf9a60065b 46
kadonotakashi 0:8fdf9a60065b 47 #ifndef SPI_H_INCLUDED
kadonotakashi 0:8fdf9a60065b 48 #define SPI_H_INCLUDED
kadonotakashi 0:8fdf9a60065b 49
kadonotakashi 0:8fdf9a60065b 50 #include "compiler.h"
kadonotakashi 0:8fdf9a60065b 51
kadonotakashi 0:8fdf9a60065b 52 /// @cond 0
kadonotakashi 0:8fdf9a60065b 53 /**INDENT-OFF**/
kadonotakashi 0:8fdf9a60065b 54 #ifdef __cplusplus
kadonotakashi 0:8fdf9a60065b 55 extern "C" {
kadonotakashi 0:8fdf9a60065b 56 #endif
kadonotakashi 0:8fdf9a60065b 57 /**INDENT-ON**/
kadonotakashi 0:8fdf9a60065b 58 /// @endcond
kadonotakashi 0:8fdf9a60065b 59
kadonotakashi 0:8fdf9a60065b 60 /** Time-out value (number of attempts). */
kadonotakashi 0:8fdf9a60065b 61 #define SPI_TIMEOUT 15000
kadonotakashi 0:8fdf9a60065b 62
kadonotakashi 0:8fdf9a60065b 63 /** Status codes used by the SPI driver. */
kadonotakashi 0:8fdf9a60065b 64 typedef enum {
kadonotakashi 0:8fdf9a60065b 65 SPI_ERROR = -1,
kadonotakashi 0:8fdf9a60065b 66 SPI_OK = 0,
kadonotakashi 0:8fdf9a60065b 67 SPI_ERROR_TIMEOUT = 1,
kadonotakashi 0:8fdf9a60065b 68 SPI_ERROR_ARGUMENT,
kadonotakashi 0:8fdf9a60065b 69 SPI_ERROR_OVERRUN,
kadonotakashi 0:8fdf9a60065b 70 SPI_ERROR_MODE_FAULT,
kadonotakashi 0:8fdf9a60065b 71 SPI_ERROR_OVERRUN_AND_MODE_FAULT
kadonotakashi 0:8fdf9a60065b 72 } spi_status_t;
kadonotakashi 0:8fdf9a60065b 73
kadonotakashi 0:8fdf9a60065b 74 /** SPI Chip Select behavior modes while transferring. */
kadonotakashi 0:8fdf9a60065b 75 typedef enum spi_cs_behavior {
kadonotakashi 0:8fdf9a60065b 76 /** CS does not rise until a new transfer is requested on different chip select. */
kadonotakashi 0:8fdf9a60065b 77 SPI_CS_KEEP_LOW = SPI_CSR_CSAAT,
kadonotakashi 0:8fdf9a60065b 78 /** CS rises if there is no more data to transfer. */
kadonotakashi 0:8fdf9a60065b 79 SPI_CS_RISE_NO_TX = 0,
kadonotakashi 0:8fdf9a60065b 80 /** CS is de-asserted systematically during a time DLYBCS. */
kadonotakashi 0:8fdf9a60065b 81 SPI_CS_RISE_FORCED = SPI_CSR_CSNAAT
kadonotakashi 0:8fdf9a60065b 82 } spi_cs_behavior_t;
kadonotakashi 0:8fdf9a60065b 83
kadonotakashi 0:8fdf9a60065b 84 /**
kadonotakashi 0:8fdf9a60065b 85 * \brief Generate Peripheral Chip Select Value from Chip Select ID
kadonotakashi 0:8fdf9a60065b 86 * \note When chip select n is working, PCS bit n is set to low level.
kadonotakashi 0:8fdf9a60065b 87 *
kadonotakashi 0:8fdf9a60065b 88 * \param chip_sel_id The chip select number used
kadonotakashi 0:8fdf9a60065b 89 */
kadonotakashi 0:8fdf9a60065b 90 #define spi_get_pcs(chip_sel_id) ((~(1u<<(chip_sel_id)))&0xF)
kadonotakashi 0:8fdf9a60065b 91
kadonotakashi 0:8fdf9a60065b 92 /**
kadonotakashi 0:8fdf9a60065b 93 * \brief Reset SPI and set it to Slave mode.
kadonotakashi 0:8fdf9a60065b 94 *
kadonotakashi 0:8fdf9a60065b 95 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 96 */
kadonotakashi 0:8fdf9a60065b 97 static inline void spi_reset(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 98 {
kadonotakashi 0:8fdf9a60065b 99 p_spi->SPI_CR = SPI_CR_SWRST;
kadonotakashi 0:8fdf9a60065b 100 }
kadonotakashi 0:8fdf9a60065b 101
kadonotakashi 0:8fdf9a60065b 102 /**
kadonotakashi 0:8fdf9a60065b 103 * \brief Enable SPI.
kadonotakashi 0:8fdf9a60065b 104 *
kadonotakashi 0:8fdf9a60065b 105 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 106 */
kadonotakashi 0:8fdf9a60065b 107 static inline void spi_enable(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 108 {
kadonotakashi 0:8fdf9a60065b 109 p_spi->SPI_CR = SPI_CR_SPIEN;
kadonotakashi 0:8fdf9a60065b 110 }
kadonotakashi 0:8fdf9a60065b 111
kadonotakashi 0:8fdf9a60065b 112 /**
kadonotakashi 0:8fdf9a60065b 113 * \brief Disable SPI.
kadonotakashi 0:8fdf9a60065b 114 *
kadonotakashi 0:8fdf9a60065b 115 * \note CS is de-asserted, which indicates that the last data is done, and user
kadonotakashi 0:8fdf9a60065b 116 * should check TX_EMPTY before disabling SPI.
kadonotakashi 0:8fdf9a60065b 117 *
kadonotakashi 0:8fdf9a60065b 118 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 119 */
kadonotakashi 0:8fdf9a60065b 120 static inline void spi_disable(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 121 {
kadonotakashi 0:8fdf9a60065b 122 p_spi->SPI_CR = SPI_CR_SPIDIS;
kadonotakashi 0:8fdf9a60065b 123 }
kadonotakashi 0:8fdf9a60065b 124
kadonotakashi 0:8fdf9a60065b 125 /**
kadonotakashi 0:8fdf9a60065b 126 * \brief Issue a LASTXFER command.
kadonotakashi 0:8fdf9a60065b 127 * The next transfer is the last transfer and after that CS is de-asserted.
kadonotakashi 0:8fdf9a60065b 128 *
kadonotakashi 0:8fdf9a60065b 129 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 130 */
kadonotakashi 0:8fdf9a60065b 131 static inline void spi_set_lastxfer(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 132 {
kadonotakashi 0:8fdf9a60065b 133 p_spi->SPI_CR = SPI_CR_LASTXFER;
kadonotakashi 0:8fdf9a60065b 134 }
kadonotakashi 0:8fdf9a60065b 135
kadonotakashi 0:8fdf9a60065b 136 /**
kadonotakashi 0:8fdf9a60065b 137 * \brief Set SPI to Master mode.
kadonotakashi 0:8fdf9a60065b 138 *
kadonotakashi 0:8fdf9a60065b 139 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 140 */
kadonotakashi 0:8fdf9a60065b 141 static inline void spi_set_master_mode(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 142 {
kadonotakashi 0:8fdf9a60065b 143 p_spi->SPI_MR |= SPI_MR_MSTR;
kadonotakashi 0:8fdf9a60065b 144 }
kadonotakashi 0:8fdf9a60065b 145
kadonotakashi 0:8fdf9a60065b 146 /**
kadonotakashi 0:8fdf9a60065b 147 * \brief Set SPI to Slave mode.
kadonotakashi 0:8fdf9a60065b 148 *
kadonotakashi 0:8fdf9a60065b 149 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 150 */
kadonotakashi 0:8fdf9a60065b 151 static inline void spi_set_slave_mode(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 152 {
kadonotakashi 0:8fdf9a60065b 153 p_spi->SPI_MR &= (~SPI_MR_MSTR);
kadonotakashi 0:8fdf9a60065b 154 }
kadonotakashi 0:8fdf9a60065b 155
kadonotakashi 0:8fdf9a60065b 156 /**
kadonotakashi 0:8fdf9a60065b 157 * \brief Get SPI work mode.
kadonotakashi 0:8fdf9a60065b 158 *
kadonotakashi 0:8fdf9a60065b 159 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 160 *
kadonotakashi 0:8fdf9a60065b 161 * \return 1 for master mode, 0 for slave mode.
kadonotakashi 0:8fdf9a60065b 162 */
kadonotakashi 0:8fdf9a60065b 163 static inline uint32_t spi_get_mode(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 164 {
kadonotakashi 0:8fdf9a60065b 165 if (p_spi->SPI_MR & SPI_MR_MSTR) {
kadonotakashi 0:8fdf9a60065b 166 return 1;
kadonotakashi 0:8fdf9a60065b 167 } else {
kadonotakashi 0:8fdf9a60065b 168 return 0;
kadonotakashi 0:8fdf9a60065b 169 }
kadonotakashi 0:8fdf9a60065b 170 }
kadonotakashi 0:8fdf9a60065b 171
kadonotakashi 0:8fdf9a60065b 172 /**
kadonotakashi 0:8fdf9a60065b 173 * \brief Set Variable Peripheral Select.
kadonotakashi 0:8fdf9a60065b 174 * Peripheral Chip Select can be controlled by SPI_TDR.
kadonotakashi 0:8fdf9a60065b 175 *
kadonotakashi 0:8fdf9a60065b 176 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 177 */
kadonotakashi 0:8fdf9a60065b 178 static inline void spi_set_variable_peripheral_select(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 179 {
kadonotakashi 0:8fdf9a60065b 180 p_spi->SPI_MR |= SPI_MR_PS;
kadonotakashi 0:8fdf9a60065b 181 }
kadonotakashi 0:8fdf9a60065b 182
kadonotakashi 0:8fdf9a60065b 183 /**
kadonotakashi 0:8fdf9a60065b 184 * \brief Set Fixed Peripheral Select.
kadonotakashi 0:8fdf9a60065b 185 * Peripheral Chip Select is controlled by SPI_MR.
kadonotakashi 0:8fdf9a60065b 186 *
kadonotakashi 0:8fdf9a60065b 187 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 188 */
kadonotakashi 0:8fdf9a60065b 189 static inline void spi_set_fixed_peripheral_select(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 190 {
kadonotakashi 0:8fdf9a60065b 191 p_spi->SPI_MR &= (~SPI_MR_PS);
kadonotakashi 0:8fdf9a60065b 192 }
kadonotakashi 0:8fdf9a60065b 193
kadonotakashi 0:8fdf9a60065b 194 /**
kadonotakashi 0:8fdf9a60065b 195 * \brief Get Peripheral Select mode.
kadonotakashi 0:8fdf9a60065b 196 *
kadonotakashi 0:8fdf9a60065b 197 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 198 *
kadonotakashi 0:8fdf9a60065b 199 * \return 1 for Variable mode, 0 for fixed mode.
kadonotakashi 0:8fdf9a60065b 200 */
kadonotakashi 0:8fdf9a60065b 201 static inline uint32_t spi_get_peripheral_select_mode(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 202 {
kadonotakashi 0:8fdf9a60065b 203 if (p_spi->SPI_MR & SPI_MR_PS) {
kadonotakashi 0:8fdf9a60065b 204 return 1;
kadonotakashi 0:8fdf9a60065b 205 } else {
kadonotakashi 0:8fdf9a60065b 206 return 0;
kadonotakashi 0:8fdf9a60065b 207 }
kadonotakashi 0:8fdf9a60065b 208 }
kadonotakashi 0:8fdf9a60065b 209
kadonotakashi 0:8fdf9a60065b 210 /**
kadonotakashi 0:8fdf9a60065b 211 * \brief Enable Peripheral Select Decode.
kadonotakashi 0:8fdf9a60065b 212 *
kadonotakashi 0:8fdf9a60065b 213 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 214 */
kadonotakashi 0:8fdf9a60065b 215 static inline void spi_enable_peripheral_select_decode(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 216 {
kadonotakashi 0:8fdf9a60065b 217 p_spi->SPI_MR |= SPI_MR_PCSDEC;
kadonotakashi 0:8fdf9a60065b 218 }
kadonotakashi 0:8fdf9a60065b 219
kadonotakashi 0:8fdf9a60065b 220 /**
kadonotakashi 0:8fdf9a60065b 221 * \brief Disable Peripheral Select Decode.
kadonotakashi 0:8fdf9a60065b 222 *
kadonotakashi 0:8fdf9a60065b 223 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 224 */
kadonotakashi 0:8fdf9a60065b 225 static inline void spi_disable_peripheral_select_decode(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 226 {
kadonotakashi 0:8fdf9a60065b 227 p_spi->SPI_MR &= (~SPI_MR_PCSDEC);
kadonotakashi 0:8fdf9a60065b 228 }
kadonotakashi 0:8fdf9a60065b 229
kadonotakashi 0:8fdf9a60065b 230 /**
kadonotakashi 0:8fdf9a60065b 231 * \brief Get Peripheral Select Decode mode.
kadonotakashi 0:8fdf9a60065b 232 *
kadonotakashi 0:8fdf9a60065b 233 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 234 *
kadonotakashi 0:8fdf9a60065b 235 * \return 1 for decode mode, 0 for direct mode.
kadonotakashi 0:8fdf9a60065b 236 */
kadonotakashi 0:8fdf9a60065b 237 static inline uint32_t spi_get_peripheral_select_decode_setting(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 238 {
kadonotakashi 0:8fdf9a60065b 239 if (p_spi->SPI_MR & SPI_MR_PCSDEC) {
kadonotakashi 0:8fdf9a60065b 240 return 1;
kadonotakashi 0:8fdf9a60065b 241 } else {
kadonotakashi 0:8fdf9a60065b 242 return 0;
kadonotakashi 0:8fdf9a60065b 243 }
kadonotakashi 0:8fdf9a60065b 244 }
kadonotakashi 0:8fdf9a60065b 245
kadonotakashi 0:8fdf9a60065b 246 /**
kadonotakashi 0:8fdf9a60065b 247 * \brief Enable Mode Fault Detection.
kadonotakashi 0:8fdf9a60065b 248 *
kadonotakashi 0:8fdf9a60065b 249 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 250 */
kadonotakashi 0:8fdf9a60065b 251 static inline void spi_enable_mode_fault_detect(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 252 {
kadonotakashi 0:8fdf9a60065b 253 p_spi->SPI_MR &= (~SPI_MR_MODFDIS);
kadonotakashi 0:8fdf9a60065b 254 }
kadonotakashi 0:8fdf9a60065b 255
kadonotakashi 0:8fdf9a60065b 256 /**
kadonotakashi 0:8fdf9a60065b 257 * \brief Disable Mode Fault Detection.
kadonotakashi 0:8fdf9a60065b 258 *
kadonotakashi 0:8fdf9a60065b 259 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 260 */
kadonotakashi 0:8fdf9a60065b 261 static inline void spi_disable_mode_fault_detect(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 262 {
kadonotakashi 0:8fdf9a60065b 263 p_spi->SPI_MR |= SPI_MR_MODFDIS;
kadonotakashi 0:8fdf9a60065b 264 }
kadonotakashi 0:8fdf9a60065b 265
kadonotakashi 0:8fdf9a60065b 266 /**
kadonotakashi 0:8fdf9a60065b 267 * \brief Check if mode fault detection is enabled.
kadonotakashi 0:8fdf9a60065b 268 *
kadonotakashi 0:8fdf9a60065b 269 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 270 *
kadonotakashi 0:8fdf9a60065b 271 * \return 1 for disabled, 0 for enabled.
kadonotakashi 0:8fdf9a60065b 272 */
kadonotakashi 0:8fdf9a60065b 273 static inline uint32_t spi_get_mode_fault_detect_setting(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 274 {
kadonotakashi 0:8fdf9a60065b 275 if (p_spi->SPI_MR & SPI_MR_MODFDIS) {
kadonotakashi 0:8fdf9a60065b 276 return 1;
kadonotakashi 0:8fdf9a60065b 277 } else {
kadonotakashi 0:8fdf9a60065b 278 return 0;
kadonotakashi 0:8fdf9a60065b 279 }
kadonotakashi 0:8fdf9a60065b 280 }
kadonotakashi 0:8fdf9a60065b 281
kadonotakashi 0:8fdf9a60065b 282 /**
kadonotakashi 0:8fdf9a60065b 283 * \brief Enable waiting RX_EMPTY before transfer starts.
kadonotakashi 0:8fdf9a60065b 284 *
kadonotakashi 0:8fdf9a60065b 285 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 286 */
kadonotakashi 0:8fdf9a60065b 287 static inline void spi_enable_tx_on_rx_empty(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 288 {
kadonotakashi 0:8fdf9a60065b 289 p_spi->SPI_MR |= SPI_MR_WDRBT;
kadonotakashi 0:8fdf9a60065b 290 }
kadonotakashi 0:8fdf9a60065b 291
kadonotakashi 0:8fdf9a60065b 292 /**
kadonotakashi 0:8fdf9a60065b 293 * \brief Disable waiting RX_EMPTY before transfer starts.
kadonotakashi 0:8fdf9a60065b 294 *
kadonotakashi 0:8fdf9a60065b 295 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 296 */
kadonotakashi 0:8fdf9a60065b 297 static inline void spi_disable_tx_on_rx_empty(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 298 {
kadonotakashi 0:8fdf9a60065b 299 p_spi->SPI_MR &= (~SPI_MR_WDRBT);
kadonotakashi 0:8fdf9a60065b 300 }
kadonotakashi 0:8fdf9a60065b 301
kadonotakashi 0:8fdf9a60065b 302 /**
kadonotakashi 0:8fdf9a60065b 303 * \brief Check if SPI waits RX_EMPTY before transfer starts.
kadonotakashi 0:8fdf9a60065b 304 *
kadonotakashi 0:8fdf9a60065b 305 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 306 *
kadonotakashi 0:8fdf9a60065b 307 * \return 1 for SPI waits, 0 for no wait.
kadonotakashi 0:8fdf9a60065b 308 */
kadonotakashi 0:8fdf9a60065b 309 static inline uint32_t spi_get_tx_on_rx_empty_setting(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 310 {
kadonotakashi 0:8fdf9a60065b 311 if (p_spi->SPI_MR & SPI_MR_WDRBT) {
kadonotakashi 0:8fdf9a60065b 312 return 1;
kadonotakashi 0:8fdf9a60065b 313 } else {
kadonotakashi 0:8fdf9a60065b 314 return 0;
kadonotakashi 0:8fdf9a60065b 315 }
kadonotakashi 0:8fdf9a60065b 316 }
kadonotakashi 0:8fdf9a60065b 317
kadonotakashi 0:8fdf9a60065b 318 /**
kadonotakashi 0:8fdf9a60065b 319 * \brief Enable loopback mode.
kadonotakashi 0:8fdf9a60065b 320 *
kadonotakashi 0:8fdf9a60065b 321 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 322 */
kadonotakashi 0:8fdf9a60065b 323 static inline void spi_enable_loopback(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 324 {
kadonotakashi 0:8fdf9a60065b 325 p_spi->SPI_MR |= SPI_MR_LLB;
kadonotakashi 0:8fdf9a60065b 326 }
kadonotakashi 0:8fdf9a60065b 327
kadonotakashi 0:8fdf9a60065b 328 /**
kadonotakashi 0:8fdf9a60065b 329 * \brief Disable loopback mode.
kadonotakashi 0:8fdf9a60065b 330 *
kadonotakashi 0:8fdf9a60065b 331 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 332 */
kadonotakashi 0:8fdf9a60065b 333 static inline void spi_disable_loopback(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 334 {
kadonotakashi 0:8fdf9a60065b 335 p_spi->SPI_MR &= (~SPI_MR_LLB);
kadonotakashi 0:8fdf9a60065b 336 }
kadonotakashi 0:8fdf9a60065b 337
kadonotakashi 0:8fdf9a60065b 338 void spi_enable_clock(Spi *p_spi);
kadonotakashi 0:8fdf9a60065b 339 void spi_disable_clock(Spi *p_spi);
kadonotakashi 0:8fdf9a60065b 340 void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value);
kadonotakashi 0:8fdf9a60065b 341 void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay);
kadonotakashi 0:8fdf9a60065b 342 spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs);
kadonotakashi 0:8fdf9a60065b 343 spi_status_t spi_write(Spi *p_spi, uint16_t us_data, uint8_t uc_pcs,
kadonotakashi 0:8fdf9a60065b 344 uint8_t uc_last);
kadonotakashi 0:8fdf9a60065b 345
kadonotakashi 0:8fdf9a60065b 346 /**
kadonotakashi 0:8fdf9a60065b 347 * \brief Read status register.
kadonotakashi 0:8fdf9a60065b 348 *
kadonotakashi 0:8fdf9a60065b 349 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 350 *
kadonotakashi 0:8fdf9a60065b 351 * \return SPI status register value.
kadonotakashi 0:8fdf9a60065b 352 */
kadonotakashi 0:8fdf9a60065b 353 static inline uint32_t spi_read_status(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 354 {
kadonotakashi 0:8fdf9a60065b 355 return p_spi->SPI_SR;
kadonotakashi 0:8fdf9a60065b 356 }
kadonotakashi 0:8fdf9a60065b 357
kadonotakashi 0:8fdf9a60065b 358 /**
kadonotakashi 0:8fdf9a60065b 359 * \brief Test if the SPI is enabled.
kadonotakashi 0:8fdf9a60065b 360 *
kadonotakashi 0:8fdf9a60065b 361 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 362 *
kadonotakashi 0:8fdf9a60065b 363 * \return 1 if the SPI is enabled, otherwise 0.
kadonotakashi 0:8fdf9a60065b 364 */
kadonotakashi 0:8fdf9a60065b 365 static inline uint32_t spi_is_enabled(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 366 {
kadonotakashi 0:8fdf9a60065b 367 if (p_spi->SPI_SR & SPI_SR_SPIENS) {
kadonotakashi 0:8fdf9a60065b 368 return 1;
kadonotakashi 0:8fdf9a60065b 369 } else {
kadonotakashi 0:8fdf9a60065b 370 return 0;
kadonotakashi 0:8fdf9a60065b 371 }
kadonotakashi 0:8fdf9a60065b 372 }
kadonotakashi 0:8fdf9a60065b 373
kadonotakashi 0:8fdf9a60065b 374 /**
kadonotakashi 0:8fdf9a60065b 375 * \brief Put one data to a SPI peripheral.
kadonotakashi 0:8fdf9a60065b 376 *
kadonotakashi 0:8fdf9a60065b 377 * \param p_spi Base address of the SPI instance.
kadonotakashi 0:8fdf9a60065b 378 * \param data The data byte to be loaded
kadonotakashi 0:8fdf9a60065b 379 *
kadonotakashi 0:8fdf9a60065b 380 */
kadonotakashi 0:8fdf9a60065b 381 static inline void spi_put(Spi *p_spi, uint16_t data)
kadonotakashi 0:8fdf9a60065b 382 {
kadonotakashi 0:8fdf9a60065b 383 p_spi->SPI_TDR = SPI_TDR_TD(data);
kadonotakashi 0:8fdf9a60065b 384 }
kadonotakashi 0:8fdf9a60065b 385
kadonotakashi 0:8fdf9a60065b 386 /** \brief Get one data to a SPI peripheral.
kadonotakashi 0:8fdf9a60065b 387 *
kadonotakashi 0:8fdf9a60065b 388 * \param p_spi Base address of the SPI instance.
kadonotakashi 0:8fdf9a60065b 389 * \return The data byte
kadonotakashi 0:8fdf9a60065b 390 *
kadonotakashi 0:8fdf9a60065b 391 */
kadonotakashi 0:8fdf9a60065b 392 static inline uint16_t spi_get(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 393 {
kadonotakashi 0:8fdf9a60065b 394 return (p_spi->SPI_RDR & SPI_RDR_RD_Msk);
kadonotakashi 0:8fdf9a60065b 395 }
kadonotakashi 0:8fdf9a60065b 396
kadonotakashi 0:8fdf9a60065b 397 /**
kadonotakashi 0:8fdf9a60065b 398 * \brief Check if all transmissions are complete.
kadonotakashi 0:8fdf9a60065b 399 *
kadonotakashi 0:8fdf9a60065b 400 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 401 *
kadonotakashi 0:8fdf9a60065b 402 * \retval 1 if transmissions are complete.
kadonotakashi 0:8fdf9a60065b 403 * \retval 0 if transmissions are not complete.
kadonotakashi 0:8fdf9a60065b 404 */
kadonotakashi 0:8fdf9a60065b 405 static inline uint32_t spi_is_tx_empty(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 406 {
kadonotakashi 0:8fdf9a60065b 407 if (p_spi->SPI_SR & SPI_SR_TXEMPTY) {
kadonotakashi 0:8fdf9a60065b 408 return 1;
kadonotakashi 0:8fdf9a60065b 409 } else {
kadonotakashi 0:8fdf9a60065b 410 return 0;
kadonotakashi 0:8fdf9a60065b 411 }
kadonotakashi 0:8fdf9a60065b 412 }
kadonotakashi 0:8fdf9a60065b 413
kadonotakashi 0:8fdf9a60065b 414 /**
kadonotakashi 0:8fdf9a60065b 415 * \brief Check if all transmissions are ready.
kadonotakashi 0:8fdf9a60065b 416 *
kadonotakashi 0:8fdf9a60065b 417 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 418 *
kadonotakashi 0:8fdf9a60065b 419 * \retval 1 if transmissions are complete.
kadonotakashi 0:8fdf9a60065b 420 * \retval 0 if transmissions are not complete.
kadonotakashi 0:8fdf9a60065b 421 */
kadonotakashi 0:8fdf9a60065b 422 static inline uint32_t spi_is_tx_ready(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 423 {
kadonotakashi 0:8fdf9a60065b 424 if (p_spi->SPI_SR & SPI_SR_TDRE) {
kadonotakashi 0:8fdf9a60065b 425 return 1;
kadonotakashi 0:8fdf9a60065b 426 } else {
kadonotakashi 0:8fdf9a60065b 427 return 0;
kadonotakashi 0:8fdf9a60065b 428 }
kadonotakashi 0:8fdf9a60065b 429 }
kadonotakashi 0:8fdf9a60065b 430
kadonotakashi 0:8fdf9a60065b 431 /**
kadonotakashi 0:8fdf9a60065b 432 * \brief Check if the SPI contains a received character.
kadonotakashi 0:8fdf9a60065b 433 *
kadonotakashi 0:8fdf9a60065b 434 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 435 *
kadonotakashi 0:8fdf9a60065b 436 * \return 1 if the SPI Receive Holding Register is full, otherwise 0.
kadonotakashi 0:8fdf9a60065b 437 */
kadonotakashi 0:8fdf9a60065b 438 static inline uint32_t spi_is_rx_full(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 439 {
kadonotakashi 0:8fdf9a60065b 440 if (p_spi->SPI_SR & SPI_SR_RDRF) {
kadonotakashi 0:8fdf9a60065b 441 return 1;
kadonotakashi 0:8fdf9a60065b 442 } else {
kadonotakashi 0:8fdf9a60065b 443 return 0;
kadonotakashi 0:8fdf9a60065b 444 }
kadonotakashi 0:8fdf9a60065b 445 }
kadonotakashi 0:8fdf9a60065b 446
kadonotakashi 0:8fdf9a60065b 447 /**
kadonotakashi 0:8fdf9a60065b 448 * \brief Check if all receptions are ready.
kadonotakashi 0:8fdf9a60065b 449 *
kadonotakashi 0:8fdf9a60065b 450 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 451 *
kadonotakashi 0:8fdf9a60065b 452 * \return 1 if the SPI Receiver is ready, otherwise 0.
kadonotakashi 0:8fdf9a60065b 453 */
kadonotakashi 0:8fdf9a60065b 454 static inline uint32_t spi_is_rx_ready(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 455 {
kadonotakashi 0:8fdf9a60065b 456 if ((p_spi->SPI_SR & (SPI_SR_RDRF | SPI_SR_TXEMPTY))
kadonotakashi 0:8fdf9a60065b 457 == (SPI_SR_RDRF | SPI_SR_TXEMPTY)) {
kadonotakashi 0:8fdf9a60065b 458 return 1;
kadonotakashi 0:8fdf9a60065b 459 } else {
kadonotakashi 0:8fdf9a60065b 460 return 0;
kadonotakashi 0:8fdf9a60065b 461 }
kadonotakashi 0:8fdf9a60065b 462 }
kadonotakashi 0:8fdf9a60065b 463
kadonotakashi 0:8fdf9a60065b 464 /**
kadonotakashi 0:8fdf9a60065b 465 * \brief Enable SPI interrupts.
kadonotakashi 0:8fdf9a60065b 466 *
kadonotakashi 0:8fdf9a60065b 467 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 468 * \param ul_sources Interrupts to be enabled.
kadonotakashi 0:8fdf9a60065b 469 */
kadonotakashi 0:8fdf9a60065b 470 static inline void spi_enable_interrupt(Spi *p_spi, uint32_t ul_sources)
kadonotakashi 0:8fdf9a60065b 471 {
kadonotakashi 0:8fdf9a60065b 472 p_spi->SPI_IER = ul_sources;
kadonotakashi 0:8fdf9a60065b 473 }
kadonotakashi 0:8fdf9a60065b 474
kadonotakashi 0:8fdf9a60065b 475 /**
kadonotakashi 0:8fdf9a60065b 476 * \brief Disable SPI interrupts.
kadonotakashi 0:8fdf9a60065b 477 *
kadonotakashi 0:8fdf9a60065b 478 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 479 * \param ul_sources Interrupts to be disabled.
kadonotakashi 0:8fdf9a60065b 480 */
kadonotakashi 0:8fdf9a60065b 481 static inline void spi_disable_interrupt(Spi *p_spi, uint32_t ul_sources)
kadonotakashi 0:8fdf9a60065b 482 {
kadonotakashi 0:8fdf9a60065b 483 p_spi->SPI_IDR = ul_sources;
kadonotakashi 0:8fdf9a60065b 484 }
kadonotakashi 0:8fdf9a60065b 485
kadonotakashi 0:8fdf9a60065b 486 /**
kadonotakashi 0:8fdf9a60065b 487 * \brief Read SPI interrupt mask.
kadonotakashi 0:8fdf9a60065b 488 *
kadonotakashi 0:8fdf9a60065b 489 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 490 *
kadonotakashi 0:8fdf9a60065b 491 * \return The interrupt mask value.
kadonotakashi 0:8fdf9a60065b 492 */
kadonotakashi 0:8fdf9a60065b 493 static inline uint32_t spi_read_interrupt_mask(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 494 {
kadonotakashi 0:8fdf9a60065b 495 return p_spi->SPI_IMR;
kadonotakashi 0:8fdf9a60065b 496 }
kadonotakashi 0:8fdf9a60065b 497
kadonotakashi 0:8fdf9a60065b 498 void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch,
kadonotakashi 0:8fdf9a60065b 499 uint32_t ul_polarity);
kadonotakashi 0:8fdf9a60065b 500 void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase);
kadonotakashi 0:8fdf9a60065b 501 void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch,
kadonotakashi 0:8fdf9a60065b 502 uint32_t ul_cs_behavior);
kadonotakashi 0:8fdf9a60065b 503 void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_bits);
kadonotakashi 0:8fdf9a60065b 504 int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck);
kadonotakashi 0:8fdf9a60065b 505 void spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch,
kadonotakashi 0:8fdf9a60065b 506 uint8_t uc_baudrate_divider);
kadonotakashi 0:8fdf9a60065b 507 void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch, uint8_t uc_dlybs,
kadonotakashi 0:8fdf9a60065b 508 uint8_t uc_dlybct);
kadonotakashi 0:8fdf9a60065b 509
kadonotakashi 0:8fdf9a60065b 510 #if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM)
kadonotakashi 0:8fdf9a60065b 511 /**
kadonotakashi 0:8fdf9a60065b 512 * \brief Get PDC registers base address.
kadonotakashi 0:8fdf9a60065b 513 *
kadonotakashi 0:8fdf9a60065b 514 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 515 *
kadonotakashi 0:8fdf9a60065b 516 * \return PDC registers base for PDC driver to access.
kadonotakashi 0:8fdf9a60065b 517 */
kadonotakashi 0:8fdf9a60065b 518 static inline Pdc *spi_get_pdc_base(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 519 {
kadonotakashi 0:8fdf9a60065b 520 return (Pdc *)&(p_spi->SPI_RPR);
kadonotakashi 0:8fdf9a60065b 521 }
kadonotakashi 0:8fdf9a60065b 522 #endif
kadonotakashi 0:8fdf9a60065b 523
kadonotakashi 0:8fdf9a60065b 524 #if (SAM3U || SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
kadonotakashi 0:8fdf9a60065b 525 /**
kadonotakashi 0:8fdf9a60065b 526 * \brief Get transmit data register address for DMA operation.
kadonotakashi 0:8fdf9a60065b 527 *
kadonotakashi 0:8fdf9a60065b 528 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 529 *
kadonotakashi 0:8fdf9a60065b 530 * \return Transmit address for DMA access.
kadonotakashi 0:8fdf9a60065b 531 */
kadonotakashi 0:8fdf9a60065b 532 static inline void *spi_get_tx_access(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 533 {
kadonotakashi 0:8fdf9a60065b 534 return (void *)&(p_spi->SPI_TDR);
kadonotakashi 0:8fdf9a60065b 535 }
kadonotakashi 0:8fdf9a60065b 536
kadonotakashi 0:8fdf9a60065b 537 /**
kadonotakashi 0:8fdf9a60065b 538 * \brief Get receive data register address for DMA operation.
kadonotakashi 0:8fdf9a60065b 539 *
kadonotakashi 0:8fdf9a60065b 540 * \param p_spi Pointer to an SPI instance.
kadonotakashi 0:8fdf9a60065b 541 *
kadonotakashi 0:8fdf9a60065b 542 * \return Receive address for DMA access.
kadonotakashi 0:8fdf9a60065b 543 */
kadonotakashi 0:8fdf9a60065b 544 static inline void *spi_get_rx_access(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 545 {
kadonotakashi 0:8fdf9a60065b 546 return (void *)&(p_spi->SPI_RDR);
kadonotakashi 0:8fdf9a60065b 547 }
kadonotakashi 0:8fdf9a60065b 548 #endif
kadonotakashi 0:8fdf9a60065b 549
kadonotakashi 0:8fdf9a60065b 550 void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable);
kadonotakashi 0:8fdf9a60065b 551 uint32_t spi_get_writeprotect_status(Spi *p_spi);
kadonotakashi 0:8fdf9a60065b 552
kadonotakashi 0:8fdf9a60065b 553 /// @cond 0
kadonotakashi 0:8fdf9a60065b 554 /**INDENT-OFF**/
kadonotakashi 0:8fdf9a60065b 555 #ifdef __cplusplus
kadonotakashi 0:8fdf9a60065b 556 }
kadonotakashi 0:8fdf9a60065b 557 #endif
kadonotakashi 0:8fdf9a60065b 558 /**INDENT-ON**/
kadonotakashi 0:8fdf9a60065b 559 /// @endcond
kadonotakashi 0:8fdf9a60065b 560
kadonotakashi 0:8fdf9a60065b 561 /**
kadonotakashi 0:8fdf9a60065b 562 * \page sam_spi_quickstart Quickstart guide for SAM SPI driver
kadonotakashi 0:8fdf9a60065b 563 *
kadonotakashi 0:8fdf9a60065b 564 * This is the quickstart guide for the \ref spi_group "SAM SPI driver",
kadonotakashi 0:8fdf9a60065b 565 * with step-by-step instructions on how to configure and use the driver in a
kadonotakashi 0:8fdf9a60065b 566 * selection of use cases.
kadonotakashi 0:8fdf9a60065b 567 *
kadonotakashi 0:8fdf9a60065b 568 * The use cases contain several code fragments. The code fragments in the
kadonotakashi 0:8fdf9a60065b 569 * steps for setup can be copied into a custom initialization function, while
kadonotakashi 0:8fdf9a60065b 570 * the steps for usage can be copied into, e.g.the main application function.
kadonotakashi 0:8fdf9a60065b 571 *
kadonotakashi 0:8fdf9a60065b 572 * \section spi_basic_use_case Basic use case
kadonotakashi 0:8fdf9a60065b 573 * In this basic use case, the SPI module are configured for:
kadonotakashi 0:8fdf9a60065b 574 * - Master mode
kadonotakashi 0:8fdf9a60065b 575 * - Interrupt-based handling
kadonotakashi 0:8fdf9a60065b 576 *
kadonotakashi 0:8fdf9a60065b 577 * \subsection sam_spi_quickstart_prereq Prerequisites
kadonotakashi 0:8fdf9a60065b 578 * -# \ref sysclk_group "System Clock Management (Sysclock)"
kadonotakashi 0:8fdf9a60065b 579 *
kadonotakashi 0:8fdf9a60065b 580 * \section spi_basic_use_case_setup Setup steps
kadonotakashi 0:8fdf9a60065b 581 * \subsection spi_basic_use_case_setup_code Example code
kadonotakashi 0:8fdf9a60065b 582 * Add to application C-file:
kadonotakashi 0:8fdf9a60065b 583 * \code
kadonotakashi 0:8fdf9a60065b 584 void spi_master_init(Spi *p_spi)
kadonotakashi 0:8fdf9a60065b 585 {
kadonotakashi 0:8fdf9a60065b 586 spi_enable_clock(p_spi);
kadonotakashi 0:8fdf9a60065b 587 spi_reset(p_spi);
kadonotakashi 0:8fdf9a60065b 588 spi_set_master_mode(p_spi);
kadonotakashi 0:8fdf9a60065b 589 spi_disable_mode_fault_detect(p_spi);
kadonotakashi 0:8fdf9a60065b 590 spi_disable_loopback(p_spi);
kadonotakashi 0:8fdf9a60065b 591 spi_set_peripheral_chip_select_value(p_spi,
kadonotakashi 0:8fdf9a60065b 592 spi_get_pcs(DEFAULT_CHIP_ID));
kadonotakashi 0:8fdf9a60065b 593 spi_set_fixed_peripheral_select(p_spi);
kadonotakashi 0:8fdf9a60065b 594 spi_disable_peripheral_select_decode(p_spi);
kadonotakashi 0:8fdf9a60065b 595 spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
kadonotakashi 0:8fdf9a60065b 596 }
kadonotakashi 0:8fdf9a60065b 597 void spi_master_setup_device(Spi *p_spi, struct spi_device *device,
kadonotakashi 0:8fdf9a60065b 598 spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
kadonotakashi 0:8fdf9a60065b 599 {
kadonotakashi 0:8fdf9a60065b 600 spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
kadonotakashi 0:8fdf9a60065b 601 CONFIG_SPI_MASTER_DELAY_BCT);
kadonotakashi 0:8fdf9a60065b 602
kadonotakashi 0:8fdf9a60065b 603 spi_set_bits_per_transfer(p_spi, device->id, CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
kadonotakashi 0:8fdf9a60065b 604 spi_set_baudrate_div(p_spi, device->id,
kadonotakashi 0:8fdf9a60065b 605 spi_calc_baudrate_div(baud_rate, sysclk_get_cpu_hz()));
kadonotakashi 0:8fdf9a60065b 606
kadonotakashi 0:8fdf9a60065b 607 spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
kadonotakashi 0:8fdf9a60065b 608
kadonotakashi 0:8fdf9a60065b 609 spi_set_clock_polarity(p_spi, device->id, flags >> 1);
kadonotakashi 0:8fdf9a60065b 610 spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
kadonotakashi 0:8fdf9a60065b 611 }
kadonotakashi 0:8fdf9a60065b 612 \endcode
kadonotakashi 0:8fdf9a60065b 613 *
kadonotakashi 0:8fdf9a60065b 614 * \subsection spi_basic_use_case_setup_flow Workflow
kadonotakashi 0:8fdf9a60065b 615 * -# Initialize the SPI in master mode:
kadonotakashi 0:8fdf9a60065b 616 * - \code
kadonotakashi 0:8fdf9a60065b 617 void spi_master_init(SPI_EXAMPLE);
kadonotakashi 0:8fdf9a60065b 618 \endcode
kadonotakashi 0:8fdf9a60065b 619 * -# Set up an SPI device:
kadonotakashi 0:8fdf9a60065b 620 * - \code void spi_master_setup_device(SPI_EXAMPLE, &SPI_DEVICE_EXAMPLE,
kadonotakashi 0:8fdf9a60065b 621 SPI_MODE_0, SPI_EXAMPLE_BAUDRATE, 0); \endcode
kadonotakashi 0:8fdf9a60065b 622 * - \note The returned device descriptor structure must be passed to the driver
kadonotakashi 0:8fdf9a60065b 623 * whenever that device should be used as current slave device.
kadonotakashi 0:8fdf9a60065b 624 * -# Enable SPI module:
kadonotakashi 0:8fdf9a60065b 625 * - \code spi_enable(SPI_EXAMPLE); \endcode
kadonotakashi 0:8fdf9a60065b 626 */
kadonotakashi 0:8fdf9a60065b 627 #endif /* SPI_H_INCLUDED */