takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/gpio_irq_api.c@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /* mbed Microcontroller Library
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2006-2015 ARM Limited
kadonotakashi 0:8fdf9a60065b 3 *
kadonotakashi 0:8fdf9a60065b 4 * Licensed under the Apache License, Version 2.0 (the "License");
kadonotakashi 0:8fdf9a60065b 5 * you may not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 6 * You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * http://www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 11 * distributed under the License is distributed on an "AS IS" BASIS,
kadonotakashi 0:8fdf9a60065b 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 13 * See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 14 * limitations under the License.
kadonotakashi 0:8fdf9a60065b 15 */
kadonotakashi 0:8fdf9a60065b 16 #include <stddef.h>
kadonotakashi 0:8fdf9a60065b 17 #include "cmsis.h"
kadonotakashi 0:8fdf9a60065b 18
kadonotakashi 0:8fdf9a60065b 19 #include "gpio_irq_api.h"
kadonotakashi 0:8fdf9a60065b 20 #include "gpio_api.h"
kadonotakashi 0:8fdf9a60065b 21 #include "mbed_error.h"
kadonotakashi 0:8fdf9a60065b 22 #include "extint.h"
kadonotakashi 0:8fdf9a60065b 23 #include "pinmap.h"
kadonotakashi 0:8fdf9a60065b 24 #include "PeripheralPins.h"
kadonotakashi 0:8fdf9a60065b 25 #include "port.h"
kadonotakashi 0:8fdf9a60065b 26
kadonotakashi 0:8fdf9a60065b 27 #define IRQ_RISE_POSITION 1
kadonotakashi 0:8fdf9a60065b 28 #define IRQ_FALL_POSITION 2
kadonotakashi 0:8fdf9a60065b 29 #define CHANNEL_NUM 16
kadonotakashi 0:8fdf9a60065b 30 #define pEXT_CONF(obj) (obj->config_extint_chan)
kadonotakashi 0:8fdf9a60065b 31 static uint32_t channel_ids[CHANNEL_NUM] = {0};
kadonotakashi 0:8fdf9a60065b 32 static gpio_irq_handler irq_handler;
kadonotakashi 0:8fdf9a60065b 33 uint8_t ext_int_pins[EIC_NUMBER_OF_INTERRUPTS] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
kadonotakashi 0:8fdf9a60065b 34
kadonotakashi 0:8fdf9a60065b 35 void gpio_irq(void)
kadonotakashi 0:8fdf9a60065b 36 {
kadonotakashi 0:8fdf9a60065b 37 uint32_t current_channel;
kadonotakashi 0:8fdf9a60065b 38 uint32_t mask;
kadonotakashi 0:8fdf9a60065b 39 gpio_irq_event event;
kadonotakashi 0:8fdf9a60065b 40 PortGroup *port_base;
kadonotakashi 0:8fdf9a60065b 41
kadonotakashi 0:8fdf9a60065b 42 for (current_channel = 0; current_channel < EIC_NUMBER_OF_INTERRUPTS ; current_channel++) {
kadonotakashi 0:8fdf9a60065b 43 if (extint_chan_is_detected(current_channel)) {
kadonotakashi 0:8fdf9a60065b 44 extint_chan_clear_detected(current_channel);
kadonotakashi 0:8fdf9a60065b 45 port_base = (PortGroup*)port_get_group_from_gpio_pin(ext_int_pins[current_channel]);
kadonotakashi 0:8fdf9a60065b 46 mask = gpio_set((PinName)ext_int_pins[current_channel]);
kadonotakashi 0:8fdf9a60065b 47 if ((port_base->IN.reg & mask) != 0) {
kadonotakashi 0:8fdf9a60065b 48 event = IRQ_RISE;
kadonotakashi 0:8fdf9a60065b 49 } else {
kadonotakashi 0:8fdf9a60065b 50 event = IRQ_FALL;
kadonotakashi 0:8fdf9a60065b 51 }
kadonotakashi 0:8fdf9a60065b 52 if(irq_handler) {
kadonotakashi 0:8fdf9a60065b 53 irq_handler(channel_ids[current_channel], event);
kadonotakashi 0:8fdf9a60065b 54 }
kadonotakashi 0:8fdf9a60065b 55 }
kadonotakashi 0:8fdf9a60065b 56 }
kadonotakashi 0:8fdf9a60065b 57 }
kadonotakashi 0:8fdf9a60065b 58
kadonotakashi 0:8fdf9a60065b 59 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
kadonotakashi 0:8fdf9a60065b 60 {
kadonotakashi 0:8fdf9a60065b 61 MBED_ASSERT(obj);
kadonotakashi 0:8fdf9a60065b 62 if (pin == NC)
kadonotakashi 0:8fdf9a60065b 63 return -1;
kadonotakashi 0:8fdf9a60065b 64
kadonotakashi 0:8fdf9a60065b 65 IRQn_Type irq_n = (IRQn_Type)0;
kadonotakashi 0:8fdf9a60065b 66 uint32_t vector = 0;
kadonotakashi 0:8fdf9a60065b 67 int int_channel = 0;
kadonotakashi 0:8fdf9a60065b 68 irq_handler = handler; // assuming the usage of these apis in mbed layer only
kadonotakashi 0:8fdf9a60065b 69
kadonotakashi 0:8fdf9a60065b 70 obj->pin = pin;
kadonotakashi 0:8fdf9a60065b 71
kadonotakashi 0:8fdf9a60065b 72 extint_chan_get_config_defaults(&pEXT_CONF(obj));
kadonotakashi 0:8fdf9a60065b 73 pEXT_CONF(obj).gpio_pin = (uint32_t)pin;
kadonotakashi 0:8fdf9a60065b 74 pEXT_CONF(obj).gpio_pin_mux = 0; // mux setting for ext int is 0
kadonotakashi 0:8fdf9a60065b 75 pEXT_CONF(obj).gpio_pin_pull = EXTINT_PULL_UP;
kadonotakashi 0:8fdf9a60065b 76 pEXT_CONF(obj).detection_criteria = EXTINT_DETECT_NONE;
kadonotakashi 0:8fdf9a60065b 77
kadonotakashi 0:8fdf9a60065b 78 int_channel = pinmap_find_peripheral(pin, PinMap_EXTINT);
kadonotakashi 0:8fdf9a60065b 79 if (int_channel == NC) {
kadonotakashi 0:8fdf9a60065b 80 return -1;
kadonotakashi 0:8fdf9a60065b 81 }
kadonotakashi 0:8fdf9a60065b 82 extint_chan_set_config(int_channel, &pEXT_CONF(obj));
kadonotakashi 0:8fdf9a60065b 83 ext_int_pins[int_channel] = pin;
kadonotakashi 0:8fdf9a60065b 84
kadonotakashi 0:8fdf9a60065b 85 irq_n = EIC_IRQn;
kadonotakashi 0:8fdf9a60065b 86 vector = (uint32_t)gpio_irq;
kadonotakashi 0:8fdf9a60065b 87 NVIC_SetVector(irq_n, vector);
kadonotakashi 0:8fdf9a60065b 88 NVIC_EnableIRQ(irq_n);
kadonotakashi 0:8fdf9a60065b 89 obj->ch = int_channel;
kadonotakashi 0:8fdf9a60065b 90 channel_ids[int_channel] = id;
kadonotakashi 0:8fdf9a60065b 91 obj->irqmask = 0;
kadonotakashi 0:8fdf9a60065b 92
kadonotakashi 0:8fdf9a60065b 93 return 0;
kadonotakashi 0:8fdf9a60065b 94 }
kadonotakashi 0:8fdf9a60065b 95
kadonotakashi 0:8fdf9a60065b 96 void gpio_irq_free(gpio_irq_t *obj)
kadonotakashi 0:8fdf9a60065b 97 {
kadonotakashi 0:8fdf9a60065b 98 MBED_ASSERT(obj);
kadonotakashi 0:8fdf9a60065b 99 Eic *const eic = _extint_get_eic_from_channel(obj->ch);
kadonotakashi 0:8fdf9a60065b 100 channel_ids[obj->ch] = 0;
kadonotakashi 0:8fdf9a60065b 101 eic->INTENCLR.reg = (1UL << obj->ch);
kadonotakashi 0:8fdf9a60065b 102 }
kadonotakashi 0:8fdf9a60065b 103
kadonotakashi 0:8fdf9a60065b 104 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
kadonotakashi 0:8fdf9a60065b 105 {
kadonotakashi 0:8fdf9a60065b 106 MBED_ASSERT(obj);
kadonotakashi 0:8fdf9a60065b 107 Eic *const eic = _extint_get_eic_from_channel(obj->ch);
kadonotakashi 0:8fdf9a60065b 108 if (enable) {
kadonotakashi 0:8fdf9a60065b 109 if (event == IRQ_RISE) {
kadonotakashi 0:8fdf9a60065b 110 obj->irqmask |= IRQ_RISE_POSITION;
kadonotakashi 0:8fdf9a60065b 111 } else if (event == IRQ_FALL) {
kadonotakashi 0:8fdf9a60065b 112 obj->irqmask |= IRQ_FALL_POSITION;
kadonotakashi 0:8fdf9a60065b 113 }
kadonotakashi 0:8fdf9a60065b 114 eic->INTENSET.reg = (1UL << obj->ch);
kadonotakashi 0:8fdf9a60065b 115 } else {
kadonotakashi 0:8fdf9a60065b 116 if (event == IRQ_RISE) {
kadonotakashi 0:8fdf9a60065b 117 obj->irqmask &= ~IRQ_RISE_POSITION;
kadonotakashi 0:8fdf9a60065b 118 } else if (event == IRQ_FALL) {
kadonotakashi 0:8fdf9a60065b 119 obj->irqmask &= ~IRQ_FALL_POSITION;
kadonotakashi 0:8fdf9a60065b 120 }
kadonotakashi 0:8fdf9a60065b 121 }
kadonotakashi 0:8fdf9a60065b 122
kadonotakashi 0:8fdf9a60065b 123 if (obj->irqmask == (IRQ_RISE_POSITION | IRQ_FALL_POSITION)) {
kadonotakashi 0:8fdf9a60065b 124 pEXT_CONF(obj).detection_criteria = EXTINT_DETECT_BOTH;
kadonotakashi 0:8fdf9a60065b 125 } else if (obj->irqmask == IRQ_RISE_POSITION) {
kadonotakashi 0:8fdf9a60065b 126 pEXT_CONF(obj).detection_criteria = EXTINT_DETECT_RISING;
kadonotakashi 0:8fdf9a60065b 127 } else if (obj->irqmask == IRQ_FALL_POSITION) {
kadonotakashi 0:8fdf9a60065b 128 pEXT_CONF(obj).detection_criteria = EXTINT_DETECT_FALLING;
kadonotakashi 0:8fdf9a60065b 129 } else {
kadonotakashi 0:8fdf9a60065b 130 pEXT_CONF(obj).detection_criteria = EXTINT_DETECT_NONE;
kadonotakashi 0:8fdf9a60065b 131 eic->INTENCLR.reg = (1UL << obj->ch);
kadonotakashi 0:8fdf9a60065b 132 }
kadonotakashi 0:8fdf9a60065b 133
kadonotakashi 0:8fdf9a60065b 134 extint_chan_set_config(obj->ch, &pEXT_CONF(obj));
kadonotakashi 0:8fdf9a60065b 135 }
kadonotakashi 0:8fdf9a60065b 136
kadonotakashi 0:8fdf9a60065b 137 void gpio_irq_enable(gpio_irq_t *obj)
kadonotakashi 0:8fdf9a60065b 138 {
kadonotakashi 0:8fdf9a60065b 139 MBED_ASSERT(obj);
kadonotakashi 0:8fdf9a60065b 140 Eic *const eic = _extint_get_eic_from_channel(obj->ch);
kadonotakashi 0:8fdf9a60065b 141 NVIC_EnableIRQ(EIC_IRQn);
kadonotakashi 0:8fdf9a60065b 142 eic->INTENSET.reg = (1UL << obj->ch);
kadonotakashi 0:8fdf9a60065b 143 }
kadonotakashi 0:8fdf9a60065b 144
kadonotakashi 0:8fdf9a60065b 145 void gpio_irq_disable(gpio_irq_t *obj)
kadonotakashi 0:8fdf9a60065b 146 {
kadonotakashi 0:8fdf9a60065b 147 MBED_ASSERT(obj);
kadonotakashi 0:8fdf9a60065b 148 Eic *const eic = _extint_get_eic_from_channel(obj->ch);
kadonotakashi 0:8fdf9a60065b 149 eic->INTENCLR.reg = (1UL << obj->ch);
kadonotakashi 0:8fdf9a60065b 150 if (eic->INTENSET.reg == 0) {
kadonotakashi 0:8fdf9a60065b 151 NVIC_DisableIRQ(EIC_IRQn);
kadonotakashi 0:8fdf9a60065b 152 }
kadonotakashi 0:8fdf9a60065b 153 }