takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /* mbed Microcontroller Library
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2006-2015 ARM Limited
kadonotakashi 0:8fdf9a60065b 3 *
kadonotakashi 0:8fdf9a60065b 4 * Licensed under the Apache License, Version 2.0 (the "License");
kadonotakashi 0:8fdf9a60065b 5 * you may not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 6 * You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * http://www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 11 * distributed under the License is distributed on an "AS IS" BASIS,
kadonotakashi 0:8fdf9a60065b 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 13 * See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 14 * limitations under the License.
kadonotakashi 0:8fdf9a60065b 15 * ----------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 16 * File: apspi.h
kadonotakashi 0:8fdf9a60065b 17 * Release: Version 2.0
kadonotakashi 0:8fdf9a60065b 18 * ----------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 19 *
kadonotakashi 0:8fdf9a60065b 20 * SSP interface Support
kadonotakashi 0:8fdf9a60065b 21 * =====================
kadonotakashi 0:8fdf9a60065b 22 */
kadonotakashi 0:8fdf9a60065b 23
kadonotakashi 0:8fdf9a60065b 24 #define SSPCS_BASE (0x4002804C) // SSP chip select register
kadonotakashi 0:8fdf9a60065b 25 #define SSP_BASE (0x40020000) // SSP Prime Cell
kadonotakashi 0:8fdf9a60065b 26
kadonotakashi 0:8fdf9a60065b 27 #define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00))
kadonotakashi 0:8fdf9a60065b 28 #define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04))
kadonotakashi 0:8fdf9a60065b 29 #define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08))
kadonotakashi 0:8fdf9a60065b 30 #define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C))
kadonotakashi 0:8fdf9a60065b 31 #define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10))
kadonotakashi 0:8fdf9a60065b 32 #define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14))
kadonotakashi 0:8fdf9a60065b 33 #define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18))
kadonotakashi 0:8fdf9a60065b 34 #define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C))
kadonotakashi 0:8fdf9a60065b 35 #define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20))
kadonotakashi 0:8fdf9a60065b 36 #define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24))
kadonotakashi 0:8fdf9a60065b 37 #define SSPCS ((volatile unsigned int *)(SSPCS_BASE))
kadonotakashi 0:8fdf9a60065b 38
kadonotakashi 0:8fdf9a60065b 39 // SSPCR0 Control register 0
kadonotakashi 0:8fdf9a60065b 40 #define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
kadonotakashi 0:8fdf9a60065b 41 #define SSPCR0_SPH 0x0080 // SSPCLKOUT phase
kadonotakashi 0:8fdf9a60065b 42 #define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity
kadonotakashi 0:8fdf9a60065b 43 #define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
kadonotakashi 0:8fdf9a60065b 44 #define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits
kadonotakashi 0:8fdf9a60065b 45 #define SSPCR0_DSS_16 0x000F // Data packet size, 16bits
kadonotakashi 0:8fdf9a60065b 46
kadonotakashi 0:8fdf9a60065b 47 // SSPCR1 Control register 1
kadonotakashi 0:8fdf9a60065b 48 #define SSPCR1_SOD 0x0008 // Slave Output mode Disable
kadonotakashi 0:8fdf9a60065b 49 #define SSPCR1_MS 0x0004 // Master or Slave mode
kadonotakashi 0:8fdf9a60065b 50 #define SSPCR1_SSE 0x0002 // Serial port enable
kadonotakashi 0:8fdf9a60065b 51 #define SSPCR1_LBM 0x0001 // Loop Back Mode
kadonotakashi 0:8fdf9a60065b 52
kadonotakashi 0:8fdf9a60065b 53 // SSPSR Status register
kadonotakashi 0:8fdf9a60065b 54 #define SSPSR_BSY 0x0010 // Busy
kadonotakashi 0:8fdf9a60065b 55 #define SSPSR_RFF 0x0008 // Receive FIFO full
kadonotakashi 0:8fdf9a60065b 56 #define SSPSR_RNE 0x0004 // Receive FIFO not empty
kadonotakashi 0:8fdf9a60065b 57 #define SSPSR_TNF 0x0002 // Transmit FIFO not full
kadonotakashi 0:8fdf9a60065b 58 #define SSPSR_TFE 0x0001 // Transmit FIFO empty
kadonotakashi 0:8fdf9a60065b 59
kadonotakashi 0:8fdf9a60065b 60 // SSPCPSR Clock prescale register
kadonotakashi 0:8fdf9a60065b 61 #define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
kadonotakashi 0:8fdf9a60065b 62
kadonotakashi 0:8fdf9a60065b 63 // SSPIMSC Interrupt mask set and clear register
kadonotakashi 0:8fdf9a60065b 64 #define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked
kadonotakashi 0:8fdf9a60065b 65 #define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked
kadonotakashi 0:8fdf9a60065b 66 #define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked
kadonotakashi 0:8fdf9a60065b 67 #define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked
kadonotakashi 0:8fdf9a60065b 68
kadonotakashi 0:8fdf9a60065b 69 // SSPRIS Raw interrupt status register
kadonotakashi 0:8fdf9a60065b 70 #define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag
kadonotakashi 0:8fdf9a60065b 71 #define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag
kadonotakashi 0:8fdf9a60065b 72 #define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag
kadonotakashi 0:8fdf9a60065b 73 #define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag
kadonotakashi 0:8fdf9a60065b 74
kadonotakashi 0:8fdf9a60065b 75 // SSPMIS Masked interrupt status register
kadonotakashi 0:8fdf9a60065b 76 #define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag
kadonotakashi 0:8fdf9a60065b 77 #define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag
kadonotakashi 0:8fdf9a60065b 78 #define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag
kadonotakashi 0:8fdf9a60065b 79 #define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag
kadonotakashi 0:8fdf9a60065b 80
kadonotakashi 0:8fdf9a60065b 81 // SSPICR Interrupt clear register
kadonotakashi 0:8fdf9a60065b 82 #define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag
kadonotakashi 0:8fdf9a60065b 83 #define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag
kadonotakashi 0:8fdf9a60065b 84
kadonotakashi 0:8fdf9a60065b 85 // SSPDMACR DMA control register
kadonotakashi 0:8fdf9a60065b 86 #define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA
kadonotakashi 0:8fdf9a60065b 87 #define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA
kadonotakashi 0:8fdf9a60065b 88
kadonotakashi 0:8fdf9a60065b 89 // SPICS register (0=Chip Select low)
kadonotakashi 0:8fdf9a60065b 90 #define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS)
kadonotakashi 0:8fdf9a60065b 91
kadonotakashi 0:8fdf9a60065b 92 // SPI defaults
kadonotakashi 0:8fdf9a60065b 93 #define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS)
kadonotakashi 0:8fdf9a60065b 94
kadonotakashi 0:8fdf9a60065b 95 // EEPROM instruction set
kadonotakashi 0:8fdf9a60065b 96 #define EEWRSR 0x0001 // Write status
kadonotakashi 0:8fdf9a60065b 97 #define EEWRITE 0x0002 // Write data
kadonotakashi 0:8fdf9a60065b 98 #define EEREAD 0x0003 // Read data
kadonotakashi 0:8fdf9a60065b 99 #define EEWDI 0x0004 // Write disable
kadonotakashi 0:8fdf9a60065b 100 #define EEWREN 0x0006 // Write enable
kadonotakashi 0:8fdf9a60065b 101 #define EERDSR 0x0005 // Read status
kadonotakashi 0:8fdf9a60065b 102
kadonotakashi 0:8fdf9a60065b 103 // EEPROM status register flags
kadonotakashi 0:8fdf9a60065b 104 #define EERDSR_WIP 0x0001 // Write in process
kadonotakashi 0:8fdf9a60065b 105 #define EERDSR_WEL 0x0002 // Write enable latch
kadonotakashi 0:8fdf9a60065b 106 #define EERDSR_BP0 0x0004 // Block protect 0
kadonotakashi 0:8fdf9a60065b 107 #define EERDSR_BP1 0x0008 // Block protect 1
kadonotakashi 0:8fdf9a60065b 108 #define EERDSR_WPEN 0x0080 // Write protect enable
kadonotakashi 0:8fdf9a60065b 109
kadonotakashi 0:8fdf9a60065b 110 /* ----------------------------------------------------------------
kadonotakashi 0:8fdf9a60065b 111 *
kadonotakashi 0:8fdf9a60065b 112 * Color LCD Support
kadonotakashi 0:8fdf9a60065b 113 * =================
kadonotakashi 0:8fdf9a60065b 114 */
kadonotakashi 0:8fdf9a60065b 115
kadonotakashi 0:8fdf9a60065b 116 // Color LCD Controller Internal Register addresses
kadonotakashi 0:8fdf9a60065b 117 #define LSSPCS_BASE (0x4002804C) // LSSP chip select register
kadonotakashi 0:8fdf9a60065b 118 #define LSSP_BASE (0x40021000) // LSSP Prime Cell
kadonotakashi 0:8fdf9a60065b 119
kadonotakashi 0:8fdf9a60065b 120 #define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00))
kadonotakashi 0:8fdf9a60065b 121 #define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04))
kadonotakashi 0:8fdf9a60065b 122 #define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08))
kadonotakashi 0:8fdf9a60065b 123 #define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C))
kadonotakashi 0:8fdf9a60065b 124 #define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10))
kadonotakashi 0:8fdf9a60065b 125 #define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14))
kadonotakashi 0:8fdf9a60065b 126 #define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18))
kadonotakashi 0:8fdf9a60065b 127 #define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C))
kadonotakashi 0:8fdf9a60065b 128 #define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20))
kadonotakashi 0:8fdf9a60065b 129 #define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24))
kadonotakashi 0:8fdf9a60065b 130 #define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE))
kadonotakashi 0:8fdf9a60065b 131
kadonotakashi 0:8fdf9a60065b 132 // LSSPCR0 Control register 0
kadonotakashi 0:8fdf9a60065b 133 #define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
kadonotakashi 0:8fdf9a60065b 134 #define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase
kadonotakashi 0:8fdf9a60065b 135 #define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity
kadonotakashi 0:8fdf9a60065b 136 #define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
kadonotakashi 0:8fdf9a60065b 137 #define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits
kadonotakashi 0:8fdf9a60065b 138 #define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits
kadonotakashi 0:8fdf9a60065b 139
kadonotakashi 0:8fdf9a60065b 140 // LSSPCR1 Control register 1
kadonotakashi 0:8fdf9a60065b 141 #define LSSPCR1_SOD 0x0008 // Slave Output mode Disable
kadonotakashi 0:8fdf9a60065b 142 #define LSSPCR1_MS 0x0004 // Master or Slave mode
kadonotakashi 0:8fdf9a60065b 143 #define LSSPCR1_SSE 0x0002 // Serial port enable
kadonotakashi 0:8fdf9a60065b 144 #define LSSPCR1_LBM 0x0001 // Loop Back Mode
kadonotakashi 0:8fdf9a60065b 145
kadonotakashi 0:8fdf9a60065b 146 // LSSPSR Status register
kadonotakashi 0:8fdf9a60065b 147 #define LSSPSR_BSY 0x0010 // Busy
kadonotakashi 0:8fdf9a60065b 148 #define LSSPSR_RFF 0x0008 // Receive FIFO full
kadonotakashi 0:8fdf9a60065b 149 #define LSSPSR_RNE 0x0004 // Receive FIFO not empty
kadonotakashi 0:8fdf9a60065b 150 #define LSSPSR_TNF 0x0002 // Transmit FIFO not full
kadonotakashi 0:8fdf9a60065b 151 #define LSSPSR_TFE 0x0001 // Transmit FIFO empty
kadonotakashi 0:8fdf9a60065b 152
kadonotakashi 0:8fdf9a60065b 153 // LSSPCPSR Clock prescale register
kadonotakashi 0:8fdf9a60065b 154 #define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
kadonotakashi 0:8fdf9a60065b 155
kadonotakashi 0:8fdf9a60065b 156 // SPICS register
kadonotakashi 0:8fdf9a60065b 157 #define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS)
kadonotakashi 0:8fdf9a60065b 158 #define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS)
kadonotakashi 0:8fdf9a60065b 159 #define LCD_RESET 0x0008 // RESET (CLCD_RESET)
kadonotakashi 0:8fdf9a60065b 160 #define LCD_RS 0x0010 // RS (CLCD_RS)
kadonotakashi 0:8fdf9a60065b 161 #define LCD_RD 0x0020 // RD (CLCD_RD)
kadonotakashi 0:8fdf9a60065b 162 #define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL)
kadonotakashi 0:8fdf9a60065b 163
kadonotakashi 0:8fdf9a60065b 164 // SPI defaults
kadonotakashi 0:8fdf9a60065b 165 #define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS)
kadonotakashi 0:8fdf9a60065b 166 #define LSPI_START (0x70) // Start byte for SPI transfer
kadonotakashi 0:8fdf9a60065b 167 #define LSPI_RD (0x01) // WR bit 1 within start
kadonotakashi 0:8fdf9a60065b 168 #define LSPI_WR (0x00) // WR bit 0 within start
kadonotakashi 0:8fdf9a60065b 169 #define LSPI_DATA (0x02) // RS bit 1 within start byte
kadonotakashi 0:8fdf9a60065b 170 #define LSPI_INDEX (0x00) // RS bit 0 within start byte
kadonotakashi 0:8fdf9a60065b 171
kadonotakashi 0:8fdf9a60065b 172 // Screen size
kadonotakashi 0:8fdf9a60065b 173 #define LCD_WIDTH 320 // Screen Width (in pixels)
kadonotakashi 0:8fdf9a60065b 174 #define LCD_HEIGHT 240 // Screen Height (in pixels)