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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_overrides.c@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /* mbed Microcontroller Library |
kadonotakashi | 0:8fdf9a60065b | 2 | * Copyright (c) 2015-2017 Nuvoton |
kadonotakashi | 0:8fdf9a60065b | 3 | * |
kadonotakashi | 0:8fdf9a60065b | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
kadonotakashi | 0:8fdf9a60065b | 5 | * you may not use this file except in compliance with the License. |
kadonotakashi | 0:8fdf9a60065b | 6 | * You may obtain a copy of the License at |
kadonotakashi | 0:8fdf9a60065b | 7 | * |
kadonotakashi | 0:8fdf9a60065b | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
kadonotakashi | 0:8fdf9a60065b | 9 | * |
kadonotakashi | 0:8fdf9a60065b | 10 | * Unless required by applicable law or agreed to in writing, software |
kadonotakashi | 0:8fdf9a60065b | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
kadonotakashi | 0:8fdf9a60065b | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
kadonotakashi | 0:8fdf9a60065b | 13 | * See the License for the specific language governing permissions and |
kadonotakashi | 0:8fdf9a60065b | 14 | * limitations under the License. |
kadonotakashi | 0:8fdf9a60065b | 15 | */ |
kadonotakashi | 0:8fdf9a60065b | 16 | |
kadonotakashi | 0:8fdf9a60065b | 17 | #include "cmsis.h" |
kadonotakashi | 0:8fdf9a60065b | 18 | |
kadonotakashi | 0:8fdf9a60065b | 19 | void mbed_sdk_init(void) |
kadonotakashi | 0:8fdf9a60065b | 20 | { |
kadonotakashi | 0:8fdf9a60065b | 21 | // NOTE: Support singleton semantics to be called from other init functions |
kadonotakashi | 0:8fdf9a60065b | 22 | static int inited = 0; |
kadonotakashi | 0:8fdf9a60065b | 23 | if (inited) { |
kadonotakashi | 0:8fdf9a60065b | 24 | return; |
kadonotakashi | 0:8fdf9a60065b | 25 | } |
kadonotakashi | 0:8fdf9a60065b | 26 | inited = 1; |
kadonotakashi | 0:8fdf9a60065b | 27 | |
kadonotakashi | 0:8fdf9a60065b | 28 | /*---------------------------------------------------------------------------------------------------------*/ |
kadonotakashi | 0:8fdf9a60065b | 29 | /* Init System Clock */ |
kadonotakashi | 0:8fdf9a60065b | 30 | /*---------------------------------------------------------------------------------------------------------*/ |
kadonotakashi | 0:8fdf9a60065b | 31 | /* Unlock protected registers */ |
kadonotakashi | 0:8fdf9a60065b | 32 | SYS_UnlockReg(); |
kadonotakashi | 0:8fdf9a60065b | 33 | |
kadonotakashi | 0:8fdf9a60065b | 34 | /* Enable HIRC clock (internal OSC 12MHz) */ |
kadonotakashi | 0:8fdf9a60065b | 35 | CLK_EnableXtalRC(CLK_PWRCTL_HIRC_EN_Msk); |
kadonotakashi | 0:8fdf9a60065b | 36 | /* Enable HXT clock (external XTAL 12MHz) */ |
kadonotakashi | 0:8fdf9a60065b | 37 | CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk); |
kadonotakashi | 0:8fdf9a60065b | 38 | /* Enable LIRC clock (OSC 10KHz) for lp_ticker */ |
kadonotakashi | 0:8fdf9a60065b | 39 | CLK_EnableXtalRC(CLK_PWRCTL_LIRC_EN_Msk); |
kadonotakashi | 0:8fdf9a60065b | 40 | /* Enable LXT clock (XTAL 32KHz) for RTC */ |
kadonotakashi | 0:8fdf9a60065b | 41 | CLK_EnableXtalRC(CLK_PWRCTL_LXT_EN_Msk); |
kadonotakashi | 0:8fdf9a60065b | 42 | |
kadonotakashi | 0:8fdf9a60065b | 43 | /* Wait for HIRC clock ready */ |
kadonotakashi | 0:8fdf9a60065b | 44 | CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk); |
kadonotakashi | 0:8fdf9a60065b | 45 | /* Wait for HXT clock ready */ |
kadonotakashi | 0:8fdf9a60065b | 46 | CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk); |
kadonotakashi | 0:8fdf9a60065b | 47 | /* Wait for LIRC clock ready */ |
kadonotakashi | 0:8fdf9a60065b | 48 | CLK_WaitClockReady(CLK_CLKSTATUS_LIRC_STB_Msk); |
kadonotakashi | 0:8fdf9a60065b | 49 | /* Wait for LXT clock ready */ |
kadonotakashi | 0:8fdf9a60065b | 50 | CLK_WaitClockReady(CLK_CLKSTATUS_LXT_STB_Msk); |
kadonotakashi | 0:8fdf9a60065b | 51 | |
kadonotakashi | 0:8fdf9a60065b | 52 | /* Set HCLK source form HXT and HCLK source divide 1 */ |
kadonotakashi | 0:8fdf9a60065b | 53 | CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_HCLK_CLK_DIVIDER(1)); |
kadonotakashi | 0:8fdf9a60065b | 54 | |
kadonotakashi | 0:8fdf9a60065b | 55 | /* Select HXT/HIRC to clock PLL |
kadonotakashi | 0:8fdf9a60065b | 56 | * |
kadonotakashi | 0:8fdf9a60065b | 57 | * Comparison between HXT/HIRC-clocked PLL: |
kadonotakashi | 0:8fdf9a60065b | 58 | * 1. Spare HXT on board if only HIRC is used. |
kadonotakashi | 0:8fdf9a60065b | 59 | * 2. HIRC has shorter stable time. |
kadonotakashi | 0:8fdf9a60065b | 60 | * 3. HXT has better accuracy. USBD requires HXT-clocked PLL. |
kadonotakashi | 0:8fdf9a60065b | 61 | * 4. HIRC has shorter wake-up time from power-down mode. |
kadonotakashi | 0:8fdf9a60065b | 62 | * Per test, wake-up time from power-down mode would take: |
kadonotakashi | 0:8fdf9a60065b | 63 | * T1. 1~13 ms (proportional to deep sleep time) with HXT-clocked PLL as HCLK clock source |
kadonotakashi | 0:8fdf9a60065b | 64 | * T2. <1 ms with HIRC-clocked PLL as HCLK clock source |
kadonotakashi | 0:8fdf9a60065b | 65 | * T1 will fail Greentea test which requires max 10 ms wake-up time. |
kadonotakashi | 0:8fdf9a60065b | 66 | * |
kadonotakashi | 0:8fdf9a60065b | 67 | * If we just call CLK_SetCoreClock(FREQ_42MHZ) to configure HCLK to 42 MHz, |
kadonotakashi | 0:8fdf9a60065b | 68 | * it will go T1 with HXT already enabled in front. So we manually configure |
kadonotakashi | 0:8fdf9a60065b | 69 | * it to choose HXT/HIRC-clocked PLL. |
kadonotakashi | 0:8fdf9a60065b | 70 | */ |
kadonotakashi | 0:8fdf9a60065b | 71 | #define NU_HXT_PLL 1 |
kadonotakashi | 0:8fdf9a60065b | 72 | #define NU_HIRC_PLL 2 |
kadonotakashi | 0:8fdf9a60065b | 73 | |
kadonotakashi | 0:8fdf9a60065b | 74 | #ifndef NU_CLOCK_PLL |
kadonotakashi | 0:8fdf9a60065b | 75 | #define NU_CLOCK_PLL NU_HIRC_PLL |
kadonotakashi | 0:8fdf9a60065b | 76 | #endif |
kadonotakashi | 0:8fdf9a60065b | 77 | |
kadonotakashi | 0:8fdf9a60065b | 78 | #if (NU_CLOCK_PLL == NU_HXT_PLL) |
kadonotakashi | 0:8fdf9a60065b | 79 | CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, FREQ_42MHZ*2); |
kadonotakashi | 0:8fdf9a60065b | 80 | CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2)); |
kadonotakashi | 0:8fdf9a60065b | 81 | #elif (NU_CLOCK_PLL == NU_HIRC_PLL) |
kadonotakashi | 0:8fdf9a60065b | 82 | CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC, FREQ_42MHZ*2); |
kadonotakashi | 0:8fdf9a60065b | 83 | CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2)); |
kadonotakashi | 0:8fdf9a60065b | 84 | #endif |
kadonotakashi | 0:8fdf9a60065b | 85 | |
kadonotakashi | 0:8fdf9a60065b | 86 | /* Update System Core Clock */ |
kadonotakashi | 0:8fdf9a60065b | 87 | /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ |
kadonotakashi | 0:8fdf9a60065b | 88 | SystemCoreClockUpdate(); |
kadonotakashi | 0:8fdf9a60065b | 89 | |
kadonotakashi | 0:8fdf9a60065b | 90 | /* Lock protected registers */ |
kadonotakashi | 0:8fdf9a60065b | 91 | SYS_LockReg(); |
kadonotakashi | 0:8fdf9a60065b | 92 | } |