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mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/uuart_reg.h@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
| kadonotakashi | 0:8fdf9a60065b | 2 | * @file uuart_reg.h |
| kadonotakashi | 0:8fdf9a60065b | 3 | * @version V1.00 |
| kadonotakashi | 0:8fdf9a60065b | 4 | * @brief UUART register definition header file |
| kadonotakashi | 0:8fdf9a60065b | 5 | * |
| kadonotakashi | 0:8fdf9a60065b | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
| kadonotakashi | 0:8fdf9a60065b | 7 | *****************************************************************************/ |
| kadonotakashi | 0:8fdf9a60065b | 8 | #ifndef __UUART_REG_H__ |
| kadonotakashi | 0:8fdf9a60065b | 9 | #define __UUART_REG_H__ |
| kadonotakashi | 0:8fdf9a60065b | 10 | |
| kadonotakashi | 0:8fdf9a60065b | 11 | |
| kadonotakashi | 0:8fdf9a60065b | 12 | |
| kadonotakashi | 0:8fdf9a60065b | 13 | /*---------------------- UART Mode of USCI Controller -------------------------*/ |
| kadonotakashi | 0:8fdf9a60065b | 14 | /** |
| kadonotakashi | 0:8fdf9a60065b | 15 | @addtogroup UUART UART Mode of USCI Controller(UUART) |
| kadonotakashi | 0:8fdf9a60065b | 16 | Memory Mapped Structure for UUART Controller |
| kadonotakashi | 0:8fdf9a60065b | 17 | @{ */ |
| kadonotakashi | 0:8fdf9a60065b | 18 | |
| kadonotakashi | 0:8fdf9a60065b | 19 | typedef struct |
| kadonotakashi | 0:8fdf9a60065b | 20 | { |
| kadonotakashi | 0:8fdf9a60065b | 21 | |
| kadonotakashi | 0:8fdf9a60065b | 22 | |
| kadonotakashi | 0:8fdf9a60065b | 23 | /** |
| kadonotakashi | 0:8fdf9a60065b | 24 | * @var UUART_T::CTL |
| kadonotakashi | 0:8fdf9a60065b | 25 | * Offset: 0x00 USCI Control Register |
| kadonotakashi | 0:8fdf9a60065b | 26 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 27 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 28 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 29 | * |[2:0] |FUNMODE |Function Mode |
| kadonotakashi | 0:8fdf9a60065b | 30 | * | | |This bit field selects the protocol for this USCI controller. |
| kadonotakashi | 0:8fdf9a60065b | 31 | * | | |Selecting a protocol that is not available or a reserved combination disables the USCI. |
| kadonotakashi | 0:8fdf9a60065b | 32 | * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol. |
| kadonotakashi | 0:8fdf9a60065b | 33 | * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. |
| kadonotakashi | 0:8fdf9a60065b | 34 | * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. |
| kadonotakashi | 0:8fdf9a60065b | 35 | * | | |001 = The SPI protocol is selected. |
| kadonotakashi | 0:8fdf9a60065b | 36 | * | | |010 = The UART protocol is selected. |
| kadonotakashi | 0:8fdf9a60065b | 37 | * | | |100 = The I2C protocol is selected. |
| kadonotakashi | 0:8fdf9a60065b | 38 | * | | |Others = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 39 | * @var UUART_T::INTEN |
| kadonotakashi | 0:8fdf9a60065b | 40 | * Offset: 0x04 USCI Interrupt Enable Register |
| kadonotakashi | 0:8fdf9a60065b | 41 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 42 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 43 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 44 | * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 45 | * | | |This bit enables the interrupt generation in case of a transmit start event. |
| kadonotakashi | 0:8fdf9a60065b | 46 | * | | |0 = The transmit start interrupt is disabled. |
| kadonotakashi | 0:8fdf9a60065b | 47 | * | | |1 = The transmit start interrupt is enabled. |
| kadonotakashi | 0:8fdf9a60065b | 48 | * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 49 | * | | |This bit enables the interrupt generation in case of a transmit finish event. |
| kadonotakashi | 0:8fdf9a60065b | 50 | * | | |0 = The transmit finish interrupt is disabled. |
| kadonotakashi | 0:8fdf9a60065b | 51 | * | | |1 = The transmit finish interrupt is enabled. |
| kadonotakashi | 0:8fdf9a60065b | 52 | * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 53 | * | | |This bit enables the interrupt generation in case of a receive start event. |
| kadonotakashi | 0:8fdf9a60065b | 54 | * | | |0 = The receive start interrupt is disabled. |
| kadonotakashi | 0:8fdf9a60065b | 55 | * | | |1 = The receive start interrupt is enabled. |
| kadonotakashi | 0:8fdf9a60065b | 56 | * |[4] |RXENDIEN |Receive End Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 57 | * | | |This bit enables the interrupt generation in case of a receive finish event. |
| kadonotakashi | 0:8fdf9a60065b | 58 | * | | |0 = The receive end interrupt is disabled. |
| kadonotakashi | 0:8fdf9a60065b | 59 | * | | |1 = The receive end interrupt is enabled. |
| kadonotakashi | 0:8fdf9a60065b | 60 | * @var UUART_T::BRGEN |
| kadonotakashi | 0:8fdf9a60065b | 61 | * Offset: 0x08 USCI Baud Rate Generator Register |
| kadonotakashi | 0:8fdf9a60065b | 62 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 63 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 64 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 65 | * |[0] |RCLKSEL |Reference Clock Source Selection |
| kadonotakashi | 0:8fdf9a60065b | 66 | * | | |This bit selects the source signal of reference clock (fREF_CLK). |
| kadonotakashi | 0:8fdf9a60065b | 67 | * | | |0 = Peripheral device clock fPCLK. |
| kadonotakashi | 0:8fdf9a60065b | 68 | * | | |1 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 69 | * |[1] |PTCLKSEL |Protocol Clock Source Selection |
| kadonotakashi | 0:8fdf9a60065b | 70 | * | | |This bit selects the source signal of protocol clock (fPROT_CLK). |
| kadonotakashi | 0:8fdf9a60065b | 71 | * | | |0 = Reference clock fREF_CLK. |
| kadonotakashi | 0:8fdf9a60065b | 72 | * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). |
| kadonotakashi | 0:8fdf9a60065b | 73 | * |[3:2] |SPCLKSEL |Sample Clock Source Selection |
| kadonotakashi | 0:8fdf9a60065b | 74 | * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. |
| kadonotakashi | 0:8fdf9a60065b | 75 | * | | |00 = fSAMP_CLK frequency is fDIV_CLK. |
| kadonotakashi | 0:8fdf9a60065b | 76 | * | | |01 = fSAMP_CLK frequency is from fPROT_CLK. |
| kadonotakashi | 0:8fdf9a60065b | 77 | * | | |10 = fSAMP_CLK frequency is from fSCLK. |
| kadonotakashi | 0:8fdf9a60065b | 78 | * | | |11 = fSAMP_CLK frequency is from fREF_CLK. |
| kadonotakashi | 0:8fdf9a60065b | 79 | * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 80 | * | | |This bit enables the 10-bit timing measurement counter. |
| kadonotakashi | 0:8fdf9a60065b | 81 | * | | |0 = Timing measurement counter is Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 82 | * | | |1 = Timing measurement counter is Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 83 | * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection |
| kadonotakashi | 0:8fdf9a60065b | 84 | * | | |0 = Timing measurement counter with fPROT_CLK. |
| kadonotakashi | 0:8fdf9a60065b | 85 | * | | |1 = Timing measurement counter with fDIV_CLK. |
| kadonotakashi | 0:8fdf9a60065b | 86 | * |[9:8] |PDSCNT |Pre-divider for Sample Counter |
| kadonotakashi | 0:8fdf9a60065b | 87 | * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK. |
| kadonotakashi | 0:8fdf9a60065b | 88 | * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). |
| kadonotakashi | 0:8fdf9a60065b | 89 | * |[14:10] |DSCNT |Denominator for Sample Counter |
| kadonotakashi | 0:8fdf9a60065b | 90 | * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. |
| kadonotakashi | 0:8fdf9a60065b | 91 | * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). |
| kadonotakashi | 0:8fdf9a60065b | 92 | * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. |
| kadonotakashi | 0:8fdf9a60065b | 93 | * |[25:16] |CLKDIV |Clock Divider |
| kadonotakashi | 0:8fdf9a60065b | 94 | * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). |
| kadonotakashi | 0:8fdf9a60065b | 95 | * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. |
| kadonotakashi | 0:8fdf9a60065b | 96 | * | | |The revised value is the average bit time between bit 5 and bit 6. |
| kadonotakashi | 0:8fdf9a60065b | 97 | * | | |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. |
| kadonotakashi | 0:8fdf9a60065b | 98 | * @var UUART_T::DATIN0 |
| kadonotakashi | 0:8fdf9a60065b | 99 | * Offset: 0x10 USCI Input Data Signal Configuration Register 0 |
| kadonotakashi | 0:8fdf9a60065b | 100 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 101 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 102 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 103 | * |[0] |SYNCSEL |Input Signal Synchronization Selection |
| kadonotakashi | 0:8fdf9a60065b | 104 | * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. |
| kadonotakashi | 0:8fdf9a60065b | 105 | * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. |
| kadonotakashi | 0:8fdf9a60065b | 106 | * | | |1 = The synchronized signal can be taken as input for the data shift unit. |
| kadonotakashi | 0:8fdf9a60065b | 107 | * |[2] |ININV |Input Signal Inverse Selection |
| kadonotakashi | 0:8fdf9a60065b | 108 | * | | |This bit defines the inverter enable of the input asynchronous signal. |
| kadonotakashi | 0:8fdf9a60065b | 109 | * | | |0 = The un-synchronized input signal will not be inverted. |
| kadonotakashi | 0:8fdf9a60065b | 110 | * | | |1 = The un-synchronized input signal will be inverted. |
| kadonotakashi | 0:8fdf9a60065b | 111 | * |[4:3] |EDGEDET |Input Signal Edge Detection Mode |
| kadonotakashi | 0:8fdf9a60065b | 112 | * | | |This bit field selects which edge actives the trigger event of input data signal. |
| kadonotakashi | 0:8fdf9a60065b | 113 | * | | |00 = The trigger event activation is disabled. |
| kadonotakashi | 0:8fdf9a60065b | 114 | * | | |01 = A rising edge activates the trigger event of input data signal. |
| kadonotakashi | 0:8fdf9a60065b | 115 | * | | |10 = A falling edge activates the trigger event of input data signal. |
| kadonotakashi | 0:8fdf9a60065b | 116 | * | | |11 = Both edges activate the trigger event of input data signal. |
| kadonotakashi | 0:8fdf9a60065b | 117 | * | | |Note: In UART function mode, it is suggested to set this bit field as 10. |
| kadonotakashi | 0:8fdf9a60065b | 118 | * @var UUART_T::CTLIN0 |
| kadonotakashi | 0:8fdf9a60065b | 119 | * Offset: 0x20 USCI Input Control Signal Configuration Register 0 |
| kadonotakashi | 0:8fdf9a60065b | 120 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 121 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 122 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 123 | * |[0] |SYNCSEL |Input Synchronization Signal Selection |
| kadonotakashi | 0:8fdf9a60065b | 124 | * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. |
| kadonotakashi | 0:8fdf9a60065b | 125 | * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. |
| kadonotakashi | 0:8fdf9a60065b | 126 | * | | |1 = The synchronized signal can be taken as input for the data shift unit. |
| kadonotakashi | 0:8fdf9a60065b | 127 | * |[2] |ININV |Input Signal Inverse Selection |
| kadonotakashi | 0:8fdf9a60065b | 128 | * | | |This bit defines the inverter enable of the input asynchronous signal. |
| kadonotakashi | 0:8fdf9a60065b | 129 | * | | |0 = The un-synchronized input signal will not be inverted. |
| kadonotakashi | 0:8fdf9a60065b | 130 | * | | |1 = The un-synchronized input signal will be inverted. |
| kadonotakashi | 0:8fdf9a60065b | 131 | * @var UUART_T::CLKIN |
| kadonotakashi | 0:8fdf9a60065b | 132 | * Offset: 0x28 USCI Input Clock Signal Configuration Register |
| kadonotakashi | 0:8fdf9a60065b | 133 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 134 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 135 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 136 | * |[0] |SYNCSEL |Input Synchronization Signal Selection |
| kadonotakashi | 0:8fdf9a60065b | 137 | * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. |
| kadonotakashi | 0:8fdf9a60065b | 138 | * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. |
| kadonotakashi | 0:8fdf9a60065b | 139 | * | | |1 = The synchronized signal can be taken as input for the data shift unit. |
| kadonotakashi | 0:8fdf9a60065b | 140 | * @var UUART_T::LINECTL |
| kadonotakashi | 0:8fdf9a60065b | 141 | * Offset: 0x2C USCI Line Control Register |
| kadonotakashi | 0:8fdf9a60065b | 142 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 143 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 144 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 145 | * |[0] |LSB |LSB First Transmission Selection |
| kadonotakashi | 0:8fdf9a60065b | 146 | * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. |
| kadonotakashi | 0:8fdf9a60065b | 147 | * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. |
| kadonotakashi | 0:8fdf9a60065b | 148 | * |[5] |DATOINV |Data Output Inverse Selection |
| kadonotakashi | 0:8fdf9a60065b | 149 | * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. |
| kadonotakashi | 0:8fdf9a60065b | 150 | * | | |0 = The value of USCIx_DAT1 is equal to the data shift register. |
| kadonotakashi | 0:8fdf9a60065b | 151 | * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register. |
| kadonotakashi | 0:8fdf9a60065b | 152 | * |[7] |CTLOINV |Control Signal Output Inverse Selection |
| kadonotakashi | 0:8fdf9a60065b | 153 | * | | |This bit defines the relation between the internal control signal and the output control signal. |
| kadonotakashi | 0:8fdf9a60065b | 154 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 155 | * | | |1 = The control signal will be inverted before its output. |
| kadonotakashi | 0:8fdf9a60065b | 156 | * | | |Note: In UART protocol, the control signal means nRTS signal. |
| kadonotakashi | 0:8fdf9a60065b | 157 | * |[11:8] |DWIDTH |Word Length of Transmission |
| kadonotakashi | 0:8fdf9a60065b | 158 | * | | |This bit field defines the data word length (amount of bits) for reception and transmission |
| kadonotakashi | 0:8fdf9a60065b | 159 | * | | |The data word is always right-aligned in the data buffer |
| kadonotakashi | 0:8fdf9a60065b | 160 | * | | |USCI support word length from 4 to 16 bits. |
| kadonotakashi | 0:8fdf9a60065b | 161 | * | | |0x0 = The data word contains 16 bits located at bit positions [15:0]. |
| kadonotakashi | 0:8fdf9a60065b | 162 | * | | |0x1 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 163 | * | | |0x2 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 164 | * | | |0x3 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 165 | * | | |0x4 = The data word contains 4 bits located at bit positions [3:0]. |
| kadonotakashi | 0:8fdf9a60065b | 166 | * | | |0x5 = The data word contains 5 bits located at bit positions [4:0]. |
| kadonotakashi | 0:8fdf9a60065b | 167 | * | | |... |
| kadonotakashi | 0:8fdf9a60065b | 168 | * | | |0xF = The data word contains 15 bits located at bit positions [14:0]. |
| kadonotakashi | 0:8fdf9a60065b | 169 | * | | |Note: In UART protocol, the length can be configured as 6~13 bits. |
| kadonotakashi | 0:8fdf9a60065b | 170 | * @var UUART_T::TXDAT |
| kadonotakashi | 0:8fdf9a60065b | 171 | * Offset: 0x30 USCI Transmit Data Register |
| kadonotakashi | 0:8fdf9a60065b | 172 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 173 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 174 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 175 | * |[15:0] |TXDAT |Transmit Data |
| kadonotakashi | 0:8fdf9a60065b | 176 | * | | |Software can use this bit field to write 16-bit transmit data for transmission. |
| kadonotakashi | 0:8fdf9a60065b | 177 | * @var UUART_T::RXDAT |
| kadonotakashi | 0:8fdf9a60065b | 178 | * Offset: 0x34 USCI Receive Data Register |
| kadonotakashi | 0:8fdf9a60065b | 179 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 180 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 181 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 182 | * |[15:0] |RXDAT |Received Data |
| kadonotakashi | 0:8fdf9a60065b | 183 | * | | |This bit field monitors the received data which stored in receive data buffer. |
| kadonotakashi | 0:8fdf9a60065b | 184 | * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). |
| kadonotakashi | 0:8fdf9a60065b | 185 | * @var UUART_T::BUFCTL |
| kadonotakashi | 0:8fdf9a60065b | 186 | * Offset: 0x38 USCI Transmit/Receive Buffer Control Register |
| kadonotakashi | 0:8fdf9a60065b | 187 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 188 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 189 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 190 | * |[7] |TXCLR |Clear Transmit Buffer |
| kadonotakashi | 0:8fdf9a60065b | 191 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 192 | * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). |
| kadonotakashi | 0:8fdf9a60065b | 193 | * | | |Should only be used while the buffer is not taking part in data traffic. |
| kadonotakashi | 0:8fdf9a60065b | 194 | * | | |Note: It is cleared automatically after one PCLK cycle. |
| kadonotakashi | 0:8fdf9a60065b | 195 | * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 196 | * | | |0 = Receive overrun interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 197 | * | | |1 = Receive overrun interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 198 | * |[15] |RXCLR |Clear Receive Buffer |
| kadonotakashi | 0:8fdf9a60065b | 199 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 200 | * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). |
| kadonotakashi | 0:8fdf9a60065b | 201 | * | | |Should only be used while the buffer is not taking part in data traffic. |
| kadonotakashi | 0:8fdf9a60065b | 202 | * | | |Note: It is cleared automatically after one PCLK cycle. |
| kadonotakashi | 0:8fdf9a60065b | 203 | * |[16] |TXRST |Transmit Reset |
| kadonotakashi | 0:8fdf9a60065b | 204 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 205 | * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. |
| kadonotakashi | 0:8fdf9a60065b | 206 | * | | |Note: It is cleared automatically after one PCLK cycle. |
| kadonotakashi | 0:8fdf9a60065b | 207 | * |[17] |RXRST |Receive Reset |
| kadonotakashi | 0:8fdf9a60065b | 208 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 209 | * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. |
| kadonotakashi | 0:8fdf9a60065b | 210 | * | | |Note1: It is cleared automatically after one PCLK cycle. |
| kadonotakashi | 0:8fdf9a60065b | 211 | * | | |Note2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 212 | * @var UUART_T::BUFSTS |
| kadonotakashi | 0:8fdf9a60065b | 213 | * Offset: 0x3C USCI Transmit/Receive Buffer Status Register |
| kadonotakashi | 0:8fdf9a60065b | 214 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 215 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 216 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 217 | * |[0] |RXEMPTY |Receive Buffer Empty Indicator |
| kadonotakashi | 0:8fdf9a60065b | 218 | * | | |0 = Receive buffer is not empty. |
| kadonotakashi | 0:8fdf9a60065b | 219 | * | | |1 = Receive buffer is empty. |
| kadonotakashi | 0:8fdf9a60065b | 220 | * |[1] |RXFULL |Receive Buffer Full Indicator |
| kadonotakashi | 0:8fdf9a60065b | 221 | * | | |0 = Receive buffer is not full. |
| kadonotakashi | 0:8fdf9a60065b | 222 | * | | |1 = Receive buffer is full. |
| kadonotakashi | 0:8fdf9a60065b | 223 | * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status |
| kadonotakashi | 0:8fdf9a60065b | 224 | * | | |This bit indicates that a receive buffer overrun error event has been detected. |
| kadonotakashi | 0:8fdf9a60065b | 225 | * | | |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. |
| kadonotakashi | 0:8fdf9a60065b | 226 | * | | |It is cleared by software writes 1 to this bit. |
| kadonotakashi | 0:8fdf9a60065b | 227 | * | | |0 = A receive buffer overrun error event has not been detected. |
| kadonotakashi | 0:8fdf9a60065b | 228 | * | | |1 = A receive buffer overrun error event has been detected. |
| kadonotakashi | 0:8fdf9a60065b | 229 | * |[8] |TXEMPTY |Transmit Buffer Empty Indicator |
| kadonotakashi | 0:8fdf9a60065b | 230 | * | | |0 = Transmit buffer is not empty. |
| kadonotakashi | 0:8fdf9a60065b | 231 | * | | |1 = Transmit buffer is empty. |
| kadonotakashi | 0:8fdf9a60065b | 232 | * |[9] |TXFULL |Transmit Buffer Full Indicator |
| kadonotakashi | 0:8fdf9a60065b | 233 | * | | |0 = Transmit buffer is not full. |
| kadonotakashi | 0:8fdf9a60065b | 234 | * | | |1 = Transmit buffer is full. |
| kadonotakashi | 0:8fdf9a60065b | 235 | * @var UUART_T::PDMACTL |
| kadonotakashi | 0:8fdf9a60065b | 236 | * Offset: 0x40 USCI PDMA Control Register |
| kadonotakashi | 0:8fdf9a60065b | 237 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 238 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 239 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 240 | * |[0] |PDMARST |PDMA Reset |
| kadonotakashi | 0:8fdf9a60065b | 241 | * | | |0 = No effect. |
| kadonotakashi | 0:8fdf9a60065b | 242 | * | | |1 = Reset the USCI PDMA control logic. This bit will be cleared to 0 automatically. |
| kadonotakashi | 0:8fdf9a60065b | 243 | * |[1] |TXPDMAEN |PDMA Transmit Channel Available |
| kadonotakashi | 0:8fdf9a60065b | 244 | * | | |0 = Transmit PDMA function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 245 | * | | |1 = Transmit PDMA function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 246 | * |[2] |RXPDMAEN |PDMA Receive Channel Available |
| kadonotakashi | 0:8fdf9a60065b | 247 | * | | |0 = Receive PDMA function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 248 | * | | |1 = Receive PDMA function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 249 | * |[3] |PDMAEN |PDMA Mode Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 250 | * | | |0 = PDMA function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 251 | * | | |1 = PDMA function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 252 | * @var UUART_T::WKCTL |
| kadonotakashi | 0:8fdf9a60065b | 253 | * Offset: 0x54 USCI Wake-up Control Register |
| kadonotakashi | 0:8fdf9a60065b | 254 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 255 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 256 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 257 | * |[0] |WKEN |Wake-up Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 258 | * | | |0 = Wake-up function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 259 | * | | |1 = Wake-up function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 260 | * |[2] |PDBOPT |Power Down Blocking Option |
| kadonotakashi | 0:8fdf9a60065b | 261 | * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. |
| kadonotakashi | 0:8fdf9a60065b | 262 | * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. |
| kadonotakashi | 0:8fdf9a60065b | 263 | * @var UUART_T::WKSTS |
| kadonotakashi | 0:8fdf9a60065b | 264 | * Offset: 0x58 USCI Wake-up Status Register |
| kadonotakashi | 0:8fdf9a60065b | 265 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 266 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 267 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 268 | * |[0] |WKF |Wake-up Flag |
| kadonotakashi | 0:8fdf9a60065b | 269 | * | | |When chip is woken up from Power-down mode, this bit is set to 1 |
| kadonotakashi | 0:8fdf9a60065b | 270 | * | | |Software can write 1 to clear this bit. |
| kadonotakashi | 0:8fdf9a60065b | 271 | * @var UUART_T::PROTCTL |
| kadonotakashi | 0:8fdf9a60065b | 272 | * Offset: 0x5C USCI Protocol Control Register |
| kadonotakashi | 0:8fdf9a60065b | 273 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 274 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 275 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 276 | * |[0] |STOPB |Stop Bits |
| kadonotakashi | 0:8fdf9a60065b | 277 | * | | |This bit defines the number of stop bits in an UART frame. |
| kadonotakashi | 0:8fdf9a60065b | 278 | * | | |0 = The number of stop bits is 1. |
| kadonotakashi | 0:8fdf9a60065b | 279 | * | | |1 = The number of stop bits is 2. |
| kadonotakashi | 0:8fdf9a60065b | 280 | * |[1] |PARITYEN |Parity Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 281 | * | | |This bit defines the parity bit is enabled in an UART frame. |
| kadonotakashi | 0:8fdf9a60065b | 282 | * | | |0 = The parity bit Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 283 | * | | |1 = The parity bit Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 284 | * |[2] |EVENPARITY|Even Parity Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 285 | * | | |0 = Odd number of logic 1's is transmitted and checked in each word. |
| kadonotakashi | 0:8fdf9a60065b | 286 | * | | |1 = Even number of logic 1's is transmitted and checked in each word. |
| kadonotakashi | 0:8fdf9a60065b | 287 | * | | |Note: This bit has effect only when PARITYEN is set. |
| kadonotakashi | 0:8fdf9a60065b | 288 | * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 289 | * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] = 1)), the UART will de-assert nRTS signal. |
| kadonotakashi | 0:8fdf9a60065b | 290 | * | | |0 = nRTS auto-flow control Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 291 | * | | |1 = nRTS auto-flow control Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 292 | * | | |Note: This bit has effect only when the RTSAUDIREN is not set. |
| kadonotakashi | 0:8fdf9a60065b | 293 | * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 294 | * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). |
| kadonotakashi | 0:8fdf9a60065b | 295 | * | | |0 = nCTS auto-flow control Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 296 | * | | |1 = nCTS auto-flow control Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 297 | * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 298 | * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the nRTS signal is inactive. |
| kadonotakashi | 0:8fdf9a60065b | 299 | * | | |0 = nRTS auto direction control Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 300 | * | | |1 = nRTS auto direction control Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 301 | * | | |Note1: This bit is used for nRTS auto direction control for RS485. |
| kadonotakashi | 0:8fdf9a60065b | 302 | * | | |Note2: This bit has effect only when the RTSAUTOEN is not set. |
| kadonotakashi | 0:8fdf9a60065b | 303 | * |[6] |ABREN |Auto-baud Rate Detect Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 304 | * | | |0 = Auto-baud rate detect function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 305 | * | | |1 = Auto-baud rate detect function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 306 | * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit. |
| kadonotakashi | 0:8fdf9a60065b | 307 | * | | |The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). |
| kadonotakashi | 0:8fdf9a60065b | 308 | * |[9] |DATWKEN |Data Wake-up Mode Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 309 | * | | |0 = Data wake-up mode Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 310 | * | | |1 = Data wake-up mode Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 311 | * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 312 | * | | |0 = nCTS wake-up mode Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 313 | * | | |1 = nCTS wake-up mode Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 314 | * |[14:11] |WAKECNT |Wake-up Counter |
| kadonotakashi | 0:8fdf9a60065b | 315 | * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. |
| kadonotakashi | 0:8fdf9a60065b | 316 | * |[24:16] |BRDETITV |Baud Rate Detection Interval |
| kadonotakashi | 0:8fdf9a60065b | 317 | * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. |
| kadonotakashi | 0:8fdf9a60065b | 318 | * | | |The order of the bus shall be 1 and 0 step by step (e.g |
| kadonotakashi | 0:8fdf9a60065b | 319 | * | | |the input data pattern shall be 0x55) |
| kadonotakashi | 0:8fdf9a60065b | 320 | * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set. |
| kadonotakashi | 0:8fdf9a60065b | 321 | * | | |Note: This bit can be cleared to 0 by software writing u20180' to the BRDETITV. |
| kadonotakashi | 0:8fdf9a60065b | 322 | * |[26] |STICKEN |Stick Parity Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 323 | * | | |0 = Stick parity Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 324 | * | | |1 = Stick parity Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 325 | * | | |Note: Refer to RS-485 Support section for detail information. |
| kadonotakashi | 0:8fdf9a60065b | 326 | * |[29] |BCEN |Transmit Break Control Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 327 | * | | |0 = Transmit Break Control Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 328 | * | | |1 = Transmit Break Control Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 329 | * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). |
| kadonotakashi | 0:8fdf9a60065b | 330 | * | | |This bit acts only on TX line and has no effect on the transmitter logic. |
| kadonotakashi | 0:8fdf9a60065b | 331 | * |[31] |PROTEN |UART Protocol Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 332 | * | | |0 = UART Protocol Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 333 | * | | |1 = UART Protocol Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 334 | * @var UUART_T::PROTIEN |
| kadonotakashi | 0:8fdf9a60065b | 335 | * Offset: 0x60 USCI Protocol Interrupt Enable Register |
| kadonotakashi | 0:8fdf9a60065b | 336 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 337 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 338 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 339 | * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 340 | * | | |0 = Auto-baud rate interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 341 | * | | |1 = Auto-baud rate interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 342 | * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 343 | * | | |0 = Receive line status interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 344 | * | | |1 = Receive line status interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 345 | * | | |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 346 | * @var UUART_T::PROTSTS |
| kadonotakashi | 0:8fdf9a60065b | 347 | * Offset: 0x64 USCI Protocol Status Register |
| kadonotakashi | 0:8fdf9a60065b | 348 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 349 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 350 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 351 | * |[1] |TXSTIF |Transmit Start Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 352 | * | | |0 = A transmit start interrupt status has not occurred. |
| kadonotakashi | 0:8fdf9a60065b | 353 | * | | |1 = A transmit start interrupt status has occurred. |
| kadonotakashi | 0:8fdf9a60065b | 354 | * | | |Note1: It is cleared by software writing one into this bit. |
| kadonotakashi | 0:8fdf9a60065b | 355 | * | | |Note2: Used for user to load next transmit data when there is no data in transmit buffer. |
| kadonotakashi | 0:8fdf9a60065b | 356 | * |[2] |TXENDIF |Transmit End Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 357 | * | | |0 = A transmit end interrupt status has not occurred. |
| kadonotakashi | 0:8fdf9a60065b | 358 | * | | |1 = A transmit end interrupt status has occurred. |
| kadonotakashi | 0:8fdf9a60065b | 359 | * | | |Note: It is cleared by software writing one into this bit. |
| kadonotakashi | 0:8fdf9a60065b | 360 | * |[3] |RXSTIF |Receive Start Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 361 | * | | |0 = A receive start interrupt status has not occurred. |
| kadonotakashi | 0:8fdf9a60065b | 362 | * | | |1 = A receive start interrupt status has occurred. |
| kadonotakashi | 0:8fdf9a60065b | 363 | * | | |Note: It is cleared by software writing one into this bit. |
| kadonotakashi | 0:8fdf9a60065b | 364 | * |[4] |RXENDIF |Receive End Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 365 | * | | |0 = A receive finish interrupt status has not occurred. |
| kadonotakashi | 0:8fdf9a60065b | 366 | * | | |1 = A receive finish interrupt status has occurred. |
| kadonotakashi | 0:8fdf9a60065b | 367 | * | | |Note: It is cleared by software writing one into this bit. |
| kadonotakashi | 0:8fdf9a60065b | 368 | * |[5] |PARITYERR |Parity Error Flag |
| kadonotakashi | 0:8fdf9a60065b | 369 | * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. |
| kadonotakashi | 0:8fdf9a60065b | 370 | * | | |0 = No parity error is generated. |
| kadonotakashi | 0:8fdf9a60065b | 371 | * | | |1 = Parity error is generated. |
| kadonotakashi | 0:8fdf9a60065b | 372 | * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. |
| kadonotakashi | 0:8fdf9a60065b | 373 | * |[6] |FRMERR |Framing Error Flag |
| kadonotakashi | 0:8fdf9a60065b | 374 | * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). |
| kadonotakashi | 0:8fdf9a60065b | 375 | * | | |0 = No framing error is generated. |
| kadonotakashi | 0:8fdf9a60065b | 376 | * | | |1 = Framing error is generated. |
| kadonotakashi | 0:8fdf9a60065b | 377 | * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. |
| kadonotakashi | 0:8fdf9a60065b | 378 | * |[7] |BREAK |Break Flag |
| kadonotakashi | 0:8fdf9a60065b | 379 | * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). |
| kadonotakashi | 0:8fdf9a60065b | 380 | * | | |0 = No Break is generated. |
| kadonotakashi | 0:8fdf9a60065b | 381 | * | | |1 = Break is generated in the receiver bus. |
| kadonotakashi | 0:8fdf9a60065b | 382 | * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. |
| kadonotakashi | 0:8fdf9a60065b | 383 | * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 384 | * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data. |
| kadonotakashi | 0:8fdf9a60065b | 385 | * | | |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. |
| kadonotakashi | 0:8fdf9a60065b | 386 | * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. |
| kadonotakashi | 0:8fdf9a60065b | 387 | * | | |0 = Auto-baud rate detect function is not done. |
| kadonotakashi | 0:8fdf9a60065b | 388 | * | | |1 = One Bit auto-baud rate detect function is done. |
| kadonotakashi | 0:8fdf9a60065b | 389 | * | | |Note: This bit can be cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 390 | * |[10] |RXBUSY |RX Bus Status Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 391 | * | | |This bit indicates the busy status of the receiver. |
| kadonotakashi | 0:8fdf9a60065b | 392 | * | | |0 = The receiver is Idle. |
| kadonotakashi | 0:8fdf9a60065b | 393 | * | | |1 = The receiver is BUSY. |
| kadonotakashi | 0:8fdf9a60065b | 394 | * |[11] |ABERRSTS |Auto-baud Rate Error Status |
| kadonotakashi | 0:8fdf9a60065b | 395 | * | | |This bit is set when auto-baud rate detection counter overrun. |
| kadonotakashi | 0:8fdf9a60065b | 396 | * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again. |
| kadonotakashi | 0:8fdf9a60065b | 397 | * | | |0 = Auto-baud rate detect counter is not overrun. |
| kadonotakashi | 0:8fdf9a60065b | 398 | * | | |1 = Auto-baud rate detect counter is overrun. |
| kadonotakashi | 0:8fdf9a60065b | 399 | * | | |Note1: This bit is set at the same time of ABRDETIF. |
| kadonotakashi | 0:8fdf9a60065b | 400 | * | | |Note2: This bit can be cleared by writing 1 to ABRDETIF or ABERRSTS. |
| kadonotakashi | 0:8fdf9a60065b | 401 | * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 402 | * | | |This bit used to indicate the current status of the internal synchronized nCTS signal. |
| kadonotakashi | 0:8fdf9a60065b | 403 | * | | |0 = The internal synchronized nCTS is low. |
| kadonotakashi | 0:8fdf9a60065b | 404 | * | | |1 = The internal synchronized nCTS is high. |
| kadonotakashi | 0:8fdf9a60065b | 405 | * |[17] |CTSLV |nCTS Pin Status (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 406 | * | | |This bit used to monitor the current status of nCTS pin input. |
| kadonotakashi | 0:8fdf9a60065b | 407 | * | | |0 = nCTS pin input is low level voltage logic state. |
| kadonotakashi | 0:8fdf9a60065b | 408 | * | | |1 = nCTS pin input is high level voltage logic state. |
| kadonotakashi | 0:8fdf9a60065b | 409 | */ |
| kadonotakashi | 0:8fdf9a60065b | 410 | |
| kadonotakashi | 0:8fdf9a60065b | 411 | __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 412 | __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ |
| kadonotakashi | 0:8fdf9a60065b | 413 | __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ |
| kadonotakashi | 0:8fdf9a60065b | 414 | __I uint32_t RESERVE0[1]; |
| kadonotakashi | 0:8fdf9a60065b | 415 | __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ |
| kadonotakashi | 0:8fdf9a60065b | 416 | __I uint32_t RESERVE1[3]; |
| kadonotakashi | 0:8fdf9a60065b | 417 | __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ |
| kadonotakashi | 0:8fdf9a60065b | 418 | __I uint32_t RESERVE2[1]; |
| kadonotakashi | 0:8fdf9a60065b | 419 | __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ |
| kadonotakashi | 0:8fdf9a60065b | 420 | __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 421 | __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ |
| kadonotakashi | 0:8fdf9a60065b | 422 | __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ |
| kadonotakashi | 0:8fdf9a60065b | 423 | __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 424 | __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ |
| kadonotakashi | 0:8fdf9a60065b | 425 | __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 426 | __I uint32_t RESERVE3[4]; |
| kadonotakashi | 0:8fdf9a60065b | 427 | __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 428 | __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ |
| kadonotakashi | 0:8fdf9a60065b | 429 | __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ |
| kadonotakashi | 0:8fdf9a60065b | 430 | __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ |
| kadonotakashi | 0:8fdf9a60065b | 431 | __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ |
| kadonotakashi | 0:8fdf9a60065b | 432 | |
| kadonotakashi | 0:8fdf9a60065b | 433 | } UUART_T; |
| kadonotakashi | 0:8fdf9a60065b | 434 | |
| kadonotakashi | 0:8fdf9a60065b | 435 | /** |
| kadonotakashi | 0:8fdf9a60065b | 436 | @addtogroup UUART_CONST UUART Bit Field Definition |
| kadonotakashi | 0:8fdf9a60065b | 437 | Constant Definitions for UUART Controller |
| kadonotakashi | 0:8fdf9a60065b | 438 | @{ */ |
| kadonotakashi | 0:8fdf9a60065b | 439 | |
| kadonotakashi | 0:8fdf9a60065b | 440 | #define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */ |
| kadonotakashi | 0:8fdf9a60065b | 441 | #define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 442 | |
| kadonotakashi | 0:8fdf9a60065b | 443 | #define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 444 | #define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 445 | |
| kadonotakashi | 0:8fdf9a60065b | 446 | #define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 447 | #define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 448 | |
| kadonotakashi | 0:8fdf9a60065b | 449 | #define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 450 | #define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 451 | |
| kadonotakashi | 0:8fdf9a60065b | 452 | #define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 453 | #define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 454 | |
| kadonotakashi | 0:8fdf9a60065b | 455 | #define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 456 | #define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 457 | |
| kadonotakashi | 0:8fdf9a60065b | 458 | #define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 459 | #define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 460 | |
| kadonotakashi | 0:8fdf9a60065b | 461 | #define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 462 | #define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 463 | |
| kadonotakashi | 0:8fdf9a60065b | 464 | #define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 465 | #define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 466 | |
| kadonotakashi | 0:8fdf9a60065b | 467 | #define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */ |
| kadonotakashi | 0:8fdf9a60065b | 468 | #define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 469 | |
| kadonotakashi | 0:8fdf9a60065b | 470 | #define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 471 | #define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 472 | |
| kadonotakashi | 0:8fdf9a60065b | 473 | #define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 474 | #define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 475 | |
| kadonotakashi | 0:8fdf9a60065b | 476 | #define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 477 | #define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 478 | |
| kadonotakashi | 0:8fdf9a60065b | 479 | #define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 480 | #define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 481 | |
| kadonotakashi | 0:8fdf9a60065b | 482 | #define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 483 | #define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 484 | |
| kadonotakashi | 0:8fdf9a60065b | 485 | #define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */ |
| kadonotakashi | 0:8fdf9a60065b | 486 | #define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 487 | |
| kadonotakashi | 0:8fdf9a60065b | 488 | #define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 489 | #define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 490 | |
| kadonotakashi | 0:8fdf9a60065b | 491 | #define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 492 | #define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 493 | |
| kadonotakashi | 0:8fdf9a60065b | 494 | #define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 495 | #define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 496 | |
| kadonotakashi | 0:8fdf9a60065b | 497 | #define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */ |
| kadonotakashi | 0:8fdf9a60065b | 498 | #define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 499 | |
| kadonotakashi | 0:8fdf9a60065b | 500 | #define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 501 | #define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 502 | |
| kadonotakashi | 0:8fdf9a60065b | 503 | #define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 504 | #define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 505 | |
| kadonotakashi | 0:8fdf9a60065b | 506 | #define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */ |
| kadonotakashi | 0:8fdf9a60065b | 507 | #define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 508 | |
| kadonotakashi | 0:8fdf9a60065b | 509 | #define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 510 | #define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 511 | |
| kadonotakashi | 0:8fdf9a60065b | 512 | #define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 513 | #define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 514 | |
| kadonotakashi | 0:8fdf9a60065b | 515 | #define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */ |
| kadonotakashi | 0:8fdf9a60065b | 516 | #define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 517 | |
| kadonotakashi | 0:8fdf9a60065b | 518 | #define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 519 | #define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 520 | |
| kadonotakashi | 0:8fdf9a60065b | 521 | #define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */ |
| kadonotakashi | 0:8fdf9a60065b | 522 | #define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 523 | |
| kadonotakashi | 0:8fdf9a60065b | 524 | #define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */ |
| kadonotakashi | 0:8fdf9a60065b | 525 | #define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 526 | |
| kadonotakashi | 0:8fdf9a60065b | 527 | #define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */ |
| kadonotakashi | 0:8fdf9a60065b | 528 | #define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 529 | |
| kadonotakashi | 0:8fdf9a60065b | 530 | #define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */ |
| kadonotakashi | 0:8fdf9a60065b | 531 | #define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 532 | |
| kadonotakashi | 0:8fdf9a60065b | 533 | #define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 534 | #define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 535 | |
| kadonotakashi | 0:8fdf9a60065b | 536 | #define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 537 | #define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 538 | |
| kadonotakashi | 0:8fdf9a60065b | 539 | #define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */ |
| kadonotakashi | 0:8fdf9a60065b | 540 | #define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 541 | |
| kadonotakashi | 0:8fdf9a60065b | 542 | #define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 543 | #define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 544 | |
| kadonotakashi | 0:8fdf9a60065b | 545 | #define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */ |
| kadonotakashi | 0:8fdf9a60065b | 546 | #define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 547 | |
| kadonotakashi | 0:8fdf9a60065b | 548 | #define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 549 | #define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 550 | |
| kadonotakashi | 0:8fdf9a60065b | 551 | #define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 552 | #define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 553 | |
| kadonotakashi | 0:8fdf9a60065b | 554 | #define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 555 | #define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 556 | |
| kadonotakashi | 0:8fdf9a60065b | 557 | #define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 558 | #define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 559 | |
| kadonotakashi | 0:8fdf9a60065b | 560 | #define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 561 | #define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 562 | |
| kadonotakashi | 0:8fdf9a60065b | 563 | #define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 564 | #define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 565 | |
| kadonotakashi | 0:8fdf9a60065b | 566 | #define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */ |
| kadonotakashi | 0:8fdf9a60065b | 567 | #define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 568 | |
| kadonotakashi | 0:8fdf9a60065b | 569 | #define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 570 | #define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 571 | |
| kadonotakashi | 0:8fdf9a60065b | 572 | #define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */ |
| kadonotakashi | 0:8fdf9a60065b | 573 | #define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 574 | |
| kadonotakashi | 0:8fdf9a60065b | 575 | #define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 576 | #define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 577 | |
| kadonotakashi | 0:8fdf9a60065b | 578 | #define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 579 | #define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 580 | |
| kadonotakashi | 0:8fdf9a60065b | 581 | #define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 582 | #define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 583 | |
| kadonotakashi | 0:8fdf9a60065b | 584 | #define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 585 | #define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 586 | |
| kadonotakashi | 0:8fdf9a60065b | 587 | #define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 588 | #define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 589 | |
| kadonotakashi | 0:8fdf9a60065b | 590 | #define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 591 | #define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 592 | |
| kadonotakashi | 0:8fdf9a60065b | 593 | #define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 594 | #define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 595 | |
| kadonotakashi | 0:8fdf9a60065b | 596 | #define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 597 | #define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 598 | |
| kadonotakashi | 0:8fdf9a60065b | 599 | #define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 600 | #define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 601 | |
| kadonotakashi | 0:8fdf9a60065b | 602 | #define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 603 | #define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 604 | |
| kadonotakashi | 0:8fdf9a60065b | 605 | #define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 606 | #define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 607 | |
| kadonotakashi | 0:8fdf9a60065b | 608 | #define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 609 | #define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 610 | |
| kadonotakashi | 0:8fdf9a60065b | 611 | #define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 612 | #define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 613 | |
| kadonotakashi | 0:8fdf9a60065b | 614 | #define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 615 | #define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 616 | |
| kadonotakashi | 0:8fdf9a60065b | 617 | #define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 618 | #define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 619 | |
| kadonotakashi | 0:8fdf9a60065b | 620 | #define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 621 | #define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 622 | |
| kadonotakashi | 0:8fdf9a60065b | 623 | #define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 624 | #define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 625 | |
| kadonotakashi | 0:8fdf9a60065b | 626 | #define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */ |
| kadonotakashi | 0:8fdf9a60065b | 627 | #define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 628 | |
| kadonotakashi | 0:8fdf9a60065b | 629 | #define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */ |
| kadonotakashi | 0:8fdf9a60065b | 630 | #define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 631 | |
| kadonotakashi | 0:8fdf9a60065b | 632 | #define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */ |
| kadonotakashi | 0:8fdf9a60065b | 633 | #define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 634 | |
| kadonotakashi | 0:8fdf9a60065b | 635 | #define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 636 | #define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 637 | |
| kadonotakashi | 0:8fdf9a60065b | 638 | #define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */ |
| kadonotakashi | 0:8fdf9a60065b | 639 | #define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 640 | |
| kadonotakashi | 0:8fdf9a60065b | 641 | #define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */ |
| kadonotakashi | 0:8fdf9a60065b | 642 | #define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 643 | |
| kadonotakashi | 0:8fdf9a60065b | 644 | #define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 645 | #define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 646 | |
| kadonotakashi | 0:8fdf9a60065b | 647 | #define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 648 | #define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 649 | |
| kadonotakashi | 0:8fdf9a60065b | 650 | /**@}*/ /* UUART_CONST */ |
| kadonotakashi | 0:8fdf9a60065b | 651 | /**@}*/ /* end of UUART register group */ |
| kadonotakashi | 0:8fdf9a60065b | 652 | |
| kadonotakashi | 0:8fdf9a60065b | 653 | |
| kadonotakashi | 0:8fdf9a60065b | 654 | |
| kadonotakashi | 0:8fdf9a60065b | 655 | #endif /* __UUART_REG_H__ */ |