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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/timer_reg.h@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:: kadonotakashi
Date:: Wed Oct 10 00:33:53 2018 +0000
Revision:: 0:8fdf9a60065b

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User	Revision	Line number	New contents of line
kadonotakashi	0:8fdf9a60065b	1	/************************************************************************//
kadonotakashi	0:8fdf9a60065b	2	* @file timer_reg.h
kadonotakashi	0:8fdf9a60065b	3	* @version V1.00
kadonotakashi	0:8fdf9a60065b	4	* @brief TIMER register definition header file
kadonotakashi	0:8fdf9a60065b	5	*
kadonotakashi	0:8fdf9a60065b	6	* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
kadonotakashi	0:8fdf9a60065b	7	*****************************************************************************/
kadonotakashi	0:8fdf9a60065b	8	#ifndef __TIMER_REG_H__
kadonotakashi	0:8fdf9a60065b	9	#define __TIMER_REG_H__
kadonotakashi	0:8fdf9a60065b	10
kadonotakashi	0:8fdf9a60065b	11
kadonotakashi	0:8fdf9a60065b	12	/---------------------- Timer Controller -------------------------/
kadonotakashi	0:8fdf9a60065b	13	/**
kadonotakashi	0:8fdf9a60065b	14	@addtogroup TIMER Timer Controller(TIMER)
kadonotakashi	0:8fdf9a60065b	15	Memory Mapped Structure for TIMER Controller
kadonotakashi	0:8fdf9a60065b	16	@{ */
kadonotakashi	0:8fdf9a60065b	17
kadonotakashi	0:8fdf9a60065b	18	typedef struct
kadonotakashi	0:8fdf9a60065b	19	{
kadonotakashi	0:8fdf9a60065b	20
kadonotakashi	0:8fdf9a60065b	21
kadonotakashi	0:8fdf9a60065b	22	/**
kadonotakashi	0:8fdf9a60065b	23	* @var TIMER_T::CTL
kadonotakashi	0:8fdf9a60065b	24	* Offset: 0x00 Timer Control Register
kadonotakashi	0:8fdf9a60065b	25	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	26	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	27	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	28	* \|[7:0] \|PSC \|Prescale Counter
kadonotakashi	0:8fdf9a60065b	29	* \| \| \|Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter
kadonotakashi	0:8fdf9a60065b	30	* \| \| \|If this field is 0 (PSC = 0), then there is no scaling.
kadonotakashi	0:8fdf9a60065b	31	* \| \| \|Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
kadonotakashi	0:8fdf9a60065b	32	* \|[19] \|INTRGEN \|Inter-timer Trigger Mode Enable Control
kadonotakashi	0:8fdf9a60065b	33	* \| \| \|Setting this bit will enable the inter-timer trigger capture function.
kadonotakashi	0:8fdf9a60065b	34	* \| \| \|The Timer0/2 will be in event counter mode and counting with external clock source or event
kadonotakashi	0:8fdf9a60065b	35	* \| \| \|Also, Timer1/3 will be in trigger-counting mode of capture function.
kadonotakashi	0:8fdf9a60065b	36	* \| \| \|0 = Inter-Timer Trigger Capture mode Disabled.
kadonotakashi	0:8fdf9a60065b	37	* \| \| \|1 = Inter-Timer Trigger Capture mode Enabled.
kadonotakashi	0:8fdf9a60065b	38	* \| \| \|Note: For Timer1/3, this bit is ignored and the read back value is always 0.
kadonotakashi	0:8fdf9a60065b	39	* \|[20] \|PERIOSEL \|Periodic Mode Behavior Selection Enable Bit
kadonotakashi	0:8fdf9a60065b	40	* \| \| \|0 = The behavior selection in periodic mode is Disabled.
kadonotakashi	0:8fdf9a60065b	41	* \| \| \|When user updates CMPDAT while timer is running in periodic mode,
kadonotakashi	0:8fdf9a60065b	42	* \| \| \|CNT will be reset to default value.
kadonotakashi	0:8fdf9a60065b	43	* \| \| \|1 = The behavior selection in periodic mode is Enabled.
kadonotakashi	0:8fdf9a60065b	44	* \| \| \|When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list,
kadonotakashi	0:8fdf9a60065b	45	* \| \| \|If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually.
kadonotakashi	0:8fdf9a60065b	46	* \| \| \|If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately.
kadonotakashi	0:8fdf9a60065b	47	* \| \| \|If updated CMPDAT value < CNT, CNT will be reset to default value.
kadonotakashi	0:8fdf9a60065b	48	* \|[21] \|TGLPINSEL \|Toggle-output Pin Select
kadonotakashi	0:8fdf9a60065b	49	* \| \| \|0 = Toggle mode output to TMx (Timer Event Counter Pin).
kadonotakashi	0:8fdf9a60065b	50	* \| \| \|1 = Toggle mode output to TMx_EXT (Timer External Capture Pin).
kadonotakashi	0:8fdf9a60065b	51	* \|[22] \|CAPSRC \|Capture Pin Source Selection
kadonotakashi	0:8fdf9a60065b	52	* \| \| \|0 = Capture Function source is from TMx_EXT (x= 0~3) pin.
kadonotakashi	0:8fdf9a60065b	53	* \| \| \|1 = Capture Function source is from internal ACMP output signal
kadonotakashi	0:8fdf9a60065b	54	* \| \| \|User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source.
kadonotakashi	0:8fdf9a60065b	55	* \|[23] \|WKEN \|Wake-up Function Enable Bit
kadonotakashi	0:8fdf9a60065b	56	* \| \| \|If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
kadonotakashi	0:8fdf9a60065b	57	* \| \| \|0 = Wake-up function Disabled if timer interrupt signal generated.
kadonotakashi	0:8fdf9a60065b	58	* \| \| \|1 = Wake-up function Enabled if timer interrupt signal generated.
kadonotakashi	0:8fdf9a60065b	59	* \|[24] \|EXTCNTEN \|Event Counter Mode Enable Bit
kadonotakashi	0:8fdf9a60065b	60	* \| \| \|This bit is for external counting pin function enabled.
kadonotakashi	0:8fdf9a60065b	61	* \| \| \|0 = Event counter mode Disabled.
kadonotakashi	0:8fdf9a60065b	62	* \| \| \|1 = Event counter mode Enabled.
kadonotakashi	0:8fdf9a60065b	63	* \| \| \|Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
kadonotakashi	0:8fdf9a60065b	64	* \|[25] \|ACTSTS \|Timer Active Status Bit (Read Only)
kadonotakashi	0:8fdf9a60065b	65	* \| \| \|This bit indicates the 24-bit up counter status.
kadonotakashi	0:8fdf9a60065b	66	* \| \| \|0 = 24-bit up counter is not active.
kadonotakashi	0:8fdf9a60065b	67	* \| \| \|1 = 24-bit up counter is active.
kadonotakashi	0:8fdf9a60065b	68	* \| \| \|Note: This bit may active when CNT 0 transition to CNT 1.
kadonotakashi	0:8fdf9a60065b	69	* \|[28:27] \|OPMODE \|Timer Counting Mode Select
kadonotakashi	0:8fdf9a60065b	70	* \| \| \|00 = The Timer controller is operated in One-shot mode.
kadonotakashi	0:8fdf9a60065b	71	* \| \| \|01 = The Timer controller is operated in Periodic mode.
kadonotakashi	0:8fdf9a60065b	72	* \| \| \|10 = The Timer controller is operated in Toggle-output mode.
kadonotakashi	0:8fdf9a60065b	73	* \| \| \|11 = The Timer controller is operated in Continuous Counting mode.
kadonotakashi	0:8fdf9a60065b	74	* \|[29] \|INTEN \|Timer Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	75	* \| \| \|0 = Timer time-out interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	76	* \| \| \|1 = Timer time-out interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	77	* \| \| \|Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
kadonotakashi	0:8fdf9a60065b	78	* \|[30] \|CNTEN \|Timer Counting Enable Bit
kadonotakashi	0:8fdf9a60065b	79	* \| \| \|0 = Stops/Suspends counting.
kadonotakashi	0:8fdf9a60065b	80	* \| \| \|1 = Starts counting.
kadonotakashi	0:8fdf9a60065b	81	* \| \| \|Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
kadonotakashi	0:8fdf9a60065b	82	* \| \| \|Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
kadonotakashi	0:8fdf9a60065b	83	* \| \| \|Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
kadonotakashi	0:8fdf9a60065b	84	* \|[31] \|ICEDEBUG \|ICE Debug Mode Acknowledge Disable Control (Write Protect)
kadonotakashi	0:8fdf9a60065b	85	* \| \| \|0 = ICE debug mode acknowledgment effects TIMER counting.
kadonotakashi	0:8fdf9a60065b	86	* \| \| \|TIMER counter will be held while CPU is held by ICE.
kadonotakashi	0:8fdf9a60065b	87	* \| \| \|1 = ICE debug mode acknowledgment Disabled.
kadonotakashi	0:8fdf9a60065b	88	* \| \| \|TIMER counter will keep going no matter CPU is held by ICE or not.
kadonotakashi	0:8fdf9a60065b	89	* \| \| \|Note: This bit is write protected. Refer to the SYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	90	* @var TIMER_T::CMP
kadonotakashi	0:8fdf9a60065b	91	* Offset: 0x04 Timer Comparator Register
kadonotakashi	0:8fdf9a60065b	92	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	93	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	94	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	95	* \|[23:0] \|CMPDAT \|Timer Comparator Value
kadonotakashi	0:8fdf9a60065b	96	* \| \| \|CMPDAT is a 24-bit compared value register
kadonotakashi	0:8fdf9a60065b	97	* \| \| \|When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
kadonotakashi	0:8fdf9a60065b	98	* \| \| \|Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
kadonotakashi	0:8fdf9a60065b	99	* \| \| \|Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
kadonotakashi	0:8fdf9a60065b	100	* \| \| \|Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field
kadonotakashi	0:8fdf9a60065b	101	* \| \| \|But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
kadonotakashi	0:8fdf9a60065b	102	* @var TIMER_T::INTSTS
kadonotakashi	0:8fdf9a60065b	103	* Offset: 0x08 Timer Interrupt Status Register
kadonotakashi	0:8fdf9a60065b	104	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	105	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	106	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	107	* \|[0] \|TIF \|Timer Interrupt Flag
kadonotakashi	0:8fdf9a60065b	108	* \| \| \|This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
kadonotakashi	0:8fdf9a60065b	109	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	110	* \| \| \|1 = CNT value matches the CMPDAT value.
kadonotakashi	0:8fdf9a60065b	111	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	112	* \|[1] \|TWKF \|Timer Wake-up Flag
kadonotakashi	0:8fdf9a60065b	113	* \| \| \|This bit indicates the interrupt wake-up flag status of timer.
kadonotakashi	0:8fdf9a60065b	114	* \| \| \|0 = Timer does not cause CPU wake-up.
kadonotakashi	0:8fdf9a60065b	115	* \| \| \|1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
kadonotakashi	0:8fdf9a60065b	116	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	117	* @var TIMER_T::CNT
kadonotakashi	0:8fdf9a60065b	118	* Offset: 0x0C Timer Data Register
kadonotakashi	0:8fdf9a60065b	119	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	120	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	121	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	122	* \|[23:0] \|CNT \|Timer Data Register
kadonotakashi	0:8fdf9a60065b	123	* \| \| \|Read operation.
kadonotakashi	0:8fdf9a60065b	124	* \| \| \|Read this register to get CNT value. For example:
kadonotakashi	0:8fdf9a60065b	125	* \| \| \|If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value.
kadonotakashi	0:8fdf9a60065b	126	* \| \| \|If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value.
kadonotakashi	0:8fdf9a60065b	127	* \| \| \|Write operation.
kadonotakashi	0:8fdf9a60065b	128	* \| \| \|Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
kadonotakashi	0:8fdf9a60065b	129	* \|[31] \|RSTACT \|Timer Data Register Reset Active (Read Only)
kadonotakashi	0:8fdf9a60065b	130	* \| \| \|This bit indicates if the counter reset operation active.
kadonotakashi	0:8fdf9a60065b	131	* \| \| \|When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter
kadonotakashi	0:8fdf9a60065b	132	* \| \| \|At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress
kadonotakashi	0:8fdf9a60065b	133	* \| \| \|Once the counter reset operation done, timer clear this bit to 0 automatically.
kadonotakashi	0:8fdf9a60065b	134	* \| \| \|0 = Reset operation is done.
kadonotakashi	0:8fdf9a60065b	135	* \| \| \|1 = Reset operation triggered by writing TIMERx_CNT is in progress.
kadonotakashi	0:8fdf9a60065b	136	* \| \| \|Note: This bit is read only.
kadonotakashi	0:8fdf9a60065b	137	* @var TIMER_T::CAP
kadonotakashi	0:8fdf9a60065b	138	* Offset: 0x10 Timer Capture Data Register
kadonotakashi	0:8fdf9a60065b	139	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	140	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	141	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	142	* \|[23:0] \|CAPDAT \|Timer Capture Data Register
kadonotakashi	0:8fdf9a60065b	143	* \| \| \|When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
kadonotakashi	0:8fdf9a60065b	144	* @var TIMER_T::EXTCTL
kadonotakashi	0:8fdf9a60065b	145	* Offset: 0x14 Timer External Control Register
kadonotakashi	0:8fdf9a60065b	146	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	147	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	148	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	149	* \|[0] \|CNTPHASE \|Timer External Count Phase
kadonotakashi	0:8fdf9a60065b	150	* \| \| \|This bit indicates the detection phase of external counting pin TMx (x= 0~3).
kadonotakashi	0:8fdf9a60065b	151	* \| \| \|0 = A falling edge of external counting pin will be counted.
kadonotakashi	0:8fdf9a60065b	152	* \| \| \|1 = A rising edge of external counting pin will be counted.
kadonotakashi	0:8fdf9a60065b	153	* \|[3] \|CAPEN \|Timer External Capture Pin Enable Bit
kadonotakashi	0:8fdf9a60065b	154	* \| \| \|This bit enables the TMx_EXT capture pin input function.
kadonotakashi	0:8fdf9a60065b	155	* \| \| \|0 =TMx_EXT (x= 0~3) pin Disabled.
kadonotakashi	0:8fdf9a60065b	156	* \| \| \|1 =TMx_EXT (x= 0~3) pin Enabled.
kadonotakashi	0:8fdf9a60065b	157	* \|[4] \|CAPFUNCS \|Capture Function Selection
kadonotakashi	0:8fdf9a60065b	158	* \| \| \|0 = External Capture Mode Enabled.
kadonotakashi	0:8fdf9a60065b	159	* \| \| \|1 = External Reset Mode Enabled.
kadonotakashi	0:8fdf9a60065b	160	* \| \| \|Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field.
kadonotakashi	0:8fdf9a60065b	161	* \| \| \|Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately.
kadonotakashi	0:8fdf9a60065b	162	* \|[5] \|CAPIEN \|Timer External Capture Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	163	* \| \| \|0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	164	* \| \| \|1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	165	* \| \| \|Note: CAPIEN is used to enable timer external interrupt
kadonotakashi	0:8fdf9a60065b	166	* \| \| \|If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
kadonotakashi	0:8fdf9a60065b	167	* \| \| \|For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
kadonotakashi	0:8fdf9a60065b	168	* \|[6] \|CAPDBEN \|Timer External Capture Pin De-bounce Enable Bit
kadonotakashi	0:8fdf9a60065b	169	* \| \| \|0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled.
kadonotakashi	0:8fdf9a60065b	170	* \| \| \|1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled.
kadonotakashi	0:8fdf9a60065b	171	* \| \| \|Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
kadonotakashi	0:8fdf9a60065b	172	* \|[7] \|CNTDBEN \|Timer Counter Pin De-bounce Enable Bit
kadonotakashi	0:8fdf9a60065b	173	* \| \| \|0 = TMx (x= 0~3) pin de-bounce Disabled.
kadonotakashi	0:8fdf9a60065b	174	* \| \| \|1 = TMx (x= 0~3) pin de-bounce Enabled.
kadonotakashi	0:8fdf9a60065b	175	* \| \| \|Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
kadonotakashi	0:8fdf9a60065b	176	* \|[8] \|ACMPSSEL \|ACMP Source Selection to Trigger Capture Function
kadonotakashi	0:8fdf9a60065b	177	* \| \| \|0 = Capture Function source is from internal ACMP0 output signal.
kadonotakashi	0:8fdf9a60065b	178	* \| \| \|1 = Capture Function source is from internal ACMP1 output signal.
kadonotakashi	0:8fdf9a60065b	179	* \| \| \|Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
kadonotakashi	0:8fdf9a60065b	180	* \|[14:12] \|CAPEDGE \|Timer External Capture Pin Edge Detect
kadonotakashi	0:8fdf9a60065b	181	* \| \| \|When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
kadonotakashi	0:8fdf9a60065b	182	* \| \| \|000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin.
kadonotakashi	0:8fdf9a60065b	183	* \| \| \|001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin.
kadonotakashi	0:8fdf9a60065b	184	* \| \| \|010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer.
kadonotakashi	0:8fdf9a60065b	185	* \| \| \|011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer..
kadonotakashi	0:8fdf9a60065b	186	* \| \| \|110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin.
kadonotakashi	0:8fdf9a60065b	187	* \| \| \|111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin.
kadonotakashi	0:8fdf9a60065b	188	* \| \| \|100, 101 = Reserved.
kadonotakashi	0:8fdf9a60065b	189	* \|[16] \|ECNTSSEL \|Event Counter Source Selection to Trigger Event Counter Function
kadonotakashi	0:8fdf9a60065b	190	* \| \| \|0 = Event Counter input source is from TMx (x= 0~3) pin.
kadonotakashi	0:8fdf9a60065b	191	* \| \| \|1 = Event Counter input source is from USB internal SOF output signal.
kadonotakashi	0:8fdf9a60065b	192	* @var TIMER_T::EINTSTS
kadonotakashi	0:8fdf9a60065b	193	* Offset: 0x18 Timer External Interrupt Status Register
kadonotakashi	0:8fdf9a60065b	194	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	195	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	196	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	197	* \|[0] \|CAPIF \|Timer External Capture Interrupt Flag
kadonotakashi	0:8fdf9a60065b	198	* \| \| \|This bit indicates the timer external capture interrupt flag status.
kadonotakashi	0:8fdf9a60065b	199	* \| \| \|0 = TMx_EXT (x= 0~3) pin interrupt did not occur.
kadonotakashi	0:8fdf9a60065b	200	* \| \| \|1 = TMx_EXT (x= 0~3) pin interrupt occurred.
kadonotakashi	0:8fdf9a60065b	201	* \| \| \|Note1: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	202	* \| \| \|Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
kadonotakashi	0:8fdf9a60065b	203	* \| \| \|Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status
kadonotakashi	0:8fdf9a60065b	204	* \| \| \|If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
kadonotakashi	0:8fdf9a60065b	205	* @var TIMER_T::TRGCTL
kadonotakashi	0:8fdf9a60065b	206	* Offset: 0x1C Timer Trigger Control Register
kadonotakashi	0:8fdf9a60065b	207	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	208	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	209	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	210	* \|[0] \|TRGSSEL \|Trigger Source Select Bit
kadonotakashi	0:8fdf9a60065b	211	* \| \| \|This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
kadonotakashi	0:8fdf9a60065b	212	* \| \| \|0 = Time-out interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC.
kadonotakashi	0:8fdf9a60065b	213	* \| \| \|1 = Capture interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC.
kadonotakashi	0:8fdf9a60065b	214	* \|[1] \|TRGEPWM \|Trigger PWM Enable Bit
kadonotakashi	0:8fdf9a60065b	215	* \| \| \|If this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source.
kadonotakashi	0:8fdf9a60065b	216	* \| \| \|0 = Timer interrupt trigger PWM Disabled.
kadonotakashi	0:8fdf9a60065b	217	* \| \| \|1 = Timer interrupt trigger PWM Enabled.
kadonotakashi	0:8fdf9a60065b	218	* \| \| \|Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as PWM counter clock source.
kadonotakashi	0:8fdf9a60065b	219	* \| \| \|If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as PWM counter clock source.
kadonotakashi	0:8fdf9a60065b	220	* \|[2] \|TRGEADC \|Trigger EADC Enable Bit
kadonotakashi	0:8fdf9a60065b	221	* \| \| \|If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
kadonotakashi	0:8fdf9a60065b	222	* \| \| \|0 = Timer interrupt trigger EADC Disabled.
kadonotakashi	0:8fdf9a60065b	223	* \| \| \|1 = Timer interrupt trigger EADC Enabled.
kadonotakashi	0:8fdf9a60065b	224	* \| \| \|Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion.
kadonotakashi	0:8fdf9a60065b	225	* \| \| \|If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger ADC conversion.
kadonotakashi	0:8fdf9a60065b	226	* \|[3] \|TRGDAC \|Trigger DAC Enable Bit
kadonotakashi	0:8fdf9a60065b	227	* \| \| \|If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
kadonotakashi	0:8fdf9a60065b	228	* \| \| \|0 = Timer interrupt trigger DAC Disabled.
kadonotakashi	0:8fdf9a60065b	229	* \| \| \|1 = Timer interrupt trigger DAC Enabled.
kadonotakashi	0:8fdf9a60065b	230	* \| \| \|Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC.
kadonotakashi	0:8fdf9a60065b	231	* \| \| \|If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC.
kadonotakashi	0:8fdf9a60065b	232	* \|[4] \|TRGPDMA \|Trigger PDMA Enable Bit
kadonotakashi	0:8fdf9a60065b	233	* \| \| \|If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
kadonotakashi	0:8fdf9a60065b	234	* \| \| \|0 = Timer interrupt trigger PDMA Disabled.
kadonotakashi	0:8fdf9a60065b	235	* \| \| \|1 = Timer interrupt trigger PDMA Enabled.
kadonotakashi	0:8fdf9a60065b	236	* \| \| \|Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer.
kadonotakashi	0:8fdf9a60065b	237	* \| \| \|If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer.
kadonotakashi	0:8fdf9a60065b	238	* @var TIMER_T::ALTCTL
kadonotakashi	0:8fdf9a60065b	239	* Offset: 0x20 Timer Alternative Control Register
kadonotakashi	0:8fdf9a60065b	240	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	241	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	242	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	243	* \|[0] \|FUNCSEL \|Function Selection
kadonotakashi	0:8fdf9a60065b	244	* \| \| \|0 = Timer controller is used as timer function.
kadonotakashi	0:8fdf9a60065b	245	* \| \| \|1 = Timer controller is used as PWM function.
kadonotakashi	0:8fdf9a60065b	246	* \| \| \|Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
kadonotakashi	0:8fdf9a60065b	247	* @var TIMER_T::PWMCTL
kadonotakashi	0:8fdf9a60065b	248	* Offset: 0x40 Timer PWM Control Register
kadonotakashi	0:8fdf9a60065b	249	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	250	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	251	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	252	* \|[0] \|CNTEN \|PWM Counter Enable Bit
kadonotakashi	0:8fdf9a60065b	253	* \| \| \|0 = PWM counter and clock prescale Stop Running.
kadonotakashi	0:8fdf9a60065b	254	* \| \| \|1 = PWM counter and clock prescale Start Running.
kadonotakashi	0:8fdf9a60065b	255	* \|[2:1] \|CNTTYPE \|PWM Counter Behavior Type
kadonotakashi	0:8fdf9a60065b	256	* \| \| \|00 = Up count type.
kadonotakashi	0:8fdf9a60065b	257	* \| \| \|01 = Down count type.
kadonotakashi	0:8fdf9a60065b	258	* \| \| \|10 = Up-down count type.
kadonotakashi	0:8fdf9a60065b	259	* \| \| \|11 = Reserved.
kadonotakashi	0:8fdf9a60065b	260	* \|[3] \|CNTMODE \|PWM Counter Mode
kadonotakashi	0:8fdf9a60065b	261	* \| \| \|0 = Auto-reload mode.
kadonotakashi	0:8fdf9a60065b	262	* \| \| \|1 = One-shot mode.
kadonotakashi	0:8fdf9a60065b	263	* \|[8] \|CTRLD \|Center Re-load
kadonotakashi	0:8fdf9a60065b	264	* \| \| \|In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period.
kadonotakashi	0:8fdf9a60065b	265	* \|[9] \|IMMLDEN \|Immediately Load Enable Bit
kadonotakashi	0:8fdf9a60065b	266	* \| \| \|0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled
kadonotakashi	0:8fdf9a60065b	267	* \| \| \|If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period.
kadonotakashi	0:8fdf9a60065b	268	* \| \| \|1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP.
kadonotakashi	0:8fdf9a60065b	269	* \| \| \|Note: If IMMLDEN is enabled, CTRLD will be invalid.
kadonotakashi	0:8fdf9a60065b	270	* \|[16] \|OUTMODE \|PWM Output Mode
kadonotakashi	0:8fdf9a60065b	271	* \| \| \|This bit controls the output mode of corresponding PWM channel.
kadonotakashi	0:8fdf9a60065b	272	* \| \| \|0 = PWM independent mode.
kadonotakashi	0:8fdf9a60065b	273	* \| \| \|1 = PWM complementary mode.
kadonotakashi	0:8fdf9a60065b	274	* \|[30] \|DBGHALT \|ICE Debug Mode Counter Halt (Write Protect)
kadonotakashi	0:8fdf9a60065b	275	* \| \| \|If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode.
kadonotakashi	0:8fdf9a60065b	276	* \| \| \|0 = ICE debug mode counter halt disable.
kadonotakashi	0:8fdf9a60065b	277	* \| \| \|1 = ICE debug mode counter halt enable.
kadonotakashi	0:8fdf9a60065b	278	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	279	* \|[31] \|DBGTRIOFF \|ICE Debug Mode Acknowledge Disable Bit (Write Protect)
kadonotakashi	0:8fdf9a60065b	280	* \| \| \|0 = ICE debug mode acknowledgment effects PWM output.
kadonotakashi	0:8fdf9a60065b	281	* \| \| \|PWM output pin will be forced as tri-state while ICE debug mode acknowledged.
kadonotakashi	0:8fdf9a60065b	282	* \| \| \|1 = ICE debug mode acknowledgment disabled.
kadonotakashi	0:8fdf9a60065b	283	* \| \| \|PWM output pin will keep output no matter ICE debug mode acknowledged or not.
kadonotakashi	0:8fdf9a60065b	284	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	285	* @var TIMER_T::PWMCLKSRC
kadonotakashi	0:8fdf9a60065b	286	* Offset: 0x44 Timer PWM Counter Clock Source Register
kadonotakashi	0:8fdf9a60065b	287	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	288	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	289	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	290	* \|[2:0] \|CLKSRC \|PWM Counter Clock Source Select
kadonotakashi	0:8fdf9a60065b	291	* \| \| \|The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.
kadonotakashi	0:8fdf9a60065b	292	* \| \| \|000 = TMRx_CLK.
kadonotakashi	0:8fdf9a60065b	293	* \| \| \|001 = Internal TIMER0 time-out or capture event.
kadonotakashi	0:8fdf9a60065b	294	* \| \| \|010 = Internal TIMER1 time-out or capture event.
kadonotakashi	0:8fdf9a60065b	295	* \| \| \|011 = Internal TIMER2 time-out or capture event.
kadonotakashi	0:8fdf9a60065b	296	* \| \| \|100 = Internal TIMER3 time-out or capture event.
kadonotakashi	0:8fdf9a60065b	297	* \| \| \|Others = Reserved.
kadonotakashi	0:8fdf9a60065b	298	* \| \| \|Note: If Timer PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.
kadonotakashi	0:8fdf9a60065b	299	* @var TIMER_T::PWMCLKPSC
kadonotakashi	0:8fdf9a60065b	300	* Offset: 0x48 Timer PWM Counter Clock Pre-scale Register
kadonotakashi	0:8fdf9a60065b	301	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	302	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	303	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	304	* \|[11:0] \|CLKPSC \|PWM Counter Clock Pre-scale
kadonotakashi	0:8fdf9a60065b	305	* \| \| \|The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)
kadonotakashi	0:8fdf9a60065b	306	* \| \| \|If CLKPSC is 0, then there is no scaling in PWM counter clock source.
kadonotakashi	0:8fdf9a60065b	307	* @var TIMER_T::PWMCNTCLR
kadonotakashi	0:8fdf9a60065b	308	* Offset: 0x4C Timer PWM Clear Counter Register
kadonotakashi	0:8fdf9a60065b	309	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	310	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	311	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	312	* \|[0] \|CNTCLR \|Clear PWM Counter Control Bit
kadonotakashi	0:8fdf9a60065b	313	* \| \| \|It is automatically cleared by hardware.
kadonotakashi	0:8fdf9a60065b	314	* \| \| \|0 = No effect.
kadonotakashi	0:8fdf9a60065b	315	* \| \| \|1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type.
kadonotakashi	0:8fdf9a60065b	316	* @var TIMER_T::PWMPERIOD
kadonotakashi	0:8fdf9a60065b	317	* Offset: 0x50 Timer PWM Period Register
kadonotakashi	0:8fdf9a60065b	318	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	319	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	320	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	321	* \|[15:0] \|PERIOD \|PWM Period Register
kadonotakashi	0:8fdf9a60065b	322	* \| \| \|In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.
kadonotakashi	0:8fdf9a60065b	323	* \| \| \|In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.
kadonotakashi	0:8fdf9a60065b	324	* \| \| \|In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
kadonotakashi	0:8fdf9a60065b	325	* \| \| \|In up and down count type:
kadonotakashi	0:8fdf9a60065b	326	* \| \| \|PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK.
kadonotakashi	0:8fdf9a60065b	327	* \| \| \|In up-down count type:
kadonotakashi	0:8fdf9a60065b	328	* \| \| \|PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK.
kadonotakashi	0:8fdf9a60065b	329	* \| \| \|Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type.
kadonotakashi	0:8fdf9a60065b	330	* @var TIMER_T::PWMCMPDAT
kadonotakashi	0:8fdf9a60065b	331	* Offset: 0x54 Timer PWM Comparator Register
kadonotakashi	0:8fdf9a60065b	332	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	333	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	334	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	335	* \|[15:0] \|CMP \|PWM Comparator Register
kadonotakashi	0:8fdf9a60065b	336	* \| \| \|PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert.
kadonotakashi	0:8fdf9a60065b	337	* @var TIMER_T::PWMDTCTL
kadonotakashi	0:8fdf9a60065b	338	* Offset: 0x58 Timer PWM Dead-Time Control Register
kadonotakashi	0:8fdf9a60065b	339	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	340	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	341	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	342	* \|[11:0] \|DTCNT \|Dead-time Counter (Write Protect)
kadonotakashi	0:8fdf9a60065b	343	* \| \| \|The dead-time can be calculated from the following two formulas:
kadonotakashi	0:8fdf9a60065b	344	* \| \| \|Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0.
kadonotakashi	0:8fdf9a60065b	345	* \| \| \|Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1.
kadonotakashi	0:8fdf9a60065b	346	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	347	* \|[16] \|DTEN \|Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)
kadonotakashi	0:8fdf9a60065b	348	* \| \| \|Dead-time insertion function is only active when PWM complementary mode is enabled
kadonotakashi	0:8fdf9a60065b	349	* \| \| \|If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.
kadonotakashi	0:8fdf9a60065b	350	* \| \| \|0 = Dead-time insertion Disabled on the pin pair.
kadonotakashi	0:8fdf9a60065b	351	* \| \| \|1 = Dead-time insertion Enabled on the pin pair.
kadonotakashi	0:8fdf9a60065b	352	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	353	* \|[24] \|DTCKSEL \|Dead-time Clock Select (Write Protect)
kadonotakashi	0:8fdf9a60065b	354	* \| \| \|0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale.
kadonotakashi	0:8fdf9a60065b	355	* \| \| \|1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale.
kadonotakashi	0:8fdf9a60065b	356	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	357	* @var TIMER_T::PWMCNT
kadonotakashi	0:8fdf9a60065b	358	* Offset: 0x5C Timer PWM Counter Register
kadonotakashi	0:8fdf9a60065b	359	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	360	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	361	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	362	* \|[15:0] \|CNT \|PWM Counter Value Register (Read Only)
kadonotakashi	0:8fdf9a60065b	363	* \| \| \|User can monitor CNT to know the current counter value in 16-bit period counter.
kadonotakashi	0:8fdf9a60065b	364	* \|[16] \|DIRF \|PWM Counter Direction Indicator Flag (Read Only)
kadonotakashi	0:8fdf9a60065b	365	* \| \| \|0 = Counter is active in down count.
kadonotakashi	0:8fdf9a60065b	366	* \| \| \|1 = Counter is active up count.
kadonotakashi	0:8fdf9a60065b	367	* @var TIMER_T::PWMMSKEN
kadonotakashi	0:8fdf9a60065b	368	* Offset: 0x60 Timer PWM Output Mask Enable Register
kadonotakashi	0:8fdf9a60065b	369	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	370	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	371	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	372	* \|[0] \|MSKEN0 \|PWMx_CH0 Output Mask Enable Bit
kadonotakashi	0:8fdf9a60065b	373	* \| \| \|The PWMx_CH0 output signal will be masked when this bit is enabled
kadonotakashi	0:8fdf9a60065b	374	* \| \| \|The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data.
kadonotakashi	0:8fdf9a60065b	375	* \| \| \|0 = PWMx_CH0 output signal is non-masked.
kadonotakashi	0:8fdf9a60065b	376	* \| \| \|1 = PWMx_CH0 output signal is masked and output MSKDAT0 data.
kadonotakashi	0:8fdf9a60065b	377	* \|[1] \|MSKEN1 \|PWMx_CH1 Output Mask Enable Bit
kadonotakashi	0:8fdf9a60065b	378	* \| \| \|The PWMx_CH1 output signal will be masked when this bit is enabled
kadonotakashi	0:8fdf9a60065b	379	* \| \| \|The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data.
kadonotakashi	0:8fdf9a60065b	380	* \| \| \|0 = PWMx_CH1 output signal is non-masked.
kadonotakashi	0:8fdf9a60065b	381	* \| \| \|1 = PWMx_CH1 output signal is masked and output MSKDAT1 data.
kadonotakashi	0:8fdf9a60065b	382	* @var TIMER_T::PWMMSK
kadonotakashi	0:8fdf9a60065b	383	* Offset: 0x64 Timer PWM Output Mask Data Control Register
kadonotakashi	0:8fdf9a60065b	384	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	385	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	386	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	387	* \|[0] \|MSKDAT0 \|PWMx_CH0 Output Mask Data Control Bit
kadonotakashi	0:8fdf9a60065b	388	* \| \| \|This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1).
kadonotakashi	0:8fdf9a60065b	389	* \| \| \|0 = Output logic Low to PWMx_CH0.
kadonotakashi	0:8fdf9a60065b	390	* \| \| \|1 = Output logic High to PWMx_CH0.
kadonotakashi	0:8fdf9a60065b	391	* \|[1] \|MSKDAT1 \|PWMx_CH1 Output Mask Data Control Bit
kadonotakashi	0:8fdf9a60065b	392	* \| \| \|This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1).
kadonotakashi	0:8fdf9a60065b	393	* \| \| \|0 = Output logic Low to PWMx_CH1.
kadonotakashi	0:8fdf9a60065b	394	* \| \| \|1 = Output logic High to PWMx_CH1.
kadonotakashi	0:8fdf9a60065b	395	* @var TIMER_T::PWMBNF
kadonotakashi	0:8fdf9a60065b	396	* Offset: 0x68 Timer PWM Brake Pin Noise Filter Register
kadonotakashi	0:8fdf9a60065b	397	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	398	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	399	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	400	* \|[0] \|BRKNFEN \|Brake Pin Noise Filter Enable Bit
kadonotakashi	0:8fdf9a60065b	401	* \| \| \|0 = Pin noise filter detect of PWMx_BRAKEy Disabled.
kadonotakashi	0:8fdf9a60065b	402	* \| \| \|1 = Pin noise filter detect of PWMx_BRAKEy Enabled.
kadonotakashi	0:8fdf9a60065b	403	* \|[3:1] \|BRKNFSEL \|Brake Pin Noise Filter Clock Selection
kadonotakashi	0:8fdf9a60065b	404	* \| \| \|000 = Noise filter clock is PCLKx.
kadonotakashi	0:8fdf9a60065b	405	* \| \| \|001 = Noise filter clock is PCLKx/2.
kadonotakashi	0:8fdf9a60065b	406	* \| \| \|010 = Noise filter clock is PCLKx/4.
kadonotakashi	0:8fdf9a60065b	407	* \| \| \|011 = Noise filter clock is PCLKx/8.
kadonotakashi	0:8fdf9a60065b	408	* \| \| \|100 = Noise filter clock is PCLKx/16.
kadonotakashi	0:8fdf9a60065b	409	* \| \| \|101 = Noise filter clock is PCLKx/32.
kadonotakashi	0:8fdf9a60065b	410	* \| \| \|110 = Noise filter clock is PCLKx/64.
kadonotakashi	0:8fdf9a60065b	411	* \| \| \|111 = Noise filter clock is PCLKx/128.
kadonotakashi	0:8fdf9a60065b	412	* \|[6:4] \|BRKFCNT \|Brake Pin Noise Filter Count
kadonotakashi	0:8fdf9a60065b	413	* \| \| \|The fields is used to control the active noise filter sample time.
kadonotakashi	0:8fdf9a60065b	414	* \| \| \|Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT.
kadonotakashi	0:8fdf9a60065b	415	* \|[7] \|BRKPINV \|Brake Pin Detection Control Bit
kadonotakashi	0:8fdf9a60065b	416	* \| \| \|0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect.
kadonotakashi	0:8fdf9a60065b	417	* \| \| \|1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect .
kadonotakashi	0:8fdf9a60065b	418	* \|[17:16] \|BKPINSRC \|Brake Pin Source Select
kadonotakashi	0:8fdf9a60065b	419	* \| \| \|00 = Brake pin source comes from PWM0_BRAKE0 pin.
kadonotakashi	0:8fdf9a60065b	420	* \| \| \|01 = Brake pin source comes from PWM0_BRAKE1 pin.
kadonotakashi	0:8fdf9a60065b	421	* \| \| \|10 = Brake pin source comes from PWM1_BRAKE0 pin.
kadonotakashi	0:8fdf9a60065b	422	* \| \| \|11 = Brake pin source comes from PWM1_BRAKE1 pin.
kadonotakashi	0:8fdf9a60065b	423	* @var TIMER_T::PWMFAILBRK
kadonotakashi	0:8fdf9a60065b	424	* Offset: 0x6C Timer PWM System Fail Brake Control Register
kadonotakashi	0:8fdf9a60065b	425	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	426	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	427	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	428	* \|[0] \|CSSBRKEN \|Clock Security System Detection Trigger PWM Brake Function Enable Bit
kadonotakashi	0:8fdf9a60065b	429	* \| \| \|0 = Brake Function triggered by clock fail detection Disabled.
kadonotakashi	0:8fdf9a60065b	430	* \| \| \|1 = Brake Function triggered by clock fail detection Enabled.
kadonotakashi	0:8fdf9a60065b	431	* \|[1] \|BODBRKEN \|Brown-out Detection Trigger PWM Brake Function Enable Bit
kadonotakashi	0:8fdf9a60065b	432	* \| \| \|0 = Brake Function triggered by BOD event Disabled.
kadonotakashi	0:8fdf9a60065b	433	* \| \| \|1 = Brake Function triggered by BOD event Enabled.
kadonotakashi	0:8fdf9a60065b	434	* \|[2] \|RAMBRKEN \|SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit
kadonotakashi	0:8fdf9a60065b	435	* \| \| \|0 = Brake Function triggered by SRAM parity error detection Disabled.
kadonotakashi	0:8fdf9a60065b	436	* \| \| \|1 = Brake Function triggered by SRAM parity error detection Enabled.
kadonotakashi	0:8fdf9a60065b	437	* \|[3] \|CORBRKEN \|Core Lockup Detection Trigger PWM Brake Function Enable Bit
kadonotakashi	0:8fdf9a60065b	438	* \| \| \|0 = Brake Function triggered by core lockup event Disabled.
kadonotakashi	0:8fdf9a60065b	439	* \| \| \|1 = Brake Function triggered by core lockup event Enabled.
kadonotakashi	0:8fdf9a60065b	440	* @var TIMER_T::PWMBRKCTL
kadonotakashi	0:8fdf9a60065b	441	* Offset: 0x70 Timer PWM Brake Control Register
kadonotakashi	0:8fdf9a60065b	442	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	443	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	444	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	445	* \|[0] \|CPO0EBEN \|Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
kadonotakashi	0:8fdf9a60065b	446	* \| \| \|0 = Internal ACMP0_O signal as edge-detect brake source Disabled.
kadonotakashi	0:8fdf9a60065b	447	* \| \| \|1 = Internal ACMP0_O signal as edge-detect brake source Enabled.
kadonotakashi	0:8fdf9a60065b	448	* \| \| \|Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
kadonotakashi	0:8fdf9a60065b	449	* \| \| \|Note2: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	450	* \|[1] \|CPO1EBEN \|Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
kadonotakashi	0:8fdf9a60065b	451	* \| \| \|0 = Internal ACMP1_O signal as edge-detect brake source Disabled.
kadonotakashi	0:8fdf9a60065b	452	* \| \| \|1 = Internal ACMP1_O signal as edge-detect brake source Enabled.
kadonotakashi	0:8fdf9a60065b	453	* \| \| \|Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
kadonotakashi	0:8fdf9a60065b	454	* \| \| \|Note2: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	455	* \|[4] \|BRKPEEN \|Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)
kadonotakashi	0:8fdf9a60065b	456	* \| \| \|0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled.
kadonotakashi	0:8fdf9a60065b	457	* \| \| \|1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled.
kadonotakashi	0:8fdf9a60065b	458	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	459	* \|[7] \|SYSEBEN \|Enable System Fail As Edge-detect Brake Source (Write Protect)
kadonotakashi	0:8fdf9a60065b	460	* \| \| \|0 = System fail condition as edge-detect brake source Disabled.
kadonotakashi	0:8fdf9a60065b	461	* \| \| \|1 = System fail condition as edge-detect brake source Enabled.
kadonotakashi	0:8fdf9a60065b	462	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	463	* \|[8] \|CPO0LBEN \|Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
kadonotakashi	0:8fdf9a60065b	464	* \| \| \|0 = Internal ACMP0_O signal as level-detect brake source Disabled.
kadonotakashi	0:8fdf9a60065b	465	* \| \| \|1 = Internal ACMP0_O signal as level-detect brake source Enabled.
kadonotakashi	0:8fdf9a60065b	466	* \| \| \|Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
kadonotakashi	0:8fdf9a60065b	467	* \| \| \|Note2: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	468	* \|[9] \|CPO1LBEN \|Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
kadonotakashi	0:8fdf9a60065b	469	* \| \| \|0 = Internal ACMP1_O signal as level-detect brake source Disabled.
kadonotakashi	0:8fdf9a60065b	470	* \| \| \|1 = Internal ACMP1_O signal as level-detect brake source Enabled.
kadonotakashi	0:8fdf9a60065b	471	* \| \| \|Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
kadonotakashi	0:8fdf9a60065b	472	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	473	* \|[12] \|BRKPLEN \|Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)
kadonotakashi	0:8fdf9a60065b	474	* \| \| \|0 = PWMx_BRAKEy pin event as level-detect brake source Disabled.
kadonotakashi	0:8fdf9a60065b	475	* \| \| \|1 = PWMx_BRAKEy pin event as level-detect brake source Enabled.
kadonotakashi	0:8fdf9a60065b	476	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	477	* \|[15] \|SYSLBEN \|Enable System Fail As Level-detect Brake Source (Write Protect)
kadonotakashi	0:8fdf9a60065b	478	* \| \| \|0 = System fail condition as level-detect brake source Disabled.
kadonotakashi	0:8fdf9a60065b	479	* \| \| \|1 = System fail condition as level-detect brake source Enabled.
kadonotakashi	0:8fdf9a60065b	480	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	481	* \|[17:16] \|BRKAEVEN \|PWM Brake Action Select for PWMx_CH0 (Write Protect)
kadonotakashi	0:8fdf9a60065b	482	* \| \| \|00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output.
kadonotakashi	0:8fdf9a60065b	483	* \| \| \|01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened.
kadonotakashi	0:8fdf9a60065b	484	* \| \| \|10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened.
kadonotakashi	0:8fdf9a60065b	485	* \| \| \|11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened.
kadonotakashi	0:8fdf9a60065b	486	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	487	* \|[19:18] \|BRKAODD \|PWM Brake Action Select for PWMx_CH1 (Write Protect)
kadonotakashi	0:8fdf9a60065b	488	* \| \| \|00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output.
kadonotakashi	0:8fdf9a60065b	489	* \| \| \|01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened.
kadonotakashi	0:8fdf9a60065b	490	* \| \| \|10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened.
kadonotakashi	0:8fdf9a60065b	491	* \| \| \|11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened.
kadonotakashi	0:8fdf9a60065b	492	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	493	* @var TIMER_T::PWMPOLCTL
kadonotakashi	0:8fdf9a60065b	494	* Offset: 0x74 Timer PWM Pin Output Polar Control Register
kadonotakashi	0:8fdf9a60065b	495	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	496	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	497	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	498	* \|[0] \|PINV0 \|PWMx_CH0 Output Pin Polar Control Bit
kadonotakashi	0:8fdf9a60065b	499	* \| \| \|The bit is used to control polarity state of PWMx_CH0 output pin.
kadonotakashi	0:8fdf9a60065b	500	* \| \| \|0 = PWMx_CH0 output pin polar inverse Disabled.
kadonotakashi	0:8fdf9a60065b	501	* \| \| \|1 = PWMx_CH0 output pin polar inverse Enabled.
kadonotakashi	0:8fdf9a60065b	502	* \|[1] \|PINV1 \|PWMx_CH1 Output Pin Polar Control Bit
kadonotakashi	0:8fdf9a60065b	503	* \| \| \|The bit is used to control polarity state of PWMx_CH1 output pin.
kadonotakashi	0:8fdf9a60065b	504	* \| \| \|0 = PWMx_CH1 output pin polar inverse Disabled.
kadonotakashi	0:8fdf9a60065b	505	* \| \| \|1 = PWMx_CH1 output pin polar inverse Enabled.
kadonotakashi	0:8fdf9a60065b	506	* @var TIMER_T::PWMPOEN
kadonotakashi	0:8fdf9a60065b	507	* Offset: 0x78 Timer PWM Pin Output Enable Register
kadonotakashi	0:8fdf9a60065b	508	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	509	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	510	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	511	* \|[0] \|POEN0 \|PWMx_CH0 Output Pin Enable Bit
kadonotakashi	0:8fdf9a60065b	512	* \| \| \|0 = PWMx_CH0 pin at tri-state mode.
kadonotakashi	0:8fdf9a60065b	513	* \| \| \|1 = PWMx_CH0 pin in output mode.
kadonotakashi	0:8fdf9a60065b	514	* \|[1] \|POEN1 \|PWMx_CH1 Output Pin Enable Bit
kadonotakashi	0:8fdf9a60065b	515	* \| \| \|0 = PWMx_CH1 pin at tri-state mode.
kadonotakashi	0:8fdf9a60065b	516	* \| \| \|1 = PWMx_CH1 pin in output mode.
kadonotakashi	0:8fdf9a60065b	517	* @var TIMER_T::PWMSWBRK
kadonotakashi	0:8fdf9a60065b	518	* Offset: 0x7C Timer PWM Software Trigger Brake Control Register
kadonotakashi	0:8fdf9a60065b	519	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	520	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	521	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	522	* \|[0] \|BRKETRG \|Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)
kadonotakashi	0:8fdf9a60065b	523	* \| \| \|Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
kadonotakashi	0:8fdf9a60065b	524	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	525	* \|[8] \|BRKLTRG \|Software Trigger Level-detect Brake Source (Write Only) (Write Protect)
kadonotakashi	0:8fdf9a60065b	526	* \| \| \|Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
kadonotakashi	0:8fdf9a60065b	527	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	528	* @var TIMER_T::PWMINTEN0
kadonotakashi	0:8fdf9a60065b	529	* Offset: 0x80 Timer PWM Interrupt Enable Register 0
kadonotakashi	0:8fdf9a60065b	530	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	531	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	532	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	533	* \|[0] \|ZIEN \|PWM Zero Point Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	534	* \| \| \|0 = Zero point interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	535	* \| \| \|1 = Zero point interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	536	* \|[1] \|PIEN \|PWM Period Point Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	537	* \| \| \|0 = Period point interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	538	* \| \| \|1 = Period point interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	539	* \| \| \|Note: When in up-down count type, period point means the center point of current PWM period.
kadonotakashi	0:8fdf9a60065b	540	* \|[2] \|CMPUIEN \|PWM Compare Up Count Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	541	* \| \| \|0 = Compare up count interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	542	* \| \| \|1 = Compare up count interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	543	* \|[3] \|CMPDIEN \|PWM Compare Down Count Interrupt Enable Bit
kadonotakashi	0:8fdf9a60065b	544	* \| \| \|0 = Compare down count interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	545	* \| \| \|1 = Compare down count interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	546	* @var TIMER_T::PWMINTEN1
kadonotakashi	0:8fdf9a60065b	547	* Offset: 0x84 Timer PWM Interrupt Enable Register 1
kadonotakashi	0:8fdf9a60065b	548	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	549	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	550	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	551	* \|[0] \|BRKEIEN \|PWM Edge-detect Brake Interrupt Enable (Write Protect)
kadonotakashi	0:8fdf9a60065b	552	* \| \| \|0 = PWM edge-detect brake interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	553	* \| \| \|1 = PWM edge-detect brake interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	554	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	555	* \|[8] \|BRKLIEN \|PWM Level-detect Brake Interrupt Enable (Write Protect)
kadonotakashi	0:8fdf9a60065b	556	* \| \| \|0 = PWM level-detect brake interrupt Disabled.
kadonotakashi	0:8fdf9a60065b	557	* \| \| \|1 = PWM level-detect brake interrupt Enabled.
kadonotakashi	0:8fdf9a60065b	558	* \| \| \|Note: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	559	* @var TIMER_T::PWMINTSTS0
kadonotakashi	0:8fdf9a60065b	560	* Offset: 0x88 Timer PWM Interrupt Status Register 0
kadonotakashi	0:8fdf9a60065b	561	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	562	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	563	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	564	* \|[0] \|ZIF \|PWM Zero Point Interrupt Flag
kadonotakashi	0:8fdf9a60065b	565	* \| \| \|This bit is set by hardware when TIMERx_PWM counter reaches zero.
kadonotakashi	0:8fdf9a60065b	566	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	567	* \|[1] \|PIF \|PWM Period Point Interrupt Flag
kadonotakashi	0:8fdf9a60065b	568	* \| \| \|This bit is set by hardware when TIMERx_PWM counter reaches PERIOD.
kadonotakashi	0:8fdf9a60065b	569	* \| \| \|Note1: When in up-down count type, PIF flag means the center point flag of current PWM period.
kadonotakashi	0:8fdf9a60065b	570	* \| \| \|Note2: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	571	* \|[2] \|CMPUIF \|PWM Compare Up Count Interrupt Flag
kadonotakashi	0:8fdf9a60065b	572	* \| \| \|This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.
kadonotakashi	0:8fdf9a60065b	573	* \| \| \|Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type..
kadonotakashi	0:8fdf9a60065b	574	* \| \| \|Note2: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	575	* \|[3] \|CMPDIF \|PWM Compare Down Count Interrupt Flag
kadonotakashi	0:8fdf9a60065b	576	* \| \| \|This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.
kadonotakashi	0:8fdf9a60065b	577	* \| \| \|Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.
kadonotakashi	0:8fdf9a60065b	578	* \| \| \|Note2: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	579	* @var TIMER_T::PWMINTSTS1
kadonotakashi	0:8fdf9a60065b	580	* Offset: 0x8C Timer PWM Interrupt Status Register 1
kadonotakashi	0:8fdf9a60065b	581	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	582	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	583	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	584	* \|[0] \|BRKEIF0 \|Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
kadonotakashi	0:8fdf9a60065b	585	* \| \| \|0 = PWMx_CH0 edge-detect brake event do not happened.
kadonotakashi	0:8fdf9a60065b	586	* \| \| \|1 = PWMx_CH0 edge-detect brake event happened.
kadonotakashi	0:8fdf9a60065b	587	* \| \| \|Note1: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	588	* \| \| \|Note2: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	589	* \|[1] \|BRKEIF1 \|Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)
kadonotakashi	0:8fdf9a60065b	590	* \| \| \|0 = PWMx_CH1 edge-detect brake event do not happened.
kadonotakashi	0:8fdf9a60065b	591	* \| \| \|1 = PWMx_CH1 edge-detect brake event happened.
kadonotakashi	0:8fdf9a60065b	592	* \| \| \|Note1: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	593	* \| \| \|Note2: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	594	* \|[8] \|BRKLIF0 \|Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
kadonotakashi	0:8fdf9a60065b	595	* \| \| \|0 = PWMx_CH0 level-detect brake event do not happened.
kadonotakashi	0:8fdf9a60065b	596	* \| \| \|1 = PWMx_CH0 level-detect brake event happened.
kadonotakashi	0:8fdf9a60065b	597	* \| \| \|Note1: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	598	* \| \| \|Note2: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	599	* \|[9] \|BRKLIF1 \|Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)
kadonotakashi	0:8fdf9a60065b	600	* \| \| \|0 = PWMx_CH1 level-detect brake event do not happened.
kadonotakashi	0:8fdf9a60065b	601	* \| \| \|1 = PWMx_CH1 level-detect brake event happened.
kadonotakashi	0:8fdf9a60065b	602	* \| \| \|Note1: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	603	* \| \| \|Note2: This register is write protected. Refer toSYS_REGLCTL register.
kadonotakashi	0:8fdf9a60065b	604	* \|[16] \|BRKESTS0 \|Edge -detect Brake Status of PWMx_CH0 (Read Only)
kadonotakashi	0:8fdf9a60065b	605	* \| \| \|0 = PWMx_CH0 edge-detect brake state is released.
kadonotakashi	0:8fdf9a60065b	606	* \| \| \|1 = PWMx_CH0 at edge-detect brake state.
kadonotakashi	0:8fdf9a60065b	607	* \| \| \|Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period.
kadonotakashi	0:8fdf9a60065b	608	* \|[17] \|BRKESTS1 \|Edge-detect Brake Status of PWMx_CH1 (Read Only)
kadonotakashi	0:8fdf9a60065b	609	* \| \| \|0 = PWMx_CH1 edge-detect brake state is released.
kadonotakashi	0:8fdf9a60065b	610	* \| \| \|1 = PWMx_CH1 at edge-detect brake state.
kadonotakashi	0:8fdf9a60065b	611	* \| \| \|Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period.
kadonotakashi	0:8fdf9a60065b	612	* \|[24] \|BRKLSTS0 \|Level-detect Brake Status of PWMx_CH0 (Read Only)
kadonotakashi	0:8fdf9a60065b	613	* \| \| \|0 = PWMx_CH0 level-detect brake state is released.
kadonotakashi	0:8fdf9a60065b	614	* \| \| \|1 = PWMx_CH0 at level-detect brake state.
kadonotakashi	0:8fdf9a60065b	615	* \| \| \|Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
kadonotakashi	0:8fdf9a60065b	616	* \|[25] \|BRKLSTS1 \|Level-detect Brake Status of PWMx_CH1 (Read Only)
kadonotakashi	0:8fdf9a60065b	617	* \| \| \|0 = PWMx_CH1 level-detect brake state is released.
kadonotakashi	0:8fdf9a60065b	618	* \| \| \|1 = PWMx_CH1 at level-detect brake state.
kadonotakashi	0:8fdf9a60065b	619	* \| \| \|Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
kadonotakashi	0:8fdf9a60065b	620	* @var TIMER_T::PWMADCTS
kadonotakashi	0:8fdf9a60065b	621	* Offset: 0x90 Timer PWM ADC Trigger Source Select Register
kadonotakashi	0:8fdf9a60065b	622	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	623	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	624	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	625	* \|[2:0] \|TRGSEL \|PWM Counter Event Source Select to Trigger EADC Conversion
kadonotakashi	0:8fdf9a60065b	626	* \| \| \|000 = Trigger EADC conversion at zero point (ZIF).
kadonotakashi	0:8fdf9a60065b	627	* \| \| \|001 = Trigger EADC conversion at period point (PIF).
kadonotakashi	0:8fdf9a60065b	628	* \| \| \|010 = Trigger EADC conversion at zero or period point (ZIF or PIF).
kadonotakashi	0:8fdf9a60065b	629	* \| \| \|011 = Trigger EADC conversion at compare up count point (CMPUIF).
kadonotakashi	0:8fdf9a60065b	630	* \| \| \|100 = Trigger EADC conversion at compare down count point (CMPDIF).
kadonotakashi	0:8fdf9a60065b	631	* \| \| \|Others = Reserved.
kadonotakashi	0:8fdf9a60065b	632	* \|[7] \|TRGEN \|PWM Counter Event Trigger EADC Conversion Enable Bit
kadonotakashi	0:8fdf9a60065b	633	* \| \| \|0 = PWM counter event trigger EADC conversion Disabled.
kadonotakashi	0:8fdf9a60065b	634	* \| \| \|1 = PWM counter event trigger EADC conversion Enabled.
kadonotakashi	0:8fdf9a60065b	635	* @var TIMER_T::PWMSCTL
kadonotakashi	0:8fdf9a60065b	636	* Offset: 0x94 Timer PWM Synchronous Control Register
kadonotakashi	0:8fdf9a60065b	637	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	638	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	639	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	640	* \|[1:0] \|SYNCMODE \|PWM Synchronous Mode Enable Select
kadonotakashi	0:8fdf9a60065b	641	* \| \| \|00 = PWM synchronous function Disabled.
kadonotakashi	0:8fdf9a60065b	642	* \| \| \|01 = PWM synchronous counter start function Enabled.
kadonotakashi	0:8fdf9a60065b	643	* \| \| \|10 = Reserved.
kadonotakashi	0:8fdf9a60065b	644	* \| \| \|11 = PWM synchronous counter clear function Enabled.
kadonotakashi	0:8fdf9a60065b	645	* \|[8] \|SYNCSRC \|PWM Synchronous Counter Start/Clear Source Select
kadonotakashi	0:8fdf9a60065b	646	* \| \| \|0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN.
kadonotakashi	0:8fdf9a60065b	647	* \| \| \|1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN.
kadonotakashi	0:8fdf9a60065b	648	* \| \| \|Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.
kadonotakashi	0:8fdf9a60065b	649	* \| \| \|Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1.
kadonotakashi	0:8fdf9a60065b	650	* @var TIMER_T::PWMSTRG
kadonotakashi	0:8fdf9a60065b	651	* Offset: 0x98 Timer PWM Synchronous Trigger Register
kadonotakashi	0:8fdf9a60065b	652	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	653	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	654	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	655	* \|[0] \|STRGEN \|PWM Counter Synchronous Trigger Enable Bit (Write Only)
kadonotakashi	0:8fdf9a60065b	656	* \| \| \|PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.
kadonotakashi	0:8fdf9a60065b	657	* \| \| \|Note: This bit is only available in TIMER0 and TIMER2.
kadonotakashi	0:8fdf9a60065b	658	* @var TIMER_T::PWMSTATUS
kadonotakashi	0:8fdf9a60065b	659	* Offset: 0x9C Timer PWM Status Register
kadonotakashi	0:8fdf9a60065b	660	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	661	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	662	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	663	* \|[0] \|CNTMAXF \|PWM Counter Equal to 0xFFFF Flag
kadonotakashi	0:8fdf9a60065b	664	* \| \| \|0 = Indicates the PWM counter value never reached its maximum value 0xFFFF.
kadonotakashi	0:8fdf9a60065b	665	* \| \| \|1 = Indicates the PWM counter value has reached its maximum value.
kadonotakashi	0:8fdf9a60065b	666	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	667	* \|[16] \|EADCTRGF \|Trigger EADC Start Conversion Flag
kadonotakashi	0:8fdf9a60065b	668	* \| \| \|0 = PWM counter event trigger EADC start conversion is not occurred.
kadonotakashi	0:8fdf9a60065b	669	* \| \| \|1 = PWM counter event trigger EADC start conversion has occurred.
kadonotakashi	0:8fdf9a60065b	670	* \| \| \|Note: This bit is cleared by writing 1 to it.
kadonotakashi	0:8fdf9a60065b	671	* @var TIMER_T::PWMPBUF
kadonotakashi	0:8fdf9a60065b	672	* Offset: 0xA0 Timer PWM Period Buffer Register
kadonotakashi	0:8fdf9a60065b	673	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	674	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	675	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	676	* \|[15:0] \|PBUF \|PWM Period Buffer Register (Read Only)
kadonotakashi	0:8fdf9a60065b	677	* \| \| \|Used as PERIOD active register.
kadonotakashi	0:8fdf9a60065b	678	* @var TIMER_T::PWMCMPBUF
kadonotakashi	0:8fdf9a60065b	679	* Offset: 0xA4 Timer PWM Comparator Buffer Register
kadonotakashi	0:8fdf9a60065b	680	* ---------------------------------------------------------------------------------------------------
kadonotakashi	0:8fdf9a60065b	681	* \|Bits \|Field \|Descriptions
kadonotakashi	0:8fdf9a60065b	682	* \| :----: \| :----: \| :---- \|
kadonotakashi	0:8fdf9a60065b	683	* \|[15:0] \|CMPBUF \|PWM Comparator Buffer Register (Read Only)
kadonotakashi	0:8fdf9a60065b	684	* \| \| \|Used as CMP active register.
kadonotakashi	0:8fdf9a60065b	685	*/
kadonotakashi	0:8fdf9a60065b	686	__IO uint32_t CTL; /!< [0x0000] Timer Control Register /
kadonotakashi	0:8fdf9a60065b	687	__IO uint32_t CMP; /!< [0x0004] Timer Comparator Register /
kadonotakashi	0:8fdf9a60065b	688	__IO uint32_t INTSTS; /!< [0x0008] Timer Interrupt Status Register /
kadonotakashi	0:8fdf9a60065b	689	__IO uint32_t CNT; /!< [0x000c] Timer Data Register /
kadonotakashi	0:8fdf9a60065b	690	__I uint32_t CAP; /!< [0x0010] Timer Capture Data Register /
kadonotakashi	0:8fdf9a60065b	691	__IO uint32_t EXTCTL; /!< [0x0014] Timer External Control Register /
kadonotakashi	0:8fdf9a60065b	692	__IO uint32_t EINTSTS; /!< [0x0018] Timer External Interrupt Status Register /
kadonotakashi	0:8fdf9a60065b	693	__IO uint32_t TRGCTL; /!< [0x001c] Timer Trigger Control Register /
kadonotakashi	0:8fdf9a60065b	694	__IO uint32_t ALTCTL; /!< [0x0020] Timer Alternative Control Register /
kadonotakashi	0:8fdf9a60065b	695	__I uint32_t RESERVE0[7];
kadonotakashi	0:8fdf9a60065b	696	__IO uint32_t PWMCTL; /!< [0x0040] Timer PWM Control Register /
kadonotakashi	0:8fdf9a60065b	697	__IO uint32_t PWMCLKSRC; /!< [0x0044] Timer PWM Counter Clock Source Register /
kadonotakashi	0:8fdf9a60065b	698	__IO uint32_t PWMCLKPSC; /!< [0x0048] Timer PWM Counter Clock Pre-scale Register /
kadonotakashi	0:8fdf9a60065b	699	__IO uint32_t PWMCNTCLR; /!< [0x004c] Timer PWM Clear Counter Register /
kadonotakashi	0:8fdf9a60065b	700	__IO uint32_t PWMPERIOD; /!< [0x0050] Timer PWM Period Register /
kadonotakashi	0:8fdf9a60065b	701	__IO uint32_t PWMCMPDAT; /!< [0x0054] Timer PWM Comparator Register /
kadonotakashi	0:8fdf9a60065b	702	__IO uint32_t PWMDTCTL; /!< [0x0058] Timer PWM Dead-Time Control Register /
kadonotakashi	0:8fdf9a60065b	703	__I uint32_t PWMCNT; /!< [0x005c] Timer PWM Counter Register /
kadonotakashi	0:8fdf9a60065b	704	__IO uint32_t PWMMSKEN; /!< [0x0060] Timer PWM Output Mask Enable Register /
kadonotakashi	0:8fdf9a60065b	705	__IO uint32_t PWMMSK; /!< [0x0064] Timer PWM Output Mask Data Control Register /
kadonotakashi	0:8fdf9a60065b	706	__IO uint32_t PWMBNF; /!< [0x0068] Timer PWM Brake Pin Noise Filter Register /
kadonotakashi	0:8fdf9a60065b	707	__IO uint32_t PWMFAILBRK; /!< [0x006c] Timer PWM System Fail Brake Control Register /
kadonotakashi	0:8fdf9a60065b	708	__IO uint32_t PWMBRKCTL; /!< [0x0070] Timer PWM Brake Control Register /
kadonotakashi	0:8fdf9a60065b	709	__IO uint32_t PWMPOLCTL; /!< [0x0074] Timer PWM Pin Output Polar Control Register /
kadonotakashi	0:8fdf9a60065b	710	__IO uint32_t PWMPOEN; /!< [0x0078] Timer PWM Pin Output Enable Register /
kadonotakashi	0:8fdf9a60065b	711	__O uint32_t PWMSWBRK; /!< [0x007c] Timer PWM Software Trigger Brake Control Register /
kadonotakashi	0:8fdf9a60065b	712	__IO uint32_t PWMINTEN0; /!< [0x0080] Timer PWM Interrupt Enable Register 0 /
kadonotakashi	0:8fdf9a60065b	713	__IO uint32_t PWMINTEN1; /!< [0x0084] Timer PWM Interrupt Enable Register 1 /
kadonotakashi	0:8fdf9a60065b	714	__IO uint32_t PWMINTSTS0; /!< [0x0088] Timer PWM Interrupt Status Register 0 /
kadonotakashi	0:8fdf9a60065b	715	__IO uint32_t PWMINTSTS1; /!< [0x008c] Timer PWM Interrupt Status Register 1 /
kadonotakashi	0:8fdf9a60065b	716	__IO uint32_t PWMEADCTS; /!< [0x0090] Timer PWM ADC Trigger Source Select Register /
kadonotakashi	0:8fdf9a60065b	717	__IO uint32_t PWMSCTL; /!< [0x0094] Timer PWM Synchronous Control Register /
kadonotakashi	0:8fdf9a60065b	718	__O uint32_t PWMSTRG; /!< [0x0098] Timer PWM Synchronous Trigger Register /
kadonotakashi	0:8fdf9a60065b	719	__IO uint32_t PWMSTATUS; /!< [0x009c] Timer PWM Status Register /
kadonotakashi	0:8fdf9a60065b	720	__I uint32_t PWMPBUF; /!< [0x00a0] Timer PWM Period Buffer Register /
kadonotakashi	0:8fdf9a60065b	721	__I uint32_t PWMCMPBUF; /!< [0x00a4] Timer PWM Comparator Buffer Register /
kadonotakashi	0:8fdf9a60065b	722
kadonotakashi	0:8fdf9a60065b	723	} TIMER_T;
kadonotakashi	0:8fdf9a60065b	724
kadonotakashi	0:8fdf9a60065b	725	/**
kadonotakashi	0:8fdf9a60065b	726	@addtogroup TIMER_CONST TIMER Bit Field Definition
kadonotakashi	0:8fdf9a60065b	727	Constant Definitions for TIMER Controller
kadonotakashi	0:8fdf9a60065b	728	@{ */
kadonotakashi	0:8fdf9a60065b	729
kadonotakashi	0:8fdf9a60065b	730	#define TIMER_CTL_PSC_Pos (0) /!< TIMER_T::CTL: PSC Position /
kadonotakashi	0:8fdf9a60065b	731	#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /!< TIMER_T::CTL: PSC Mask /
kadonotakashi	0:8fdf9a60065b	732
kadonotakashi	0:8fdf9a60065b	733	#define TIMER_CTL_INTRGEN_Pos (19) /!< TIMER_T::CTL: INTRGEN Position /
kadonotakashi	0:8fdf9a60065b	734	#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /!< TIMER_T::CTL: INTRGEN Mask /
kadonotakashi	0:8fdf9a60065b	735
kadonotakashi	0:8fdf9a60065b	736	#define TIMER_CTL_PERIOSEL_Pos (20) /!< TIMER_T::CTL: PERIOSEL Position /
kadonotakashi	0:8fdf9a60065b	737	#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /!< TIMER_T::CTL: PERIOSEL Mask /
kadonotakashi	0:8fdf9a60065b	738
kadonotakashi	0:8fdf9a60065b	739	#define TIMER_CTL_TGLPINSEL_Pos (21) /!< TIMER_T::CTL: TGLPINSEL Position /
kadonotakashi	0:8fdf9a60065b	740	#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /!< TIMER_T::CTL: TGLPINSEL Mask /
kadonotakashi	0:8fdf9a60065b	741
kadonotakashi	0:8fdf9a60065b	742	#define TIMER_CTL_CAPSRC_Pos (22) /!< TIMER_T::CTL: CAPSRC Position /
kadonotakashi	0:8fdf9a60065b	743	#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /!< TIMER_T::CTL: CAPSRC Mask /
kadonotakashi	0:8fdf9a60065b	744
kadonotakashi	0:8fdf9a60065b	745	#define TIMER_CTL_WKEN_Pos (23) /!< TIMER_T::CTL: WKEN Position /
kadonotakashi	0:8fdf9a60065b	746	#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /!< TIMER_T::CTL: WKEN Mask /
kadonotakashi	0:8fdf9a60065b	747
kadonotakashi	0:8fdf9a60065b	748	#define TIMER_CTL_EXTCNTEN_Pos (24) /!< TIMER_T::CTL: EXTCNTEN Position /
kadonotakashi	0:8fdf9a60065b	749	#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /!< TIMER_T::CTL: EXTCNTEN Mask /
kadonotakashi	0:8fdf9a60065b	750
kadonotakashi	0:8fdf9a60065b	751	#define TIMER_CTL_ACTSTS_Pos (25) /!< TIMER_T::CTL: ACTSTS Position /
kadonotakashi	0:8fdf9a60065b	752	#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /!< TIMER_T::CTL: ACTSTS Mask /
kadonotakashi	0:8fdf9a60065b	753
kadonotakashi	0:8fdf9a60065b	754	#define TIMER_CTL_OPMODE_Pos (27) /!< TIMER_T::CTL: OPMODE Position /
kadonotakashi	0:8fdf9a60065b	755	#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /!< TIMER_T::CTL: OPMODE Mask /
kadonotakashi	0:8fdf9a60065b	756
kadonotakashi	0:8fdf9a60065b	757	#define TIMER_CTL_INTEN_Pos (29) /!< TIMER_T::CTL: INTEN Position /
kadonotakashi	0:8fdf9a60065b	758	#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /!< TIMER_T::CTL: INTEN Mask /
kadonotakashi	0:8fdf9a60065b	759
kadonotakashi	0:8fdf9a60065b	760	#define TIMER_CTL_CNTEN_Pos (30) /!< TIMER_T::CTL: CNTEN Position /
kadonotakashi	0:8fdf9a60065b	761	#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /!< TIMER_T::CTL: CNTEN Mask /
kadonotakashi	0:8fdf9a60065b	762
kadonotakashi	0:8fdf9a60065b	763	#define TIMER_CTL_ICEDEBUG_Pos (31) /!< TIMER_T::CTL: ICEDEBUG Position /
kadonotakashi	0:8fdf9a60065b	764	#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /!< TIMER_T::CTL: ICEDEBUG Mask /
kadonotakashi	0:8fdf9a60065b	765
kadonotakashi	0:8fdf9a60065b	766	#define TIMER_CMP_CMPDAT_Pos (0) /!< TIMER_T::CMP: CMPDAT Position /
kadonotakashi	0:8fdf9a60065b	767	#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /!< TIMER_T::CMP: CMPDAT Mask /
kadonotakashi	0:8fdf9a60065b	768
kadonotakashi	0:8fdf9a60065b	769	#define TIMER_INTSTS_TIF_Pos (0) /!< TIMER_T::INTSTS: TIF Position /
kadonotakashi	0:8fdf9a60065b	770	#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /!< TIMER_T::INTSTS: TIF Mask /
kadonotakashi	0:8fdf9a60065b	771
kadonotakashi	0:8fdf9a60065b	772	#define TIMER_INTSTS_TWKF_Pos (1) /!< TIMER_T::INTSTS: TWKF Position /
kadonotakashi	0:8fdf9a60065b	773	#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /!< TIMER_T::INTSTS: TWKF Mask /
kadonotakashi	0:8fdf9a60065b	774
kadonotakashi	0:8fdf9a60065b	775	#define TIMER_CNT_CNT_Pos (0) /!< TIMER_T::CNT: CNT Position /
kadonotakashi	0:8fdf9a60065b	776	#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /!< TIMER_T::CNT: CNT Mask /
kadonotakashi	0:8fdf9a60065b	777
kadonotakashi	0:8fdf9a60065b	778	#define TIMER_CNT_RSTACT_Pos (31) /!< TIMER_T::CNT: RSTACT Position /
kadonotakashi	0:8fdf9a60065b	779	#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /!< TIMER_T::CNT: RSTACT Mask /
kadonotakashi	0:8fdf9a60065b	780
kadonotakashi	0:8fdf9a60065b	781	#define TIMER_CAP_CAPDAT_Pos (0) /!< TIMER_T::CAP: CAPDAT Position /
kadonotakashi	0:8fdf9a60065b	782	#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /!< TIMER_T::CAP: CAPDAT Mask /
kadonotakashi	0:8fdf9a60065b	783
kadonotakashi	0:8fdf9a60065b	784	#define TIMER_EXTCTL_CNTPHASE_Pos (0) /!< TIMER_T::EXTCTL: CNTPHASE Position /
kadonotakashi	0:8fdf9a60065b	785	#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /!< TIMER_T::EXTCTL: CNTPHASE Mask /
kadonotakashi	0:8fdf9a60065b	786
kadonotakashi	0:8fdf9a60065b	787	#define TIMER_EXTCTL_CAPEN_Pos (3) /!< TIMER_T::EXTCTL: CAPEN Position /
kadonotakashi	0:8fdf9a60065b	788	#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /!< TIMER_T::EXTCTL: CAPEN Mask /
kadonotakashi	0:8fdf9a60065b	789
kadonotakashi	0:8fdf9a60065b	790	#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /!< TIMER_T::EXTCTL: CAPFUNCS Position /
kadonotakashi	0:8fdf9a60065b	791	#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /!< TIMER_T::EXTCTL: CAPFUNCS Mask /
kadonotakashi	0:8fdf9a60065b	792
kadonotakashi	0:8fdf9a60065b	793	#define TIMER_EXTCTL_CAPIEN_Pos (5) /!< TIMER_T::EXTCTL: CAPIEN Position /
kadonotakashi	0:8fdf9a60065b	794	#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /!< TIMER_T::EXTCTL: CAPIEN Mask /
kadonotakashi	0:8fdf9a60065b	795
kadonotakashi	0:8fdf9a60065b	796	#define TIMER_EXTCTL_CAPDBEN_Pos (6) /!< TIMER_T::EXTCTL: CAPDBEN Position /
kadonotakashi	0:8fdf9a60065b	797	#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /!< TIMER_T::EXTCTL: CAPDBEN Mask /
kadonotakashi	0:8fdf9a60065b	798
kadonotakashi	0:8fdf9a60065b	799	#define TIMER_EXTCTL_CNTDBEN_Pos (7) /!< TIMER_T::EXTCTL: CNTDBEN Position /
kadonotakashi	0:8fdf9a60065b	800	#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /!< TIMER_T::EXTCTL: CNTDBEN Mask /
kadonotakashi	0:8fdf9a60065b	801
kadonotakashi	0:8fdf9a60065b	802	#define TIMER_EXTCTL_ACMPSSEL_Pos (8) /!< TIMER_T::EXTCTL: ACMPSSEL Position /
kadonotakashi	0:8fdf9a60065b	803	#define TIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos) /!< TIMER_T::EXTCTL: ACMPSSEL Mask /
kadonotakashi	0:8fdf9a60065b	804
kadonotakashi	0:8fdf9a60065b	805	#define TIMER_EXTCTL_CAPEDGE_Pos (12) /!< TIMER_T::EXTCTL: CAPEDGE Position /
kadonotakashi	0:8fdf9a60065b	806	#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /!< TIMER_T::EXTCTL: CAPEDGE Mask /
kadonotakashi	0:8fdf9a60065b	807
kadonotakashi	0:8fdf9a60065b	808	#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /!< TIMER_T::EXTCTL: ECNTSSEL Position /
kadonotakashi	0:8fdf9a60065b	809	#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /!< TIMER_T::EXTCTL: ECNTSSEL Mask /
kadonotakashi	0:8fdf9a60065b	810
kadonotakashi	0:8fdf9a60065b	811	#define TIMER_EINTSTS_CAPIF_Pos (0) /!< TIMER_T::EINTSTS: CAPIF Position /
kadonotakashi	0:8fdf9a60065b	812	#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /!< TIMER_T::EINTSTS: CAPIF Mask /
kadonotakashi	0:8fdf9a60065b	813
kadonotakashi	0:8fdf9a60065b	814	#define TIMER_TRGCTL_TRGSSEL_Pos (0) /!< TIMER_T::TRGCTL: TRGSSEL Position /
kadonotakashi	0:8fdf9a60065b	815	#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /!< TIMER_T::TRGCTL: TRGSSEL Mask /
kadonotakashi	0:8fdf9a60065b	816
kadonotakashi	0:8fdf9a60065b	817	#define TIMER_TRGCTL_TRGEPWM_Pos (1) /!< TIMER_T::TRGCTL: TRGEPWM Position /
kadonotakashi	0:8fdf9a60065b	818	#define TIMER_TRGCTL_TRGEPWM_Msk (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos) /!< TIMER_T::TRGCTL: TRGEPWM Mask /
kadonotakashi	0:8fdf9a60065b	819
kadonotakashi	0:8fdf9a60065b	820	#define TIMER_TRGCTL_TRGEADC_Pos (2) /!< TIMER_T::TRGCTL: TRGEADC Position /
kadonotakashi	0:8fdf9a60065b	821	#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /!< TIMER_T::TRGCTL: TRGEADC Mask /
kadonotakashi	0:8fdf9a60065b	822
kadonotakashi	0:8fdf9a60065b	823	#define TIMER_TRGCTL_TRGDAC_Pos (3) /!< TIMER_T::TRGCTL: TRGDAC Position /
kadonotakashi	0:8fdf9a60065b	824	#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /!< TIMER_T::TRGCTL: TRGDAC Mask /
kadonotakashi	0:8fdf9a60065b	825
kadonotakashi	0:8fdf9a60065b	826	#define TIMER_TRGCTL_TRGPDMA_Pos (4) /!< TIMER_T::TRGCTL: TRGPDMA Position /
kadonotakashi	0:8fdf9a60065b	827	#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /!< TIMER_T::TRGCTL: TRGPDMA Mask /
kadonotakashi	0:8fdf9a60065b	828
kadonotakashi	0:8fdf9a60065b	829	#define TIMER_ALTCTL_FUNCSEL_Pos (0) /!< TIMER_T::ALTCTL: FUNCSEL Position /
kadonotakashi	0:8fdf9a60065b	830	#define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /!< TIMER_T::ALTCTL: FUNCSEL Mask /
kadonotakashi	0:8fdf9a60065b	831
kadonotakashi	0:8fdf9a60065b	832	#define TIMER_PWMCTL_CNTEN_Pos (0) /!< TIMER_T::PWMCTL: CNTEN Position /
kadonotakashi	0:8fdf9a60065b	833	#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /!< TIMER_T::PWMCTL: CNTEN Mask /
kadonotakashi	0:8fdf9a60065b	834
kadonotakashi	0:8fdf9a60065b	835	#define TIMER_PWMCTL_CNTTYPE_Pos (1) /!< TIMER_T::PWMCTL: CNTTYPE Position /
kadonotakashi	0:8fdf9a60065b	836	#define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /!< TIMER_T::PWMCTL: CNTTYPE Mask /
kadonotakashi	0:8fdf9a60065b	837
kadonotakashi	0:8fdf9a60065b	838	#define TIMER_PWMCTL_CNTMODE_Pos (3) /!< TIMER_T::PWMCTL: CNTMODE Position /
kadonotakashi	0:8fdf9a60065b	839	#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /!< TIMER_T::PWMCTL: CNTMODE Mask /
kadonotakashi	0:8fdf9a60065b	840
kadonotakashi	0:8fdf9a60065b	841	#define TIMER_PWMCTL_CTRLD_Pos (8) /!< TIMER_T::PWMCTL: CTRLD Position /
kadonotakashi	0:8fdf9a60065b	842	#define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /!< TIMER_T::PWMCTL: CTRLD Mask /
kadonotakashi	0:8fdf9a60065b	843
kadonotakashi	0:8fdf9a60065b	844	#define TIMER_PWMCTL_IMMLDEN_Pos (9) /!< TIMER_T::PWMCTL: IMMLDEN Position /
kadonotakashi	0:8fdf9a60065b	845	#define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /!< TIMER_T::PWMCTL: IMMLDEN Mask /
kadonotakashi	0:8fdf9a60065b	846
kadonotakashi	0:8fdf9a60065b	847	#define TIMER_PWMCTL_OUTMODE_Pos (16) /!< TIMER_T::PWMCTL: OUTMODE Position /
kadonotakashi	0:8fdf9a60065b	848	#define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /!< TIMER_T::PWMCTL: OUTMODE Mask /
kadonotakashi	0:8fdf9a60065b	849
kadonotakashi	0:8fdf9a60065b	850	#define TIMER_PWMCTL_DBGHALT_Pos (30) /!< TIMER_T::PWMCTL: DBGHALT Position /
kadonotakashi	0:8fdf9a60065b	851	#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /!< TIMER_T::PWMCTL: DBGHALT Mask /
kadonotakashi	0:8fdf9a60065b	852
kadonotakashi	0:8fdf9a60065b	853	#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /!< TIMER_T::PWMCTL: DBGTRIOFF Position /
kadonotakashi	0:8fdf9a60065b	854	#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /!< TIMER_T::PWMCTL: DBGTRIOFF Mask /
kadonotakashi	0:8fdf9a60065b	855
kadonotakashi	0:8fdf9a60065b	856	#define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /!< TIMER_T::PWMCLKSRC: CLKSRC Position /
kadonotakashi	0:8fdf9a60065b	857	#define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /!< TIMER_T::PWMCLKSRC: CLKSRC Mask /
kadonotakashi	0:8fdf9a60065b	858
kadonotakashi	0:8fdf9a60065b	859	#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /!< TIMER_T::PWMCLKPSC: CLKPSC Position /
kadonotakashi	0:8fdf9a60065b	860	#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /!< TIMER_T::PWMCLKPSC: CLKPSC Mask /
kadonotakashi	0:8fdf9a60065b	861
kadonotakashi	0:8fdf9a60065b	862	#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /!< TIMER_T::PWMCNTCLR: CNTCLR Position /
kadonotakashi	0:8fdf9a60065b	863	#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /!< TIMER_T::PWMCNTCLR: CNTCLR Mask /
kadonotakashi	0:8fdf9a60065b	864
kadonotakashi	0:8fdf9a60065b	865	#define TIMER_PWMPERIOD_PERIOD_Pos (0) /!< TIMER_T::PWMPERIOD: PERIOD Position /
kadonotakashi	0:8fdf9a60065b	866	#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /!< TIMER_T::PWMPERIOD: PERIOD Mask /
kadonotakashi	0:8fdf9a60065b	867
kadonotakashi	0:8fdf9a60065b	868	#define TIMER_PWMCMPDAT_CMP_Pos (0) /!< TIMER_T::PWMCMPDAT: CMP Position /
kadonotakashi	0:8fdf9a60065b	869	#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /!< TIMER_T::PWMCMPDAT: CMP Mask /
kadonotakashi	0:8fdf9a60065b	870
kadonotakashi	0:8fdf9a60065b	871	#define TIMER_PWMDTCTL_DTCNT_Pos (0) /!< TIMER_T::PWMDTCTL: DTCNT Position /
kadonotakashi	0:8fdf9a60065b	872	#define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /!< TIMER_T::PWMDTCTL: DTCNT Mask /
kadonotakashi	0:8fdf9a60065b	873
kadonotakashi	0:8fdf9a60065b	874	#define TIMER_PWMDTCTL_DTEN_Pos (16) /!< TIMER_T::PWMDTCTL: DTEN Position /
kadonotakashi	0:8fdf9a60065b	875	#define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /!< TIMER_T::PWMDTCTL: DTEN Mask /
kadonotakashi	0:8fdf9a60065b	876
kadonotakashi	0:8fdf9a60065b	877	#define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /!< TIMER_T::PWMDTCTL: DTCKSEL Position /
kadonotakashi	0:8fdf9a60065b	878	#define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /!< TIMER_T::PWMDTCTL: DTCKSEL Mask /
kadonotakashi	0:8fdf9a60065b	879
kadonotakashi	0:8fdf9a60065b	880	#define TIMER_PWMCNT_CNT_Pos (0) /!< TIMER_T::PWMCNT: CNT Position /
kadonotakashi	0:8fdf9a60065b	881	#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /!< TIMER_T::PWMCNT: CNT Mask /
kadonotakashi	0:8fdf9a60065b	882
kadonotakashi	0:8fdf9a60065b	883	#define TIMER_PWMCNT_DIRF_Pos (16) /!< TIMER_T::PWMCNT: DIRF Position /
kadonotakashi	0:8fdf9a60065b	884	#define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /!< TIMER_T::PWMCNT: DIRF Mask /
kadonotakashi	0:8fdf9a60065b	885
kadonotakashi	0:8fdf9a60065b	886	#define TIMER_PWMMSKEN_MSKEN0_Pos (0) /!< TIMER_T::PWMMSKEN: MSKEN0 Position /
kadonotakashi	0:8fdf9a60065b	887	#define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /!< TIMER_T::PWMMSKEN: MSKEN0 Mask /
kadonotakashi	0:8fdf9a60065b	888
kadonotakashi	0:8fdf9a60065b	889	#define TIMER_PWMMSKEN_MSKEN1_Pos (1) /!< TIMER_T::PWMMSKEN: MSKEN1 Position /
kadonotakashi	0:8fdf9a60065b	890	#define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /!< TIMER_T::PWMMSKEN: MSKEN1 Mask /
kadonotakashi	0:8fdf9a60065b	891
kadonotakashi	0:8fdf9a60065b	892	#define TIMER_PWMMSK_MSKDAT0_Pos (0) /!< TIMER_T::PWMMSK: MSKDAT0 Position /
kadonotakashi	0:8fdf9a60065b	893	#define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /!< TIMER_T::PWMMSK: MSKDAT0 Mask /
kadonotakashi	0:8fdf9a60065b	894
kadonotakashi	0:8fdf9a60065b	895	#define TIMER_PWMMSK_MSKDAT1_Pos (1) /!< TIMER_T::PWMMSK: MSKDAT1 Position /
kadonotakashi	0:8fdf9a60065b	896	#define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /!< TIMER_T::PWMMSK: MSKDAT1 Mask /
kadonotakashi	0:8fdf9a60065b	897
kadonotakashi	0:8fdf9a60065b	898	#define TIMER_PWMBNF_BRKNFEN_Pos (0) /!< TIMER_T::PWMBNF: BRKNFEN Position /
kadonotakashi	0:8fdf9a60065b	899	#define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /!< TIMER_T::PWMBNF: BRKNFEN Mask /
kadonotakashi	0:8fdf9a60065b	900
kadonotakashi	0:8fdf9a60065b	901	#define TIMER_PWMBNF_BRKNFSEL_Pos (1) /!< TIMER_T::PWMBNF: BRKNFSEL Position /
kadonotakashi	0:8fdf9a60065b	902	#define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /!< TIMER_T::PWMBNF: BRKNFSEL Mask /
kadonotakashi	0:8fdf9a60065b	903
kadonotakashi	0:8fdf9a60065b	904	#define TIMER_PWMBNF_BRKFCNT_Pos (4) /!< TIMER_T::PWMBNF: BRKFCNT Position /
kadonotakashi	0:8fdf9a60065b	905	#define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /!< TIMER_T::PWMBNF: BRKFCNT Mask /
kadonotakashi	0:8fdf9a60065b	906
kadonotakashi	0:8fdf9a60065b	907	#define TIMER_PWMBNF_BRKPINV_Pos (7) /!< TIMER_T::PWMBNF: BRKPINV Position /
kadonotakashi	0:8fdf9a60065b	908	#define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /!< TIMER_T::PWMBNF: BRKPINV Mask /
kadonotakashi	0:8fdf9a60065b	909
kadonotakashi	0:8fdf9a60065b	910	#define TIMER_PWMBNF_BKPINSRC_Pos (16) /!< TIMER_T::PWMBNF: BKPINSRC Position /
kadonotakashi	0:8fdf9a60065b	911	#define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /!< TIMER_T::PWMBNF: BKPINSRC Mask /
kadonotakashi	0:8fdf9a60065b	912
kadonotakashi	0:8fdf9a60065b	913	#define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /!< TIMER_T::PWMFAILBRK: CSSBRKEN Position /
kadonotakashi	0:8fdf9a60065b	914	#define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask /
kadonotakashi	0:8fdf9a60065b	915
kadonotakashi	0:8fdf9a60065b	916	#define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /!< TIMER_T::PWMFAILBRK: BODBRKEN Position /
kadonotakashi	0:8fdf9a60065b	917	#define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /!< TIMER_T::PWMFAILBRK: BODBRKEN Mask /
kadonotakashi	0:8fdf9a60065b	918
kadonotakashi	0:8fdf9a60065b	919	#define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /!< TIMER_T::PWMFAILBRK: RAMBRKEN Position /
kadonotakashi	0:8fdf9a60065b	920	#define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask /
kadonotakashi	0:8fdf9a60065b	921
kadonotakashi	0:8fdf9a60065b	922	#define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /!< TIMER_T::PWMFAILBRK: CORBRKEN Position /
kadonotakashi	0:8fdf9a60065b	923	#define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /!< TIMER_T::PWMFAILBRK: CORBRKEN Mask /
kadonotakashi	0:8fdf9a60065b	924
kadonotakashi	0:8fdf9a60065b	925	#define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /!< TIMER_T::PWMBRKCTL: CPO0EBEN Position /
kadonotakashi	0:8fdf9a60065b	926	#define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask /
kadonotakashi	0:8fdf9a60065b	927
kadonotakashi	0:8fdf9a60065b	928	#define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /!< TIMER_T::PWMBRKCTL: CPO1EBEN Position /
kadonotakashi	0:8fdf9a60065b	929	#define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask /
kadonotakashi	0:8fdf9a60065b	930
kadonotakashi	0:8fdf9a60065b	931	#define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /!< TIMER_T::PWMBRKCTL: BRKPEEN Position /
kadonotakashi	0:8fdf9a60065b	932	#define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /!< TIMER_T::PWMBRKCTL: BRKPEEN Mask /
kadonotakashi	0:8fdf9a60065b	933
kadonotakashi	0:8fdf9a60065b	934	#define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /!< TIMER_T::PWMBRKCTL: SYSEBEN Position /
kadonotakashi	0:8fdf9a60065b	935	#define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /!< TIMER_T::PWMBRKCTL: SYSEBEN Mask /
kadonotakashi	0:8fdf9a60065b	936
kadonotakashi	0:8fdf9a60065b	937	#define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /!< TIMER_T::PWMBRKCTL: CPO0LBEN Position /
kadonotakashi	0:8fdf9a60065b	938	#define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask /
kadonotakashi	0:8fdf9a60065b	939
kadonotakashi	0:8fdf9a60065b	940	#define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /!< TIMER_T::PWMBRKCTL: CPO1LBEN Position /
kadonotakashi	0:8fdf9a60065b	941	#define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask /
kadonotakashi	0:8fdf9a60065b	942
kadonotakashi	0:8fdf9a60065b	943	#define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /!< TIMER_T::PWMBRKCTL: BRKPLEN Position /
kadonotakashi	0:8fdf9a60065b	944	#define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /!< TIMER_T::PWMBRKCTL: BRKPLEN Mask /
kadonotakashi	0:8fdf9a60065b	945
kadonotakashi	0:8fdf9a60065b	946	#define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /!< TIMER_T::PWMBRKCTL: SYSLBEN Position /
kadonotakashi	0:8fdf9a60065b	947	#define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /!< TIMER_T::PWMBRKCTL: SYSLBEN Mask /
kadonotakashi	0:8fdf9a60065b	948
kadonotakashi	0:8fdf9a60065b	949	#define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /!< TIMER_T::PWMBRKCTL: BRKAEVEN Position /
kadonotakashi	0:8fdf9a60065b	950	#define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask /
kadonotakashi	0:8fdf9a60065b	951
kadonotakashi	0:8fdf9a60065b	952	#define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /!< TIMER_T::PWMBRKCTL: BRKAODD Position /
kadonotakashi	0:8fdf9a60065b	953	#define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /!< TIMER_T::PWMBRKCTL: BRKAODD Mask /
kadonotakashi	0:8fdf9a60065b	954
kadonotakashi	0:8fdf9a60065b	955	#define TIMER_PWMPOLCTL_PINV0_Pos (0) /!< TIMER_T::PWMPOLCTL: PINV0 Position /
kadonotakashi	0:8fdf9a60065b	956	#define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /!< TIMER_T::PWMPOLCTL: PINV0 Mask /
kadonotakashi	0:8fdf9a60065b	957
kadonotakashi	0:8fdf9a60065b	958	#define TIMER_PWMPOLCTL_PINV1_Pos (1) /!< TIMER_T::PWMPOLCTL: PINV1 Position /
kadonotakashi	0:8fdf9a60065b	959	#define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /!< TIMER_T::PWMPOLCTL: PINV1 Mask /
kadonotakashi	0:8fdf9a60065b	960
kadonotakashi	0:8fdf9a60065b	961	#define TIMER_PWMPOEN_POEN0_Pos (0) /!< TIMER_T::PWMPOEN: POEN0 Position /
kadonotakashi	0:8fdf9a60065b	962	#define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /!< TIMER_T::PWMPOEN: POEN0 Mask /
kadonotakashi	0:8fdf9a60065b	963
kadonotakashi	0:8fdf9a60065b	964	#define TIMER_PWMPOEN_POEN1_Pos (1) /!< TIMER_T::PWMPOEN: POEN1 Position /
kadonotakashi	0:8fdf9a60065b	965	#define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /!< TIMER_T::PWMPOEN: POEN1 Mask /
kadonotakashi	0:8fdf9a60065b	966
kadonotakashi	0:8fdf9a60065b	967	#define TIMER_PWMSWBRK_BRKETRG_Pos (0) /!< TIMER_T::PWMSWBRK: BRKETRG Position /
kadonotakashi	0:8fdf9a60065b	968	#define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /!< TIMER_T::PWMSWBRK: BRKETRG Mask /
kadonotakashi	0:8fdf9a60065b	969
kadonotakashi	0:8fdf9a60065b	970	#define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /!< TIMER_T::PWMSWBRK: BRKLTRG Position /
kadonotakashi	0:8fdf9a60065b	971	#define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /!< TIMER_T::PWMSWBRK: BRKLTRG Mask /
kadonotakashi	0:8fdf9a60065b	972
kadonotakashi	0:8fdf9a60065b	973	#define TIMER_PWMINTEN0_ZIEN_Pos (0) /!< TIMER_T::PWMINTEN0: ZIEN Position /
kadonotakashi	0:8fdf9a60065b	974	#define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /!< TIMER_T::PWMINTEN0: ZIEN Mask /
kadonotakashi	0:8fdf9a60065b	975
kadonotakashi	0:8fdf9a60065b	976	#define TIMER_PWMINTEN0_PIEN_Pos (1) /!< TIMER_T::PWMINTEN0: PIEN Position /
kadonotakashi	0:8fdf9a60065b	977	#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /!< TIMER_T::PWMINTEN0: PIEN Mask /
kadonotakashi	0:8fdf9a60065b	978
kadonotakashi	0:8fdf9a60065b	979	#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /!< TIMER_T::PWMINTEN0: CMPUIEN Position /
kadonotakashi	0:8fdf9a60065b	980	#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /!< TIMER_T::PWMINTEN0: CMPUIEN Mask /
kadonotakashi	0:8fdf9a60065b	981
kadonotakashi	0:8fdf9a60065b	982	#define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /!< TIMER_T::PWMINTEN0: CMPDIEN Position /
kadonotakashi	0:8fdf9a60065b	983	#define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /!< TIMER_T::PWMINTEN0: CMPDIEN Mask /
kadonotakashi	0:8fdf9a60065b	984
kadonotakashi	0:8fdf9a60065b	985	#define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /!< TIMER_T::PWMINTEN1: BRKEIEN Position /
kadonotakashi	0:8fdf9a60065b	986	#define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /!< TIMER_T::PWMINTEN1: BRKEIEN Mask /
kadonotakashi	0:8fdf9a60065b	987
kadonotakashi	0:8fdf9a60065b	988	#define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /!< TIMER_T::PWMINTEN1: BRKLIEN Position /
kadonotakashi	0:8fdf9a60065b	989	#define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /!< TIMER_T::PWMINTEN1: BRKLIEN Mask /
kadonotakashi	0:8fdf9a60065b	990
kadonotakashi	0:8fdf9a60065b	991	#define TIMER_PWMINTSTS0_ZIF_Pos (0) /!< TIMER_T::PWMINTSTS0: ZIF Position /
kadonotakashi	0:8fdf9a60065b	992	#define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /!< TIMER_T::PWMINTSTS0: ZIF Mask /
kadonotakashi	0:8fdf9a60065b	993
kadonotakashi	0:8fdf9a60065b	994	#define TIMER_PWMINTSTS0_PIF_Pos (1) /!< TIMER_T::PWMINTSTS0: PIF Position /
kadonotakashi	0:8fdf9a60065b	995	#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /!< TIMER_T::PWMINTSTS0: PIF Mask /
kadonotakashi	0:8fdf9a60065b	996
kadonotakashi	0:8fdf9a60065b	997	#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /!< TIMER_T::PWMINTSTS0: CMPUIF Position /
kadonotakashi	0:8fdf9a60065b	998	#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /!< TIMER_T::PWMINTSTS0: CMPUIF Mask /
kadonotakashi	0:8fdf9a60065b	999
kadonotakashi	0:8fdf9a60065b	1000	#define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /!< TIMER_T::PWMINTSTS0: CMPDIF Position /
kadonotakashi	0:8fdf9a60065b	1001	#define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /!< TIMER_T::PWMINTSTS0: CMPDIF Mask /
kadonotakashi	0:8fdf9a60065b	1002
kadonotakashi	0:8fdf9a60065b	1003	#define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /!< TIMER_T::PWMINTSTS1: BRKEIF0 Position /
kadonotakashi	0:8fdf9a60065b	1004	#define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask /
kadonotakashi	0:8fdf9a60065b	1005
kadonotakashi	0:8fdf9a60065b	1006	#define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /!< TIMER_T::PWMINTSTS1: BRKEIF1 Position /
kadonotakashi	0:8fdf9a60065b	1007	#define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask /
kadonotakashi	0:8fdf9a60065b	1008
kadonotakashi	0:8fdf9a60065b	1009	#define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /!< TIMER_T::PWMINTSTS1: BRKLIF0 Position /
kadonotakashi	0:8fdf9a60065b	1010	#define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask /
kadonotakashi	0:8fdf9a60065b	1011
kadonotakashi	0:8fdf9a60065b	1012	#define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /!< TIMER_T::PWMINTSTS1: BRKLIF1 Position /
kadonotakashi	0:8fdf9a60065b	1013	#define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask /
kadonotakashi	0:8fdf9a60065b	1014
kadonotakashi	0:8fdf9a60065b	1015	#define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /!< TIMER_T::PWMINTSTS1: BRKESTS0 Position /
kadonotakashi	0:8fdf9a60065b	1016	#define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask /
kadonotakashi	0:8fdf9a60065b	1017
kadonotakashi	0:8fdf9a60065b	1018	#define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /!< TIMER_T::PWMINTSTS1: BRKESTS1 Position /
kadonotakashi	0:8fdf9a60065b	1019	#define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask /
kadonotakashi	0:8fdf9a60065b	1020
kadonotakashi	0:8fdf9a60065b	1021	#define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position /
kadonotakashi	0:8fdf9a60065b	1022	#define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask /
kadonotakashi	0:8fdf9a60065b	1023
kadonotakashi	0:8fdf9a60065b	1024	#define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position /
kadonotakashi	0:8fdf9a60065b	1025	#define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask /
kadonotakashi	0:8fdf9a60065b	1026
kadonotakashi	0:8fdf9a60065b	1027	#define TIMER_PWMEADCTS_TRGSEL_Pos (0) /!< TIMER_T::PWMEADCTS: TRGSEL Position /
kadonotakashi	0:8fdf9a60065b	1028	#define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) /!< TIMER_T::PWMEADCTS: TRGSEL Mask /
kadonotakashi	0:8fdf9a60065b	1029
kadonotakashi	0:8fdf9a60065b	1030	#define TIMER_PWMEADCTS_TRGEN_Pos (7) /!< TIMER_T::PWMEADCTS: TRGEN Position /
kadonotakashi	0:8fdf9a60065b	1031	#define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) /!< TIMER_T::PWMEADCTS: TRGEN Mask /
kadonotakashi	0:8fdf9a60065b	1032
kadonotakashi	0:8fdf9a60065b	1033	#define TIMER_PWMSCTL_SYNCMODE_Pos (0) /!< TIMER_T::PWMSCTL: SYNCMODE Position /
kadonotakashi	0:8fdf9a60065b	1034	#define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /!< TIMER_T::PWMSCTL: SYNCMODE Mask /
kadonotakashi	0:8fdf9a60065b	1035
kadonotakashi	0:8fdf9a60065b	1036	#define TIMER_PWMSCTL_SYNCSRC_Pos (8) /!< TIMER_T::PWMSCTL: SYNCSRC Position /
kadonotakashi	0:8fdf9a60065b	1037	#define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /!< TIMER_T::PWMSCTL: SYNCSRC Mask /
kadonotakashi	0:8fdf9a60065b	1038
kadonotakashi	0:8fdf9a60065b	1039	#define TIMER_PWMSTRG_STRGEN_Pos (0) /!< TIMER_T::PWMSTRG: STRGEN Position /
kadonotakashi	0:8fdf9a60065b	1040	#define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /!< TIMER_T::PWMSTRG: STRGEN Mask /
kadonotakashi	0:8fdf9a60065b	1041
kadonotakashi	0:8fdf9a60065b	1042	#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /!< TIMER_T::PWMSTATUS: CNTMAXF Position /
kadonotakashi	0:8fdf9a60065b	1043	#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /!< TIMER_T::PWMSTATUS: CNTMAXF Mask /
kadonotakashi	0:8fdf9a60065b	1044
kadonotakashi	0:8fdf9a60065b	1045	#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /!< TIMER_T::PWMSTATUS: EADCTRGF Position /
kadonotakashi	0:8fdf9a60065b	1046	#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /!< TIMER_T::PWMSTATUS: EADCTRGF Mask /
kadonotakashi	0:8fdf9a60065b	1047
kadonotakashi	0:8fdf9a60065b	1048	#define TIMER_PWMPBUF_PBUF_Pos (0) /!< TIMER_T::PWMPBUF: PBUF Position /
kadonotakashi	0:8fdf9a60065b	1049	#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /!< TIMER_T::PWMPBUF: PBUF Mask /
kadonotakashi	0:8fdf9a60065b	1050
kadonotakashi	0:8fdf9a60065b	1051	#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /!< TIMER_T::PWMCMPBUF: CMPBUF Position /
kadonotakashi	0:8fdf9a60065b	1052	#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /!< TIMER_T::PWMCMPBUF: CMPBUF Mask /
kadonotakashi	0:8fdf9a60065b	1053
kadonotakashi	0:8fdf9a60065b	1054	/*@}/ /* TIMER_CONST */
kadonotakashi	0:8fdf9a60065b	1055	/*@}/ /* end of TIMER register group */
kadonotakashi	0:8fdf9a60065b	1056
kadonotakashi	0:8fdf9a60065b	1057
kadonotakashi	0:8fdf9a60065b	1058
kadonotakashi	0:8fdf9a60065b	1059	#endif /* __TIMER_REG_H__ */

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Type:	Program
Mbed OS support:	Mbed OS
Created:	11 Oct 2018
Imports:	15
Forks:	0
Commits:	4
Dependents:	0
Dependencies:	1
Followers:	1

mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/timer_reg.h@0:8fdf9a60065b, 2018-10-10 (annotated)

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