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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/i2s_reg.h@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
| kadonotakashi | 0:8fdf9a60065b | 2 | * @file i2s_reg.h |
| kadonotakashi | 0:8fdf9a60065b | 3 | * @version V1.00 |
| kadonotakashi | 0:8fdf9a60065b | 4 | * @brief I2S register definition header file |
| kadonotakashi | 0:8fdf9a60065b | 5 | * |
| kadonotakashi | 0:8fdf9a60065b | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
| kadonotakashi | 0:8fdf9a60065b | 7 | *****************************************************************************/ |
| kadonotakashi | 0:8fdf9a60065b | 8 | #ifndef __I2S_REG_H__ |
| kadonotakashi | 0:8fdf9a60065b | 9 | #define __I2S_REG_H__ |
| kadonotakashi | 0:8fdf9a60065b | 10 | |
| kadonotakashi | 0:8fdf9a60065b | 11 | |
| kadonotakashi | 0:8fdf9a60065b | 12 | /*---------------------- I2S Interface Controller -------------------------*/ |
| kadonotakashi | 0:8fdf9a60065b | 13 | /** |
| kadonotakashi | 0:8fdf9a60065b | 14 | @addtogroup I2S I2S Interface Controller(I2S) |
| kadonotakashi | 0:8fdf9a60065b | 15 | Memory Mapped Structure for I2S Controller |
| kadonotakashi | 0:8fdf9a60065b | 16 | @{ */ |
| kadonotakashi | 0:8fdf9a60065b | 17 | |
| kadonotakashi | 0:8fdf9a60065b | 18 | typedef struct |
| kadonotakashi | 0:8fdf9a60065b | 19 | { |
| kadonotakashi | 0:8fdf9a60065b | 20 | |
| kadonotakashi | 0:8fdf9a60065b | 21 | |
| kadonotakashi | 0:8fdf9a60065b | 22 | /** |
| kadonotakashi | 0:8fdf9a60065b | 23 | * @var I2S_T::CTL0 |
| kadonotakashi | 0:8fdf9a60065b | 24 | * Offset: 0x00 I2S Control Register 0 |
| kadonotakashi | 0:8fdf9a60065b | 25 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 26 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 27 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 28 | * |[0] |I2SEN |I2S Controller Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 29 | * | | |0 = I2S controller Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 30 | * | | |1 = I2S controller Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 31 | * |[1] |TXEN |Transmit Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 32 | * | | |0 = Data transmission Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 33 | * | | |1 = Data transmission Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 34 | * |[2] |RXEN |Receive Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 35 | * | | |0 = Data receiving Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 36 | * | | |1 = Data receiving Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 37 | * |[3] |MUTE |Transmit Mute Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 38 | * | | |0 = Transmit data is shifted from buffer. |
| kadonotakashi | 0:8fdf9a60065b | 39 | * | | |1 = Send zero on transmit channel. |
| kadonotakashi | 0:8fdf9a60065b | 40 | * |[5:4] |DATWIDTH |Data Width |
| kadonotakashi | 0:8fdf9a60065b | 41 | * | | |This bit field is used to define the bit-width of data word in each audio channel |
| kadonotakashi | 0:8fdf9a60065b | 42 | * | | |00 = The bit-width of data word is 8-bit. |
| kadonotakashi | 0:8fdf9a60065b | 43 | * | | |01 = The bit-width of data word is 16-bit. |
| kadonotakashi | 0:8fdf9a60065b | 44 | * | | |10 = The bit-width of data word is 24-bit. |
| kadonotakashi | 0:8fdf9a60065b | 45 | * | | |11 = The bit-width of data word is 32-bit. |
| kadonotakashi | 0:8fdf9a60065b | 46 | * |[6] |MONO |Monaural Data Control |
| kadonotakashi | 0:8fdf9a60065b | 47 | * | | |0 = Data is stereo format. |
| kadonotakashi | 0:8fdf9a60065b | 48 | * | | |1 = Data is monaural format. |
| kadonotakashi | 0:8fdf9a60065b | 49 | * | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected. |
| kadonotakashi | 0:8fdf9a60065b | 50 | * |[7] |ORDER |Stereo Data Order in FIFO |
| kadonotakashi | 0:8fdf9a60065b | 51 | * | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte |
| kadonotakashi | 0:8fdf9a60065b | 52 | * | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries. |
| kadonotakashi | 0:8fdf9a60065b | 53 | * | | |0 = Even channel data at high byte in 8-bit/16-bit data width. |
| kadonotakashi | 0:8fdf9a60065b | 54 | * | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries. |
| kadonotakashi | 0:8fdf9a60065b | 55 | * | | |1 = Even channel data at low byte. |
| kadonotakashi | 0:8fdf9a60065b | 56 | * | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries. |
| kadonotakashi | 0:8fdf9a60065b | 57 | * |[8] |SLAVE |Slave Mode Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 58 | * | | |0 = Master mode. |
| kadonotakashi | 0:8fdf9a60065b | 59 | * | | |1 = Slave mode. |
| kadonotakashi | 0:8fdf9a60065b | 60 | * | | |Note: I2S can operate as master or slave |
| kadonotakashi | 0:8fdf9a60065b | 61 | * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip |
| kadonotakashi | 0:8fdf9a60065b | 62 | * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. |
| kadonotakashi | 0:8fdf9a60065b | 63 | * |[15] |MCLKEN |Master Clock Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 64 | * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices. |
| kadonotakashi | 0:8fdf9a60065b | 65 | * | | |0 = Master clock Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 66 | * | | |1 = Master clock Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 67 | * |[18] |TXFBCLR |Transmit FIFO Buffer Clear |
| kadonotakashi | 0:8fdf9a60065b | 68 | * | | |0 = No Effect. |
| kadonotakashi | 0:8fdf9a60065b | 69 | * | | |1 = Clear TX FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 70 | * | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. |
| kadonotakashi | 0:8fdf9a60065b | 71 | * | | |Note2: This bit is clear by hardware automatically, read it return zero. |
| kadonotakashi | 0:8fdf9a60065b | 72 | * |[19] |RXFBCLR |Receive FIFO Buffer Clear |
| kadonotakashi | 0:8fdf9a60065b | 73 | * | | |0 = No Effect. |
| kadonotakashi | 0:8fdf9a60065b | 74 | * | | |1 = Clear RX FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 75 | * | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty. |
| kadonotakashi | 0:8fdf9a60065b | 76 | * | | |Note2: This bit is cleared by hardware automatically, read it return zero. |
| kadonotakashi | 0:8fdf9a60065b | 77 | * |[20] |TXPDMAEN |Transmit PDMA Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 78 | * | | |0 = Transmit PDMA function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 79 | * | | |1 = Transmit PDMA function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 80 | * |[21] |RXPDMAEN |Receive PDMA Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 81 | * | | |0 = Receiver PDMA function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 82 | * | | |1 = Receiver PDMA function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 83 | * |[23] |RXLCH |Receive Left Channel Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 84 | * | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 85 | * | | |0 = Receives channel1 data in MONO mode. |
| kadonotakashi | 0:8fdf9a60065b | 86 | * | | |1 = Receives channel0 data in MONO mode. |
| kadonotakashi | 0:8fdf9a60065b | 87 | * |[26:24] |FORMAT |Data Format Selection |
| kadonotakashi | 0:8fdf9a60065b | 88 | * | | |000 = I2S standard data format. |
| kadonotakashi | 0:8fdf9a60065b | 89 | * | | |001 = I2S with MSB justified. |
| kadonotakashi | 0:8fdf9a60065b | 90 | * | | |010 = I2S with LSB justified. |
| kadonotakashi | 0:8fdf9a60065b | 91 | * | | |011 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 92 | * | | |100 = PCM standard data format. |
| kadonotakashi | 0:8fdf9a60065b | 93 | * | | |101 = PCM with MSB justified. |
| kadonotakashi | 0:8fdf9a60065b | 94 | * | | |110 = PCM with LSB justified. |
| kadonotakashi | 0:8fdf9a60065b | 95 | * | | |111 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 96 | * |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection |
| kadonotakashi | 0:8fdf9a60065b | 97 | * | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol |
| kadonotakashi | 0:8fdf9a60065b | 98 | * | | |0 = One BCLK period. |
| kadonotakashi | 0:8fdf9a60065b | 99 | * | | |1 = One channel period. |
| kadonotakashi | 0:8fdf9a60065b | 100 | * | | |Note: This bit is only available in master mode |
| kadonotakashi | 0:8fdf9a60065b | 101 | * |[29:28] |CHWIDTH |Channel Width |
| kadonotakashi | 0:8fdf9a60065b | 102 | * | | |This bit fields are used to define the length of audio channel |
| kadonotakashi | 0:8fdf9a60065b | 103 | * | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH. |
| kadonotakashi | 0:8fdf9a60065b | 104 | * | | |00 = The bit-width of each audio channel is 8-bit. |
| kadonotakashi | 0:8fdf9a60065b | 105 | * | | |01 = The bit-width of each audio channel is 16-bit. |
| kadonotakashi | 0:8fdf9a60065b | 106 | * | | |10 = The bit-width of each audio channel is 24-bit. |
| kadonotakashi | 0:8fdf9a60065b | 107 | * | | |11 = The bit-width of each audio channel is 32-bit. |
| kadonotakashi | 0:8fdf9a60065b | 108 | * |[31:30] |TDMCHNUM |TDM Channel Number |
| kadonotakashi | 0:8fdf9a60065b | 109 | * | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1). |
| kadonotakashi | 0:8fdf9a60065b | 110 | * | | |00 = 2 channels in audio frame. |
| kadonotakashi | 0:8fdf9a60065b | 111 | * | | |01 = 4 channels in audio frame. |
| kadonotakashi | 0:8fdf9a60065b | 112 | * | | |10 = 6 channels in audio frame. |
| kadonotakashi | 0:8fdf9a60065b | 113 | * | | |11 = 8 channels in audio frame. |
| kadonotakashi | 0:8fdf9a60065b | 114 | * @var I2S_T::CLKDIV |
| kadonotakashi | 0:8fdf9a60065b | 115 | * Offset: 0x04 I2S Clock Divider Register |
| kadonotakashi | 0:8fdf9a60065b | 116 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 117 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 118 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 119 | * |[5:0] |MCLKDIV |Master Clock Divider |
| kadonotakashi | 0:8fdf9a60065b | 120 | * | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip |
| kadonotakashi | 0:8fdf9a60065b | 121 | * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input. |
| kadonotakashi | 0:8fdf9a60065b | 122 | * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1. |
| kadonotakashi | 0:8fdf9a60065b | 123 | * | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ). |
| kadonotakashi | 0:8fdf9a60065b | 124 | * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ). |
| kadonotakashi | 0:8fdf9a60065b | 125 | * | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK |
| kadonotakashi | 0:8fdf9a60065b | 126 | * |[16:8] |BCLKDIV |Bit Clock Divider |
| kadonotakashi | 0:8fdf9a60065b | 127 | * | | |The I2S controller will generate bit clock in Master mode |
| kadonotakashi | 0:8fdf9a60065b | 128 | * | | |Software can program these bit fields to generate sampling rate clock frequency. |
| kadonotakashi | 0:8fdf9a60065b | 129 | * | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)). |
| kadonotakashi | 0:8fdf9a60065b | 130 | * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK |
| kadonotakashi | 0:8fdf9a60065b | 131 | * @var I2S_T::IEN |
| kadonotakashi | 0:8fdf9a60065b | 132 | * Offset: 0x08 I2S Interrupt Enable Register |
| kadonotakashi | 0:8fdf9a60065b | 133 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 134 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 135 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 136 | * |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 137 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 138 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 139 | * | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 140 | * |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 141 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 142 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 143 | * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1 |
| kadonotakashi | 0:8fdf9a60065b | 144 | * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 145 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 146 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 147 | * | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1 |
| kadonotakashi | 0:8fdf9a60065b | 148 | * | | |If RXTHIEN bit is enabled, interrupt occur. |
| kadonotakashi | 0:8fdf9a60065b | 149 | * |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 150 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 151 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 152 | * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 153 | * |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 154 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 155 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 156 | * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1 |
| kadonotakashi | 0:8fdf9a60065b | 157 | * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 158 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 159 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 160 | * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]). |
| kadonotakashi | 0:8fdf9a60065b | 161 | * |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 162 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 163 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 164 | * | | |Note1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross |
| kadonotakashi | 0:8fdf9a60065b | 165 | * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. |
| kadonotakashi | 0:8fdf9a60065b | 166 | * |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 167 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 168 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 169 | * | | |Note1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross |
| kadonotakashi | 0:8fdf9a60065b | 170 | * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. |
| kadonotakashi | 0:8fdf9a60065b | 171 | * |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 172 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 173 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 174 | * | | |Note1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross |
| kadonotakashi | 0:8fdf9a60065b | 175 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 176 | * |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 177 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 178 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 179 | * | | |Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross |
| kadonotakashi | 0:8fdf9a60065b | 180 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 181 | * |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 182 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 183 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 184 | * | | |Note1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross |
| kadonotakashi | 0:8fdf9a60065b | 185 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 186 | * |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 187 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 188 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 189 | * | | |Note1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross |
| kadonotakashi | 0:8fdf9a60065b | 190 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 191 | * |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 192 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 193 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 194 | * | | |Note1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross |
| kadonotakashi | 0:8fdf9a60065b | 195 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 196 | * |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 197 | * | | |0 = Interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 198 | * | | |1 = Interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 199 | * | | |Note1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross |
| kadonotakashi | 0:8fdf9a60065b | 200 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 201 | * @var I2S_T::STATUS0 |
| kadonotakashi | 0:8fdf9a60065b | 202 | * Offset: 0x0C I2S Status Register 0 |
| kadonotakashi | 0:8fdf9a60065b | 203 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 204 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 205 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 206 | * |[0] |I2SINT |I2S Interrupt Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 207 | * | | |0 = No I2S interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 208 | * | | |1 = I2S interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 209 | * | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits. |
| kadonotakashi | 0:8fdf9a60065b | 210 | * |[1] |I2SRXINT |I2S Receive Interrupt (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 211 | * | | |0 = No receive interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 212 | * | | |1 = Receive interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 213 | * |[2] |I2STXINT |I2S Transmit Interrupt (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 214 | * | | |0 = No transmit interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 215 | * | | |1 = Transmit interrupt. |
| kadonotakashi | 0:8fdf9a60065b | 216 | * |[5:3] |DATACH |Transmission Data Channel (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 217 | * | | |This bit fields are used to indicate which audio channel is current transmit data belong. |
| kadonotakashi | 0:8fdf9a60065b | 218 | * | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode). |
| kadonotakashi | 0:8fdf9a60065b | 219 | * | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode). |
| kadonotakashi | 0:8fdf9a60065b | 220 | * | | |010 = channel2 (available while 4-channel TDM PCM mode). |
| kadonotakashi | 0:8fdf9a60065b | 221 | * | | |011 = channel3 (available while 4-channel TDM PCM mode). |
| kadonotakashi | 0:8fdf9a60065b | 222 | * | | |100 = channel4 (available while 6-channel TDM PCM mode). |
| kadonotakashi | 0:8fdf9a60065b | 223 | * | | |101 = channel5 (available while 6-channel TDM PCM mode). |
| kadonotakashi | 0:8fdf9a60065b | 224 | * | | |110 = channel6 (available while 8-channel TDM PCM mode). |
| kadonotakashi | 0:8fdf9a60065b | 225 | * | | |111 = channel7 (available while 8-channel TDM PCM mode). |
| kadonotakashi | 0:8fdf9a60065b | 226 | * |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 227 | * | | |0 = No underflow occur. |
| kadonotakashi | 0:8fdf9a60065b | 228 | * | | |1 = Underflow occur. |
| kadonotakashi | 0:8fdf9a60065b | 229 | * | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again |
| kadonotakashi | 0:8fdf9a60065b | 230 | * | | |This bit will be set to 1, and it indicates underflow situation occurs. |
| kadonotakashi | 0:8fdf9a60065b | 231 | * | | |Note2: Write 1 to clear this bit to zero |
| kadonotakashi | 0:8fdf9a60065b | 232 | * |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 233 | * | | |0 = No overflow occur. |
| kadonotakashi | 0:8fdf9a60065b | 234 | * | | |1 = Overflow occur. |
| kadonotakashi | 0:8fdf9a60065b | 235 | * | | |Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. |
| kadonotakashi | 0:8fdf9a60065b | 236 | * | | |Note2: Write 1 to clear this bit to 0. |
| kadonotakashi | 0:8fdf9a60065b | 237 | * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 238 | * | | |0 = Data word(s) in FIFO is not higher than threshold level. |
| kadonotakashi | 0:8fdf9a60065b | 239 | * | | |1 = Data word(s) in FIFO is higher than threshold level. |
| kadonotakashi | 0:8fdf9a60065b | 240 | * | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1 |
| kadonotakashi | 0:8fdf9a60065b | 241 | * | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register. |
| kadonotakashi | 0:8fdf9a60065b | 242 | * |[11] |RXFULL |Receive FIFO Full (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 243 | * | | |0 = Not full. |
| kadonotakashi | 0:8fdf9a60065b | 244 | * | | |1 = Full. |
| kadonotakashi | 0:8fdf9a60065b | 245 | * | | |Note: This bit reflects data words number in receive FIFO is 16. |
| kadonotakashi | 0:8fdf9a60065b | 246 | * |[12] |RXEMPTY |Receive FIFO Empty (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 247 | * | | |0 = Not empty. |
| kadonotakashi | 0:8fdf9a60065b | 248 | * | | |1 = Empty. |
| kadonotakashi | 0:8fdf9a60065b | 249 | * | | |Note: This bit reflects data words number in receive FIFO is zero |
| kadonotakashi | 0:8fdf9a60065b | 250 | * |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 251 | * | | |0 = No underflow. |
| kadonotakashi | 0:8fdf9a60065b | 252 | * | | |1 = Underflow. |
| kadonotakashi | 0:8fdf9a60065b | 253 | * | | |Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. |
| kadonotakashi | 0:8fdf9a60065b | 254 | * | | |Note2: Write 1 to clear this bit to 0. |
| kadonotakashi | 0:8fdf9a60065b | 255 | * |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 256 | * | | |0 = No overflow. |
| kadonotakashi | 0:8fdf9a60065b | 257 | * | | |1 = Overflow. |
| kadonotakashi | 0:8fdf9a60065b | 258 | * | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1 |
| kadonotakashi | 0:8fdf9a60065b | 259 | * | | |Note2: Write 1 to clear this bit to 0. |
| kadonotakashi | 0:8fdf9a60065b | 260 | * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 261 | * | | |0 = Data word(s) in FIFO is higher than threshold level. |
| kadonotakashi | 0:8fdf9a60065b | 262 | * | | |1 = Data word(s) in FIFO is equal or lower than threshold level. |
| kadonotakashi | 0:8fdf9a60065b | 263 | * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1 |
| kadonotakashi | 0:8fdf9a60065b | 264 | * | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register. |
| kadonotakashi | 0:8fdf9a60065b | 265 | * |[19] |TXFULL |Transmit FIFO Full (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 266 | * | | |This bit reflect data word number in transmit FIFO is 16 |
| kadonotakashi | 0:8fdf9a60065b | 267 | * | | |0 = Not full. |
| kadonotakashi | 0:8fdf9a60065b | 268 | * | | |1 = Full. |
| kadonotakashi | 0:8fdf9a60065b | 269 | * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 270 | * | | |This bit reflect data word number in transmit FIFO is zero |
| kadonotakashi | 0:8fdf9a60065b | 271 | * | | |0 = Not empty. |
| kadonotakashi | 0:8fdf9a60065b | 272 | * | | |1 = Empty. |
| kadonotakashi | 0:8fdf9a60065b | 273 | * |[21] |TXBUSY |Transmit Busy (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 274 | * | | |0 = Transmit shift buffer is empty. |
| kadonotakashi | 0:8fdf9a60065b | 275 | * | | |1 = Transmit shift buffer is busy. |
| kadonotakashi | 0:8fdf9a60065b | 276 | * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out |
| kadonotakashi | 0:8fdf9a60065b | 277 | * | | |And set to 1 when 1st data is load to shift buffer |
| kadonotakashi | 0:8fdf9a60065b | 278 | * @var I2S_T::TXFIFO |
| kadonotakashi | 0:8fdf9a60065b | 279 | * Offset: 0x10 I2S Transmit FIFO Register |
| kadonotakashi | 0:8fdf9a60065b | 280 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 281 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 282 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 283 | * |[31:0] |TXFIFO |Transmit FIFO Bits |
| kadonotakashi | 0:8fdf9a60065b | 284 | * | | |I2S contains 16 words (16x32 bit) data buffer for data transmit |
| kadonotakashi | 0:8fdf9a60065b | 285 | * | | |Write data to this register to prepare data for transmit |
| kadonotakashi | 0:8fdf9a60065b | 286 | * | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]). |
| kadonotakashi | 0:8fdf9a60065b | 287 | * @var I2S_T::RXFIFO |
| kadonotakashi | 0:8fdf9a60065b | 288 | * Offset: 0x14 I2S Receive FIFO Register |
| kadonotakashi | 0:8fdf9a60065b | 289 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 290 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 291 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 292 | * |[31:0] |RXFIFO |Receive FIFO Bits |
| kadonotakashi | 0:8fdf9a60065b | 293 | * | | |I2S contains 16 words (16x32 bit) data buffer for data receive |
| kadonotakashi | 0:8fdf9a60065b | 294 | * | | |Read this register to get data in FIFO |
| kadonotakashi | 0:8fdf9a60065b | 295 | * | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]). |
| kadonotakashi | 0:8fdf9a60065b | 296 | * @var I2S_T::CTL1 |
| kadonotakashi | 0:8fdf9a60065b | 297 | * Offset: 0x20 I2S Control Register 1 |
| kadonotakashi | 0:8fdf9a60065b | 298 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 299 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 300 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 301 | * |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 302 | * | | |0 = channel0 zero-cross detect Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 303 | * | | |1 = channel0 zero-cross detect Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 304 | * | | |Note1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. |
| kadonotakashi | 0:8fdf9a60065b | 305 | * | | |Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 306 | * | | |Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute. |
| kadonotakashi | 0:8fdf9a60065b | 307 | * |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 308 | * | | |0 = channel1 zero-cross detect Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 309 | * | | |1 = channel1 zero-cross detect Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 310 | * | | |Note1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. |
| kadonotakashi | 0:8fdf9a60065b | 311 | * | | |Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 312 | * | | |Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute. |
| kadonotakashi | 0:8fdf9a60065b | 313 | * |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 314 | * | | |0 = channel2 zero-cross detect Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 315 | * | | |1 = channel2 zero-cross detect Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 316 | * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 317 | * | | |Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 318 | * | | |Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute. |
| kadonotakashi | 0:8fdf9a60065b | 319 | * |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 320 | * | | |0 = channel3 zero-cross detect Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 321 | * | | |1 = channel3 zero-cross detect Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 322 | * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 323 | * | | |Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 324 | * | | |Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute. |
| kadonotakashi | 0:8fdf9a60065b | 325 | * |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 326 | * | | |0 = channel4 zero-cross detect Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 327 | * | | |1 = channel4 zero-cross detect Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 328 | * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 329 | * | | |Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 330 | * | | |Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute. |
| kadonotakashi | 0:8fdf9a60065b | 331 | * |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 332 | * | | |0 = channel5 zero-cross detect Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 333 | * | | |1 = channel5 zero-cross detect Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 334 | * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 335 | * | | |Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 336 | * | | |Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute. |
| kadonotakashi | 0:8fdf9a60065b | 337 | * |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 338 | * | | |0 = channel6 zero-cross detect Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 339 | * | | |1 = channel6 zero-cross detect Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 340 | * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 341 | * | | |Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 342 | * | | |Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute. |
| kadonotakashi | 0:8fdf9a60065b | 343 | * |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 344 | * | | |0 = channel7 zero-cross detect Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 345 | * | | |1 = channel7 zero-cross detect Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 346 | * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 347 | * | | |Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1. |
| kadonotakashi | 0:8fdf9a60065b | 348 | * | | |Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute. |
| kadonotakashi | 0:8fdf9a60065b | 349 | * |[11:8] |TXTH |Transmit FIFO Threshold Level |
| kadonotakashi | 0:8fdf9a60065b | 350 | * | | |0000 = 0 data word in transmit FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 351 | * | | |0001 = 1 data word in transmit FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 352 | * | | |0010 = 2 data words in transmit FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 353 | * | | |... |
| kadonotakashi | 0:8fdf9a60065b | 354 | * | | |1110 = 14 data words in transmit FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 355 | * | | |1111 = 15 data words in transmit FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 356 | * | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set. |
| kadonotakashi | 0:8fdf9a60065b | 357 | * |[19:16] |RXTH |Receive FIFO Threshold Level |
| kadonotakashi | 0:8fdf9a60065b | 358 | * | | |0000 = 1 data word in receive FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 359 | * | | |0001 = 2 data words in receive FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 360 | * | | |0010 = 3 data words in receive FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 361 | * | | |... |
| kadonotakashi | 0:8fdf9a60065b | 362 | * | | |1110 = 15 data words in receive FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 363 | * | | |1111 = 16 data words in receive FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 364 | * | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set. |
| kadonotakashi | 0:8fdf9a60065b | 365 | * |[24] |PBWIDTH |Peripheral Bus Data Width Selection |
| kadonotakashi | 0:8fdf9a60065b | 366 | * | | |This bit is used to choice the available data width of APB bus |
| kadonotakashi | 0:8fdf9a60065b | 367 | * | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode |
| kadonotakashi | 0:8fdf9a60065b | 368 | * | | |0 = 32 bits data width. |
| kadonotakashi | 0:8fdf9a60065b | 369 | * | | |1 = 16 bits data width. |
| kadonotakashi | 0:8fdf9a60065b | 370 | * | | |Note1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available. |
| kadonotakashi | 0:8fdf9a60065b | 371 | * | | |Note2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations. |
| kadonotakashi | 0:8fdf9a60065b | 372 | * | | |Note3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations. |
| kadonotakashi | 0:8fdf9a60065b | 373 | * |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus |
| kadonotakashi | 0:8fdf9a60065b | 374 | * | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access |
| kadonotakashi | 0:8fdf9a60065b | 375 | * | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries. |
| kadonotakashi | 0:8fdf9a60065b | 376 | * | | |0 = Low 16-bit read/write access first. |
| kadonotakashi | 0:8fdf9a60065b | 377 | * | | |1 = High 16-bit read/write access first. |
| kadonotakashi | 0:8fdf9a60065b | 378 | * | | |Note: This bit is available while PBWIDTH = 1. |
| kadonotakashi | 0:8fdf9a60065b | 379 | * @var I2S_T::STATUS1 |
| kadonotakashi | 0:8fdf9a60065b | 380 | * Offset: 0x24 I2S Status Register 1 |
| kadonotakashi | 0:8fdf9a60065b | 381 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 382 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 383 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 384 | * |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 385 | * | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero. |
| kadonotakashi | 0:8fdf9a60065b | 386 | * | | |0 = No zero-cross in channel0. |
| kadonotakashi | 0:8fdf9a60065b | 387 | * | | |1 = Channel0 zero-cross is detected. |
| kadonotakashi | 0:8fdf9a60065b | 388 | * | | |Note1: Write 1 to clear this bit to 0. |
| kadonotakashi | 0:8fdf9a60065b | 389 | * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. |
| kadonotakashi | 0:8fdf9a60065b | 390 | * |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 391 | * | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero. |
| kadonotakashi | 0:8fdf9a60065b | 392 | * | | |0 = No zero-cross in channel1. |
| kadonotakashi | 0:8fdf9a60065b | 393 | * | | |1 = Channel1 zero-cross is detected. |
| kadonotakashi | 0:8fdf9a60065b | 394 | * | | |Note1: Write 1 to clear this bit to 0. |
| kadonotakashi | 0:8fdf9a60065b | 395 | * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. |
| kadonotakashi | 0:8fdf9a60065b | 396 | * |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 397 | * | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero. |
| kadonotakashi | 0:8fdf9a60065b | 398 | * | | |0 = No zero-cross in channel2. |
| kadonotakashi | 0:8fdf9a60065b | 399 | * | | |1 = Channel2 zero-cross is detected. |
| kadonotakashi | 0:8fdf9a60065b | 400 | * | | |Note1: Write 1 to clear this bit to 0. |
| kadonotakashi | 0:8fdf9a60065b | 401 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 402 | * |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 403 | * | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero. |
| kadonotakashi | 0:8fdf9a60065b | 404 | * | | |0 = No zero-cross in channel3. |
| kadonotakashi | 0:8fdf9a60065b | 405 | * | | |1 = Channel3 zero-cross is detected. |
| kadonotakashi | 0:8fdf9a60065b | 406 | * | | |Note1: Write 1 to clear this bit to 0. |
| kadonotakashi | 0:8fdf9a60065b | 407 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 408 | * |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 409 | * | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero. |
| kadonotakashi | 0:8fdf9a60065b | 410 | * | | |0 = No zero-cross in channel4. |
| kadonotakashi | 0:8fdf9a60065b | 411 | * | | |1 = Channel4 zero-cross is detected. |
| kadonotakashi | 0:8fdf9a60065b | 412 | * | | |Note1: Write 1 to clear this bit to 0. |
| kadonotakashi | 0:8fdf9a60065b | 413 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 414 | * |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 415 | * | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero. |
| kadonotakashi | 0:8fdf9a60065b | 416 | * | | |0 = No zero-cross in channel5. |
| kadonotakashi | 0:8fdf9a60065b | 417 | * | | |1 = Channel5 zero-cross is detected. |
| kadonotakashi | 0:8fdf9a60065b | 418 | * | | |Note1: Write 1 to clear this bit to 0. |
| kadonotakashi | 0:8fdf9a60065b | 419 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 420 | * |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 421 | * | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero. |
| kadonotakashi | 0:8fdf9a60065b | 422 | * | | |0 = No zero-cross in channel6. |
| kadonotakashi | 0:8fdf9a60065b | 423 | * | | |1 = Channel6 zero-cross is detected. |
| kadonotakashi | 0:8fdf9a60065b | 424 | * | | |Note1: Write 1 to clear this bit to 0. |
| kadonotakashi | 0:8fdf9a60065b | 425 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 426 | * |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag |
| kadonotakashi | 0:8fdf9a60065b | 427 | * | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero. |
| kadonotakashi | 0:8fdf9a60065b | 428 | * | | |0 = No zero-cross in channel7. |
| kadonotakashi | 0:8fdf9a60065b | 429 | * | | |1 = Channel7 zero-cross is detected. |
| kadonotakashi | 0:8fdf9a60065b | 430 | * | | |Note1: Write 1 to clear this bit to 0. |
| kadonotakashi | 0:8fdf9a60065b | 431 | * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. |
| kadonotakashi | 0:8fdf9a60065b | 432 | * |[12:8] |TXCNT |Transmit FIFO Level (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 433 | * | | |These bits indicate the number of available entries in transmit FIFO |
| kadonotakashi | 0:8fdf9a60065b | 434 | * | | |00000 = No data. |
| kadonotakashi | 0:8fdf9a60065b | 435 | * | | |00001 = 1 word in transmit FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 436 | * | | |00010 = 2 words in transmit FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 437 | * | | |... |
| kadonotakashi | 0:8fdf9a60065b | 438 | * | | |01110 = 14 words in transmit FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 439 | * | | |01111 = 15 words in transmit FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 440 | * | | |10000 = 16 words in transmit FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 441 | * | | |Others are reserved. |
| kadonotakashi | 0:8fdf9a60065b | 442 | * |[20:16] |RXCNT |Receive FIFO Level (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 443 | * | | |These bits indicate the number of available entries in receive FIFO |
| kadonotakashi | 0:8fdf9a60065b | 444 | * | | |00000 = No data. |
| kadonotakashi | 0:8fdf9a60065b | 445 | * | | |00001 = 1 word in receive FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 446 | * | | |00010 = 2 words in receive FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 447 | * | | |... |
| kadonotakashi | 0:8fdf9a60065b | 448 | * | | |01110 = 14 words in receive FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 449 | * | | |01111 = 15 words in receive FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 450 | * | | |10000 = 16 words in receive FIFO. |
| kadonotakashi | 0:8fdf9a60065b | 451 | * | | |Others are reserved. |
| kadonotakashi | 0:8fdf9a60065b | 452 | */ |
| kadonotakashi | 0:8fdf9a60065b | 453 | __IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */ |
| kadonotakashi | 0:8fdf9a60065b | 454 | __IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */ |
| kadonotakashi | 0:8fdf9a60065b | 455 | __IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */ |
| kadonotakashi | 0:8fdf9a60065b | 456 | __IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */ |
| kadonotakashi | 0:8fdf9a60065b | 457 | __O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */ |
| kadonotakashi | 0:8fdf9a60065b | 458 | __I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */ |
| kadonotakashi | 0:8fdf9a60065b | 459 | __I uint32_t RESERVE0[2]; |
| kadonotakashi | 0:8fdf9a60065b | 460 | __IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */ |
| kadonotakashi | 0:8fdf9a60065b | 461 | __IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */ |
| kadonotakashi | 0:8fdf9a60065b | 462 | |
| kadonotakashi | 0:8fdf9a60065b | 463 | } I2S_T; |
| kadonotakashi | 0:8fdf9a60065b | 464 | |
| kadonotakashi | 0:8fdf9a60065b | 465 | /** |
| kadonotakashi | 0:8fdf9a60065b | 466 | @addtogroup I2S_CONST I2S Bit Field Definition |
| kadonotakashi | 0:8fdf9a60065b | 467 | Constant Definitions for I2S Controller |
| kadonotakashi | 0:8fdf9a60065b | 468 | @{ */ |
| kadonotakashi | 0:8fdf9a60065b | 469 | |
| kadonotakashi | 0:8fdf9a60065b | 470 | #define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 471 | #define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 472 | |
| kadonotakashi | 0:8fdf9a60065b | 473 | #define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 474 | #define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 475 | |
| kadonotakashi | 0:8fdf9a60065b | 476 | #define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 477 | #define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 478 | |
| kadonotakashi | 0:8fdf9a60065b | 479 | #define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */ |
| kadonotakashi | 0:8fdf9a60065b | 480 | #define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 481 | |
| kadonotakashi | 0:8fdf9a60065b | 482 | #define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */ |
| kadonotakashi | 0:8fdf9a60065b | 483 | #define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 484 | |
| kadonotakashi | 0:8fdf9a60065b | 485 | #define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */ |
| kadonotakashi | 0:8fdf9a60065b | 486 | #define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 487 | |
| kadonotakashi | 0:8fdf9a60065b | 488 | #define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */ |
| kadonotakashi | 0:8fdf9a60065b | 489 | #define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 490 | |
| kadonotakashi | 0:8fdf9a60065b | 491 | #define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */ |
| kadonotakashi | 0:8fdf9a60065b | 492 | #define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 493 | |
| kadonotakashi | 0:8fdf9a60065b | 494 | #define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 495 | #define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 496 | |
| kadonotakashi | 0:8fdf9a60065b | 497 | #define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */ |
| kadonotakashi | 0:8fdf9a60065b | 498 | #define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 499 | |
| kadonotakashi | 0:8fdf9a60065b | 500 | #define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */ |
| kadonotakashi | 0:8fdf9a60065b | 501 | #define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 502 | |
| kadonotakashi | 0:8fdf9a60065b | 503 | #define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 504 | #define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 505 | |
| kadonotakashi | 0:8fdf9a60065b | 506 | #define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 507 | #define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 508 | |
| kadonotakashi | 0:8fdf9a60065b | 509 | #define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */ |
| kadonotakashi | 0:8fdf9a60065b | 510 | #define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 511 | |
| kadonotakashi | 0:8fdf9a60065b | 512 | #define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 513 | #define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 514 | |
| kadonotakashi | 0:8fdf9a60065b | 515 | #define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */ |
| kadonotakashi | 0:8fdf9a60065b | 516 | #define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 517 | |
| kadonotakashi | 0:8fdf9a60065b | 518 | #define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */ |
| kadonotakashi | 0:8fdf9a60065b | 519 | #define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 520 | |
| kadonotakashi | 0:8fdf9a60065b | 521 | #define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */ |
| kadonotakashi | 0:8fdf9a60065b | 522 | #define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 523 | |
| kadonotakashi | 0:8fdf9a60065b | 524 | #define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 525 | #define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 526 | |
| kadonotakashi | 0:8fdf9a60065b | 527 | #define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */ |
| kadonotakashi | 0:8fdf9a60065b | 528 | #define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 529 | |
| kadonotakashi | 0:8fdf9a60065b | 530 | #define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 531 | #define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 532 | |
| kadonotakashi | 0:8fdf9a60065b | 533 | #define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 534 | #define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 535 | |
| kadonotakashi | 0:8fdf9a60065b | 536 | #define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 537 | #define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 538 | |
| kadonotakashi | 0:8fdf9a60065b | 539 | #define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 540 | #define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 541 | |
| kadonotakashi | 0:8fdf9a60065b | 542 | #define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 543 | #define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 544 | |
| kadonotakashi | 0:8fdf9a60065b | 545 | #define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 546 | #define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 547 | |
| kadonotakashi | 0:8fdf9a60065b | 548 | #define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 549 | #define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 550 | |
| kadonotakashi | 0:8fdf9a60065b | 551 | #define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 552 | #define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 553 | |
| kadonotakashi | 0:8fdf9a60065b | 554 | #define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 555 | #define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 556 | |
| kadonotakashi | 0:8fdf9a60065b | 557 | #define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 558 | #define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 559 | |
| kadonotakashi | 0:8fdf9a60065b | 560 | #define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 561 | #define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 562 | |
| kadonotakashi | 0:8fdf9a60065b | 563 | #define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 564 | #define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 565 | |
| kadonotakashi | 0:8fdf9a60065b | 566 | #define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 567 | #define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 568 | |
| kadonotakashi | 0:8fdf9a60065b | 569 | #define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 570 | #define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 571 | |
| kadonotakashi | 0:8fdf9a60065b | 572 | #define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 573 | #define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 574 | |
| kadonotakashi | 0:8fdf9a60065b | 575 | #define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 576 | #define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 577 | |
| kadonotakashi | 0:8fdf9a60065b | 578 | #define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 579 | #define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 580 | |
| kadonotakashi | 0:8fdf9a60065b | 581 | #define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */ |
| kadonotakashi | 0:8fdf9a60065b | 582 | #define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 583 | |
| kadonotakashi | 0:8fdf9a60065b | 584 | #define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 585 | #define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 586 | |
| kadonotakashi | 0:8fdf9a60065b | 587 | #define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 588 | #define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 589 | |
| kadonotakashi | 0:8fdf9a60065b | 590 | #define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 591 | #define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 592 | |
| kadonotakashi | 0:8fdf9a60065b | 593 | #define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 594 | #define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 595 | |
| kadonotakashi | 0:8fdf9a60065b | 596 | #define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */ |
| kadonotakashi | 0:8fdf9a60065b | 597 | #define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 598 | |
| kadonotakashi | 0:8fdf9a60065b | 599 | #define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 600 | #define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 601 | |
| kadonotakashi | 0:8fdf9a60065b | 602 | #define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 603 | #define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 604 | |
| kadonotakashi | 0:8fdf9a60065b | 605 | #define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 606 | #define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 607 | |
| kadonotakashi | 0:8fdf9a60065b | 608 | #define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 609 | #define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 610 | |
| kadonotakashi | 0:8fdf9a60065b | 611 | #define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */ |
| kadonotakashi | 0:8fdf9a60065b | 612 | #define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 613 | |
| kadonotakashi | 0:8fdf9a60065b | 614 | #define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */ |
| kadonotakashi | 0:8fdf9a60065b | 615 | #define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 616 | |
| kadonotakashi | 0:8fdf9a60065b | 617 | #define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */ |
| kadonotakashi | 0:8fdf9a60065b | 618 | #define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 619 | |
| kadonotakashi | 0:8fdf9a60065b | 620 | #define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */ |
| kadonotakashi | 0:8fdf9a60065b | 621 | #define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 622 | |
| kadonotakashi | 0:8fdf9a60065b | 623 | #define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 624 | #define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 625 | |
| kadonotakashi | 0:8fdf9a60065b | 626 | #define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 627 | #define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 628 | |
| kadonotakashi | 0:8fdf9a60065b | 629 | #define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 630 | #define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 631 | |
| kadonotakashi | 0:8fdf9a60065b | 632 | #define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 633 | #define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 634 | |
| kadonotakashi | 0:8fdf9a60065b | 635 | #define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 636 | #define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 637 | |
| kadonotakashi | 0:8fdf9a60065b | 638 | #define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 639 | #define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 640 | |
| kadonotakashi | 0:8fdf9a60065b | 641 | #define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 642 | #define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 643 | |
| kadonotakashi | 0:8fdf9a60065b | 644 | #define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 645 | #define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 646 | |
| kadonotakashi | 0:8fdf9a60065b | 647 | #define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */ |
| kadonotakashi | 0:8fdf9a60065b | 648 | #define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 649 | |
| kadonotakashi | 0:8fdf9a60065b | 650 | #define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */ |
| kadonotakashi | 0:8fdf9a60065b | 651 | #define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 652 | |
| kadonotakashi | 0:8fdf9a60065b | 653 | #define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */ |
| kadonotakashi | 0:8fdf9a60065b | 654 | #define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 655 | |
| kadonotakashi | 0:8fdf9a60065b | 656 | #define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */ |
| kadonotakashi | 0:8fdf9a60065b | 657 | #define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 658 | |
| kadonotakashi | 0:8fdf9a60065b | 659 | #define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 660 | #define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 661 | |
| kadonotakashi | 0:8fdf9a60065b | 662 | #define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 663 | #define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 664 | |
| kadonotakashi | 0:8fdf9a60065b | 665 | #define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 666 | #define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 667 | |
| kadonotakashi | 0:8fdf9a60065b | 668 | #define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 669 | #define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 670 | |
| kadonotakashi | 0:8fdf9a60065b | 671 | #define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 672 | #define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 673 | |
| kadonotakashi | 0:8fdf9a60065b | 674 | #define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 675 | #define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 676 | |
| kadonotakashi | 0:8fdf9a60065b | 677 | #define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 678 | #define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 679 | |
| kadonotakashi | 0:8fdf9a60065b | 680 | #define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 681 | #define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 682 | |
| kadonotakashi | 0:8fdf9a60065b | 683 | #define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 684 | #define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 685 | |
| kadonotakashi | 0:8fdf9a60065b | 686 | #define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 687 | #define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 688 | |
| kadonotakashi | 0:8fdf9a60065b | 689 | /**@}*/ /* I2S_CONST */ |
| kadonotakashi | 0:8fdf9a60065b | 690 | /**@}*/ /* end of I2S register group */ |
| kadonotakashi | 0:8fdf9a60065b | 691 | |
| kadonotakashi | 0:8fdf9a60065b | 692 | |
| kadonotakashi | 0:8fdf9a60065b | 693 | |
| kadonotakashi | 0:8fdf9a60065b | 694 | #endif /* __I2S_REG_H__ */ |