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mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/hdiv_reg.h@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
kadonotakashi | 0:8fdf9a60065b | 2 | * @file hdiv_reg.h |
kadonotakashi | 0:8fdf9a60065b | 3 | * @version V1.00 |
kadonotakashi | 0:8fdf9a60065b | 4 | * @brief HDIV register definition header file |
kadonotakashi | 0:8fdf9a60065b | 5 | * |
kadonotakashi | 0:8fdf9a60065b | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 7 | *****************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 8 | #ifndef __HDIV_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 9 | #define __HDIV_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 10 | |
kadonotakashi | 0:8fdf9a60065b | 11 | |
kadonotakashi | 0:8fdf9a60065b | 12 | /*---------------------- Hardware Divider --------------------------------*/ |
kadonotakashi | 0:8fdf9a60065b | 13 | /** |
kadonotakashi | 0:8fdf9a60065b | 14 | @addtogroup HDIV Hardware Divider(HDIV) |
kadonotakashi | 0:8fdf9a60065b | 15 | Memory Mapped Structure for HDIV Controller |
kadonotakashi | 0:8fdf9a60065b | 16 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 17 | |
kadonotakashi | 0:8fdf9a60065b | 18 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 19 | { |
kadonotakashi | 0:8fdf9a60065b | 20 | |
kadonotakashi | 0:8fdf9a60065b | 21 | |
kadonotakashi | 0:8fdf9a60065b | 22 | /** |
kadonotakashi | 0:8fdf9a60065b | 23 | * @var HDIV_T::DIVIDEND |
kadonotakashi | 0:8fdf9a60065b | 24 | * Offset: 0x00 Dividend Source Register |
kadonotakashi | 0:8fdf9a60065b | 25 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 26 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 27 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 28 | * |[31:0] |DIVIDEND |Dividend Source |
kadonotakashi | 0:8fdf9a60065b | 29 | * | | |This register is given the dividend of divider before calculation starting. |
kadonotakashi | 0:8fdf9a60065b | 30 | * @var HDIV_T::DIVISOR |
kadonotakashi | 0:8fdf9a60065b | 31 | * Offset: 0x04 Divisor Source Resister |
kadonotakashi | 0:8fdf9a60065b | 32 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 33 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 34 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 35 | * |[15:0] |DIVISOR |Divisor Source |
kadonotakashi | 0:8fdf9a60065b | 36 | * | | |This register is given the divisor of divider before calculation starts. |
kadonotakashi | 0:8fdf9a60065b | 37 | * | | |Note: When this register is written, hardware divider will start calculate. |
kadonotakashi | 0:8fdf9a60065b | 38 | * @var HDIV_T::DIVQUO |
kadonotakashi | 0:8fdf9a60065b | 39 | * Offset: 0x08 Quotient Result Resister |
kadonotakashi | 0:8fdf9a60065b | 40 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 41 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 42 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 43 | * |[31:0] |QUOTIENT |Quotient Result |
kadonotakashi | 0:8fdf9a60065b | 44 | * | | |This register holds the quotient result of divider after calculation complete. |
kadonotakashi | 0:8fdf9a60065b | 45 | * @var HDIV_T::DIVREM |
kadonotakashi | 0:8fdf9a60065b | 46 | * Offset: 0x0C Remainder Result Register |
kadonotakashi | 0:8fdf9a60065b | 47 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 48 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 49 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 50 | * |[31:0] |REMAINDER |Remainder Result |
kadonotakashi | 0:8fdf9a60065b | 51 | * | | |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete. |
kadonotakashi | 0:8fdf9a60065b | 52 | * | | |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer. |
kadonotakashi | 0:8fdf9a60065b | 53 | * | | |This register holds the remainder result of divider after calculation complete. |
kadonotakashi | 0:8fdf9a60065b | 54 | * @var HDIV_T::DIVSTS |
kadonotakashi | 0:8fdf9a60065b | 55 | * Offset: 0x10 Divider Status Register |
kadonotakashi | 0:8fdf9a60065b | 56 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 57 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 58 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 59 | * |[0] |FINISH |Division Finish Flag |
kadonotakashi | 0:8fdf9a60065b | 60 | * | | |0 = Under Calculation. |
kadonotakashi | 0:8fdf9a60065b | 61 | * | | |1 = Calculation finished. |
kadonotakashi | 0:8fdf9a60065b | 62 | * | | |The flag will become low when the divider is in calculation. |
kadonotakashi | 0:8fdf9a60065b | 63 | * | | |The flag will go back to high once the calculation finished. |
kadonotakashi | 0:8fdf9a60065b | 64 | * |[1] |DIV0 |Divisor Zero Warning |
kadonotakashi | 0:8fdf9a60065b | 65 | * | | |0 = The divisor is not 0. |
kadonotakashi | 0:8fdf9a60065b | 66 | * | | |1 = The divisor is 0. |
kadonotakashi | 0:8fdf9a60065b | 67 | * | | |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written |
kadonotakashi | 0:8fdf9a60065b | 68 | * | | |This register is read only. |
kadonotakashi | 0:8fdf9a60065b | 69 | */ |
kadonotakashi | 0:8fdf9a60065b | 70 | __IO uint32_t DIVIDEND; /*!< [0x0000] Dividend Source Register */ |
kadonotakashi | 0:8fdf9a60065b | 71 | __IO uint32_t DIVISOR; /*!< [0x0004] Divisor Source Resister */ |
kadonotakashi | 0:8fdf9a60065b | 72 | __IO uint32_t DIVQUO; /*!< [0x0008] Quotient Result Resister */ |
kadonotakashi | 0:8fdf9a60065b | 73 | __IO uint32_t DIVREM; /*!< [0x000c] Remainder Result Register */ |
kadonotakashi | 0:8fdf9a60065b | 74 | __I uint32_t DIVSTS; /*!< [0x0010] Divider Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 75 | |
kadonotakashi | 0:8fdf9a60065b | 76 | } HDIV_T; |
kadonotakashi | 0:8fdf9a60065b | 77 | |
kadonotakashi | 0:8fdf9a60065b | 78 | /** |
kadonotakashi | 0:8fdf9a60065b | 79 | @addtogroup HDIV_CONST HDIV Bit Field Definition |
kadonotakashi | 0:8fdf9a60065b | 80 | Constant Definitions for HDIV Controller |
kadonotakashi | 0:8fdf9a60065b | 81 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 82 | |
kadonotakashi | 0:8fdf9a60065b | 83 | #define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */ |
kadonotakashi | 0:8fdf9a60065b | 84 | #define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */ |
kadonotakashi | 0:8fdf9a60065b | 85 | |
kadonotakashi | 0:8fdf9a60065b | 86 | #define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */ |
kadonotakashi | 0:8fdf9a60065b | 87 | #define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 88 | |
kadonotakashi | 0:8fdf9a60065b | 89 | #define HDIV_DIVQUO_QUOTIENT_Pos (0) /*!< HDIV_T::DIVQUO: QUOTIENT Position */ |
kadonotakashi | 0:8fdf9a60065b | 90 | #define HDIV_DIVQUO_QUOTIENT_Msk (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos) /*!< HDIV_T::DIVQUO: QUOTIENT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 91 | |
kadonotakashi | 0:8fdf9a60065b | 92 | #define HDIV_DIVREM_REMAINDER_Pos (0) /*!< HDIV_T::DIVREM: REMAINDER Position */ |
kadonotakashi | 0:8fdf9a60065b | 93 | #define HDIV_DIVREM_REMAINDER_Msk (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos) /*!< HDIV_T::DIVREM: REMAINDER Mask */ |
kadonotakashi | 0:8fdf9a60065b | 94 | |
kadonotakashi | 0:8fdf9a60065b | 95 | #define HDIV_DIVSTS_FINISH_Pos (0) /*!< HDIV_T::DIVSTS: FINISH Position */ |
kadonotakashi | 0:8fdf9a60065b | 96 | #define HDIV_DIVSTS_FINISH_Msk (0x1ul << HDIV_DIVSTS_FINISH_Pos) /*!< HDIV_T::DIVSTS: FINISH Mask */ |
kadonotakashi | 0:8fdf9a60065b | 97 | |
kadonotakashi | 0:8fdf9a60065b | 98 | #define HDIV_DIVSTS_DIV0_Pos (1) /*!< HDIV_T::DIVSTS: DIV0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 99 | #define HDIV_DIVSTS_DIV0_Msk (0x1ul << HDIV_DIVSTS_DIV0_Pos) /*!< HDIV_T::DIVSTS: DIV0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 100 | |
kadonotakashi | 0:8fdf9a60065b | 101 | /**@}*/ /* HDIV_CONST */ |
kadonotakashi | 0:8fdf9a60065b | 102 | /**@}*/ /* end of HDIV register group */ |
kadonotakashi | 0:8fdf9a60065b | 103 | |
kadonotakashi | 0:8fdf9a60065b | 104 | |
kadonotakashi | 0:8fdf9a60065b | 105 | #endif /* __HDIV_REG_H__ */ |