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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/fmc_reg.h@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
kadonotakashi | 0:8fdf9a60065b | 2 | * @file fmc_reg.h |
kadonotakashi | 0:8fdf9a60065b | 3 | * @version V1.00 |
kadonotakashi | 0:8fdf9a60065b | 4 | * @brief FMC register definition header file |
kadonotakashi | 0:8fdf9a60065b | 5 | * |
kadonotakashi | 0:8fdf9a60065b | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 7 | *****************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 8 | #ifndef __FMC_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 9 | #define __FMC_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 10 | |
kadonotakashi | 0:8fdf9a60065b | 11 | /*---------------------- Flash Memory Controller -------------------------*/ |
kadonotakashi | 0:8fdf9a60065b | 12 | /** |
kadonotakashi | 0:8fdf9a60065b | 13 | @addtogroup FMC Flash Memory Controller(FMC) |
kadonotakashi | 0:8fdf9a60065b | 14 | Memory Mapped Structure for FMC Controller |
kadonotakashi | 0:8fdf9a60065b | 15 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 16 | |
kadonotakashi | 0:8fdf9a60065b | 17 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 18 | { |
kadonotakashi | 0:8fdf9a60065b | 19 | |
kadonotakashi | 0:8fdf9a60065b | 20 | |
kadonotakashi | 0:8fdf9a60065b | 21 | /** |
kadonotakashi | 0:8fdf9a60065b | 22 | * @var FMC_T::ISPCTL |
kadonotakashi | 0:8fdf9a60065b | 23 | * Offset: 0x00 ISP Control Register |
kadonotakashi | 0:8fdf9a60065b | 24 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 25 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 26 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 27 | * |[0] |ISPEN |ISP Enable Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 28 | * | | |ISP function enable bit. Set this bit to enable ISP function. |
kadonotakashi | 0:8fdf9a60065b | 29 | * | | |0 = ISP function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 30 | * | | |1 = ISP function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 31 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 32 | * |[1] |BS |Boot Select (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 33 | * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively |
kadonotakashi | 0:8fdf9a60065b | 34 | * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from |
kadonotakashi | 0:8fdf9a60065b | 35 | * | | |This bit is initiated with the inverse value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened |
kadonotakashi | 0:8fdf9a60065b | 36 | * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1. |
kadonotakashi | 0:8fdf9a60065b | 37 | * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. |
kadonotakashi | 0:8fdf9a60065b | 38 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 39 | * |[3] |APUEN |APROM Update Enable Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 40 | * | | |0 = APROM cannot be updated when the chip runs in APROM. |
kadonotakashi | 0:8fdf9a60065b | 41 | * | | |1 = APROM can be updated when the chip runs in APROM. |
kadonotakashi | 0:8fdf9a60065b | 42 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 43 | * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 44 | * | | |0 = CONFIG cannot be updated. |
kadonotakashi | 0:8fdf9a60065b | 45 | * | | |1 = CONFIG can be updated. |
kadonotakashi | 0:8fdf9a60065b | 46 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 47 | * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 48 | * | | |LDROM update enable bit. |
kadonotakashi | 0:8fdf9a60065b | 49 | * | | |0 = LDROM cannot be updated. |
kadonotakashi | 0:8fdf9a60065b | 50 | * | | |1 = LDROM can be updated. |
kadonotakashi | 0:8fdf9a60065b | 51 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 52 | * |[6] |ISPFF |ISP Fail Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 53 | * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: |
kadonotakashi | 0:8fdf9a60065b | 54 | * | | |This bit needs to be cleared by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 55 | * | | |(1) APROM writes to itself if APUEN is set to 0. |
kadonotakashi | 0:8fdf9a60065b | 56 | * | | |(2) LDROM writes to itself if LDUEN is set to 0. |
kadonotakashi | 0:8fdf9a60065b | 57 | * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. |
kadonotakashi | 0:8fdf9a60065b | 58 | * | | |(4) Page Erase command at LOCK mode with ICE connection |
kadonotakashi | 0:8fdf9a60065b | 59 | * | | |(5) Erase or Program command at brown-out detected |
kadonotakashi | 0:8fdf9a60065b | 60 | * | | |(6) Destination address is illegal, such as over an available range. |
kadonotakashi | 0:8fdf9a60065b | 61 | * | | |(7) Invalid ISP commands |
kadonotakashi | 0:8fdf9a60065b | 62 | * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1 |
kadonotakashi | 0:8fdf9a60065b | 63 | * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1 |
kadonotakashi | 0:8fdf9a60065b | 64 | * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1 |
kadonotakashi | 0:8fdf9a60065b | 65 | * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0 |
kadonotakashi | 0:8fdf9a60065b | 66 | * | | |(12) Read any content of boot loader with ICE connection |
kadonotakashi | 0:8fdf9a60065b | 67 | * | | |(13) The address of block erase and bank erase is not in APROM |
kadonotakashi | 0:8fdf9a60065b | 68 | * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command |
kadonotakashi | 0:8fdf9a60065b | 69 | * | | |(15) The wrong setting of page erase ISP CMD in XOM |
kadonotakashi | 0:8fdf9a60065b | 70 | * | | |(16) Violate XOM setting one time protection |
kadonotakashi | 0:8fdf9a60065b | 71 | * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page |
kadonotakashi | 0:8fdf9a60065b | 72 | * | | |(18) Mass erase when MERASE (CFG0[13]) is disable |
kadonotakashi | 0:8fdf9a60065b | 73 | * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP |
kadonotakashi | 0:8fdf9a60065b | 74 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 75 | * |[16] |BL |Boot Loader Booting (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 76 | * | | |This bit is initiated with the inverses value of MBS (CONFIG0[5]) |
kadonotakashi | 0:8fdf9a60065b | 77 | * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded |
kadonotakashi | 0:8fdf9a60065b | 78 | * | | |This bit is used to check chip boot from Boot Loader or not |
kadonotakashi | 0:8fdf9a60065b | 79 | * | | |User should keep original value of this bit when updating FMC_ISPCTL register. |
kadonotakashi | 0:8fdf9a60065b | 80 | * | | |0 = Booting from APROM or LDROM. |
kadonotakashi | 0:8fdf9a60065b | 81 | * | | |1 = Booting from Boot Loader. |
kadonotakashi | 0:8fdf9a60065b | 82 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 83 | * |[24] |INTEN |Interrupt Enable (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 84 | * | | |0 = ISP INT Disabled. |
kadonotakashi | 0:8fdf9a60065b | 85 | * | | |1 = ISP INT Enabled. |
kadonotakashi | 0:8fdf9a60065b | 86 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. Before use INT, user need to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time. |
kadonotakashi | 0:8fdf9a60065b | 87 | * @var FMC_T::ISPADDR |
kadonotakashi | 0:8fdf9a60065b | 88 | * Offset: 0x04 ISP Address Register |
kadonotakashi | 0:8fdf9a60065b | 89 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 90 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 91 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 92 | * |[31:0] |ISPADDR |ISP Address |
kadonotakashi | 0:8fdf9a60065b | 93 | * | | |The NuMicro M2351 series is equipped with embedded flash |
kadonotakashi | 0:8fdf9a60065b | 94 | * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation |
kadonotakashi | 0:8fdf9a60065b | 95 | * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. |
kadonotakashi | 0:8fdf9a60065b | 96 | * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 KBytes alignment is necessary for CRC32 checksum calculation. |
kadonotakashi | 0:8fdf9a60065b | 97 | * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte) |
kadonotakashi | 0:8fdf9a60065b | 98 | * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). |
kadonotakashi | 0:8fdf9a60065b | 99 | * @var FMC_T::ISPDAT |
kadonotakashi | 0:8fdf9a60065b | 100 | * Offset: 0x08 ISP Data Register |
kadonotakashi | 0:8fdf9a60065b | 101 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 102 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 103 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 104 | * |[31:0] |ISPDAT |ISP Data |
kadonotakashi | 0:8fdf9a60065b | 105 | * | | |Write data to this register before ISP program operation. |
kadonotakashi | 0:8fdf9a60065b | 106 | * | | |Read data from this register after ISP read operation. |
kadonotakashi | 0:8fdf9a60065b | 107 | * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff |
kadonotakashi | 0:8fdf9a60065b | 108 | * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 2 KBytes alignment |
kadonotakashi | 0:8fdf9a60065b | 109 | * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result |
kadonotakashi | 0:8fdf9a60065b | 110 | * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect |
kadonotakashi | 0:8fdf9a60065b | 111 | * | | |For XOM page erase function, , ISPDAT = 0x0055_aa03. |
kadonotakashi | 0:8fdf9a60065b | 112 | * @var FMC_T::ISPCMD |
kadonotakashi | 0:8fdf9a60065b | 113 | * Offset: 0x0C ISP Command Register |
kadonotakashi | 0:8fdf9a60065b | 114 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 115 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 116 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 117 | * |[6:0] |CMD |ISP Command |
kadonotakashi | 0:8fdf9a60065b | 118 | * | | |ISP command table is shown below: |
kadonotakashi | 0:8fdf9a60065b | 119 | * | | |0x00= FLASH Read. |
kadonotakashi | 0:8fdf9a60065b | 120 | * | | |0x04= Read Unique ID. |
kadonotakashi | 0:8fdf9a60065b | 121 | * | | |0x08= Read Flash All-One Result. |
kadonotakashi | 0:8fdf9a60065b | 122 | * | | |0x0B= Read Company ID. |
kadonotakashi | 0:8fdf9a60065b | 123 | * | | |0x0C= Read Device ID. |
kadonotakashi | 0:8fdf9a60065b | 124 | * | | |0x0D= Read Checksum. |
kadonotakashi | 0:8fdf9a60065b | 125 | * | | |0x21= FLASH 32-bit Program. |
kadonotakashi | 0:8fdf9a60065b | 126 | * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. |
kadonotakashi | 0:8fdf9a60065b | 127 | * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. |
kadonotakashi | 0:8fdf9a60065b | 128 | * | | |0x25= FLASH Block Erase Erase four pages alignment of APROM in BANK0 or BANK1.. |
kadonotakashi | 0:8fdf9a60065b | 129 | * | | |0x27= FLASH Multi-Word Program. |
kadonotakashi | 0:8fdf9a60065b | 130 | * | | |0x28= Run Flash All-One Verification. |
kadonotakashi | 0:8fdf9a60065b | 131 | * | | |0x2D= Run Checksum Calculation. |
kadonotakashi | 0:8fdf9a60065b | 132 | * | | |0x2E= Vector Remap. |
kadonotakashi | 0:8fdf9a60065b | 133 | * | | |0x40= FLASH 64-bit Read. |
kadonotakashi | 0:8fdf9a60065b | 134 | * | | |0x61= FLASH 64-bit Program. |
kadonotakashi | 0:8fdf9a60065b | 135 | * | | |The other commands are invalid. |
kadonotakashi | 0:8fdf9a60065b | 136 | * @var FMC_T::ISPTRG |
kadonotakashi | 0:8fdf9a60065b | 137 | * Offset: 0x10 ISP Trigger Control Register |
kadonotakashi | 0:8fdf9a60065b | 138 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 139 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 140 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 141 | * |[0] |ISPGO |ISP Start Trigger (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 142 | * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished |
kadonotakashi | 0:8fdf9a60065b | 143 | * | | |When ISPGO=1, the operation of accessing value from address FMC_BA+0x00 to FMC_BA+0x68 would halt CPU still ISPGO =0 |
kadonotakashi | 0:8fdf9a60065b | 144 | * | | |If user want to monitor whether ISP finish or not,user can access FMC_MPSTS[0] MPBUSY. |
kadonotakashi | 0:8fdf9a60065b | 145 | * | | |0 = ISP operation is finished. |
kadonotakashi | 0:8fdf9a60065b | 146 | * | | |1 = ISP is progressed. |
kadonotakashi | 0:8fdf9a60065b | 147 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 148 | * @var FMC_T::ISPSTS |
kadonotakashi | 0:8fdf9a60065b | 149 | * Offset: 0x40 ISP Status Register |
kadonotakashi | 0:8fdf9a60065b | 150 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 151 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 152 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 153 | * |[0] |ISPBUSY |ISP Busy Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 154 | * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. |
kadonotakashi | 0:8fdf9a60065b | 155 | * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). |
kadonotakashi | 0:8fdf9a60065b | 156 | * | | |0 = ISP operation is finished. |
kadonotakashi | 0:8fdf9a60065b | 157 | * | | |1 = ISP is progressed. |
kadonotakashi | 0:8fdf9a60065b | 158 | * |[2] |CBS |Boot Selection of CONFIG (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 159 | * | | |This bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. |
kadonotakashi | 0:8fdf9a60065b | 160 | * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1. |
kadonotakashi | 0:8fdf9a60065b | 161 | * | | |0 = LDROM with IAP mode. |
kadonotakashi | 0:8fdf9a60065b | 162 | * | | |1 = APROM with IAP mode. |
kadonotakashi | 0:8fdf9a60065b | 163 | * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 164 | * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened |
kadonotakashi | 0:8fdf9a60065b | 165 | * | | |0 = Booting from Boot Loader. |
kadonotakashi | 0:8fdf9a60065b | 166 | * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting) |
kadonotakashi | 0:8fdf9a60065b | 167 | * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 168 | * | | |This bit is set if flash access cycle auto-tuning function is disabled |
kadonotakashi | 0:8fdf9a60065b | 169 | * | | |The auto-tuning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. |
kadonotakashi | 0:8fdf9a60065b | 170 | * | | |0 = Flash access cycle auto-tuning is Enabled. |
kadonotakashi | 0:8fdf9a60065b | 171 | * | | |1 = Flash access cycle auto-tuning is Disabled. |
kadonotakashi | 0:8fdf9a60065b | 172 | * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 173 | * | | |This bit is set if data is mismatched at ISP programming verification |
kadonotakashi | 0:8fdf9a60065b | 174 | * | | |This bit is clear by performing ISP flash erase or ISP read CID operation |
kadonotakashi | 0:8fdf9a60065b | 175 | * | | |0 = Flash Program is success. |
kadonotakashi | 0:8fdf9a60065b | 176 | * | | |1 = Flash Program is fail. Program data is different with data in the flash memory |
kadonotakashi | 0:8fdf9a60065b | 177 | * |[6] |ISPFF |ISP Fail Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 178 | * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] if this bit is set. |
kadonotakashi | 0:8fdf9a60065b | 179 | * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: |
kadonotakashi | 0:8fdf9a60065b | 180 | * | | |(1) APROM writes to itself if APUEN is set to 0. |
kadonotakashi | 0:8fdf9a60065b | 181 | * | | |(2) LDROM writes to itself if LDUEN is set to 0. |
kadonotakashi | 0:8fdf9a60065b | 182 | * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. |
kadonotakashi | 0:8fdf9a60065b | 183 | * | | |(4) Page Erase command at LOCK mode with ICE connection |
kadonotakashi | 0:8fdf9a60065b | 184 | * | | |(5) Erase or Program command at brown-out detected |
kadonotakashi | 0:8fdf9a60065b | 185 | * | | |(6) Destination address is illegal, such as over an available range. |
kadonotakashi | 0:8fdf9a60065b | 186 | * | | |(7) Invalid ISP commands |
kadonotakashi | 0:8fdf9a60065b | 187 | * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1 |
kadonotakashi | 0:8fdf9a60065b | 188 | * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1 |
kadonotakashi | 0:8fdf9a60065b | 189 | * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1 |
kadonotakashi | 0:8fdf9a60065b | 190 | * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0. |
kadonotakashi | 0:8fdf9a60065b | 191 | * | | |(12) Read any content of boot loader with ICE connection |
kadonotakashi | 0:8fdf9a60065b | 192 | * | | |(13) The address of block erase and bank erase is not in APROM |
kadonotakashi | 0:8fdf9a60065b | 193 | * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command |
kadonotakashi | 0:8fdf9a60065b | 194 | * | | |(15) The wrong setting of page erase ISP CMD in XOM |
kadonotakashi | 0:8fdf9a60065b | 195 | * | | |(16) Violate XOM setting one time protection |
kadonotakashi | 0:8fdf9a60065b | 196 | * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page |
kadonotakashi | 0:8fdf9a60065b | 197 | * | | |(18) Mass erase when MERASE (CFG0[13]) is disable |
kadonotakashi | 0:8fdf9a60065b | 198 | * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP |
kadonotakashi | 0:8fdf9a60065b | 199 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 200 | * |[7] |ALLONE |Flash All-one Verification Flag |
kadonotakashi | 0:8fdf9a60065b | 201 | * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete; this bit also can be clear by writing 1 |
kadonotakashi | 0:8fdf9a60065b | 202 | * | | |0 = All of flash bits are 1 after Run Flash All-One Verification complete. |
kadonotakashi | 0:8fdf9a60065b | 203 | * | | |1 = Flash bits are not all 1 after Run Flash All-One Verification complete. |
kadonotakashi | 0:8fdf9a60065b | 204 | * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 205 | * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF} |
kadonotakashi | 0:8fdf9a60065b | 206 | * |[24] |INTFLAG |Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 207 | * | | |0 = ISP is not finish. |
kadonotakashi | 0:8fdf9a60065b | 208 | * | | |1 = ISP done or ISPFF set. |
kadonotakashi | 0:8fdf9a60065b | 209 | * @var FMC_T::CYCCTL |
kadonotakashi | 0:8fdf9a60065b | 210 | * Offset: 0x4C Flash Access Cycle Control Register |
kadonotakashi | 0:8fdf9a60065b | 211 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 212 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 213 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 214 | * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 215 | * | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1) |
kadonotakashi | 0:8fdf9a60065b | 216 | * | | |0000 = CPU access with zero wait cycle ; flash access cycle is 1;. |
kadonotakashi | 0:8fdf9a60065b | 217 | * | | |The HCLK working frequency range is <27MHz; Cache is disabled by hardware. |
kadonotakashi | 0:8fdf9a60065b | 218 | * | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;. |
kadonotakashi | 0:8fdf9a60065b | 219 | * | | |The HCLK working frequency range range is<27MHz |
kadonotakashi | 0:8fdf9a60065b | 220 | * | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;. |
kadonotakashi | 0:8fdf9a60065b | 221 | * | | | The optimized HCLK working frequency range is 27~54 MHz |
kadonotakashi | 0:8fdf9a60065b | 222 | * | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;. |
kadonotakashi | 0:8fdf9a60065b | 223 | * | | |The optimized HCLK working frequency range is 54~81MHz |
kadonotakashi | 0:8fdf9a60065b | 224 | * | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;. |
kadonotakashi | 0:8fdf9a60065b | 225 | * | | | The optimized HCLK working frequency range is81~108MHz |
kadonotakashi | 0:8fdf9a60065b | 226 | * | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;. |
kadonotakashi | 0:8fdf9a60065b | 227 | * | | |The optimized HCLK working frequency range is 108~135MHz |
kadonotakashi | 0:8fdf9a60065b | 228 | * | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;. |
kadonotakashi | 0:8fdf9a60065b | 229 | * | | | The optimized HCLK working frequency range is 135~162MHz |
kadonotakashi | 0:8fdf9a60065b | 230 | * | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;. |
kadonotakashi | 0:8fdf9a60065b | 231 | * | | | The optimized HCLK working frequency range is 162~192MHz |
kadonotakashi | 0:8fdf9a60065b | 232 | * | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;. |
kadonotakashi | 0:8fdf9a60065b | 233 | * | | |The optimized HCLK working frequency range is >192MHz |
kadonotakashi | 0:8fdf9a60065b | 234 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 235 | * |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 236 | * | | |Set this bit to disable flash access cycle auto-tuning function |
kadonotakashi | 0:8fdf9a60065b | 237 | * | | |0 = Flash access cycle auto-tuning is enabled. |
kadonotakashi | 0:8fdf9a60065b | 238 | * | | |1 = Flash access cycle auto-tuning is disabled. |
kadonotakashi | 0:8fdf9a60065b | 239 | * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 240 | * @var FMC_T::KPKEY0 |
kadonotakashi | 0:8fdf9a60065b | 241 | * Offset: 0x50 KPROM KEY0 Data Register |
kadonotakashi | 0:8fdf9a60065b | 242 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 243 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 244 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 245 | * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only) |
kadonotakashi | 0:8fdf9a60065b | 246 | * | | |Write KPKEY0 data to this register before KEY Comparison operation. |
kadonotakashi | 0:8fdf9a60065b | 247 | * @var FMC_T::KPKEY1 |
kadonotakashi | 0:8fdf9a60065b | 248 | * Offset: 0x54 KPROM KEY1 Data Register |
kadonotakashi | 0:8fdf9a60065b | 249 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 250 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 251 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 252 | * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only) |
kadonotakashi | 0:8fdf9a60065b | 253 | * | | |Write KPKEY1 data to this register before KEY Comparison operation. |
kadonotakashi | 0:8fdf9a60065b | 254 | * @var FMC_T::KPKEY2 |
kadonotakashi | 0:8fdf9a60065b | 255 | * Offset: 0x58 KPROM KEY2 Data Register |
kadonotakashi | 0:8fdf9a60065b | 256 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 257 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 258 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 259 | * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only) |
kadonotakashi | 0:8fdf9a60065b | 260 | * | | |Write KPKEY2 data to this register before KEY Comparison operation. |
kadonotakashi | 0:8fdf9a60065b | 261 | * @var FMC_T::KPKEYTRG |
kadonotakashi | 0:8fdf9a60065b | 262 | * Offset: 0x5C KPROM KEY Comparison Trigger Control Register |
kadonotakashi | 0:8fdf9a60065b | 263 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 264 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 265 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 266 | * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection) |
kadonotakashi | 0:8fdf9a60065b | 267 | * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished |
kadonotakashi | 0:8fdf9a60065b | 268 | * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0. |
kadonotakashi | 0:8fdf9a60065b | 269 | * | | |0 = KEY comparison operation is finished. |
kadonotakashi | 0:8fdf9a60065b | 270 | * | | |1 = KEY comparison is progressed. |
kadonotakashi | 0:8fdf9a60065b | 271 | * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 272 | * |[1] |TCEN |Timeout Counting Enable (Write Protection) |
kadonotakashi | 0:8fdf9a60065b | 273 | * | | |0 = Timeout counting is disabled. |
kadonotakashi | 0:8fdf9a60065b | 274 | * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish. |
kadonotakashi | 0:8fdf9a60065b | 275 | * | | |10 minutes is at least for timeout, and average is about 20 minutes. |
kadonotakashi | 0:8fdf9a60065b | 276 | * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 277 | * @var FMC_T::KPKEYSTS |
kadonotakashi | 0:8fdf9a60065b | 278 | * Offset: 0x60 KPROM KEY Comparison Status Register |
kadonotakashi | 0:8fdf9a60065b | 279 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 280 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 281 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 282 | * |[0] |KEYBUSY |KEY Comparison Busy (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 283 | * | | |0 = KEY comparison is finished. |
kadonotakashi | 0:8fdf9a60065b | 284 | * | | |1 = KEY comparison is busy. |
kadonotakashi | 0:8fdf9a60065b | 285 | * |[1] |KEYLOCK |KEY LOCK Flag |
kadonotakashi | 0:8fdf9a60065b | 286 | * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection |
kadonotakashi | 0:8fdf9a60065b | 287 | * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0 |
kadonotakashi | 0:8fdf9a60065b | 288 | * | | |This bit also can be set to 1 while |
kadonotakashi | 0:8fdf9a60065b | 289 | * | | |l CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or |
kadonotakashi | 0:8fdf9a60065b | 290 | * | | |l KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or |
kadonotakashi | 0:8fdf9a60065b | 291 | * | | |l KEYENROM is programmed a non-0x5a value or |
kadonotakashi | 0:8fdf9a60065b | 292 | * | | |l Timeout event or |
kadonotakashi | 0:8fdf9a60065b | 293 | * | | |l FORBID(FMC_KPKEYSTS[3]) is 1 |
kadonotakashi | 0:8fdf9a60065b | 294 | * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection. |
kadonotakashi | 0:8fdf9a60065b | 295 | * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection. |
kadonotakashi | 0:8fdf9a60065b | 296 | * | | |CONFIG write protect is depended on CFGFLAG |
kadonotakashi | 0:8fdf9a60065b | 297 | * |[2] |KEYMATCH |KEY Match Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 298 | * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched |
kadonotakashi | 0:8fdf9a60065b | 299 | * | | |This bit is also cleared to 0 while |
kadonotakashi | 0:8fdf9a60065b | 300 | * | | |l CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or |
kadonotakashi | 0:8fdf9a60065b | 301 | * | | |l Timeout event or |
kadonotakashi | 0:8fdf9a60065b | 302 | * | | |l KPROM is erased or |
kadonotakashi | 0:8fdf9a60065b | 303 | * | | |l KEYENROM is programmed to a non-0x5a value. |
kadonotakashi | 0:8fdf9a60065b | 304 | * | | |l Chip is in power down mode. |
kadonotakashi | 0:8fdf9a60065b | 305 | * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting. |
kadonotakashi | 0:8fdf9a60065b | 306 | * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting. |
kadonotakashi | 0:8fdf9a60065b | 307 | * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 308 | * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]). |
kadonotakashi | 0:8fdf9a60065b | 309 | * | | |0 = KEY comparison is not forbidden. |
kadonotakashi | 0:8fdf9a60065b | 310 | * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger. |
kadonotakashi | 0:8fdf9a60065b | 311 | * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 312 | * | | |This bit is set while the KEYENROM [7:0] is not 0x5a at power-on or reset |
kadonotakashi | 0:8fdf9a60065b | 313 | * | | |This bit is cleared to 0 by hardware while KPROM is erased |
kadonotakashi | 0:8fdf9a60065b | 314 | * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0x5a value. |
kadonotakashi | 0:8fdf9a60065b | 315 | * | | |0 = Security Key protection is disabled. |
kadonotakashi | 0:8fdf9a60065b | 316 | * | | |1 = Security Key protection is enabled. |
kadonotakashi | 0:8fdf9a60065b | 317 | * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 318 | * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset |
kadonotakashi | 0:8fdf9a60065b | 319 | * | | |This bit is cleared to 0 by hardware while KPROM is erased |
kadonotakashi | 0:8fdf9a60065b | 320 | * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. |
kadonotakashi | 0:8fdf9a60065b | 321 | * | | |0 = CONFIG write-protection is disabled. |
kadonotakashi | 0:8fdf9a60065b | 322 | * | | |1 = CONFIG write-protection is enabled. |
kadonotakashi | 0:8fdf9a60065b | 323 | * |[8] |SBKPBUSY |Secure Boot Key Programming BUSY (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 324 | * | | |This bit is set to 1 while secure boot key program function is running |
kadonotakashi | 0:8fdf9a60065b | 325 | * | | |This bit is cleared to 0 while secure boot key key program function had been done. |
kadonotakashi | 0:8fdf9a60065b | 326 | * | | |0 = Secure boot key program function is done. |
kadonotakashi | 0:8fdf9a60065b | 327 | * | | |1 = Secure boot key program function is busy. |
kadonotakashi | 0:8fdf9a60065b | 328 | * |[9] |SBKPFLAG |Secure Boot Key Programming Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 329 | * | | |This bit is set to 1 while secure boot key program function fails |
kadonotakashi | 0:8fdf9a60065b | 330 | * | | |This bit is cleared to 0 while secure boot key had been programmed into flash memory. |
kadonotakashi | 0:8fdf9a60065b | 331 | * | | |0 = Secure boot key program function is successful. |
kadonotakashi | 0:8fdf9a60065b | 332 | * | | |1 = Secure boot key program function fails. |
kadonotakashi | 0:8fdf9a60065b | 333 | * @var FMC_T::KPKEYCNT |
kadonotakashi | 0:8fdf9a60065b | 334 | * Offset: 0x64 KPROM KEY-Unmatched Counting Register |
kadonotakashi | 0:8fdf9a60065b | 335 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 336 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 337 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 338 | * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 339 | * | | |KPKECNT is increased when entry keys is wrong in Security Key protection |
kadonotakashi | 0:8fdf9a60065b | 340 | * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on. |
kadonotakashi | 0:8fdf9a60065b | 341 | * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 342 | * | | |KPKEMAX is the maximum error key entry number at each power-on |
kadonotakashi | 0:8fdf9a60065b | 343 | * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated |
kadonotakashi | 0:8fdf9a60065b | 344 | * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting |
kadonotakashi | 0:8fdf9a60065b | 345 | * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX. |
kadonotakashi | 0:8fdf9a60065b | 346 | * @var FMC_T::KPCNT |
kadonotakashi | 0:8fdf9a60065b | 347 | * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register |
kadonotakashi | 0:8fdf9a60065b | 348 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 349 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 350 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 351 | * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only) |
kadonotakashi | 0:8fdf9a60065b | 352 | * | | |KPCNT is the power-on counting for error key entry in Security Key protection |
kadonotakashi | 0:8fdf9a60065b | 353 | * | | |KPCNT is cleared to 0 if key comparison is matched. |
kadonotakashi | 0:8fdf9a60065b | 354 | * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 355 | * | | |KPMAX is the power-on maximum number for error key entry |
kadonotakashi | 0:8fdf9a60065b | 356 | * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated |
kadonotakashi | 0:8fdf9a60065b | 357 | * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting |
kadonotakashi | 0:8fdf9a60065b | 358 | * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX |
kadonotakashi | 0:8fdf9a60065b | 359 | * @var FMC_T::MPDAT0 |
kadonotakashi | 0:8fdf9a60065b | 360 | * Offset: 0x80 ISP Data0 Register |
kadonotakashi | 0:8fdf9a60065b | 361 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 362 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 363 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 364 | * |[31:0] |ISPDAT0 |ISP Data 0 |
kadonotakashi | 0:8fdf9a60065b | 365 | * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data |
kadonotakashi | 0:8fdf9a60065b | 366 | * @var FMC_T::MPDAT1 |
kadonotakashi | 0:8fdf9a60065b | 367 | * Offset: 0x84 ISP Data1 Register |
kadonotakashi | 0:8fdf9a60065b | 368 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 369 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 370 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 371 | * |[31:0] |ISPDAT1 |ISP Data 1 |
kadonotakashi | 0:8fdf9a60065b | 372 | * | | |This register is the second 32-bit data for 64-bit/multi-word programming. |
kadonotakashi | 0:8fdf9a60065b | 373 | * @var FMC_T::MPDAT2 |
kadonotakashi | 0:8fdf9a60065b | 374 | * Offset: 0x88 ISP Data2 Register |
kadonotakashi | 0:8fdf9a60065b | 375 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 376 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 377 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 378 | * |[31:0] |ISPDAT2 |ISP Data 2 |
kadonotakashi | 0:8fdf9a60065b | 379 | * | | |This register is the third 32-bit data for multi-word programming. |
kadonotakashi | 0:8fdf9a60065b | 380 | * @var FMC_T::MPDAT3 |
kadonotakashi | 0:8fdf9a60065b | 381 | * Offset: 0x8C ISP Data3 Register |
kadonotakashi | 0:8fdf9a60065b | 382 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 383 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 384 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 385 | * |[31:0] |ISPDAT3 |ISP Data 3 |
kadonotakashi | 0:8fdf9a60065b | 386 | * | | |This register is the fourth 32-bit data for multi-word programming. |
kadonotakashi | 0:8fdf9a60065b | 387 | * @var FMC_T::MPSTS |
kadonotakashi | 0:8fdf9a60065b | 388 | * Offset: 0xC0 ISP Multi-Program Status Register |
kadonotakashi | 0:8fdf9a60065b | 389 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 390 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 391 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 392 | * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 393 | * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. |
kadonotakashi | 0:8fdf9a60065b | 394 | * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). |
kadonotakashi | 0:8fdf9a60065b | 395 | * | | |0 = ISP Multi-Word program operation is finished. |
kadonotakashi | 0:8fdf9a60065b | 396 | * | | |1 = ISP Multi-Word program operation is progressed. |
kadonotakashi | 0:8fdf9a60065b | 397 | * |[1] |PPGO |ISP Multi-program Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 398 | * | | |0 = ISP multi-word program operation is not active. |
kadonotakashi | 0:8fdf9a60065b | 399 | * | | |1 = ISP multi-word program operation is in progress. |
kadonotakashi | 0:8fdf9a60065b | 400 | * |[2] |ISPFF |ISP Fail Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 401 | * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] |
kadonotakashi | 0:8fdf9a60065b | 402 | * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: |
kadonotakashi | 0:8fdf9a60065b | 403 | * | | |(1) APROM writes to itself if APUEN is set to 0. |
kadonotakashi | 0:8fdf9a60065b | 404 | * | | |(2) LDROM writes to itself if LDUEN is set to 0. |
kadonotakashi | 0:8fdf9a60065b | 405 | * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. |
kadonotakashi | 0:8fdf9a60065b | 406 | * | | |(4) Page Erase command at LOCK mode with ICE connection |
kadonotakashi | 0:8fdf9a60065b | 407 | * | | |(5) Erase or Program command at brown-out detected |
kadonotakashi | 0:8fdf9a60065b | 408 | * | | |(6) Destination address is illegal, such as over an available range. |
kadonotakashi | 0:8fdf9a60065b | 409 | * | | |(7) Invalid ISP commands |
kadonotakashi | 0:8fdf9a60065b | 410 | * |[4] |D0 |ISP DATA 0 Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 411 | * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 412 | * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 413 | * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 414 | * |[5] |D1 |ISP DATA 1 Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 415 | * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 416 | * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 417 | * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 418 | * |[6] |D2 |ISP DATA 2 Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 419 | * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 420 | * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 421 | * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 422 | * |[7] |D3 |ISP DATA 3 Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 423 | * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 424 | * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 425 | * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete. |
kadonotakashi | 0:8fdf9a60065b | 426 | * @var FMC_T::MPADDR |
kadonotakashi | 0:8fdf9a60065b | 427 | * Offset: 0xC4 ISP Multi-Program Address Register |
kadonotakashi | 0:8fdf9a60065b | 428 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 429 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 430 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 431 | * |[31:0] |MPADDR |ISP Multi-word Program Address |
kadonotakashi | 0:8fdf9a60065b | 432 | * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. |
kadonotakashi | 0:8fdf9a60065b | 433 | * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. |
kadonotakashi | 0:8fdf9a60065b | 434 | * @var FMC_T::XOMR0STS |
kadonotakashi | 0:8fdf9a60065b | 435 | * Offset: 0xD0 XOM Region 0 Status Register |
kadonotakashi | 0:8fdf9a60065b | 436 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 437 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 438 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 439 | * |[7:0] |SIZE |XOM Region 0 Size (Page-aligned) |
kadonotakashi | 0:8fdf9a60065b | 440 | * | | |SIZE is the page number of XOM Region 0. |
kadonotakashi | 0:8fdf9a60065b | 441 | * |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned) |
kadonotakashi | 0:8fdf9a60065b | 442 | * | | |BASE is the base address of XOM Region 0. |
kadonotakashi | 0:8fdf9a60065b | 443 | * @var FMC_T::XOMR1STS |
kadonotakashi | 0:8fdf9a60065b | 444 | * Offset: 0xD4 XOM Region 1 Status Register |
kadonotakashi | 0:8fdf9a60065b | 445 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 446 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 447 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 448 | * |[7:0] |SIZE |XOM Region 1 Size (Page-aligned) |
kadonotakashi | 0:8fdf9a60065b | 449 | * | | |SIZE is the page number of XOM Region 1. |
kadonotakashi | 0:8fdf9a60065b | 450 | * |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned) |
kadonotakashi | 0:8fdf9a60065b | 451 | * | | |BASE is the base address of XOM Region 1. |
kadonotakashi | 0:8fdf9a60065b | 452 | * @var FMC_T::XOMR2STS |
kadonotakashi | 0:8fdf9a60065b | 453 | * Offset: 0xD8 XOM Region 2 Status Register |
kadonotakashi | 0:8fdf9a60065b | 454 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 455 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 456 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 457 | * |[7:0] |SIZE |XOM Region 2 Size (Page-aligned) |
kadonotakashi | 0:8fdf9a60065b | 458 | * | | |SIZE is the page number of XOM Region 2. |
kadonotakashi | 0:8fdf9a60065b | 459 | * |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned) |
kadonotakashi | 0:8fdf9a60065b | 460 | * | | |BASE is the base address of XOM Region 2. |
kadonotakashi | 0:8fdf9a60065b | 461 | * @var FMC_T::XOMR3STS |
kadonotakashi | 0:8fdf9a60065b | 462 | * Offset: 0xDC XOM Region 3 Status Register |
kadonotakashi | 0:8fdf9a60065b | 463 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 464 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 465 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 466 | * |[7:0] |SIZE |XOM Region 3 Size (Page-aligned) |
kadonotakashi | 0:8fdf9a60065b | 467 | * | | |SIZE is the page number of XOM Region 3. |
kadonotakashi | 0:8fdf9a60065b | 468 | * |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned) |
kadonotakashi | 0:8fdf9a60065b | 469 | * | | |BASE is the base address of XOM Region 3. |
kadonotakashi | 0:8fdf9a60065b | 470 | * @var FMC_T::XOMSTS |
kadonotakashi | 0:8fdf9a60065b | 471 | * Offset: 0xE0 XOM Status Register |
kadonotakashi | 0:8fdf9a60065b | 472 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 473 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 474 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 475 | * |[0] |XOMR0ON |XOM Region 0 On |
kadonotakashi | 0:8fdf9a60065b | 476 | * | | |XOM Region 0 active status. |
kadonotakashi | 0:8fdf9a60065b | 477 | * | | |0 = No active. |
kadonotakashi | 0:8fdf9a60065b | 478 | * | | |1 = XOM region 0 is active. |
kadonotakashi | 0:8fdf9a60065b | 479 | * |[1] |XOMR1ON |XOM Region 1 On |
kadonotakashi | 0:8fdf9a60065b | 480 | * | | |XOM Region 1 active status. |
kadonotakashi | 0:8fdf9a60065b | 481 | * | | |0 = No active. |
kadonotakashi | 0:8fdf9a60065b | 482 | * | | |1 = XOM region 1 is active. |
kadonotakashi | 0:8fdf9a60065b | 483 | * |[2] |XOMR2ON |XOM Region 2 On |
kadonotakashi | 0:8fdf9a60065b | 484 | * | | |XOM Region 2 active status. |
kadonotakashi | 0:8fdf9a60065b | 485 | * | | |0 = No active. |
kadonotakashi | 0:8fdf9a60065b | 486 | * | | |1 = XOM region 2 is active. |
kadonotakashi | 0:8fdf9a60065b | 487 | * |[3] |XOMR3ON |XOM Region 3 On |
kadonotakashi | 0:8fdf9a60065b | 488 | * | | |XOM Region 3 active status. |
kadonotakashi | 0:8fdf9a60065b | 489 | * | | |0 = No active. |
kadonotakashi | 0:8fdf9a60065b | 490 | * | | |1 = XOM region 3 is active. |
kadonotakashi | 0:8fdf9a60065b | 491 | * |[4] |XOMPEF |XOM Page Erase Function Fail |
kadonotakashi | 0:8fdf9a60065b | 492 | * | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again. |
kadonotakashi | 0:8fdf9a60065b | 493 | * | | |0 = Success. |
kadonotakashi | 0:8fdf9a60065b | 494 | * | | |1 = Fail. |
kadonotakashi | 0:8fdf9a60065b | 495 | */ |
kadonotakashi | 0:8fdf9a60065b | 496 | __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 497 | __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ |
kadonotakashi | 0:8fdf9a60065b | 498 | __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ |
kadonotakashi | 0:8fdf9a60065b | 499 | __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ |
kadonotakashi | 0:8fdf9a60065b | 500 | __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 501 | __I uint32_t RESERVE0[11]; |
kadonotakashi | 0:8fdf9a60065b | 502 | __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 503 | __I uint32_t RESERVE1[2]; |
kadonotakashi | 0:8fdf9a60065b | 504 | __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 505 | __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */ |
kadonotakashi | 0:8fdf9a60065b | 506 | __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */ |
kadonotakashi | 0:8fdf9a60065b | 507 | __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */ |
kadonotakashi | 0:8fdf9a60065b | 508 | __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 509 | __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 510 | __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */ |
kadonotakashi | 0:8fdf9a60065b | 511 | __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */ |
kadonotakashi | 0:8fdf9a60065b | 512 | __I uint32_t RESERVE2[5]; |
kadonotakashi | 0:8fdf9a60065b | 513 | __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ |
kadonotakashi | 0:8fdf9a60065b | 514 | __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ |
kadonotakashi | 0:8fdf9a60065b | 515 | __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ |
kadonotakashi | 0:8fdf9a60065b | 516 | __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ |
kadonotakashi | 0:8fdf9a60065b | 517 | __I uint32_t RESERVE3[12]; |
kadonotakashi | 0:8fdf9a60065b | 518 | __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 519 | __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ |
kadonotakashi | 0:8fdf9a60065b | 520 | __I uint32_t RESERVE4[2]; |
kadonotakashi | 0:8fdf9a60065b | 521 | __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 522 | __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 523 | __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 524 | __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 525 | __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 526 | |
kadonotakashi | 0:8fdf9a60065b | 527 | } FMC_T; |
kadonotakashi | 0:8fdf9a60065b | 528 | |
kadonotakashi | 0:8fdf9a60065b | 529 | /** |
kadonotakashi | 0:8fdf9a60065b | 530 | @addtogroup FMC_CONST FMC Bit Field Definition |
kadonotakashi | 0:8fdf9a60065b | 531 | Constant Definitions for FMC Controller |
kadonotakashi | 0:8fdf9a60065b | 532 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 533 | |
kadonotakashi | 0:8fdf9a60065b | 534 | #define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 535 | #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 536 | |
kadonotakashi | 0:8fdf9a60065b | 537 | #define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ |
kadonotakashi | 0:8fdf9a60065b | 538 | #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 539 | |
kadonotakashi | 0:8fdf9a60065b | 540 | #define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 541 | #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 542 | |
kadonotakashi | 0:8fdf9a60065b | 543 | #define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 544 | #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 545 | |
kadonotakashi | 0:8fdf9a60065b | 546 | #define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 547 | #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 548 | |
kadonotakashi | 0:8fdf9a60065b | 549 | #define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ |
kadonotakashi | 0:8fdf9a60065b | 550 | #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 551 | |
kadonotakashi | 0:8fdf9a60065b | 552 | #define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */ |
kadonotakashi | 0:8fdf9a60065b | 553 | #define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 554 | |
kadonotakashi | 0:8fdf9a60065b | 555 | #define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 556 | #define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 557 | |
kadonotakashi | 0:8fdf9a60065b | 558 | #define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ |
kadonotakashi | 0:8fdf9a60065b | 559 | #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 560 | |
kadonotakashi | 0:8fdf9a60065b | 561 | #define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 562 | #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 563 | |
kadonotakashi | 0:8fdf9a60065b | 564 | #define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ |
kadonotakashi | 0:8fdf9a60065b | 565 | #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 566 | |
kadonotakashi | 0:8fdf9a60065b | 567 | #define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ |
kadonotakashi | 0:8fdf9a60065b | 568 | #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ |
kadonotakashi | 0:8fdf9a60065b | 569 | |
kadonotakashi | 0:8fdf9a60065b | 570 | #define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ |
kadonotakashi | 0:8fdf9a60065b | 571 | #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 572 | |
kadonotakashi | 0:8fdf9a60065b | 573 | #define FMC_ISPSTS_CBS_Pos (2) /*!< FMC_T::ISPSTS: CBS Position */ |
kadonotakashi | 0:8fdf9a60065b | 574 | #define FMC_ISPSTS_CBS_Msk (0x1ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 575 | |
kadonotakashi | 0:8fdf9a60065b | 576 | #define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */ |
kadonotakashi | 0:8fdf9a60065b | 577 | #define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 578 | |
kadonotakashi | 0:8fdf9a60065b | 579 | #define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */ |
kadonotakashi | 0:8fdf9a60065b | 580 | #define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 581 | |
kadonotakashi | 0:8fdf9a60065b | 582 | #define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ |
kadonotakashi | 0:8fdf9a60065b | 583 | #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 584 | |
kadonotakashi | 0:8fdf9a60065b | 585 | #define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ |
kadonotakashi | 0:8fdf9a60065b | 586 | #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 587 | |
kadonotakashi | 0:8fdf9a60065b | 588 | #define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ |
kadonotakashi | 0:8fdf9a60065b | 589 | #define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 590 | |
kadonotakashi | 0:8fdf9a60065b | 591 | #define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ |
kadonotakashi | 0:8fdf9a60065b | 592 | #define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 593 | |
kadonotakashi | 0:8fdf9a60065b | 594 | #define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */ |
kadonotakashi | 0:8fdf9a60065b | 595 | #define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */ |
kadonotakashi | 0:8fdf9a60065b | 596 | |
kadonotakashi | 0:8fdf9a60065b | 597 | #define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ |
kadonotakashi | 0:8fdf9a60065b | 598 | #define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 599 | |
kadonotakashi | 0:8fdf9a60065b | 600 | #define FMC_CYCCTL_FADIS_Pos (8) /*!< FMC_T::CYCCTL: FADIS Position */ |
kadonotakashi | 0:8fdf9a60065b | 601 | #define FMC_CYCCTL_FADIS_Msk (0x1ul << FMC_CYCCTL_FADIS_Pos) /*!< FMC_T::CYCCTL: FADIS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 602 | |
kadonotakashi | 0:8fdf9a60065b | 603 | #define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 604 | #define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 605 | |
kadonotakashi | 0:8fdf9a60065b | 606 | #define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 607 | #define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 608 | |
kadonotakashi | 0:8fdf9a60065b | 609 | #define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 610 | #define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 611 | |
kadonotakashi | 0:8fdf9a60065b | 612 | #define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */ |
kadonotakashi | 0:8fdf9a60065b | 613 | #define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */ |
kadonotakashi | 0:8fdf9a60065b | 614 | |
kadonotakashi | 0:8fdf9a60065b | 615 | #define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 616 | #define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 617 | |
kadonotakashi | 0:8fdf9a60065b | 618 | #define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */ |
kadonotakashi | 0:8fdf9a60065b | 619 | #define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 620 | |
kadonotakashi | 0:8fdf9a60065b | 621 | #define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */ |
kadonotakashi | 0:8fdf9a60065b | 622 | #define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */ |
kadonotakashi | 0:8fdf9a60065b | 623 | |
kadonotakashi | 0:8fdf9a60065b | 624 | #define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */ |
kadonotakashi | 0:8fdf9a60065b | 625 | #define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */ |
kadonotakashi | 0:8fdf9a60065b | 626 | |
kadonotakashi | 0:8fdf9a60065b | 627 | #define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */ |
kadonotakashi | 0:8fdf9a60065b | 628 | #define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */ |
kadonotakashi | 0:8fdf9a60065b | 629 | |
kadonotakashi | 0:8fdf9a60065b | 630 | #define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */ |
kadonotakashi | 0:8fdf9a60065b | 631 | #define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */ |
kadonotakashi | 0:8fdf9a60065b | 632 | |
kadonotakashi | 0:8fdf9a60065b | 633 | #define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */ |
kadonotakashi | 0:8fdf9a60065b | 634 | #define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */ |
kadonotakashi | 0:8fdf9a60065b | 635 | |
kadonotakashi | 0:8fdf9a60065b | 636 | #define FMC_KPKEYSTS_SBKPBUSY_Pos (8) /*!< FMC_T::KPKEYSTS: SBKPBUSY Position */ |
kadonotakashi | 0:8fdf9a60065b | 637 | #define FMC_KPKEYSTS_SBKPBUSY_Msk (0x1ul << FMC_KPKEYSTS_SBKPBUSY_Pos) /*!< FMC_T::KPKEYSTS: SBKPBUSY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 638 | |
kadonotakashi | 0:8fdf9a60065b | 639 | #define FMC_KPKEYSTS_SBKPFLAG_Pos (9) /*!< FMC_T::KPKEYSTS: SBKPFLAG Position */ |
kadonotakashi | 0:8fdf9a60065b | 640 | #define FMC_KPKEYSTS_SBKPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SBKPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SBKPFLAG Mask */ |
kadonotakashi | 0:8fdf9a60065b | 641 | |
kadonotakashi | 0:8fdf9a60065b | 642 | #define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 643 | #define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 644 | |
kadonotakashi | 0:8fdf9a60065b | 645 | #define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */ |
kadonotakashi | 0:8fdf9a60065b | 646 | #define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */ |
kadonotakashi | 0:8fdf9a60065b | 647 | |
kadonotakashi | 0:8fdf9a60065b | 648 | #define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 649 | #define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 650 | |
kadonotakashi | 0:8fdf9a60065b | 651 | #define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */ |
kadonotakashi | 0:8fdf9a60065b | 652 | #define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */ |
kadonotakashi | 0:8fdf9a60065b | 653 | |
kadonotakashi | 0:8fdf9a60065b | 654 | #define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 655 | #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 656 | |
kadonotakashi | 0:8fdf9a60065b | 657 | #define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 658 | #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 659 | |
kadonotakashi | 0:8fdf9a60065b | 660 | #define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 661 | #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 662 | |
kadonotakashi | 0:8fdf9a60065b | 663 | #define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 664 | #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 665 | |
kadonotakashi | 0:8fdf9a60065b | 666 | #define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ |
kadonotakashi | 0:8fdf9a60065b | 667 | #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 668 | |
kadonotakashi | 0:8fdf9a60065b | 669 | #define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ |
kadonotakashi | 0:8fdf9a60065b | 670 | #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ |
kadonotakashi | 0:8fdf9a60065b | 671 | |
kadonotakashi | 0:8fdf9a60065b | 672 | #define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ |
kadonotakashi | 0:8fdf9a60065b | 673 | #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 674 | |
kadonotakashi | 0:8fdf9a60065b | 675 | #define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 676 | #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 677 | |
kadonotakashi | 0:8fdf9a60065b | 678 | #define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 679 | #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 680 | |
kadonotakashi | 0:8fdf9a60065b | 681 | #define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 682 | #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 683 | |
kadonotakashi | 0:8fdf9a60065b | 684 | #define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 685 | #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 686 | |
kadonotakashi | 0:8fdf9a60065b | 687 | #define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ |
kadonotakashi | 0:8fdf9a60065b | 688 | #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 689 | |
kadonotakashi | 0:8fdf9a60065b | 690 | #define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */ |
kadonotakashi | 0:8fdf9a60065b | 691 | #define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 692 | |
kadonotakashi | 0:8fdf9a60065b | 693 | #define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */ |
kadonotakashi | 0:8fdf9a60065b | 694 | #define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 695 | |
kadonotakashi | 0:8fdf9a60065b | 696 | #define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */ |
kadonotakashi | 0:8fdf9a60065b | 697 | #define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 698 | |
kadonotakashi | 0:8fdf9a60065b | 699 | #define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */ |
kadonotakashi | 0:8fdf9a60065b | 700 | #define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 701 | |
kadonotakashi | 0:8fdf9a60065b | 702 | #define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */ |
kadonotakashi | 0:8fdf9a60065b | 703 | #define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 704 | |
kadonotakashi | 0:8fdf9a60065b | 705 | #define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */ |
kadonotakashi | 0:8fdf9a60065b | 706 | #define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOMR2STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 707 | |
kadonotakashi | 0:8fdf9a60065b | 708 | #define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */ |
kadonotakashi | 0:8fdf9a60065b | 709 | #define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 710 | |
kadonotakashi | 0:8fdf9a60065b | 711 | #define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */ |
kadonotakashi | 0:8fdf9a60065b | 712 | #define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 713 | |
kadonotakashi | 0:8fdf9a60065b | 714 | #define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */ |
kadonotakashi | 0:8fdf9a60065b | 715 | #define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 716 | |
kadonotakashi | 0:8fdf9a60065b | 717 | #define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */ |
kadonotakashi | 0:8fdf9a60065b | 718 | #define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 719 | |
kadonotakashi | 0:8fdf9a60065b | 720 | #define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */ |
kadonotakashi | 0:8fdf9a60065b | 721 | #define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 722 | |
kadonotakashi | 0:8fdf9a60065b | 723 | #define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */ |
kadonotakashi | 0:8fdf9a60065b | 724 | #define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */ |
kadonotakashi | 0:8fdf9a60065b | 725 | |
kadonotakashi | 0:8fdf9a60065b | 726 | #define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */ |
kadonotakashi | 0:8fdf9a60065b | 727 | #define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 728 | |
kadonotakashi | 0:8fdf9a60065b | 729 | /**@}*/ /* FMC_CONST */ |
kadonotakashi | 0:8fdf9a60065b | 730 | /**@}*/ /* end of FMC register group */ |
kadonotakashi | 0:8fdf9a60065b | 731 | |
kadonotakashi | 0:8fdf9a60065b | 732 | #endif /* __FMC_REG_H__ */ |