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mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/epwm_reg.h@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
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Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
kadonotakashi | 0:8fdf9a60065b | 2 | * @file epwm_reg.h |
kadonotakashi | 0:8fdf9a60065b | 3 | * @version V1.00 |
kadonotakashi | 0:8fdf9a60065b | 4 | * @brief EPWM register definition header file |
kadonotakashi | 0:8fdf9a60065b | 5 | * |
kadonotakashi | 0:8fdf9a60065b | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 7 | *****************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 8 | #ifndef __EPWM_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 9 | #define __EPWM_REG_H__ |
kadonotakashi | 0:8fdf9a60065b | 10 | |
kadonotakashi | 0:8fdf9a60065b | 11 | |
kadonotakashi | 0:8fdf9a60065b | 12 | |
kadonotakashi | 0:8fdf9a60065b | 13 | /*---------------------- Enhanced Pulse Width Modulation Controller -------------------------*/ |
kadonotakashi | 0:8fdf9a60065b | 14 | /** |
kadonotakashi | 0:8fdf9a60065b | 15 | @addtogroup EPWM Enhanced Pulse Width Modulation Controller(EPWM) |
kadonotakashi | 0:8fdf9a60065b | 16 | Memory Mapped Structure for EPWM Controller |
kadonotakashi | 0:8fdf9a60065b | 17 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 18 | |
kadonotakashi | 0:8fdf9a60065b | 19 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 20 | { |
kadonotakashi | 0:8fdf9a60065b | 21 | /** |
kadonotakashi | 0:8fdf9a60065b | 22 | * @var ECAPDAT_T::RCAPDAT |
kadonotakashi | 0:8fdf9a60065b | 23 | * Offset: 0x20C EPWM Rising Capture Data Register 0~5 |
kadonotakashi | 0:8fdf9a60065b | 24 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 25 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 26 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 27 | * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 28 | * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. |
kadonotakashi | 0:8fdf9a60065b | 29 | * @var ECAPDAT_T::FCAPDAT |
kadonotakashi | 0:8fdf9a60065b | 30 | * Offset: 0x210 EPWM Falling Capture Data Register 0~5 |
kadonotakashi | 0:8fdf9a60065b | 31 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 32 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 33 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 34 | * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 35 | * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. |
kadonotakashi | 0:8fdf9a60065b | 36 | */ |
kadonotakashi | 0:8fdf9a60065b | 37 | __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */ |
kadonotakashi | 0:8fdf9a60065b | 38 | __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */ |
kadonotakashi | 0:8fdf9a60065b | 39 | } ECAPDAT_T; |
kadonotakashi | 0:8fdf9a60065b | 40 | |
kadonotakashi | 0:8fdf9a60065b | 41 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 42 | { |
kadonotakashi | 0:8fdf9a60065b | 43 | |
kadonotakashi | 0:8fdf9a60065b | 44 | |
kadonotakashi | 0:8fdf9a60065b | 45 | /** |
kadonotakashi | 0:8fdf9a60065b | 46 | * @var EPWM_T::CTL0 |
kadonotakashi | 0:8fdf9a60065b | 47 | * Offset: 0x00 EPWM Control Register 0 |
kadonotakashi | 0:8fdf9a60065b | 48 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 49 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 50 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 51 | * |[0] |CTRLD0 |Center Re-load |
kadonotakashi | 0:8fdf9a60065b | 52 | * | | |In up-down counter type, PERIOD0 register will load to PBUF0 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 53 | * | | |CMPDAT0 register will load to CMPBUF0 register at the center point of a period. |
kadonotakashi | 0:8fdf9a60065b | 54 | * |[1] |CTRLD1 |Center Re-load |
kadonotakashi | 0:8fdf9a60065b | 55 | * | | |In up-down counter type, PERIOD1 register will load to PBUF1 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 56 | * | | |CMPDAT1 register will load to CMPBUF1 register at the center point of a period. |
kadonotakashi | 0:8fdf9a60065b | 57 | * |[2] |CTRLD2 |Center Re-load |
kadonotakashi | 0:8fdf9a60065b | 58 | * | | |In up-down counter type, PERIOD2 register will load to PBUF2 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 59 | * | | |CMPDAT2 register will load to CMPBUF2 register at the center point of a period. |
kadonotakashi | 0:8fdf9a60065b | 60 | * |[3] |CTRLD3 |Center Re-load |
kadonotakashi | 0:8fdf9a60065b | 61 | * | | |In up-down counter type, PERIOD3 register will load to PBUF3 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 62 | * | | |CMPDAT3 register will load to CMPBUF3 register at the center point of a period. |
kadonotakashi | 0:8fdf9a60065b | 63 | * |[4] |CTRLD4 |Center Re-load |
kadonotakashi | 0:8fdf9a60065b | 64 | * | | |In up-down counter type, PERIOD4 register will load to PBUF4 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 65 | * | | |CMPDAT4 register will load to CMPBUF4 register at the center point of a period. |
kadonotakashi | 0:8fdf9a60065b | 66 | * |[5] |CTRLD5 |Center Re-load |
kadonotakashi | 0:8fdf9a60065b | 67 | * | | |In up-down counter type, PERIOD5 register will load to PBUF5 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 68 | * | | |CMPDAT5 register will load to CMPBUF5 register at the center point of a period. |
kadonotakashi | 0:8fdf9a60065b | 69 | * |[8] |WINLDEN0 |Window Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 70 | * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 71 | * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit. |
kadonotakashi | 0:8fdf9a60065b | 72 | * | | |1 = PERIOD0 register will load to PBUF0 and CMPDAT0 registers will load to CMPBUF0 register at the end point of each period when valid reload window is set. |
kadonotakashi | 0:8fdf9a60065b | 73 | * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. |
kadonotakashi | 0:8fdf9a60065b | 74 | * |[9] |WINLDEN1 |Window Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 75 | * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 76 | * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit. |
kadonotakashi | 0:8fdf9a60065b | 77 | * | | |1 = PERIOD1 register will load to PBUF1 and CMPDAT1 registers will load to CMPBUF1 register at the end point of each period when valid reload window is set. |
kadonotakashi | 0:8fdf9a60065b | 78 | * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. |
kadonotakashi | 0:8fdf9a60065b | 79 | * |[10] |WINLDEN2 |Window Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 80 | * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 81 | * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit. |
kadonotakashi | 0:8fdf9a60065b | 82 | * | | |1 = PERIOD2 register will load to PBUF2 and CMPDAT2 registers will load to CMPBUF2 register at the end point of each period when valid reload window is set. |
kadonotakashi | 0:8fdf9a60065b | 83 | * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. |
kadonotakashi | 0:8fdf9a60065b | 84 | * |[11] |WINLDEN3 |Window Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 85 | * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 86 | * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit. |
kadonotakashi | 0:8fdf9a60065b | 87 | * | | |1 = PERIOD3 register will load to PBUF3 and CMPDAT3 registers will load to CMPBUF3 register at the end point of each period when valid reload window is set. |
kadonotakashi | 0:8fdf9a60065b | 88 | * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. |
kadonotakashi | 0:8fdf9a60065b | 89 | * |[12] |WINLDEN4 |Window Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 90 | * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 91 | * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit. |
kadonotakashi | 0:8fdf9a60065b | 92 | * | | |1 = PERIOD4 register will load to PBUF4 and CMPDAT4 registers will load to CMPBUF4 register at the end point of each period when valid reload window is set. |
kadonotakashi | 0:8fdf9a60065b | 93 | * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. |
kadonotakashi | 0:8fdf9a60065b | 94 | * |[13] |WINLDEN5 |Window Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 95 | * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 96 | * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit. |
kadonotakashi | 0:8fdf9a60065b | 97 | * | | |1 = PERIOD5 register will load to PBUF5 and CMPDAT5 registers will load to CMPBUF5 register at the end point of each period when valid reload window is set. |
kadonotakashi | 0:8fdf9a60065b | 98 | * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. |
kadonotakashi | 0:8fdf9a60065b | 99 | * |[16] |IMMLDEN0 |Immediately Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 100 | * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 101 | * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit. |
kadonotakashi | 0:8fdf9a60065b | 102 | * | | |1 = PERIOD0/CMPDAT0 registers will load to PBUF0 and CMPBUF0 register immediately when software update PERIOD0/CMPDAT0 register. |
kadonotakashi | 0:8fdf9a60065b | 103 | * | | |Note: If IMMLDEN0 bit is enabled, WINLDEN0 bit and CTRLD0 bits will be invalid. |
kadonotakashi | 0:8fdf9a60065b | 104 | * |[17] |IMMLDEN1 |Immediately Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 105 | * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 106 | * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit. |
kadonotakashi | 0:8fdf9a60065b | 107 | * | | |1 = PERIOD1/CMPDAT1 registers will load to PBUF1 and CMPBUF1 register immediately when software update PERIOD1/CMPDAT1 register. |
kadonotakashi | 0:8fdf9a60065b | 108 | * | | |Note: If IMMLDEN1 bit is enabled, WINLDEN1 bit and CTRLD1 bits will be invalid. |
kadonotakashi | 0:8fdf9a60065b | 109 | * |[18] |IMMLDEN2 |Immediately Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 110 | * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 111 | * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit. |
kadonotakashi | 0:8fdf9a60065b | 112 | * | | |1 = PERIOD2/CMPDAT2 registers will load to PBUF2 and CMPBUF2 register immediately when software update PERIOD2/CMPDAT2 register. |
kadonotakashi | 0:8fdf9a60065b | 113 | * | | |Note: If IMMLDEN2 bit is enabled, WINLDEN2 bit and CTRLD2 bits will be invalid. |
kadonotakashi | 0:8fdf9a60065b | 114 | * |[19] |IMMLDEN3 |Immediately Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 115 | * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 116 | * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit. |
kadonotakashi | 0:8fdf9a60065b | 117 | * | | |1 = PERIOD3/CMPDAT3 registers will load to PBUF3 and CMPBUF3 register immediately when software update PERIOD3/CMPDAT3 register. |
kadonotakashi | 0:8fdf9a60065b | 118 | * | | |Note: If IMMLDEN3 bit is enabled, WINLDEN3 bit and CTRLD3 bits will be invalid. |
kadonotakashi | 0:8fdf9a60065b | 119 | * |[20] |IMMLDEN4 |Immediately Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 120 | * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 121 | * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit. |
kadonotakashi | 0:8fdf9a60065b | 122 | * | | |1 = PERIOD4/CMPDAT4 registers will load to PBUF4 and CMPBUF4 register immediately when software update PERIOD4/CMPDAT4 register. |
kadonotakashi | 0:8fdf9a60065b | 123 | * | | |Note: If IMMLDEN4 bit is enabled, WINLDEN4 bit and CTRLD4 bits will be invalid. |
kadonotakashi | 0:8fdf9a60065b | 124 | * |[21] |IMMLDEN5 |Immediately Load Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 125 | * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period. |
kadonotakashi | 0:8fdf9a60065b | 126 | * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit. |
kadonotakashi | 0:8fdf9a60065b | 127 | * | | |1 = PERIOD5/CMPDAT5 registers will load to PBUF5 and CMPBUF5 register immediately when software update PERIOD5/CMPDAT5 register. |
kadonotakashi | 0:8fdf9a60065b | 128 | * | | |Note: If IMMLDEN5 bit is enabled, WINLDEN5 bit and CTRLD5 bits will be invalid. |
kadonotakashi | 0:8fdf9a60065b | 129 | * |[24] |GROUPEN |Group Function Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 130 | * | | |0 = The output waveform of each EPWM channel are independent. |
kadonotakashi | 0:8fdf9a60065b | 131 | * | | |1 = Unify the EPWMx_CH2 and EPWMx_CH4 to output the same waveform as EPWMx_CH0 and unify the EPWMx_CH3 and EPWMx_CH5 to output the same waveform as EPWMx_CH1. |
kadonotakashi | 0:8fdf9a60065b | 132 | * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 133 | * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. |
kadonotakashi | 0:8fdf9a60065b | 134 | * | | |0 = ICE debug mode counter halt disable. |
kadonotakashi | 0:8fdf9a60065b | 135 | * | | |1 = ICE debug mode counter halt enable. |
kadonotakashi | 0:8fdf9a60065b | 136 | * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 137 | * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 138 | * | | |0 = ICE debug mode acknowledgement effects EPWM output. |
kadonotakashi | 0:8fdf9a60065b | 139 | * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged. |
kadonotakashi | 0:8fdf9a60065b | 140 | * | | |1 = ICE debug mode acknowledgement disabled. |
kadonotakashi | 0:8fdf9a60065b | 141 | * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not. |
kadonotakashi | 0:8fdf9a60065b | 142 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 143 | * @var EPWM_T::CTL1 |
kadonotakashi | 0:8fdf9a60065b | 144 | * Offset: 0x04 EPWM Control Register 1 |
kadonotakashi | 0:8fdf9a60065b | 145 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 146 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 147 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 148 | * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type |
kadonotakashi | 0:8fdf9a60065b | 149 | * | | |00 = Up counter type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 150 | * | | |01 = Down count type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 151 | * | | |10 = Up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 152 | * | | |11 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 153 | * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type |
kadonotakashi | 0:8fdf9a60065b | 154 | * | | |00 = Up counter type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 155 | * | | |01 = Down count type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 156 | * | | |10 = Up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 157 | * | | |11 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 158 | * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type |
kadonotakashi | 0:8fdf9a60065b | 159 | * | | |00 = Up counter type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 160 | * | | |01 = Down count type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 161 | * | | |10 = Up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 162 | * | | |11 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 163 | * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type |
kadonotakashi | 0:8fdf9a60065b | 164 | * | | |00 = Up counter type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 165 | * | | |01 = Down count type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 166 | * | | |10 = Up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 167 | * | | |11 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 168 | * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type |
kadonotakashi | 0:8fdf9a60065b | 169 | * | | |00 = Up counter type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 170 | * | | |01 = Down count type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 171 | * | | |10 = Up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 172 | * | | |11 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 173 | * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type |
kadonotakashi | 0:8fdf9a60065b | 174 | * | | |00 = Up counter type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 175 | * | | |01 = Down count type (supports in capture mode). |
kadonotakashi | 0:8fdf9a60065b | 176 | * | | |10 = Up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 177 | * | | |11 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 178 | * |[16] |CNTMODE0 |EPWM Counter Mode |
kadonotakashi | 0:8fdf9a60065b | 179 | * | | |0 = Auto-reload mode. |
kadonotakashi | 0:8fdf9a60065b | 180 | * | | |1 = One-shot mode. |
kadonotakashi | 0:8fdf9a60065b | 181 | * |[17] |CNTMODE1 |EPWM Counter Mode |
kadonotakashi | 0:8fdf9a60065b | 182 | * | | |0 = Auto-reload mode. |
kadonotakashi | 0:8fdf9a60065b | 183 | * | | |1 = One-shot mode. |
kadonotakashi | 0:8fdf9a60065b | 184 | * |[18] |CNTMODE2 |EPWM Counter Mode |
kadonotakashi | 0:8fdf9a60065b | 185 | * | | |0 = Auto-reload mode. |
kadonotakashi | 0:8fdf9a60065b | 186 | * | | |1 = One-shot mode. |
kadonotakashi | 0:8fdf9a60065b | 187 | * |[19] |CNTMODE3 |EPWM Counter Mode |
kadonotakashi | 0:8fdf9a60065b | 188 | * | | |0 = Auto-reload mode. |
kadonotakashi | 0:8fdf9a60065b | 189 | * | | |1 = One-shot mode. |
kadonotakashi | 0:8fdf9a60065b | 190 | * |[20] |CNTMODE4 |EPWM Counter Mode |
kadonotakashi | 0:8fdf9a60065b | 191 | * | | |0 = Auto-reload mode. |
kadonotakashi | 0:8fdf9a60065b | 192 | * | | |1 = One-shot mode. |
kadonotakashi | 0:8fdf9a60065b | 193 | * |[21] |CNTMODE5 |EPWM Counter Mode |
kadonotakashi | 0:8fdf9a60065b | 194 | * | | |0 = Auto-reload mode. |
kadonotakashi | 0:8fdf9a60065b | 195 | * | | |1 = One-shot mode. |
kadonotakashi | 0:8fdf9a60065b | 196 | * |[24] |OUTMODE0 |EPWM Output Mode |
kadonotakashi | 0:8fdf9a60065b | 197 | * | | |Each bit n controls the output mode of corresponding EPWM channel n. |
kadonotakashi | 0:8fdf9a60065b | 198 | * | | |0 = EPWM independent mode. |
kadonotakashi | 0:8fdf9a60065b | 199 | * | | |1 = EPWM complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 200 | * | | |Note: When operating in group function, these bits must all set to the same mode. |
kadonotakashi | 0:8fdf9a60065b | 201 | * |[25] |OUTMODE2 |EPWM Output Mode |
kadonotakashi | 0:8fdf9a60065b | 202 | * | | |Each bit n controls the output mode of corresponding EPWM channel n. |
kadonotakashi | 0:8fdf9a60065b | 203 | * | | |0 = EPWM independent mode. |
kadonotakashi | 0:8fdf9a60065b | 204 | * | | |1 = EPWM complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 205 | * | | |Note: When operating in group function, these bits must all set to the same mode. |
kadonotakashi | 0:8fdf9a60065b | 206 | * |[26] |OUTMODE4 |EPWM Output Mode |
kadonotakashi | 0:8fdf9a60065b | 207 | * | | |Each bit n controls the output mode of corresponding EPWM channel n. |
kadonotakashi | 0:8fdf9a60065b | 208 | * | | |0 = EPWM independent mode. |
kadonotakashi | 0:8fdf9a60065b | 209 | * | | |1 = EPWM complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 210 | * | | |Note: When operating in group function, these bits must all set to the same mode. |
kadonotakashi | 0:8fdf9a60065b | 211 | * @var EPWM_T::SYNC |
kadonotakashi | 0:8fdf9a60065b | 212 | * Offset: 0x08 EPWM Synchronization Register |
kadonotakashi | 0:8fdf9a60065b | 213 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 214 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 215 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 216 | * |[0] |PHSEN0 |SYNC Phase Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 217 | * | | |0 = EPWM counter disable to load PHS value. |
kadonotakashi | 0:8fdf9a60065b | 218 | * | | |1 = EPWM counter enable to load PHS value. |
kadonotakashi | 0:8fdf9a60065b | 219 | * |[1] |PHSEN2 |SYNC Phase Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 220 | * | | |0 = EPWM counter disable to load PHS value. |
kadonotakashi | 0:8fdf9a60065b | 221 | * | | |1 = EPWM counter enable to load PHS value. |
kadonotakashi | 0:8fdf9a60065b | 222 | * |[2] |PHSEN4 |SYNC Phase Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 223 | * | | |0 = EPWM counter disable to load PHS value. |
kadonotakashi | 0:8fdf9a60065b | 224 | * | | |1 = EPWM counter enable to load PHS value. |
kadonotakashi | 0:8fdf9a60065b | 225 | * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection |
kadonotakashi | 0:8fdf9a60065b | 226 | * | | |00 = Synchronize source from SYNC_IN or SWSYNC. |
kadonotakashi | 0:8fdf9a60065b | 227 | * | | |01 = Counter equal to 0. |
kadonotakashi | 0:8fdf9a60065b | 228 | * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. |
kadonotakashi | 0:8fdf9a60065b | 229 | * | | |11 = SYNC_OUT will not be generated. |
kadonotakashi | 0:8fdf9a60065b | 230 | * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection |
kadonotakashi | 0:8fdf9a60065b | 231 | * | | |00 = Synchronize source from SYNC_IN or SWSYNC. |
kadonotakashi | 0:8fdf9a60065b | 232 | * | | |01 = Counter equal to 0. |
kadonotakashi | 0:8fdf9a60065b | 233 | * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. |
kadonotakashi | 0:8fdf9a60065b | 234 | * | | |11 = SYNC_OUT will not be generated. |
kadonotakashi | 0:8fdf9a60065b | 235 | * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection |
kadonotakashi | 0:8fdf9a60065b | 236 | * | | |00 = Synchronize source from SYNC_IN or SWSYNC. |
kadonotakashi | 0:8fdf9a60065b | 237 | * | | |01 = Counter equal to 0. |
kadonotakashi | 0:8fdf9a60065b | 238 | * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. |
kadonotakashi | 0:8fdf9a60065b | 239 | * | | |11 = SYNC_OUT will not be generated. |
kadonotakashi | 0:8fdf9a60065b | 240 | * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 241 | * | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled. |
kadonotakashi | 0:8fdf9a60065b | 242 | * | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled. |
kadonotakashi | 0:8fdf9a60065b | 243 | * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection |
kadonotakashi | 0:8fdf9a60065b | 244 | * | | |000 = Filter clock = HCLK. |
kadonotakashi | 0:8fdf9a60065b | 245 | * | | |001 = Filter clock = HCLK/2. |
kadonotakashi | 0:8fdf9a60065b | 246 | * | | |010 = Filter clock = HCLK/4. |
kadonotakashi | 0:8fdf9a60065b | 247 | * | | |011 = Filter clock = HCLK/8. |
kadonotakashi | 0:8fdf9a60065b | 248 | * | | |100 = Filter clock = HCLK/16. |
kadonotakashi | 0:8fdf9a60065b | 249 | * | | |101 = Filter clock = HCLK/32. |
kadonotakashi | 0:8fdf9a60065b | 250 | * | | |110 = Filter clock = HCLK/64. |
kadonotakashi | 0:8fdf9a60065b | 251 | * | | |111 = Filter clock = HCLK/128. |
kadonotakashi | 0:8fdf9a60065b | 252 | * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count |
kadonotakashi | 0:8fdf9a60065b | 253 | * | | |The register bits control the counter number of edge detector. |
kadonotakashi | 0:8fdf9a60065b | 254 | * |[23] |SINPINV |SYNC Input Pin Inverse |
kadonotakashi | 0:8fdf9a60065b | 255 | * | | |0 = The state of pin EPWM0_SYNC_IN is passed to the negative edge detector. |
kadonotakashi | 0:8fdf9a60065b | 256 | * | | |1 = The inverse state of pin EPWM0_SYNC_IN is passed to the negative edge detector. |
kadonotakashi | 0:8fdf9a60065b | 257 | * |[24] |PHSDIR0 |EPWM Phase Direction Control |
kadonotakashi | 0:8fdf9a60065b | 258 | * | | |0 = Control EPWM counter count decrement after synchronizing. |
kadonotakashi | 0:8fdf9a60065b | 259 | * | | |1 = Control EPWM counter count increment after synchronizing. |
kadonotakashi | 0:8fdf9a60065b | 260 | * |[25] |PHSDIR2 |EPWM Phase Direction Control |
kadonotakashi | 0:8fdf9a60065b | 261 | * | | |0 = Control EPWM counter count decrement after synchronizing. |
kadonotakashi | 0:8fdf9a60065b | 262 | * | | |1 = Control EPWM counter count increment after synchronizing. |
kadonotakashi | 0:8fdf9a60065b | 263 | * |[26] |PHSDIR4 |EPWM Phase Direction Control |
kadonotakashi | 0:8fdf9a60065b | 264 | * | | |0 = Control EPWM counter count decrement after synchronizing. |
kadonotakashi | 0:8fdf9a60065b | 265 | * | | |1 = Control EPWM counter count increment after synchronizing. |
kadonotakashi | 0:8fdf9a60065b | 266 | * @var EPWM_T::SWSYNC |
kadonotakashi | 0:8fdf9a60065b | 267 | * Offset: 0x0C EPWM Software Control Synchronization Register |
kadonotakashi | 0:8fdf9a60065b | 268 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 269 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 270 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 271 | * |[0] |SWSYNC0 |Software SYNC Function |
kadonotakashi | 0:8fdf9a60065b | 272 | * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. |
kadonotakashi | 0:8fdf9a60065b | 273 | * |[1] |SWSYNC2 |Software SYNC Function |
kadonotakashi | 0:8fdf9a60065b | 274 | * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. |
kadonotakashi | 0:8fdf9a60065b | 275 | * |[2] |SWSYNC4 |Software SYNC Function |
kadonotakashi | 0:8fdf9a60065b | 276 | * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. |
kadonotakashi | 0:8fdf9a60065b | 277 | * @var EPWM_T::CLKSRC |
kadonotakashi | 0:8fdf9a60065b | 278 | * Offset: 0x10 EPWM Clock Source Register |
kadonotakashi | 0:8fdf9a60065b | 279 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 280 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 281 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 282 | * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select |
kadonotakashi | 0:8fdf9a60065b | 283 | * | | |000 = EPWMx_CLK, x denotes 0 or 1. |
kadonotakashi | 0:8fdf9a60065b | 284 | * | | |001 = TIMER0 overflow. |
kadonotakashi | 0:8fdf9a60065b | 285 | * | | |010 = TIMER1 overflow. |
kadonotakashi | 0:8fdf9a60065b | 286 | * | | |011 = TIMER2 overflow. |
kadonotakashi | 0:8fdf9a60065b | 287 | * | | |100 = TIMER3 overflow. |
kadonotakashi | 0:8fdf9a60065b | 288 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 289 | * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select |
kadonotakashi | 0:8fdf9a60065b | 290 | * | | |000 = EPWMx_CLK, x denotes 0 or 1. |
kadonotakashi | 0:8fdf9a60065b | 291 | * | | |001 = TIMER0 overflow. |
kadonotakashi | 0:8fdf9a60065b | 292 | * | | |010 = TIMER1 overflow. |
kadonotakashi | 0:8fdf9a60065b | 293 | * | | |011 = TIMER2 overflow. |
kadonotakashi | 0:8fdf9a60065b | 294 | * | | |100 = TIMER3 overflow. |
kadonotakashi | 0:8fdf9a60065b | 295 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 296 | * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select |
kadonotakashi | 0:8fdf9a60065b | 297 | * | | |000 = EPWMx_CLK, x denotes 0 or 1. |
kadonotakashi | 0:8fdf9a60065b | 298 | * | | |001 = TIMER0 overflow. |
kadonotakashi | 0:8fdf9a60065b | 299 | * | | |010 = TIMER1 overflow. |
kadonotakashi | 0:8fdf9a60065b | 300 | * | | |011 = TIMER2 overflow. |
kadonotakashi | 0:8fdf9a60065b | 301 | * | | |100 = TIMER3 overflow. |
kadonotakashi | 0:8fdf9a60065b | 302 | * | | |Others = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 303 | * @var EPWM_T::CLKPSC[3] |
kadonotakashi | 0:8fdf9a60065b | 304 | * Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5 |
kadonotakashi | 0:8fdf9a60065b | 305 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 306 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 307 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 308 | * |[11:0] |CLKPSC |EPWM Counter Clock Prescale |
kadonotakashi | 0:8fdf9a60065b | 309 | * | | |The clock of EPWM counter is decided by clock prescaler |
kadonotakashi | 0:8fdf9a60065b | 310 | * | | |Each EPWM pair share one EPWM counter clock prescaler |
kadonotakashi | 0:8fdf9a60065b | 311 | * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) |
kadonotakashi | 0:8fdf9a60065b | 312 | * @var EPWM_T::CNTEN |
kadonotakashi | 0:8fdf9a60065b | 313 | * Offset: 0x20 EPWM Counter Enable Register |
kadonotakashi | 0:8fdf9a60065b | 314 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 315 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 316 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 317 | * |[0] |CNTEN0 |EPWM Counter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 318 | * | | |0 = EPWM Counter and clock prescaler Stop Running. |
kadonotakashi | 0:8fdf9a60065b | 319 | * | | |1 = EPWM Counter and clock prescaler Start Running. |
kadonotakashi | 0:8fdf9a60065b | 320 | * |[1] |CNTEN1 |EPWM Counter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 321 | * | | |0 = EPWM Counter and clock prescaler Stop Running. |
kadonotakashi | 0:8fdf9a60065b | 322 | * | | |1 = EPWM Counter and clock prescaler Start Running. |
kadonotakashi | 0:8fdf9a60065b | 323 | * |[2] |CNTEN2 |EPWM Counter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 324 | * | | |0 = EPWM Counter and clock prescaler Stop Running. |
kadonotakashi | 0:8fdf9a60065b | 325 | * | | |1 = EPWM Counter and clock prescaler Start Running. |
kadonotakashi | 0:8fdf9a60065b | 326 | * |[3] |CNTEN3 |EPWM Counter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 327 | * | | |0 = EPWM Counter and clock prescaler Stop Running. |
kadonotakashi | 0:8fdf9a60065b | 328 | * | | |1 = EPWM Counter and clock prescaler Start Running. |
kadonotakashi | 0:8fdf9a60065b | 329 | * |[4] |CNTEN4 |EPWM Counter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 330 | * | | |0 = EPWM Counter and clock prescaler Stop Running. |
kadonotakashi | 0:8fdf9a60065b | 331 | * | | |1 = EPWM Counter and clock prescaler Start Running. |
kadonotakashi | 0:8fdf9a60065b | 332 | * |[5] |CNTEN5 |EPWM Counter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 333 | * | | |0 = EPWM Counter and clock prescaler Stop Running. |
kadonotakashi | 0:8fdf9a60065b | 334 | * | | |1 = EPWM Counter and clock prescaler Start Running. |
kadonotakashi | 0:8fdf9a60065b | 335 | * @var EPWM_T::CNTCLR |
kadonotakashi | 0:8fdf9a60065b | 336 | * Offset: 0x24 EPWM Clear Counter Register |
kadonotakashi | 0:8fdf9a60065b | 337 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 338 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 339 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 340 | * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit |
kadonotakashi | 0:8fdf9a60065b | 341 | * | | |It is automatically cleared by hardware. |
kadonotakashi | 0:8fdf9a60065b | 342 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 343 | * | | |1 = Clear 16-bit EPWM counter to 0000H. |
kadonotakashi | 0:8fdf9a60065b | 344 | * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit |
kadonotakashi | 0:8fdf9a60065b | 345 | * | | |It is automatically cleared by hardware. |
kadonotakashi | 0:8fdf9a60065b | 346 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 347 | * | | |1 = Clear 16-bit EPWM counter to 0000H. |
kadonotakashi | 0:8fdf9a60065b | 348 | * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit |
kadonotakashi | 0:8fdf9a60065b | 349 | * | | |It is automatically cleared by hardware. |
kadonotakashi | 0:8fdf9a60065b | 350 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 351 | * | | |1 = Clear 16-bit EPWM counter to 0000H. |
kadonotakashi | 0:8fdf9a60065b | 352 | * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit |
kadonotakashi | 0:8fdf9a60065b | 353 | * | | |It is automatically cleared by hardware. |
kadonotakashi | 0:8fdf9a60065b | 354 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 355 | * | | |1 = Clear 16-bit EPWM counter to 0000H. |
kadonotakashi | 0:8fdf9a60065b | 356 | * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit |
kadonotakashi | 0:8fdf9a60065b | 357 | * | | |It is automatically cleared by hardware. |
kadonotakashi | 0:8fdf9a60065b | 358 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 359 | * | | |1 = Clear 16-bit EPWM counter to 0000H. |
kadonotakashi | 0:8fdf9a60065b | 360 | * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit |
kadonotakashi | 0:8fdf9a60065b | 361 | * | | |It is automatically cleared by hardware. |
kadonotakashi | 0:8fdf9a60065b | 362 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 363 | * | | |1 = Clear 16-bit EPWM counter to 0000H. |
kadonotakashi | 0:8fdf9a60065b | 364 | * @var EPWM_T::LOAD |
kadonotakashi | 0:8fdf9a60065b | 365 | * Offset: 0x28 EPWM Load Register |
kadonotakashi | 0:8fdf9a60065b | 366 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 367 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 368 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 369 | * |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit |
kadonotakashi | 0:8fdf9a60065b | 370 | * | | |This bit is software write, hardware clear when current EPWM period end. |
kadonotakashi | 0:8fdf9a60065b | 371 | * | | |Write Operation: |
kadonotakashi | 0:8fdf9a60065b | 372 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 373 | * | | |1 = Set load window of window loading mode. |
kadonotakashi | 0:8fdf9a60065b | 374 | * | | |Read Operation: |
kadonotakashi | 0:8fdf9a60065b | 375 | * | | |0 = No load window is set. |
kadonotakashi | 0:8fdf9a60065b | 376 | * | | |1 = Load window is set. |
kadonotakashi | 0:8fdf9a60065b | 377 | * | | |Note: This bit only use in window loading mode, WINLDEN0(EPWM_CTL0[13:8]) = 1. |
kadonotakashi | 0:8fdf9a60065b | 378 | * |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit |
kadonotakashi | 0:8fdf9a60065b | 379 | * | | |This bit is software write, hardware clear when current EPWM period end. |
kadonotakashi | 0:8fdf9a60065b | 380 | * | | |Write Operation: |
kadonotakashi | 0:8fdf9a60065b | 381 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 382 | * | | |1 = Set load window of window loading mode. |
kadonotakashi | 0:8fdf9a60065b | 383 | * | | |Read Operation: |
kadonotakashi | 0:8fdf9a60065b | 384 | * | | |0 = No load window is set. |
kadonotakashi | 0:8fdf9a60065b | 385 | * | | |1 = Load window is set. |
kadonotakashi | 0:8fdf9a60065b | 386 | * | | |Note: This bit only use in window loading mode, WINLDEN1(EPWM_CTL0[13:8]) = 1. |
kadonotakashi | 0:8fdf9a60065b | 387 | * |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit |
kadonotakashi | 0:8fdf9a60065b | 388 | * | | |This bit is software write, hardware clear when current EPWM period end. |
kadonotakashi | 0:8fdf9a60065b | 389 | * | | |Write Operation: |
kadonotakashi | 0:8fdf9a60065b | 390 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 391 | * | | |1 = Set load window of window loading mode. |
kadonotakashi | 0:8fdf9a60065b | 392 | * | | |Read Operation: |
kadonotakashi | 0:8fdf9a60065b | 393 | * | | |0 = No load window is set. |
kadonotakashi | 0:8fdf9a60065b | 394 | * | | |1 = Load window is set. |
kadonotakashi | 0:8fdf9a60065b | 395 | * | | |Note: This bit only use in window loading mode, WINLDEN2(EPWM_CTL0[13:8]) = 1. |
kadonotakashi | 0:8fdf9a60065b | 396 | * |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit |
kadonotakashi | 0:8fdf9a60065b | 397 | * | | |This bit is software write, hardware clear when current EPWM period end. |
kadonotakashi | 0:8fdf9a60065b | 398 | * | | |Write Operation: |
kadonotakashi | 0:8fdf9a60065b | 399 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 400 | * | | |1 = Set load window of window loading mode. |
kadonotakashi | 0:8fdf9a60065b | 401 | * | | |Read Operation: |
kadonotakashi | 0:8fdf9a60065b | 402 | * | | |0 = No load window is set. |
kadonotakashi | 0:8fdf9a60065b | 403 | * | | |1 = Load window is set. |
kadonotakashi | 0:8fdf9a60065b | 404 | * | | |Note: This bit only use in window loading mode, WINLDEN3(EPWM_CTL0[13:8]) = 1. |
kadonotakashi | 0:8fdf9a60065b | 405 | * |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit |
kadonotakashi | 0:8fdf9a60065b | 406 | * | | |This bit is software write, hardware clear when current EPWM period end. |
kadonotakashi | 0:8fdf9a60065b | 407 | * | | |Write Operation: |
kadonotakashi | 0:8fdf9a60065b | 408 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 409 | * | | |1 = Set load window of window loading mode. |
kadonotakashi | 0:8fdf9a60065b | 410 | * | | |Read Operation: |
kadonotakashi | 0:8fdf9a60065b | 411 | * | | |0 = No load window is set. |
kadonotakashi | 0:8fdf9a60065b | 412 | * | | |1 = Load window is set. |
kadonotakashi | 0:8fdf9a60065b | 413 | * | | |Note: This bit only use in window loading mode, WINLDEN4(EPWM_CTL0[13:8]) = 1. |
kadonotakashi | 0:8fdf9a60065b | 414 | * |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit |
kadonotakashi | 0:8fdf9a60065b | 415 | * | | |This bit is software write, hardware clear when current EPWM period end. |
kadonotakashi | 0:8fdf9a60065b | 416 | * | | |Write Operation: |
kadonotakashi | 0:8fdf9a60065b | 417 | * | | |0 = No effect. |
kadonotakashi | 0:8fdf9a60065b | 418 | * | | |1 = Set load window of window loading mode. |
kadonotakashi | 0:8fdf9a60065b | 419 | * | | |Read Operation: |
kadonotakashi | 0:8fdf9a60065b | 420 | * | | |0 = No load window is set. |
kadonotakashi | 0:8fdf9a60065b | 421 | * | | |1 = Load window is set. |
kadonotakashi | 0:8fdf9a60065b | 422 | * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. |
kadonotakashi | 0:8fdf9a60065b | 423 | * @var EPWM_T::PERIOD[6] |
kadonotakashi | 0:8fdf9a60065b | 424 | * Offset: 0x30 EPWM Period Register 0~5 |
kadonotakashi | 0:8fdf9a60065b | 425 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 426 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 427 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 428 | * |[15:0] |PERIOD |EPWM Period Register |
kadonotakashi | 0:8fdf9a60065b | 429 | * | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. |
kadonotakashi | 0:8fdf9a60065b | 430 | * | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. |
kadonotakashi | 0:8fdf9a60065b | 431 | * | | |EPWM period time = (PERIOD+1) * EPWM_CLK period. |
kadonotakashi | 0:8fdf9a60065b | 432 | * | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. |
kadonotakashi | 0:8fdf9a60065b | 433 | * | | |EPWM period time = 2 * PERIOD * EPWM_CLK period. |
kadonotakashi | 0:8fdf9a60065b | 434 | * @var EPWM_T::CMPDAT[6] |
kadonotakashi | 0:8fdf9a60065b | 435 | * Offset: 0x50 EPWM Comparator Register 0 |
kadonotakashi | 0:8fdf9a60065b | 436 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 437 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 438 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 439 | * |[15:0] |CMP |EPWM Comparator Register |
kadonotakashi | 0:8fdf9a60065b | 440 | * | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC. |
kadonotakashi | 0:8fdf9a60065b | 441 | * | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point. |
kadonotakashi | 0:8fdf9a60065b | 442 | * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. |
kadonotakashi | 0:8fdf9a60065b | 443 | * @var EPWM_T::DTCTL[3] |
kadonotakashi | 0:8fdf9a60065b | 444 | * Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5 |
kadonotakashi | 0:8fdf9a60065b | 445 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 446 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 447 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 448 | * |[11:0] |DTCNT |Dead-time Counter (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 449 | * | | |The dead-time can be calculated from the following formula: |
kadonotakashi | 0:8fdf9a60065b | 450 | * | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period. |
kadonotakashi | 0:8fdf9a60065b | 451 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 452 | * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 453 | * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled |
kadonotakashi | 0:8fdf9a60065b | 454 | * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. |
kadonotakashi | 0:8fdf9a60065b | 455 | * | | |0 = Dead-time insertion Disabled on the pin pair. |
kadonotakashi | 0:8fdf9a60065b | 456 | * | | |1 = Dead-time insertion Enabled on the pin pair. |
kadonotakashi | 0:8fdf9a60065b | 457 | * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 458 | * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 459 | * | | |0 = Dead-time clock source from EPWM_CLK. |
kadonotakashi | 0:8fdf9a60065b | 460 | * | | |1 = Dead-time clock source from prescaler output. |
kadonotakashi | 0:8fdf9a60065b | 461 | * | | |Note: This register is write protected. Refer toREGWRPROT register. |
kadonotakashi | 0:8fdf9a60065b | 462 | * @var EPWM_T::PHS[3] |
kadonotakashi | 0:8fdf9a60065b | 463 | * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5 |
kadonotakashi | 0:8fdf9a60065b | 464 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 465 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 466 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 467 | * |[15:0] |PHS |EPWM Synchronous Start Phase Bits |
kadonotakashi | 0:8fdf9a60065b | 468 | * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. |
kadonotakashi | 0:8fdf9a60065b | 469 | * @var EPWM_T::CNT[6] |
kadonotakashi | 0:8fdf9a60065b | 470 | * Offset: 0x90 EPWM Counter Register 0~5 |
kadonotakashi | 0:8fdf9a60065b | 471 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 472 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 473 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 474 | * |[15:0] |CNT |EPWM Data Register (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 475 | * | | |User can monitor CNTR to know the current value in 16-bit period counter. |
kadonotakashi | 0:8fdf9a60065b | 476 | * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 477 | * | | |0 = Counter is Down count. |
kadonotakashi | 0:8fdf9a60065b | 478 | * | | |1 = Counter is UP count. |
kadonotakashi | 0:8fdf9a60065b | 479 | * @var EPWM_T::WGCTL0 |
kadonotakashi | 0:8fdf9a60065b | 480 | * Offset: 0xB0 EPWM Generation Register 0 |
kadonotakashi | 0:8fdf9a60065b | 481 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 482 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 483 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 484 | * |[1:0] |ZPCTL0 |EPWM Zero Point Control |
kadonotakashi | 0:8fdf9a60065b | 485 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 486 | * | | |01 = EPWM zero point output Low. |
kadonotakashi | 0:8fdf9a60065b | 487 | * | | |10 = EPWM zero point output High. |
kadonotakashi | 0:8fdf9a60065b | 488 | * | | |11 = EPWM zero point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 489 | * | | |EPWM can control output level when EPWM counter count to zero. |
kadonotakashi | 0:8fdf9a60065b | 490 | * |[3:2] |ZPCTL1 |EPWM Zero Point Control |
kadonotakashi | 0:8fdf9a60065b | 491 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 492 | * | | |01 = EPWM zero point output Low. |
kadonotakashi | 0:8fdf9a60065b | 493 | * | | |10 = EPWM zero point output High. |
kadonotakashi | 0:8fdf9a60065b | 494 | * | | |11 = EPWM zero point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 495 | * | | |EPWM can control output level when EPWM counter count to zero. |
kadonotakashi | 0:8fdf9a60065b | 496 | * |[5:4] |ZPCTL2 |EPWM Zero Point Control |
kadonotakashi | 0:8fdf9a60065b | 497 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 498 | * | | |01 = EPWM zero point output Low. |
kadonotakashi | 0:8fdf9a60065b | 499 | * | | |10 = EPWM zero point output High. |
kadonotakashi | 0:8fdf9a60065b | 500 | * | | |11 = EPWM zero point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 501 | * | | |EPWM can control output level when EPWM counter count to zero. |
kadonotakashi | 0:8fdf9a60065b | 502 | * |[7:6] |ZPCTL3 |EPWM Zero Point Control |
kadonotakashi | 0:8fdf9a60065b | 503 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 504 | * | | |01 = EPWM zero point output Low. |
kadonotakashi | 0:8fdf9a60065b | 505 | * | | |10 = EPWM zero point output High. |
kadonotakashi | 0:8fdf9a60065b | 506 | * | | |11 = EPWM zero point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 507 | * | | |EPWM can control output level when EPWM counter count to zero. |
kadonotakashi | 0:8fdf9a60065b | 508 | * |[9:8] |ZPCTL4 |EPWM Zero Point Control |
kadonotakashi | 0:8fdf9a60065b | 509 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 510 | * | | |01 = EPWM zero point output Low. |
kadonotakashi | 0:8fdf9a60065b | 511 | * | | |10 = EPWM zero point output High. |
kadonotakashi | 0:8fdf9a60065b | 512 | * | | |11 = EPWM zero point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 513 | * | | |EPWM can control output level when EPWM counter count to zero. |
kadonotakashi | 0:8fdf9a60065b | 514 | * |[11:10] |ZPCTL5 |EPWM Zero Point Control |
kadonotakashi | 0:8fdf9a60065b | 515 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 516 | * | | |01 = EPWM zero point output Low. |
kadonotakashi | 0:8fdf9a60065b | 517 | * | | |10 = EPWM zero point output High. |
kadonotakashi | 0:8fdf9a60065b | 518 | * | | |11 = EPWM zero point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 519 | * | | |EPWM can control output level when EPWM counter count to zero. |
kadonotakashi | 0:8fdf9a60065b | 520 | * |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control |
kadonotakashi | 0:8fdf9a60065b | 521 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 522 | * | | |01 = EPWM period (center) point output Low. |
kadonotakashi | 0:8fdf9a60065b | 523 | * | | |10 = EPWM period (center) point output High. |
kadonotakashi | 0:8fdf9a60065b | 524 | * | | |11 = EPWM period (center) point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 525 | * | | |EPWM can control output level when EPWM counter count to (PERIOD0+1). |
kadonotakashi | 0:8fdf9a60065b | 526 | * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 527 | * |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control |
kadonotakashi | 0:8fdf9a60065b | 528 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 529 | * | | |01 = EPWM period (center) point output Low. |
kadonotakashi | 0:8fdf9a60065b | 530 | * | | |10 = EPWM period (center) point output High. |
kadonotakashi | 0:8fdf9a60065b | 531 | * | | |11 = EPWM period (center) point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 532 | * | | |EPWM can control output level when EPWM counter count to (PERIOD1+1). |
kadonotakashi | 0:8fdf9a60065b | 533 | * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 534 | * |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control |
kadonotakashi | 0:8fdf9a60065b | 535 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 536 | * | | |01 = EPWM period (center) point output Low. |
kadonotakashi | 0:8fdf9a60065b | 537 | * | | |10 = EPWM period (center) point output High. |
kadonotakashi | 0:8fdf9a60065b | 538 | * | | |11 = EPWM period (center) point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 539 | * | | |EPWM can control output level when EPWM counter count to (PERIOD2+1). |
kadonotakashi | 0:8fdf9a60065b | 540 | * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 541 | * |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control |
kadonotakashi | 0:8fdf9a60065b | 542 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 543 | * | | |01 = EPWM period (center) point output Low. |
kadonotakashi | 0:8fdf9a60065b | 544 | * | | |10 = EPWM period (center) point output High. |
kadonotakashi | 0:8fdf9a60065b | 545 | * | | |11 = EPWM period (center) point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 546 | * | | |EPWM can control output level when EPWM counter count to (PERIOD3+1). |
kadonotakashi | 0:8fdf9a60065b | 547 | * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 548 | * |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control |
kadonotakashi | 0:8fdf9a60065b | 549 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 550 | * | | |01 = EPWM period (center) point output Low. |
kadonotakashi | 0:8fdf9a60065b | 551 | * | | |10 = EPWM period (center) point output High. |
kadonotakashi | 0:8fdf9a60065b | 552 | * | | |11 = EPWM period (center) point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 553 | * | | |EPWM can control output level when EPWM counter count to (PERIOD4+1). |
kadonotakashi | 0:8fdf9a60065b | 554 | * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 555 | * |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control |
kadonotakashi | 0:8fdf9a60065b | 556 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 557 | * | | |01 = EPWM period (center) point output Low. |
kadonotakashi | 0:8fdf9a60065b | 558 | * | | |10 = EPWM period (center) point output High. |
kadonotakashi | 0:8fdf9a60065b | 559 | * | | |11 = EPWM period (center) point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 560 | * | | |EPWM can control output level when EPWM counter count to (PERIOD5+1). |
kadonotakashi | 0:8fdf9a60065b | 561 | * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. |
kadonotakashi | 0:8fdf9a60065b | 562 | * @var EPWM_T::WGCTL1 |
kadonotakashi | 0:8fdf9a60065b | 563 | * Offset: 0xB4 EPWM Generation Register 1 |
kadonotakashi | 0:8fdf9a60065b | 564 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 565 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 566 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 567 | * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control |
kadonotakashi | 0:8fdf9a60065b | 568 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 569 | * | | |01 = EPWM compare up point output Low. |
kadonotakashi | 0:8fdf9a60065b | 570 | * | | |10 = EPWM compare up point output High. |
kadonotakashi | 0:8fdf9a60065b | 571 | * | | |11 = EPWM compare up point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 572 | * | | |EPWM can control output level when EPWM counter up count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 573 | * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 574 | * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control |
kadonotakashi | 0:8fdf9a60065b | 575 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 576 | * | | |01 = EPWM compare up point output Low. |
kadonotakashi | 0:8fdf9a60065b | 577 | * | | |10 = EPWM compare up point output High. |
kadonotakashi | 0:8fdf9a60065b | 578 | * | | |11 = EPWM compare up point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 579 | * | | |EPWM can control output level when EPWM counter up count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 580 | * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 581 | * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control |
kadonotakashi | 0:8fdf9a60065b | 582 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 583 | * | | |01 = EPWM compare up point output Low. |
kadonotakashi | 0:8fdf9a60065b | 584 | * | | |10 = EPWM compare up point output High. |
kadonotakashi | 0:8fdf9a60065b | 585 | * | | |11 = EPWM compare up point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 586 | * | | |EPWM can control output level when EPWM counter up count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 587 | * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 588 | * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control |
kadonotakashi | 0:8fdf9a60065b | 589 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 590 | * | | |01 = EPWM compare up point output Low. |
kadonotakashi | 0:8fdf9a60065b | 591 | * | | |10 = EPWM compare up point output High. |
kadonotakashi | 0:8fdf9a60065b | 592 | * | | |11 = EPWM compare up point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 593 | * | | |EPWM can control output level when EPWM counter up count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 594 | * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 595 | * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control |
kadonotakashi | 0:8fdf9a60065b | 596 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 597 | * | | |01 = EPWM compare up point output Low. |
kadonotakashi | 0:8fdf9a60065b | 598 | * | | |10 = EPWM compare up point output High. |
kadonotakashi | 0:8fdf9a60065b | 599 | * | | |11 = EPWM compare up point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 600 | * | | |EPWM can control output level when EPWM counter up count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 601 | * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 602 | * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control |
kadonotakashi | 0:8fdf9a60065b | 603 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 604 | * | | |01 = EPWM compare up point output Low. |
kadonotakashi | 0:8fdf9a60065b | 605 | * | | |10 = EPWM compare up point output High. |
kadonotakashi | 0:8fdf9a60065b | 606 | * | | |11 = EPWM compare up point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 607 | * | | |EPWM can control output level when EPWM counter up count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 608 | * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 609 | * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control |
kadonotakashi | 0:8fdf9a60065b | 610 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 611 | * | | |01 = EPWM compare down point output Low. |
kadonotakashi | 0:8fdf9a60065b | 612 | * | | |10 = EPWM compare down point output High. |
kadonotakashi | 0:8fdf9a60065b | 613 | * | | |11 = EPWM compare down point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 614 | * | | |EPWM can control output level when EPWM counter down count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 615 | * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 616 | * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control |
kadonotakashi | 0:8fdf9a60065b | 617 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 618 | * | | |01 = EPWM compare down point output Low. |
kadonotakashi | 0:8fdf9a60065b | 619 | * | | |10 = EPWM compare down point output High. |
kadonotakashi | 0:8fdf9a60065b | 620 | * | | |11 = EPWM compare down point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 621 | * | | |EPWM can control output level when EPWM counter down count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 622 | * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 623 | * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control |
kadonotakashi | 0:8fdf9a60065b | 624 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 625 | * | | |01 = EPWM compare down point output Low. |
kadonotakashi | 0:8fdf9a60065b | 626 | * | | |10 = EPWM compare down point output High. |
kadonotakashi | 0:8fdf9a60065b | 627 | * | | |11 = EPWM compare down point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 628 | * | | |EPWM can control output level when EPWM counter down count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 629 | * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 630 | * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control |
kadonotakashi | 0:8fdf9a60065b | 631 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 632 | * | | |01 = EPWM compare down point output Low. |
kadonotakashi | 0:8fdf9a60065b | 633 | * | | |10 = EPWM compare down point output High. |
kadonotakashi | 0:8fdf9a60065b | 634 | * | | |11 = EPWM compare down point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 635 | * | | |EPWM can control output level when EPWM counter down count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 636 | * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 637 | * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control |
kadonotakashi | 0:8fdf9a60065b | 638 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 639 | * | | |01 = EPWM compare down point output Low. |
kadonotakashi | 0:8fdf9a60065b | 640 | * | | |10 = EPWM compare down point output High. |
kadonotakashi | 0:8fdf9a60065b | 641 | * | | |11 = EPWM compare down point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 642 | * | | |EPWM can control output level when EPWM counter down count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 643 | * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 644 | * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control |
kadonotakashi | 0:8fdf9a60065b | 645 | * | | |00 = Do nothing. |
kadonotakashi | 0:8fdf9a60065b | 646 | * | | |01 = EPWM compare down point output Low. |
kadonotakashi | 0:8fdf9a60065b | 647 | * | | |10 = EPWM compare down point output High. |
kadonotakashi | 0:8fdf9a60065b | 648 | * | | |11 = EPWM compare down point output Toggle. |
kadonotakashi | 0:8fdf9a60065b | 649 | * | | |EPWM can control output level when EPWM counter down count to CMPDAT. |
kadonotakashi | 0:8fdf9a60065b | 650 | * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 651 | * @var EPWM_T::MSKEN |
kadonotakashi | 0:8fdf9a60065b | 652 | * Offset: 0xB8 EPWM Mask Enable Register |
kadonotakashi | 0:8fdf9a60065b | 653 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 654 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 655 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 656 | * |[0] |MSKEN0 |EPWM Mask Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 657 | * | | |The EPWM output signal will be masked when this bit is enabled. |
kadonotakashi | 0:8fdf9a60065b | 658 | * | | |The corresponding EPWM channel 0 will output MSKDAT0 (EPWM_MSK[5:0]) data. |
kadonotakashi | 0:8fdf9a60065b | 659 | * | | |0 = EPWM output signal is non-masked. |
kadonotakashi | 0:8fdf9a60065b | 660 | * | | |1 = EPWM output signal is masked and output MSKDAT0 data. |
kadonotakashi | 0:8fdf9a60065b | 661 | * |[1] |MSKEN1 |EPWM Mask Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 662 | * | | |The EPWM output signal will be masked when this bit is enabled. |
kadonotakashi | 0:8fdf9a60065b | 663 | * | | |The corresponding EPWM channel 1 will output MSKDAT1 (EPWM_MSK[5:0]) data. |
kadonotakashi | 0:8fdf9a60065b | 664 | * | | |0 = EPWM output signal is non-masked. |
kadonotakashi | 0:8fdf9a60065b | 665 | * | | |1 = EPWM output signal is masked and output MSKDAT1 data. |
kadonotakashi | 0:8fdf9a60065b | 666 | * |[2] |MSKEN2 |EPWM Mask Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 667 | * | | |The EPWM output signal will be masked when this bit is enabled. |
kadonotakashi | 0:8fdf9a60065b | 668 | * | | |The corresponding EPWM channel 2 will output MSKDAT2 (EPWM_MSK[5:0]) data. |
kadonotakashi | 0:8fdf9a60065b | 669 | * | | |0 = EPWM output signal is non-masked. |
kadonotakashi | 0:8fdf9a60065b | 670 | * | | |1 = EPWM output signal is masked and output MSKDAT2 data. |
kadonotakashi | 0:8fdf9a60065b | 671 | * |[3] |MSKEN3 |EPWM Mask Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 672 | * | | |The EPWM output signal will be masked when this bit is enabled. |
kadonotakashi | 0:8fdf9a60065b | 673 | * | | |The corresponding EPWM channel 3 will output MSKDAT3 (EPWM_MSK[5:0]) data. |
kadonotakashi | 0:8fdf9a60065b | 674 | * | | |0 = EPWM output signal is non-masked. |
kadonotakashi | 0:8fdf9a60065b | 675 | * | | |1 = EPWM output signal is masked and output MSKDAT3 data. |
kadonotakashi | 0:8fdf9a60065b | 676 | * |[4] |MSKEN4 |EPWM Mask Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 677 | * | | |The EPWM output signal will be masked when this bit is enabled. |
kadonotakashi | 0:8fdf9a60065b | 678 | * | | |The corresponding EPWM channel 4 will output MSKDAT4 (EPWM_MSK[5:0]) data. |
kadonotakashi | 0:8fdf9a60065b | 679 | * | | |0 = EPWM output signal is non-masked. |
kadonotakashi | 0:8fdf9a60065b | 680 | * | | |1 = EPWM output signal is masked and output MSKDAT4 data. |
kadonotakashi | 0:8fdf9a60065b | 681 | * |[5] |MSKEN5 |EPWM Mask Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 682 | * | | |The EPWM output signal will be masked when this bit is enabled. |
kadonotakashi | 0:8fdf9a60065b | 683 | * | | |The corresponding EPWM channel 5 will output MSKDAT5 (EPWM_MSK[5:0]) data. |
kadonotakashi | 0:8fdf9a60065b | 684 | * | | |0 = EPWM output signal is non-masked. |
kadonotakashi | 0:8fdf9a60065b | 685 | * | | |1 = EPWM output signal is masked and output MSKDAT5 data. |
kadonotakashi | 0:8fdf9a60065b | 686 | * @var EPWM_T::MSK |
kadonotakashi | 0:8fdf9a60065b | 687 | * Offset: 0xBC EPWM Mask Data Register |
kadonotakashi | 0:8fdf9a60065b | 688 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 689 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 690 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 691 | * |[0] |MSKDAT0 |EPWM Mask Data Bit |
kadonotakashi | 0:8fdf9a60065b | 692 | * | | |This data bit control the state of EPWM_CH0 output pin, if corresponding mask function is enabled. |
kadonotakashi | 0:8fdf9a60065b | 693 | * | | |0 = Output logic low to EPWM_CH0. |
kadonotakashi | 0:8fdf9a60065b | 694 | * | | |1 = Output logic high to EPWM_CH0. |
kadonotakashi | 0:8fdf9a60065b | 695 | * |[1] |MSKDAT1 |EPWM Mask Data Bit |
kadonotakashi | 0:8fdf9a60065b | 696 | * | | |This data bit control the state of EPWM_CH1 output pin, if corresponding mask function is enabled. |
kadonotakashi | 0:8fdf9a60065b | 697 | * | | |0 = Output logic low to EPWM_CH1. |
kadonotakashi | 0:8fdf9a60065b | 698 | * | | |1 = Output logic high to EPWM_CH1. |
kadonotakashi | 0:8fdf9a60065b | 699 | * |[2] |MSKDAT2 |EPWM Mask Data Bit |
kadonotakashi | 0:8fdf9a60065b | 700 | * | | |This data bit control the state of EPWM_CH2 output pin, if corresponding mask function is enabled. |
kadonotakashi | 0:8fdf9a60065b | 701 | * | | |0 = Output logic low to EPWM_CH2. |
kadonotakashi | 0:8fdf9a60065b | 702 | * | | |1 = Output logic high to EPWM_CH2. |
kadonotakashi | 0:8fdf9a60065b | 703 | * |[3] |MSKDAT3 |EPWM Mask Data Bit |
kadonotakashi | 0:8fdf9a60065b | 704 | * | | |This data bit control the state of EPWM_CH3 output pin, if corresponding mask function is enabled. |
kadonotakashi | 0:8fdf9a60065b | 705 | * | | |0 = Output logic low to EPWM_CH3. |
kadonotakashi | 0:8fdf9a60065b | 706 | * | | |1 = Output logic high to EPWM_CH3. |
kadonotakashi | 0:8fdf9a60065b | 707 | * |[4] |MSKDAT4 |EPWM Mask Data Bit |
kadonotakashi | 0:8fdf9a60065b | 708 | * | | |This data bit control the state of EPWM_CH4 output pin, if corresponding mask function is enabled. |
kadonotakashi | 0:8fdf9a60065b | 709 | * | | |0 = Output logic low to EPWM_CH4. |
kadonotakashi | 0:8fdf9a60065b | 710 | * | | |1 = Output logic high to EPWM_CH4. |
kadonotakashi | 0:8fdf9a60065b | 711 | * |[5] |MSKDAT5 |EPWM Mask Data Bit |
kadonotakashi | 0:8fdf9a60065b | 712 | * | | |This data bit control the state of EPWM_CH5 output pin, if corresponding mask function is enabled. |
kadonotakashi | 0:8fdf9a60065b | 713 | * | | |0 = Output logic low to EPWM_CH5. |
kadonotakashi | 0:8fdf9a60065b | 714 | * | | |1 = Output logic high to EPWM_CH5. |
kadonotakashi | 0:8fdf9a60065b | 715 | * @var EPWM_T::BNF |
kadonotakashi | 0:8fdf9a60065b | 716 | * Offset: 0xC0 EPWM Brake Noise Filter Register |
kadonotakashi | 0:8fdf9a60065b | 717 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 718 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 719 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 720 | * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 721 | * | | |0 = Noise filter of EPWM Brake 0 Disabled. |
kadonotakashi | 0:8fdf9a60065b | 722 | * | | |1 = Noise filter of EPWM Brake 0 Enabled. |
kadonotakashi | 0:8fdf9a60065b | 723 | * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection |
kadonotakashi | 0:8fdf9a60065b | 724 | * | | |000 = Filter clock = HCLK. |
kadonotakashi | 0:8fdf9a60065b | 725 | * | | |001 = Filter clock = HCLK/2. |
kadonotakashi | 0:8fdf9a60065b | 726 | * | | |010 = Filter clock = HCLK/4. |
kadonotakashi | 0:8fdf9a60065b | 727 | * | | |011 = Filter clock = HCLK/8. |
kadonotakashi | 0:8fdf9a60065b | 728 | * | | |100 = Filter clock = HCLK/16. |
kadonotakashi | 0:8fdf9a60065b | 729 | * | | |101 = Filter clock = HCLK/32. |
kadonotakashi | 0:8fdf9a60065b | 730 | * | | |110 = Filter clock = HCLK/64. |
kadonotakashi | 0:8fdf9a60065b | 731 | * | | |111 = Filter clock = HCLK/128. |
kadonotakashi | 0:8fdf9a60065b | 732 | * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count |
kadonotakashi | 0:8fdf9a60065b | 733 | * | | |The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT. |
kadonotakashi | 0:8fdf9a60065b | 734 | * |[7] |BRK0PINV |Brake 0 Pin Inverse |
kadonotakashi | 0:8fdf9a60065b | 735 | * | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector. |
kadonotakashi | 0:8fdf9a60065b | 736 | * | | |1 = The inversed state of pin EPWMx_BRAKE0 is passed to the negative edge detector. |
kadonotakashi | 0:8fdf9a60065b | 737 | * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 738 | * | | |0 = Noise filter of EPWM Brake 1 Disabled. |
kadonotakashi | 0:8fdf9a60065b | 739 | * | | |1 = Noise filter of EPWM Brake 1 Enabled. |
kadonotakashi | 0:8fdf9a60065b | 740 | * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection |
kadonotakashi | 0:8fdf9a60065b | 741 | * | | |000 = Filter clock = HCLK. |
kadonotakashi | 0:8fdf9a60065b | 742 | * | | |001 = Filter clock = HCLK/2. |
kadonotakashi | 0:8fdf9a60065b | 743 | * | | |010 = Filter clock = HCLK/4. |
kadonotakashi | 0:8fdf9a60065b | 744 | * | | |011 = Filter clock = HCLK/8. |
kadonotakashi | 0:8fdf9a60065b | 745 | * | | |100 = Filter clock = HCLK/16. |
kadonotakashi | 0:8fdf9a60065b | 746 | * | | |101 = Filter clock = HCLK/32. |
kadonotakashi | 0:8fdf9a60065b | 747 | * | | |110 = Filter clock = HCLK/64. |
kadonotakashi | 0:8fdf9a60065b | 748 | * | | |111 = Filter clock = HCLK/128. |
kadonotakashi | 0:8fdf9a60065b | 749 | * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count |
kadonotakashi | 0:8fdf9a60065b | 750 | * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. |
kadonotakashi | 0:8fdf9a60065b | 751 | * |[15] |BRK1PINV |Brake 1 Pin Inverse |
kadonotakashi | 0:8fdf9a60065b | 752 | * | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector. |
kadonotakashi | 0:8fdf9a60065b | 753 | * | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector. |
kadonotakashi | 0:8fdf9a60065b | 754 | * |[16] |BK0SRC |Brake 0 Pin Source Select |
kadonotakashi | 0:8fdf9a60065b | 755 | * | | |For EPWM0 setting: |
kadonotakashi | 0:8fdf9a60065b | 756 | * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0. |
kadonotakashi | 0:8fdf9a60065b | 757 | * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0. |
kadonotakashi | 0:8fdf9a60065b | 758 | * | | |For EPWM1 setting: |
kadonotakashi | 0:8fdf9a60065b | 759 | * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0. |
kadonotakashi | 0:8fdf9a60065b | 760 | * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. |
kadonotakashi | 0:8fdf9a60065b | 761 | * |[24] |BK1SRC |Brake 1 Pin Source Select |
kadonotakashi | 0:8fdf9a60065b | 762 | * | | |For EPWM0 setting: |
kadonotakashi | 0:8fdf9a60065b | 763 | * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1. |
kadonotakashi | 0:8fdf9a60065b | 764 | * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1. |
kadonotakashi | 0:8fdf9a60065b | 765 | * | | |For EPWM1 setting: |
kadonotakashi | 0:8fdf9a60065b | 766 | * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1. |
kadonotakashi | 0:8fdf9a60065b | 767 | * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. |
kadonotakashi | 0:8fdf9a60065b | 768 | * @var EPWM_T::FAILBRK |
kadonotakashi | 0:8fdf9a60065b | 769 | * Offset: 0xC4 EPWM System Fail Brake Control Register |
kadonotakashi | 0:8fdf9a60065b | 770 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 771 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 772 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 773 | * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 774 | * | | |0 = Brake Function triggered by CSS detection Disabled. |
kadonotakashi | 0:8fdf9a60065b | 775 | * | | |1 = Brake Function triggered by CSS detection Enabled. |
kadonotakashi | 0:8fdf9a60065b | 776 | * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 777 | * | | |0 = Brake Function triggered by BOD Disabled. |
kadonotakashi | 0:8fdf9a60065b | 778 | * | | |1 = Brake Function triggered by BOD Enabled. |
kadonotakashi | 0:8fdf9a60065b | 779 | * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 780 | * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. |
kadonotakashi | 0:8fdf9a60065b | 781 | * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. |
kadonotakashi | 0:8fdf9a60065b | 782 | * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 783 | * | | |0 = Brake Function triggered by Core lockup detection Disabled. |
kadonotakashi | 0:8fdf9a60065b | 784 | * | | |1 = Brake Function triggered by Core lockup detection Enabled. |
kadonotakashi | 0:8fdf9a60065b | 785 | * @var EPWM_T::BRKCTL[3] |
kadonotakashi | 0:8fdf9a60065b | 786 | * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 |
kadonotakashi | 0:8fdf9a60065b | 787 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 788 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 789 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 790 | * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 791 | * | | |0 = ACMP0_O as edge-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 792 | * | | |1 = ACMP0_O as edge-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 793 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 794 | * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 795 | * | | |0 = ACMP1_O as edge-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 796 | * | | |1 = ACMP1_O as edge-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 797 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 798 | * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 799 | * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 800 | * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 801 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 802 | * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 803 | * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 804 | * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 805 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 806 | * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 807 | * | | |0 = System Fail condition as edge-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 808 | * | | |1 = System Fail condition as edge-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 809 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 810 | * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 811 | * | | |0 = ACMP0_O as level-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 812 | * | | |1 = ACMP0_O as level-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 813 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 814 | * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 815 | * | | |0 = ACMP1_O as level-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 816 | * | | |1 = ACMP1_O as level-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 817 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 818 | * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 819 | * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 820 | * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 821 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 822 | * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 823 | * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 824 | * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 825 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 826 | * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 827 | * | | |0 = System Fail condition as level-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 828 | * | | |1 = System Fail condition as level-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 829 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 830 | * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 831 | * | | |00 = EPWMx brake event will not affect even channels output. |
kadonotakashi | 0:8fdf9a60065b | 832 | * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. |
kadonotakashi | 0:8fdf9a60065b | 833 | * | | |10 = EPWM even channel output low level when EPWMx brake event happened. |
kadonotakashi | 0:8fdf9a60065b | 834 | * | | |11 = EPWM even channel output high level when EPWMx brake event happened. |
kadonotakashi | 0:8fdf9a60065b | 835 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 836 | * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 837 | * | | |00 = EPWMx brake event will not affect odd channels output. |
kadonotakashi | 0:8fdf9a60065b | 838 | * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. |
kadonotakashi | 0:8fdf9a60065b | 839 | * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. |
kadonotakashi | 0:8fdf9a60065b | 840 | * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. |
kadonotakashi | 0:8fdf9a60065b | 841 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 842 | * |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 843 | * | | |0 = EADCRM as edge-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 844 | * | | |1 = EADCRM as edge-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 845 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 846 | * |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 847 | * | | |0 = EADCRM as level-detect brake source Disabled. |
kadonotakashi | 0:8fdf9a60065b | 848 | * | | |1 = EADCRM as level-detect brake source Enabled. |
kadonotakashi | 0:8fdf9a60065b | 849 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 850 | * @var EPWM_T::POLCTL |
kadonotakashi | 0:8fdf9a60065b | 851 | * Offset: 0xD4 EPWM Pin Polar Inverse Register |
kadonotakashi | 0:8fdf9a60065b | 852 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 853 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 854 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 855 | * |[0] |PINV0 |EPWM_CH0 PIN Polar Inverse Control |
kadonotakashi | 0:8fdf9a60065b | 856 | * | | |The register controls polarity state of EPWM_CH0 output. |
kadonotakashi | 0:8fdf9a60065b | 857 | * | | |0 = EPWM_CH0 output polar inverse Disabled. |
kadonotakashi | 0:8fdf9a60065b | 858 | * | | |1 = EPWM_CH0 output polar inverse Enabled. |
kadonotakashi | 0:8fdf9a60065b | 859 | * |[1] |PINV1 |EPWM_CH1 PIN Polar Inverse Control |
kadonotakashi | 0:8fdf9a60065b | 860 | * | | |The register controls polarity state of EPWM_CH1 output. |
kadonotakashi | 0:8fdf9a60065b | 861 | * | | |0 = EPWM_CH1 output polar inverse Disabled. |
kadonotakashi | 0:8fdf9a60065b | 862 | * | | |1 = EPWM_CH1 output polar inverse Enabled. |
kadonotakashi | 0:8fdf9a60065b | 863 | * |[2] |PINV2 |EPWM_CH2 PIN Polar Inverse Control |
kadonotakashi | 0:8fdf9a60065b | 864 | * | | |The register controls polarity state of EPWM_CH2 output. |
kadonotakashi | 0:8fdf9a60065b | 865 | * | | |0 = EPWM_CH2 output polar inverse Disabled. |
kadonotakashi | 0:8fdf9a60065b | 866 | * | | |1 = EPWM_CH2 output polar inverse Enabled. |
kadonotakashi | 0:8fdf9a60065b | 867 | * |[3] |PINV3 |EPWM_CH3 PIN Polar Inverse Control |
kadonotakashi | 0:8fdf9a60065b | 868 | * | | |The register controls polarity state of EPWM_CH3 output. |
kadonotakashi | 0:8fdf9a60065b | 869 | * | | |0 = EPWM_CH3 output polar inverse Disabled. |
kadonotakashi | 0:8fdf9a60065b | 870 | * | | |1 = EPWM_CH3 output polar inverse Enabled. |
kadonotakashi | 0:8fdf9a60065b | 871 | * |[4] |PINV4 |EPWM_CH4 PIN Polar Inverse Control |
kadonotakashi | 0:8fdf9a60065b | 872 | * | | |The register controls polarity state of EPWM_CH4 output. |
kadonotakashi | 0:8fdf9a60065b | 873 | * | | |0 = EPWM_CH4 output polar inverse Disabled. |
kadonotakashi | 0:8fdf9a60065b | 874 | * | | |1 = EPWM_CH4 output polar inverse Enabled. |
kadonotakashi | 0:8fdf9a60065b | 875 | * |[5] |PINV5 |EPWM_CH5 PIN Polar Inverse Control |
kadonotakashi | 0:8fdf9a60065b | 876 | * | | |The register controls polarity state of EPWM_CH5 output. |
kadonotakashi | 0:8fdf9a60065b | 877 | * | | |0 = EPWM_CH5 output polar inverse Disabled. |
kadonotakashi | 0:8fdf9a60065b | 878 | * | | |1 = EPWM_CH5 output polar inverse Enabled. |
kadonotakashi | 0:8fdf9a60065b | 879 | * @var EPWM_T::POEN |
kadonotakashi | 0:8fdf9a60065b | 880 | * Offset: 0xD8 EPWM Output Enable Register |
kadonotakashi | 0:8fdf9a60065b | 881 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 882 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 883 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 884 | * |[0] |POEN0 |EPWM_CH0 Pin Output Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 885 | * | | |0 = EPWM_CH0 pin at tri-state. |
kadonotakashi | 0:8fdf9a60065b | 886 | * | | |1 = EPWM_CH0 pin in output mode. |
kadonotakashi | 0:8fdf9a60065b | 887 | * |[1] |POEN1 |EPWM_CH1 Pin Output Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 888 | * | | |0 = EPWM_CH1 pin at tri-state. |
kadonotakashi | 0:8fdf9a60065b | 889 | * | | |1 = EPWM_CH1 pin in output mode. |
kadonotakashi | 0:8fdf9a60065b | 890 | * |[2] |POEN2 |EPWM_CH2 Pin Output Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 891 | * | | |0 = EPWM_CH2 pin at tri-state. |
kadonotakashi | 0:8fdf9a60065b | 892 | * | | |1 = EPWM_CH2 pin in output mode. |
kadonotakashi | 0:8fdf9a60065b | 893 | * |[3] |POEN3 |EPWM_CH3 Pin Output Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 894 | * | | |0 = EPWM_CH3 pin at tri-state. |
kadonotakashi | 0:8fdf9a60065b | 895 | * | | |1 = EPWM_CH3 pin in output mode. |
kadonotakashi | 0:8fdf9a60065b | 896 | * |[4] |POEN4 |EPWM_CH4 Pin Output Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 897 | * | | |0 = EPWM_CH4 pin at tri-state. |
kadonotakashi | 0:8fdf9a60065b | 898 | * | | |1 = EPWM_CH4 pin in output mode. |
kadonotakashi | 0:8fdf9a60065b | 899 | * |[5] |POEN5 |EPWM_CH5 Pin Output Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 900 | * | | |0 = EPWM_CH5 pin at tri-state. |
kadonotakashi | 0:8fdf9a60065b | 901 | * | | |1 = EPWM_CH5 pin in output mode. |
kadonotakashi | 0:8fdf9a60065b | 902 | * @var EPWM_T::SWBRK |
kadonotakashi | 0:8fdf9a60065b | 903 | * Offset: 0xDC EPWM Software Brake Control Register |
kadonotakashi | 0:8fdf9a60065b | 904 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 905 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 906 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 907 | * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 908 | * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF0 to 1 in EPWM_INTSTS1 register. |
kadonotakashi | 0:8fdf9a60065b | 909 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 910 | * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 911 | * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF2 to 1 in EPWM_INTSTS1 register. |
kadonotakashi | 0:8fdf9a60065b | 912 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 913 | * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 914 | * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF4 to 1 in EPWM_INTSTS1 register. |
kadonotakashi | 0:8fdf9a60065b | 915 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 916 | * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 917 | * | | |Write 1 to this bit will trigger level brake, and set BRKLIF0 to 1 in EPWM_INTSTS1 register. |
kadonotakashi | 0:8fdf9a60065b | 918 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 919 | * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 920 | * | | |Write 1 to this bit will trigger level brake, and set BRKLIF2 to 1 in EPWM_INTSTS1 register. |
kadonotakashi | 0:8fdf9a60065b | 921 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 922 | * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 923 | * | | |Write 1 to this bit will trigger level brake, and set BRKLIF4 to 1 in EPWM_INTSTS1 register. |
kadonotakashi | 0:8fdf9a60065b | 924 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 925 | * @var EPWM_T::INTEN0 |
kadonotakashi | 0:8fdf9a60065b | 926 | * Offset: 0xE0 EPWM Interrupt Enable Register 0 |
kadonotakashi | 0:8fdf9a60065b | 927 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 928 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 929 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 930 | * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 931 | * | | |0 = Zero point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 932 | * | | |1 = Zero point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 933 | * | | |Note: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 934 | * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 935 | * | | |0 = Zero point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 936 | * | | |1 = Zero point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 937 | * | | |Note: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 938 | * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 939 | * | | |0 = Zero point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 940 | * | | |1 = Zero point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 941 | * | | |Note: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 942 | * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 943 | * | | |0 = Zero point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 944 | * | | |1 = Zero point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 945 | * | | |Note: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 946 | * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 947 | * | | |0 = Zero point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 948 | * | | |1 = Zero point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 949 | * | | |Note: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 950 | * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 951 | * | | |0 = Zero point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 952 | * | | |1 = Zero point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 953 | * | | |Note: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 954 | * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 955 | * | | |0 = Period point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 956 | * | | |1 = Period point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 957 | * | | |Note1: When up-down counter type period point means center point. |
kadonotakashi | 0:8fdf9a60065b | 958 | * | | |Note2: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 959 | * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 960 | * | | |0 = Period point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 961 | * | | |1 = Period point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 962 | * | | |Note1: When up-down counter type period point means center point. |
kadonotakashi | 0:8fdf9a60065b | 963 | * | | |Note2: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 964 | * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 965 | * | | |0 = Period point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 966 | * | | |1 = Period point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 967 | * | | |Note1: When up-down counter type period point means center point. |
kadonotakashi | 0:8fdf9a60065b | 968 | * | | |Note2: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 969 | * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 970 | * | | |0 = Period point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 971 | * | | |1 = Period point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 972 | * | | |Note1: When up-down counter type period point means center point. |
kadonotakashi | 0:8fdf9a60065b | 973 | * | | |Note2: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 974 | * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 975 | * | | |0 = Period point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 976 | * | | |1 = Period point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 977 | * | | |Note1: When up-down counter type period point means center point. |
kadonotakashi | 0:8fdf9a60065b | 978 | * | | |Note2: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 979 | * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 980 | * | | |0 = Period point interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 981 | * | | |1 = Period point interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 982 | * | | |Note1: When up-down counter type period point means center point. |
kadonotakashi | 0:8fdf9a60065b | 983 | * | | |Note2: Odd channels will read always 0 at complementary mode. |
kadonotakashi | 0:8fdf9a60065b | 984 | * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 985 | * | | |0 = Compare up count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 986 | * | | |1 = Compare up count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 987 | * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 988 | * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 989 | * | | |0 = Compare up count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 990 | * | | |1 = Compare up count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 991 | * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 992 | * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 993 | * | | |0 = Compare up count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 994 | * | | |1 = Compare up count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 995 | * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 996 | * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 997 | * | | |0 = Compare up count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 998 | * | | |1 = Compare up count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 999 | * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1000 | * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1001 | * | | |0 = Compare up count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1002 | * | | |1 = Compare up count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1003 | * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1004 | * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1005 | * | | |0 = Compare up count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1006 | * | | |1 = Compare up count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1007 | * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1008 | * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1009 | * | | |0 = Compare down count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1010 | * | | |1 = Compare down count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1011 | * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1012 | * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1013 | * | | |0 = Compare down count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1014 | * | | |1 = Compare down count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1015 | * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1016 | * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1017 | * | | |0 = Compare down count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1018 | * | | |1 = Compare down count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1019 | * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1020 | * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1021 | * | | |0 = Compare down count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1022 | * | | |1 = Compare down count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1023 | * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1024 | * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1025 | * | | |0 = Compare down count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1026 | * | | |1 = Compare down count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1027 | * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1028 | * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1029 | * | | |0 = Compare down count interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1030 | * | | |1 = Compare down count interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1031 | * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1032 | * @var EPWM_T::INTEN1 |
kadonotakashi | 0:8fdf9a60065b | 1033 | * Offset: 0xE4 EPWM Interrupt Enable Register 1 |
kadonotakashi | 0:8fdf9a60065b | 1034 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1035 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1036 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1037 | * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1038 | * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1039 | * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1040 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1041 | * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1042 | * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1043 | * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1044 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1045 | * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1046 | * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1047 | * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1048 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1049 | * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1050 | * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1051 | * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1052 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1053 | * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1054 | * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1055 | * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1056 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1057 | * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1058 | * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1059 | * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1060 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1061 | * @var EPWM_T::INTSTS0 |
kadonotakashi | 0:8fdf9a60065b | 1062 | * Offset: 0xE8 EPWM Interrupt Flag Register 0 |
kadonotakashi | 0:8fdf9a60065b | 1063 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1064 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1065 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1066 | * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1067 | * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. |
kadonotakashi | 0:8fdf9a60065b | 1068 | * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1069 | * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. |
kadonotakashi | 0:8fdf9a60065b | 1070 | * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1071 | * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. |
kadonotakashi | 0:8fdf9a60065b | 1072 | * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1073 | * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. |
kadonotakashi | 0:8fdf9a60065b | 1074 | * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1075 | * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. |
kadonotakashi | 0:8fdf9a60065b | 1076 | * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1077 | * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. |
kadonotakashi | 0:8fdf9a60065b | 1078 | * |[8] |PIF0 |EPWM Period Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1079 | * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD0, software can write 1 to clear this bit to zero |
kadonotakashi | 0:8fdf9a60065b | 1080 | * |[9] |PIF1 |EPWM Period Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1081 | * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD1, software can write 1 to clear this bit to zero |
kadonotakashi | 0:8fdf9a60065b | 1082 | * |[10] |PIF2 |EPWM Period Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1083 | * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD2, software can write 1 to clear this bit to zero |
kadonotakashi | 0:8fdf9a60065b | 1084 | * |[11] |PIF3 |EPWM Period Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1085 | * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD4, software can write 1 to clear this bit to zero |
kadonotakashi | 0:8fdf9a60065b | 1086 | * |[12] |PIF4 |EPWM Period Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1087 | * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD5, software can write 1 to clear this bit to zero |
kadonotakashi | 0:8fdf9a60065b | 1088 | * |[13] |PIF5 |EPWM Period Point Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1089 | * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. |
kadonotakashi | 0:8fdf9a60065b | 1090 | * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1091 | * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1092 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1093 | * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1094 | * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1095 | * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1096 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1097 | * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1098 | * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1099 | * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1100 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1101 | * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1102 | * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1103 | * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1104 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1105 | * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1106 | * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1107 | * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1108 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1109 | * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1110 | * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1111 | * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1112 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1113 | * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1114 | * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1115 | * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1116 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1117 | * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1118 | * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1119 | * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1120 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1121 | * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1122 | * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1123 | * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1124 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1125 | * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1126 | * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1127 | * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1128 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1129 | * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1130 | * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1131 | * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1132 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1133 | * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1134 | * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1135 | * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1136 | * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. |
kadonotakashi | 0:8fdf9a60065b | 1137 | * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1138 | * @var EPWM_T::INTSTS1 |
kadonotakashi | 0:8fdf9a60065b | 1139 | * Offset: 0xEC EPWM Interrupt Flag Register 1 |
kadonotakashi | 0:8fdf9a60065b | 1140 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1141 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1142 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1143 | * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1144 | * | | |0 = EPWM channel0 edge-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1145 | * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1146 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1147 | * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1148 | * | | |0 = EPWM channel1 edge-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1149 | * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1150 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1151 | * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1152 | * | | |0 = EPWM channel2 edge-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1153 | * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1154 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1155 | * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1156 | * | | |0 = EPWM channel3 edge-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1157 | * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1158 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1159 | * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1160 | * | | |0 = EPWM channel4 edge-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1161 | * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1162 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1163 | * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1164 | * | | |0 = EPWM channel5 edge-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1165 | * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1166 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1167 | * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1168 | * | | |0 = EPWM channel0 level-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1169 | * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1170 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1171 | * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1172 | * | | |0 = EPWM channel1 level-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1173 | * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1174 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1175 | * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1176 | * | | |0 = EPWM channel2 level-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1177 | * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1178 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1179 | * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1180 | * | | |0 = EPWM channel3 level-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1181 | * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1182 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1183 | * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1184 | * | | |0 = EPWM channel4 level-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1185 | * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1186 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1187 | * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect) |
kadonotakashi | 0:8fdf9a60065b | 1188 | * | | |0 = EPWM channel5 level-detect brake event do not happened. |
kadonotakashi | 0:8fdf9a60065b | 1189 | * | | |1 = When EPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1190 | * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. |
kadonotakashi | 0:8fdf9a60065b | 1191 | * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1192 | * | | |0 = EPWM channel0 edge-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1193 | * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1194 | * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1195 | * | | |0 = EPWM channel1 edge-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1196 | * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1197 | * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1198 | * | | |0 = EPWM channel2 edge-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1199 | * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1200 | * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1201 | * | | |0 = EPWM channel3 edge-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1202 | * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1203 | * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1204 | * | | |0 = EPWM channel4 edge-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1205 | * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1206 | * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1207 | * | | |0 = EPWM channel5 edge-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1208 | * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1209 | * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1210 | * | | |0 = EPWM channel0 level-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1211 | * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state. |
kadonotakashi | 0:8fdf9a60065b | 1212 | * | | |Note: This bit is read only and auto cleared by hardware |
kadonotakashi | 0:8fdf9a60065b | 1213 | * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished |
kadonotakashi | 0:8fdf9a60065b | 1214 | * | | |The EPWM waveform will start output from next full EPWM period. |
kadonotakashi | 0:8fdf9a60065b | 1215 | * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1216 | * | | |0 = EPWM channel1 level-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1217 | * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state. |
kadonotakashi | 0:8fdf9a60065b | 1218 | * | | |Note: This bit is read only and auto cleared by hardware |
kadonotakashi | 0:8fdf9a60065b | 1219 | * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished |
kadonotakashi | 0:8fdf9a60065b | 1220 | * | | |The EPWM waveform will start output from next full EPWM period. |
kadonotakashi | 0:8fdf9a60065b | 1221 | * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1222 | * | | |0 = EPWM channel2 level-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1223 | * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state. |
kadonotakashi | 0:8fdf9a60065b | 1224 | * | | |Note: This bit is read only and auto cleared by hardware |
kadonotakashi | 0:8fdf9a60065b | 1225 | * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished |
kadonotakashi | 0:8fdf9a60065b | 1226 | * | | |The EPWM waveform will start output from next full EPWM period. |
kadonotakashi | 0:8fdf9a60065b | 1227 | * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1228 | * | | |0 = EPWM channel3 level-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1229 | * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state. |
kadonotakashi | 0:8fdf9a60065b | 1230 | * | | |Note: This bit is read only and auto cleared by hardware |
kadonotakashi | 0:8fdf9a60065b | 1231 | * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished |
kadonotakashi | 0:8fdf9a60065b | 1232 | * | | |The EPWM waveform will start output from next full EPWM period. |
kadonotakashi | 0:8fdf9a60065b | 1233 | * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1234 | * | | |0 = EPWM channel4 level-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1235 | * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state. |
kadonotakashi | 0:8fdf9a60065b | 1236 | * | | |Note: This bit is read only and auto cleared by hardware |
kadonotakashi | 0:8fdf9a60065b | 1237 | * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished |
kadonotakashi | 0:8fdf9a60065b | 1238 | * | | |The EPWM waveform will start output from next full EPWM period. |
kadonotakashi | 0:8fdf9a60065b | 1239 | * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1240 | * | | |0 = EPWM channel5 level-detect brake state is released. |
kadonotakashi | 0:8fdf9a60065b | 1241 | * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state. |
kadonotakashi | 0:8fdf9a60065b | 1242 | * | | |Note: This bit is read only and auto cleared by hardware |
kadonotakashi | 0:8fdf9a60065b | 1243 | * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished |
kadonotakashi | 0:8fdf9a60065b | 1244 | * | | |The EPWM waveform will start output from next full EPWM period. |
kadonotakashi | 0:8fdf9a60065b | 1245 | * @var EPWM_T::DACTRGEN |
kadonotakashi | 0:8fdf9a60065b | 1246 | * Offset: 0xF4 EPWM Trigger DAC Enable Register |
kadonotakashi | 0:8fdf9a60065b | 1247 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1248 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1249 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1250 | * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1251 | * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1252 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1253 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1254 | * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1255 | * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1256 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1257 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1258 | * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1259 | * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1260 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1261 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1262 | * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1263 | * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1264 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1265 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1266 | * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1267 | * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1268 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1269 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1270 | * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1271 | * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1272 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1273 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1274 | * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1275 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1276 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1277 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1278 | * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1279 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1280 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1281 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1282 | * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1283 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1284 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1285 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1286 | * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1287 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1288 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1289 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1290 | * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1291 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1292 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1293 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1294 | * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1295 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1296 | * | | |0 = EPWM period point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1297 | * | | |1 = EPWM period point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1298 | * |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1299 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1300 | * | | |0 = EPWM Compare Up point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1301 | * | | |1 = EPWM Compare Up point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1302 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. |
kadonotakashi | 0:8fdf9a60065b | 1303 | * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1304 | * |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1305 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1306 | * | | |0 = EPWM Compare Up point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1307 | * | | |1 = EPWM Compare Up point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1308 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. |
kadonotakashi | 0:8fdf9a60065b | 1309 | * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1310 | * |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1311 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1312 | * | | |0 = EPWM Compare Up point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1313 | * | | |1 = EPWM Compare Up point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1314 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. |
kadonotakashi | 0:8fdf9a60065b | 1315 | * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1316 | * |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1317 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1318 | * | | |0 = EPWM Compare Up point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1319 | * | | |1 = EPWM Compare Up point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1320 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. |
kadonotakashi | 0:8fdf9a60065b | 1321 | * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1322 | * |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1323 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1324 | * | | |0 = EPWM Compare Up point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1325 | * | | |1 = EPWM Compare Up point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1326 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. |
kadonotakashi | 0:8fdf9a60065b | 1327 | * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1328 | * |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1329 | * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1330 | * | | |0 = EPWM Compare Up point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1331 | * | | |1 = EPWM Compare Up point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1332 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. |
kadonotakashi | 0:8fdf9a60065b | 1333 | * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1334 | * |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1335 | * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1336 | * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1337 | * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1338 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. |
kadonotakashi | 0:8fdf9a60065b | 1339 | * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1340 | * |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1341 | * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1342 | * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1343 | * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1344 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. |
kadonotakashi | 0:8fdf9a60065b | 1345 | * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1346 | * |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1347 | * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1348 | * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1349 | * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1350 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. |
kadonotakashi | 0:8fdf9a60065b | 1351 | * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1352 | * |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1353 | * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1354 | * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1355 | * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1356 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. |
kadonotakashi | 0:8fdf9a60065b | 1357 | * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1358 | * |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1359 | * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1360 | * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1361 | * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1362 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. |
kadonotakashi | 0:8fdf9a60065b | 1363 | * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1364 | * |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1365 | * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. |
kadonotakashi | 0:8fdf9a60065b | 1366 | * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1367 | * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1368 | * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. |
kadonotakashi | 0:8fdf9a60065b | 1369 | * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. |
kadonotakashi | 0:8fdf9a60065b | 1370 | * @var EPWM_T::EADCTS0 |
kadonotakashi | 0:8fdf9a60065b | 1371 | * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0 |
kadonotakashi | 0:8fdf9a60065b | 1372 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1373 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1374 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1375 | * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select |
kadonotakashi | 0:8fdf9a60065b | 1376 | * | | |0000 = EPWM_CH0 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1377 | * | | |0001 = EPWM_CH0 period point. |
kadonotakashi | 0:8fdf9a60065b | 1378 | * | | |0010 = EPWM_CH0 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1379 | * | | |0011 = EPWM_CH0 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1380 | * | | |0100 = EPWM_CH0 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1381 | * | | |0101 = EPWM_CH1 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1382 | * | | |0110 = EPWM_CH1 period point. |
kadonotakashi | 0:8fdf9a60065b | 1383 | * | | |0111 = EPWM_CH1 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1384 | * | | |1000 = EPWM_CH1 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1385 | * | | |1001 = EPWM_CH1 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1386 | * | | |1010 = EPWM_CH0 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1387 | * | | |1011 = EPWM_CH0 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1388 | * | | |1100 = EPWM_CH2 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1389 | * | | |1101 = EPWM_CH2 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1390 | * | | |1110 = EPWM_CH4 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1391 | * | | |1111 = EPWM_CH4 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1392 | * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit |
kadonotakashi | 0:8fdf9a60065b | 1393 | * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select |
kadonotakashi | 0:8fdf9a60065b | 1394 | * | | |0000 = EPWM_CH0 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1395 | * | | |0001 = EPWM_CH0 period point. |
kadonotakashi | 0:8fdf9a60065b | 1396 | * | | |0010 = EPWM_CH0 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1397 | * | | |0011 = EPWM_CH0 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1398 | * | | |0100 = EPWM_CH0 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1399 | * | | |0101 = EPWM_CH1 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1400 | * | | |0110 = EPWM_CH1 period point. |
kadonotakashi | 0:8fdf9a60065b | 1401 | * | | |0111 = EPWM_CH1 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1402 | * | | |1000 = EPWM_CH1 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1403 | * | | |1001 = EPWM_CH1 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1404 | * | | |1010 = EPWM_CH0 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1405 | * | | |1011 = EPWM_CH0 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1406 | * | | |1100 = EPWM_CH2 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1407 | * | | |1101 = EPWM_CH2 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1408 | * | | |1110 = EPWM_CH4 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1409 | * | | |1111 = EPWM_CH4 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1410 | * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit |
kadonotakashi | 0:8fdf9a60065b | 1411 | * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select |
kadonotakashi | 0:8fdf9a60065b | 1412 | * | | |0000 = EPWM_CH2 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1413 | * | | |0001 = EPWM_CH2 period point. |
kadonotakashi | 0:8fdf9a60065b | 1414 | * | | |0010 = EPWM_CH2 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1415 | * | | |0011 = EPWM_CH2 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1416 | * | | |0100 = EPWM_CH2 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1417 | * | | |0101 = EPWM_CH3 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1418 | * | | |0110 = EPWM_CH3 period point. |
kadonotakashi | 0:8fdf9a60065b | 1419 | * | | |0111 = EPWM_CH3 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1420 | * | | |1000 = EPWM_CH3 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1421 | * | | |1001 = EPWM_CH3 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1422 | * | | |1010 = EPWM_CH0 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1423 | * | | |1011 = EPWM_CH0 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1424 | * | | |1100 = EPWM_CH2 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1425 | * | | |1101 = EPWM_CH2 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1426 | * | | |1110 = EPWM_CH4 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1427 | * | | |1111 = EPWM_CH4 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1428 | * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit |
kadonotakashi | 0:8fdf9a60065b | 1429 | * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select |
kadonotakashi | 0:8fdf9a60065b | 1430 | * | | |0000 = EPWM_CH2 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1431 | * | | |0001 = EPWM_CH2 period point. |
kadonotakashi | 0:8fdf9a60065b | 1432 | * | | |0010 = EPWM_CH2 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1433 | * | | |0011 = EPWM_CH2 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1434 | * | | |0100 = EPWM_CH2 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1435 | * | | |0101 = EPWM_CH3 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1436 | * | | |0110 = EPWM_CH3 period point. |
kadonotakashi | 0:8fdf9a60065b | 1437 | * | | |0111 = EPWM_CH3 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1438 | * | | |1000 = EPWM_CH3 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1439 | * | | |1001 = EPWM_CH3 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1440 | * | | |1010 = EPWM_CH0 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1441 | * | | |1011 = EPWM_CH0 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1442 | * | | |1100 = EPWM_CH2 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1443 | * | | |1101 = EPWM_CH2 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1444 | * | | |1110 = EPWM_CH4 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1445 | * | | |1111 = EPWM_CH4 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1446 | * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit |
kadonotakashi | 0:8fdf9a60065b | 1447 | * @var EPWM_T::EADCTS1 |
kadonotakashi | 0:8fdf9a60065b | 1448 | * Offset: 0xFC EPWM Trigger EADC Source Select Register 1 |
kadonotakashi | 0:8fdf9a60065b | 1449 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1450 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1451 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1452 | * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select |
kadonotakashi | 0:8fdf9a60065b | 1453 | * | | |0000 = EPWM_CH4 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1454 | * | | |0001 = EPWM_CH4 period point. |
kadonotakashi | 0:8fdf9a60065b | 1455 | * | | |0010 = EPWM_CH4 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1456 | * | | |0011 = EPWM_CH4 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1457 | * | | |0100 = EPWM_CH4 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1458 | * | | |0101 = EPWM_CH5 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1459 | * | | |0110 = EPWM_CH5 period point. |
kadonotakashi | 0:8fdf9a60065b | 1460 | * | | |0111 = EPWM_CH5 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1461 | * | | |1000 = EPWM_CH5 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1462 | * | | |1001 = EPWM_CH5 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1463 | * | | |1010 = EPWM_CH0 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1464 | * | | |1011 = EPWM_CH0 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1465 | * | | |1100 = EPWM_CH2 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1466 | * | | |1101 = EPWM_CH2 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1467 | * | | |1110 = EPWM_CH4 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1468 | * | | |1111 = EPWM_CH4 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1469 | * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit |
kadonotakashi | 0:8fdf9a60065b | 1470 | * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select |
kadonotakashi | 0:8fdf9a60065b | 1471 | * | | |0000 = EPWM_CH4 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1472 | * | | |0001 = EPWM_CH4 period point. |
kadonotakashi | 0:8fdf9a60065b | 1473 | * | | |0010 = EPWM_CH4 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1474 | * | | |0011 = EPWM_CH4 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1475 | * | | |0100 = EPWM_CH4 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1476 | * | | |0101 = EPWM_CH5 zero point. |
kadonotakashi | 0:8fdf9a60065b | 1477 | * | | |0110 = EPWM_CH5 period point. |
kadonotakashi | 0:8fdf9a60065b | 1478 | * | | |0111 = EPWM_CH5 zero or period point. |
kadonotakashi | 0:8fdf9a60065b | 1479 | * | | |1000 = EPWM_CH5 up-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1480 | * | | |1001 = EPWM_CH5 down-count CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1481 | * | | |1010 = EPWM_CH0 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1482 | * | | |1011 = EPWM_CH0 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1483 | * | | |1100 = EPWM_CH2 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1484 | * | | |1101 = EPWM_CH2 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1485 | * | | |1110 = EPWM_CH4 up-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1486 | * | | |1111 = EPWM_CH4 down-count free CMPDAT point. |
kadonotakashi | 0:8fdf9a60065b | 1487 | * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit |
kadonotakashi | 0:8fdf9a60065b | 1488 | * @var EPWM_T::FTCMPDAT[3] |
kadonotakashi | 0:8fdf9a60065b | 1489 | * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5 |
kadonotakashi | 0:8fdf9a60065b | 1490 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1491 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1492 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1493 | * |[15:0] |FTCMP |EPWM Free Trigger Compare Register |
kadonotakashi | 0:8fdf9a60065b | 1494 | * | | |FTCMP use to compare with even CNTR to trigger EADC |
kadonotakashi | 0:8fdf9a60065b | 1495 | * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. |
kadonotakashi | 0:8fdf9a60065b | 1496 | * @var EPWM_T::SSCTL |
kadonotakashi | 0:8fdf9a60065b | 1497 | * Offset: 0x110 EPWM Synchronous Start Control Register |
kadonotakashi | 0:8fdf9a60065b | 1498 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1499 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1500 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1501 | * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1502 | * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). |
kadonotakashi | 0:8fdf9a60065b | 1503 | * | | |0 = EPWM synchronous start function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1504 | * | | |1 = EPWM synchronous start function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1505 | * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1506 | * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). |
kadonotakashi | 0:8fdf9a60065b | 1507 | * | | |0 = EPWM synchronous start function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1508 | * | | |1 = EPWM synchronous start function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1509 | * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1510 | * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). |
kadonotakashi | 0:8fdf9a60065b | 1511 | * | | |0 = EPWM synchronous start function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1512 | * | | |1 = EPWM synchronous start function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1513 | * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1514 | * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). |
kadonotakashi | 0:8fdf9a60065b | 1515 | * | | |0 = EPWM synchronous start function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1516 | * | | |1 = EPWM synchronous start function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1517 | * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1518 | * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). |
kadonotakashi | 0:8fdf9a60065b | 1519 | * | | |0 = EPWM synchronous start function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1520 | * | | |1 = EPWM synchronous start function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1521 | * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1522 | * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). |
kadonotakashi | 0:8fdf9a60065b | 1523 | * | | |0 = EPWM synchronous start function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1524 | * | | |1 = EPWM synchronous start function Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1525 | * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits |
kadonotakashi | 0:8fdf9a60065b | 1526 | * | | |00 = Synchronous start source come from EPWM0. |
kadonotakashi | 0:8fdf9a60065b | 1527 | * | | |01 = Synchronous start source come from EPWM1. |
kadonotakashi | 0:8fdf9a60065b | 1528 | * | | |10 = Synchronous start source come from BPWM0. |
kadonotakashi | 0:8fdf9a60065b | 1529 | * | | |11 = Synchronous start source come from BPWM1. |
kadonotakashi | 0:8fdf9a60065b | 1530 | * @var EPWM_T::SSTRG |
kadonotakashi | 0:8fdf9a60065b | 1531 | * Offset: 0x114 EPWM Synchronous Start Trigger Register |
kadonotakashi | 0:8fdf9a60065b | 1532 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1533 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1534 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1535 | * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only) |
kadonotakashi | 0:8fdf9a60065b | 1536 | * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. |
kadonotakashi | 0:8fdf9a60065b | 1537 | * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. |
kadonotakashi | 0:8fdf9a60065b | 1538 | * @var EPWM_T::LEBCTL |
kadonotakashi | 0:8fdf9a60065b | 1539 | * Offset: 0x118 EPWM Leading Edge Blanking Control Register |
kadonotakashi | 0:8fdf9a60065b | 1540 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1541 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1542 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1543 | * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 1544 | * | | |0 = EPWM Leading Edge Blanking Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1545 | * | | |1 = EPWM Leading Edge Blanking Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1546 | * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 1547 | * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1548 | * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1549 | * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 1550 | * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1551 | * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1552 | * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit |
kadonotakashi | 0:8fdf9a60065b | 1553 | * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1554 | * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1555 | * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type |
kadonotakashi | 0:8fdf9a60065b | 1556 | * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting. |
kadonotakashi | 0:8fdf9a60065b | 1557 | * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting. |
kadonotakashi | 0:8fdf9a60065b | 1558 | * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting. |
kadonotakashi | 0:8fdf9a60065b | 1559 | * | | |3 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 1560 | * @var EPWM_T::LEBCNT |
kadonotakashi | 0:8fdf9a60065b | 1561 | * Offset: 0x11C EPWM Leading Edge Blanking Counter Register |
kadonotakashi | 0:8fdf9a60065b | 1562 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1563 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1564 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1565 | * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter |
kadonotakashi | 0:8fdf9a60065b | 1566 | * | | |This counter value decides leading edge blanking window size. |
kadonotakashi | 0:8fdf9a60065b | 1567 | * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK. |
kadonotakashi | 0:8fdf9a60065b | 1568 | * @var EPWM_T::STATUS |
kadonotakashi | 0:8fdf9a60065b | 1569 | * Offset: 0x120 EPWM Status Register |
kadonotakashi | 0:8fdf9a60065b | 1570 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1571 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1572 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1573 | * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag |
kadonotakashi | 0:8fdf9a60065b | 1574 | * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. |
kadonotakashi | 0:8fdf9a60065b | 1575 | * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1576 | * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag |
kadonotakashi | 0:8fdf9a60065b | 1577 | * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. |
kadonotakashi | 0:8fdf9a60065b | 1578 | * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1579 | * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag |
kadonotakashi | 0:8fdf9a60065b | 1580 | * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. |
kadonotakashi | 0:8fdf9a60065b | 1581 | * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1582 | * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag |
kadonotakashi | 0:8fdf9a60065b | 1583 | * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. |
kadonotakashi | 0:8fdf9a60065b | 1584 | * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1585 | * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag |
kadonotakashi | 0:8fdf9a60065b | 1586 | * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. |
kadonotakashi | 0:8fdf9a60065b | 1587 | * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1588 | * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag |
kadonotakashi | 0:8fdf9a60065b | 1589 | * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. |
kadonotakashi | 0:8fdf9a60065b | 1590 | * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1591 | * |[8] |SYNCINF0 |Input Synchronization Latched Flag |
kadonotakashi | 0:8fdf9a60065b | 1592 | * | | |0 = Indicates no SYNC_IN event has occurred. |
kadonotakashi | 0:8fdf9a60065b | 1593 | * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1594 | * |[9] |SYNCINF2 |Input Synchronization Latched Flag |
kadonotakashi | 0:8fdf9a60065b | 1595 | * | | |0 = Indicates no SYNC_IN event has occurred. |
kadonotakashi | 0:8fdf9a60065b | 1596 | * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1597 | * |[10] |SYNCINF4 |Input Synchronization Latched Flag |
kadonotakashi | 0:8fdf9a60065b | 1598 | * | | |0 = Indicates no SYNC_IN event has occurred. |
kadonotakashi | 0:8fdf9a60065b | 1599 | * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1600 | * |[16] |EADCTRGF0 |EADC Start of Conversion Flag |
kadonotakashi | 0:8fdf9a60065b | 1601 | * | | |0 = Indicates no EADC start of conversion trigger event has occurred. |
kadonotakashi | 0:8fdf9a60065b | 1602 | * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1603 | * |[17] |EADCTRGF1 |EADC Start of Conversion Flag |
kadonotakashi | 0:8fdf9a60065b | 1604 | * | | |0 = Indicates no EADC start of conversion trigger event has occurred. |
kadonotakashi | 0:8fdf9a60065b | 1605 | * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1606 | * |[18] |EADCTRGF2 |EADC Start of Conversion Flag |
kadonotakashi | 0:8fdf9a60065b | 1607 | * | | |0 = Indicates no EADC start of conversion trigger event has occurred. |
kadonotakashi | 0:8fdf9a60065b | 1608 | * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1609 | * |[19] |EADCTRGF3 |EADC Start of Conversion Flag |
kadonotakashi | 0:8fdf9a60065b | 1610 | * | | |0 = Indicates no EADC start of conversion trigger event has occurred. |
kadonotakashi | 0:8fdf9a60065b | 1611 | * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1612 | * |[20] |EADCTRGF4 |EADC Start of Conversion Flag |
kadonotakashi | 0:8fdf9a60065b | 1613 | * | | |0 = Indicates no EADC start of conversion trigger event has occurred. |
kadonotakashi | 0:8fdf9a60065b | 1614 | * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1615 | * |[21] |EADCTRGF5 |EADC Start of Conversion Flag |
kadonotakashi | 0:8fdf9a60065b | 1616 | * | | |0 = Indicates no EADC start of conversion trigger event has occurred. |
kadonotakashi | 0:8fdf9a60065b | 1617 | * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 1618 | * |[24] |DACTRGF |DAC Start of Conversion Flag |
kadonotakashi | 0:8fdf9a60065b | 1619 | * | | |0 = Indicates no DAC start of conversion trigger event has occurred. |
kadonotakashi | 0:8fdf9a60065b | 1620 | * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit |
kadonotakashi | 0:8fdf9a60065b | 1621 | * @var EPWM_T::IFA[6] |
kadonotakashi | 0:8fdf9a60065b | 1622 | * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5 |
kadonotakashi | 0:8fdf9a60065b | 1623 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1624 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1625 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1626 | * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter |
kadonotakashi | 0:8fdf9a60065b | 1627 | * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. |
kadonotakashi | 0:8fdf9a60065b | 1628 | * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. |
kadonotakashi | 0:8fdf9a60065b | 1629 | * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select |
kadonotakashi | 0:8fdf9a60065b | 1630 | * | | |00 = CNT equal to Zero in channel n. |
kadonotakashi | 0:8fdf9a60065b | 1631 | * | | |01 = CNT equal to PERIOD in channel n. |
kadonotakashi | 0:8fdf9a60065b | 1632 | * | | |10 = CNT equal to CMPU in channel n. |
kadonotakashi | 0:8fdf9a60065b | 1633 | * | | |11 = CNT equal to CMPD in channel n. |
kadonotakashi | 0:8fdf9a60065b | 1634 | * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1635 | * | | |0 = EPWM_CHn interrupt flag accumulator disable. |
kadonotakashi | 0:8fdf9a60065b | 1636 | * | | |1 = EPWM_CHn interrupt flag accumulator enable. |
kadonotakashi | 0:8fdf9a60065b | 1637 | * @var EPWM_T::AINTSTS |
kadonotakashi | 0:8fdf9a60065b | 1638 | * Offset: 0x150 EPWM Accumulator Interrupt Flag Register |
kadonotakashi | 0:8fdf9a60065b | 1639 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1640 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1641 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1642 | * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1643 | * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1644 | * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1645 | * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1646 | * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1647 | * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1648 | * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1649 | * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1650 | * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1651 | * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1652 | * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1653 | * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. |
kadonotakashi | 0:8fdf9a60065b | 1654 | * @var EPWM_T::AINTEN |
kadonotakashi | 0:8fdf9a60065b | 1655 | * Offset: 0x154 EPWM Accumulator Interrupt Enable Register |
kadonotakashi | 0:8fdf9a60065b | 1656 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1657 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1658 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1659 | * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1660 | * | | |0 = Interrupt Flag accumulator interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1661 | * | | |1 = Interrupt Flag accumulator interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1662 | * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1663 | * | | |0 = Interrupt Flag accumulator interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1664 | * | | |1 = Interrupt Flag accumulator interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1665 | * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1666 | * | | |0 = Interrupt Flag accumulator interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1667 | * | | |1 = Interrupt Flag accumulator interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1668 | * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1669 | * | | |0 = Interrupt Flag accumulator interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1670 | * | | |1 = Interrupt Flag accumulator interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1671 | * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1672 | * | | |0 = Interrupt Flag accumulator interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1673 | * | | |1 = Interrupt Flag accumulator interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1674 | * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1675 | * | | |0 = Interrupt Flag accumulator interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1676 | * | | |1 = Interrupt Flag accumulator interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1677 | * @var EPWM_T::APDMACTL |
kadonotakashi | 0:8fdf9a60065b | 1678 | * Offset: 0x158 EPWM Accumulator PDMA Control Register |
kadonotakashi | 0:8fdf9a60065b | 1679 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1680 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1681 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1682 | * |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1683 | * | | |0 = Channel n PDMA function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1684 | * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. |
kadonotakashi | 0:8fdf9a60065b | 1685 | * |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1686 | * | | |0 = Channel n PDMA function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1687 | * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. |
kadonotakashi | 0:8fdf9a60065b | 1688 | * |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1689 | * | | |0 = Channel n PDMA function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1690 | * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. |
kadonotakashi | 0:8fdf9a60065b | 1691 | * |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1692 | * | | |0 = Channel n PDMA function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1693 | * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. |
kadonotakashi | 0:8fdf9a60065b | 1694 | * |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1695 | * | | |0 = Channel n PDMA function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1696 | * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. |
kadonotakashi | 0:8fdf9a60065b | 1697 | * |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1698 | * | | |0 = Channel n PDMA function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1699 | * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. |
kadonotakashi | 0:8fdf9a60065b | 1700 | * @var EPWM_T::CAPINEN |
kadonotakashi | 0:8fdf9a60065b | 1701 | * Offset: 0x200 EPWM Capture Input Enable Register |
kadonotakashi | 0:8fdf9a60065b | 1702 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1703 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1704 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1705 | * |[0] |CAPINEN0 |Capture Input Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1706 | * | | |0 = EPWM Channel capture input path Disabled |
kadonotakashi | 0:8fdf9a60065b | 1707 | * | | |The input of EPWM channel capture function is always regarded as 0. |
kadonotakashi | 0:8fdf9a60065b | 1708 | * | | |1 = EPWM Channel capture input path Enabled |
kadonotakashi | 0:8fdf9a60065b | 1709 | * | | |The input of EPWM channel capture function comes from correlative multifunction pin. |
kadonotakashi | 0:8fdf9a60065b | 1710 | * |[1] |CAPINEN1 |Capture Input Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1711 | * | | |0 = EPWM Channel capture input path Disabled |
kadonotakashi | 0:8fdf9a60065b | 1712 | * | | |The input of EPWM channel capture function is always regarded as 0. |
kadonotakashi | 0:8fdf9a60065b | 1713 | * | | |1 = EPWM Channel capture input path Enabled |
kadonotakashi | 0:8fdf9a60065b | 1714 | * | | |The input of EPWM channel capture function comes from correlative multifunction pin. |
kadonotakashi | 0:8fdf9a60065b | 1715 | * |[2] |CAPINEN2 |Capture Input Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1716 | * | | |0 = EPWM Channel capture input path Disabled |
kadonotakashi | 0:8fdf9a60065b | 1717 | * | | |The input of EPWM channel capture function is always regarded as 0. |
kadonotakashi | 0:8fdf9a60065b | 1718 | * | | |1 = EPWM Channel capture input path Enabled |
kadonotakashi | 0:8fdf9a60065b | 1719 | * | | |The input of EPWM channel capture function comes from correlative multifunction pin. |
kadonotakashi | 0:8fdf9a60065b | 1720 | * |[3] |CAPINEN3 |Capture Input Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1721 | * | | |0 = EPWM Channel capture input path Disabled |
kadonotakashi | 0:8fdf9a60065b | 1722 | * | | |The input of EPWM channel capture function is always regarded as 0. |
kadonotakashi | 0:8fdf9a60065b | 1723 | * | | |1 = EPWM Channel capture input path Enabled |
kadonotakashi | 0:8fdf9a60065b | 1724 | * | | |The input of EPWM channel capture function comes from correlative multifunction pin. |
kadonotakashi | 0:8fdf9a60065b | 1725 | * |[4] |CAPINEN4 |Capture Input Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1726 | * | | |0 = EPWM Channel capture input path Disabled |
kadonotakashi | 0:8fdf9a60065b | 1727 | * | | |The input of EPWM channel capture function is always regarded as 0. |
kadonotakashi | 0:8fdf9a60065b | 1728 | * | | |1 = EPWM Channel capture input path Enabled |
kadonotakashi | 0:8fdf9a60065b | 1729 | * | | |The input of EPWM channel capture function comes from correlative multifunction pin. |
kadonotakashi | 0:8fdf9a60065b | 1730 | * |[5] |CAPINEN5 |Capture Input Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1731 | * | | |0 = EPWM Channel capture input path Disabled |
kadonotakashi | 0:8fdf9a60065b | 1732 | * | | |The input of EPWM channel capture function is always regarded as 0. |
kadonotakashi | 0:8fdf9a60065b | 1733 | * | | |1 = EPWM Channel capture input path Enabled |
kadonotakashi | 0:8fdf9a60065b | 1734 | * | | |The input of EPWM channel capture function comes from correlative multifunction pin. |
kadonotakashi | 0:8fdf9a60065b | 1735 | * @var EPWM_T::CAPCTL |
kadonotakashi | 0:8fdf9a60065b | 1736 | * Offset: 0x204 EPWM Capture Control Register |
kadonotakashi | 0:8fdf9a60065b | 1737 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1738 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1739 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1740 | * |[0] |CAPEN0 |Capture Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1741 | * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. |
kadonotakashi | 0:8fdf9a60065b | 1742 | * | | |1 = Capture function Enabled |
kadonotakashi | 0:8fdf9a60065b | 1743 | * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
kadonotakashi | 0:8fdf9a60065b | 1744 | * |[1] |CAPEN1 |Capture Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1745 | * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. |
kadonotakashi | 0:8fdf9a60065b | 1746 | * | | |1 = Capture function Enabled |
kadonotakashi | 0:8fdf9a60065b | 1747 | * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
kadonotakashi | 0:8fdf9a60065b | 1748 | * |[2] |CAPEN2 |Capture Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1749 | * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. |
kadonotakashi | 0:8fdf9a60065b | 1750 | * | | |1 = Capture function Enabled |
kadonotakashi | 0:8fdf9a60065b | 1751 | * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
kadonotakashi | 0:8fdf9a60065b | 1752 | * |[3] |CAPEN3 |Capture Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1753 | * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. |
kadonotakashi | 0:8fdf9a60065b | 1754 | * | | |1 = Capture function Enabled |
kadonotakashi | 0:8fdf9a60065b | 1755 | * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
kadonotakashi | 0:8fdf9a60065b | 1756 | * |[4] |CAPEN4 |Capture Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1757 | * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. |
kadonotakashi | 0:8fdf9a60065b | 1758 | * | | |1 = Capture function Enabled |
kadonotakashi | 0:8fdf9a60065b | 1759 | * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
kadonotakashi | 0:8fdf9a60065b | 1760 | * |[5] |CAPEN5 |Capture Function Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1761 | * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. |
kadonotakashi | 0:8fdf9a60065b | 1762 | * | | |1 = Capture function Enabled |
kadonotakashi | 0:8fdf9a60065b | 1763 | * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). |
kadonotakashi | 0:8fdf9a60065b | 1764 | * |[8] |CAPINV0 |Capture Inverter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1765 | * | | |0 = Capture source inverter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1766 | * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
kadonotakashi | 0:8fdf9a60065b | 1767 | * |[9] |CAPINV1 |Capture Inverter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1768 | * | | |0 = Capture source inverter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1769 | * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
kadonotakashi | 0:8fdf9a60065b | 1770 | * |[10] |CAPINV2 |Capture Inverter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1771 | * | | |0 = Capture source inverter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1772 | * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
kadonotakashi | 0:8fdf9a60065b | 1773 | * |[11] |CAPINV3 |Capture Inverter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1774 | * | | |0 = Capture source inverter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1775 | * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
kadonotakashi | 0:8fdf9a60065b | 1776 | * |[12] |CAPINV4 |Capture Inverter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1777 | * | | |0 = Capture source inverter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1778 | * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
kadonotakashi | 0:8fdf9a60065b | 1779 | * |[13] |CAPINV5 |Capture Inverter Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1780 | * | | |0 = Capture source inverter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1781 | * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. |
kadonotakashi | 0:8fdf9a60065b | 1782 | * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1783 | * | | |0 = Rising capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1784 | * | | |1 = Rising capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1785 | * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1786 | * | | |0 = Rising capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1787 | * | | |1 = Rising capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1788 | * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1789 | * | | |0 = Rising capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1790 | * | | |1 = Rising capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1791 | * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1792 | * | | |0 = Rising capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1793 | * | | |1 = Rising capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1794 | * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1795 | * | | |0 = Rising capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1796 | * | | |1 = Rising capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1797 | * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1798 | * | | |0 = Rising capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1799 | * | | |1 = Rising capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1800 | * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1801 | * | | |0 = Falling capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1802 | * | | |1 = Falling capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1803 | * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1804 | * | | |0 = Falling capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1805 | * | | |1 = Falling capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1806 | * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1807 | * | | |0 = Falling capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1808 | * | | |1 = Falling capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1809 | * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1810 | * | | |0 = Falling capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1811 | * | | |1 = Falling capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1812 | * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1813 | * | | |0 = Falling capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1814 | * | | |1 = Falling capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1815 | * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1816 | * | | |0 = Falling capture reload counter Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1817 | * | | |1 = Falling capture reload counter Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1818 | * @var EPWM_T::CAPSTS |
kadonotakashi | 0:8fdf9a60065b | 1819 | * Offset: 0x208 EPWM Capture Status Register |
kadonotakashi | 0:8fdf9a60065b | 1820 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1821 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1822 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1823 | * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1824 | * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1825 | * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. |
kadonotakashi | 0:8fdf9a60065b | 1826 | * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1827 | * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1828 | * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. |
kadonotakashi | 0:8fdf9a60065b | 1829 | * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1830 | * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1831 | * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. |
kadonotakashi | 0:8fdf9a60065b | 1832 | * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1833 | * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1834 | * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. |
kadonotakashi | 0:8fdf9a60065b | 1835 | * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1836 | * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1837 | * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. |
kadonotakashi | 0:8fdf9a60065b | 1838 | * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1839 | * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1840 | * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. |
kadonotakashi | 0:8fdf9a60065b | 1841 | * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1842 | * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1843 | * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. |
kadonotakashi | 0:8fdf9a60065b | 1844 | * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1845 | * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1846 | * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. |
kadonotakashi | 0:8fdf9a60065b | 1847 | * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1848 | * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1849 | * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. |
kadonotakashi | 0:8fdf9a60065b | 1850 | * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1851 | * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1852 | * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. |
kadonotakashi | 0:8fdf9a60065b | 1853 | * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1854 | * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1855 | * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. |
kadonotakashi | 0:8fdf9a60065b | 1856 | * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1857 | * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. |
kadonotakashi | 0:8fdf9a60065b | 1858 | * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. |
kadonotakashi | 0:8fdf9a60065b | 1859 | * @var EPWM_T::PDMACTL |
kadonotakashi | 0:8fdf9a60065b | 1860 | * Offset: 0x23C EPWM PDMA Control Register |
kadonotakashi | 0:8fdf9a60065b | 1861 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1862 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1863 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1864 | * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable |
kadonotakashi | 0:8fdf9a60065b | 1865 | * | | |0 = Channel 0/1 PDMA function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1866 | * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. |
kadonotakashi | 0:8fdf9a60065b | 1867 | * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer |
kadonotakashi | 0:8fdf9a60065b | 1868 | * | | |00 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 1869 | * | | |01 = EPWM_RCAPDAT0/1 register. |
kadonotakashi | 0:8fdf9a60065b | 1870 | * | | |10 = EPWM_FCAPDAT0/1 register. |
kadonotakashi | 0:8fdf9a60065b | 1871 | * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1 registers. |
kadonotakashi | 0:8fdf9a60065b | 1872 | * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order |
kadonotakashi | 0:8fdf9a60065b | 1873 | * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to = 0x3. |
kadonotakashi | 0:8fdf9a60065b | 1874 | * | | |0 = EPWM_FCAPDAT0/1 register is the first captured data to memory. |
kadonotakashi | 0:8fdf9a60065b | 1875 | * | | |1 = EPWM_RCAPDAT0/1 register is the first captured data to memory. |
kadonotakashi | 0:8fdf9a60065b | 1876 | * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer |
kadonotakashi | 0:8fdf9a60065b | 1877 | * | | |0 = Channel0. |
kadonotakashi | 0:8fdf9a60065b | 1878 | * | | |1 = Channel1. |
kadonotakashi | 0:8fdf9a60065b | 1879 | * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable |
kadonotakashi | 0:8fdf9a60065b | 1880 | * | | |0 = Channel 2/3 PDMA function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1881 | * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. |
kadonotakashi | 0:8fdf9a60065b | 1882 | * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer |
kadonotakashi | 0:8fdf9a60065b | 1883 | * | | |00 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 1884 | * | | |01 = EPWM_RCAPDAT2/3 register. |
kadonotakashi | 0:8fdf9a60065b | 1885 | * | | |10 = EPWM_FCAPDAT2/3 register. |
kadonotakashi | 0:8fdf9a60065b | 1886 | * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3 registers. |
kadonotakashi | 0:8fdf9a60065b | 1887 | * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order |
kadonotakashi | 0:8fdf9a60065b | 1888 | * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to =0x3. |
kadonotakashi | 0:8fdf9a60065b | 1889 | * | | |0 = EPWM_FCAPDAT2/3 register is the first captured data to memory. |
kadonotakashi | 0:8fdf9a60065b | 1890 | * | | |1 = EPWM_RCAPDAT2/3 register is the first captured data to memory. |
kadonotakashi | 0:8fdf9a60065b | 1891 | * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer |
kadonotakashi | 0:8fdf9a60065b | 1892 | * | | |0 = Channel2. |
kadonotakashi | 0:8fdf9a60065b | 1893 | * | | |1 = Channel3. |
kadonotakashi | 0:8fdf9a60065b | 1894 | * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable |
kadonotakashi | 0:8fdf9a60065b | 1895 | * | | |0 = Channel 4/5 PDMA function Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1896 | * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. |
kadonotakashi | 0:8fdf9a60065b | 1897 | * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer |
kadonotakashi | 0:8fdf9a60065b | 1898 | * | | |00 = Reserved. |
kadonotakashi | 0:8fdf9a60065b | 1899 | * | | |01 = EPWM_RCAPDAT4/5 register. |
kadonotakashi | 0:8fdf9a60065b | 1900 | * | | |10 = EPWM_FCAPDAT4/5 register. |
kadonotakashi | 0:8fdf9a60065b | 1901 | * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5 registers. |
kadonotakashi | 0:8fdf9a60065b | 1902 | * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order |
kadonotakashi | 0:8fdf9a60065b | 1903 | * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits =are set to 0x3. |
kadonotakashi | 0:8fdf9a60065b | 1904 | * | | |0 = EPWM_FCAPDAT4/5 register is the first captured data to memory. |
kadonotakashi | 0:8fdf9a60065b | 1905 | * | | |1 = EPWM_RCAPDAT4/5 register is the first captured data to memory. |
kadonotakashi | 0:8fdf9a60065b | 1906 | * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer |
kadonotakashi | 0:8fdf9a60065b | 1907 | * | | |0 = Channel4. |
kadonotakashi | 0:8fdf9a60065b | 1908 | * | | |1 = Channel5. |
kadonotakashi | 0:8fdf9a60065b | 1909 | * @var EPWM_T::PDMACAP[3] |
kadonotakashi | 0:8fdf9a60065b | 1910 | * Offset: 0x240 EPWM Capture Channel 01 PDMA Register |
kadonotakashi | 0:8fdf9a60065b | 1911 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1912 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1913 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1914 | * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 1915 | * | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. |
kadonotakashi | 0:8fdf9a60065b | 1916 | * @var EPWM_T::CAPIEN |
kadonotakashi | 0:8fdf9a60065b | 1917 | * Offset: 0x250 EPWM Capture Interrupt Enable Register |
kadonotakashi | 0:8fdf9a60065b | 1918 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1919 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1920 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1921 | * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1922 | * | | |0 = Capture rising edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1923 | * | | |1 = Capture rising edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1924 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN0 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1925 | * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1926 | * | | |0 = Capture rising edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1927 | * | | |1 = Capture rising edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1928 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN1 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1929 | * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1930 | * | | |0 = Capture rising edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1931 | * | | |1 = Capture rising edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1932 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN2 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1933 | * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1934 | * | | |0 = Capture rising edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1935 | * | | |1 = Capture rising edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1936 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN3 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1937 | * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1938 | * | | |0 = Capture rising edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1939 | * | | |1 = Capture rising edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1940 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN4 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1941 | * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1942 | * | | |0 = Capture rising edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1943 | * | | |1 = Capture rising edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1944 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN5 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1945 | * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1946 | * | | |0 = Capture falling edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1947 | * | | |1 = Capture falling edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1948 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN0 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1949 | * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1950 | * | | |0 = Capture falling edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1951 | * | | |1 = Capture falling edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1952 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN1 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1953 | * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1954 | * | | |0 = Capture falling edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1955 | * | | |1 = Capture falling edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1956 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN2 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1957 | * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1958 | * | | |0 = Capture falling edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1959 | * | | |1 = Capture falling edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1960 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN3 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1961 | * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1962 | * | | |0 = Capture falling edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1963 | * | | |1 = Capture falling edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1964 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN4 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1965 | * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits |
kadonotakashi | 0:8fdf9a60065b | 1966 | * | | |0 = Capture falling edge latch interrupt Disabled. |
kadonotakashi | 0:8fdf9a60065b | 1967 | * | | |1 = Capture falling edge latch interrupt Enabled. |
kadonotakashi | 0:8fdf9a60065b | 1968 | * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN5 bit must be disabled. |
kadonotakashi | 0:8fdf9a60065b | 1969 | * @var EPWM_T::CAPIF |
kadonotakashi | 0:8fdf9a60065b | 1970 | * Offset: 0x254 EPWM Capture Interrupt Flag Register |
kadonotakashi | 0:8fdf9a60065b | 1971 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 1972 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 1973 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 1974 | * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1975 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1976 | * | | |0 = No capture rising latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 1977 | * | | |1 = Capture rising latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 1978 | * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF0 bit will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 1979 | * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1980 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1981 | * | | |0 = No capture rising latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 1982 | * | | |1 = Capture rising latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 1983 | * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF1 bit will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 1984 | * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1985 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1986 | * | | |0 = No capture rising latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 1987 | * | | |1 = Capture rising latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 1988 | * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF2 bit will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 1989 | * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1990 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1991 | * | | |0 = No capture rising latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 1992 | * | | |1 = Capture rising latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 1993 | * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF3 bit will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 1994 | * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 1995 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 1996 | * | | |0 = No capture rising latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 1997 | * | | |1 = Capture rising latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 1998 | * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF4 bit will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 1999 | * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 2000 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 2001 | * | | |0 = No capture rising latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 2002 | * | | |1 = Capture rising latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 2003 | * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF5 bit will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 2004 | * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 2005 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 2006 | * | | |0 = No capture falling latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 2007 | * | | |1 = Capture falling latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 2008 | * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF0 bit will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 2009 | * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 2010 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 2011 | * | | |0 = No capture falling latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 2012 | * | | |1 = Capture falling latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 2013 | * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF1 bit will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 2014 | * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 2015 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 2016 | * | | |0 = No capture falling latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 2017 | * | | |1 = Capture falling latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 2018 | * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF2 bit will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 2019 | * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 2020 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 2021 | * | | |0 = No capture falling latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 2022 | * | | |1 = Capture falling latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 2023 | * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF3 bit will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 2024 | * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 2025 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 2026 | * | | |0 = No capture falling latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 2027 | * | | |1 = Capture falling latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 2028 | * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF4 bit will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 2029 | * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag |
kadonotakashi | 0:8fdf9a60065b | 2030 | * | | |This bit is writing 1 to clear. |
kadonotakashi | 0:8fdf9a60065b | 2031 | * | | |0 = No capture falling latch condition happened. |
kadonotakashi | 0:8fdf9a60065b | 2032 | * | | |1 = Capture falling latch condition happened, this flag will be set to high. |
kadonotakashi | 0:8fdf9a60065b | 2033 | * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. |
kadonotakashi | 0:8fdf9a60065b | 2034 | * @var EPWM_T::PBUF[6] |
kadonotakashi | 0:8fdf9a60065b | 2035 | * Offset: 0x304 EPWM PERIOD0~5 Buffer |
kadonotakashi | 0:8fdf9a60065b | 2036 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 2037 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 2038 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 2039 | * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 2040 | * | | |Used as PERIOD active register. |
kadonotakashi | 0:8fdf9a60065b | 2041 | * @var EPWM_T::CMPBUF[6] |
kadonotakashi | 0:8fdf9a60065b | 2042 | * Offset: 0x31C EPWM CMPDAT0~5 Buffer |
kadonotakashi | 0:8fdf9a60065b | 2043 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 2044 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 2045 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 2046 | * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 2047 | * | | |Used as CMP active register. |
kadonotakashi | 0:8fdf9a60065b | 2048 | * @var EPWM_T::CPSCBUF[3] |
kadonotakashi | 0:8fdf9a60065b | 2049 | * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer |
kadonotakashi | 0:8fdf9a60065b | 2050 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 2051 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 2052 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 2053 | * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer |
kadonotakashi | 0:8fdf9a60065b | 2054 | * | | |Use as EPWM counter clock prescale active register. |
kadonotakashi | 0:8fdf9a60065b | 2055 | * @var EPWM_T::FTCBUF[3] |
kadonotakashi | 0:8fdf9a60065b | 2056 | * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer |
kadonotakashi | 0:8fdf9a60065b | 2057 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 2058 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 2059 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 2060 | * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) |
kadonotakashi | 0:8fdf9a60065b | 2061 | * | | |Used as FTCMPDAT active register. |
kadonotakashi | 0:8fdf9a60065b | 2062 | * @var EPWM_T::FTCI |
kadonotakashi | 0:8fdf9a60065b | 2063 | * Offset: 0x34C EPWM FTCMPDAT Indicator Register |
kadonotakashi | 0:8fdf9a60065b | 2064 | * --------------------------------------------------------------------------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 2065 | * |Bits |Field |Descriptions |
kadonotakashi | 0:8fdf9a60065b | 2066 | * | :----: | :----: | :---- | |
kadonotakashi | 0:8fdf9a60065b | 2067 | * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator |
kadonotakashi | 0:8fdf9a60065b | 2068 | * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 2069 | * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator |
kadonotakashi | 0:8fdf9a60065b | 2070 | * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 2071 | * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator |
kadonotakashi | 0:8fdf9a60065b | 2072 | * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 2073 | * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator |
kadonotakashi | 0:8fdf9a60065b | 2074 | * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 2075 | * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator |
kadonotakashi | 0:8fdf9a60065b | 2076 | * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 2077 | * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator |
kadonotakashi | 0:8fdf9a60065b | 2078 | * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. |
kadonotakashi | 0:8fdf9a60065b | 2079 | */ |
kadonotakashi | 0:8fdf9a60065b | 2080 | __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */ |
kadonotakashi | 0:8fdf9a60065b | 2081 | __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */ |
kadonotakashi | 0:8fdf9a60065b | 2082 | __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */ |
kadonotakashi | 0:8fdf9a60065b | 2083 | __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */ |
kadonotakashi | 0:8fdf9a60065b | 2084 | __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */ |
kadonotakashi | 0:8fdf9a60065b | 2085 | __IO uint32_t CLKPSC[3]; /*!< [0x0014~0x001c] EPWM Clock Prescale Register 0_1,2_3,4_5 */ |
kadonotakashi | 0:8fdf9a60065b | 2086 | __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */ |
kadonotakashi | 0:8fdf9a60065b | 2087 | __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */ |
kadonotakashi | 0:8fdf9a60065b | 2088 | __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */ |
kadonotakashi | 0:8fdf9a60065b | 2089 | __I uint32_t RESERVE0[1]; |
kadonotakashi | 0:8fdf9a60065b | 2090 | __IO uint32_t PERIOD[6]; /*!< [0x0030~0x0044] EPWM Period Register 0~5 */ |
kadonotakashi | 0:8fdf9a60065b | 2091 | __I uint32_t RESERVE1[2]; |
kadonotakashi | 0:8fdf9a60065b | 2092 | __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] EPWM Comparator Register 0~5 */ |
kadonotakashi | 0:8fdf9a60065b | 2093 | __I uint32_t RESERVE2[2]; |
kadonotakashi | 0:8fdf9a60065b | 2094 | __IO uint32_t DTCTL[3]; /*!< [0x0070~0x0078] EPWM Dead-Time Control Register 0_1,2_3,4_5 */ |
kadonotakashi | 0:8fdf9a60065b | 2095 | __I uint32_t RESERVE3[1]; |
kadonotakashi | 0:8fdf9a60065b | 2096 | __IO uint32_t PHS[3]; /*!< [0x0080~0x0088] EPWM Counter Phase Register 0_1,2_3,4_5 */ |
kadonotakashi | 0:8fdf9a60065b | 2097 | __I uint32_t RESERVE4[1]; |
kadonotakashi | 0:8fdf9a60065b | 2098 | __I uint32_t CNT[6]; /*!< [0x0090~0x00A4 EPWM Counter Register 0~5 */ |
kadonotakashi | 0:8fdf9a60065b | 2099 | __I uint32_t RESERVE5[2]; |
kadonotakashi | 0:8fdf9a60065b | 2100 | __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */ |
kadonotakashi | 0:8fdf9a60065b | 2101 | __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */ |
kadonotakashi | 0:8fdf9a60065b | 2102 | __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */ |
kadonotakashi | 0:8fdf9a60065b | 2103 | __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */ |
kadonotakashi | 0:8fdf9a60065b | 2104 | __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */ |
kadonotakashi | 0:8fdf9a60065b | 2105 | __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 2106 | __IO uint32_t BRKCTL[3]; /*!< [0x00c8~0x00d0] EPWM Brake Edge Detect Control Register 0_1,2_3,4_5 */ |
kadonotakashi | 0:8fdf9a60065b | 2107 | __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */ |
kadonotakashi | 0:8fdf9a60065b | 2108 | __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */ |
kadonotakashi | 0:8fdf9a60065b | 2109 | __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 2110 | __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */ |
kadonotakashi | 0:8fdf9a60065b | 2111 | __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */ |
kadonotakashi | 0:8fdf9a60065b | 2112 | __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */ |
kadonotakashi | 0:8fdf9a60065b | 2113 | __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */ |
kadonotakashi | 0:8fdf9a60065b | 2114 | __I uint32_t RESERVE6[1]; |
kadonotakashi | 0:8fdf9a60065b | 2115 | __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */ |
kadonotakashi | 0:8fdf9a60065b | 2116 | __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */ |
kadonotakashi | 0:8fdf9a60065b | 2117 | __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */ |
kadonotakashi | 0:8fdf9a60065b | 2118 | __IO uint32_t FTCMPDAT[3]; /*!< [0x0100~0x108] EPWM Free Trigger Compare Register 0_1,2_3,4_5 */ |
kadonotakashi | 0:8fdf9a60065b | 2119 | __I uint32_t RESERVE7[1]; |
kadonotakashi | 0:8fdf9a60065b | 2120 | __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 2121 | __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */ |
kadonotakashi | 0:8fdf9a60065b | 2122 | __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 2123 | __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */ |
kadonotakashi | 0:8fdf9a60065b | 2124 | __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 2125 | __I uint32_t RESERVE8[3]; |
kadonotakashi | 0:8fdf9a60065b | 2126 | __IO uint32_t IFA[6]; /*!< [0x0130~0x144] EPWM Interrupt Flag Accumulator Register 0~5 */ |
kadonotakashi | 0:8fdf9a60065b | 2127 | __I uint32_t RESERVE9[2]; |
kadonotakashi | 0:8fdf9a60065b | 2128 | __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */ |
kadonotakashi | 0:8fdf9a60065b | 2129 | __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */ |
kadonotakashi | 0:8fdf9a60065b | 2130 | __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 2131 | __I uint32_t RESERVE10[41]; |
kadonotakashi | 0:8fdf9a60065b | 2132 | __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */ |
kadonotakashi | 0:8fdf9a60065b | 2133 | __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 2134 | __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 2135 | ECAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] EPWM Rising and Falling Capture Data Register 0~5 */ |
kadonotakashi | 0:8fdf9a60065b | 2136 | __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 2137 | __I uint32_t PDMACAP[3]; /*!< [0x0240~0x248] EPWM Capture Channel 0_1,2_3,4_5 PDMA Register */ |
kadonotakashi | 0:8fdf9a60065b | 2138 | __I uint32_t RESERVE11[1]; |
kadonotakashi | 0:8fdf9a60065b | 2139 | __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */ |
kadonotakashi | 0:8fdf9a60065b | 2140 | __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */ |
kadonotakashi | 0:8fdf9a60065b | 2141 | __I uint32_t RESERVE12[43]; |
kadonotakashi | 0:8fdf9a60065b | 2142 | __I uint32_t PBUF[6]; /*!< [0x0304~0x0318 EPWM PERIOD0~5 Buffer */ |
kadonotakashi | 0:8fdf9a60065b | 2143 | __I uint32_t CMPBUF[6]; /*!< [0x031C~0x0330 EPWM CMPDAT0~5 Buffer */ |
kadonotakashi | 0:8fdf9a60065b | 2144 | __I uint32_t CPSCBUF[3]; /*!< [0x0334~0x33c] EPWM CLKPSC0_1,2_3,4_5 Buffer */ |
kadonotakashi | 0:8fdf9a60065b | 2145 | __I uint32_t FTCBUF[3]; /*!< [0x0340~0x348] EPWM FTCMPDAT0_1,2_3,4_5 Buffer */ |
kadonotakashi | 0:8fdf9a60065b | 2146 | __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */ |
kadonotakashi | 0:8fdf9a60065b | 2147 | |
kadonotakashi | 0:8fdf9a60065b | 2148 | } EPWM_T; |
kadonotakashi | 0:8fdf9a60065b | 2149 | |
kadonotakashi | 0:8fdf9a60065b | 2150 | /** |
kadonotakashi | 0:8fdf9a60065b | 2151 | @addtogroup EPWM_CONST EPWM Bit Field Definition |
kadonotakashi | 0:8fdf9a60065b | 2152 | Constant Definitions for EPWM Controller |
kadonotakashi | 0:8fdf9a60065b | 2153 | @{ */ |
kadonotakashi | 0:8fdf9a60065b | 2154 | |
kadonotakashi | 0:8fdf9a60065b | 2155 | #define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2156 | #define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2157 | |
kadonotakashi | 0:8fdf9a60065b | 2158 | #define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2159 | #define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2160 | |
kadonotakashi | 0:8fdf9a60065b | 2161 | #define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2162 | #define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2163 | |
kadonotakashi | 0:8fdf9a60065b | 2164 | #define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2165 | #define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2166 | |
kadonotakashi | 0:8fdf9a60065b | 2167 | #define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2168 | #define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2169 | |
kadonotakashi | 0:8fdf9a60065b | 2170 | #define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2171 | #define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2172 | |
kadonotakashi | 0:8fdf9a60065b | 2173 | #define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2174 | #define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2175 | |
kadonotakashi | 0:8fdf9a60065b | 2176 | #define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2177 | #define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2178 | |
kadonotakashi | 0:8fdf9a60065b | 2179 | #define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2180 | #define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2181 | |
kadonotakashi | 0:8fdf9a60065b | 2182 | #define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2183 | #define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2184 | |
kadonotakashi | 0:8fdf9a60065b | 2185 | #define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2186 | #define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2187 | |
kadonotakashi | 0:8fdf9a60065b | 2188 | #define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2189 | #define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2190 | |
kadonotakashi | 0:8fdf9a60065b | 2191 | #define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2192 | #define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2193 | |
kadonotakashi | 0:8fdf9a60065b | 2194 | #define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2195 | #define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2196 | |
kadonotakashi | 0:8fdf9a60065b | 2197 | #define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2198 | #define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2199 | |
kadonotakashi | 0:8fdf9a60065b | 2200 | #define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2201 | #define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2202 | |
kadonotakashi | 0:8fdf9a60065b | 2203 | #define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2204 | #define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2205 | |
kadonotakashi | 0:8fdf9a60065b | 2206 | #define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2207 | #define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2208 | |
kadonotakashi | 0:8fdf9a60065b | 2209 | #define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2210 | #define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2211 | |
kadonotakashi | 0:8fdf9a60065b | 2212 | #define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2213 | #define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2214 | |
kadonotakashi | 0:8fdf9a60065b | 2215 | #define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */ |
kadonotakashi | 0:8fdf9a60065b | 2216 | #define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2217 | |
kadonotakashi | 0:8fdf9a60065b | 2218 | #define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2219 | #define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2220 | |
kadonotakashi | 0:8fdf9a60065b | 2221 | #define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2222 | #define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2223 | |
kadonotakashi | 0:8fdf9a60065b | 2224 | #define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2225 | #define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2226 | |
kadonotakashi | 0:8fdf9a60065b | 2227 | #define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2228 | #define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2229 | |
kadonotakashi | 0:8fdf9a60065b | 2230 | #define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2231 | #define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2232 | |
kadonotakashi | 0:8fdf9a60065b | 2233 | #define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2234 | #define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2235 | |
kadonotakashi | 0:8fdf9a60065b | 2236 | #define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2237 | #define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2238 | |
kadonotakashi | 0:8fdf9a60065b | 2239 | #define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2240 | #define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2241 | |
kadonotakashi | 0:8fdf9a60065b | 2242 | #define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2243 | #define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2244 | |
kadonotakashi | 0:8fdf9a60065b | 2245 | #define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2246 | #define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2247 | |
kadonotakashi | 0:8fdf9a60065b | 2248 | #define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2249 | #define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2250 | |
kadonotakashi | 0:8fdf9a60065b | 2251 | #define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2252 | #define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2253 | |
kadonotakashi | 0:8fdf9a60065b | 2254 | #define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2255 | #define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2256 | |
kadonotakashi | 0:8fdf9a60065b | 2257 | #define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2258 | #define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2259 | |
kadonotakashi | 0:8fdf9a60065b | 2260 | #define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2261 | #define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2262 | |
kadonotakashi | 0:8fdf9a60065b | 2263 | #define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2264 | #define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2265 | |
kadonotakashi | 0:8fdf9a60065b | 2266 | #define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2267 | #define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2268 | |
kadonotakashi | 0:8fdf9a60065b | 2269 | #define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2270 | #define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2271 | |
kadonotakashi | 0:8fdf9a60065b | 2272 | #define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2273 | #define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2274 | |
kadonotakashi | 0:8fdf9a60065b | 2275 | #define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2276 | #define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2277 | |
kadonotakashi | 0:8fdf9a60065b | 2278 | #define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2279 | #define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2280 | |
kadonotakashi | 0:8fdf9a60065b | 2281 | #define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2282 | #define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2283 | |
kadonotakashi | 0:8fdf9a60065b | 2284 | #define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 2285 | #define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2286 | |
kadonotakashi | 0:8fdf9a60065b | 2287 | #define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2288 | #define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2289 | |
kadonotakashi | 0:8fdf9a60065b | 2290 | #define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */ |
kadonotakashi | 0:8fdf9a60065b | 2291 | #define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2292 | |
kadonotakashi | 0:8fdf9a60065b | 2293 | #define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2294 | #define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2295 | |
kadonotakashi | 0:8fdf9a60065b | 2296 | #define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2297 | #define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2298 | |
kadonotakashi | 0:8fdf9a60065b | 2299 | #define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2300 | #define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2301 | |
kadonotakashi | 0:8fdf9a60065b | 2302 | #define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2303 | #define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2304 | |
kadonotakashi | 0:8fdf9a60065b | 2305 | #define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2306 | #define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2307 | |
kadonotakashi | 0:8fdf9a60065b | 2308 | #define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2309 | #define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2310 | |
kadonotakashi | 0:8fdf9a60065b | 2311 | #define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2312 | #define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2313 | |
kadonotakashi | 0:8fdf9a60065b | 2314 | #define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2315 | #define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2316 | |
kadonotakashi | 0:8fdf9a60065b | 2317 | #define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2318 | #define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2319 | |
kadonotakashi | 0:8fdf9a60065b | 2320 | #define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */ |
kadonotakashi | 0:8fdf9a60065b | 2321 | #define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2322 | |
kadonotakashi | 0:8fdf9a60065b | 2323 | #define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */ |
kadonotakashi | 0:8fdf9a60065b | 2324 | #define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2325 | |
kadonotakashi | 0:8fdf9a60065b | 2326 | #define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */ |
kadonotakashi | 0:8fdf9a60065b | 2327 | #define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2328 | |
kadonotakashi | 0:8fdf9a60065b | 2329 | #define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2330 | #define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2331 | |
kadonotakashi | 0:8fdf9a60065b | 2332 | #define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2333 | #define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2334 | |
kadonotakashi | 0:8fdf9a60065b | 2335 | #define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2336 | #define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2337 | |
kadonotakashi | 0:8fdf9a60065b | 2338 | #define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2339 | #define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2340 | |
kadonotakashi | 0:8fdf9a60065b | 2341 | #define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2342 | #define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2343 | |
kadonotakashi | 0:8fdf9a60065b | 2344 | #define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2345 | #define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2346 | |
kadonotakashi | 0:8fdf9a60065b | 2347 | #define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2348 | #define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2349 | |
kadonotakashi | 0:8fdf9a60065b | 2350 | #define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2351 | #define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2352 | |
kadonotakashi | 0:8fdf9a60065b | 2353 | #define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2354 | #define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2355 | |
kadonotakashi | 0:8fdf9a60065b | 2356 | #define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2357 | #define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2358 | |
kadonotakashi | 0:8fdf9a60065b | 2359 | #define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2360 | #define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2361 | |
kadonotakashi | 0:8fdf9a60065b | 2362 | #define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2363 | #define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2364 | |
kadonotakashi | 0:8fdf9a60065b | 2365 | #define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2366 | #define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2367 | |
kadonotakashi | 0:8fdf9a60065b | 2368 | #define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2369 | #define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2370 | |
kadonotakashi | 0:8fdf9a60065b | 2371 | #define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2372 | #define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2373 | |
kadonotakashi | 0:8fdf9a60065b | 2374 | #define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2375 | #define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2376 | |
kadonotakashi | 0:8fdf9a60065b | 2377 | #define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2378 | #define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2379 | |
kadonotakashi | 0:8fdf9a60065b | 2380 | #define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2381 | #define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2382 | |
kadonotakashi | 0:8fdf9a60065b | 2383 | #define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */ |
kadonotakashi | 0:8fdf9a60065b | 2384 | #define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2385 | |
kadonotakashi | 0:8fdf9a60065b | 2386 | #define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */ |
kadonotakashi | 0:8fdf9a60065b | 2387 | #define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2388 | |
kadonotakashi | 0:8fdf9a60065b | 2389 | #define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */ |
kadonotakashi | 0:8fdf9a60065b | 2390 | #define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2391 | |
kadonotakashi | 0:8fdf9a60065b | 2392 | #define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */ |
kadonotakashi | 0:8fdf9a60065b | 2393 | #define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2394 | |
kadonotakashi | 0:8fdf9a60065b | 2395 | #define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */ |
kadonotakashi | 0:8fdf9a60065b | 2396 | #define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2397 | |
kadonotakashi | 0:8fdf9a60065b | 2398 | #define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */ |
kadonotakashi | 0:8fdf9a60065b | 2399 | #define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2400 | |
kadonotakashi | 0:8fdf9a60065b | 2401 | #define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */ |
kadonotakashi | 0:8fdf9a60065b | 2402 | #define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2403 | |
kadonotakashi | 0:8fdf9a60065b | 2404 | #define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */ |
kadonotakashi | 0:8fdf9a60065b | 2405 | #define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2406 | |
kadonotakashi | 0:8fdf9a60065b | 2407 | #define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */ |
kadonotakashi | 0:8fdf9a60065b | 2408 | #define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2409 | |
kadonotakashi | 0:8fdf9a60065b | 2410 | #define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */ |
kadonotakashi | 0:8fdf9a60065b | 2411 | #define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2412 | |
kadonotakashi | 0:8fdf9a60065b | 2413 | #define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */ |
kadonotakashi | 0:8fdf9a60065b | 2414 | #define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2415 | |
kadonotakashi | 0:8fdf9a60065b | 2416 | #define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */ |
kadonotakashi | 0:8fdf9a60065b | 2417 | #define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2418 | |
kadonotakashi | 0:8fdf9a60065b | 2419 | #define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2420 | #define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2421 | |
kadonotakashi | 0:8fdf9a60065b | 2422 | #define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2423 | #define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2424 | |
kadonotakashi | 0:8fdf9a60065b | 2425 | #define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 2426 | #define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2427 | |
kadonotakashi | 0:8fdf9a60065b | 2428 | #define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2429 | #define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2430 | |
kadonotakashi | 0:8fdf9a60065b | 2431 | #define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2432 | #define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2433 | |
kadonotakashi | 0:8fdf9a60065b | 2434 | #define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 2435 | #define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2436 | |
kadonotakashi | 0:8fdf9a60065b | 2437 | #define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2438 | #define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2439 | |
kadonotakashi | 0:8fdf9a60065b | 2440 | #define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2441 | #define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2442 | |
kadonotakashi | 0:8fdf9a60065b | 2443 | #define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 2444 | #define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2445 | |
kadonotakashi | 0:8fdf9a60065b | 2446 | #define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */ |
kadonotakashi | 0:8fdf9a60065b | 2447 | #define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2448 | |
kadonotakashi | 0:8fdf9a60065b | 2449 | #define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */ |
kadonotakashi | 0:8fdf9a60065b | 2450 | #define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2451 | |
kadonotakashi | 0:8fdf9a60065b | 2452 | #define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */ |
kadonotakashi | 0:8fdf9a60065b | 2453 | #define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2454 | |
kadonotakashi | 0:8fdf9a60065b | 2455 | #define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2456 | #define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2457 | |
kadonotakashi | 0:8fdf9a60065b | 2458 | #define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */ |
kadonotakashi | 0:8fdf9a60065b | 2459 | #define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2460 | |
kadonotakashi | 0:8fdf9a60065b | 2461 | #define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2462 | #define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2463 | |
kadonotakashi | 0:8fdf9a60065b | 2464 | #define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */ |
kadonotakashi | 0:8fdf9a60065b | 2465 | #define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2466 | |
kadonotakashi | 0:8fdf9a60065b | 2467 | #define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2468 | #define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2469 | |
kadonotakashi | 0:8fdf9a60065b | 2470 | #define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */ |
kadonotakashi | 0:8fdf9a60065b | 2471 | #define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2472 | |
kadonotakashi | 0:8fdf9a60065b | 2473 | #define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2474 | #define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2475 | |
kadonotakashi | 0:8fdf9a60065b | 2476 | #define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */ |
kadonotakashi | 0:8fdf9a60065b | 2477 | #define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2478 | |
kadonotakashi | 0:8fdf9a60065b | 2479 | #define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2480 | #define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2481 | |
kadonotakashi | 0:8fdf9a60065b | 2482 | #define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */ |
kadonotakashi | 0:8fdf9a60065b | 2483 | #define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2484 | |
kadonotakashi | 0:8fdf9a60065b | 2485 | #define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2486 | #define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2487 | |
kadonotakashi | 0:8fdf9a60065b | 2488 | #define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */ |
kadonotakashi | 0:8fdf9a60065b | 2489 | #define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2490 | |
kadonotakashi | 0:8fdf9a60065b | 2491 | #define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2492 | #define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2493 | |
kadonotakashi | 0:8fdf9a60065b | 2494 | #define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2495 | #define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2496 | |
kadonotakashi | 0:8fdf9a60065b | 2497 | #define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2498 | #define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2499 | |
kadonotakashi | 0:8fdf9a60065b | 2500 | #define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2501 | #define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2502 | |
kadonotakashi | 0:8fdf9a60065b | 2503 | #define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2504 | #define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2505 | |
kadonotakashi | 0:8fdf9a60065b | 2506 | #define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2507 | #define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2508 | |
kadonotakashi | 0:8fdf9a60065b | 2509 | #define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2510 | #define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2511 | |
kadonotakashi | 0:8fdf9a60065b | 2512 | #define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2513 | #define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2514 | |
kadonotakashi | 0:8fdf9a60065b | 2515 | #define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2516 | #define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2517 | |
kadonotakashi | 0:8fdf9a60065b | 2518 | #define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2519 | #define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2520 | |
kadonotakashi | 0:8fdf9a60065b | 2521 | #define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2522 | #define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2523 | |
kadonotakashi | 0:8fdf9a60065b | 2524 | #define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2525 | #define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2526 | |
kadonotakashi | 0:8fdf9a60065b | 2527 | #define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2528 | #define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2529 | |
kadonotakashi | 0:8fdf9a60065b | 2530 | #define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2531 | #define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2532 | |
kadonotakashi | 0:8fdf9a60065b | 2533 | #define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2534 | #define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2535 | |
kadonotakashi | 0:8fdf9a60065b | 2536 | #define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2537 | #define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2538 | |
kadonotakashi | 0:8fdf9a60065b | 2539 | #define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2540 | #define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2541 | |
kadonotakashi | 0:8fdf9a60065b | 2542 | #define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2543 | #define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2544 | |
kadonotakashi | 0:8fdf9a60065b | 2545 | #define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2546 | #define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2547 | |
kadonotakashi | 0:8fdf9a60065b | 2548 | #define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2549 | #define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2550 | |
kadonotakashi | 0:8fdf9a60065b | 2551 | #define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2552 | #define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2553 | |
kadonotakashi | 0:8fdf9a60065b | 2554 | #define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2555 | #define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2556 | |
kadonotakashi | 0:8fdf9a60065b | 2557 | #define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2558 | #define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2559 | |
kadonotakashi | 0:8fdf9a60065b | 2560 | #define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2561 | #define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2562 | |
kadonotakashi | 0:8fdf9a60065b | 2563 | #define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2564 | #define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2565 | |
kadonotakashi | 0:8fdf9a60065b | 2566 | #define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2567 | #define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2568 | |
kadonotakashi | 0:8fdf9a60065b | 2569 | #define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2570 | #define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2571 | |
kadonotakashi | 0:8fdf9a60065b | 2572 | #define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2573 | #define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2574 | |
kadonotakashi | 0:8fdf9a60065b | 2575 | #define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2576 | #define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2577 | |
kadonotakashi | 0:8fdf9a60065b | 2578 | #define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2579 | #define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2580 | |
kadonotakashi | 0:8fdf9a60065b | 2581 | #define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2582 | #define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2583 | |
kadonotakashi | 0:8fdf9a60065b | 2584 | #define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2585 | #define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2586 | |
kadonotakashi | 0:8fdf9a60065b | 2587 | #define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2588 | #define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2589 | |
kadonotakashi | 0:8fdf9a60065b | 2590 | #define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2591 | #define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2592 | |
kadonotakashi | 0:8fdf9a60065b | 2593 | #define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2594 | #define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2595 | |
kadonotakashi | 0:8fdf9a60065b | 2596 | #define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2597 | #define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2598 | |
kadonotakashi | 0:8fdf9a60065b | 2599 | #define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2600 | #define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2601 | |
kadonotakashi | 0:8fdf9a60065b | 2602 | #define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 2603 | #define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2604 | |
kadonotakashi | 0:8fdf9a60065b | 2605 | #define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2606 | #define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2607 | |
kadonotakashi | 0:8fdf9a60065b | 2608 | #define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */ |
kadonotakashi | 0:8fdf9a60065b | 2609 | #define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2610 | |
kadonotakashi | 0:8fdf9a60065b | 2611 | #define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2612 | #define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2613 | |
kadonotakashi | 0:8fdf9a60065b | 2614 | #define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 2615 | #define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2616 | |
kadonotakashi | 0:8fdf9a60065b | 2617 | #define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 2618 | #define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2619 | |
kadonotakashi | 0:8fdf9a60065b | 2620 | #define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */ |
kadonotakashi | 0:8fdf9a60065b | 2621 | #define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2622 | |
kadonotakashi | 0:8fdf9a60065b | 2623 | #define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */ |
kadonotakashi | 0:8fdf9a60065b | 2624 | #define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2625 | |
kadonotakashi | 0:8fdf9a60065b | 2626 | #define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */ |
kadonotakashi | 0:8fdf9a60065b | 2627 | #define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2628 | |
kadonotakashi | 0:8fdf9a60065b | 2629 | #define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2630 | #define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2631 | |
kadonotakashi | 0:8fdf9a60065b | 2632 | #define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2633 | #define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2634 | |
kadonotakashi | 0:8fdf9a60065b | 2635 | #define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2636 | #define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2637 | |
kadonotakashi | 0:8fdf9a60065b | 2638 | #define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2639 | #define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2640 | |
kadonotakashi | 0:8fdf9a60065b | 2641 | #define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2642 | #define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2643 | |
kadonotakashi | 0:8fdf9a60065b | 2644 | #define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2645 | #define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2646 | |
kadonotakashi | 0:8fdf9a60065b | 2647 | #define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2648 | #define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2649 | |
kadonotakashi | 0:8fdf9a60065b | 2650 | #define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2651 | #define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2652 | |
kadonotakashi | 0:8fdf9a60065b | 2653 | #define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2654 | #define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2655 | |
kadonotakashi | 0:8fdf9a60065b | 2656 | #define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2657 | #define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2658 | |
kadonotakashi | 0:8fdf9a60065b | 2659 | #define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2660 | #define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2661 | |
kadonotakashi | 0:8fdf9a60065b | 2662 | #define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2663 | #define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2664 | |
kadonotakashi | 0:8fdf9a60065b | 2665 | #define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2666 | #define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2667 | |
kadonotakashi | 0:8fdf9a60065b | 2668 | #define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2669 | #define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2670 | |
kadonotakashi | 0:8fdf9a60065b | 2671 | #define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2672 | #define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2673 | |
kadonotakashi | 0:8fdf9a60065b | 2674 | #define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */ |
kadonotakashi | 0:8fdf9a60065b | 2675 | #define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2676 | |
kadonotakashi | 0:8fdf9a60065b | 2677 | #define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2678 | #define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2679 | |
kadonotakashi | 0:8fdf9a60065b | 2680 | #define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2681 | #define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2682 | |
kadonotakashi | 0:8fdf9a60065b | 2683 | #define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2684 | #define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2685 | |
kadonotakashi | 0:8fdf9a60065b | 2686 | #define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2687 | #define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2688 | |
kadonotakashi | 0:8fdf9a60065b | 2689 | #define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2690 | #define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2691 | |
kadonotakashi | 0:8fdf9a60065b | 2692 | #define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2693 | #define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2694 | |
kadonotakashi | 0:8fdf9a60065b | 2695 | #define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2696 | #define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2697 | |
kadonotakashi | 0:8fdf9a60065b | 2698 | #define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2699 | #define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2700 | |
kadonotakashi | 0:8fdf9a60065b | 2701 | #define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2702 | #define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2703 | |
kadonotakashi | 0:8fdf9a60065b | 2704 | #define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2705 | #define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2706 | |
kadonotakashi | 0:8fdf9a60065b | 2707 | #define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2708 | #define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2709 | |
kadonotakashi | 0:8fdf9a60065b | 2710 | #define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2711 | #define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2712 | |
kadonotakashi | 0:8fdf9a60065b | 2713 | #define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2714 | #define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2715 | |
kadonotakashi | 0:8fdf9a60065b | 2716 | #define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */ |
kadonotakashi | 0:8fdf9a60065b | 2717 | #define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2718 | |
kadonotakashi | 0:8fdf9a60065b | 2719 | #define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2720 | #define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2721 | |
kadonotakashi | 0:8fdf9a60065b | 2722 | #define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2723 | #define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2724 | |
kadonotakashi | 0:8fdf9a60065b | 2725 | #define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2726 | #define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2727 | |
kadonotakashi | 0:8fdf9a60065b | 2728 | #define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2729 | #define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2730 | |
kadonotakashi | 0:8fdf9a60065b | 2731 | #define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2732 | #define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2733 | |
kadonotakashi | 0:8fdf9a60065b | 2734 | #define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2735 | #define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2736 | |
kadonotakashi | 0:8fdf9a60065b | 2737 | #define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2738 | #define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2739 | |
kadonotakashi | 0:8fdf9a60065b | 2740 | #define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2741 | #define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2742 | |
kadonotakashi | 0:8fdf9a60065b | 2743 | #define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2744 | #define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2745 | |
kadonotakashi | 0:8fdf9a60065b | 2746 | #define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2747 | #define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2748 | |
kadonotakashi | 0:8fdf9a60065b | 2749 | #define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2750 | #define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2751 | |
kadonotakashi | 0:8fdf9a60065b | 2752 | #define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2753 | #define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2754 | |
kadonotakashi | 0:8fdf9a60065b | 2755 | #define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2756 | #define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2757 | |
kadonotakashi | 0:8fdf9a60065b | 2758 | #define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */ |
kadonotakashi | 0:8fdf9a60065b | 2759 | #define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2760 | |
kadonotakashi | 0:8fdf9a60065b | 2761 | #define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2762 | #define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2763 | |
kadonotakashi | 0:8fdf9a60065b | 2764 | #define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 2765 | #define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2766 | |
kadonotakashi | 0:8fdf9a60065b | 2767 | #define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2768 | #define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2769 | |
kadonotakashi | 0:8fdf9a60065b | 2770 | #define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2771 | #define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2772 | |
kadonotakashi | 0:8fdf9a60065b | 2773 | #define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2774 | #define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2775 | |
kadonotakashi | 0:8fdf9a60065b | 2776 | #define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2777 | #define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2778 | |
kadonotakashi | 0:8fdf9a60065b | 2779 | #define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2780 | #define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2781 | |
kadonotakashi | 0:8fdf9a60065b | 2782 | #define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2783 | #define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2784 | |
kadonotakashi | 0:8fdf9a60065b | 2785 | #define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2786 | #define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2787 | |
kadonotakashi | 0:8fdf9a60065b | 2788 | #define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2789 | #define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2790 | |
kadonotakashi | 0:8fdf9a60065b | 2791 | #define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2792 | #define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2793 | |
kadonotakashi | 0:8fdf9a60065b | 2794 | #define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2795 | #define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2796 | |
kadonotakashi | 0:8fdf9a60065b | 2797 | #define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2798 | #define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2799 | |
kadonotakashi | 0:8fdf9a60065b | 2800 | #define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2801 | #define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2802 | |
kadonotakashi | 0:8fdf9a60065b | 2803 | #define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2804 | #define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2805 | |
kadonotakashi | 0:8fdf9a60065b | 2806 | #define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2807 | #define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2808 | |
kadonotakashi | 0:8fdf9a60065b | 2809 | #define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2810 | #define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2811 | |
kadonotakashi | 0:8fdf9a60065b | 2812 | #define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2813 | #define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2814 | |
kadonotakashi | 0:8fdf9a60065b | 2815 | #define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2816 | #define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2817 | |
kadonotakashi | 0:8fdf9a60065b | 2818 | #define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2819 | #define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2820 | |
kadonotakashi | 0:8fdf9a60065b | 2821 | #define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2822 | #define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2823 | |
kadonotakashi | 0:8fdf9a60065b | 2824 | #define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2825 | #define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2826 | |
kadonotakashi | 0:8fdf9a60065b | 2827 | #define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2828 | #define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2829 | |
kadonotakashi | 0:8fdf9a60065b | 2830 | #define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2831 | #define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2832 | |
kadonotakashi | 0:8fdf9a60065b | 2833 | #define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2834 | #define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2835 | |
kadonotakashi | 0:8fdf9a60065b | 2836 | #define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2837 | #define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2838 | |
kadonotakashi | 0:8fdf9a60065b | 2839 | #define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2840 | #define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2841 | |
kadonotakashi | 0:8fdf9a60065b | 2842 | #define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2843 | #define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2844 | |
kadonotakashi | 0:8fdf9a60065b | 2845 | #define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2846 | #define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2847 | |
kadonotakashi | 0:8fdf9a60065b | 2848 | #define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2849 | #define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2850 | |
kadonotakashi | 0:8fdf9a60065b | 2851 | #define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2852 | #define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2853 | |
kadonotakashi | 0:8fdf9a60065b | 2854 | #define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2855 | #define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2856 | |
kadonotakashi | 0:8fdf9a60065b | 2857 | #define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2858 | #define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2859 | |
kadonotakashi | 0:8fdf9a60065b | 2860 | #define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2861 | #define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2862 | |
kadonotakashi | 0:8fdf9a60065b | 2863 | #define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2864 | #define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2865 | |
kadonotakashi | 0:8fdf9a60065b | 2866 | #define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2867 | #define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2868 | |
kadonotakashi | 0:8fdf9a60065b | 2869 | #define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2870 | #define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2871 | |
kadonotakashi | 0:8fdf9a60065b | 2872 | #define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2873 | #define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2874 | |
kadonotakashi | 0:8fdf9a60065b | 2875 | #define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2876 | #define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2877 | |
kadonotakashi | 0:8fdf9a60065b | 2878 | #define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2879 | #define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2880 | |
kadonotakashi | 0:8fdf9a60065b | 2881 | #define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2882 | #define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2883 | |
kadonotakashi | 0:8fdf9a60065b | 2884 | #define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2885 | #define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2886 | |
kadonotakashi | 0:8fdf9a60065b | 2887 | #define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2888 | #define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2889 | |
kadonotakashi | 0:8fdf9a60065b | 2890 | #define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2891 | #define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2892 | |
kadonotakashi | 0:8fdf9a60065b | 2893 | #define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2894 | #define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2895 | |
kadonotakashi | 0:8fdf9a60065b | 2896 | #define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2897 | #define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2898 | |
kadonotakashi | 0:8fdf9a60065b | 2899 | #define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2900 | #define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2901 | |
kadonotakashi | 0:8fdf9a60065b | 2902 | #define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2903 | #define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2904 | |
kadonotakashi | 0:8fdf9a60065b | 2905 | #define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2906 | #define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2907 | |
kadonotakashi | 0:8fdf9a60065b | 2908 | #define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2909 | #define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2910 | |
kadonotakashi | 0:8fdf9a60065b | 2911 | #define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2912 | #define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2913 | |
kadonotakashi | 0:8fdf9a60065b | 2914 | #define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2915 | #define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2916 | |
kadonotakashi | 0:8fdf9a60065b | 2917 | #define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2918 | #define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2919 | |
kadonotakashi | 0:8fdf9a60065b | 2920 | #define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2921 | #define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2922 | |
kadonotakashi | 0:8fdf9a60065b | 2923 | #define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2924 | #define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2925 | |
kadonotakashi | 0:8fdf9a60065b | 2926 | #define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2927 | #define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2928 | |
kadonotakashi | 0:8fdf9a60065b | 2929 | #define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2930 | #define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2931 | |
kadonotakashi | 0:8fdf9a60065b | 2932 | #define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2933 | #define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2934 | |
kadonotakashi | 0:8fdf9a60065b | 2935 | #define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2936 | #define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2937 | |
kadonotakashi | 0:8fdf9a60065b | 2938 | #define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2939 | #define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2940 | |
kadonotakashi | 0:8fdf9a60065b | 2941 | #define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2942 | #define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2943 | |
kadonotakashi | 0:8fdf9a60065b | 2944 | #define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2945 | #define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2946 | |
kadonotakashi | 0:8fdf9a60065b | 2947 | #define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2948 | #define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2949 | |
kadonotakashi | 0:8fdf9a60065b | 2950 | #define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2951 | #define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2952 | |
kadonotakashi | 0:8fdf9a60065b | 2953 | #define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2954 | #define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2955 | |
kadonotakashi | 0:8fdf9a60065b | 2956 | #define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2957 | #define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2958 | |
kadonotakashi | 0:8fdf9a60065b | 2959 | #define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2960 | #define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2961 | |
kadonotakashi | 0:8fdf9a60065b | 2962 | #define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2963 | #define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2964 | |
kadonotakashi | 0:8fdf9a60065b | 2965 | #define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2966 | #define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2967 | |
kadonotakashi | 0:8fdf9a60065b | 2968 | #define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2969 | #define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2970 | |
kadonotakashi | 0:8fdf9a60065b | 2971 | #define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2972 | #define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2973 | |
kadonotakashi | 0:8fdf9a60065b | 2974 | #define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2975 | #define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2976 | |
kadonotakashi | 0:8fdf9a60065b | 2977 | #define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2978 | #define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2979 | |
kadonotakashi | 0:8fdf9a60065b | 2980 | #define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2981 | #define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2982 | |
kadonotakashi | 0:8fdf9a60065b | 2983 | #define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2984 | #define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2985 | |
kadonotakashi | 0:8fdf9a60065b | 2986 | #define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2987 | #define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2988 | |
kadonotakashi | 0:8fdf9a60065b | 2989 | #define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2990 | #define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2991 | |
kadonotakashi | 0:8fdf9a60065b | 2992 | #define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2993 | #define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2994 | |
kadonotakashi | 0:8fdf9a60065b | 2995 | #define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2996 | #define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 2997 | |
kadonotakashi | 0:8fdf9a60065b | 2998 | #define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 2999 | #define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3000 | |
kadonotakashi | 0:8fdf9a60065b | 3001 | #define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3002 | #define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3003 | |
kadonotakashi | 0:8fdf9a60065b | 3004 | #define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3005 | #define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3006 | |
kadonotakashi | 0:8fdf9a60065b | 3007 | #define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3008 | #define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3009 | |
kadonotakashi | 0:8fdf9a60065b | 3010 | #define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3011 | #define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3012 | |
kadonotakashi | 0:8fdf9a60065b | 3013 | #define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3014 | #define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3015 | |
kadonotakashi | 0:8fdf9a60065b | 3016 | #define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3017 | #define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3018 | |
kadonotakashi | 0:8fdf9a60065b | 3019 | #define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3020 | #define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3021 | |
kadonotakashi | 0:8fdf9a60065b | 3022 | #define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3023 | #define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3024 | |
kadonotakashi | 0:8fdf9a60065b | 3025 | #define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3026 | #define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3027 | |
kadonotakashi | 0:8fdf9a60065b | 3028 | #define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3029 | #define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3030 | |
kadonotakashi | 0:8fdf9a60065b | 3031 | #define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3032 | #define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3033 | |
kadonotakashi | 0:8fdf9a60065b | 3034 | #define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3035 | #define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3036 | |
kadonotakashi | 0:8fdf9a60065b | 3037 | #define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3038 | #define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3039 | |
kadonotakashi | 0:8fdf9a60065b | 3040 | #define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3041 | #define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3042 | |
kadonotakashi | 0:8fdf9a60065b | 3043 | #define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3044 | #define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3045 | |
kadonotakashi | 0:8fdf9a60065b | 3046 | #define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3047 | #define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3048 | |
kadonotakashi | 0:8fdf9a60065b | 3049 | #define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3050 | #define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3051 | |
kadonotakashi | 0:8fdf9a60065b | 3052 | #define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3053 | #define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3054 | |
kadonotakashi | 0:8fdf9a60065b | 3055 | #define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3056 | #define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3057 | |
kadonotakashi | 0:8fdf9a60065b | 3058 | #define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3059 | #define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3060 | |
kadonotakashi | 0:8fdf9a60065b | 3061 | #define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3062 | #define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3063 | |
kadonotakashi | 0:8fdf9a60065b | 3064 | #define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3065 | #define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3066 | |
kadonotakashi | 0:8fdf9a60065b | 3067 | #define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3068 | #define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3069 | |
kadonotakashi | 0:8fdf9a60065b | 3070 | #define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3071 | #define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3072 | |
kadonotakashi | 0:8fdf9a60065b | 3073 | #define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3074 | #define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3075 | |
kadonotakashi | 0:8fdf9a60065b | 3076 | #define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3077 | #define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3078 | |
kadonotakashi | 0:8fdf9a60065b | 3079 | #define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3080 | #define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3081 | |
kadonotakashi | 0:8fdf9a60065b | 3082 | #define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3083 | #define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3084 | |
kadonotakashi | 0:8fdf9a60065b | 3085 | #define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3086 | #define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3087 | |
kadonotakashi | 0:8fdf9a60065b | 3088 | #define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3089 | #define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3090 | |
kadonotakashi | 0:8fdf9a60065b | 3091 | #define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3092 | #define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3093 | |
kadonotakashi | 0:8fdf9a60065b | 3094 | #define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3095 | #define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3096 | |
kadonotakashi | 0:8fdf9a60065b | 3097 | #define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3098 | #define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3099 | |
kadonotakashi | 0:8fdf9a60065b | 3100 | #define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3101 | #define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3102 | |
kadonotakashi | 0:8fdf9a60065b | 3103 | #define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3104 | #define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3105 | |
kadonotakashi | 0:8fdf9a60065b | 3106 | #define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3107 | #define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3108 | |
kadonotakashi | 0:8fdf9a60065b | 3109 | #define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3110 | #define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3111 | |
kadonotakashi | 0:8fdf9a60065b | 3112 | #define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3113 | #define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3114 | |
kadonotakashi | 0:8fdf9a60065b | 3115 | #define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3116 | #define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3117 | |
kadonotakashi | 0:8fdf9a60065b | 3118 | #define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3119 | #define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3120 | |
kadonotakashi | 0:8fdf9a60065b | 3121 | #define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3122 | #define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3123 | |
kadonotakashi | 0:8fdf9a60065b | 3124 | #define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3125 | #define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3126 | |
kadonotakashi | 0:8fdf9a60065b | 3127 | #define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3128 | #define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3129 | |
kadonotakashi | 0:8fdf9a60065b | 3130 | #define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3131 | #define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3132 | |
kadonotakashi | 0:8fdf9a60065b | 3133 | #define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3134 | #define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3135 | |
kadonotakashi | 0:8fdf9a60065b | 3136 | #define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3137 | #define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3138 | |
kadonotakashi | 0:8fdf9a60065b | 3139 | #define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3140 | #define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3141 | |
kadonotakashi | 0:8fdf9a60065b | 3142 | #define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3143 | #define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3144 | |
kadonotakashi | 0:8fdf9a60065b | 3145 | #define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3146 | #define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3147 | |
kadonotakashi | 0:8fdf9a60065b | 3148 | #define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3149 | #define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3150 | |
kadonotakashi | 0:8fdf9a60065b | 3151 | #define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3152 | #define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3153 | |
kadonotakashi | 0:8fdf9a60065b | 3154 | #define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3155 | #define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3156 | |
kadonotakashi | 0:8fdf9a60065b | 3157 | #define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3158 | #define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3159 | |
kadonotakashi | 0:8fdf9a60065b | 3160 | #define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3161 | #define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3162 | |
kadonotakashi | 0:8fdf9a60065b | 3163 | #define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */ |
kadonotakashi | 0:8fdf9a60065b | 3164 | #define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3165 | |
kadonotakashi | 0:8fdf9a60065b | 3166 | #define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */ |
kadonotakashi | 0:8fdf9a60065b | 3167 | #define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3168 | |
kadonotakashi | 0:8fdf9a60065b | 3169 | #define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */ |
kadonotakashi | 0:8fdf9a60065b | 3170 | #define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3171 | |
kadonotakashi | 0:8fdf9a60065b | 3172 | #define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3173 | #define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3174 | |
kadonotakashi | 0:8fdf9a60065b | 3175 | #define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3176 | #define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3177 | |
kadonotakashi | 0:8fdf9a60065b | 3178 | #define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3179 | #define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3180 | |
kadonotakashi | 0:8fdf9a60065b | 3181 | #define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3182 | #define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3183 | |
kadonotakashi | 0:8fdf9a60065b | 3184 | #define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3185 | #define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3186 | |
kadonotakashi | 0:8fdf9a60065b | 3187 | #define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3188 | #define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3189 | |
kadonotakashi | 0:8fdf9a60065b | 3190 | #define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */ |
kadonotakashi | 0:8fdf9a60065b | 3191 | #define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3192 | |
kadonotakashi | 0:8fdf9a60065b | 3193 | #define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 3194 | #define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3195 | |
kadonotakashi | 0:8fdf9a60065b | 3196 | #define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 3197 | #define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3198 | |
kadonotakashi | 0:8fdf9a60065b | 3199 | #define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3200 | #define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3201 | |
kadonotakashi | 0:8fdf9a60065b | 3202 | #define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3203 | #define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3204 | |
kadonotakashi | 0:8fdf9a60065b | 3205 | #define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3206 | #define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3207 | |
kadonotakashi | 0:8fdf9a60065b | 3208 | #define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */ |
kadonotakashi | 0:8fdf9a60065b | 3209 | #define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3210 | |
kadonotakashi | 0:8fdf9a60065b | 3211 | #define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3212 | #define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3213 | |
kadonotakashi | 0:8fdf9a60065b | 3214 | #define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3215 | #define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3216 | |
kadonotakashi | 0:8fdf9a60065b | 3217 | #define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3218 | #define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3219 | |
kadonotakashi | 0:8fdf9a60065b | 3220 | #define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3221 | #define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3222 | |
kadonotakashi | 0:8fdf9a60065b | 3223 | #define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3224 | #define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3225 | |
kadonotakashi | 0:8fdf9a60065b | 3226 | #define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3227 | #define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3228 | |
kadonotakashi | 0:8fdf9a60065b | 3229 | #define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3230 | #define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3231 | |
kadonotakashi | 0:8fdf9a60065b | 3232 | #define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3233 | #define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3234 | |
kadonotakashi | 0:8fdf9a60065b | 3235 | #define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3236 | #define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3237 | |
kadonotakashi | 0:8fdf9a60065b | 3238 | #define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3239 | #define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3240 | |
kadonotakashi | 0:8fdf9a60065b | 3241 | #define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3242 | #define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3243 | |
kadonotakashi | 0:8fdf9a60065b | 3244 | #define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3245 | #define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3246 | |
kadonotakashi | 0:8fdf9a60065b | 3247 | #define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3248 | #define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3249 | |
kadonotakashi | 0:8fdf9a60065b | 3250 | #define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3251 | #define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3252 | |
kadonotakashi | 0:8fdf9a60065b | 3253 | #define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3254 | #define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3255 | |
kadonotakashi | 0:8fdf9a60065b | 3256 | #define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3257 | #define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3258 | |
kadonotakashi | 0:8fdf9a60065b | 3259 | #define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3260 | #define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3261 | |
kadonotakashi | 0:8fdf9a60065b | 3262 | #define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3263 | #define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3264 | |
kadonotakashi | 0:8fdf9a60065b | 3265 | #define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 3266 | #define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3267 | |
kadonotakashi | 0:8fdf9a60065b | 3268 | #define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 3269 | #define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3270 | |
kadonotakashi | 0:8fdf9a60065b | 3271 | #define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3272 | #define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3273 | |
kadonotakashi | 0:8fdf9a60065b | 3274 | #define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 3275 | #define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3276 | |
kadonotakashi | 0:8fdf9a60065b | 3277 | #define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 3278 | #define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3279 | |
kadonotakashi | 0:8fdf9a60065b | 3280 | #define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3281 | #define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3282 | |
kadonotakashi | 0:8fdf9a60065b | 3283 | #define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 3284 | #define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3285 | |
kadonotakashi | 0:8fdf9a60065b | 3286 | #define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 3287 | #define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3288 | |
kadonotakashi | 0:8fdf9a60065b | 3289 | #define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3290 | #define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3291 | |
kadonotakashi | 0:8fdf9a60065b | 3292 | #define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 3293 | #define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3294 | |
kadonotakashi | 0:8fdf9a60065b | 3295 | #define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 3296 | #define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3297 | |
kadonotakashi | 0:8fdf9a60065b | 3298 | #define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3299 | #define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3300 | |
kadonotakashi | 0:8fdf9a60065b | 3301 | #define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 3302 | #define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3303 | |
kadonotakashi | 0:8fdf9a60065b | 3304 | #define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 3305 | #define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3306 | |
kadonotakashi | 0:8fdf9a60065b | 3307 | #define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3308 | #define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3309 | |
kadonotakashi | 0:8fdf9a60065b | 3310 | #define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 3311 | #define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3312 | |
kadonotakashi | 0:8fdf9a60065b | 3313 | #define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */ |
kadonotakashi | 0:8fdf9a60065b | 3314 | #define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3315 | |
kadonotakashi | 0:8fdf9a60065b | 3316 | #define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3317 | #define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3318 | |
kadonotakashi | 0:8fdf9a60065b | 3319 | #define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3320 | #define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3321 | |
kadonotakashi | 0:8fdf9a60065b | 3322 | #define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3323 | #define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3324 | |
kadonotakashi | 0:8fdf9a60065b | 3325 | #define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3326 | #define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3327 | |
kadonotakashi | 0:8fdf9a60065b | 3328 | #define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3329 | #define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3330 | |
kadonotakashi | 0:8fdf9a60065b | 3331 | #define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3332 | #define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3333 | |
kadonotakashi | 0:8fdf9a60065b | 3334 | #define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3335 | #define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3336 | |
kadonotakashi | 0:8fdf9a60065b | 3337 | #define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3338 | #define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3339 | |
kadonotakashi | 0:8fdf9a60065b | 3340 | #define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3341 | #define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3342 | |
kadonotakashi | 0:8fdf9a60065b | 3343 | #define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3344 | #define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3345 | |
kadonotakashi | 0:8fdf9a60065b | 3346 | #define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3347 | #define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3348 | |
kadonotakashi | 0:8fdf9a60065b | 3349 | #define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3350 | #define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3351 | |
kadonotakashi | 0:8fdf9a60065b | 3352 | #define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3353 | #define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3354 | |
kadonotakashi | 0:8fdf9a60065b | 3355 | #define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3356 | #define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3357 | |
kadonotakashi | 0:8fdf9a60065b | 3358 | #define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3359 | #define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3360 | |
kadonotakashi | 0:8fdf9a60065b | 3361 | #define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3362 | #define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3363 | |
kadonotakashi | 0:8fdf9a60065b | 3364 | #define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3365 | #define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3366 | |
kadonotakashi | 0:8fdf9a60065b | 3367 | #define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3368 | #define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3369 | |
kadonotakashi | 0:8fdf9a60065b | 3370 | #define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3371 | #define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3372 | |
kadonotakashi | 0:8fdf9a60065b | 3373 | #define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3374 | #define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3375 | |
kadonotakashi | 0:8fdf9a60065b | 3376 | #define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3377 | #define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3378 | |
kadonotakashi | 0:8fdf9a60065b | 3379 | #define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3380 | #define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3381 | |
kadonotakashi | 0:8fdf9a60065b | 3382 | #define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3383 | #define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3384 | |
kadonotakashi | 0:8fdf9a60065b | 3385 | #define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3386 | #define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3387 | |
kadonotakashi | 0:8fdf9a60065b | 3388 | #define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3389 | #define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3390 | |
kadonotakashi | 0:8fdf9a60065b | 3391 | #define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3392 | #define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3393 | |
kadonotakashi | 0:8fdf9a60065b | 3394 | #define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3395 | #define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3396 | |
kadonotakashi | 0:8fdf9a60065b | 3397 | #define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3398 | #define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3399 | |
kadonotakashi | 0:8fdf9a60065b | 3400 | #define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3401 | #define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3402 | |
kadonotakashi | 0:8fdf9a60065b | 3403 | #define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3404 | #define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3405 | |
kadonotakashi | 0:8fdf9a60065b | 3406 | #define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3407 | #define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3408 | |
kadonotakashi | 0:8fdf9a60065b | 3409 | #define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3410 | #define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3411 | |
kadonotakashi | 0:8fdf9a60065b | 3412 | #define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3413 | #define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3414 | |
kadonotakashi | 0:8fdf9a60065b | 3415 | #define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3416 | #define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3417 | |
kadonotakashi | 0:8fdf9a60065b | 3418 | #define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3419 | #define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3420 | |
kadonotakashi | 0:8fdf9a60065b | 3421 | #define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3422 | #define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3423 | |
kadonotakashi | 0:8fdf9a60065b | 3424 | #define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3425 | #define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3426 | |
kadonotakashi | 0:8fdf9a60065b | 3427 | #define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3428 | #define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3429 | |
kadonotakashi | 0:8fdf9a60065b | 3430 | #define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3431 | #define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3432 | |
kadonotakashi | 0:8fdf9a60065b | 3433 | #define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3434 | #define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3435 | |
kadonotakashi | 0:8fdf9a60065b | 3436 | #define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3437 | #define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3438 | |
kadonotakashi | 0:8fdf9a60065b | 3439 | #define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3440 | #define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3441 | |
kadonotakashi | 0:8fdf9a60065b | 3442 | #define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3443 | #define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3444 | |
kadonotakashi | 0:8fdf9a60065b | 3445 | #define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3446 | #define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3447 | |
kadonotakashi | 0:8fdf9a60065b | 3448 | #define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3449 | #define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3450 | |
kadonotakashi | 0:8fdf9a60065b | 3451 | #define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3452 | #define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3453 | |
kadonotakashi | 0:8fdf9a60065b | 3454 | #define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3455 | #define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3456 | |
kadonotakashi | 0:8fdf9a60065b | 3457 | #define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3458 | #define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3459 | |
kadonotakashi | 0:8fdf9a60065b | 3460 | #define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3461 | #define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3462 | |
kadonotakashi | 0:8fdf9a60065b | 3463 | #define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3464 | #define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3465 | |
kadonotakashi | 0:8fdf9a60065b | 3466 | #define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3467 | #define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3468 | |
kadonotakashi | 0:8fdf9a60065b | 3469 | #define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3470 | #define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3471 | |
kadonotakashi | 0:8fdf9a60065b | 3472 | #define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3473 | #define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3474 | |
kadonotakashi | 0:8fdf9a60065b | 3475 | #define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3476 | #define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3477 | |
kadonotakashi | 0:8fdf9a60065b | 3478 | #define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3479 | #define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3480 | |
kadonotakashi | 0:8fdf9a60065b | 3481 | #define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3482 | #define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3483 | |
kadonotakashi | 0:8fdf9a60065b | 3484 | #define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3485 | #define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3486 | |
kadonotakashi | 0:8fdf9a60065b | 3487 | #define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3488 | #define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3489 | |
kadonotakashi | 0:8fdf9a60065b | 3490 | #define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3491 | #define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3492 | |
kadonotakashi | 0:8fdf9a60065b | 3493 | #define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3494 | #define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3495 | |
kadonotakashi | 0:8fdf9a60065b | 3496 | #define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3497 | #define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3498 | |
kadonotakashi | 0:8fdf9a60065b | 3499 | #define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3500 | #define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3501 | |
kadonotakashi | 0:8fdf9a60065b | 3502 | #define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3503 | #define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3504 | |
kadonotakashi | 0:8fdf9a60065b | 3505 | #define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3506 | #define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3507 | |
kadonotakashi | 0:8fdf9a60065b | 3508 | #define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3509 | #define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3510 | |
kadonotakashi | 0:8fdf9a60065b | 3511 | #define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3512 | #define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3513 | |
kadonotakashi | 0:8fdf9a60065b | 3514 | #define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3515 | #define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3516 | |
kadonotakashi | 0:8fdf9a60065b | 3517 | #define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3518 | #define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3519 | |
kadonotakashi | 0:8fdf9a60065b | 3520 | #define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3521 | #define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3522 | |
kadonotakashi | 0:8fdf9a60065b | 3523 | #define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3524 | #define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3525 | |
kadonotakashi | 0:8fdf9a60065b | 3526 | #define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3527 | #define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3528 | |
kadonotakashi | 0:8fdf9a60065b | 3529 | #define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 3530 | #define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3531 | |
kadonotakashi | 0:8fdf9a60065b | 3532 | #define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3533 | #define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3534 | |
kadonotakashi | 0:8fdf9a60065b | 3535 | #define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3536 | #define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3537 | |
kadonotakashi | 0:8fdf9a60065b | 3538 | #define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3539 | #define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3540 | |
kadonotakashi | 0:8fdf9a60065b | 3541 | #define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3542 | #define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3543 | |
kadonotakashi | 0:8fdf9a60065b | 3544 | #define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3545 | #define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3546 | |
kadonotakashi | 0:8fdf9a60065b | 3547 | #define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3548 | #define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3549 | |
kadonotakashi | 0:8fdf9a60065b | 3550 | #define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3551 | #define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3552 | |
kadonotakashi | 0:8fdf9a60065b | 3553 | #define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3554 | #define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3555 | |
kadonotakashi | 0:8fdf9a60065b | 3556 | #define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3557 | #define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3558 | |
kadonotakashi | 0:8fdf9a60065b | 3559 | #define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3560 | #define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3561 | |
kadonotakashi | 0:8fdf9a60065b | 3562 | #define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3563 | #define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3564 | |
kadonotakashi | 0:8fdf9a60065b | 3565 | #define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3566 | #define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3567 | |
kadonotakashi | 0:8fdf9a60065b | 3568 | #define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3569 | #define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3570 | |
kadonotakashi | 0:8fdf9a60065b | 3571 | #define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3572 | #define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3573 | |
kadonotakashi | 0:8fdf9a60065b | 3574 | #define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3575 | #define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3576 | |
kadonotakashi | 0:8fdf9a60065b | 3577 | #define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3578 | #define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3579 | |
kadonotakashi | 0:8fdf9a60065b | 3580 | #define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3581 | #define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3582 | |
kadonotakashi | 0:8fdf9a60065b | 3583 | #define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3584 | #define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3585 | |
kadonotakashi | 0:8fdf9a60065b | 3586 | #define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3587 | #define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3588 | |
kadonotakashi | 0:8fdf9a60065b | 3589 | #define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3590 | #define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3591 | |
kadonotakashi | 0:8fdf9a60065b | 3592 | #define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3593 | #define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3594 | |
kadonotakashi | 0:8fdf9a60065b | 3595 | #define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3596 | #define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3597 | |
kadonotakashi | 0:8fdf9a60065b | 3598 | #define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3599 | #define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3600 | |
kadonotakashi | 0:8fdf9a60065b | 3601 | #define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3602 | #define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3603 | |
kadonotakashi | 0:8fdf9a60065b | 3604 | #define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3605 | #define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3606 | |
kadonotakashi | 0:8fdf9a60065b | 3607 | #define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3608 | #define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3609 | |
kadonotakashi | 0:8fdf9a60065b | 3610 | #define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3611 | #define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3612 | |
kadonotakashi | 0:8fdf9a60065b | 3613 | #define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3614 | #define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3615 | |
kadonotakashi | 0:8fdf9a60065b | 3616 | #define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3617 | #define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3618 | |
kadonotakashi | 0:8fdf9a60065b | 3619 | #define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3620 | #define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3621 | |
kadonotakashi | 0:8fdf9a60065b | 3622 | #define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3623 | #define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3624 | |
kadonotakashi | 0:8fdf9a60065b | 3625 | #define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3626 | #define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3627 | |
kadonotakashi | 0:8fdf9a60065b | 3628 | #define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3629 | #define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3630 | |
kadonotakashi | 0:8fdf9a60065b | 3631 | #define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3632 | #define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3633 | |
kadonotakashi | 0:8fdf9a60065b | 3634 | #define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3635 | #define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3636 | |
kadonotakashi | 0:8fdf9a60065b | 3637 | #define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3638 | #define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3639 | |
kadonotakashi | 0:8fdf9a60065b | 3640 | #define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3641 | #define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3642 | |
kadonotakashi | 0:8fdf9a60065b | 3643 | #define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3644 | #define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3645 | |
kadonotakashi | 0:8fdf9a60065b | 3646 | #define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3647 | #define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3648 | |
kadonotakashi | 0:8fdf9a60065b | 3649 | #define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3650 | #define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3651 | |
kadonotakashi | 0:8fdf9a60065b | 3652 | #define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3653 | #define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3654 | |
kadonotakashi | 0:8fdf9a60065b | 3655 | #define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3656 | #define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3657 | |
kadonotakashi | 0:8fdf9a60065b | 3658 | #define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3659 | #define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3660 | |
kadonotakashi | 0:8fdf9a60065b | 3661 | #define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3662 | #define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3663 | |
kadonotakashi | 0:8fdf9a60065b | 3664 | #define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3665 | #define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3666 | |
kadonotakashi | 0:8fdf9a60065b | 3667 | #define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3668 | #define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3669 | |
kadonotakashi | 0:8fdf9a60065b | 3670 | #define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3671 | #define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3672 | |
kadonotakashi | 0:8fdf9a60065b | 3673 | #define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3674 | #define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3675 | |
kadonotakashi | 0:8fdf9a60065b | 3676 | #define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3677 | #define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3678 | |
kadonotakashi | 0:8fdf9a60065b | 3679 | #define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3680 | #define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3681 | |
kadonotakashi | 0:8fdf9a60065b | 3682 | #define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3683 | #define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3684 | |
kadonotakashi | 0:8fdf9a60065b | 3685 | #define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3686 | #define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3687 | |
kadonotakashi | 0:8fdf9a60065b | 3688 | #define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3689 | #define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3690 | |
kadonotakashi | 0:8fdf9a60065b | 3691 | #define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3692 | #define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3693 | |
kadonotakashi | 0:8fdf9a60065b | 3694 | #define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3695 | #define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3696 | |
kadonotakashi | 0:8fdf9a60065b | 3697 | #define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3698 | #define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3699 | |
kadonotakashi | 0:8fdf9a60065b | 3700 | #define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */ |
kadonotakashi | 0:8fdf9a60065b | 3701 | #define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3702 | |
kadonotakashi | 0:8fdf9a60065b | 3703 | #define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3704 | #define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3705 | |
kadonotakashi | 0:8fdf9a60065b | 3706 | #define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3707 | #define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3708 | |
kadonotakashi | 0:8fdf9a60065b | 3709 | #define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3710 | #define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3711 | |
kadonotakashi | 0:8fdf9a60065b | 3712 | #define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3713 | #define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3714 | |
kadonotakashi | 0:8fdf9a60065b | 3715 | #define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3716 | #define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3717 | |
kadonotakashi | 0:8fdf9a60065b | 3718 | #define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */ |
kadonotakashi | 0:8fdf9a60065b | 3719 | #define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */ |
kadonotakashi | 0:8fdf9a60065b | 3720 | |
kadonotakashi | 0:8fdf9a60065b | 3721 | /**@}*/ /* EPWM_CONST */ |
kadonotakashi | 0:8fdf9a60065b | 3722 | /**@}*/ /* end of EPWM register group */ |
kadonotakashi | 0:8fdf9a60065b | 3723 | |
kadonotakashi | 0:8fdf9a60065b | 3724 | |
kadonotakashi | 0:8fdf9a60065b | 3725 | |
kadonotakashi | 0:8fdf9a60065b | 3726 | #endif /* __EPWM_REG_H__ */ |