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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/M2351.h@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
kadonotakashi | 0:8fdf9a60065b | 2 | * @file M2351.h |
kadonotakashi | 0:8fdf9a60065b | 3 | * @version V1.0 |
kadonotakashi | 0:8fdf9a60065b | 4 | * @brief Peripheral Access Layer Header File |
kadonotakashi | 0:8fdf9a60065b | 5 | * |
kadonotakashi | 0:8fdf9a60065b | 6 | * @note |
kadonotakashi | 0:8fdf9a60065b | 7 | * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 8 | * |
kadonotakashi | 0:8fdf9a60065b | 9 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 10 | |
kadonotakashi | 0:8fdf9a60065b | 11 | /** |
kadonotakashi | 0:8fdf9a60065b | 12 | \mainpage Introduction |
kadonotakashi | 0:8fdf9a60065b | 13 | * |
kadonotakashi | 0:8fdf9a60065b | 14 | * |
kadonotakashi | 0:8fdf9a60065b | 15 | * This user manual describes the usage of M2351 device driver |
kadonotakashi | 0:8fdf9a60065b | 16 | * |
kadonotakashi | 0:8fdf9a60065b | 17 | * <b>Disclaimer</b> |
kadonotakashi | 0:8fdf9a60065b | 18 | * |
kadonotakashi | 0:8fdf9a60065b | 19 | * The Software is furnished "AS IS", without warranty as to performance or results, and |
kadonotakashi | 0:8fdf9a60065b | 20 | * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all |
kadonotakashi | 0:8fdf9a60065b | 21 | * warranties, express, implied or otherwise, with regard to the Software, its use, or |
kadonotakashi | 0:8fdf9a60065b | 22 | * operation, including without limitation any and all warranties of merchantability, fitness |
kadonotakashi | 0:8fdf9a60065b | 23 | * for a particular purpose, and non-infringement of intellectual property rights. |
kadonotakashi | 0:8fdf9a60065b | 24 | * |
kadonotakashi | 0:8fdf9a60065b | 25 | * <b>Copyright Notice</b> |
kadonotakashi | 0:8fdf9a60065b | 26 | * |
kadonotakashi | 0:8fdf9a60065b | 27 | * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 28 | */ |
kadonotakashi | 0:8fdf9a60065b | 29 | |
kadonotakashi | 0:8fdf9a60065b | 30 | |
kadonotakashi | 0:8fdf9a60065b | 31 | #ifndef __M2351_H__ |
kadonotakashi | 0:8fdf9a60065b | 32 | #define __M2351_H__ |
kadonotakashi | 0:8fdf9a60065b | 33 | |
kadonotakashi | 0:8fdf9a60065b | 34 | |
kadonotakashi | 0:8fdf9a60065b | 35 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 36 | extern "C" { |
kadonotakashi | 0:8fdf9a60065b | 37 | #endif |
kadonotakashi | 0:8fdf9a60065b | 38 | |
kadonotakashi | 0:8fdf9a60065b | 39 | /******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 40 | /* Processor and Core Peripherals */ |
kadonotakashi | 0:8fdf9a60065b | 41 | /******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 42 | /** @addtogroup CMSIS_Device CMSIS Definitions |
kadonotakashi | 0:8fdf9a60065b | 43 | Configuration of the Cortex-M23 Processor and Core Peripherals |
kadonotakashi | 0:8fdf9a60065b | 44 | @{ |
kadonotakashi | 0:8fdf9a60065b | 45 | */ |
kadonotakashi | 0:8fdf9a60065b | 46 | |
kadonotakashi | 0:8fdf9a60065b | 47 | |
kadonotakashi | 0:8fdf9a60065b | 48 | /* |
kadonotakashi | 0:8fdf9a60065b | 49 | * ========================================================================== |
kadonotakashi | 0:8fdf9a60065b | 50 | * ---------- Interrupt Number Definition ----------------------------------- |
kadonotakashi | 0:8fdf9a60065b | 51 | * ========================================================================== |
kadonotakashi | 0:8fdf9a60065b | 52 | */ |
kadonotakashi | 0:8fdf9a60065b | 53 | |
kadonotakashi | 0:8fdf9a60065b | 54 | /** |
kadonotakashi | 0:8fdf9a60065b | 55 | * @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible. |
kadonotakashi | 0:8fdf9a60065b | 56 | */ |
kadonotakashi | 0:8fdf9a60065b | 57 | typedef enum IRQn |
kadonotakashi | 0:8fdf9a60065b | 58 | { |
kadonotakashi | 0:8fdf9a60065b | 59 | /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 60 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 61 | HardFault_IRQn = -13, /*!< 3 Cortex-M23 Hard Fault Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 62 | SVCall_IRQn = -5, /*!< 11 Cortex-M23 SV Call Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 63 | PendSV_IRQn = -2, /*!< 14 Cortex-M23 Pend SV Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 64 | SysTick_IRQn = -1, /*!< 15 Cortex-M23 System Tick Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 65 | |
kadonotakashi | 0:8fdf9a60065b | 66 | /****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 67 | |
kadonotakashi | 0:8fdf9a60065b | 68 | BOD_IRQn = 0, /*!< Brown Out detection Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 69 | IRC_IRQn = 1, /*!< Internal RC Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 70 | PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 71 | RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 72 | CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 73 | ISP_IRQn = 5, /*!< FMC ISP Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 74 | RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 75 | TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 76 | WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 77 | WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 78 | EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 79 | EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 80 | EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 81 | EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 82 | EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 83 | EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 84 | GPA_IRQn = 16, /*!< GPIO Port A Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 85 | GPB_IRQn = 17, /*!< GPIO Port B Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 86 | GPC_IRQn = 18, /*!< GPIO Port C Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 87 | GPD_IRQn = 19, /*!< GPIO Port D Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 88 | GPE_IRQn = 20, /*!< GPIO Port E Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 89 | GPF_IRQn = 21, /*!< GPIO Port F Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 90 | QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 91 | SPI0_IRQn = 23, /*!< SPI0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 92 | BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 93 | EPWM0_P0_IRQn = 25, /*!< EPWM0P0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 94 | EPWM0_P1_IRQn = 26, /*!< EPWM0P1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 95 | EPWM0_P2_IRQn = 27, /*!< EPWM0P2 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 96 | BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 97 | EPWM1_P0_IRQn = 29, /*!< EPWM1P0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 98 | EPWM1_P1_IRQn = 30, /*!< EPWM1P1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 99 | EPWM1_P2_IRQn = 31, /*!< EPWM1P2 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 100 | TMR0_IRQn = 32, /*!< Timer 0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 101 | TMR1_IRQn = 33, /*!< Timer 1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 102 | TMR2_IRQn = 34, /*!< Timer 2 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 103 | TMR3_IRQn = 35, /*!< Timer 3 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 104 | UART0_IRQn = 36, /*!< UART 0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 105 | UART1_IRQn = 37, /*!< UART 1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 106 | I2C0_IRQn = 38, /*!< I2C 0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 107 | I2C1_IRQn = 39, /*!< I2C 1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 108 | PDMA0_IRQn = 40, /*!< Peripheral DMA 0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 109 | DAC_IRQn = 41, /*!< DAC Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 110 | EADC0_IRQn = 42, /*!< EADC Source 0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 111 | EADC1_IRQn = 43, /*!< EADC Source 1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 112 | ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 113 | EADC2_IRQn = 46, /*!< EADC Source 2 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 114 | EADC3_IRQn = 47, /*!< EADC Source 3 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 115 | UART2_IRQn = 48, /*!< UART2 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 116 | UART3_IRQn = 49, /*!< UART3 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 117 | SPI1_IRQn = 51, /*!< SPI1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 118 | SPI2_IRQn = 52, /*!< SPI2 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 119 | USBD_IRQn = 53, /*!< USB device Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 120 | USBH_IRQn = 54, /*!< USB host Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 121 | USBOTG_IRQn = 55, /*!< USB OTG Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 122 | CAN0_IRQn = 56, /*!< CAN0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 123 | SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 124 | SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 125 | SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 126 | SPI3_IRQn = 62, /*!< SPI3 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 127 | SDH0_IRQn = 64, /*!< SDH0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 128 | I2S0_IRQn = 68, /*!< I2S0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 129 | CRPT_IRQn = 71, /*!< CRPT Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 130 | GPG_IRQn = 72, /*!< GPIO Port G Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 131 | EINT6_IRQn = 73, /*!< External Input 6 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 132 | UART4_IRQn = 74, /*!< UART4 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 133 | UART5_IRQn = 75, /*!< UART5 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 134 | USCI0_IRQn = 76, /*!< USCI0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 135 | USCI1_IRQn = 77, /*!< USCI1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 136 | BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 137 | BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 138 | I2C2_IRQn = 82, /*!< I2C2 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 139 | QEI0_IRQn = 84, /*!< QEI0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 140 | QEI1_IRQn = 85, /*!< QEI1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 141 | ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 142 | ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 143 | GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 144 | EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 145 | SPI5_IRQn = 96, /*!< SPI5 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 146 | DSRC_IRQn = 97, /*!< DSRC Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 147 | PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 148 | SCU_IRQn = 99, /*!< SCU Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 149 | TRNG_IRQn = 101 /*!< TRNG interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 150 | |
kadonotakashi | 0:8fdf9a60065b | 151 | |
kadonotakashi | 0:8fdf9a60065b | 152 | } IRQn_Type; |
kadonotakashi | 0:8fdf9a60065b | 153 | |
kadonotakashi | 0:8fdf9a60065b | 154 | |
kadonotakashi | 0:8fdf9a60065b | 155 | /* ================================================================================ */ |
kadonotakashi | 0:8fdf9a60065b | 156 | /* ================ Processor and Core Peripheral Section ================ */ |
kadonotakashi | 0:8fdf9a60065b | 157 | /* ================================================================================ */ |
kadonotakashi | 0:8fdf9a60065b | 158 | |
kadonotakashi | 0:8fdf9a60065b | 159 | /* ------- Start of section using anonymous unions and disabling warnings ------- */ |
kadonotakashi | 0:8fdf9a60065b | 160 | #if defined (__CC_ARM) |
kadonotakashi | 0:8fdf9a60065b | 161 | #pragma push |
kadonotakashi | 0:8fdf9a60065b | 162 | #pragma anon_unions |
kadonotakashi | 0:8fdf9a60065b | 163 | #elif defined (__ICCARM__) |
kadonotakashi | 0:8fdf9a60065b | 164 | #pragma language=extended |
kadonotakashi | 0:8fdf9a60065b | 165 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
kadonotakashi | 0:8fdf9a60065b | 166 | #pragma clang diagnostic push |
kadonotakashi | 0:8fdf9a60065b | 167 | #pragma clang diagnostic ignored "-Wc11-extensions" |
kadonotakashi | 0:8fdf9a60065b | 168 | #pragma clang diagnostic ignored "-Wreserved-id-macro" |
kadonotakashi | 0:8fdf9a60065b | 169 | #elif defined (__GNUC__) |
kadonotakashi | 0:8fdf9a60065b | 170 | /* anonymous unions are enabled by default */ |
kadonotakashi | 0:8fdf9a60065b | 171 | #elif defined (__TMS470__) |
kadonotakashi | 0:8fdf9a60065b | 172 | /* anonymous unions are enabled by default */ |
kadonotakashi | 0:8fdf9a60065b | 173 | #elif defined (__TASKING__) |
kadonotakashi | 0:8fdf9a60065b | 174 | #pragma warning 586 |
kadonotakashi | 0:8fdf9a60065b | 175 | #elif defined (__CSMC__) |
kadonotakashi | 0:8fdf9a60065b | 176 | /* anonymous unions are enabled by default */ |
kadonotakashi | 0:8fdf9a60065b | 177 | #else |
kadonotakashi | 0:8fdf9a60065b | 178 | #warning Not supported compiler type |
kadonotakashi | 0:8fdf9a60065b | 179 | #endif |
kadonotakashi | 0:8fdf9a60065b | 180 | |
kadonotakashi | 0:8fdf9a60065b | 181 | |
kadonotakashi | 0:8fdf9a60065b | 182 | /* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */ |
kadonotakashi | 0:8fdf9a60065b | 183 | #define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */ |
kadonotakashi | 0:8fdf9a60065b | 184 | #define __SAU_PRESENT 1U /* SAU present */ |
kadonotakashi | 0:8fdf9a60065b | 185 | #define __SAUREGION_PRESENT 1U /* SAU present */ |
kadonotakashi | 0:8fdf9a60065b | 186 | #define __MPU_PRESENT 1U /* MPU present */ |
kadonotakashi | 0:8fdf9a60065b | 187 | #define __VTOR_PRESENT 1U /* VTOR present */ |
kadonotakashi | 0:8fdf9a60065b | 188 | #define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ |
kadonotakashi | 0:8fdf9a60065b | 189 | #define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ |
kadonotakashi | 0:8fdf9a60065b | 190 | #define USE_ASSERT 0U /* Define to use Assert function or not */ |
kadonotakashi | 0:8fdf9a60065b | 191 | |
kadonotakashi | 0:8fdf9a60065b | 192 | /*@}*/ /* end of group CMSIS */ |
kadonotakashi | 0:8fdf9a60065b | 193 | |
kadonotakashi | 0:8fdf9a60065b | 194 | |
kadonotakashi | 0:8fdf9a60065b | 195 | #include "core_armv8mbl.h" /* Processor and core peripherals */ |
kadonotakashi | 0:8fdf9a60065b | 196 | #include "system_M2351.h" /* System Header */ |
kadonotakashi | 0:8fdf9a60065b | 197 | |
kadonotakashi | 0:8fdf9a60065b | 198 | /** |
kadonotakashi | 0:8fdf9a60065b | 199 | * Initialize the system clock |
kadonotakashi | 0:8fdf9a60065b | 200 | * |
kadonotakashi | 0:8fdf9a60065b | 201 | * @param none |
kadonotakashi | 0:8fdf9a60065b | 202 | * @return none |
kadonotakashi | 0:8fdf9a60065b | 203 | * |
kadonotakashi | 0:8fdf9a60065b | 204 | * @brief Setup the micro controller system |
kadonotakashi | 0:8fdf9a60065b | 205 | * Initialize the PLL and update the SystemFrequency variable |
kadonotakashi | 0:8fdf9a60065b | 206 | */ |
kadonotakashi | 0:8fdf9a60065b | 207 | extern void SystemInit(void); |
kadonotakashi | 0:8fdf9a60065b | 208 | |
kadonotakashi | 0:8fdf9a60065b | 209 | |
kadonotakashi | 0:8fdf9a60065b | 210 | /******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 211 | /* Device Specific Peripheral registers structures */ |
kadonotakashi | 0:8fdf9a60065b | 212 | /******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 213 | |
kadonotakashi | 0:8fdf9a60065b | 214 | /** @addtogroup REGISTER Control Register |
kadonotakashi | 0:8fdf9a60065b | 215 | |
kadonotakashi | 0:8fdf9a60065b | 216 | @{ |
kadonotakashi | 0:8fdf9a60065b | 217 | |
kadonotakashi | 0:8fdf9a60065b | 218 | */ |
kadonotakashi | 0:8fdf9a60065b | 219 | |
kadonotakashi | 0:8fdf9a60065b | 220 | #include "acmp_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 221 | #include "bpwm_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 222 | #include "can_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 223 | #include "clk_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 224 | #include "crc_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 225 | #include "dac_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 226 | #include "eadc_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 227 | #include "ebi_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 228 | #include "ecap_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 229 | #include "fmc_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 230 | #include "gpio_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 231 | #include "hdiv_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 232 | #include "i2c_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 233 | #include "i2s_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 234 | #include "pdma_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 235 | #include "epwm_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 236 | #include "qei_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 237 | #include "rtc_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 238 | #include "sc_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 239 | #include "scu_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 240 | #include "sdh_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 241 | #include "qspi_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 242 | #include "spi_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 243 | #include "spi5_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 244 | #include "sys_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 245 | #include "timer_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 246 | #include "trng_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 247 | #include "uart_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 248 | #include "ui2c_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 249 | #include "usbh_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 250 | #include "usbd_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 251 | #include "otg_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 252 | #include "crpt_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 253 | #include "uspi_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 254 | #include "uuart_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 255 | #include "wdt_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 256 | #include "wwdt_reg.h" |
kadonotakashi | 0:8fdf9a60065b | 257 | |
kadonotakashi | 0:8fdf9a60065b | 258 | /**@}*/ /* end of REGISTER group */ |
kadonotakashi | 0:8fdf9a60065b | 259 | |
kadonotakashi | 0:8fdf9a60065b | 260 | |
kadonotakashi | 0:8fdf9a60065b | 261 | /******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 262 | /* Peripheral memory map */ |
kadonotakashi | 0:8fdf9a60065b | 263 | /******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 264 | /** @addtogroup PERIPHERAL_BASE Peripheral Memory Base |
kadonotakashi | 0:8fdf9a60065b | 265 | Memory Mapped Structure for Series Peripheral |
kadonotakashi | 0:8fdf9a60065b | 266 | @{ |
kadonotakashi | 0:8fdf9a60065b | 267 | */ |
kadonotakashi | 0:8fdf9a60065b | 268 | |
kadonotakashi | 0:8fdf9a60065b | 269 | |
kadonotakashi | 0:8fdf9a60065b | 270 | /* Peripheral and SRAM base address */ |
kadonotakashi | 0:8fdf9a60065b | 271 | #define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ |
kadonotakashi | 0:8fdf9a60065b | 272 | #define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ |
kadonotakashi | 0:8fdf9a60065b | 273 | #define NS_OFFSET (0x10000000UL) |
kadonotakashi | 0:8fdf9a60065b | 274 | |
kadonotakashi | 0:8fdf9a60065b | 275 | /* Peripheral memory map */ |
kadonotakashi | 0:8fdf9a60065b | 276 | #define AHBPERIPH_BASE PERIPH_BASE |
kadonotakashi | 0:8fdf9a60065b | 277 | #define APBPERIPH_BASE (PERIPH_BASE + 0x00040000UL) |
kadonotakashi | 0:8fdf9a60065b | 278 | |
kadonotakashi | 0:8fdf9a60065b | 279 | /*!< AHB peripherals */ |
kadonotakashi | 0:8fdf9a60065b | 280 | #define SYS_BASE (AHBPERIPH_BASE + 0x00000UL) |
kadonotakashi | 0:8fdf9a60065b | 281 | #define CLK_BASE (AHBPERIPH_BASE + 0x00200UL) |
kadonotakashi | 0:8fdf9a60065b | 282 | #define INT_BASE (AHBPERIPH_BASE + 0x00300UL) |
kadonotakashi | 0:8fdf9a60065b | 283 | #define GPIO_BASE (AHBPERIPH_BASE + 0x04000UL) |
kadonotakashi | 0:8fdf9a60065b | 284 | #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL) |
kadonotakashi | 0:8fdf9a60065b | 285 | #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL) |
kadonotakashi | 0:8fdf9a60065b | 286 | #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL) |
kadonotakashi | 0:8fdf9a60065b | 287 | #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL) |
kadonotakashi | 0:8fdf9a60065b | 288 | #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL) |
kadonotakashi | 0:8fdf9a60065b | 289 | #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL) |
kadonotakashi | 0:8fdf9a60065b | 290 | #define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL) |
kadonotakashi | 0:8fdf9a60065b | 291 | #define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL) |
kadonotakashi | 0:8fdf9a60065b | 292 | #define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL) |
kadonotakashi | 0:8fdf9a60065b | 293 | #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) |
kadonotakashi | 0:8fdf9a60065b | 294 | #define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL) |
kadonotakashi | 0:8fdf9a60065b | 295 | #define PDMA0_BASE (AHBPERIPH_BASE + 0x08000UL) |
kadonotakashi | 0:8fdf9a60065b | 296 | #define PDMA1_BASE (AHBPERIPH_BASE + 0x18000UL) |
kadonotakashi | 0:8fdf9a60065b | 297 | #define USBH_BASE (AHBPERIPH_BASE + 0x09000UL) |
kadonotakashi | 0:8fdf9a60065b | 298 | #define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL) |
kadonotakashi | 0:8fdf9a60065b | 299 | #define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL) |
kadonotakashi | 0:8fdf9a60065b | 300 | #define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL) |
kadonotakashi | 0:8fdf9a60065b | 301 | #define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) |
kadonotakashi | 0:8fdf9a60065b | 302 | #define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) |
kadonotakashi | 0:8fdf9a60065b | 303 | #define CRPT_BASE (AHBPERIPH_BASE + 0x32000UL) |
kadonotakashi | 0:8fdf9a60065b | 304 | #define SCU_BASE (AHBPERIPH_BASE + 0x2F000UL) |
kadonotakashi | 0:8fdf9a60065b | 305 | |
kadonotakashi | 0:8fdf9a60065b | 306 | /*!< APB peripherals */ |
kadonotakashi | 0:8fdf9a60065b | 307 | #define WDT_BASE (APBPERIPH_BASE + 0x00000UL) |
kadonotakashi | 0:8fdf9a60065b | 308 | #define WWDT_BASE (APBPERIPH_BASE + 0x00100UL) |
kadonotakashi | 0:8fdf9a60065b | 309 | #define RTC_BASE (APBPERIPH_BASE + 0x01000UL) |
kadonotakashi | 0:8fdf9a60065b | 310 | #define EADC_BASE (APBPERIPH_BASE + 0x03000UL) |
kadonotakashi | 0:8fdf9a60065b | 311 | #define EADC0_BASE (APBPERIPH_BASE + 0x03000UL) |
kadonotakashi | 0:8fdf9a60065b | 312 | #define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) |
kadonotakashi | 0:8fdf9a60065b | 313 | #define DAC0_BASE (APBPERIPH_BASE + 0x07000UL) |
kadonotakashi | 0:8fdf9a60065b | 314 | #define DAC1_BASE (APBPERIPH_BASE + 0x07040UL) |
kadonotakashi | 0:8fdf9a60065b | 315 | #define I2S0_BASE (APBPERIPH_BASE + 0x08000UL) |
kadonotakashi | 0:8fdf9a60065b | 316 | #define OTG_BASE (APBPERIPH_BASE + 0x0D000UL) |
kadonotakashi | 0:8fdf9a60065b | 317 | #define TMR01_BASE (APBPERIPH_BASE + 0x10000UL) |
kadonotakashi | 0:8fdf9a60065b | 318 | #define TMR23_BASE (APBPERIPH_BASE + 0x11000UL) |
kadonotakashi | 0:8fdf9a60065b | 319 | #define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL) |
kadonotakashi | 0:8fdf9a60065b | 320 | #define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL) |
kadonotakashi | 0:8fdf9a60065b | 321 | #define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL) |
kadonotakashi | 0:8fdf9a60065b | 322 | #define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL) |
kadonotakashi | 0:8fdf9a60065b | 323 | #define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL) |
kadonotakashi | 0:8fdf9a60065b | 324 | #define SPI0_BASE (APBPERIPH_BASE + 0x21000UL) |
kadonotakashi | 0:8fdf9a60065b | 325 | #define SPI1_BASE (APBPERIPH_BASE + 0x22000UL) |
kadonotakashi | 0:8fdf9a60065b | 326 | #define SPI2_BASE (APBPERIPH_BASE + 0x23000UL) |
kadonotakashi | 0:8fdf9a60065b | 327 | #define SPI3_BASE (APBPERIPH_BASE + 0x24000UL) |
kadonotakashi | 0:8fdf9a60065b | 328 | #define SPI5_BASE (APBPERIPH_BASE + 0x25000UL) |
kadonotakashi | 0:8fdf9a60065b | 329 | #define UART0_BASE (APBPERIPH_BASE + 0x30000UL) |
kadonotakashi | 0:8fdf9a60065b | 330 | #define UART0_BASE (APBPERIPH_BASE + 0x30000UL) |
kadonotakashi | 0:8fdf9a60065b | 331 | #define UART1_BASE (APBPERIPH_BASE + 0x31000UL) |
kadonotakashi | 0:8fdf9a60065b | 332 | #define UART2_BASE (APBPERIPH_BASE + 0x32000UL) |
kadonotakashi | 0:8fdf9a60065b | 333 | #define UART3_BASE (APBPERIPH_BASE + 0x33000UL) |
kadonotakashi | 0:8fdf9a60065b | 334 | #define UART4_BASE (APBPERIPH_BASE + 0x34000UL) |
kadonotakashi | 0:8fdf9a60065b | 335 | #define UART5_BASE (APBPERIPH_BASE + 0x35000UL) |
kadonotakashi | 0:8fdf9a60065b | 336 | #define I2C0_BASE (APBPERIPH_BASE + 0x40000UL) |
kadonotakashi | 0:8fdf9a60065b | 337 | #define I2C1_BASE (APBPERIPH_BASE + 0x41000UL) |
kadonotakashi | 0:8fdf9a60065b | 338 | #define I2C2_BASE (APBPERIPH_BASE + 0x42000UL) |
kadonotakashi | 0:8fdf9a60065b | 339 | #define SC0_BASE (APBPERIPH_BASE + 0x50000UL) |
kadonotakashi | 0:8fdf9a60065b | 340 | #define SC1_BASE (APBPERIPH_BASE + 0x51000UL) |
kadonotakashi | 0:8fdf9a60065b | 341 | #define SC2_BASE (APBPERIPH_BASE + 0x52000UL) |
kadonotakashi | 0:8fdf9a60065b | 342 | #define CAN0_BASE (APBPERIPH_BASE + 0x60000UL) |
kadonotakashi | 0:8fdf9a60065b | 343 | #define QEI0_BASE (APBPERIPH_BASE + 0x70000UL) |
kadonotakashi | 0:8fdf9a60065b | 344 | #define QEI1_BASE (APBPERIPH_BASE + 0x71000UL) |
kadonotakashi | 0:8fdf9a60065b | 345 | #define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL) |
kadonotakashi | 0:8fdf9a60065b | 346 | #define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL) |
kadonotakashi | 0:8fdf9a60065b | 347 | #define DSRC_BASE (APBPERIPH_BASE + 0x77000UL) |
kadonotakashi | 0:8fdf9a60065b | 348 | #define TRNG_BASE (APBPERIPH_BASE + 0x79000UL) |
kadonotakashi | 0:8fdf9a60065b | 349 | #define USBD_BASE (APBPERIPH_BASE + 0x80000UL) |
kadonotakashi | 0:8fdf9a60065b | 350 | #define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) |
kadonotakashi | 0:8fdf9a60065b | 351 | #define USCI1_BASE (APBPERIPH_BASE + 0x91000UL) |
kadonotakashi | 0:8fdf9a60065b | 352 | |
kadonotakashi | 0:8fdf9a60065b | 353 | |
kadonotakashi | 0:8fdf9a60065b | 354 | /**@}*/ /* PERIPHERAL */ |
kadonotakashi | 0:8fdf9a60065b | 355 | |
kadonotakashi | 0:8fdf9a60065b | 356 | /******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 357 | /* Peripheral declaration */ |
kadonotakashi | 0:8fdf9a60065b | 358 | /******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 359 | |
kadonotakashi | 0:8fdf9a60065b | 360 | /** @addtogroup PMODULE Peripheral Pointer |
kadonotakashi | 0:8fdf9a60065b | 361 | The Declaration of Peripheral Pointer |
kadonotakashi | 0:8fdf9a60065b | 362 | @{ |
kadonotakashi | 0:8fdf9a60065b | 363 | */ |
kadonotakashi | 0:8fdf9a60065b | 364 | |
kadonotakashi | 0:8fdf9a60065b | 365 | /** @addtogroup PMODULE_S Secure Peripheral Pointer |
kadonotakashi | 0:8fdf9a60065b | 366 | The Declaration of Secure Peripheral Pointer |
kadonotakashi | 0:8fdf9a60065b | 367 | @{ |
kadonotakashi | 0:8fdf9a60065b | 368 | */ |
kadonotakashi | 0:8fdf9a60065b | 369 | |
kadonotakashi | 0:8fdf9a60065b | 370 | |
kadonotakashi | 0:8fdf9a60065b | 371 | #define PA ((GPIO_T *) GPIOA_BASE) /*!< GPIO PORTA Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 372 | #define PB ((GPIO_T *) GPIOB_BASE) /*!< GPIO PORTB Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 373 | #define PC ((GPIO_T *) GPIOC_BASE) /*!< GPIO PORTC Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 374 | #define PD ((GPIO_T *) GPIOD_BASE) /*!< GPIO PORTD Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 375 | #define PE ((GPIO_T *) GPIOE_BASE) /*!< GPIO PORTE Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 376 | #define PF ((GPIO_T *) GPIOF_BASE) /*!< GPIO PORTF Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 377 | #define PG ((GPIO_T *) GPIOG_BASE) /*!< GPIO PORTG Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 378 | #define PH ((GPIO_T *) GPIOH_BASE) /*!< GPIO PORTH Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 379 | |
kadonotakashi | 0:8fdf9a60065b | 380 | #define UART0 ((UART_T *) UART0_BASE) /*!< UART0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 381 | #define UART1 ((UART_T *) UART1_BASE) /*!< UART1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 382 | #define UART2 ((UART_T *) UART2_BASE) /*!< UART2 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 383 | #define UART3 ((UART_T *) UART3_BASE) /*!< UART3 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 384 | #define UART4 ((UART_T *) UART4_BASE) /*!< UART4 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 385 | #define UART5 ((UART_T *) UART5_BASE) /*!< UART5 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 386 | |
kadonotakashi | 0:8fdf9a60065b | 387 | |
kadonotakashi | 0:8fdf9a60065b | 388 | #define TIMER0 ((TIMER_T *) TMR01_BASE) /*!< TIMER0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 389 | #define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x100UL)) /*!< TIMER1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 390 | #define TIMER2 ((TIMER_T *) TMR23_BASE) /*!< TIMER2 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 391 | #define TIMER3 ((TIMER_T *) (TMR23_BASE + 0x100UL)) /*!< TIMER3 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 392 | |
kadonotakashi | 0:8fdf9a60065b | 393 | #define WDT ((WDT_T *) WDT_BASE) /*!< Watch Dog Timer Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 394 | |
kadonotakashi | 0:8fdf9a60065b | 395 | #define WWDT ((WWDT_T *) WWDT_BASE) /*!< Window Watch Dog Timer Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 396 | |
kadonotakashi | 0:8fdf9a60065b | 397 | #define QSPI0 ((QSPI_T *) QSPI0_BASE) /*!< QSPI0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 398 | #define SPI0 ((SPI_T *) SPI0_BASE) /*!< SPI0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 399 | #define SPI1 ((SPI_T *) SPI1_BASE) /*!< SPI1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 400 | #define SPI2 ((SPI_T *) SPI2_BASE) /*!< SPI2 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 401 | #define SPI3 ((SPI_T *) SPI3_BASE) /*!< SPI3 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 402 | #define SPI5 ((SPI5_T *) SPI5_BASE) /*!< SPI5 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 403 | |
kadonotakashi | 0:8fdf9a60065b | 404 | #define I2S0 ((I2S_T *) I2S0_BASE) /*!< I2S0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 405 | |
kadonotakashi | 0:8fdf9a60065b | 406 | #define I2C0 ((I2C_T *) I2C0_BASE) /*!< I2C0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 407 | #define I2C1 ((I2C_T *) I2C1_BASE) /*!< I2C1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 408 | #define I2C2 ((I2C_T *) I2C2_BASE) /*!< I2C1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 409 | |
kadonotakashi | 0:8fdf9a60065b | 410 | #define QEI0 ((QEI_T *) QEI0_BASE) /*!< QEI0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 411 | #define QEI1 ((QEI_T *) QEI1_BASE) /*!< QEI1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 412 | |
kadonotakashi | 0:8fdf9a60065b | 413 | #define RTC ((RTC_T *) RTC_BASE) /*!< RTC Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 414 | |
kadonotakashi | 0:8fdf9a60065b | 415 | #define ACMP01 ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 416 | |
kadonotakashi | 0:8fdf9a60065b | 417 | #define CLK ((CLK_T *) CLK_BASE) /*!< System Clock Controller Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 418 | |
kadonotakashi | 0:8fdf9a60065b | 419 | #define DAC0 ((DAC_T *) DAC0_BASE) /*!< DAC0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 420 | #define DAC1 ((DAC_T *) DAC1_BASE) /*!< DAC1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 421 | |
kadonotakashi | 0:8fdf9a60065b | 422 | #define EADC ((EADC_T *) EADC_BASE) /*!< EADC Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 423 | |
kadonotakashi | 0:8fdf9a60065b | 424 | #define SYS ((SYS_T *) SYS_BASE) /*!< System Global Controller Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 425 | |
kadonotakashi | 0:8fdf9a60065b | 426 | #define SYSINT ((SYS_INT_T *) INT_BASE) /*!< Interrupt Source Controller Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 427 | |
kadonotakashi | 0:8fdf9a60065b | 428 | #define FMC ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */ |
kadonotakashi | 0:8fdf9a60065b | 429 | |
kadonotakashi | 0:8fdf9a60065b | 430 | #define SDH0 ((SDH_T *) SDH0_BASE) |
kadonotakashi | 0:8fdf9a60065b | 431 | |
kadonotakashi | 0:8fdf9a60065b | 432 | #define CRPT ((CRPT_T *) CRPT_BASE) /*!< Crypto Accelerator Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 433 | #define TRNG ((TRNG_T *)TRNG_BASE) /*!< True Random Number Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 434 | |
kadonotakashi | 0:8fdf9a60065b | 435 | #define BPWM0 ((BPWM_T *) BPWM0_BASE) /*!< BPWM0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 436 | #define BPWM1 ((BPWM_T *) BPWM1_BASE) /*!< BPWM1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 437 | |
kadonotakashi | 0:8fdf9a60065b | 438 | #define EPWM0 ((EPWM_T *) EPWM0_BASE) /*!< EPWM0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 439 | #define EPWM1 ((EPWM_T *) EPWM1_BASE) /*!< EPWM1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 440 | |
kadonotakashi | 0:8fdf9a60065b | 441 | #define SC0 ((SC_T *) SC0_BASE) /*!< SC0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 442 | #define SC1 ((SC_T *) SC1_BASE) /*!< SC1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 443 | #define SC2 ((SC_T *) SC2_BASE) /*!< SC2 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 444 | |
kadonotakashi | 0:8fdf9a60065b | 445 | #define EBI ((EBI_T *) EBI_BASE) /*!< EBI Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 446 | |
kadonotakashi | 0:8fdf9a60065b | 447 | #define CRC ((CRC_T *) CRC_BASE) /*!< CRC Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 448 | |
kadonotakashi | 0:8fdf9a60065b | 449 | #define USBD ((USBD_T *) USBD_BASE) /*!< USB Device Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 450 | #define USBH ((USBH_T *) USBH_BASE) /*!< USBH Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 451 | #define OTG ((OTG_T *) OTG_BASE) /*!< OTG Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 452 | |
kadonotakashi | 0:8fdf9a60065b | 453 | #define PDMA0 ((PDMA_T *) PDMA0_BASE) /*!< PDMA0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 454 | #define PDMA1 ((PDMA_T *) PDMA1_BASE) /*!< PDMA1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 455 | |
kadonotakashi | 0:8fdf9a60065b | 456 | #define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 457 | #define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 458 | #define UI2C2 ((UI2C_T *) USCI2_BASE) /*!< UI2C2 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 459 | |
kadonotakashi | 0:8fdf9a60065b | 460 | #define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 461 | #define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 462 | |
kadonotakashi | 0:8fdf9a60065b | 463 | #define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 464 | #define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 465 | |
kadonotakashi | 0:8fdf9a60065b | 466 | #define SCU ((SCU_T *) SCU_BASE) /*!< SCU Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 467 | #define ECAP0 ((ECAP_T *) ECAP0_BASE) /*!< ECAP0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 468 | #define ECAP1 ((ECAP_T *) ECAP1_BASE) /*!< ECAP1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 469 | |
kadonotakashi | 0:8fdf9a60065b | 470 | #define CAN0 ((CAN_T *)CAN0_BASE) /*!< CAN0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 471 | |
kadonotakashi | 0:8fdf9a60065b | 472 | |
kadonotakashi | 0:8fdf9a60065b | 473 | |
kadonotakashi | 0:8fdf9a60065b | 474 | |
kadonotakashi | 0:8fdf9a60065b | 475 | /**@}*/ /* end of group PMODULE_S */ |
kadonotakashi | 0:8fdf9a60065b | 476 | |
kadonotakashi | 0:8fdf9a60065b | 477 | /** @addtogroup PMODULE_NS Non-secure Peripheral Pointer |
kadonotakashi | 0:8fdf9a60065b | 478 | The Declaration of Non-secure Peripheral Pointer |
kadonotakashi | 0:8fdf9a60065b | 479 | @{ |
kadonotakashi | 0:8fdf9a60065b | 480 | */ |
kadonotakashi | 0:8fdf9a60065b | 481 | |
kadonotakashi | 0:8fdf9a60065b | 482 | |
kadonotakashi | 0:8fdf9a60065b | 483 | #define PA_NS ((GPIO_T *) (GPIOA_BASE+NS_OFFSET)) /*!< GPIO PORTA Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 484 | #define PB_NS ((GPIO_T *) (GPIOB_BASE+NS_OFFSET)) /*!< GPIO PORTB Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 485 | #define PC_NS ((GPIO_T *) (GPIOC_BASE+NS_OFFSET)) /*!< GPIO PORTC Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 486 | #define PD_NS ((GPIO_T *) (GPIOD_BASE+NS_OFFSET)) /*!< GPIO PORTD Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 487 | #define PE_NS ((GPIO_T *) (GPIOE_BASE+NS_OFFSET)) /*!< GPIO PORTE Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 488 | #define PF_NS ((GPIO_T *) (GPIOF_BASE+NS_OFFSET)) /*!< GPIO PORTF Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 489 | #define PG_NS ((GPIO_T *) (GPIOG_BASE+NS_OFFSET)) /*!< GPIO PORTG Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 490 | #define PH_NS ((GPIO_T *) (GPIOH_BASE+NS_OFFSET)) /*!< GPIO PORTH Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 491 | #define UART0_NS ((UART_T *) (UART0_BASE+NS_OFFSET)) /*!< UART0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 492 | #define UART1_NS ((UART_T *) (UART1_BASE+NS_OFFSET)) /*!< UART1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 493 | #define UART2_NS ((UART_T *) (UART2_BASE+NS_OFFSET)) /*!< UART2 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 494 | #define UART3_NS ((UART_T *) (UART3_BASE+NS_OFFSET)) /*!< UART3 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 495 | #define UART4_NS ((UART_T *) (UART4_BASE+NS_OFFSET)) /*!< UART4 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 496 | #define UART5_NS ((UART_T *) (UART5_BASE+NS_OFFSET)) /*!< UART5 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 497 | #define TIMER2_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET)) /*!< TIMER2 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 498 | #define TIMER3_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET+0x100UL)) /*!< TIMER3 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 499 | #define QSPI0_NS ((QSPI_T *) (QSPI0_BASE+NS_OFFSET)) /*!< QSPI0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 500 | #define SPI0_NS ((SPI_T *) (SPI0_BASE+NS_OFFSET)) /*!< SPI0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 501 | #define SPI1_NS ((SPI_T *) (SPI1_BASE+NS_OFFSET)) /*!< SPI1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 502 | #define SPI2_NS ((SPI_T *) (SPI2_BASE+NS_OFFSET)) /*!< SPI2 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 503 | #define SPI3_NS ((SPI_T *) (SPI3_BASE+NS_OFFSET)) /*!< SPI3 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 504 | #define SPI5_NS ((SPI5_T *) (SPI5_BASE+NS_OFFSET)) /*!< SPI5 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 505 | #define I2S0_NS ((I2S_T *) (I2S0_BASE+NS_OFFSET)) /*!< I2S0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 506 | #define I2C0_NS ((I2C_T *) (I2C0_BASE+NS_OFFSET)) /*!< I2C0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 507 | #define I2C1_NS ((I2C_T *) (I2C1_BASE+NS_OFFSET)) /*!< I2C1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 508 | #define I2C2_NS ((I2C_T *) (I2C2_BASE+NS_OFFSET)) /*!< I2C1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 509 | #define QEI0_NS ((QEI_T *) (QEI0_BASE+NS_OFFSET)) /*!< QEI0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 510 | #define QEI1_NS ((QEI_T *) (QEI1_BASE+NS_OFFSET)) /*!< QEI1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 511 | #define RTC_NS ((RTC_T *) (RTC_BASE +NS_OFFSET)) /*!< RTC Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 512 | #define ACMP01_NS ((ACMP_T *) (ACMP01_BASE+NS_OFFSET)) /*!< ACMP01 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 513 | #define DAC0_NS ((DAC_T *) (DAC0_BASE+NS_OFFSET)) /*!< DAC0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 514 | #define DAC1_NS ((DAC_T *) (DAC1_BASE+NS_OFFSET)) /*!< DAC1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 515 | #define EADC_NS ((EADC_T *) (EADC_BASE+NS_OFFSET)) /*!< EADC Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 516 | #define SDH0_NS ((SDH_T *) (SDH0_BASE +NS_OFFSET)) |
kadonotakashi | 0:8fdf9a60065b | 517 | #define CRPT_NS ((CRPT_T *) (CRPT_BASE +NS_OFFSET)) |
kadonotakashi | 0:8fdf9a60065b | 518 | #define TRNG_NS ((TRNG_T *) (TRNG_BASE +NS_OFFSET)) /*!< Random Number Generator Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 519 | #define BPWM0_NS ((BPWM_T *) (BPWM0_BASE+NS_OFFSET)) /*!< BPWM0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 520 | #define BPWM1_NS ((BPWM_T *) (BPWM1_BASE+NS_OFFSET)) /*!< BPWM1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 521 | #define EPWM0_NS ((EPWM_T *) (EPWM0_BASE+NS_OFFSET)) /*!< EPWM0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 522 | #define EPWM1_NS ((EPWM_T *) (EPWM1_BASE+NS_OFFSET)) /*!< EPWM1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 523 | #define SC0_NS ((SC_T *) (SC0_BASE +NS_OFFSET)) /*!< SC0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 524 | #define SC1_NS ((SC_T *) (SC1_BASE +NS_OFFSET)) /*!< SC1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 525 | #define SC2_NS ((SC_T *) (SC2_BASE +NS_OFFSET)) /*!< SC2 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 526 | #define EBI_NS ((EBI_T *) (EBI_BASE +NS_OFFSET)) /*!< EBI Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 527 | #define CRC_NS ((CRC_T *) (CRC_BASE +NS_OFFSET)) /*!< CRC Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 528 | #define USBD_NS ((USBD_T *) (USBD_BASE +NS_OFFSET)) /*!< USB Device Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 529 | #define USBH_NS ((USBH_T *) (USBH_BASE +NS_OFFSET)) /*!< USBH Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 530 | #define OTG_NS ((OTG_T *) (OTG_BASE +NS_OFFSET)) /*!< OTG Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 531 | #define PDMA1_NS ((PDMA_T *) (PDMA1_BASE +NS_OFFSET)) /*!< PDMA1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 532 | #define UI2C0_NS ((UI2C_T *) (USCI0_BASE +NS_OFFSET)) /*!< UI2C0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 533 | #define UI2C1_NS ((UI2C_T *) (USCI1_BASE +NS_OFFSET)) /*!< UI2C1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 534 | #define UI2C2_NS ((UI2C_T *) (USCI2_BASE +NS_OFFSET)) /*!< UI2C2 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 535 | #define USPI0_NS ((USPI_T *) (USCI0_BASE +NS_OFFSET)) /*!< USPI0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 536 | #define USPI1_NS ((USPI_T *) (USCI1_BASE +NS_OFFSET)) /*!< USPI1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 537 | #define UUART0_NS ((UUART_T *) (USCI0_BASE+NS_OFFSET)) /*!< UUART0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 538 | #define UUART1_NS ((UUART_T *) (USCI1_BASE+NS_OFFSET)) /*!< UUART1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 539 | #define SCU_NS ((SCU_T *) (SCU_BASE +NS_OFFSET)) /*!< SCU Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 540 | #define ECAP0_NS ((ECAP_T *) (ECAP0_BASE+NS_OFFSET)) /*!< ECAP0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 541 | #define ECAP1_NS ((ECAP_T *) (ECAP1_BASE+NS_OFFSET)) /*!< ECAP1 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 542 | #define CAN0_NS ((CAN_T *) (CAN0_BASE +NS_OFFSET)) /*!< CAN0 Pointer */ |
kadonotakashi | 0:8fdf9a60065b | 543 | |
kadonotakashi | 0:8fdf9a60065b | 544 | /**@}*/ /* end of group PMODULE_NS */ |
kadonotakashi | 0:8fdf9a60065b | 545 | /**@}*/ /* end of group PMODULE */ |
kadonotakashi | 0:8fdf9a60065b | 546 | |
kadonotakashi | 0:8fdf9a60065b | 547 | /* -------------------- End of section using anonymous unions ------------------- */ |
kadonotakashi | 0:8fdf9a60065b | 548 | #if defined (__CC_ARM) |
kadonotakashi | 0:8fdf9a60065b | 549 | #pragma pop |
kadonotakashi | 0:8fdf9a60065b | 550 | #elif defined (__ICCARM__) |
kadonotakashi | 0:8fdf9a60065b | 551 | /* leave anonymous unions enabled */ |
kadonotakashi | 0:8fdf9a60065b | 552 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
kadonotakashi | 0:8fdf9a60065b | 553 | #pragma clang diagnostic pop |
kadonotakashi | 0:8fdf9a60065b | 554 | #elif defined (__GNUC__) |
kadonotakashi | 0:8fdf9a60065b | 555 | /* anonymous unions are enabled by default */ |
kadonotakashi | 0:8fdf9a60065b | 556 | #elif defined (__TMS470__) |
kadonotakashi | 0:8fdf9a60065b | 557 | /* anonymous unions are enabled by default */ |
kadonotakashi | 0:8fdf9a60065b | 558 | #elif defined (__TASKING__) |
kadonotakashi | 0:8fdf9a60065b | 559 | #pragma warning restore |
kadonotakashi | 0:8fdf9a60065b | 560 | #elif defined (__CSMC__) |
kadonotakashi | 0:8fdf9a60065b | 561 | /* anonymous unions are enabled by default */ |
kadonotakashi | 0:8fdf9a60065b | 562 | #else |
kadonotakashi | 0:8fdf9a60065b | 563 | #warning Not supported compiler type |
kadonotakashi | 0:8fdf9a60065b | 564 | #endif |
kadonotakashi | 0:8fdf9a60065b | 565 | |
kadonotakashi | 0:8fdf9a60065b | 566 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 567 | } |
kadonotakashi | 0:8fdf9a60065b | 568 | #endif |
kadonotakashi | 0:8fdf9a60065b | 569 | |
kadonotakashi | 0:8fdf9a60065b | 570 | |
kadonotakashi | 0:8fdf9a60065b | 571 | /*=============================================================================*/ |
kadonotakashi | 0:8fdf9a60065b | 572 | typedef volatile unsigned char vu8; |
kadonotakashi | 0:8fdf9a60065b | 573 | typedef volatile unsigned long vu32; |
kadonotakashi | 0:8fdf9a60065b | 574 | typedef volatile unsigned short vu16; |
kadonotakashi | 0:8fdf9a60065b | 575 | #define M8(adr) (*((vu8 *) (adr))) |
kadonotakashi | 0:8fdf9a60065b | 576 | #define M16(adr) (*((vu16 *) (adr))) |
kadonotakashi | 0:8fdf9a60065b | 577 | #define M32(adr) (*((vu32 *) (adr))) |
kadonotakashi | 0:8fdf9a60065b | 578 | |
kadonotakashi | 0:8fdf9a60065b | 579 | #define outpw(port,value) (*((volatile unsigned int *)(port))=(value)) |
kadonotakashi | 0:8fdf9a60065b | 580 | #define inpw(port) ((*((volatile unsigned int *)(port)))) |
kadonotakashi | 0:8fdf9a60065b | 581 | #define outpb(port,value) (*((volatile unsigned char *)(port))=(value)) |
kadonotakashi | 0:8fdf9a60065b | 582 | #define inpb(port) ((*((volatile unsigned char *)(port)))) |
kadonotakashi | 0:8fdf9a60065b | 583 | #define outps(port,value) (*((volatile unsigned short *)(port))=(value)) |
kadonotakashi | 0:8fdf9a60065b | 584 | #define inps(port) ((*((volatile unsigned short *)(port)))) |
kadonotakashi | 0:8fdf9a60065b | 585 | |
kadonotakashi | 0:8fdf9a60065b | 586 | #define outp32(port,value) (*((volatile unsigned int *)(port))=(value)) |
kadonotakashi | 0:8fdf9a60065b | 587 | #define inp32(port) ((*((volatile unsigned int *)(port)))) |
kadonotakashi | 0:8fdf9a60065b | 588 | #define outp8(port,value) (*((volatile unsigned char *)(port))=(value)) |
kadonotakashi | 0:8fdf9a60065b | 589 | #define inp8(port) ((*((volatile unsigned char *)(port)))) |
kadonotakashi | 0:8fdf9a60065b | 590 | #define outp16(port,value) (*((volatile unsigned short *)(port))=(value)) |
kadonotakashi | 0:8fdf9a60065b | 591 | #define inp16(port) ((*((volatile unsigned short *)(port)))) |
kadonotakashi | 0:8fdf9a60065b | 592 | |
kadonotakashi | 0:8fdf9a60065b | 593 | |
kadonotakashi | 0:8fdf9a60065b | 594 | #define E_SUCCESS 0 |
kadonotakashi | 0:8fdf9a60065b | 595 | |
kadonotakashi | 0:8fdf9a60065b | 596 | #define TRUE (1L) |
kadonotakashi | 0:8fdf9a60065b | 597 | #define FALSE (0L) |
kadonotakashi | 0:8fdf9a60065b | 598 | |
kadonotakashi | 0:8fdf9a60065b | 599 | #define ENABLE 1 |
kadonotakashi | 0:8fdf9a60065b | 600 | #define DISABLE 0 |
kadonotakashi | 0:8fdf9a60065b | 601 | |
kadonotakashi | 0:8fdf9a60065b | 602 | /* Bit Mask Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 603 | #define BIT0 0x00000001UL |
kadonotakashi | 0:8fdf9a60065b | 604 | #define BIT1 0x00000002UL |
kadonotakashi | 0:8fdf9a60065b | 605 | #define BIT2 0x00000004UL |
kadonotakashi | 0:8fdf9a60065b | 606 | #define BIT3 0x00000008UL |
kadonotakashi | 0:8fdf9a60065b | 607 | #define BIT4 0x00000010UL |
kadonotakashi | 0:8fdf9a60065b | 608 | #define BIT5 0x00000020UL |
kadonotakashi | 0:8fdf9a60065b | 609 | #define BIT6 0x00000040UL |
kadonotakashi | 0:8fdf9a60065b | 610 | #define BIT7 0x00000080UL |
kadonotakashi | 0:8fdf9a60065b | 611 | #define BIT8 0x00000100UL |
kadonotakashi | 0:8fdf9a60065b | 612 | #define BIT9 0x00000200UL |
kadonotakashi | 0:8fdf9a60065b | 613 | #define BIT10 0x00000400UL |
kadonotakashi | 0:8fdf9a60065b | 614 | #define BIT11 0x00000800UL |
kadonotakashi | 0:8fdf9a60065b | 615 | #define BIT12 0x00001000UL |
kadonotakashi | 0:8fdf9a60065b | 616 | #define BIT13 0x00002000UL |
kadonotakashi | 0:8fdf9a60065b | 617 | #define BIT14 0x00004000UL |
kadonotakashi | 0:8fdf9a60065b | 618 | #define BIT15 0x00008000UL |
kadonotakashi | 0:8fdf9a60065b | 619 | #define BIT16 0x00010000UL |
kadonotakashi | 0:8fdf9a60065b | 620 | #define BIT17 0x00020000UL |
kadonotakashi | 0:8fdf9a60065b | 621 | #define BIT18 0x00040000UL |
kadonotakashi | 0:8fdf9a60065b | 622 | #define BIT19 0x00080000UL |
kadonotakashi | 0:8fdf9a60065b | 623 | #define BIT20 0x00100000UL |
kadonotakashi | 0:8fdf9a60065b | 624 | #define BIT21 0x00200000UL |
kadonotakashi | 0:8fdf9a60065b | 625 | #define BIT22 0x00400000UL |
kadonotakashi | 0:8fdf9a60065b | 626 | #define BIT23 0x00800000UL |
kadonotakashi | 0:8fdf9a60065b | 627 | #define BIT24 0x01000000UL |
kadonotakashi | 0:8fdf9a60065b | 628 | #define BIT25 0x02000000UL |
kadonotakashi | 0:8fdf9a60065b | 629 | #define BIT26 0x04000000UL |
kadonotakashi | 0:8fdf9a60065b | 630 | #define BIT27 0x08000000UL |
kadonotakashi | 0:8fdf9a60065b | 631 | #define BIT28 0x10000000UL |
kadonotakashi | 0:8fdf9a60065b | 632 | #define BIT29 0x20000000UL |
kadonotakashi | 0:8fdf9a60065b | 633 | #define BIT30 0x40000000UL |
kadonotakashi | 0:8fdf9a60065b | 634 | #define BIT31 0x80000000UL |
kadonotakashi | 0:8fdf9a60065b | 635 | |
kadonotakashi | 0:8fdf9a60065b | 636 | |
kadonotakashi | 0:8fdf9a60065b | 637 | /* Byte Mask Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 638 | #define BYTE0_Msk (0x000000FFUL) |
kadonotakashi | 0:8fdf9a60065b | 639 | #define BYTE1_Msk (0x0000FF00UL) |
kadonotakashi | 0:8fdf9a60065b | 640 | #define BYTE2_Msk (0x00FF0000UL) |
kadonotakashi | 0:8fdf9a60065b | 641 | #define BYTE3_Msk (0xFF000000UL) |
kadonotakashi | 0:8fdf9a60065b | 642 | |
kadonotakashi | 0:8fdf9a60065b | 643 | #define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ |
kadonotakashi | 0:8fdf9a60065b | 644 | #define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8UL) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ |
kadonotakashi | 0:8fdf9a60065b | 645 | #define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16UL) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ |
kadonotakashi | 0:8fdf9a60065b | 646 | #define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24UL) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ |
kadonotakashi | 0:8fdf9a60065b | 647 | |
kadonotakashi | 0:8fdf9a60065b | 648 | |
kadonotakashi | 0:8fdf9a60065b | 649 | /******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 650 | /* Peripheral header files */ |
kadonotakashi | 0:8fdf9a60065b | 651 | /******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 652 | #include "m2351_sys.h" |
kadonotakashi | 0:8fdf9a60065b | 653 | #include "m2351_clk.h" |
kadonotakashi | 0:8fdf9a60065b | 654 | #include "m2351_dac.h" |
kadonotakashi | 0:8fdf9a60065b | 655 | #include "m2351_eadc.h" |
kadonotakashi | 0:8fdf9a60065b | 656 | #include "m2351_ebi.h" |
kadonotakashi | 0:8fdf9a60065b | 657 | #include "m2351_ecap.h" |
kadonotakashi | 0:8fdf9a60065b | 658 | #include "m2351_fmc.h" |
kadonotakashi | 0:8fdf9a60065b | 659 | #include "m2351_gpio.h" |
kadonotakashi | 0:8fdf9a60065b | 660 | #include "m2351_i2c.h" |
kadonotakashi | 0:8fdf9a60065b | 661 | #include "m2351_i2s.h" |
kadonotakashi | 0:8fdf9a60065b | 662 | #include "m2351_bpwm.h" |
kadonotakashi | 0:8fdf9a60065b | 663 | #include "m2351_epwm.h" |
kadonotakashi | 0:8fdf9a60065b | 664 | #include "m2351_qspi.h" |
kadonotakashi | 0:8fdf9a60065b | 665 | #include "m2351_spi.h" |
kadonotakashi | 0:8fdf9a60065b | 666 | #include "m2351_spi5.h" |
kadonotakashi | 0:8fdf9a60065b | 667 | #include "m2351_timer.h" |
kadonotakashi | 0:8fdf9a60065b | 668 | #include "m2351_timer_pwm.h" |
kadonotakashi | 0:8fdf9a60065b | 669 | #include "m2351_wdt.h" |
kadonotakashi | 0:8fdf9a60065b | 670 | #include "m2351_wwdt.h" |
kadonotakashi | 0:8fdf9a60065b | 671 | #include "m2351_rtc.h" |
kadonotakashi | 0:8fdf9a60065b | 672 | #include "m2351_uart.h" |
kadonotakashi | 0:8fdf9a60065b | 673 | #include "m2351_acmp.h" |
kadonotakashi | 0:8fdf9a60065b | 674 | #include "m2351_crc.h" |
kadonotakashi | 0:8fdf9a60065b | 675 | #include "m2351_usbd.h" |
kadonotakashi | 0:8fdf9a60065b | 676 | #include "m2351_otg.h" |
kadonotakashi | 0:8fdf9a60065b | 677 | #include "m2351_pdma.h" |
kadonotakashi | 0:8fdf9a60065b | 678 | #include "m2351_ebi.h" |
kadonotakashi | 0:8fdf9a60065b | 679 | #include "m2351_crypto.h" |
kadonotakashi | 0:8fdf9a60065b | 680 | #include "m2351_sc.h" |
kadonotakashi | 0:8fdf9a60065b | 681 | #include "m2351_scuart.h" |
kadonotakashi | 0:8fdf9a60065b | 682 | #include "m2351_usci_spi.h" |
kadonotakashi | 0:8fdf9a60065b | 683 | #include "m2351_usci_uart.h" |
kadonotakashi | 0:8fdf9a60065b | 684 | #include "m2351_usci_i2c.h" |
kadonotakashi | 0:8fdf9a60065b | 685 | #include "m2351_sdh.h" |
kadonotakashi | 0:8fdf9a60065b | 686 | #include "m2351_qei.h" |
kadonotakashi | 0:8fdf9a60065b | 687 | #include "m2351_can.h" |
kadonotakashi | 0:8fdf9a60065b | 688 | #include "m2351_scu.h" |
kadonotakashi | 0:8fdf9a60065b | 689 | #include "m2351_bootloader.h" |
kadonotakashi | 0:8fdf9a60065b | 690 | |
kadonotakashi | 0:8fdf9a60065b | 691 | #endif /* __M2351_H__ */ |
kadonotakashi | 0:8fdf9a60065b | 692 | |
kadonotakashi | 0:8fdf9a60065b | 693 | |
kadonotakashi | 0:8fdf9a60065b | 694 | /* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. */ |
kadonotakashi | 0:8fdf9a60065b | 695 |