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mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_slcd.h@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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kadonotakashi | 0:8fdf9a60065b | 1 | /* |
kadonotakashi | 0:8fdf9a60065b | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
kadonotakashi | 0:8fdf9a60065b | 3 | * All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 4 | * |
kadonotakashi | 0:8fdf9a60065b | 5 | * Redistribution and use in source and binary forms, with or without modification, |
kadonotakashi | 0:8fdf9a60065b | 6 | * are permitted provided that the following conditions are met: |
kadonotakashi | 0:8fdf9a60065b | 7 | * |
kadonotakashi | 0:8fdf9a60065b | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
kadonotakashi | 0:8fdf9a60065b | 9 | * of conditions and the following disclaimer. |
kadonotakashi | 0:8fdf9a60065b | 10 | * |
kadonotakashi | 0:8fdf9a60065b | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
kadonotakashi | 0:8fdf9a60065b | 12 | * list of conditions and the following disclaimer in the documentation and/or |
kadonotakashi | 0:8fdf9a60065b | 13 | * other materials provided with the distribution. |
kadonotakashi | 0:8fdf9a60065b | 14 | * |
kadonotakashi | 0:8fdf9a60065b | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
kadonotakashi | 0:8fdf9a60065b | 16 | * contributors may be used to endorse or promote products derived from this |
kadonotakashi | 0:8fdf9a60065b | 17 | * software without specific prior written permission. |
kadonotakashi | 0:8fdf9a60065b | 18 | * |
kadonotakashi | 0:8fdf9a60065b | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
kadonotakashi | 0:8fdf9a60065b | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
kadonotakashi | 0:8fdf9a60065b | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
kadonotakashi | 0:8fdf9a60065b | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
kadonotakashi | 0:8fdf9a60065b | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
kadonotakashi | 0:8fdf9a60065b | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
kadonotakashi | 0:8fdf9a60065b | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
kadonotakashi | 0:8fdf9a60065b | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
kadonotakashi | 0:8fdf9a60065b | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
kadonotakashi | 0:8fdf9a60065b | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
kadonotakashi | 0:8fdf9a60065b | 29 | */ |
kadonotakashi | 0:8fdf9a60065b | 30 | |
kadonotakashi | 0:8fdf9a60065b | 31 | #ifndef _FSL_SLCD_H_ |
kadonotakashi | 0:8fdf9a60065b | 32 | #define _FSL_SLCD_H_ |
kadonotakashi | 0:8fdf9a60065b | 33 | |
kadonotakashi | 0:8fdf9a60065b | 34 | #include "fsl_common.h" |
kadonotakashi | 0:8fdf9a60065b | 35 | |
kadonotakashi | 0:8fdf9a60065b | 36 | /*! |
kadonotakashi | 0:8fdf9a60065b | 37 | * @addtogroup slcd |
kadonotakashi | 0:8fdf9a60065b | 38 | * @{ |
kadonotakashi | 0:8fdf9a60065b | 39 | */ |
kadonotakashi | 0:8fdf9a60065b | 40 | |
kadonotakashi | 0:8fdf9a60065b | 41 | /*! @file */ |
kadonotakashi | 0:8fdf9a60065b | 42 | |
kadonotakashi | 0:8fdf9a60065b | 43 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 44 | * Definitions |
kadonotakashi | 0:8fdf9a60065b | 45 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 46 | |
kadonotakashi | 0:8fdf9a60065b | 47 | /*! @name Driver version */ |
kadonotakashi | 0:8fdf9a60065b | 48 | /*@{*/ |
kadonotakashi | 0:8fdf9a60065b | 49 | /*! @brief SLCD driver version 2.0.0. */ |
kadonotakashi | 0:8fdf9a60065b | 50 | #define FSL_SLCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) |
kadonotakashi | 0:8fdf9a60065b | 51 | /*@}*/ |
kadonotakashi | 0:8fdf9a60065b | 52 | |
kadonotakashi | 0:8fdf9a60065b | 53 | /*! @brief SLCD power supply option. */ |
kadonotakashi | 0:8fdf9a60065b | 54 | typedef enum _slcd_power_supply_option |
kadonotakashi | 0:8fdf9a60065b | 55 | { |
kadonotakashi | 0:8fdf9a60065b | 56 | kSLCD_InternalVll3UseChargePump = |
kadonotakashi | 0:8fdf9a60065b | 57 | 2U, /*!< VLL3 connected to VDD internally, charge pump is used to generate VLL1 and VLL2. */ |
kadonotakashi | 0:8fdf9a60065b | 58 | kSLCD_ExternalVll3UseResistorBiasNetwork = |
kadonotakashi | 0:8fdf9a60065b | 59 | 4U, /*!< VLL3 is driven externally and resistor bias network is used to generate VLL1 and VLL2. */ |
kadonotakashi | 0:8fdf9a60065b | 60 | kSLCD_ExteranlVll3UseChargePump = |
kadonotakashi | 0:8fdf9a60065b | 61 | 6U, /*!< VLL3 is driven externally and charge pump is used to generate VLL1 and VLL2. */ |
kadonotakashi | 0:8fdf9a60065b | 62 | kSLCD_InternalVll1UseChargePump = |
kadonotakashi | 0:8fdf9a60065b | 63 | 7U /*!< VIREG is connected to VLL1 internally and charge pump is used to generate VLL2 and VLL3. */ |
kadonotakashi | 0:8fdf9a60065b | 64 | } slcd_power_supply_option_t; |
kadonotakashi | 0:8fdf9a60065b | 65 | |
kadonotakashi | 0:8fdf9a60065b | 66 | /*! @brief SLCD regulated voltage trim parameter, be used to meet the desired contrast. */ |
kadonotakashi | 0:8fdf9a60065b | 67 | typedef enum _slcd_regulated_voltage_trim |
kadonotakashi | 0:8fdf9a60065b | 68 | { |
kadonotakashi | 0:8fdf9a60065b | 69 | kSLCD_RegulatedVolatgeTrim00 = 0U, /*!< Increase the voltage to 0.91 V. */ |
kadonotakashi | 0:8fdf9a60065b | 70 | kSLCD_RegulatedVolatgeTrim01, /*!< Increase the voltage to 1.01 V. */ |
kadonotakashi | 0:8fdf9a60065b | 71 | kSLCD_RegulatedVolatgeTrim02, /*!< Increase the voltage to 0.96 V. */ |
kadonotakashi | 0:8fdf9a60065b | 72 | kSLCD_RegulatedVolatgeTrim03, /*!< Increase the voltage to 1.06 V. */ |
kadonotakashi | 0:8fdf9a60065b | 73 | kSLCD_RegulatedVolatgeTrim04, /*!< Increase the voltage to 0.93 V. */ |
kadonotakashi | 0:8fdf9a60065b | 74 | kSLCD_RegulatedVolatgeTrim05, /*!< Increase the voltage to 1.02 V. */ |
kadonotakashi | 0:8fdf9a60065b | 75 | kSLCD_RegulatedVolatgeTrim06, /*!< Increase the voltage to 0.98 V. */ |
kadonotakashi | 0:8fdf9a60065b | 76 | kSLCD_RegulatedVolatgeTrim07, /*!< Increase the voltage to 1.08 V. */ |
kadonotakashi | 0:8fdf9a60065b | 77 | kSLCD_RegulatedVolatgeTrim08, /*!< Increase the voltage to 0.92 V. */ |
kadonotakashi | 0:8fdf9a60065b | 78 | kSLCD_RegulatedVolatgeTrim09, /*!< Increase the voltage to 1.02 V. */ |
kadonotakashi | 0:8fdf9a60065b | 79 | kSLCD_RegulatedVolatgeTrim10, /*!< Increase the voltage to 0.97 V. */ |
kadonotakashi | 0:8fdf9a60065b | 80 | kSLCD_RegulatedVolatgeTrim11, /*!< Increase the voltage to 1.07 V. */ |
kadonotakashi | 0:8fdf9a60065b | 81 | kSLCD_RegulatedVolatgeTrim12, /*!< Increase the voltage to 0.94 V. */ |
kadonotakashi | 0:8fdf9a60065b | 82 | kSLCD_RegulatedVolatgeTrim13, /*!< Increase the voltage to 1.05 V. */ |
kadonotakashi | 0:8fdf9a60065b | 83 | kSLCD_RegulatedVolatgeTrim14, /*!< Increase the voltage to 0.99 V. */ |
kadonotakashi | 0:8fdf9a60065b | 84 | kSLCD_RegulatedVolatgeTrim15 /*!< Increase the voltage to 1.09 V. */ |
kadonotakashi | 0:8fdf9a60065b | 85 | } slcd_regulated_voltage_trim_t; |
kadonotakashi | 0:8fdf9a60065b | 86 | |
kadonotakashi | 0:8fdf9a60065b | 87 | /*! @brief SLCD load adjust to handle different LCD glass capacitance or |
kadonotakashi | 0:8fdf9a60065b | 88 | * configure the LCD charge pump clock source. |
kadonotakashi | 0:8fdf9a60065b | 89 | * Adjust the LCD glass capacitance if resistor bias network is enabled: |
kadonotakashi | 0:8fdf9a60065b | 90 | * kSLCD_LowLoadOrFastestClkSrc - Low load (LCD glass capacitance 2000pF or lower. |
kadonotakashi | 0:8fdf9a60065b | 91 | * LCD or GPIO function can be used on VLL1,VLL2,Vcap1 and Vcap2 pins) |
kadonotakashi | 0:8fdf9a60065b | 92 | * kSLCD_LowLoadOrIntermediateClkSrc - low load (LCD glass capacitance 2000pF or lower. |
kadonotakashi | 0:8fdf9a60065b | 93 | * LCD or GPIO function can be used on VLL1,VLL2,Vcap1 and Vcap2 pins) |
kadonotakashi | 0:8fdf9a60065b | 94 | * kSLCD_HighLoadOrIntermediateClkSrc - high load (LCD glass capacitance 8000pF or lower. |
kadonotakashi | 0:8fdf9a60065b | 95 | * LCD or GPIO function can be used on Vcap1 and Vcap2 pins) |
kadonotakashi | 0:8fdf9a60065b | 96 | * kSLCD_HighLoadOrSlowestClkSrc - high load (LCD glass capacitance 8000pF or lower |
kadonotakashi | 0:8fdf9a60065b | 97 | * LCD or GPIO function can be used on Vcap1 and Vcap2 pins) |
kadonotakashi | 0:8fdf9a60065b | 98 | * Adjust clock for charge pump if charge pump is enabled: |
kadonotakashi | 0:8fdf9a60065b | 99 | * kSLCD_LowLoadOrFastestClkSrc - Fasten clock source (LCD glass capacitance |
kadonotakashi | 0:8fdf9a60065b | 100 | * 8000pF or 4000pF or lower if Fast Frame Rate is set) |
kadonotakashi | 0:8fdf9a60065b | 101 | * kSLCD_LowLoadOrIntermediateClkSrc - Intermediate clock source (LCD glass |
kadonotakashi | 0:8fdf9a60065b | 102 | * capacitance 4000pF or 2000pF or lower if Fast Frame Rate is set) |
kadonotakashi | 0:8fdf9a60065b | 103 | * kSLCD_HighLoadOrIntermediateClkSrc - Intermediate clock source (LCD glass |
kadonotakashi | 0:8fdf9a60065b | 104 | * capacitance 2000pF or 1000pF or lower if Fast Frame Rate is set) |
kadonotakashi | 0:8fdf9a60065b | 105 | * kSLCD_HighLoadOrSlowestClkSrc - slowest clock source (LCD glass capacitance |
kadonotakashi | 0:8fdf9a60065b | 106 | * 1000pF or 500pF or lower if Fast Frame Rate is set) |
kadonotakashi | 0:8fdf9a60065b | 107 | */ |
kadonotakashi | 0:8fdf9a60065b | 108 | typedef enum _slcd_load_adjust |
kadonotakashi | 0:8fdf9a60065b | 109 | { |
kadonotakashi | 0:8fdf9a60065b | 110 | kSLCD_LowLoadOrFastestClkSrc = 0U, /*!< Adjust in low load or selects fastest clock. */ |
kadonotakashi | 0:8fdf9a60065b | 111 | kSLCD_LowLoadOrIntermediateClkSrc, /*!< Adjust in low load or selects intermediate clock. */ |
kadonotakashi | 0:8fdf9a60065b | 112 | kSLCD_HighLoadOrIntermediateClkSrc, /*!< Adjust in high load or selects intermediate clock. */ |
kadonotakashi | 0:8fdf9a60065b | 113 | kSLCD_HighLoadOrSlowestClkSrc /*!< Adjust in high load or selects slowest clock. */ |
kadonotakashi | 0:8fdf9a60065b | 114 | } slcd_load_adjust_t; |
kadonotakashi | 0:8fdf9a60065b | 115 | |
kadonotakashi | 0:8fdf9a60065b | 116 | /*! @brief SLCD clock source. */ |
kadonotakashi | 0:8fdf9a60065b | 117 | typedef enum _slcd_clock_src |
kadonotakashi | 0:8fdf9a60065b | 118 | { |
kadonotakashi | 0:8fdf9a60065b | 119 | kSLCD_DefaultClk = 0U, /*!< Select default clock ERCLK32K. */ |
kadonotakashi | 0:8fdf9a60065b | 120 | kSLCD_AlternateClk1 = 1U, /*!< Select alternate clock source 1 : MCGIRCLK. */ |
kadonotakashi | 0:8fdf9a60065b | 121 | #if FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE |
kadonotakashi | 0:8fdf9a60065b | 122 | kSLCD_AlternateClk2 = 3U /*!< Select alternate clock source 2 : OSCERCLK. */ |
kadonotakashi | 0:8fdf9a60065b | 123 | #endif /* FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE */ |
kadonotakashi | 0:8fdf9a60065b | 124 | } slcd_clock_src_t; |
kadonotakashi | 0:8fdf9a60065b | 125 | |
kadonotakashi | 0:8fdf9a60065b | 126 | /*! @brief SLCD alternate clock divider. */ |
kadonotakashi | 0:8fdf9a60065b | 127 | typedef enum _slcd_alt_clock_div |
kadonotakashi | 0:8fdf9a60065b | 128 | { |
kadonotakashi | 0:8fdf9a60065b | 129 | kSLCD_AltClkDivFactor1 = 0U, /*!< No divide for alternate clock. */ |
kadonotakashi | 0:8fdf9a60065b | 130 | kSLCD_AltClkDivFactor64, /*!< Divide alternate clock with factor 64. */ |
kadonotakashi | 0:8fdf9a60065b | 131 | kSLCD_AltClkDivFactor256, /*!< Divide alternate clock with factor 256. */ |
kadonotakashi | 0:8fdf9a60065b | 132 | kSLCD_AltClkDivFactor512 /*!< Divide alternate clock with factor 512. */ |
kadonotakashi | 0:8fdf9a60065b | 133 | } slcd_alt_clock_div_t; |
kadonotakashi | 0:8fdf9a60065b | 134 | |
kadonotakashi | 0:8fdf9a60065b | 135 | /*! @brief SLCD clock prescaler to generate frame frequency. */ |
kadonotakashi | 0:8fdf9a60065b | 136 | typedef enum _slcd_clock_prescaler |
kadonotakashi | 0:8fdf9a60065b | 137 | { |
kadonotakashi | 0:8fdf9a60065b | 138 | kSLCD_ClkPrescaler00 = 0U, /*!< Prescaler 0. */ |
kadonotakashi | 0:8fdf9a60065b | 139 | kSLCD_ClkPrescaler01, /*!< Prescaler 1. */ |
kadonotakashi | 0:8fdf9a60065b | 140 | kSLCD_ClkPrescaler02, /*!< Prescaler 2. */ |
kadonotakashi | 0:8fdf9a60065b | 141 | kSLCD_ClkPrescaler03, /*!< Prescaler 3. */ |
kadonotakashi | 0:8fdf9a60065b | 142 | kSLCD_ClkPrescaler04, /*!< Prescaler 4. */ |
kadonotakashi | 0:8fdf9a60065b | 143 | kSLCD_ClkPrescaler05, /*!< Prescaler 5. */ |
kadonotakashi | 0:8fdf9a60065b | 144 | kSLCD_ClkPrescaler06, /*!< Prescaler 6. */ |
kadonotakashi | 0:8fdf9a60065b | 145 | kSLCD_ClkPrescaler07 /*!< Prescaler 7. */ |
kadonotakashi | 0:8fdf9a60065b | 146 | } slcd_clock_prescaler_t; |
kadonotakashi | 0:8fdf9a60065b | 147 | |
kadonotakashi | 0:8fdf9a60065b | 148 | /*! @brief SLCD duty cycle. */ |
kadonotakashi | 0:8fdf9a60065b | 149 | typedef enum _slcd_duty_cycle |
kadonotakashi | 0:8fdf9a60065b | 150 | { |
kadonotakashi | 0:8fdf9a60065b | 151 | kSLCD_1Div1DutyCycle = 0U, /*!< LCD use 1 BP 1/1 duty cycle. */ |
kadonotakashi | 0:8fdf9a60065b | 152 | kSLCD_1Div2DutyCycle, /*!< LCD use 2 BP 1/2 duty cycle. */ |
kadonotakashi | 0:8fdf9a60065b | 153 | kSLCD_1Div3DutyCycle, /*!< LCD use 3 BP 1/3 duty cycle. */ |
kadonotakashi | 0:8fdf9a60065b | 154 | kSLCD_1Div4DutyCycle, /*!< LCD use 4 BP 1/4 duty cycle. */ |
kadonotakashi | 0:8fdf9a60065b | 155 | kSLCD_1Div5DutyCycle, /*!< LCD use 5 BP 1/5 duty cycle. */ |
kadonotakashi | 0:8fdf9a60065b | 156 | kSLCD_1Div6DutyCycle, /*!< LCD use 6 BP 1/6 duty cycle. */ |
kadonotakashi | 0:8fdf9a60065b | 157 | kSLCD_1Div7DutyCycle, /*!< LCD use 7 BP 1/7 duty cycle. */ |
kadonotakashi | 0:8fdf9a60065b | 158 | kSLCD_1Div8DutyCycle /*!< LCD use 8 BP 1/8 duty cycle. */ |
kadonotakashi | 0:8fdf9a60065b | 159 | } slcd_duty_cycle_t; |
kadonotakashi | 0:8fdf9a60065b | 160 | |
kadonotakashi | 0:8fdf9a60065b | 161 | /*! @brief SLCD segment phase type. */ |
kadonotakashi | 0:8fdf9a60065b | 162 | typedef enum _slcd_phase_type |
kadonotakashi | 0:8fdf9a60065b | 163 | { |
kadonotakashi | 0:8fdf9a60065b | 164 | kSLCD_NoPhaseActivate = 0x00U, /*!< LCD wareform no phase activates. */ |
kadonotakashi | 0:8fdf9a60065b | 165 | kSLCD_PhaseAActivate = 0x01U, /*!< LCD waveform phase A activates. */ |
kadonotakashi | 0:8fdf9a60065b | 166 | kSLCD_PhaseBActivate = 0x02U, /*!< LCD waveform phase B activates. */ |
kadonotakashi | 0:8fdf9a60065b | 167 | kSLCD_PhaseCActivate = 0x04U, /*!< LCD waveform phase C activates. */ |
kadonotakashi | 0:8fdf9a60065b | 168 | kSLCD_PhaseDActivate = 0x08U, /*!< LCD waveform phase D activates. */ |
kadonotakashi | 0:8fdf9a60065b | 169 | kSLCD_PhaseEActivate = 0x10U, /*!< LCD waveform phase E activates. */ |
kadonotakashi | 0:8fdf9a60065b | 170 | kSLCD_PhaseFActivate = 0x20U, /*!< LCD waveform phase F activates. */ |
kadonotakashi | 0:8fdf9a60065b | 171 | kSLCD_PhaseGActivate = 0x40U, /*!< LCD waveform phase G activates. */ |
kadonotakashi | 0:8fdf9a60065b | 172 | kSLCD_PhaseHActivate = 0x80U /*!< LCD waveform phase H activates. */ |
kadonotakashi | 0:8fdf9a60065b | 173 | } slcd_phase_type_t; |
kadonotakashi | 0:8fdf9a60065b | 174 | |
kadonotakashi | 0:8fdf9a60065b | 175 | /*! @brief SLCD segment phase bit index. */ |
kadonotakashi | 0:8fdf9a60065b | 176 | typedef enum _slcd_phase_index |
kadonotakashi | 0:8fdf9a60065b | 177 | { |
kadonotakashi | 0:8fdf9a60065b | 178 | kSLCD_PhaseAIndex = 0x0U, /*!< LCD phase A bit index. */ |
kadonotakashi | 0:8fdf9a60065b | 179 | kSLCD_PhaseBIndex = 0x1U, /*!< LCD phase B bit index. */ |
kadonotakashi | 0:8fdf9a60065b | 180 | kSLCD_PhaseCIndex = 0x2U, /*!< LCD phase C bit index. */ |
kadonotakashi | 0:8fdf9a60065b | 181 | kSLCD_PhaseDIndex = 0x3U, /*!< LCD phase D bit index. */ |
kadonotakashi | 0:8fdf9a60065b | 182 | kSLCD_PhaseEIndex = 0x4U, /*!< LCD phase E bit index. */ |
kadonotakashi | 0:8fdf9a60065b | 183 | kSLCD_PhaseFIndex = 0x5U, /*!< LCD phase F bit index. */ |
kadonotakashi | 0:8fdf9a60065b | 184 | kSLCD_PhaseGIndex = 0x6U, /*!< LCD phase G bit index. */ |
kadonotakashi | 0:8fdf9a60065b | 185 | kSLCD_PhaseHIndex = 0x7U /*!< LCD phase H bit index. */ |
kadonotakashi | 0:8fdf9a60065b | 186 | } slcd_phase_index_t; |
kadonotakashi | 0:8fdf9a60065b | 187 | |
kadonotakashi | 0:8fdf9a60065b | 188 | /*! @brief SLCD display mode. */ |
kadonotakashi | 0:8fdf9a60065b | 189 | typedef enum _slcd_display_mode |
kadonotakashi | 0:8fdf9a60065b | 190 | { |
kadonotakashi | 0:8fdf9a60065b | 191 | kSLCD_NormalMode = 0U, /*!< LCD Normal display mode. */ |
kadonotakashi | 0:8fdf9a60065b | 192 | kSLCD_AlternateMode, /*!< LCD Alternate display mode. For four back planes or less. */ |
kadonotakashi | 0:8fdf9a60065b | 193 | kSLCD_BlankMode /*!< LCD Blank display mode. */ |
kadonotakashi | 0:8fdf9a60065b | 194 | } slcd_display_mode_t; |
kadonotakashi | 0:8fdf9a60065b | 195 | |
kadonotakashi | 0:8fdf9a60065b | 196 | /*! @brief SLCD blink mode. */ |
kadonotakashi | 0:8fdf9a60065b | 197 | typedef enum _slcd_blink_mode |
kadonotakashi | 0:8fdf9a60065b | 198 | { |
kadonotakashi | 0:8fdf9a60065b | 199 | kSLCD_BlankDisplayBlink = 0U, /*!< Display blank during the blink period. */ |
kadonotakashi | 0:8fdf9a60065b | 200 | kSLCD_AltDisplayBlink /*!< Display alternate display during the blink period if duty cycle is lower than 5. */ |
kadonotakashi | 0:8fdf9a60065b | 201 | } slcd_blink_mode_t; |
kadonotakashi | 0:8fdf9a60065b | 202 | |
kadonotakashi | 0:8fdf9a60065b | 203 | /*! @brief SLCD blink rate. */ |
kadonotakashi | 0:8fdf9a60065b | 204 | typedef enum _slcd_blink_rate |
kadonotakashi | 0:8fdf9a60065b | 205 | { |
kadonotakashi | 0:8fdf9a60065b | 206 | kSLCD_BlinkRate00 = 0U, /*!< SLCD blink rate is LCD clock/((2^12)). */ |
kadonotakashi | 0:8fdf9a60065b | 207 | kSLCD_BlinkRate01, /*!< SLCD blink rate is LCD clock/((2^13)). */ |
kadonotakashi | 0:8fdf9a60065b | 208 | kSLCD_BlinkRate02, /*!< SLCD blink rate is LCD clock/((2^14)). */ |
kadonotakashi | 0:8fdf9a60065b | 209 | kSLCD_BlinkRate03, /*!< SLCD blink rate is LCD clock/((2^15)). */ |
kadonotakashi | 0:8fdf9a60065b | 210 | kSLCD_BlinkRate04, /*!< SLCD blink rate is LCD clock/((2^16)). */ |
kadonotakashi | 0:8fdf9a60065b | 211 | kSLCD_BlinkRate05, /*!< SLCD blink rate is LCD clock/((2^17)). */ |
kadonotakashi | 0:8fdf9a60065b | 212 | kSLCD_BlinkRate06, /*!< SLCD blink rate is LCD clock/((2^18)). */ |
kadonotakashi | 0:8fdf9a60065b | 213 | kSLCD_BlinkRate07 /*!< SLCD blink rate is LCD clock/((2^19)). */ |
kadonotakashi | 0:8fdf9a60065b | 214 | } slcd_blink_rate_t; |
kadonotakashi | 0:8fdf9a60065b | 215 | |
kadonotakashi | 0:8fdf9a60065b | 216 | /*! @brief SLCD fault detect clock prescaler. */ |
kadonotakashi | 0:8fdf9a60065b | 217 | typedef enum _slcd_fault_detect_clock_prescaler |
kadonotakashi | 0:8fdf9a60065b | 218 | { |
kadonotakashi | 0:8fdf9a60065b | 219 | kSLCD_FaultSampleFreqDivider1 = 0U, /*!< Fault detect sample clock frequency is 1/1 bus clock. */ |
kadonotakashi | 0:8fdf9a60065b | 220 | kSLCD_FaultSampleFreqDivider2, /*!< Fault detect sample clock frequency is 1/2 bus clock. */ |
kadonotakashi | 0:8fdf9a60065b | 221 | kSLCD_FaultSampleFreqDivider4, /*!< Fault detect sample clock frequency is 1/4 bus clock. */ |
kadonotakashi | 0:8fdf9a60065b | 222 | kSLCD_FaultSampleFreqDivider8, /*!< Fault detect sample clock frequency is 1/8 bus clock. */ |
kadonotakashi | 0:8fdf9a60065b | 223 | kSLCD_FaultSampleFreqDivider16, /*!< Fault detect sample clock frequency is 1/16 bus clock. */ |
kadonotakashi | 0:8fdf9a60065b | 224 | kSLCD_FaultSampleFreqDivider32, /*!< Fault detect sample clock frequency is 1/32 bus clock. */ |
kadonotakashi | 0:8fdf9a60065b | 225 | kSLCD_FaultSampleFreqDivider64, /*!< Fault detect sample clock frequency is 1/64 bus clock. */ |
kadonotakashi | 0:8fdf9a60065b | 226 | kSLCD_FaultSampleFreqDivider128 /*!< Fault detect sample clock frequency is 1/128 bus clock. */ |
kadonotakashi | 0:8fdf9a60065b | 227 | } slcd_fault_detect_clock_prescaler_t; |
kadonotakashi | 0:8fdf9a60065b | 228 | |
kadonotakashi | 0:8fdf9a60065b | 229 | /*! @brief SLCD fault detect sample window width. */ |
kadonotakashi | 0:8fdf9a60065b | 230 | typedef enum _slcd_fault_detect_sample_window_width |
kadonotakashi | 0:8fdf9a60065b | 231 | { |
kadonotakashi | 0:8fdf9a60065b | 232 | kSLCD_FaultDetectWindowWidth4SampleClk = 0U, /*!< Sample window width is 4 sample clock cycles. */ |
kadonotakashi | 0:8fdf9a60065b | 233 | kSLCD_FaultDetectWindowWidth8SampleClk, /*!< Sample window width is 8 sample clock cycles. */ |
kadonotakashi | 0:8fdf9a60065b | 234 | kSLCD_FaultDetectWindowWidth16SampleClk, /*!< Sample window width is 16 sample clock cycles. */ |
kadonotakashi | 0:8fdf9a60065b | 235 | kSLCD_FaultDetectWindowWidth32SampleClk, /*!< Sample window width is 32 sample clock cycles. */ |
kadonotakashi | 0:8fdf9a60065b | 236 | kSLCD_FaultDetectWindowWidth64SampleClk, /*!< Sample window width is 64 sample clock cycles. */ |
kadonotakashi | 0:8fdf9a60065b | 237 | kSLCD_FaultDetectWindowWidth128SampleClk, /*!< Sample window width is 128 sample clock cycles. */ |
kadonotakashi | 0:8fdf9a60065b | 238 | kSLCD_FaultDetectWindowWidth256SampleClk, /*!< Sample window width is 256 sample clock cycles. */ |
kadonotakashi | 0:8fdf9a60065b | 239 | kSLCD_FaultDetectWindowWidth512SampleClk /*!< Sample window width is 512 sample clock cycles. */ |
kadonotakashi | 0:8fdf9a60065b | 240 | } slcd_fault_detect_sample_window_width_t; |
kadonotakashi | 0:8fdf9a60065b | 241 | |
kadonotakashi | 0:8fdf9a60065b | 242 | /*! @brief SLCD interrupt source. */ |
kadonotakashi | 0:8fdf9a60065b | 243 | typedef enum _slcd_interrupt_enable |
kadonotakashi | 0:8fdf9a60065b | 244 | { |
kadonotakashi | 0:8fdf9a60065b | 245 | kSLCD_FaultDetectCompleteInterrupt = 1U, /*!< SLCD fault detection complete interrupt source. */ |
kadonotakashi | 0:8fdf9a60065b | 246 | #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT |
kadonotakashi | 0:8fdf9a60065b | 247 | kSLCD_FrameFreqInterrupt = 2U /*!< SLCD frame frequency interrupt source. Not available in all low-power modes. */ |
kadonotakashi | 0:8fdf9a60065b | 248 | #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */ |
kadonotakashi | 0:8fdf9a60065b | 249 | } slcd_interrupt_enable_t; |
kadonotakashi | 0:8fdf9a60065b | 250 | |
kadonotakashi | 0:8fdf9a60065b | 251 | /*! @brief SLCD behavior in low power mode. */ |
kadonotakashi | 0:8fdf9a60065b | 252 | typedef enum _slcd_lowpower_behavior |
kadonotakashi | 0:8fdf9a60065b | 253 | { |
kadonotakashi | 0:8fdf9a60065b | 254 | kSLCD_EnabledInWaitStop = 0, /*!< SLCD works in wait and stop mode. */ |
kadonotakashi | 0:8fdf9a60065b | 255 | kSLCD_EnabledInWaitOnly, /*!< SLCD works in wait mode and is disabled in stop mode. */ |
kadonotakashi | 0:8fdf9a60065b | 256 | kSLCD_EnabledInStopOnly, /*!< SLCD works in stop mode and is disabled in wait mode. */ |
kadonotakashi | 0:8fdf9a60065b | 257 | kSLCD_DisabledInWaitStop /*!< SLCD is disabled in stop mode and wait mode. */ |
kadonotakashi | 0:8fdf9a60065b | 258 | } slcd_lowpower_behavior; |
kadonotakashi | 0:8fdf9a60065b | 259 | |
kadonotakashi | 0:8fdf9a60065b | 260 | /*! @brief SLCD fault frame detection configure structure. */ |
kadonotakashi | 0:8fdf9a60065b | 261 | typedef struct _slcd_fault_detect_config |
kadonotakashi | 0:8fdf9a60065b | 262 | { |
kadonotakashi | 0:8fdf9a60065b | 263 | bool faultDetectIntEnable; /*!< Fault frame detection interrupt enable flag.*/ |
kadonotakashi | 0:8fdf9a60065b | 264 | bool faultDetectBackPlaneEnable; /*!< True means the pin id fault detected is back plane otherwise front plane. */ |
kadonotakashi | 0:8fdf9a60065b | 265 | uint8_t faultDetectPinIndex; /*!< Fault detected pin id from 0 to 63. */ |
kadonotakashi | 0:8fdf9a60065b | 266 | slcd_fault_detect_clock_prescaler_t faultPrescaler; /*!< Fault detect clock prescaler. */ |
kadonotakashi | 0:8fdf9a60065b | 267 | slcd_fault_detect_sample_window_width_t width; /*!< Fault detect sample window width. */ |
kadonotakashi | 0:8fdf9a60065b | 268 | } slcd_fault_detect_config_t; |
kadonotakashi | 0:8fdf9a60065b | 269 | |
kadonotakashi | 0:8fdf9a60065b | 270 | /*! @brief SLCD clock configure structure. */ |
kadonotakashi | 0:8fdf9a60065b | 271 | typedef struct _slcd_clock_config |
kadonotakashi | 0:8fdf9a60065b | 272 | { |
kadonotakashi | 0:8fdf9a60065b | 273 | slcd_clock_src_t clkSource; /*!< Clock source. "slcd_clock_src_t" is recommended to be used. |
kadonotakashi | 0:8fdf9a60065b | 274 | The SLCD is optimized to operate using a 32.768kHz clock input. */ |
kadonotakashi | 0:8fdf9a60065b | 275 | slcd_alt_clock_div_t |
kadonotakashi | 0:8fdf9a60065b | 276 | altClkDivider; /*!< The divider to divide the alternate clock used for alternate clock source. */ |
kadonotakashi | 0:8fdf9a60065b | 277 | slcd_clock_prescaler_t clkPrescaler; /*!< Clock prescaler. */ |
kadonotakashi | 0:8fdf9a60065b | 278 | #if FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE |
kadonotakashi | 0:8fdf9a60065b | 279 | bool fastFrameRateEnable; /*!< Fast frame rate enable flag. */ |
kadonotakashi | 0:8fdf9a60065b | 280 | #endif /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */ |
kadonotakashi | 0:8fdf9a60065b | 281 | } slcd_clock_config_t; |
kadonotakashi | 0:8fdf9a60065b | 282 | |
kadonotakashi | 0:8fdf9a60065b | 283 | /*! @brief SLCD configure structure. */ |
kadonotakashi | 0:8fdf9a60065b | 284 | typedef struct _slcd_config |
kadonotakashi | 0:8fdf9a60065b | 285 | { |
kadonotakashi | 0:8fdf9a60065b | 286 | slcd_power_supply_option_t powerSupply; /*!< Power supply option. */ |
kadonotakashi | 0:8fdf9a60065b | 287 | slcd_regulated_voltage_trim_t voltageTrim; /*!< Regulated voltage trim used for the internal regulator VIREG to |
kadonotakashi | 0:8fdf9a60065b | 288 | adjust to facilitate contrast control. */ |
kadonotakashi | 0:8fdf9a60065b | 289 | slcd_clock_config_t *clkConfig; /*!< Clock configure. */ |
kadonotakashi | 0:8fdf9a60065b | 290 | slcd_display_mode_t displayMode; /*!< SLCD display mode. */ |
kadonotakashi | 0:8fdf9a60065b | 291 | slcd_load_adjust_t loadAdjust; /*!< Load adjust to handle glass capacitance. */ |
kadonotakashi | 0:8fdf9a60065b | 292 | slcd_duty_cycle_t dutyCycle; /*!< Duty cycle. */ |
kadonotakashi | 0:8fdf9a60065b | 293 | slcd_lowpower_behavior lowPowerBehavior; /*!< SLCD behavior in low power mode. */ |
kadonotakashi | 0:8fdf9a60065b | 294 | #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT |
kadonotakashi | 0:8fdf9a60065b | 295 | bool frameFreqIntEnable; /*!< Frame frequency interrupt enable flag.*/ |
kadonotakashi | 0:8fdf9a60065b | 296 | #endif /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */ |
kadonotakashi | 0:8fdf9a60065b | 297 | uint32_t slcdLowPinEnabled; /*!< Setting enabled SLCD pin 0 ~ pin 31. Setting bit n to 1 means enable pin n. */ |
kadonotakashi | 0:8fdf9a60065b | 298 | uint32_t |
kadonotakashi | 0:8fdf9a60065b | 299 | slcdHighPinEnabled; /*!< Setting enabled SLCD pin 32 ~ pin 63. Setting bit n to 1 means enable pin (n + 32). */ |
kadonotakashi | 0:8fdf9a60065b | 300 | uint32_t backPlaneLowPin; /*!< Setting back plane pin 0 ~ pin 31. Setting bit n to 1 means setting pin n as back |
kadonotakashi | 0:8fdf9a60065b | 301 | plane. It should never have the same bit setting as the frontPlane Pin. */ |
kadonotakashi | 0:8fdf9a60065b | 302 | uint32_t backPlaneHighPin; /*!< Setting back plane pin 32 ~ pin 63. Setting bit n to 1 means setting pin (n + 32) as |
kadonotakashi | 0:8fdf9a60065b | 303 | back plane. It should never have the same bit setting as the frontPlane Pin. */ |
kadonotakashi | 0:8fdf9a60065b | 304 | slcd_fault_detect_config_t *faultConfig; /*!< Fault frame detection configure. If not requirement, set to NULL. */ |
kadonotakashi | 0:8fdf9a60065b | 305 | } slcd_config_t; |
kadonotakashi | 0:8fdf9a60065b | 306 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 307 | * API |
kadonotakashi | 0:8fdf9a60065b | 308 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 309 | |
kadonotakashi | 0:8fdf9a60065b | 310 | #if defined(__cplusplus) |
kadonotakashi | 0:8fdf9a60065b | 311 | extern "C" { |
kadonotakashi | 0:8fdf9a60065b | 312 | #endif /* __cplusplus*/ |
kadonotakashi | 0:8fdf9a60065b | 313 | |
kadonotakashi | 0:8fdf9a60065b | 314 | /*! |
kadonotakashi | 0:8fdf9a60065b | 315 | * @name Initialization and deinitialization |
kadonotakashi | 0:8fdf9a60065b | 316 | * @{ |
kadonotakashi | 0:8fdf9a60065b | 317 | */ |
kadonotakashi | 0:8fdf9a60065b | 318 | |
kadonotakashi | 0:8fdf9a60065b | 319 | /*! |
kadonotakashi | 0:8fdf9a60065b | 320 | * @brief Initializes the SLCD, ungates the module clock, initializes the power |
kadonotakashi | 0:8fdf9a60065b | 321 | * setting, enables all used plane pins, and sets with interrupt and work mode |
kadonotakashi | 0:8fdf9a60065b | 322 | * with configuration. |
kadonotakashi | 0:8fdf9a60065b | 323 | * |
kadonotakashi | 0:8fdf9a60065b | 324 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 325 | * @param configure SLCD configuration pointer. |
kadonotakashi | 0:8fdf9a60065b | 326 | * For the configuration structure, many parameters have the default setting |
kadonotakashi | 0:8fdf9a60065b | 327 | * and the SLCD_Getdefaultconfig() is provided to get them. Use it |
kadonotakashi | 0:8fdf9a60065b | 328 | * verified for their applications. |
kadonotakashi | 0:8fdf9a60065b | 329 | * The others have no default settings such as "clkConfig" and must be provided |
kadonotakashi | 0:8fdf9a60065b | 330 | * by the application before calling the SLCD_Init() API. |
kadonotakashi | 0:8fdf9a60065b | 331 | */ |
kadonotakashi | 0:8fdf9a60065b | 332 | void SLCD_Init(LCD_Type *base, slcd_config_t *configure); |
kadonotakashi | 0:8fdf9a60065b | 333 | |
kadonotakashi | 0:8fdf9a60065b | 334 | /*! |
kadonotakashi | 0:8fdf9a60065b | 335 | * @brief Deinitializes the SLCD module, gates the module clock, disables an interrupt, |
kadonotakashi | 0:8fdf9a60065b | 336 | * and displays the SLCD. |
kadonotakashi | 0:8fdf9a60065b | 337 | * |
kadonotakashi | 0:8fdf9a60065b | 338 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 339 | */ |
kadonotakashi | 0:8fdf9a60065b | 340 | void SLCD_Deinit(LCD_Type *base); |
kadonotakashi | 0:8fdf9a60065b | 341 | |
kadonotakashi | 0:8fdf9a60065b | 342 | /*! |
kadonotakashi | 0:8fdf9a60065b | 343 | * @brief Gets the SLCD default configuration structure. The |
kadonotakashi | 0:8fdf9a60065b | 344 | * purpose of this API is to get default parameters of the configuration structure |
kadonotakashi | 0:8fdf9a60065b | 345 | * for the SLCD_Init(). Use these initialized parameters unchanged in SLCD_Init(), |
kadonotakashi | 0:8fdf9a60065b | 346 | * or modify some fields of the structure before the calling SLCD_Init(). |
kadonotakashi | 0:8fdf9a60065b | 347 | * All default parameters of the configure structure are listed: |
kadonotakashi | 0:8fdf9a60065b | 348 | * @code |
kadonotakashi | 0:8fdf9a60065b | 349 | config.displayMode = kSLCD_NormalMode; // SLCD normal mode |
kadonotakashi | 0:8fdf9a60065b | 350 | config.powerSupply = kSLCD_InternalVll3UseChargePump; // Use charge pump internal VLL3 |
kadonotakashi | 0:8fdf9a60065b | 351 | config.voltageTrim = kSLCD_RegulatedVolatgeTrim00; |
kadonotakashi | 0:8fdf9a60065b | 352 | config.lowPowerBehavior = kSLCD_EnabledInWaitStop; // Work on low power mode |
kadonotakashi | 0:8fdf9a60065b | 353 | config.interruptSrc = 0; // No interrupt source is enabled |
kadonotakashi | 0:8fdf9a60065b | 354 | config.faultConfig = NULL; // Fault detection is disabled |
kadonotakashi | 0:8fdf9a60065b | 355 | config.frameFreqIntEnable = false; |
kadonotakashi | 0:8fdf9a60065b | 356 | @endcode |
kadonotakashi | 0:8fdf9a60065b | 357 | * @param configure The SLCD configuration structure pointer. |
kadonotakashi | 0:8fdf9a60065b | 358 | */ |
kadonotakashi | 0:8fdf9a60065b | 359 | void SLCD_GetDefaultConfig(slcd_config_t *configure); |
kadonotakashi | 0:8fdf9a60065b | 360 | |
kadonotakashi | 0:8fdf9a60065b | 361 | /* @}*/ |
kadonotakashi | 0:8fdf9a60065b | 362 | |
kadonotakashi | 0:8fdf9a60065b | 363 | /*! |
kadonotakashi | 0:8fdf9a60065b | 364 | * @name Plane Setting and Display Control |
kadonotakashi | 0:8fdf9a60065b | 365 | * @{ |
kadonotakashi | 0:8fdf9a60065b | 366 | */ |
kadonotakashi | 0:8fdf9a60065b | 367 | |
kadonotakashi | 0:8fdf9a60065b | 368 | /*! |
kadonotakashi | 0:8fdf9a60065b | 369 | * @brief Enables the SLCD controller, starts generate, and displays the front plane and back plane waveform. |
kadonotakashi | 0:8fdf9a60065b | 370 | * |
kadonotakashi | 0:8fdf9a60065b | 371 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 372 | */ |
kadonotakashi | 0:8fdf9a60065b | 373 | static inline void SLCD_StartDisplay(LCD_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 374 | { |
kadonotakashi | 0:8fdf9a60065b | 375 | base->GCR |= LCD_GCR_LCDEN_MASK; |
kadonotakashi | 0:8fdf9a60065b | 376 | } |
kadonotakashi | 0:8fdf9a60065b | 377 | |
kadonotakashi | 0:8fdf9a60065b | 378 | /*! |
kadonotakashi | 0:8fdf9a60065b | 379 | * @brief Stops the SLCD controller. There is no waveform generator and all enabled pins |
kadonotakashi | 0:8fdf9a60065b | 380 | * only output a low value. |
kadonotakashi | 0:8fdf9a60065b | 381 | * |
kadonotakashi | 0:8fdf9a60065b | 382 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 383 | */ |
kadonotakashi | 0:8fdf9a60065b | 384 | static inline void SLCD_StopDisplay(LCD_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 385 | { |
kadonotakashi | 0:8fdf9a60065b | 386 | base->GCR &= ~LCD_GCR_LCDEN_MASK; |
kadonotakashi | 0:8fdf9a60065b | 387 | } |
kadonotakashi | 0:8fdf9a60065b | 388 | |
kadonotakashi | 0:8fdf9a60065b | 389 | /*! |
kadonotakashi | 0:8fdf9a60065b | 390 | * @brief Starts the SLCD blink mode. |
kadonotakashi | 0:8fdf9a60065b | 391 | * |
kadonotakashi | 0:8fdf9a60065b | 392 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 393 | * @param mode SLCD blink mode. |
kadonotakashi | 0:8fdf9a60065b | 394 | * @param rate SLCD blink rate. |
kadonotakashi | 0:8fdf9a60065b | 395 | */ |
kadonotakashi | 0:8fdf9a60065b | 396 | void SLCD_StartBlinkMode(LCD_Type *base, slcd_blink_mode_t mode, slcd_blink_rate_t rate); |
kadonotakashi | 0:8fdf9a60065b | 397 | |
kadonotakashi | 0:8fdf9a60065b | 398 | /*! |
kadonotakashi | 0:8fdf9a60065b | 399 | * @brief Stops the SLCD blink mode. |
kadonotakashi | 0:8fdf9a60065b | 400 | * |
kadonotakashi | 0:8fdf9a60065b | 401 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 402 | */ |
kadonotakashi | 0:8fdf9a60065b | 403 | static inline void SLCD_StopBlinkMode(LCD_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 404 | { |
kadonotakashi | 0:8fdf9a60065b | 405 | base->AR &= ~LCD_AR_BLINK_MASK; |
kadonotakashi | 0:8fdf9a60065b | 406 | } |
kadonotakashi | 0:8fdf9a60065b | 407 | |
kadonotakashi | 0:8fdf9a60065b | 408 | /*! |
kadonotakashi | 0:8fdf9a60065b | 409 | * @brief Sets the SLCD back plane pin phase. |
kadonotakashi | 0:8fdf9a60065b | 410 | * |
kadonotakashi | 0:8fdf9a60065b | 411 | * This function sets the SLCD back plane pin phase. "kSLCD_PhaseXActivate" setting |
kadonotakashi | 0:8fdf9a60065b | 412 | * means the phase X is active for the back plane pin. "kSLCD_NoPhaseActivate" setting |
kadonotakashi | 0:8fdf9a60065b | 413 | * means there is no phase active for the back plane pin. |
kadonotakashi | 0:8fdf9a60065b | 414 | * register value. |
kadonotakashi | 0:8fdf9a60065b | 415 | * For example, set the back plane pin 20 for phase A: |
kadonotakashi | 0:8fdf9a60065b | 416 | * @code |
kadonotakashi | 0:8fdf9a60065b | 417 | * SLCD_SetBackPlanePhase(LCD, 20, kSLCD_PhaseAActivate); |
kadonotakashi | 0:8fdf9a60065b | 418 | * @endcode |
kadonotakashi | 0:8fdf9a60065b | 419 | * |
kadonotakashi | 0:8fdf9a60065b | 420 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 421 | * @param pinIndx SLCD back plane pin index. Range from 0 to 63. |
kadonotakashi | 0:8fdf9a60065b | 422 | * @param phase The phase activates for the back plane pin. |
kadonotakashi | 0:8fdf9a60065b | 423 | */ |
kadonotakashi | 0:8fdf9a60065b | 424 | static inline void SLCD_SetBackPlanePhase(LCD_Type *base, uint32_t pinIndx, slcd_phase_type_t phase) |
kadonotakashi | 0:8fdf9a60065b | 425 | { |
kadonotakashi | 0:8fdf9a60065b | 426 | base->WF8B[pinIndx] = phase; |
kadonotakashi | 0:8fdf9a60065b | 427 | } |
kadonotakashi | 0:8fdf9a60065b | 428 | |
kadonotakashi | 0:8fdf9a60065b | 429 | /*! |
kadonotakashi | 0:8fdf9a60065b | 430 | * @brief Sets the SLCD front plane segment operation for a front plane pin. |
kadonotakashi | 0:8fdf9a60065b | 431 | * |
kadonotakashi | 0:8fdf9a60065b | 432 | * This function sets the SLCD front plane segment on or off operation. |
kadonotakashi | 0:8fdf9a60065b | 433 | * Each bit turns on or off the segments associated with the front plane pin in |
kadonotakashi | 0:8fdf9a60065b | 434 | * the following pattern: HGFEDCBA (most significant bit controls segment H and |
kadonotakashi | 0:8fdf9a60065b | 435 | * least significant bit controls segment A). |
kadonotakashi | 0:8fdf9a60065b | 436 | * For example, turn on the front plane pin 20 for phase B and phase C: |
kadonotakashi | 0:8fdf9a60065b | 437 | * @code |
kadonotakashi | 0:8fdf9a60065b | 438 | * SLCD_SetFrontPlaneSegments(LCD, 20, (kSLCD_PhaseBActivate | kSLCD_PhaseCActivate)); |
kadonotakashi | 0:8fdf9a60065b | 439 | * @endcode |
kadonotakashi | 0:8fdf9a60065b | 440 | * |
kadonotakashi | 0:8fdf9a60065b | 441 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 442 | * @param pinIndx SLCD back plane pin index. Range from 0 to 63. |
kadonotakashi | 0:8fdf9a60065b | 443 | * @param operation The operation for the segment on the front plane pin. |
kadonotakashi | 0:8fdf9a60065b | 444 | * This is a logical OR of the enumeration :: slcd_phase_type_t. |
kadonotakashi | 0:8fdf9a60065b | 445 | */ |
kadonotakashi | 0:8fdf9a60065b | 446 | static inline void SLCD_SetFrontPlaneSegments(LCD_Type *base, uint32_t pinIndx, uint8_t operation) |
kadonotakashi | 0:8fdf9a60065b | 447 | { |
kadonotakashi | 0:8fdf9a60065b | 448 | base->WF8B[pinIndx] = operation; |
kadonotakashi | 0:8fdf9a60065b | 449 | } |
kadonotakashi | 0:8fdf9a60065b | 450 | |
kadonotakashi | 0:8fdf9a60065b | 451 | /*! |
kadonotakashi | 0:8fdf9a60065b | 452 | * @brief Sets one SLCD front plane pin for one phase. |
kadonotakashi | 0:8fdf9a60065b | 453 | * |
kadonotakashi | 0:8fdf9a60065b | 454 | * This function can be used to set one phase on or off for the front plane pin. |
kadonotakashi | 0:8fdf9a60065b | 455 | * It can be call many times to set the plane pin for different phase indexes. |
kadonotakashi | 0:8fdf9a60065b | 456 | * For example, turn on the front plane pin 20 for phase B and phase C: |
kadonotakashi | 0:8fdf9a60065b | 457 | * @code |
kadonotakashi | 0:8fdf9a60065b | 458 | * SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseBIndex, true); |
kadonotakashi | 0:8fdf9a60065b | 459 | * SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseCIndex, true); |
kadonotakashi | 0:8fdf9a60065b | 460 | * @endcode |
kadonotakashi | 0:8fdf9a60065b | 461 | * |
kadonotakashi | 0:8fdf9a60065b | 462 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 463 | * @param pinIndx SLCD back plane pin index. Range from 0 to 63. |
kadonotakashi | 0:8fdf9a60065b | 464 | * @param phaseIndx The phase bit index @ref slcd_phase_index_t. |
kadonotakashi | 0:8fdf9a60065b | 465 | * @param enable True to turn on the segment for phaseIndx phase |
kadonotakashi | 0:8fdf9a60065b | 466 | * false to turn off the segment for phaseIndx phase. |
kadonotakashi | 0:8fdf9a60065b | 467 | */ |
kadonotakashi | 0:8fdf9a60065b | 468 | static inline void SLCD_SetFrontPlaneOnePhase(LCD_Type *base, |
kadonotakashi | 0:8fdf9a60065b | 469 | uint32_t pinIndx, |
kadonotakashi | 0:8fdf9a60065b | 470 | slcd_phase_index_t phaseIndx, |
kadonotakashi | 0:8fdf9a60065b | 471 | bool enable) |
kadonotakashi | 0:8fdf9a60065b | 472 | { |
kadonotakashi | 0:8fdf9a60065b | 473 | uint8_t reg = base->WF8B[pinIndx]; |
kadonotakashi | 0:8fdf9a60065b | 474 | |
kadonotakashi | 0:8fdf9a60065b | 475 | if (enable) |
kadonotakashi | 0:8fdf9a60065b | 476 | { |
kadonotakashi | 0:8fdf9a60065b | 477 | base->WF8B[pinIndx] = (reg | (1U << phaseIndx)); |
kadonotakashi | 0:8fdf9a60065b | 478 | } |
kadonotakashi | 0:8fdf9a60065b | 479 | else |
kadonotakashi | 0:8fdf9a60065b | 480 | { |
kadonotakashi | 0:8fdf9a60065b | 481 | base->WF8B[pinIndx] = (reg & ~(1U << phaseIndx)); |
kadonotakashi | 0:8fdf9a60065b | 482 | } |
kadonotakashi | 0:8fdf9a60065b | 483 | } |
kadonotakashi | 0:8fdf9a60065b | 484 | |
kadonotakashi | 0:8fdf9a60065b | 485 | #if FSL_FEATURE_SLCD_HAS_PAD_SAFE |
kadonotakashi | 0:8fdf9a60065b | 486 | /*! |
kadonotakashi | 0:8fdf9a60065b | 487 | * @brief Enables/disables the SLCD pad safe state. |
kadonotakashi | 0:8fdf9a60065b | 488 | * |
kadonotakashi | 0:8fdf9a60065b | 489 | * Forces the safe state on the LCD pad controls. All LCD front plane |
kadonotakashi | 0:8fdf9a60065b | 490 | * and backplane functions are disabled. |
kadonotakashi | 0:8fdf9a60065b | 491 | * |
kadonotakashi | 0:8fdf9a60065b | 492 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 493 | * @param enable True enable, false disable. |
kadonotakashi | 0:8fdf9a60065b | 494 | */ |
kadonotakashi | 0:8fdf9a60065b | 495 | static inline void SLCD_EnablePadSafeState(LCD_Type *base, bool enable) |
kadonotakashi | 0:8fdf9a60065b | 496 | { |
kadonotakashi | 0:8fdf9a60065b | 497 | if (enable) |
kadonotakashi | 0:8fdf9a60065b | 498 | { /* Enable. */ |
kadonotakashi | 0:8fdf9a60065b | 499 | base->GCR |= LCD_GCR_PADSAFE_MASK; |
kadonotakashi | 0:8fdf9a60065b | 500 | } |
kadonotakashi | 0:8fdf9a60065b | 501 | else |
kadonotakashi | 0:8fdf9a60065b | 502 | { /* Disable. */ |
kadonotakashi | 0:8fdf9a60065b | 503 | base->GCR &= ~LCD_GCR_PADSAFE_MASK; |
kadonotakashi | 0:8fdf9a60065b | 504 | } |
kadonotakashi | 0:8fdf9a60065b | 505 | } |
kadonotakashi | 0:8fdf9a60065b | 506 | #endif /* FSL_FEATURE_SLCD_HAS_PAD_SAFE */ |
kadonotakashi | 0:8fdf9a60065b | 507 | |
kadonotakashi | 0:8fdf9a60065b | 508 | /*! |
kadonotakashi | 0:8fdf9a60065b | 509 | * @brief Gets the SLCD fault detect counter. |
kadonotakashi | 0:8fdf9a60065b | 510 | * |
kadonotakashi | 0:8fdf9a60065b | 511 | * This function gets the number of samples inside the |
kadonotakashi | 0:8fdf9a60065b | 512 | * fault detection sample window. |
kadonotakashi | 0:8fdf9a60065b | 513 | * |
kadonotakashi | 0:8fdf9a60065b | 514 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 515 | * @return The fault detect counter. The maximum return value is 255. |
kadonotakashi | 0:8fdf9a60065b | 516 | * If the maximum 255 returns, the overflow may happen. |
kadonotakashi | 0:8fdf9a60065b | 517 | * Reconfigure the fault detect sample window and fault detect clock prescaler |
kadonotakashi | 0:8fdf9a60065b | 518 | * for proper sampling. |
kadonotakashi | 0:8fdf9a60065b | 519 | */ |
kadonotakashi | 0:8fdf9a60065b | 520 | static inline uint32_t SLCD_GetFaultDetectCounter(LCD_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 521 | { |
kadonotakashi | 0:8fdf9a60065b | 522 | return base->FDSR & LCD_FDSR_FDCNT_MASK; |
kadonotakashi | 0:8fdf9a60065b | 523 | } |
kadonotakashi | 0:8fdf9a60065b | 524 | |
kadonotakashi | 0:8fdf9a60065b | 525 | /* @} */ |
kadonotakashi | 0:8fdf9a60065b | 526 | |
kadonotakashi | 0:8fdf9a60065b | 527 | /*! |
kadonotakashi | 0:8fdf9a60065b | 528 | * @name Interrupts. |
kadonotakashi | 0:8fdf9a60065b | 529 | * @{ |
kadonotakashi | 0:8fdf9a60065b | 530 | */ |
kadonotakashi | 0:8fdf9a60065b | 531 | |
kadonotakashi | 0:8fdf9a60065b | 532 | /*! |
kadonotakashi | 0:8fdf9a60065b | 533 | * @brief Enables the SLCD interrupt. |
kadonotakashi | 0:8fdf9a60065b | 534 | * For example, to enable fault detect complete interrupt and frame frequency interrupt, |
kadonotakashi | 0:8fdf9a60065b | 535 | * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following. |
kadonotakashi | 0:8fdf9a60065b | 536 | * @code |
kadonotakashi | 0:8fdf9a60065b | 537 | * SLCD_EnableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt); |
kadonotakashi | 0:8fdf9a60065b | 538 | * @endcode |
kadonotakashi | 0:8fdf9a60065b | 539 | * |
kadonotakashi | 0:8fdf9a60065b | 540 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 541 | * @param mask SLCD interrupts to enable. This is a logical OR of the |
kadonotakashi | 0:8fdf9a60065b | 542 | * enumeration :: slcd_interrupt_enable_t. |
kadonotakashi | 0:8fdf9a60065b | 543 | */ |
kadonotakashi | 0:8fdf9a60065b | 544 | void SLCD_EnableInterrupts(LCD_Type *base, uint32_t mask); |
kadonotakashi | 0:8fdf9a60065b | 545 | |
kadonotakashi | 0:8fdf9a60065b | 546 | /*! |
kadonotakashi | 0:8fdf9a60065b | 547 | * @brief Disables the SLCD interrupt. |
kadonotakashi | 0:8fdf9a60065b | 548 | * For example, to disable fault detect complete interrupt and frame frequency interrupt, |
kadonotakashi | 0:8fdf9a60065b | 549 | * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following. |
kadonotakashi | 0:8fdf9a60065b | 550 | * @code |
kadonotakashi | 0:8fdf9a60065b | 551 | * SLCD_DisableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt); |
kadonotakashi | 0:8fdf9a60065b | 552 | * @endcode |
kadonotakashi | 0:8fdf9a60065b | 553 | * |
kadonotakashi | 0:8fdf9a60065b | 554 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 555 | * @param mask SLCD interrupts to disable. This is a logical OR of the |
kadonotakashi | 0:8fdf9a60065b | 556 | * enumeration :: slcd_interrupt_enable_t. |
kadonotakashi | 0:8fdf9a60065b | 557 | */ |
kadonotakashi | 0:8fdf9a60065b | 558 | void SLCD_DisableInterrupts(LCD_Type *base, uint32_t mask); |
kadonotakashi | 0:8fdf9a60065b | 559 | |
kadonotakashi | 0:8fdf9a60065b | 560 | /*! |
kadonotakashi | 0:8fdf9a60065b | 561 | * @brief Gets the SLCD interrupt status flag. |
kadonotakashi | 0:8fdf9a60065b | 562 | * |
kadonotakashi | 0:8fdf9a60065b | 563 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 564 | * @return The event status of the interrupt source. This is the logical OR of members |
kadonotakashi | 0:8fdf9a60065b | 565 | * of the enumeration :: slcd_interrupt_enable_t. |
kadonotakashi | 0:8fdf9a60065b | 566 | */ |
kadonotakashi | 0:8fdf9a60065b | 567 | uint32_t SLCD_GetInterruptStatus(LCD_Type *base); |
kadonotakashi | 0:8fdf9a60065b | 568 | |
kadonotakashi | 0:8fdf9a60065b | 569 | /*! |
kadonotakashi | 0:8fdf9a60065b | 570 | * @brief Clears the SLCD interrupt events status flag. |
kadonotakashi | 0:8fdf9a60065b | 571 | * |
kadonotakashi | 0:8fdf9a60065b | 572 | * @param base SLCD peripheral base address. |
kadonotakashi | 0:8fdf9a60065b | 573 | * @param mask SLCD interrupt source to be cleared. |
kadonotakashi | 0:8fdf9a60065b | 574 | * This is the logical OR of members of the enumeration :: slcd_interrupt_enable_t. |
kadonotakashi | 0:8fdf9a60065b | 575 | */ |
kadonotakashi | 0:8fdf9a60065b | 576 | void SLCD_ClearInterruptStatus(LCD_Type *base, uint32_t mask); |
kadonotakashi | 0:8fdf9a60065b | 577 | |
kadonotakashi | 0:8fdf9a60065b | 578 | /* @} */ |
kadonotakashi | 0:8fdf9a60065b | 579 | |
kadonotakashi | 0:8fdf9a60065b | 580 | #if defined(__cplusplus) |
kadonotakashi | 0:8fdf9a60065b | 581 | } |
kadonotakashi | 0:8fdf9a60065b | 582 | #endif /* __cplusplus*/ |
kadonotakashi | 0:8fdf9a60065b | 583 | |
kadonotakashi | 0:8fdf9a60065b | 584 | /*! @}*/ |
kadonotakashi | 0:8fdf9a60065b | 585 | |
kadonotakashi | 0:8fdf9a60065b | 586 | #endif /* _FSL_SLCD_H_*/ |