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mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_port.h@0:8fdf9a60065b, 2018-10-10 (annotated)
- Committer:
- kadonotakashi
- Date:
- Wed Oct 10 00:33:53 2018 +0000
- Revision:
- 0:8fdf9a60065b
how to make mbed librry
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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kadonotakashi | 0:8fdf9a60065b | 1 | /* |
kadonotakashi | 0:8fdf9a60065b | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
kadonotakashi | 0:8fdf9a60065b | 3 | * All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 4 | * |
kadonotakashi | 0:8fdf9a60065b | 5 | * Redistribution and use in source and binary forms, with or without modification, |
kadonotakashi | 0:8fdf9a60065b | 6 | * are permitted provided that the following conditions are met: |
kadonotakashi | 0:8fdf9a60065b | 7 | * |
kadonotakashi | 0:8fdf9a60065b | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
kadonotakashi | 0:8fdf9a60065b | 9 | * of conditions and the following disclaimer. |
kadonotakashi | 0:8fdf9a60065b | 10 | * |
kadonotakashi | 0:8fdf9a60065b | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
kadonotakashi | 0:8fdf9a60065b | 12 | * list of conditions and the following disclaimer in the documentation and/or |
kadonotakashi | 0:8fdf9a60065b | 13 | * other materials provided with the distribution. |
kadonotakashi | 0:8fdf9a60065b | 14 | * |
kadonotakashi | 0:8fdf9a60065b | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
kadonotakashi | 0:8fdf9a60065b | 16 | * contributors may be used to endorse or promote products derived from this |
kadonotakashi | 0:8fdf9a60065b | 17 | * software without specific prior written permission. |
kadonotakashi | 0:8fdf9a60065b | 18 | * |
kadonotakashi | 0:8fdf9a60065b | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
kadonotakashi | 0:8fdf9a60065b | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
kadonotakashi | 0:8fdf9a60065b | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
kadonotakashi | 0:8fdf9a60065b | 22 | * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
kadonotakashi | 0:8fdf9a60065b | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
kadonotakashi | 0:8fdf9a60065b | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
kadonotakashi | 0:8fdf9a60065b | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
kadonotakashi | 0:8fdf9a60065b | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
kadonotakashi | 0:8fdf9a60065b | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
kadonotakashi | 0:8fdf9a60065b | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
kadonotakashi | 0:8fdf9a60065b | 29 | */ |
kadonotakashi | 0:8fdf9a60065b | 30 | #ifndef _FSL_PORT_H_ |
kadonotakashi | 0:8fdf9a60065b | 31 | #define _FSL_PORT_H_ |
kadonotakashi | 0:8fdf9a60065b | 32 | |
kadonotakashi | 0:8fdf9a60065b | 33 | #include "fsl_common.h" |
kadonotakashi | 0:8fdf9a60065b | 34 | |
kadonotakashi | 0:8fdf9a60065b | 35 | /*! |
kadonotakashi | 0:8fdf9a60065b | 36 | * @addtogroup port_driver |
kadonotakashi | 0:8fdf9a60065b | 37 | * @{ |
kadonotakashi | 0:8fdf9a60065b | 38 | */ |
kadonotakashi | 0:8fdf9a60065b | 39 | |
kadonotakashi | 0:8fdf9a60065b | 40 | /*! @file */ |
kadonotakashi | 0:8fdf9a60065b | 41 | |
kadonotakashi | 0:8fdf9a60065b | 42 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 43 | * Definitions |
kadonotakashi | 0:8fdf9a60065b | 44 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 45 | |
kadonotakashi | 0:8fdf9a60065b | 46 | /*! @name Driver version */ |
kadonotakashi | 0:8fdf9a60065b | 47 | /*@{*/ |
kadonotakashi | 0:8fdf9a60065b | 48 | /*! Version 2.0.1. */ |
kadonotakashi | 0:8fdf9a60065b | 49 | #define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) |
kadonotakashi | 0:8fdf9a60065b | 50 | /*@}*/ |
kadonotakashi | 0:8fdf9a60065b | 51 | |
kadonotakashi | 0:8fdf9a60065b | 52 | /*! @brief Internal resistor pull feature selection */ |
kadonotakashi | 0:8fdf9a60065b | 53 | enum _port_pull |
kadonotakashi | 0:8fdf9a60065b | 54 | { |
kadonotakashi | 0:8fdf9a60065b | 55 | kPORT_PullDisable = 0U, /*!< internal pull-up/down resistor is disabled. */ |
kadonotakashi | 0:8fdf9a60065b | 56 | kPORT_PullDown = 2U, /*!< internal pull-down resistor is enabled. */ |
kadonotakashi | 0:8fdf9a60065b | 57 | kPORT_PullUp = 3U, /*!< internal pull-up resistor is enabled. */ |
kadonotakashi | 0:8fdf9a60065b | 58 | }; |
kadonotakashi | 0:8fdf9a60065b | 59 | |
kadonotakashi | 0:8fdf9a60065b | 60 | /*! @brief Slew rate selection */ |
kadonotakashi | 0:8fdf9a60065b | 61 | enum _port_slew_rate |
kadonotakashi | 0:8fdf9a60065b | 62 | { |
kadonotakashi | 0:8fdf9a60065b | 63 | kPORT_FastSlewRate = 0U, /*!< fast slew rate is configured. */ |
kadonotakashi | 0:8fdf9a60065b | 64 | kPORT_SlowSlewRate = 1U, /*!< slow slew rate is configured. */ |
kadonotakashi | 0:8fdf9a60065b | 65 | }; |
kadonotakashi | 0:8fdf9a60065b | 66 | |
kadonotakashi | 0:8fdf9a60065b | 67 | #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN |
kadonotakashi | 0:8fdf9a60065b | 68 | /*! @brief Internal resistor pull feature enable/disable */ |
kadonotakashi | 0:8fdf9a60065b | 69 | enum _port_open_drain_enable |
kadonotakashi | 0:8fdf9a60065b | 70 | { |
kadonotakashi | 0:8fdf9a60065b | 71 | kPORT_OpenDrainDisable = 0U, /*!< internal pull-down resistor is disabled. */ |
kadonotakashi | 0:8fdf9a60065b | 72 | kPORT_OpenDrainEnable = 1U, /*!< internal pull-up resistor is enabled. */ |
kadonotakashi | 0:8fdf9a60065b | 73 | }; |
kadonotakashi | 0:8fdf9a60065b | 74 | #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ |
kadonotakashi | 0:8fdf9a60065b | 75 | |
kadonotakashi | 0:8fdf9a60065b | 76 | /*! @brief Passive filter feature enable/disable */ |
kadonotakashi | 0:8fdf9a60065b | 77 | enum _port_passive_filter_enable |
kadonotakashi | 0:8fdf9a60065b | 78 | { |
kadonotakashi | 0:8fdf9a60065b | 79 | kPORT_PassiveFilterDisable = 0U, /*!< fast slew rate is configured. */ |
kadonotakashi | 0:8fdf9a60065b | 80 | kPORT_PassiveFilterEnable = 1U, /*!< slow slew rate is configured. */ |
kadonotakashi | 0:8fdf9a60065b | 81 | }; |
kadonotakashi | 0:8fdf9a60065b | 82 | |
kadonotakashi | 0:8fdf9a60065b | 83 | /*! @brief Configures the drive strength. */ |
kadonotakashi | 0:8fdf9a60065b | 84 | enum _port_drive_strength |
kadonotakashi | 0:8fdf9a60065b | 85 | { |
kadonotakashi | 0:8fdf9a60065b | 86 | kPORT_LowDriveStrength = 0U, /*!< low drive strength is configured. */ |
kadonotakashi | 0:8fdf9a60065b | 87 | kPORT_HighDriveStrength = 1U, /*!< high drive strength is configured. */ |
kadonotakashi | 0:8fdf9a60065b | 88 | }; |
kadonotakashi | 0:8fdf9a60065b | 89 | |
kadonotakashi | 0:8fdf9a60065b | 90 | #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK |
kadonotakashi | 0:8fdf9a60065b | 91 | /*! @brief Unlock/lock the pin control register field[15:0] */ |
kadonotakashi | 0:8fdf9a60065b | 92 | enum _port_lock_register |
kadonotakashi | 0:8fdf9a60065b | 93 | { |
kadonotakashi | 0:8fdf9a60065b | 94 | kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */ |
kadonotakashi | 0:8fdf9a60065b | 95 | kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */ |
kadonotakashi | 0:8fdf9a60065b | 96 | }; |
kadonotakashi | 0:8fdf9a60065b | 97 | #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ |
kadonotakashi | 0:8fdf9a60065b | 98 | |
kadonotakashi | 0:8fdf9a60065b | 99 | /*! @brief Pin mux selection */ |
kadonotakashi | 0:8fdf9a60065b | 100 | typedef enum _port_mux |
kadonotakashi | 0:8fdf9a60065b | 101 | { |
kadonotakashi | 0:8fdf9a60065b | 102 | kPORT_PinDisabledOrAnalog = 0U, /*!< corresponding pin is disabled, but is used as an analog pin. */ |
kadonotakashi | 0:8fdf9a60065b | 103 | kPORT_MuxAsGpio = 1U, /*!< corresponding pin is configured as GPIO. */ |
kadonotakashi | 0:8fdf9a60065b | 104 | kPORT_MuxAlt2 = 2U, /*!< chip-specific */ |
kadonotakashi | 0:8fdf9a60065b | 105 | kPORT_MuxAlt3 = 3U, /*!< chip-specific */ |
kadonotakashi | 0:8fdf9a60065b | 106 | kPORT_MuxAlt4 = 4U, /*!< chip-specific */ |
kadonotakashi | 0:8fdf9a60065b | 107 | kPORT_MuxAlt5 = 5U, /*!< chip-specific */ |
kadonotakashi | 0:8fdf9a60065b | 108 | kPORT_MuxAlt6 = 6U, /*!< chip-specific */ |
kadonotakashi | 0:8fdf9a60065b | 109 | kPORT_MuxAlt7 = 7U, /*!< chip-specific */ |
kadonotakashi | 0:8fdf9a60065b | 110 | } port_mux_t; |
kadonotakashi | 0:8fdf9a60065b | 111 | |
kadonotakashi | 0:8fdf9a60065b | 112 | /*! @brief Configures the interrupt generation condition. */ |
kadonotakashi | 0:8fdf9a60065b | 113 | typedef enum _port_interrupt |
kadonotakashi | 0:8fdf9a60065b | 114 | { |
kadonotakashi | 0:8fdf9a60065b | 115 | kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ |
kadonotakashi | 0:8fdf9a60065b | 116 | #if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST |
kadonotakashi | 0:8fdf9a60065b | 117 | kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ |
kadonotakashi | 0:8fdf9a60065b | 118 | kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ |
kadonotakashi | 0:8fdf9a60065b | 119 | kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ |
kadonotakashi | 0:8fdf9a60065b | 120 | #endif |
kadonotakashi | 0:8fdf9a60065b | 121 | #if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG |
kadonotakashi | 0:8fdf9a60065b | 122 | kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ |
kadonotakashi | 0:8fdf9a60065b | 123 | kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ |
kadonotakashi | 0:8fdf9a60065b | 124 | kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ |
kadonotakashi | 0:8fdf9a60065b | 125 | #endif |
kadonotakashi | 0:8fdf9a60065b | 126 | kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ |
kadonotakashi | 0:8fdf9a60065b | 127 | kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ |
kadonotakashi | 0:8fdf9a60065b | 128 | kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ |
kadonotakashi | 0:8fdf9a60065b | 129 | kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ |
kadonotakashi | 0:8fdf9a60065b | 130 | kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ |
kadonotakashi | 0:8fdf9a60065b | 131 | #if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER |
kadonotakashi | 0:8fdf9a60065b | 132 | kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high trigger output. */ |
kadonotakashi | 0:8fdf9a60065b | 133 | kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low trigger output. */ |
kadonotakashi | 0:8fdf9a60065b | 134 | #endif |
kadonotakashi | 0:8fdf9a60065b | 135 | } port_interrupt_t; |
kadonotakashi | 0:8fdf9a60065b | 136 | |
kadonotakashi | 0:8fdf9a60065b | 137 | #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER |
kadonotakashi | 0:8fdf9a60065b | 138 | /*! @brief Digital filter clock source selection */ |
kadonotakashi | 0:8fdf9a60065b | 139 | typedef enum _port_digital_filter_clock_source |
kadonotakashi | 0:8fdf9a60065b | 140 | { |
kadonotakashi | 0:8fdf9a60065b | 141 | kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */ |
kadonotakashi | 0:8fdf9a60065b | 142 | kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */ |
kadonotakashi | 0:8fdf9a60065b | 143 | } port_digital_filter_clock_source_t; |
kadonotakashi | 0:8fdf9a60065b | 144 | |
kadonotakashi | 0:8fdf9a60065b | 145 | /*! @brief PORT digital filter feature configuration definition */ |
kadonotakashi | 0:8fdf9a60065b | 146 | typedef struct _port_digital_filter_config |
kadonotakashi | 0:8fdf9a60065b | 147 | { |
kadonotakashi | 0:8fdf9a60065b | 148 | uint32_t digitalFilterWidth; /*!< Set digital filter width */ |
kadonotakashi | 0:8fdf9a60065b | 149 | port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */ |
kadonotakashi | 0:8fdf9a60065b | 150 | } port_digital_filter_config_t; |
kadonotakashi | 0:8fdf9a60065b | 151 | #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ |
kadonotakashi | 0:8fdf9a60065b | 152 | |
kadonotakashi | 0:8fdf9a60065b | 153 | /*! @brief PORT pin config structure */ |
kadonotakashi | 0:8fdf9a60065b | 154 | typedef struct _port_pin_config |
kadonotakashi | 0:8fdf9a60065b | 155 | { |
kadonotakashi | 0:8fdf9a60065b | 156 | uint16_t pullSelect : 2; /*!< no-pull/pull-down/pull-up select */ |
kadonotakashi | 0:8fdf9a60065b | 157 | uint16_t slewRate : 1; /*!< fast/slow slew rate Configure */ |
kadonotakashi | 0:8fdf9a60065b | 158 | uint16_t : 1; |
kadonotakashi | 0:8fdf9a60065b | 159 | uint16_t passiveFilterEnable : 1; /*!< passive filter enable/disable */ |
kadonotakashi | 0:8fdf9a60065b | 160 | #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN |
kadonotakashi | 0:8fdf9a60065b | 161 | uint16_t openDrainEnable : 1; /*!< open drain enable/disable */ |
kadonotakashi | 0:8fdf9a60065b | 162 | #else |
kadonotakashi | 0:8fdf9a60065b | 163 | uint16_t : 1; |
kadonotakashi | 0:8fdf9a60065b | 164 | #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ |
kadonotakashi | 0:8fdf9a60065b | 165 | uint16_t driveStrength : 1; /*!< fast/slow drive strength configure */ |
kadonotakashi | 0:8fdf9a60065b | 166 | uint16_t : 1; |
kadonotakashi | 0:8fdf9a60065b | 167 | uint16_t mux : 3; /*!< pin mux Configure */ |
kadonotakashi | 0:8fdf9a60065b | 168 | uint16_t : 4; |
kadonotakashi | 0:8fdf9a60065b | 169 | #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK |
kadonotakashi | 0:8fdf9a60065b | 170 | uint16_t lockRegister : 1; /*!< lock/unlock the pcr field[15:0] */ |
kadonotakashi | 0:8fdf9a60065b | 171 | #else |
kadonotakashi | 0:8fdf9a60065b | 172 | uint16_t : 1; |
kadonotakashi | 0:8fdf9a60065b | 173 | #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ |
kadonotakashi | 0:8fdf9a60065b | 174 | } port_pin_config_t; |
kadonotakashi | 0:8fdf9a60065b | 175 | |
kadonotakashi | 0:8fdf9a60065b | 176 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 177 | * API |
kadonotakashi | 0:8fdf9a60065b | 178 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 179 | |
kadonotakashi | 0:8fdf9a60065b | 180 | #if defined(__cplusplus) |
kadonotakashi | 0:8fdf9a60065b | 181 | extern "C" { |
kadonotakashi | 0:8fdf9a60065b | 182 | #endif |
kadonotakashi | 0:8fdf9a60065b | 183 | |
kadonotakashi | 0:8fdf9a60065b | 184 | /*! @name Configuration */ |
kadonotakashi | 0:8fdf9a60065b | 185 | /*@{*/ |
kadonotakashi | 0:8fdf9a60065b | 186 | |
kadonotakashi | 0:8fdf9a60065b | 187 | /*! |
kadonotakashi | 0:8fdf9a60065b | 188 | * @brief Sets the port PCR register. |
kadonotakashi | 0:8fdf9a60065b | 189 | * |
kadonotakashi | 0:8fdf9a60065b | 190 | * This is an example to define an input pin or output pin PCR configuration: |
kadonotakashi | 0:8fdf9a60065b | 191 | * @code |
kadonotakashi | 0:8fdf9a60065b | 192 | * // Define a digital input pin PCR configuration |
kadonotakashi | 0:8fdf9a60065b | 193 | * port_pin_config_t config = { |
kadonotakashi | 0:8fdf9a60065b | 194 | * kPORT_PullUp, |
kadonotakashi | 0:8fdf9a60065b | 195 | * kPORT_FastSlewRate, |
kadonotakashi | 0:8fdf9a60065b | 196 | * kPORT_PassiveFilterDisable, |
kadonotakashi | 0:8fdf9a60065b | 197 | * kPORT_OpenDrainDisable, |
kadonotakashi | 0:8fdf9a60065b | 198 | * kPORT_LowDriveStrength, |
kadonotakashi | 0:8fdf9a60065b | 199 | * kPORT_MuxAsGpio, |
kadonotakashi | 0:8fdf9a60065b | 200 | * kPORT_UnLockRegister, |
kadonotakashi | 0:8fdf9a60065b | 201 | * }; |
kadonotakashi | 0:8fdf9a60065b | 202 | * @endcode |
kadonotakashi | 0:8fdf9a60065b | 203 | * |
kadonotakashi | 0:8fdf9a60065b | 204 | * @param base PORT peripheral base pointer. |
kadonotakashi | 0:8fdf9a60065b | 205 | * @param pin PORT pin number. |
kadonotakashi | 0:8fdf9a60065b | 206 | * @param config PORT PCR register configure structure. |
kadonotakashi | 0:8fdf9a60065b | 207 | */ |
kadonotakashi | 0:8fdf9a60065b | 208 | static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) |
kadonotakashi | 0:8fdf9a60065b | 209 | { |
kadonotakashi | 0:8fdf9a60065b | 210 | assert(config); |
kadonotakashi | 0:8fdf9a60065b | 211 | uint32_t addr = (uint32_t)&base->PCR[pin]; |
kadonotakashi | 0:8fdf9a60065b | 212 | *(volatile uint16_t *)(addr) = *((const uint16_t *)config); |
kadonotakashi | 0:8fdf9a60065b | 213 | } |
kadonotakashi | 0:8fdf9a60065b | 214 | |
kadonotakashi | 0:8fdf9a60065b | 215 | /*! |
kadonotakashi | 0:8fdf9a60065b | 216 | * @brief Sets the port PCR register for multiple pins. |
kadonotakashi | 0:8fdf9a60065b | 217 | * |
kadonotakashi | 0:8fdf9a60065b | 218 | * This is an example to define input pins or output pins PCR configuration: |
kadonotakashi | 0:8fdf9a60065b | 219 | * @code |
kadonotakashi | 0:8fdf9a60065b | 220 | * // Define a digital input pin PCR configuration |
kadonotakashi | 0:8fdf9a60065b | 221 | * port_pin_config_t config = { |
kadonotakashi | 0:8fdf9a60065b | 222 | * kPORT_PullUp , |
kadonotakashi | 0:8fdf9a60065b | 223 | * kPORT_PullEnable, |
kadonotakashi | 0:8fdf9a60065b | 224 | * kPORT_FastSlewRate, |
kadonotakashi | 0:8fdf9a60065b | 225 | * kPORT_PassiveFilterDisable, |
kadonotakashi | 0:8fdf9a60065b | 226 | * kPORT_OpenDrainDisable, |
kadonotakashi | 0:8fdf9a60065b | 227 | * kPORT_LowDriveStrength, |
kadonotakashi | 0:8fdf9a60065b | 228 | * kPORT_MuxAsGpio, |
kadonotakashi | 0:8fdf9a60065b | 229 | * kPORT_UnlockRegister, |
kadonotakashi | 0:8fdf9a60065b | 230 | * }; |
kadonotakashi | 0:8fdf9a60065b | 231 | * @endcode |
kadonotakashi | 0:8fdf9a60065b | 232 | * |
kadonotakashi | 0:8fdf9a60065b | 233 | * @param base PORT peripheral base pointer. |
kadonotakashi | 0:8fdf9a60065b | 234 | * @param mask PORT pins' numbers macro. |
kadonotakashi | 0:8fdf9a60065b | 235 | * @param config PORT PCR register configure structure. |
kadonotakashi | 0:8fdf9a60065b | 236 | */ |
kadonotakashi | 0:8fdf9a60065b | 237 | static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config) |
kadonotakashi | 0:8fdf9a60065b | 238 | { |
kadonotakashi | 0:8fdf9a60065b | 239 | assert(config); |
kadonotakashi | 0:8fdf9a60065b | 240 | |
kadonotakashi | 0:8fdf9a60065b | 241 | uint16_t pcrl = *((const uint16_t *)config); |
kadonotakashi | 0:8fdf9a60065b | 242 | |
kadonotakashi | 0:8fdf9a60065b | 243 | if (mask & 0xffffU) |
kadonotakashi | 0:8fdf9a60065b | 244 | { |
kadonotakashi | 0:8fdf9a60065b | 245 | base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; |
kadonotakashi | 0:8fdf9a60065b | 246 | } |
kadonotakashi | 0:8fdf9a60065b | 247 | if (mask >> 16) |
kadonotakashi | 0:8fdf9a60065b | 248 | { |
kadonotakashi | 0:8fdf9a60065b | 249 | base->GPCHR = (mask & 0xffff0000U) | pcrl; |
kadonotakashi | 0:8fdf9a60065b | 250 | } |
kadonotakashi | 0:8fdf9a60065b | 251 | } |
kadonotakashi | 0:8fdf9a60065b | 252 | |
kadonotakashi | 0:8fdf9a60065b | 253 | /*! |
kadonotakashi | 0:8fdf9a60065b | 254 | * @brief Configures the pin muxing. |
kadonotakashi | 0:8fdf9a60065b | 255 | * |
kadonotakashi | 0:8fdf9a60065b | 256 | * @param base PORT peripheral base pointer. |
kadonotakashi | 0:8fdf9a60065b | 257 | * @param pin PORT pin number. |
kadonotakashi | 0:8fdf9a60065b | 258 | * @param mux pin muxing slot selection. |
kadonotakashi | 0:8fdf9a60065b | 259 | * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function. |
kadonotakashi | 0:8fdf9a60065b | 260 | * - #kPORT_MuxAsGpio : Set as GPIO. |
kadonotakashi | 0:8fdf9a60065b | 261 | * - #kPORT_MuxAlt2 : chip-specific. |
kadonotakashi | 0:8fdf9a60065b | 262 | * - #kPORT_MuxAlt3 : chip-specific. |
kadonotakashi | 0:8fdf9a60065b | 263 | * - #kPORT_MuxAlt4 : chip-specific. |
kadonotakashi | 0:8fdf9a60065b | 264 | * - #kPORT_MuxAlt5 : chip-specific. |
kadonotakashi | 0:8fdf9a60065b | 265 | * - #kPORT_MuxAlt6 : chip-specific. |
kadonotakashi | 0:8fdf9a60065b | 266 | * - #kPORT_MuxAlt7 : chip-specific. |
kadonotakashi | 0:8fdf9a60065b | 267 | * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because |
kadonotakashi | 0:8fdf9a60065b | 268 | * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux will |
kadonotakashi | 0:8fdf9a60065b | 269 | * be reset to zero : kPORT_PinDisabledOrAnalog). |
kadonotakashi | 0:8fdf9a60065b | 270 | * This function is recommended to use in the case you just need to reset the pin mux |
kadonotakashi | 0:8fdf9a60065b | 271 | * |
kadonotakashi | 0:8fdf9a60065b | 272 | */ |
kadonotakashi | 0:8fdf9a60065b | 273 | static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) |
kadonotakashi | 0:8fdf9a60065b | 274 | { |
kadonotakashi | 0:8fdf9a60065b | 275 | base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); |
kadonotakashi | 0:8fdf9a60065b | 276 | } |
kadonotakashi | 0:8fdf9a60065b | 277 | |
kadonotakashi | 0:8fdf9a60065b | 278 | #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER |
kadonotakashi | 0:8fdf9a60065b | 279 | |
kadonotakashi | 0:8fdf9a60065b | 280 | /*! |
kadonotakashi | 0:8fdf9a60065b | 281 | * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin. |
kadonotakashi | 0:8fdf9a60065b | 282 | * |
kadonotakashi | 0:8fdf9a60065b | 283 | * @param base PORT peripheral base pointer. |
kadonotakashi | 0:8fdf9a60065b | 284 | * @param mask PORT pins' numbers macro. |
kadonotakashi | 0:8fdf9a60065b | 285 | */ |
kadonotakashi | 0:8fdf9a60065b | 286 | static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable) |
kadonotakashi | 0:8fdf9a60065b | 287 | { |
kadonotakashi | 0:8fdf9a60065b | 288 | if (enable == true) |
kadonotakashi | 0:8fdf9a60065b | 289 | { |
kadonotakashi | 0:8fdf9a60065b | 290 | base->DFER |= mask; |
kadonotakashi | 0:8fdf9a60065b | 291 | } |
kadonotakashi | 0:8fdf9a60065b | 292 | else |
kadonotakashi | 0:8fdf9a60065b | 293 | { |
kadonotakashi | 0:8fdf9a60065b | 294 | base->DFER &= ~mask; |
kadonotakashi | 0:8fdf9a60065b | 295 | } |
kadonotakashi | 0:8fdf9a60065b | 296 | } |
kadonotakashi | 0:8fdf9a60065b | 297 | |
kadonotakashi | 0:8fdf9a60065b | 298 | /*! |
kadonotakashi | 0:8fdf9a60065b | 299 | * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin. |
kadonotakashi | 0:8fdf9a60065b | 300 | * |
kadonotakashi | 0:8fdf9a60065b | 301 | * @param base PORT peripheral base pointer. |
kadonotakashi | 0:8fdf9a60065b | 302 | * @param config PORT digital filter configuration structure. |
kadonotakashi | 0:8fdf9a60065b | 303 | */ |
kadonotakashi | 0:8fdf9a60065b | 304 | static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config) |
kadonotakashi | 0:8fdf9a60065b | 305 | { |
kadonotakashi | 0:8fdf9a60065b | 306 | assert(config); |
kadonotakashi | 0:8fdf9a60065b | 307 | |
kadonotakashi | 0:8fdf9a60065b | 308 | base->DFCR = PORT_DFCR_CS(config->clockSource); |
kadonotakashi | 0:8fdf9a60065b | 309 | base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth); |
kadonotakashi | 0:8fdf9a60065b | 310 | } |
kadonotakashi | 0:8fdf9a60065b | 311 | |
kadonotakashi | 0:8fdf9a60065b | 312 | #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ |
kadonotakashi | 0:8fdf9a60065b | 313 | |
kadonotakashi | 0:8fdf9a60065b | 314 | /*@}*/ |
kadonotakashi | 0:8fdf9a60065b | 315 | |
kadonotakashi | 0:8fdf9a60065b | 316 | /*! @name Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 317 | /*@{*/ |
kadonotakashi | 0:8fdf9a60065b | 318 | |
kadonotakashi | 0:8fdf9a60065b | 319 | /*! |
kadonotakashi | 0:8fdf9a60065b | 320 | * @brief Configures the port pin interrupt/DMA request. |
kadonotakashi | 0:8fdf9a60065b | 321 | * |
kadonotakashi | 0:8fdf9a60065b | 322 | * @param base PORT peripheral base pointer. |
kadonotakashi | 0:8fdf9a60065b | 323 | * @param pin PORT pin number. |
kadonotakashi | 0:8fdf9a60065b | 324 | * @param config PORT pin interrupt configuration. |
kadonotakashi | 0:8fdf9a60065b | 325 | * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. |
kadonotakashi | 0:8fdf9a60065b | 326 | * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). |
kadonotakashi | 0:8fdf9a60065b | 327 | * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). |
kadonotakashi | 0:8fdf9a60065b | 328 | * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). |
kadonotakashi | 0:8fdf9a60065b | 329 | * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). |
kadonotakashi | 0:8fdf9a60065b | 330 | * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). |
kadonotakashi | 0:8fdf9a60065b | 331 | * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). |
kadonotakashi | 0:8fdf9a60065b | 332 | * - #kPORT_InterruptLogicZero : Interrupt when logic zero. |
kadonotakashi | 0:8fdf9a60065b | 333 | * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. |
kadonotakashi | 0:8fdf9a60065b | 334 | * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. |
kadonotakashi | 0:8fdf9a60065b | 335 | * - #kPORT_InterruptEitherEdge : Interrupt on either edge. |
kadonotakashi | 0:8fdf9a60065b | 336 | * - #kPORT_InterruptLogicOne : Interrupt when logic one. |
kadonotakashi | 0:8fdf9a60065b | 337 | * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high trigger output(if the trigger states exit). |
kadonotakashi | 0:8fdf9a60065b | 338 | * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low trigger output(if the trigger states exit). |
kadonotakashi | 0:8fdf9a60065b | 339 | */ |
kadonotakashi | 0:8fdf9a60065b | 340 | static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config) |
kadonotakashi | 0:8fdf9a60065b | 341 | { |
kadonotakashi | 0:8fdf9a60065b | 342 | base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); |
kadonotakashi | 0:8fdf9a60065b | 343 | } |
kadonotakashi | 0:8fdf9a60065b | 344 | |
kadonotakashi | 0:8fdf9a60065b | 345 | /*! |
kadonotakashi | 0:8fdf9a60065b | 346 | * @brief Reads the whole port status flag. |
kadonotakashi | 0:8fdf9a60065b | 347 | * |
kadonotakashi | 0:8fdf9a60065b | 348 | * If a pin is configured to generate the DMA request, the corresponding flag |
kadonotakashi | 0:8fdf9a60065b | 349 | * is cleared automatically at the completion of the requested DMA transfer. |
kadonotakashi | 0:8fdf9a60065b | 350 | * Otherwise, the flag remains set until a logic one is written to that flag. |
kadonotakashi | 0:8fdf9a60065b | 351 | * If configured for a level sensitive interrupt that remains asserted, the flag |
kadonotakashi | 0:8fdf9a60065b | 352 | * is set again immediately. |
kadonotakashi | 0:8fdf9a60065b | 353 | * |
kadonotakashi | 0:8fdf9a60065b | 354 | * @param base PORT peripheral base pointer. |
kadonotakashi | 0:8fdf9a60065b | 355 | * @return Current port interrupt status flags, for example, 0x00010001 means the |
kadonotakashi | 0:8fdf9a60065b | 356 | * pin 0 and 17 have the interrupt. |
kadonotakashi | 0:8fdf9a60065b | 357 | */ |
kadonotakashi | 0:8fdf9a60065b | 358 | static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base) |
kadonotakashi | 0:8fdf9a60065b | 359 | { |
kadonotakashi | 0:8fdf9a60065b | 360 | return base->ISFR; |
kadonotakashi | 0:8fdf9a60065b | 361 | } |
kadonotakashi | 0:8fdf9a60065b | 362 | |
kadonotakashi | 0:8fdf9a60065b | 363 | /*! |
kadonotakashi | 0:8fdf9a60065b | 364 | * @brief Clears the multiple pins' interrupt status flag. |
kadonotakashi | 0:8fdf9a60065b | 365 | * |
kadonotakashi | 0:8fdf9a60065b | 366 | * @param base PORT peripheral base pointer. |
kadonotakashi | 0:8fdf9a60065b | 367 | * @param mask PORT pins' numbers macro. |
kadonotakashi | 0:8fdf9a60065b | 368 | */ |
kadonotakashi | 0:8fdf9a60065b | 369 | static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) |
kadonotakashi | 0:8fdf9a60065b | 370 | { |
kadonotakashi | 0:8fdf9a60065b | 371 | base->ISFR = mask; |
kadonotakashi | 0:8fdf9a60065b | 372 | } |
kadonotakashi | 0:8fdf9a60065b | 373 | |
kadonotakashi | 0:8fdf9a60065b | 374 | /*@}*/ |
kadonotakashi | 0:8fdf9a60065b | 375 | |
kadonotakashi | 0:8fdf9a60065b | 376 | #if defined(__cplusplus) |
kadonotakashi | 0:8fdf9a60065b | 377 | } |
kadonotakashi | 0:8fdf9a60065b | 378 | #endif |
kadonotakashi | 0:8fdf9a60065b | 379 | |
kadonotakashi | 0:8fdf9a60065b | 380 | /*! @}*/ |
kadonotakashi | 0:8fdf9a60065b | 381 | |
kadonotakashi | 0:8fdf9a60065b | 382 | #endif /* _FSL_PORT_H_ */ |