takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_gpio.h@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:
kadonotakashi
Date:
Wed Oct 10 00:33:53 2018 +0000
Revision:
0:8fdf9a60065b
how to make mbed librry

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /*
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
kadonotakashi 0:8fdf9a60065b 3 * All rights reserved.
kadonotakashi 0:8fdf9a60065b 4 *
kadonotakashi 0:8fdf9a60065b 5 * Redistribution and use in source and binary forms, with or without modification,
kadonotakashi 0:8fdf9a60065b 6 * are permitted provided that the following conditions are met:
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * o Redistributions of source code must retain the above copyright notice, this list
kadonotakashi 0:8fdf9a60065b 9 * of conditions and the following disclaimer.
kadonotakashi 0:8fdf9a60065b 10 *
kadonotakashi 0:8fdf9a60065b 11 * o Redistributions in binary form must reproduce the above copyright notice, this
kadonotakashi 0:8fdf9a60065b 12 * list of conditions and the following disclaimer in the documentation and/or
kadonotakashi 0:8fdf9a60065b 13 * other materials provided with the distribution.
kadonotakashi 0:8fdf9a60065b 14 *
kadonotakashi 0:8fdf9a60065b 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kadonotakashi 0:8fdf9a60065b 16 * contributors may be used to endorse or promote products derived from this
kadonotakashi 0:8fdf9a60065b 17 * software without specific prior written permission.
kadonotakashi 0:8fdf9a60065b 18 *
kadonotakashi 0:8fdf9a60065b 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kadonotakashi 0:8fdf9a60065b 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kadonotakashi 0:8fdf9a60065b 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kadonotakashi 0:8fdf9a60065b 22 * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kadonotakashi 0:8fdf9a60065b 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kadonotakashi 0:8fdf9a60065b 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kadonotakashi 0:8fdf9a60065b 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kadonotakashi 0:8fdf9a60065b 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kadonotakashi 0:8fdf9a60065b 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kadonotakashi 0:8fdf9a60065b 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kadonotakashi 0:8fdf9a60065b 29 */
kadonotakashi 0:8fdf9a60065b 30
kadonotakashi 0:8fdf9a60065b 31 #ifndef _FSL_GPIO_H_
kadonotakashi 0:8fdf9a60065b 32 #define _FSL_GPIO_H_
kadonotakashi 0:8fdf9a60065b 33
kadonotakashi 0:8fdf9a60065b 34 #include "fsl_common.h"
kadonotakashi 0:8fdf9a60065b 35
kadonotakashi 0:8fdf9a60065b 36 /*!
kadonotakashi 0:8fdf9a60065b 37 * @addtogroup gpio
kadonotakashi 0:8fdf9a60065b 38 * @{
kadonotakashi 0:8fdf9a60065b 39 */
kadonotakashi 0:8fdf9a60065b 40
kadonotakashi 0:8fdf9a60065b 41 /*! @file */
kadonotakashi 0:8fdf9a60065b 42
kadonotakashi 0:8fdf9a60065b 43 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 44 * Definitions
kadonotakashi 0:8fdf9a60065b 45 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 46
kadonotakashi 0:8fdf9a60065b 47 /*! @name Driver version */
kadonotakashi 0:8fdf9a60065b 48 /*@{*/
kadonotakashi 0:8fdf9a60065b 49 /*! @brief GPIO driver version 2.1.0. */
kadonotakashi 0:8fdf9a60065b 50 #define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
kadonotakashi 0:8fdf9a60065b 51 /*@}*/
kadonotakashi 0:8fdf9a60065b 52
kadonotakashi 0:8fdf9a60065b 53 /*! @brief GPIO direction definition*/
kadonotakashi 0:8fdf9a60065b 54 typedef enum _gpio_pin_direction
kadonotakashi 0:8fdf9a60065b 55 {
kadonotakashi 0:8fdf9a60065b 56 kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
kadonotakashi 0:8fdf9a60065b 57 kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
kadonotakashi 0:8fdf9a60065b 58 } gpio_pin_direction_t;
kadonotakashi 0:8fdf9a60065b 59
kadonotakashi 0:8fdf9a60065b 60 /*!
kadonotakashi 0:8fdf9a60065b 61 * @brief The GPIO pin configuration structure.
kadonotakashi 0:8fdf9a60065b 62 *
kadonotakashi 0:8fdf9a60065b 63 * Every pin can only be configured as either output pin or input pin at a time.
kadonotakashi 0:8fdf9a60065b 64 * If configured as a input pin, then leave the outputConfig unused
kadonotakashi 0:8fdf9a60065b 65 * Note : In some cases, the corresponding port property should be configured in advance
kadonotakashi 0:8fdf9a60065b 66 * with the PORT_SetPinConfig()
kadonotakashi 0:8fdf9a60065b 67 */
kadonotakashi 0:8fdf9a60065b 68 typedef struct _gpio_pin_config
kadonotakashi 0:8fdf9a60065b 69 {
kadonotakashi 0:8fdf9a60065b 70 gpio_pin_direction_t pinDirection; /*!< gpio direction, input or output */
kadonotakashi 0:8fdf9a60065b 71 /* Output configurations, please ignore if configured as a input one */
kadonotakashi 0:8fdf9a60065b 72 uint8_t outputLogic; /*!< Set default output logic, no use in input */
kadonotakashi 0:8fdf9a60065b 73 } gpio_pin_config_t;
kadonotakashi 0:8fdf9a60065b 74
kadonotakashi 0:8fdf9a60065b 75 /*! @} */
kadonotakashi 0:8fdf9a60065b 76
kadonotakashi 0:8fdf9a60065b 77 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 78 * API
kadonotakashi 0:8fdf9a60065b 79 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 80
kadonotakashi 0:8fdf9a60065b 81 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 82 extern "C" {
kadonotakashi 0:8fdf9a60065b 83 #endif
kadonotakashi 0:8fdf9a60065b 84
kadonotakashi 0:8fdf9a60065b 85 /*!
kadonotakashi 0:8fdf9a60065b 86 * @addtogroup gpio_driver
kadonotakashi 0:8fdf9a60065b 87 * @{
kadonotakashi 0:8fdf9a60065b 88 */
kadonotakashi 0:8fdf9a60065b 89
kadonotakashi 0:8fdf9a60065b 90 /*! @name GPIO Configuration */
kadonotakashi 0:8fdf9a60065b 91 /*@{*/
kadonotakashi 0:8fdf9a60065b 92
kadonotakashi 0:8fdf9a60065b 93 /*!
kadonotakashi 0:8fdf9a60065b 94 * @brief Initializes a GPIO pin used by the board.
kadonotakashi 0:8fdf9a60065b 95 *
kadonotakashi 0:8fdf9a60065b 96 * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
kadonotakashi 0:8fdf9a60065b 97 * Then, call the GPIO_PinInit() function.
kadonotakashi 0:8fdf9a60065b 98 *
kadonotakashi 0:8fdf9a60065b 99 * This is an example to define an input pin or output pin configuration:
kadonotakashi 0:8fdf9a60065b 100 * @code
kadonotakashi 0:8fdf9a60065b 101 * // Define a digital input pin configuration,
kadonotakashi 0:8fdf9a60065b 102 * gpio_pin_config_t config =
kadonotakashi 0:8fdf9a60065b 103 * {
kadonotakashi 0:8fdf9a60065b 104 * kGPIO_DigitalInput,
kadonotakashi 0:8fdf9a60065b 105 * 0,
kadonotakashi 0:8fdf9a60065b 106 * }
kadonotakashi 0:8fdf9a60065b 107 * //Define a digital output pin configuration,
kadonotakashi 0:8fdf9a60065b 108 * gpio_pin_config_t config =
kadonotakashi 0:8fdf9a60065b 109 * {
kadonotakashi 0:8fdf9a60065b 110 * kGPIO_DigitalOutput,
kadonotakashi 0:8fdf9a60065b 111 * 0,
kadonotakashi 0:8fdf9a60065b 112 * }
kadonotakashi 0:8fdf9a60065b 113 * @endcode
kadonotakashi 0:8fdf9a60065b 114 *
kadonotakashi 0:8fdf9a60065b 115 * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 116 * @param pin GPIO port pin number
kadonotakashi 0:8fdf9a60065b 117 * @param config GPIO pin configuration pointer
kadonotakashi 0:8fdf9a60065b 118 */
kadonotakashi 0:8fdf9a60065b 119 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
kadonotakashi 0:8fdf9a60065b 120
kadonotakashi 0:8fdf9a60065b 121 /*@}*/
kadonotakashi 0:8fdf9a60065b 122
kadonotakashi 0:8fdf9a60065b 123 /*! @name GPIO Output Operations */
kadonotakashi 0:8fdf9a60065b 124 /*@{*/
kadonotakashi 0:8fdf9a60065b 125
kadonotakashi 0:8fdf9a60065b 126 /*!
kadonotakashi 0:8fdf9a60065b 127 * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
kadonotakashi 0:8fdf9a60065b 128 *
kadonotakashi 0:8fdf9a60065b 129 * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 130 * @param pin GPIO pin's number
kadonotakashi 0:8fdf9a60065b 131 * @param output GPIO pin output logic level.
kadonotakashi 0:8fdf9a60065b 132 * - 0: corresponding pin output low logic level.
kadonotakashi 0:8fdf9a60065b 133 * - 1: corresponding pin output high logic level.
kadonotakashi 0:8fdf9a60065b 134 */
kadonotakashi 0:8fdf9a60065b 135 static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
kadonotakashi 0:8fdf9a60065b 136 {
kadonotakashi 0:8fdf9a60065b 137 if (output == 0U)
kadonotakashi 0:8fdf9a60065b 138 {
kadonotakashi 0:8fdf9a60065b 139 base->PCOR = 1 << pin;
kadonotakashi 0:8fdf9a60065b 140 }
kadonotakashi 0:8fdf9a60065b 141 else
kadonotakashi 0:8fdf9a60065b 142 {
kadonotakashi 0:8fdf9a60065b 143 base->PSOR = 1 << pin;
kadonotakashi 0:8fdf9a60065b 144 }
kadonotakashi 0:8fdf9a60065b 145 }
kadonotakashi 0:8fdf9a60065b 146
kadonotakashi 0:8fdf9a60065b 147 /*!
kadonotakashi 0:8fdf9a60065b 148 * @brief Sets the output level of the multiple GPIO pins to the logic 1.
kadonotakashi 0:8fdf9a60065b 149 *
kadonotakashi 0:8fdf9a60065b 150 * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 151 * @param mask GPIO pins' numbers macro
kadonotakashi 0:8fdf9a60065b 152 */
kadonotakashi 0:8fdf9a60065b 153 static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 154 {
kadonotakashi 0:8fdf9a60065b 155 base->PSOR = mask;
kadonotakashi 0:8fdf9a60065b 156 }
kadonotakashi 0:8fdf9a60065b 157
kadonotakashi 0:8fdf9a60065b 158 /*!
kadonotakashi 0:8fdf9a60065b 159 * @brief Sets the output level of the multiple GPIO pins to the logic 0.
kadonotakashi 0:8fdf9a60065b 160 *
kadonotakashi 0:8fdf9a60065b 161 * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 162 * @param mask GPIO pins' numbers macro
kadonotakashi 0:8fdf9a60065b 163 */
kadonotakashi 0:8fdf9a60065b 164 static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 165 {
kadonotakashi 0:8fdf9a60065b 166 base->PCOR = mask;
kadonotakashi 0:8fdf9a60065b 167 }
kadonotakashi 0:8fdf9a60065b 168
kadonotakashi 0:8fdf9a60065b 169 /*!
kadonotakashi 0:8fdf9a60065b 170 * @brief Reverses current output logic of the multiple GPIO pins.
kadonotakashi 0:8fdf9a60065b 171 *
kadonotakashi 0:8fdf9a60065b 172 * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 173 * @param mask GPIO pins' numbers macro
kadonotakashi 0:8fdf9a60065b 174 */
kadonotakashi 0:8fdf9a60065b 175 static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 176 {
kadonotakashi 0:8fdf9a60065b 177 base->PTOR = mask;
kadonotakashi 0:8fdf9a60065b 178 }
kadonotakashi 0:8fdf9a60065b 179 /*@}*/
kadonotakashi 0:8fdf9a60065b 180
kadonotakashi 0:8fdf9a60065b 181 /*! @name GPIO Input Operations */
kadonotakashi 0:8fdf9a60065b 182 /*@{*/
kadonotakashi 0:8fdf9a60065b 183
kadonotakashi 0:8fdf9a60065b 184 /*!
kadonotakashi 0:8fdf9a60065b 185 * @brief Reads the current input value of the whole GPIO port.
kadonotakashi 0:8fdf9a60065b 186 *
kadonotakashi 0:8fdf9a60065b 187 * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 188 * @param pin GPIO pin's number
kadonotakashi 0:8fdf9a60065b 189 * @retval GPIO port input value
kadonotakashi 0:8fdf9a60065b 190 * - 0: corresponding pin input low logic level.
kadonotakashi 0:8fdf9a60065b 191 * - 1: corresponding pin input high logic level.
kadonotakashi 0:8fdf9a60065b 192 */
kadonotakashi 0:8fdf9a60065b 193 static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
kadonotakashi 0:8fdf9a60065b 194 {
kadonotakashi 0:8fdf9a60065b 195 return (((base->PDIR) >> pin) & 0x01U);
kadonotakashi 0:8fdf9a60065b 196 }
kadonotakashi 0:8fdf9a60065b 197 /*@}*/
kadonotakashi 0:8fdf9a60065b 198
kadonotakashi 0:8fdf9a60065b 199 /*! @name GPIO Interrupt */
kadonotakashi 0:8fdf9a60065b 200 /*@{*/
kadonotakashi 0:8fdf9a60065b 201
kadonotakashi 0:8fdf9a60065b 202 /*!
kadonotakashi 0:8fdf9a60065b 203 * @brief Reads whole GPIO port interrupt status flag.
kadonotakashi 0:8fdf9a60065b 204 *
kadonotakashi 0:8fdf9a60065b 205 * If a pin is configured to generate the DMA request, the corresponding flag
kadonotakashi 0:8fdf9a60065b 206 * is cleared automatically at the completion of the requested DMA transfer.
kadonotakashi 0:8fdf9a60065b 207 * Otherwise, the flag remains set until a logic one is written to that flag.
kadonotakashi 0:8fdf9a60065b 208 * If configured for a level sensitive interrupt that remains asserted, the flag
kadonotakashi 0:8fdf9a60065b 209 * is set again immediately.
kadonotakashi 0:8fdf9a60065b 210 *
kadonotakashi 0:8fdf9a60065b 211 * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 212 * @retval Current GPIO port interrupt status flag, for example, 0x00010001 means the
kadonotakashi 0:8fdf9a60065b 213 * pin 0 and 17 have the interrupt.
kadonotakashi 0:8fdf9a60065b 214 */
kadonotakashi 0:8fdf9a60065b 215 uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base);
kadonotakashi 0:8fdf9a60065b 216
kadonotakashi 0:8fdf9a60065b 217 /*!
kadonotakashi 0:8fdf9a60065b 218 * @brief Clears multiple GPIO pins' interrupt status flag.
kadonotakashi 0:8fdf9a60065b 219 *
kadonotakashi 0:8fdf9a60065b 220 * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 221 * @param mask GPIO pins' numbers macro
kadonotakashi 0:8fdf9a60065b 222 */
kadonotakashi 0:8fdf9a60065b 223 void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
kadonotakashi 0:8fdf9a60065b 224
kadonotakashi 0:8fdf9a60065b 225 /*@}*/
kadonotakashi 0:8fdf9a60065b 226 /*! @} */
kadonotakashi 0:8fdf9a60065b 227
kadonotakashi 0:8fdf9a60065b 228 /*!
kadonotakashi 0:8fdf9a60065b 229 * @addtogroup fgpio_driver
kadonotakashi 0:8fdf9a60065b 230 * @{
kadonotakashi 0:8fdf9a60065b 231 */
kadonotakashi 0:8fdf9a60065b 232
kadonotakashi 0:8fdf9a60065b 233 /*
kadonotakashi 0:8fdf9a60065b 234 * Introduce the FGPIO feature.
kadonotakashi 0:8fdf9a60065b 235 *
kadonotakashi 0:8fdf9a60065b 236 * The FGPIO features are only support on some of Kinetis chips. The FGPIO registers are aliased to the IOPORT
kadonotakashi 0:8fdf9a60065b 237 * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore
kadonotakashi 0:8fdf9a60065b 238 * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
kadonotakashi 0:8fdf9a60065b 239 */
kadonotakashi 0:8fdf9a60065b 240
kadonotakashi 0:8fdf9a60065b 241 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
kadonotakashi 0:8fdf9a60065b 242
kadonotakashi 0:8fdf9a60065b 243 /*! @name FGPIO Configuration */
kadonotakashi 0:8fdf9a60065b 244 /*@{*/
kadonotakashi 0:8fdf9a60065b 245
kadonotakashi 0:8fdf9a60065b 246 /*!
kadonotakashi 0:8fdf9a60065b 247 * @brief Initializes a FGPIO pin used by the board.
kadonotakashi 0:8fdf9a60065b 248 *
kadonotakashi 0:8fdf9a60065b 249 * To initialize the FGPIO driver, define a pin configuration, either input or output, in the user file.
kadonotakashi 0:8fdf9a60065b 250 * Then, call the FGPIO_PinInit() function.
kadonotakashi 0:8fdf9a60065b 251 *
kadonotakashi 0:8fdf9a60065b 252 * This is an example to define an input pin or output pin configuration:
kadonotakashi 0:8fdf9a60065b 253 * @code
kadonotakashi 0:8fdf9a60065b 254 * // Define a digital input pin configuration,
kadonotakashi 0:8fdf9a60065b 255 * gpio_pin_config_t config =
kadonotakashi 0:8fdf9a60065b 256 * {
kadonotakashi 0:8fdf9a60065b 257 * kGPIO_DigitalInput,
kadonotakashi 0:8fdf9a60065b 258 * 0,
kadonotakashi 0:8fdf9a60065b 259 * }
kadonotakashi 0:8fdf9a60065b 260 * //Define a digital output pin configuration,
kadonotakashi 0:8fdf9a60065b 261 * gpio_pin_config_t config =
kadonotakashi 0:8fdf9a60065b 262 * {
kadonotakashi 0:8fdf9a60065b 263 * kGPIO_DigitalOutput,
kadonotakashi 0:8fdf9a60065b 264 * 0,
kadonotakashi 0:8fdf9a60065b 265 * }
kadonotakashi 0:8fdf9a60065b 266 * @endcode
kadonotakashi 0:8fdf9a60065b 267 *
kadonotakashi 0:8fdf9a60065b 268 * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 269 * @param pin FGPIO port pin number
kadonotakashi 0:8fdf9a60065b 270 * @param config FGPIO pin configuration pointer
kadonotakashi 0:8fdf9a60065b 271 */
kadonotakashi 0:8fdf9a60065b 272 void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
kadonotakashi 0:8fdf9a60065b 273
kadonotakashi 0:8fdf9a60065b 274 /*@}*/
kadonotakashi 0:8fdf9a60065b 275
kadonotakashi 0:8fdf9a60065b 276 /*! @name FGPIO Output Operations */
kadonotakashi 0:8fdf9a60065b 277 /*@{*/
kadonotakashi 0:8fdf9a60065b 278
kadonotakashi 0:8fdf9a60065b 279 /*!
kadonotakashi 0:8fdf9a60065b 280 * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
kadonotakashi 0:8fdf9a60065b 281 *
kadonotakashi 0:8fdf9a60065b 282 * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 283 * @param pin FGPIO pin's number
kadonotakashi 0:8fdf9a60065b 284 * @param output FGPIOpin output logic level.
kadonotakashi 0:8fdf9a60065b 285 * - 0: corresponding pin output low logic level.
kadonotakashi 0:8fdf9a60065b 286 * - 1: corresponding pin output high logic level.
kadonotakashi 0:8fdf9a60065b 287 */
kadonotakashi 0:8fdf9a60065b 288 static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output)
kadonotakashi 0:8fdf9a60065b 289 {
kadonotakashi 0:8fdf9a60065b 290 if (output == 0U)
kadonotakashi 0:8fdf9a60065b 291 {
kadonotakashi 0:8fdf9a60065b 292 base->PCOR = 1 << pin;
kadonotakashi 0:8fdf9a60065b 293 }
kadonotakashi 0:8fdf9a60065b 294 else
kadonotakashi 0:8fdf9a60065b 295 {
kadonotakashi 0:8fdf9a60065b 296 base->PSOR = 1 << pin;
kadonotakashi 0:8fdf9a60065b 297 }
kadonotakashi 0:8fdf9a60065b 298 }
kadonotakashi 0:8fdf9a60065b 299
kadonotakashi 0:8fdf9a60065b 300 /*!
kadonotakashi 0:8fdf9a60065b 301 * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
kadonotakashi 0:8fdf9a60065b 302 *
kadonotakashi 0:8fdf9a60065b 303 * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 304 * @param mask FGPIO pins' numbers macro
kadonotakashi 0:8fdf9a60065b 305 */
kadonotakashi 0:8fdf9a60065b 306 static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 307 {
kadonotakashi 0:8fdf9a60065b 308 base->PSOR = mask;
kadonotakashi 0:8fdf9a60065b 309 }
kadonotakashi 0:8fdf9a60065b 310
kadonotakashi 0:8fdf9a60065b 311 /*!
kadonotakashi 0:8fdf9a60065b 312 * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
kadonotakashi 0:8fdf9a60065b 313 *
kadonotakashi 0:8fdf9a60065b 314 * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 315 * @param mask FGPIO pins' numbers macro
kadonotakashi 0:8fdf9a60065b 316 */
kadonotakashi 0:8fdf9a60065b 317 static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 318 {
kadonotakashi 0:8fdf9a60065b 319 base->PCOR = mask;
kadonotakashi 0:8fdf9a60065b 320 }
kadonotakashi 0:8fdf9a60065b 321
kadonotakashi 0:8fdf9a60065b 322 /*!
kadonotakashi 0:8fdf9a60065b 323 * @brief Reverses current output logic of the multiple FGPIO pins.
kadonotakashi 0:8fdf9a60065b 324 *
kadonotakashi 0:8fdf9a60065b 325 * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 326 * @param mask FGPIO pins' numbers macro
kadonotakashi 0:8fdf9a60065b 327 */
kadonotakashi 0:8fdf9a60065b 328 static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 329 {
kadonotakashi 0:8fdf9a60065b 330 base->PTOR = mask;
kadonotakashi 0:8fdf9a60065b 331 }
kadonotakashi 0:8fdf9a60065b 332 /*@}*/
kadonotakashi 0:8fdf9a60065b 333
kadonotakashi 0:8fdf9a60065b 334 /*! @name FGPIO Input Operations */
kadonotakashi 0:8fdf9a60065b 335 /*@{*/
kadonotakashi 0:8fdf9a60065b 336
kadonotakashi 0:8fdf9a60065b 337 /*!
kadonotakashi 0:8fdf9a60065b 338 * @brief Reads the current input value of the whole FGPIO port.
kadonotakashi 0:8fdf9a60065b 339 *
kadonotakashi 0:8fdf9a60065b 340 * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 341 * @param pin FGPIO pin's number
kadonotakashi 0:8fdf9a60065b 342 * @retval FGPIO port input value
kadonotakashi 0:8fdf9a60065b 343 * - 0: corresponding pin input low logic level.
kadonotakashi 0:8fdf9a60065b 344 * - 1: corresponding pin input high logic level.
kadonotakashi 0:8fdf9a60065b 345 */
kadonotakashi 0:8fdf9a60065b 346 static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
kadonotakashi 0:8fdf9a60065b 347 {
kadonotakashi 0:8fdf9a60065b 348 return (((base->PDIR) >> pin) & 0x01U);
kadonotakashi 0:8fdf9a60065b 349 }
kadonotakashi 0:8fdf9a60065b 350 /*@}*/
kadonotakashi 0:8fdf9a60065b 351
kadonotakashi 0:8fdf9a60065b 352 /*! @name FGPIO Interrupt */
kadonotakashi 0:8fdf9a60065b 353 /*@{*/
kadonotakashi 0:8fdf9a60065b 354
kadonotakashi 0:8fdf9a60065b 355 /*!
kadonotakashi 0:8fdf9a60065b 356 * @brief Reads the whole FGPIO port interrupt status flag.
kadonotakashi 0:8fdf9a60065b 357 *
kadonotakashi 0:8fdf9a60065b 358 * If a pin is configured to generate the DMA request, the corresponding flag
kadonotakashi 0:8fdf9a60065b 359 * is cleared automatically at the completion of the requested DMA transfer.
kadonotakashi 0:8fdf9a60065b 360 * Otherwise, the flag remains set until a logic one is written to that flag.
kadonotakashi 0:8fdf9a60065b 361 * If configured for a level sensitive interrupt that remains asserted, the flag
kadonotakashi 0:8fdf9a60065b 362 * is set again immediately.
kadonotakashi 0:8fdf9a60065b 363 *
kadonotakashi 0:8fdf9a60065b 364 * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 365 * @retval Current FGPIO port interrupt status flags, for example, 0x00010001 means the
kadonotakashi 0:8fdf9a60065b 366 * pin 0 and 17 have the interrupt.
kadonotakashi 0:8fdf9a60065b 367 */
kadonotakashi 0:8fdf9a60065b 368 uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base);
kadonotakashi 0:8fdf9a60065b 369
kadonotakashi 0:8fdf9a60065b 370 /*!
kadonotakashi 0:8fdf9a60065b 371 * @brief Clears the multiple FGPIO pins' interrupt status flag.
kadonotakashi 0:8fdf9a60065b 372 *
kadonotakashi 0:8fdf9a60065b 373 * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
kadonotakashi 0:8fdf9a60065b 374 * @param mask FGPIO pins' numbers macro
kadonotakashi 0:8fdf9a60065b 375 */
kadonotakashi 0:8fdf9a60065b 376 void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask);
kadonotakashi 0:8fdf9a60065b 377
kadonotakashi 0:8fdf9a60065b 378 /*@}*/
kadonotakashi 0:8fdf9a60065b 379
kadonotakashi 0:8fdf9a60065b 380 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
kadonotakashi 0:8fdf9a60065b 381
kadonotakashi 0:8fdf9a60065b 382 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 383 }
kadonotakashi 0:8fdf9a60065b 384 #endif
kadonotakashi 0:8fdf9a60065b 385
kadonotakashi 0:8fdf9a60065b 386 /*!
kadonotakashi 0:8fdf9a60065b 387 * @}
kadonotakashi 0:8fdf9a60065b 388 */
kadonotakashi 0:8fdf9a60065b 389
kadonotakashi 0:8fdf9a60065b 390 #endif /* _FSL_GPIO_H_*/