takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_dma.h@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:
kadonotakashi
Date:
Wed Oct 10 00:33:53 2018 +0000
Revision:
0:8fdf9a60065b
how to make mbed librry

Who changed what in which revision?

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kadonotakashi 0:8fdf9a60065b 1 /*
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
kadonotakashi 0:8fdf9a60065b 3 * All rights reserved.
kadonotakashi 0:8fdf9a60065b 4 *
kadonotakashi 0:8fdf9a60065b 5 * Redistribution and use in source and binary forms, with or without modification,
kadonotakashi 0:8fdf9a60065b 6 * are permitted provided that the following conditions are met:
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * o Redistributions of source code must retain the above copyright notice, this list
kadonotakashi 0:8fdf9a60065b 9 * of conditions and the following disclaimer.
kadonotakashi 0:8fdf9a60065b 10 *
kadonotakashi 0:8fdf9a60065b 11 * o Redistributions in binary form must reproduce the above copyright notice, this
kadonotakashi 0:8fdf9a60065b 12 * list of conditions and the following disclaimer in the documentation and/or
kadonotakashi 0:8fdf9a60065b 13 * other materials provided with the distribution.
kadonotakashi 0:8fdf9a60065b 14 *
kadonotakashi 0:8fdf9a60065b 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kadonotakashi 0:8fdf9a60065b 16 * contributors may be used to endorse or promote products derived from this
kadonotakashi 0:8fdf9a60065b 17 * software without specific prior written permission.
kadonotakashi 0:8fdf9a60065b 18 *
kadonotakashi 0:8fdf9a60065b 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kadonotakashi 0:8fdf9a60065b 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kadonotakashi 0:8fdf9a60065b 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kadonotakashi 0:8fdf9a60065b 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kadonotakashi 0:8fdf9a60065b 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kadonotakashi 0:8fdf9a60065b 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kadonotakashi 0:8fdf9a60065b 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kadonotakashi 0:8fdf9a60065b 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kadonotakashi 0:8fdf9a60065b 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kadonotakashi 0:8fdf9a60065b 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kadonotakashi 0:8fdf9a60065b 29 */
kadonotakashi 0:8fdf9a60065b 30
kadonotakashi 0:8fdf9a60065b 31 #ifndef _FSL_DMA_H_
kadonotakashi 0:8fdf9a60065b 32 #define _FSL_DMA_H_
kadonotakashi 0:8fdf9a60065b 33
kadonotakashi 0:8fdf9a60065b 34 #include "fsl_common.h"
kadonotakashi 0:8fdf9a60065b 35
kadonotakashi 0:8fdf9a60065b 36 /*!
kadonotakashi 0:8fdf9a60065b 37 * @addtogroup dma_driver
kadonotakashi 0:8fdf9a60065b 38 * @{
kadonotakashi 0:8fdf9a60065b 39 */
kadonotakashi 0:8fdf9a60065b 40
kadonotakashi 0:8fdf9a60065b 41 /*! @file */
kadonotakashi 0:8fdf9a60065b 42
kadonotakashi 0:8fdf9a60065b 43 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 44 * Definitions
kadonotakashi 0:8fdf9a60065b 45 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 46
kadonotakashi 0:8fdf9a60065b 47 /*! @name Driver version */
kadonotakashi 0:8fdf9a60065b 48 /*@{*/
kadonotakashi 0:8fdf9a60065b 49 /*! @brief DMA driver version 2.0.0. */
kadonotakashi 0:8fdf9a60065b 50 #define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
kadonotakashi 0:8fdf9a60065b 51 /*@}*/
kadonotakashi 0:8fdf9a60065b 52
kadonotakashi 0:8fdf9a60065b 53 /*! @brief status flag for the DMA driver. */
kadonotakashi 0:8fdf9a60065b 54 enum _dma_channel_status_flags
kadonotakashi 0:8fdf9a60065b 55 {
kadonotakashi 0:8fdf9a60065b 56 kDMA_TransactionsBCRFlag = DMA_DSR_BCR_BCR_MASK, /*!< Contains the number of bytes yet to be
kadonotakashi 0:8fdf9a60065b 57 transferred for a given block */
kadonotakashi 0:8fdf9a60065b 58 kDMA_TransactionsDoneFlag = DMA_DSR_BCR_DONE_MASK, /*!< Transactions Done */
kadonotakashi 0:8fdf9a60065b 59 kDMA_TransactionsBusyFlag = DMA_DSR_BCR_BSY_MASK, /*!< Transactions Busy */
kadonotakashi 0:8fdf9a60065b 60 kDMA_TransactionsRequestFlag = DMA_DSR_BCR_REQ_MASK, /*!< Transactions Request */
kadonotakashi 0:8fdf9a60065b 61 kDMA_BusErrorOnDestinationFlag = DMA_DSR_BCR_BED_MASK, /*!< Bus Error on Destination */
kadonotakashi 0:8fdf9a60065b 62 kDMA_BusErrorOnSourceFlag = DMA_DSR_BCR_BES_MASK, /*!< Bus Error on Source */
kadonotakashi 0:8fdf9a60065b 63 kDMA_ConfigurationErrorFlag = DMA_DSR_BCR_CE_MASK, /*!< Configuration Error */
kadonotakashi 0:8fdf9a60065b 64 };
kadonotakashi 0:8fdf9a60065b 65
kadonotakashi 0:8fdf9a60065b 66 /*! @brief DMA transfer size type*/
kadonotakashi 0:8fdf9a60065b 67 typedef enum _dma_transfer_size
kadonotakashi 0:8fdf9a60065b 68 {
kadonotakashi 0:8fdf9a60065b 69 kDMA_Transfersize32bits = 0x0U, /*!< 32 bits are transferred for every read/write */
kadonotakashi 0:8fdf9a60065b 70 kDMA_Transfersize8bits, /*!< 8 bits are transferred for every read/write */
kadonotakashi 0:8fdf9a60065b 71 kDMA_Transfersize16bits, /*!< 16b its are transferred for every read/write */
kadonotakashi 0:8fdf9a60065b 72 } dma_transfer_size_t;
kadonotakashi 0:8fdf9a60065b 73
kadonotakashi 0:8fdf9a60065b 74 /*! @brief Configuration type for the DMA modulo */
kadonotakashi 0:8fdf9a60065b 75 typedef enum _dma_modulo
kadonotakashi 0:8fdf9a60065b 76 {
kadonotakashi 0:8fdf9a60065b 77 kDMA_ModuloDisable = 0x0U, /*!< Buffer disabled */
kadonotakashi 0:8fdf9a60065b 78 kDMA_Modulo16Bytes, /*!< Circular buffer size is 16 bytes. */
kadonotakashi 0:8fdf9a60065b 79 kDMA_Modulo32Bytes, /*!< Circular buffer size is 32 bytes. */
kadonotakashi 0:8fdf9a60065b 80 kDMA_Modulo64Bytes, /*!< Circular buffer size is 64 bytes. */
kadonotakashi 0:8fdf9a60065b 81 kDMA_Modulo128Bytes, /*!< Circular buffer size is 128 bytes. */
kadonotakashi 0:8fdf9a60065b 82 kDMA_Modulo256Bytes, /*!< Circular buffer size is 256 bytes. */
kadonotakashi 0:8fdf9a60065b 83 kDMA_Modulo512Bytes, /*!< Circular buffer size is 512 bytes. */
kadonotakashi 0:8fdf9a60065b 84 kDMA_Modulo1KBytes, /*!< Circular buffer size is 1 KB. */
kadonotakashi 0:8fdf9a60065b 85 kDMA_Modulo2KBytes, /*!< Circular buffer size is 2 KB. */
kadonotakashi 0:8fdf9a60065b 86 kDMA_Modulo4KBytes, /*!< Circular buffer size is 4 KB. */
kadonotakashi 0:8fdf9a60065b 87 kDMA_Modulo8KBytes, /*!< Circular buffer size is 8 KB. */
kadonotakashi 0:8fdf9a60065b 88 kDMA_Modulo16KBytes, /*!< Circular buffer size is 16 KB. */
kadonotakashi 0:8fdf9a60065b 89 kDMA_Modulo32KBytes, /*!< Circular buffer size is 32 KB. */
kadonotakashi 0:8fdf9a60065b 90 kDMA_Modulo64KBytes, /*!< Circular buffer size is 64 KB. */
kadonotakashi 0:8fdf9a60065b 91 kDMA_Modulo128KBytes, /*!< Circular buffer size is 128 KB. */
kadonotakashi 0:8fdf9a60065b 92 kDMA_Modulo256KBytes, /*!< Circular buffer size is 256 KB. */
kadonotakashi 0:8fdf9a60065b 93 } dma_modulo_t;
kadonotakashi 0:8fdf9a60065b 94
kadonotakashi 0:8fdf9a60065b 95 /*! @brief DMA channel link type */
kadonotakashi 0:8fdf9a60065b 96 typedef enum _dma_channel_link_type
kadonotakashi 0:8fdf9a60065b 97 {
kadonotakashi 0:8fdf9a60065b 98 kDMA_ChannelLinkDisable = 0x0U, /*!< No channel link. */
kadonotakashi 0:8fdf9a60065b 99 kDMA_ChannelLinkChannel1AndChannel2, /*!< Perform a link to channel LCH1 after each cycle-steal transfer.
kadonotakashi 0:8fdf9a60065b 100 followed by a link to LCH2 after the BCR decrements to 0. */
kadonotakashi 0:8fdf9a60065b 101 kDMA_ChannelLinkChannel1, /*!< Perform a link to LCH1 after each cycle-steal transfer. */
kadonotakashi 0:8fdf9a60065b 102 kDMA_ChannelLinkChannel1AfterBCR0, /*!< Perform a link to LCH1 after the BCR decrements. */
kadonotakashi 0:8fdf9a60065b 103 } dma_channel_link_type_t;
kadonotakashi 0:8fdf9a60065b 104
kadonotakashi 0:8fdf9a60065b 105 /*! @brief DMA transfer type */
kadonotakashi 0:8fdf9a60065b 106 typedef enum _dma_transfer_type
kadonotakashi 0:8fdf9a60065b 107 {
kadonotakashi 0:8fdf9a60065b 108 kDMA_MemoryToMemory = 0x0U, /*!< Memory to Memory transfer. */
kadonotakashi 0:8fdf9a60065b 109 kDMA_PeripheralToMemory, /*!< Peripheral to Memory transfer. */
kadonotakashi 0:8fdf9a60065b 110 kDMA_MemoryToPeripheral, /*!< Memory to Peripheral transfer. */
kadonotakashi 0:8fdf9a60065b 111 } dma_transfer_type_t;
kadonotakashi 0:8fdf9a60065b 112
kadonotakashi 0:8fdf9a60065b 113 /*! @brief DMA transfer options */
kadonotakashi 0:8fdf9a60065b 114 typedef enum _dma_transfer_options
kadonotakashi 0:8fdf9a60065b 115 {
kadonotakashi 0:8fdf9a60065b 116 kDMA_NoOptions = 0x0U, /*!< Transfer without options. */
kadonotakashi 0:8fdf9a60065b 117 kDMA_EnableInterrupt, /*!< Enable interrupt while transfer complete. */
kadonotakashi 0:8fdf9a60065b 118 } dma_transfer_options_t;
kadonotakashi 0:8fdf9a60065b 119
kadonotakashi 0:8fdf9a60065b 120 /*! @brief DMA transfer status */
kadonotakashi 0:8fdf9a60065b 121 enum _dma_transfer_status
kadonotakashi 0:8fdf9a60065b 122 {
kadonotakashi 0:8fdf9a60065b 123 kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0),
kadonotakashi 0:8fdf9a60065b 124 };
kadonotakashi 0:8fdf9a60065b 125
kadonotakashi 0:8fdf9a60065b 126 /*! @brief DMA transfer configuration structure */
kadonotakashi 0:8fdf9a60065b 127 typedef struct _dma_transfer_config
kadonotakashi 0:8fdf9a60065b 128 {
kadonotakashi 0:8fdf9a60065b 129 uint32_t srcAddr; /*!< DMA transfer source address. */
kadonotakashi 0:8fdf9a60065b 130 uint32_t destAddr; /*!< DMA destination address.*/
kadonotakashi 0:8fdf9a60065b 131 bool enableSrcIncrement; /*!< Source address increase after each transfer. */
kadonotakashi 0:8fdf9a60065b 132 dma_transfer_size_t srcSize; /*!< Source transfer size unit. */
kadonotakashi 0:8fdf9a60065b 133 bool enableDestIncrement; /*!< Destination address increase after each transfer. */
kadonotakashi 0:8fdf9a60065b 134 dma_transfer_size_t destSize; /*!< Destination transfer unit.*/
kadonotakashi 0:8fdf9a60065b 135 uint32_t transferSize; /*!< The number of bytes to be transferred. */
kadonotakashi 0:8fdf9a60065b 136 } dma_transfer_config_t;
kadonotakashi 0:8fdf9a60065b 137
kadonotakashi 0:8fdf9a60065b 138 /*! @brief DMA transfer configuration structure */
kadonotakashi 0:8fdf9a60065b 139 typedef struct _dma_channel_link_config
kadonotakashi 0:8fdf9a60065b 140 {
kadonotakashi 0:8fdf9a60065b 141 dma_channel_link_type_t linkType; /*!< Channel link type. */
kadonotakashi 0:8fdf9a60065b 142 uint32_t channel1; /*!< The index of channel 1. */
kadonotakashi 0:8fdf9a60065b 143 uint32_t channel2; /*!< The index of channel 2. */
kadonotakashi 0:8fdf9a60065b 144 } dma_channel_link_config_t;
kadonotakashi 0:8fdf9a60065b 145
kadonotakashi 0:8fdf9a60065b 146 struct _dma_handle;
kadonotakashi 0:8fdf9a60065b 147 /*! @brief Callback function prototype for the DMA driver. */
kadonotakashi 0:8fdf9a60065b 148 typedef void (*dma_callback)(struct _dma_handle *handle, void *userData);
kadonotakashi 0:8fdf9a60065b 149
kadonotakashi 0:8fdf9a60065b 150 /*! @brief DMA DMA handle structure */
kadonotakashi 0:8fdf9a60065b 151 typedef struct _dma_handle
kadonotakashi 0:8fdf9a60065b 152 {
kadonotakashi 0:8fdf9a60065b 153 DMA_Type *base; /*!< DMA peripheral address. */
kadonotakashi 0:8fdf9a60065b 154 uint8_t channel; /*!< DMA channel used. */
kadonotakashi 0:8fdf9a60065b 155 dma_callback callback; /*!< DMA callback function.*/
kadonotakashi 0:8fdf9a60065b 156 void *userData; /*!< Callback parameter. */
kadonotakashi 0:8fdf9a60065b 157 } dma_handle_t;
kadonotakashi 0:8fdf9a60065b 158
kadonotakashi 0:8fdf9a60065b 159 /*******************************************************************************
kadonotakashi 0:8fdf9a60065b 160 * API
kadonotakashi 0:8fdf9a60065b 161 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 162 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 163 extern "C" {
kadonotakashi 0:8fdf9a60065b 164 #endif /* __cplusplus */
kadonotakashi 0:8fdf9a60065b 165
kadonotakashi 0:8fdf9a60065b 166 /*!
kadonotakashi 0:8fdf9a60065b 167 * @name DMA Initialization and De-initialization
kadonotakashi 0:8fdf9a60065b 168 * @{
kadonotakashi 0:8fdf9a60065b 169 */
kadonotakashi 0:8fdf9a60065b 170
kadonotakashi 0:8fdf9a60065b 171 /*!
kadonotakashi 0:8fdf9a60065b 172 * @brief Initializes the DMA peripheral.
kadonotakashi 0:8fdf9a60065b 173 *
kadonotakashi 0:8fdf9a60065b 174 * This function ungates the DMA clock.
kadonotakashi 0:8fdf9a60065b 175 *
kadonotakashi 0:8fdf9a60065b 176 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 177 */
kadonotakashi 0:8fdf9a60065b 178 void DMA_Init(DMA_Type *base);
kadonotakashi 0:8fdf9a60065b 179
kadonotakashi 0:8fdf9a60065b 180 /*!
kadonotakashi 0:8fdf9a60065b 181 * @brief Deinitializes the DMA peripheral.
kadonotakashi 0:8fdf9a60065b 182 *
kadonotakashi 0:8fdf9a60065b 183 * This function gates the DMA clock.
kadonotakashi 0:8fdf9a60065b 184 *
kadonotakashi 0:8fdf9a60065b 185 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 186 */
kadonotakashi 0:8fdf9a60065b 187 void DMA_Deinit(DMA_Type *base);
kadonotakashi 0:8fdf9a60065b 188
kadonotakashi 0:8fdf9a60065b 189 /* @} */
kadonotakashi 0:8fdf9a60065b 190 /*!
kadonotakashi 0:8fdf9a60065b 191 * @name DMA Channel Operation
kadonotakashi 0:8fdf9a60065b 192 * @{
kadonotakashi 0:8fdf9a60065b 193 */
kadonotakashi 0:8fdf9a60065b 194
kadonotakashi 0:8fdf9a60065b 195 /*!
kadonotakashi 0:8fdf9a60065b 196 * @brief Resets the DMA channel.
kadonotakashi 0:8fdf9a60065b 197 *
kadonotakashi 0:8fdf9a60065b 198 * Sets all register values to reset values and enables
kadonotakashi 0:8fdf9a60065b 199 * the cycle steal and auto stop channel request features.
kadonotakashi 0:8fdf9a60065b 200 *
kadonotakashi 0:8fdf9a60065b 201 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 202 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 203 */
kadonotakashi 0:8fdf9a60065b 204 void DMA_ResetChannel(DMA_Type *base, uint32_t channel);
kadonotakashi 0:8fdf9a60065b 205
kadonotakashi 0:8fdf9a60065b 206 /*!
kadonotakashi 0:8fdf9a60065b 207 * @brief Configures the DMA transfer attribute.
kadonotakashi 0:8fdf9a60065b 208 *
kadonotakashi 0:8fdf9a60065b 209 * This function configures the transfer attribute including the source address,
kadonotakashi 0:8fdf9a60065b 210 * destination address, transfer size, and so on.
kadonotakashi 0:8fdf9a60065b 211 * This example shows how to set up the the dma_transfer_config_t
kadonotakashi 0:8fdf9a60065b 212 * parameters and how to call the DMA_ConfigBasicTransfer function.
kadonotakashi 0:8fdf9a60065b 213 * @code
kadonotakashi 0:8fdf9a60065b 214 * dma_transfer_config_t transferConfig;
kadonotakashi 0:8fdf9a60065b 215 * memset(&transferConfig, 0, sizeof(transferConfig));
kadonotakashi 0:8fdf9a60065b 216 * transferConfig.srcAddr = (uint32_t)srcAddr;
kadonotakashi 0:8fdf9a60065b 217 * transferConfig.destAddr = (uint32_t)destAddr;
kadonotakashi 0:8fdf9a60065b 218 * transferConfig.enbaleSrcIncrement = true;
kadonotakashi 0:8fdf9a60065b 219 * transferConfig.enableDestIncrement = true;
kadonotakashi 0:8fdf9a60065b 220 * transferConfig.srcSize = kDMA_Transfersize32bits;
kadonotakashi 0:8fdf9a60065b 221 * transferConfig.destSize = kDMA_Transfersize32bits;
kadonotakashi 0:8fdf9a60065b 222 * transferConfig.transferSize = sizeof(uint32_t) * BUFF_LENGTH;
kadonotakashi 0:8fdf9a60065b 223 * DMA_SetTransferConfig(DMA0, 0, &transferConfig);
kadonotakashi 0:8fdf9a60065b 224 * @endcode
kadonotakashi 0:8fdf9a60065b 225 *
kadonotakashi 0:8fdf9a60065b 226 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 227 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 228 * @param config Pointer to the DMA transfer configuration structure.
kadonotakashi 0:8fdf9a60065b 229 */
kadonotakashi 0:8fdf9a60065b 230 void DMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const dma_transfer_config_t *config);
kadonotakashi 0:8fdf9a60065b 231
kadonotakashi 0:8fdf9a60065b 232 /*!
kadonotakashi 0:8fdf9a60065b 233 * @brief Configures the DMA channel link feature.
kadonotakashi 0:8fdf9a60065b 234 *
kadonotakashi 0:8fdf9a60065b 235 * This function allows DMA channels to have their transfers linked. The current DMA channel
kadonotakashi 0:8fdf9a60065b 236 * triggers a DMA request to the linked channels (LCH1 or LCH2) depending on the channel link
kadonotakashi 0:8fdf9a60065b 237 * type.
kadonotakashi 0:8fdf9a60065b 238 * Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2
kadonotakashi 0:8fdf9a60065b 239 * after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AndChannel2.
kadonotakashi 0:8fdf9a60065b 240 * Perform a link to LCH1 after each cycle-steal transfer if the type is kDMA_ChannelLinkChannel1.
kadonotakashi 0:8fdf9a60065b 241 * Perform a link to LCH1 after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AfterBCR0.
kadonotakashi 0:8fdf9a60065b 242 *
kadonotakashi 0:8fdf9a60065b 243 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 244 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 245 * @param config Pointer to the channel link configuration structure.
kadonotakashi 0:8fdf9a60065b 246 */
kadonotakashi 0:8fdf9a60065b 247 void DMA_SetChannelLinkConfig(DMA_Type *base, uint32_t channel, const dma_channel_link_config_t *config);
kadonotakashi 0:8fdf9a60065b 248
kadonotakashi 0:8fdf9a60065b 249 /*!
kadonotakashi 0:8fdf9a60065b 250 * @brief Sets the DMA source address for the DMA transfer.
kadonotakashi 0:8fdf9a60065b 251 *
kadonotakashi 0:8fdf9a60065b 252 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 253 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 254 * @param srcAddr DMA source address.
kadonotakashi 0:8fdf9a60065b 255 */
kadonotakashi 0:8fdf9a60065b 256 static inline void DMA_SetSourceAddress(DMA_Type *base, uint32_t channel, uint32_t srcAddr)
kadonotakashi 0:8fdf9a60065b 257 {
kadonotakashi 0:8fdf9a60065b 258 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 259
kadonotakashi 0:8fdf9a60065b 260 base->DMA[channel].SAR = srcAddr;
kadonotakashi 0:8fdf9a60065b 261 }
kadonotakashi 0:8fdf9a60065b 262
kadonotakashi 0:8fdf9a60065b 263 /*!
kadonotakashi 0:8fdf9a60065b 264 * @brief Sets the DMA destination address for the DMA transfer.
kadonotakashi 0:8fdf9a60065b 265 *
kadonotakashi 0:8fdf9a60065b 266 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 267 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 268 * @param destAddr DMA destination address.
kadonotakashi 0:8fdf9a60065b 269 */
kadonotakashi 0:8fdf9a60065b 270 static inline void DMA_SetDestinationAddress(DMA_Type *base, uint32_t channel, uint32_t destAddr)
kadonotakashi 0:8fdf9a60065b 271 {
kadonotakashi 0:8fdf9a60065b 272 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 273
kadonotakashi 0:8fdf9a60065b 274 base->DMA[channel].DAR = destAddr;
kadonotakashi 0:8fdf9a60065b 275 }
kadonotakashi 0:8fdf9a60065b 276
kadonotakashi 0:8fdf9a60065b 277 /*!
kadonotakashi 0:8fdf9a60065b 278 * @brief Sets the DMA transfer size for the DMA transfer.
kadonotakashi 0:8fdf9a60065b 279 *
kadonotakashi 0:8fdf9a60065b 280 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 281 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 282 * @param size The number of bytes to be transferred.
kadonotakashi 0:8fdf9a60065b 283 */
kadonotakashi 0:8fdf9a60065b 284 static inline void DMA_SetTransferSize(DMA_Type *base, uint32_t channel, uint32_t size)
kadonotakashi 0:8fdf9a60065b 285 {
kadonotakashi 0:8fdf9a60065b 286 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 287
kadonotakashi 0:8fdf9a60065b 288 base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(size);
kadonotakashi 0:8fdf9a60065b 289 }
kadonotakashi 0:8fdf9a60065b 290
kadonotakashi 0:8fdf9a60065b 291 /*!
kadonotakashi 0:8fdf9a60065b 292 * @brief Sets the DMA modulo for the DMA transfer.
kadonotakashi 0:8fdf9a60065b 293 *
kadonotakashi 0:8fdf9a60065b 294 * This function defines a specific address range specified to be the value after (SAR + SSIZE)/(DAR + DSIZE)
kadonotakashi 0:8fdf9a60065b 295 * calculation is performed or the original register value. It provides the ability to implement a circular
kadonotakashi 0:8fdf9a60065b 296 * data queue easily.
kadonotakashi 0:8fdf9a60065b 297 *
kadonotakashi 0:8fdf9a60065b 298 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 299 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 300 * @param srcModulo source address modulo.
kadonotakashi 0:8fdf9a60065b 301 * @param destModulo destination address modulo.
kadonotakashi 0:8fdf9a60065b 302 */
kadonotakashi 0:8fdf9a60065b 303 void DMA_SetModulo(DMA_Type *base, uint32_t channel, dma_modulo_t srcModulo, dma_modulo_t destModulo);
kadonotakashi 0:8fdf9a60065b 304
kadonotakashi 0:8fdf9a60065b 305 /*!
kadonotakashi 0:8fdf9a60065b 306 * @brief Enables the DMA cycle steal for the DMA transfer.
kadonotakashi 0:8fdf9a60065b 307 *
kadonotakashi 0:8fdf9a60065b 308 * If the cycle steal feature is enabled (true), the DMA controller forces a single read/write transfer per request,
kadonotakashi 0:8fdf9a60065b 309 * or it continuously makes read/write transfers until the BCR decrements to 0.
kadonotakashi 0:8fdf9a60065b 310 *
kadonotakashi 0:8fdf9a60065b 311 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 312 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 313 * @param enable The command for enable (true) or disable (false).
kadonotakashi 0:8fdf9a60065b 314 */
kadonotakashi 0:8fdf9a60065b 315 static inline void DMA_EnableCycleSteal(DMA_Type *base, uint32_t channel, bool enable)
kadonotakashi 0:8fdf9a60065b 316 {
kadonotakashi 0:8fdf9a60065b 317 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 318
kadonotakashi 0:8fdf9a60065b 319 base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_CS_MASK)) | DMA_DCR_CS(enable);
kadonotakashi 0:8fdf9a60065b 320 }
kadonotakashi 0:8fdf9a60065b 321
kadonotakashi 0:8fdf9a60065b 322 /*!
kadonotakashi 0:8fdf9a60065b 323 * @brief Enables the DMA auto align for the DMA transfer.
kadonotakashi 0:8fdf9a60065b 324 *
kadonotakashi 0:8fdf9a60065b 325 * If the auto align feature is enabled (true), the appropriate address register increments,
kadonotakashi 0:8fdf9a60065b 326 * regardless of DINC or SINC.
kadonotakashi 0:8fdf9a60065b 327 *
kadonotakashi 0:8fdf9a60065b 328 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 329 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 330 * @param enable The command for enable (true) or disable (false).
kadonotakashi 0:8fdf9a60065b 331 */
kadonotakashi 0:8fdf9a60065b 332 static inline void DMA_EnableAutoAlign(DMA_Type *base, uint32_t channel, bool enable)
kadonotakashi 0:8fdf9a60065b 333 {
kadonotakashi 0:8fdf9a60065b 334 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 335
kadonotakashi 0:8fdf9a60065b 336 base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_AA_MASK)) | DMA_DCR_AA(enable);
kadonotakashi 0:8fdf9a60065b 337 }
kadonotakashi 0:8fdf9a60065b 338
kadonotakashi 0:8fdf9a60065b 339 /*!
kadonotakashi 0:8fdf9a60065b 340 * @brief Enables the DMA async request for the DMA transfer.
kadonotakashi 0:8fdf9a60065b 341 *
kadonotakashi 0:8fdf9a60065b 342 * If the async request feature is enabled (true), the DMA supports asynchronous DREQs
kadonotakashi 0:8fdf9a60065b 343 * while the MCU is in stop mode.
kadonotakashi 0:8fdf9a60065b 344 *
kadonotakashi 0:8fdf9a60065b 345 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 346 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 347 * @param enable The command for enable (true) or disable (false).
kadonotakashi 0:8fdf9a60065b 348 */
kadonotakashi 0:8fdf9a60065b 349 static inline void DMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)
kadonotakashi 0:8fdf9a60065b 350 {
kadonotakashi 0:8fdf9a60065b 351 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 352
kadonotakashi 0:8fdf9a60065b 353 base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_EADREQ_MASK)) | DMA_DCR_EADREQ(enable);
kadonotakashi 0:8fdf9a60065b 354 }
kadonotakashi 0:8fdf9a60065b 355
kadonotakashi 0:8fdf9a60065b 356 /*!
kadonotakashi 0:8fdf9a60065b 357 * @brief Enables an interrupt for the DMA transfer.
kadonotakashi 0:8fdf9a60065b 358 *
kadonotakashi 0:8fdf9a60065b 359 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 360 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 361 */
kadonotakashi 0:8fdf9a60065b 362 static inline void DMA_EnableInterrupts(DMA_Type *base, uint32_t channel)
kadonotakashi 0:8fdf9a60065b 363 {
kadonotakashi 0:8fdf9a60065b 364 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 365
kadonotakashi 0:8fdf9a60065b 366 base->DMA[channel].DCR |= DMA_DCR_EINT(true);
kadonotakashi 0:8fdf9a60065b 367 }
kadonotakashi 0:8fdf9a60065b 368
kadonotakashi 0:8fdf9a60065b 369 /*!
kadonotakashi 0:8fdf9a60065b 370 * @brief Disables an interrupt for the DMA transfer.
kadonotakashi 0:8fdf9a60065b 371 *
kadonotakashi 0:8fdf9a60065b 372 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 373 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 374 */
kadonotakashi 0:8fdf9a60065b 375 static inline void DMA_DisableInterrupts(DMA_Type *base, uint32_t channel)
kadonotakashi 0:8fdf9a60065b 376 {
kadonotakashi 0:8fdf9a60065b 377 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 378
kadonotakashi 0:8fdf9a60065b 379 base->DMA[channel].DCR &= ~DMA_DCR_EINT_MASK;
kadonotakashi 0:8fdf9a60065b 380 }
kadonotakashi 0:8fdf9a60065b 381
kadonotakashi 0:8fdf9a60065b 382 /* @} */
kadonotakashi 0:8fdf9a60065b 383 /*!
kadonotakashi 0:8fdf9a60065b 384 * @name DMA Channel Transfer Operation
kadonotakashi 0:8fdf9a60065b 385 * @{
kadonotakashi 0:8fdf9a60065b 386 */
kadonotakashi 0:8fdf9a60065b 387
kadonotakashi 0:8fdf9a60065b 388 /*!
kadonotakashi 0:8fdf9a60065b 389 * @brief Enables the DMA hardware channel request.
kadonotakashi 0:8fdf9a60065b 390 *
kadonotakashi 0:8fdf9a60065b 391 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 392 * @param channel The DMA channel number.
kadonotakashi 0:8fdf9a60065b 393 */
kadonotakashi 0:8fdf9a60065b 394 static inline void DMA_EnableChannelRequest(DMA_Type *base, uint32_t channel)
kadonotakashi 0:8fdf9a60065b 395 {
kadonotakashi 0:8fdf9a60065b 396 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 397
kadonotakashi 0:8fdf9a60065b 398 base->DMA[channel].DCR |= DMA_DCR_ERQ_MASK;
kadonotakashi 0:8fdf9a60065b 399 }
kadonotakashi 0:8fdf9a60065b 400
kadonotakashi 0:8fdf9a60065b 401 /*!
kadonotakashi 0:8fdf9a60065b 402 * @brief Disables the DMA hardware channel request.
kadonotakashi 0:8fdf9a60065b 403 *
kadonotakashi 0:8fdf9a60065b 404 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 405 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 406 */
kadonotakashi 0:8fdf9a60065b 407 static inline void DMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
kadonotakashi 0:8fdf9a60065b 408 {
kadonotakashi 0:8fdf9a60065b 409 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 410
kadonotakashi 0:8fdf9a60065b 411 base->DMA[channel].DCR &= ~DMA_DCR_ERQ_MASK;
kadonotakashi 0:8fdf9a60065b 412 }
kadonotakashi 0:8fdf9a60065b 413
kadonotakashi 0:8fdf9a60065b 414 /*!
kadonotakashi 0:8fdf9a60065b 415 * @brief Starts the DMA transfer with a software trigger.
kadonotakashi 0:8fdf9a60065b 416 *
kadonotakashi 0:8fdf9a60065b 417 * This function starts only one read/write iteration.
kadonotakashi 0:8fdf9a60065b 418 *
kadonotakashi 0:8fdf9a60065b 419 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 420 * @param channel The DMA channel number.
kadonotakashi 0:8fdf9a60065b 421 */
kadonotakashi 0:8fdf9a60065b 422 static inline void DMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
kadonotakashi 0:8fdf9a60065b 423 {
kadonotakashi 0:8fdf9a60065b 424 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 425
kadonotakashi 0:8fdf9a60065b 426 base->DMA[channel].DCR |= DMA_DCR_START_MASK;
kadonotakashi 0:8fdf9a60065b 427 }
kadonotakashi 0:8fdf9a60065b 428
kadonotakashi 0:8fdf9a60065b 429 /* @} */
kadonotakashi 0:8fdf9a60065b 430 /*!
kadonotakashi 0:8fdf9a60065b 431 * @name DMA Channel Status Operation
kadonotakashi 0:8fdf9a60065b 432 * @{
kadonotakashi 0:8fdf9a60065b 433 */
kadonotakashi 0:8fdf9a60065b 434
kadonotakashi 0:8fdf9a60065b 435 /*!
kadonotakashi 0:8fdf9a60065b 436 * @brief Gets the remaining bytes of the current DMA transfer.
kadonotakashi 0:8fdf9a60065b 437 *
kadonotakashi 0:8fdf9a60065b 438 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 439 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 440 * @return The number of bytes which have not been transferred yet.
kadonotakashi 0:8fdf9a60065b 441 */
kadonotakashi 0:8fdf9a60065b 442 static inline uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
kadonotakashi 0:8fdf9a60065b 443 {
kadonotakashi 0:8fdf9a60065b 444 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 445
kadonotakashi 0:8fdf9a60065b 446 return (base->DMA[channel].DSR_BCR & DMA_DSR_BCR_BCR_MASK) >> DMA_DSR_BCR_BCR_SHIFT;
kadonotakashi 0:8fdf9a60065b 447 }
kadonotakashi 0:8fdf9a60065b 448
kadonotakashi 0:8fdf9a60065b 449 /*!
kadonotakashi 0:8fdf9a60065b 450 * @brief Gets the DMA channel status flags.
kadonotakashi 0:8fdf9a60065b 451 *
kadonotakashi 0:8fdf9a60065b 452 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 453 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 454 * @return The mask of the channel status. Use the _dma_channel_status_flags
kadonotakashi 0:8fdf9a60065b 455 * type to decode the return 32 bit variables.
kadonotakashi 0:8fdf9a60065b 456 */
kadonotakashi 0:8fdf9a60065b 457 static inline uint32_t DMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
kadonotakashi 0:8fdf9a60065b 458 {
kadonotakashi 0:8fdf9a60065b 459 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 460
kadonotakashi 0:8fdf9a60065b 461 return base->DMA[channel].DSR_BCR;
kadonotakashi 0:8fdf9a60065b 462 }
kadonotakashi 0:8fdf9a60065b 463
kadonotakashi 0:8fdf9a60065b 464 /*!
kadonotakashi 0:8fdf9a60065b 465 * @brief Clears the DMA channel status flags.
kadonotakashi 0:8fdf9a60065b 466 *
kadonotakashi 0:8fdf9a60065b 467 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 468 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 469 * @param mask The mask of the channel status to be cleared. Use
kadonotakashi 0:8fdf9a60065b 470 * the defined _dma_channel_status_flags type.
kadonotakashi 0:8fdf9a60065b 471 */
kadonotakashi 0:8fdf9a60065b 472 static inline void DMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 473 {
kadonotakashi 0:8fdf9a60065b 474 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
kadonotakashi 0:8fdf9a60065b 475
kadonotakashi 0:8fdf9a60065b 476 if (mask != 0U)
kadonotakashi 0:8fdf9a60065b 477 {
kadonotakashi 0:8fdf9a60065b 478 base->DMA[channel].DSR_BCR |= DMA_DSR_BCR_DONE(true);
kadonotakashi 0:8fdf9a60065b 479 }
kadonotakashi 0:8fdf9a60065b 480 }
kadonotakashi 0:8fdf9a60065b 481
kadonotakashi 0:8fdf9a60065b 482 /* @} */
kadonotakashi 0:8fdf9a60065b 483 /*!
kadonotakashi 0:8fdf9a60065b 484 * @name DMA Channel Transactional Operation
kadonotakashi 0:8fdf9a60065b 485 * @{
kadonotakashi 0:8fdf9a60065b 486 */
kadonotakashi 0:8fdf9a60065b 487
kadonotakashi 0:8fdf9a60065b 488 /*!
kadonotakashi 0:8fdf9a60065b 489 * @brief Creates the DMA handle.
kadonotakashi 0:8fdf9a60065b 490 *
kadonotakashi 0:8fdf9a60065b 491 * This function is called first if using the transactional API for the DMA. This function
kadonotakashi 0:8fdf9a60065b 492 * initializes the internal state of the DMA handle.
kadonotakashi 0:8fdf9a60065b 493 *
kadonotakashi 0:8fdf9a60065b 494 * @param handle DMA handle pointer. The DMA handle stores callback function and
kadonotakashi 0:8fdf9a60065b 495 * parameters.
kadonotakashi 0:8fdf9a60065b 496 * @param base DMA peripheral base address.
kadonotakashi 0:8fdf9a60065b 497 * @param channel DMA channel number.
kadonotakashi 0:8fdf9a60065b 498 */
kadonotakashi 0:8fdf9a60065b 499 void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
kadonotakashi 0:8fdf9a60065b 500
kadonotakashi 0:8fdf9a60065b 501 /*!
kadonotakashi 0:8fdf9a60065b 502 * @brief Sets the DMA callback function.
kadonotakashi 0:8fdf9a60065b 503 *
kadonotakashi 0:8fdf9a60065b 504 * This callback is called in the DMA IRQ handler. Use the callback to do something
kadonotakashi 0:8fdf9a60065b 505 * after the current transfer complete.
kadonotakashi 0:8fdf9a60065b 506 *
kadonotakashi 0:8fdf9a60065b 507 * @param handle DMA handle pointer.
kadonotakashi 0:8fdf9a60065b 508 * @param callback DMA callback function pointer.
kadonotakashi 0:8fdf9a60065b 509 * @param userData Parameter for callback function. If it is not needed, just set to NULL.
kadonotakashi 0:8fdf9a60065b 510 */
kadonotakashi 0:8fdf9a60065b 511 void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
kadonotakashi 0:8fdf9a60065b 512
kadonotakashi 0:8fdf9a60065b 513 /*!
kadonotakashi 0:8fdf9a60065b 514 * @brief Prepares the DMA transfer configuration structure.
kadonotakashi 0:8fdf9a60065b 515 *
kadonotakashi 0:8fdf9a60065b 516 * This function prepares the transfer configuration structure according to the user input.
kadonotakashi 0:8fdf9a60065b 517 *
kadonotakashi 0:8fdf9a60065b 518 * @param config Pointer to the user configuration structure of type dma_transfer_config_t.
kadonotakashi 0:8fdf9a60065b 519 * @param srcAddr DMA transfer source address.
kadonotakashi 0:8fdf9a60065b 520 * @param srcWidth DMA transfer source address width (byte).
kadonotakashi 0:8fdf9a60065b 521 * @param destAddr DMA transfer destination address.
kadonotakashi 0:8fdf9a60065b 522 * @param destWidth DMA transfer destination address width (byte).
kadonotakashi 0:8fdf9a60065b 523 * @param transferBytes DMA transfer bytes to be transferred.
kadonotakashi 0:8fdf9a60065b 524 * @param type DMA transfer type.
kadonotakashi 0:8fdf9a60065b 525 */
kadonotakashi 0:8fdf9a60065b 526 void DMA_PrepareTransfer(dma_transfer_config_t *config,
kadonotakashi 0:8fdf9a60065b 527 void *srcAddr,
kadonotakashi 0:8fdf9a60065b 528 uint32_t srcWidth,
kadonotakashi 0:8fdf9a60065b 529 void *destAddr,
kadonotakashi 0:8fdf9a60065b 530 uint32_t destWidth,
kadonotakashi 0:8fdf9a60065b 531 uint32_t transferBytes,
kadonotakashi 0:8fdf9a60065b 532 dma_transfer_type_t type);
kadonotakashi 0:8fdf9a60065b 533
kadonotakashi 0:8fdf9a60065b 534 /*!
kadonotakashi 0:8fdf9a60065b 535 * @brief Submits the DMA transfer request.
kadonotakashi 0:8fdf9a60065b 536 *
kadonotakashi 0:8fdf9a60065b 537 * This function submits the DMA transfer request according to the transfer configuration structure.
kadonotakashi 0:8fdf9a60065b 538 *
kadonotakashi 0:8fdf9a60065b 539 * @param handle DMA handle pointer.
kadonotakashi 0:8fdf9a60065b 540 * @param config Pointer to DMA transfer configuration structure.
kadonotakashi 0:8fdf9a60065b 541 * @param options Additional configurations for transfer. Use
kadonotakashi 0:8fdf9a60065b 542 * the defined dma_transfer_options_t type.
kadonotakashi 0:8fdf9a60065b 543 * @retval kStatus_DMA_Success It indicates that the DMA submit transfer request succeeded.
kadonotakashi 0:8fdf9a60065b 544 * @retval kStatus_DMA_Busy It indicates that the DMA is busy. Submit transfer request is not allowed.
kadonotakashi 0:8fdf9a60065b 545 * @note This function can't process multi transfer request.
kadonotakashi 0:8fdf9a60065b 546 */
kadonotakashi 0:8fdf9a60065b 547 status_t DMA_SubmitTransfer(dma_handle_t *handle, const dma_transfer_config_t *config, uint32_t options);
kadonotakashi 0:8fdf9a60065b 548
kadonotakashi 0:8fdf9a60065b 549 /*!
kadonotakashi 0:8fdf9a60065b 550 * @brief DMA starts a transfer.
kadonotakashi 0:8fdf9a60065b 551 *
kadonotakashi 0:8fdf9a60065b 552 * This function enables the channel request. Call this function
kadonotakashi 0:8fdf9a60065b 553 * after submitting a transfer request.
kadonotakashi 0:8fdf9a60065b 554 *
kadonotakashi 0:8fdf9a60065b 555 * @param handle DMA handle pointer.
kadonotakashi 0:8fdf9a60065b 556 * @retval kStatus_DMA_Success It indicates that the DMA start transfer succeed.
kadonotakashi 0:8fdf9a60065b 557 * @retval kStatus_DMA_Busy It indicates that the DMA has started a transfer.
kadonotakashi 0:8fdf9a60065b 558 */
kadonotakashi 0:8fdf9a60065b 559 static inline void DMA_StartTransfer(dma_handle_t *handle)
kadonotakashi 0:8fdf9a60065b 560 {
kadonotakashi 0:8fdf9a60065b 561 assert(handle != NULL);
kadonotakashi 0:8fdf9a60065b 562
kadonotakashi 0:8fdf9a60065b 563 handle->base->DMA[handle->channel].DCR |= DMA_DCR_ERQ_MASK;
kadonotakashi 0:8fdf9a60065b 564 }
kadonotakashi 0:8fdf9a60065b 565
kadonotakashi 0:8fdf9a60065b 566 /*!
kadonotakashi 0:8fdf9a60065b 567 * @brief DMA stops a transfer.
kadonotakashi 0:8fdf9a60065b 568 *
kadonotakashi 0:8fdf9a60065b 569 * This function disables the channel request to stop a DMA transfer.
kadonotakashi 0:8fdf9a60065b 570 * The transfer can be resumed by calling the DMA_StartTransfer.
kadonotakashi 0:8fdf9a60065b 571 *
kadonotakashi 0:8fdf9a60065b 572 * @param handle DMA handle pointer.
kadonotakashi 0:8fdf9a60065b 573 */
kadonotakashi 0:8fdf9a60065b 574 static inline void DMA_StopTransfer(dma_handle_t *handle)
kadonotakashi 0:8fdf9a60065b 575 {
kadonotakashi 0:8fdf9a60065b 576 assert(handle != NULL);
kadonotakashi 0:8fdf9a60065b 577
kadonotakashi 0:8fdf9a60065b 578 handle->base->DMA[handle->channel].DCR &= ~DMA_DCR_ERQ_MASK;
kadonotakashi 0:8fdf9a60065b 579 }
kadonotakashi 0:8fdf9a60065b 580
kadonotakashi 0:8fdf9a60065b 581 /*!
kadonotakashi 0:8fdf9a60065b 582 * @brief DMA aborts a transfer.
kadonotakashi 0:8fdf9a60065b 583 *
kadonotakashi 0:8fdf9a60065b 584 * This function disables the channel request and clears all status bits.
kadonotakashi 0:8fdf9a60065b 585 * Submit another transfer after calling this API.
kadonotakashi 0:8fdf9a60065b 586 *
kadonotakashi 0:8fdf9a60065b 587 * @param handle DMA handle pointer.
kadonotakashi 0:8fdf9a60065b 588 */
kadonotakashi 0:8fdf9a60065b 589 void DMA_AbortTransfer(dma_handle_t *handle);
kadonotakashi 0:8fdf9a60065b 590
kadonotakashi 0:8fdf9a60065b 591 /*!
kadonotakashi 0:8fdf9a60065b 592 * @brief DMA IRQ handler for current transfer complete.
kadonotakashi 0:8fdf9a60065b 593 *
kadonotakashi 0:8fdf9a60065b 594 * This function clears the channel interrupt flag and calls
kadonotakashi 0:8fdf9a60065b 595 * the callback function if it is not NULL.
kadonotakashi 0:8fdf9a60065b 596 *
kadonotakashi 0:8fdf9a60065b 597 * @param handle DMA handle pointer.
kadonotakashi 0:8fdf9a60065b 598 */
kadonotakashi 0:8fdf9a60065b 599 void DMA_HandleIRQ(dma_handle_t *handle);
kadonotakashi 0:8fdf9a60065b 600
kadonotakashi 0:8fdf9a60065b 601 /* @} */
kadonotakashi 0:8fdf9a60065b 602
kadonotakashi 0:8fdf9a60065b 603 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 604 }
kadonotakashi 0:8fdf9a60065b 605 #endif /* __cplusplus */
kadonotakashi 0:8fdf9a60065b 606
kadonotakashi 0:8fdf9a60065b 607 /* @}*/
kadonotakashi 0:8fdf9a60065b 608
kadonotakashi 0:8fdf9a60065b 609 #endif /* _FSL_DMA_H_ */